1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2016 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
8 #include <linux/export.h>
10 #include <drm/drm_print.h>
12 #include "meson_drv.h"
13 #include "meson_vclk.h"
18 * VCLK is the "Pixel Clock" frequency generator from a dedicated PLL.
19 * We handle the following encodings :
21 * - CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks
22 * - HDMI Pixel Clocks generation
26 * - Genenate Pixel clocks for 2K/4K 10bit formats
28 * Clock generator scheme :
32 * __________ _________ _____
34 * | HDMI PLL |-| PLL_DIV |--- VCLK--| |--ENCL
35 * |__________| |_________| \ | MUX |--ENCP
39 * Final clocks can take input for either VCLK or VCLK2, but
40 * VCLK is the preferred path for HDMI clocking and VCLK2 is the
41 * preferred path for CVBS VDAC clocking.
43 * VCLK and VCLK2 have fixed divided clocks paths for /1, /2, /4, /6 or /12.
45 * The PLL_DIV can achieve an additional fractional dividing like
46 * 1.5, 3.5, 3.75... to generate special 2K and 4K 10bit clocks.
50 #define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */
51 #define VID_PLL_EN BIT(19)
52 #define VID_PLL_BYPASS BIT(18)
53 #define VID_PLL_PRESET BIT(15)
54 #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
55 #define VCLK2_DIV_MASK 0xff
56 #define VCLK2_DIV_EN BIT(16)
57 #define VCLK2_DIV_RESET BIT(17)
58 #define CTS_VDAC_SEL_MASK (0xf << 28)
59 #define CTS_VDAC_SEL_SHIFT 28
60 #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
61 #define VCLK2_EN BIT(19)
62 #define VCLK2_SEL_MASK (0x7 << 16)
63 #define VCLK2_SEL_SHIFT 16
64 #define VCLK2_SOFT_RESET BIT(15)
65 #define VCLK2_DIV1_EN BIT(0)
66 #define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */
67 #define VCLK_DIV_MASK 0xff
68 #define VCLK_DIV_EN BIT(16)
69 #define VCLK_DIV_RESET BIT(17)
70 #define CTS_ENCP_SEL_MASK (0xf << 24)
71 #define CTS_ENCP_SEL_SHIFT 24
72 #define CTS_ENCI_SEL_MASK (0xf << 28)
73 #define CTS_ENCI_SEL_SHIFT 28
74 #define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
75 #define VCLK_EN BIT(19)
76 #define VCLK_SEL_MASK (0x7 << 16)
77 #define VCLK_SEL_SHIFT 16
78 #define VCLK_SOFT_RESET BIT(15)
79 #define VCLK_DIV1_EN BIT(0)
80 #define VCLK_DIV2_EN BIT(1)
81 #define VCLK_DIV4_EN BIT(2)
82 #define VCLK_DIV6_EN BIT(3)
83 #define VCLK_DIV12_EN BIT(4)
84 #define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
85 #define CTS_ENCI_EN BIT(0)
86 #define CTS_ENCP_EN BIT(2)
87 #define CTS_VDAC_EN BIT(4)
88 #define HDMI_TX_PIXEL_EN BIT(5)
89 #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */
90 #define HDMI_TX_PIXEL_SEL_MASK (0xf << 16)
91 #define HDMI_TX_PIXEL_SEL_SHIFT 16
92 #define CTS_HDMI_SYS_SEL_MASK (0x7 << 9)
93 #define CTS_HDMI_SYS_DIV_MASK (0x7f)
94 #define CTS_HDMI_SYS_EN BIT(8)
96 #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
97 #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
99 #define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
100 #define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */
101 #define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */
102 #define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */
103 #define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */
104 #define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */
105 #define HHI_HDMI_PLL_CNTL7 0x338 /* 0xce offset in data sheet */
107 #define HDMI_PLL_RESET BIT(28)
108 #define HDMI_PLL_RESET_G12A BIT(29)
109 #define HDMI_PLL_LOCK BIT(31)
110 #define HDMI_PLL_LOCK_G12A (3 << 30)
112 #define FREQ_1000_1001(_freq) DIV_ROUND_CLOSEST(_freq * 1000, 1001)
114 /* VID PLL Dividers */
133 void meson_vid_pll_set(struct meson_drm *priv, unsigned int div)
135 unsigned int shift_val = 0;
136 unsigned int shift_sel = 0;
138 /* Disable vid_pll output clock */
139 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0);
140 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0);
147 case VID_PLL_DIV_2p5:
155 case VID_PLL_DIV_3p5:
159 case VID_PLL_DIV_3p75:
175 case VID_PLL_DIV_6p25:
183 case VID_PLL_DIV_7p5:
201 if (div == VID_PLL_DIV_1)
202 /* Enable vid_pll bypass to HDMI pll */
203 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
204 VID_PLL_BYPASS, VID_PLL_BYPASS);
207 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
210 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
212 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
214 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
217 /* Setup sel and val */
218 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
219 3 << 16, shift_sel << 16);
220 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
221 VID_PLL_PRESET, VID_PLL_PRESET);
222 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
225 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
229 /* Enable the vid_pll output clock */
230 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
231 VID_PLL_EN, VID_PLL_EN);
235 * Setup VCLK2 for 27MHz, and enable clocks for ENCI and VDAC
237 * TOFIX: Refactor into table to also handle HDMI frequency and paths
239 static void meson_venci_cvbs_clock_config(struct meson_drm *priv)
243 /* Setup PLL to output 1.485GHz */
244 if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
245 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800023d);
246 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00404e00);
247 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
248 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
249 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
250 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
251 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4800023d);
253 /* Poll for lock bit */
254 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
255 (val & HDMI_PLL_LOCK), 10, 0);
256 } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
257 meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
258 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4000027b);
259 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb300);
260 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0xa6212844);
261 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c4d000c);
262 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
263 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
266 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
267 HDMI_PLL_RESET, HDMI_PLL_RESET);
268 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
271 /* Poll for lock bit */
272 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
273 (val & HDMI_PLL_LOCK), 10, 0);
274 } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
275 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7);
276 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00010000);
277 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x00000000);
278 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x6a28dc00);
279 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x65771290);
280 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000);
281 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x56540000);
282 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x3a0504f7);
283 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7);
285 /* Poll for lock bit */
286 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
287 ((val & HDMI_PLL_LOCK_G12A) == HDMI_PLL_LOCK_G12A),
292 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
294 /* Setup vid_pll to /1 */
295 meson_vid_pll_set(priv, VID_PLL_DIV_1);
297 /* Setup the VCLK2 divider value to achieve 27MHz */
298 regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
299 VCLK2_DIV_MASK, (55 - 1));
301 /* select vid_pll for vclk2 */
302 if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
303 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
304 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
306 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
307 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT));
309 /* enable vclk2 gate */
310 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
312 /* select vclk_div1 for enci */
313 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
314 CTS_ENCI_SEL_MASK, (8 << CTS_ENCI_SEL_SHIFT));
315 /* select vclk_div1 for vdac */
316 regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
317 CTS_VDAC_SEL_MASK, (8 << CTS_VDAC_SEL_SHIFT));
319 /* release vclk2_div_reset and enable vclk2_div */
320 regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
321 VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
323 /* enable vclk2_div1 gate */
324 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
325 VCLK2_DIV1_EN, VCLK2_DIV1_EN);
328 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
329 VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
330 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
331 VCLK2_SOFT_RESET, 0);
333 /* enable enci_clk */
334 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
335 CTS_ENCI_EN, CTS_ENCI_EN);
336 /* enable vdac_clk */
337 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
338 CTS_VDAC_EN, CTS_VDAC_EN);
342 /* PLL O1 O2 O3 VP DV EN TX */
343 /* 4320 /4 /4 /1 /5 /1 => /2 /2 */
344 MESON_VCLK_HDMI_ENCI_54000 = 0,
345 /* 4320 /4 /4 /1 /5 /1 => /1 /2 */
346 MESON_VCLK_HDMI_DDR_54000,
347 /* 2970 /4 /1 /1 /5 /1 => /1 /2 */
348 MESON_VCLK_HDMI_DDR_148500,
349 /* 2970 /2 /2 /2 /5 /1 => /1 /1 */
350 MESON_VCLK_HDMI_74250,
351 /* 2970 /1 /2 /2 /5 /1 => /1 /1 */
352 MESON_VCLK_HDMI_148500,
353 /* 2970 /1 /1 /1 /5 /2 => /1 /1 */
354 MESON_VCLK_HDMI_297000,
355 /* 5940 /1 /1 /2 /5 /1 => /1 /1 */
356 MESON_VCLK_HDMI_594000
359 struct meson_vclk_params {
360 unsigned int pixel_freq;
361 unsigned int pll_base_freq;
362 unsigned int pll_od1;
363 unsigned int pll_od2;
364 unsigned int pll_od3;
365 unsigned int vid_pll_div;
366 unsigned int vclk_div;
368 [MESON_VCLK_HDMI_ENCI_54000] = {
370 .pll_base_freq = 4320000,
374 .vid_pll_div = VID_PLL_DIV_5,
377 [MESON_VCLK_HDMI_DDR_54000] = {
379 .pll_base_freq = 4320000,
383 .vid_pll_div = VID_PLL_DIV_5,
386 [MESON_VCLK_HDMI_DDR_148500] = {
387 .pixel_freq = 148500,
388 .pll_base_freq = 2970000,
392 .vid_pll_div = VID_PLL_DIV_5,
395 [MESON_VCLK_HDMI_74250] = {
397 .pll_base_freq = 2970000,
401 .vid_pll_div = VID_PLL_DIV_5,
404 [MESON_VCLK_HDMI_148500] = {
405 .pixel_freq = 148500,
406 .pll_base_freq = 2970000,
410 .vid_pll_div = VID_PLL_DIV_5,
413 [MESON_VCLK_HDMI_297000] = {
414 .pixel_freq = 297000,
415 .pll_base_freq = 5940000,
419 .vid_pll_div = VID_PLL_DIV_5,
422 [MESON_VCLK_HDMI_594000] = {
423 .pixel_freq = 594000,
424 .pll_base_freq = 5940000,
428 .vid_pll_div = VID_PLL_DIV_5,
434 static inline unsigned int pll_od_to_reg(unsigned int od)
451 void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m,
452 unsigned int frac, unsigned int od1,
453 unsigned int od2, unsigned int od3)
457 if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
458 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000200 | m);
460 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2,
463 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2,
465 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
466 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
467 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
468 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
470 /* Enable and unreset */
471 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
472 0x7 << 28, 0x4 << 28);
474 /* Poll for lock bit */
475 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
476 val, (val & HDMI_PLL_LOCK), 10, 0);
477 } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
478 meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
479 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000200 | m);
480 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac);
481 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
482 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
483 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
484 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
487 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
488 HDMI_PLL_RESET, HDMI_PLL_RESET);
489 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
492 /* Poll for lock bit */
493 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
494 (val & HDMI_PLL_LOCK), 10, 0);
495 } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
496 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x0b3a0400 | m);
498 /* Enable and reset */
499 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
500 0x3 << 28, 0x3 << 28);
502 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, frac);
503 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x00000000);
505 /* G12A HDMI PLL Needs specific parameters for 5.4GHz */
507 if (frac < 0x10000) {
508 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
510 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
513 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
515 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
518 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000);
519 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x55540000);
521 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0a691c00);
522 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x33771290);
523 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39270000);
524 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x50540000);
529 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
530 HDMI_PLL_RESET_G12A, HDMI_PLL_RESET_G12A);
533 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
534 HDMI_PLL_RESET_G12A, 0);
536 /* Poll for lock bits */
537 if (!regmap_read_poll_timeout(priv->hhi,
538 HHI_HDMI_PLL_CNTL, val,
539 ((val & HDMI_PLL_LOCK_G12A)
540 == HDMI_PLL_LOCK_G12A),
546 if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
547 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
548 3 << 16, pll_od_to_reg(od1) << 16);
549 else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
550 meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
551 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
552 3 << 21, pll_od_to_reg(od1) << 21);
553 else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
554 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
555 3 << 16, pll_od_to_reg(od1) << 16);
557 if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
558 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
559 3 << 22, pll_od_to_reg(od2) << 22);
560 else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
561 meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
562 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
563 3 << 23, pll_od_to_reg(od2) << 23);
564 else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
565 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
566 3 << 18, pll_od_to_reg(od2) << 18);
568 if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
569 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
570 3 << 18, pll_od_to_reg(od3) << 18);
571 else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
572 meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
573 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
574 3 << 19, pll_od_to_reg(od3) << 19);
575 else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
576 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
577 3 << 20, pll_od_to_reg(od3) << 20);
580 #define XTAL_FREQ 24000
582 static unsigned int meson_hdmi_pll_get_m(struct meson_drm *priv,
583 unsigned int pll_freq)
585 /* The GXBB PLL has a /2 pre-multiplier */
586 if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
589 return pll_freq / XTAL_FREQ;
592 #define HDMI_FRAC_MAX_GXBB 4096
593 #define HDMI_FRAC_MAX_GXL 1024
594 #define HDMI_FRAC_MAX_G12A 131072
596 static unsigned int meson_hdmi_pll_get_frac(struct meson_drm *priv,
598 unsigned int pll_freq)
600 unsigned int parent_freq = XTAL_FREQ;
601 unsigned int frac_max = HDMI_FRAC_MAX_GXL;
605 /* The GXBB PLL has a /2 pre-multiplier and a larger FRAC width */
606 if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
607 frac_max = HDMI_FRAC_MAX_GXBB;
611 if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
612 frac_max = HDMI_FRAC_MAX_G12A;
614 /* We can have a perfect match !*/
615 if (pll_freq / m == parent_freq &&
619 frac = div_u64((u64)pll_freq * (u64)frac_max, parent_freq);
620 frac_m = m * frac_max;
625 return min((u16)frac, (u16)(frac_max - 1));
628 static bool meson_hdmi_pll_validate_params(struct meson_drm *priv,
632 if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
633 /* Empiric supported min/max dividers */
634 if (m < 53 || m > 123)
636 if (frac >= HDMI_FRAC_MAX_GXBB)
638 } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
639 meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu") ||
640 meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
641 /* Empiric supported min/max dividers */
642 if (m < 106 || m > 247)
644 if (frac >= HDMI_FRAC_MAX_GXL)
651 static bool meson_hdmi_pll_find_params(struct meson_drm *priv,
657 /* Cycle from /16 to /2 */
658 for (*od = 16 ; *od > 1 ; *od >>= 1) {
659 *m = meson_hdmi_pll_get_m(priv, freq * *od);
662 *frac = meson_hdmi_pll_get_frac(priv, *m, freq * *od);
664 DRM_DEBUG_DRIVER("PLL params for %dkHz: m=%x frac=%x od=%d\n",
665 freq, *m, *frac, *od);
667 if (meson_hdmi_pll_validate_params(priv, *m, *frac))
674 /* pll_freq is the frequency after the OD dividers */
676 meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq)
678 unsigned int od, m, frac;
680 /* In DMT mode, path after PLL is always /10 */
683 if (meson_hdmi_pll_find_params(priv, freq, &m, &frac, &od))
686 return MODE_CLOCK_RANGE;
688 EXPORT_SYMBOL_GPL(meson_vclk_dmt_supported_freq);
690 /* pll_freq is the frequency after the OD dividers */
691 static void meson_hdmi_pll_generic_set(struct meson_drm *priv,
692 unsigned int pll_freq)
694 unsigned int od, m, frac, od1, od2, od3;
696 if (meson_hdmi_pll_find_params(priv, pll_freq, &m, &frac, &od)) {
706 DRM_DEBUG_DRIVER("PLL params for %dkHz: m=%x frac=%x od=%d/%d/%d\n",
707 pll_freq, m, frac, od1, od2, od3);
709 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
714 DRM_ERROR("Fatal, unable to find parameters for PLL freq %d\n",
719 meson_vclk_vic_supported_freq(unsigned int freq)
723 DRM_DEBUG_DRIVER("freq = %d\n", freq);
725 for (i = 0 ; params[i].pixel_freq ; ++i) {
726 DRM_DEBUG_DRIVER("i = %d pixel_freq = %d alt = %d\n",
727 i, params[i].pixel_freq,
728 FREQ_1000_1001(params[i].pixel_freq));
729 /* Match strict frequency */
730 if (freq == params[i].pixel_freq)
732 /* Match 1000/1001 variant */
733 if (freq == FREQ_1000_1001(params[i].pixel_freq))
737 return MODE_CLOCK_RANGE;
739 EXPORT_SYMBOL_GPL(meson_vclk_vic_supported_freq);
741 static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
742 unsigned int od1, unsigned int od2, unsigned int od3,
743 unsigned int vid_pll_div, unsigned int vclk_div,
744 unsigned int hdmi_tx_div, unsigned int venc_div,
745 bool hdmi_use_enci, bool vic_alternate_clock)
747 unsigned int m = 0, frac = 0;
749 /* Set HDMI-TX sys clock */
750 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
751 CTS_HDMI_SYS_SEL_MASK, 0);
752 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
753 CTS_HDMI_SYS_DIV_MASK, 0);
754 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
755 CTS_HDMI_SYS_EN, CTS_HDMI_SYS_EN);
757 /* Set HDMI PLL rate */
758 if (!od1 && !od2 && !od3) {
759 meson_hdmi_pll_generic_set(priv, pll_base_freq);
760 } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
761 switch (pll_base_freq) {
764 frac = vic_alternate_clock ? 0xd02 : 0xe00;
767 m = vic_alternate_clock ? 0x59 : 0x5a;
768 frac = vic_alternate_clock ? 0xe8f : 0;
772 frac = vic_alternate_clock ? 0xa05 : 0xc00;
776 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
777 } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
778 meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
779 switch (pll_base_freq) {
782 frac = vic_alternate_clock ? 0x281 : 0x300;
785 m = vic_alternate_clock ? 0xb3 : 0xb4;
786 frac = vic_alternate_clock ? 0x347 : 0;
790 frac = vic_alternate_clock ? 0x102 : 0x200;
794 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
795 } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
796 switch (pll_base_freq) {
799 frac = vic_alternate_clock ? 0x140b4 : 0x18000;
802 m = vic_alternate_clock ? 0xb3 : 0xb4;
803 frac = vic_alternate_clock ? 0x1a3ee : 0;
807 frac = vic_alternate_clock ? 0x8148 : 0x10000;
811 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
814 /* Setup vid_pll divider */
815 meson_vid_pll_set(priv, vid_pll_div);
818 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
820 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
821 VCLK_DIV_MASK, vclk_div - 1);
823 /* Set HDMI-TX source */
824 switch (hdmi_tx_div) {
826 /* enable vclk_div1 gate */
827 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
828 VCLK_DIV1_EN, VCLK_DIV1_EN);
830 /* select vclk_div1 for HDMI-TX */
831 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
832 HDMI_TX_PIXEL_SEL_MASK, 0);
835 /* enable vclk_div2 gate */
836 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
837 VCLK_DIV2_EN, VCLK_DIV2_EN);
839 /* select vclk_div2 for HDMI-TX */
840 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
841 HDMI_TX_PIXEL_SEL_MASK, 1 << HDMI_TX_PIXEL_SEL_SHIFT);
844 /* enable vclk_div4 gate */
845 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
846 VCLK_DIV4_EN, VCLK_DIV4_EN);
848 /* select vclk_div4 for HDMI-TX */
849 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
850 HDMI_TX_PIXEL_SEL_MASK, 2 << HDMI_TX_PIXEL_SEL_SHIFT);
853 /* enable vclk_div6 gate */
854 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
855 VCLK_DIV6_EN, VCLK_DIV6_EN);
857 /* select vclk_div6 for HDMI-TX */
858 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
859 HDMI_TX_PIXEL_SEL_MASK, 3 << HDMI_TX_PIXEL_SEL_SHIFT);
862 /* enable vclk_div12 gate */
863 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
864 VCLK_DIV12_EN, VCLK_DIV12_EN);
866 /* select vclk_div12 for HDMI-TX */
867 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
868 HDMI_TX_PIXEL_SEL_MASK, 4 << HDMI_TX_PIXEL_SEL_SHIFT);
871 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
872 HDMI_TX_PIXEL_EN, HDMI_TX_PIXEL_EN);
874 /* Set ENCI/ENCP Source */
877 /* enable vclk_div1 gate */
878 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
879 VCLK_DIV1_EN, VCLK_DIV1_EN);
882 /* select vclk_div1 for enci */
883 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
884 CTS_ENCI_SEL_MASK, 0);
886 /* select vclk_div1 for encp */
887 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
888 CTS_ENCP_SEL_MASK, 0);
891 /* enable vclk_div2 gate */
892 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
893 VCLK_DIV2_EN, VCLK_DIV2_EN);
896 /* select vclk_div2 for enci */
897 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
898 CTS_ENCI_SEL_MASK, 1 << CTS_ENCI_SEL_SHIFT);
900 /* select vclk_div2 for encp */
901 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
902 CTS_ENCP_SEL_MASK, 1 << CTS_ENCP_SEL_SHIFT);
905 /* enable vclk_div4 gate */
906 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
907 VCLK_DIV4_EN, VCLK_DIV4_EN);
910 /* select vclk_div4 for enci */
911 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
912 CTS_ENCI_SEL_MASK, 2 << CTS_ENCI_SEL_SHIFT);
914 /* select vclk_div4 for encp */
915 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
916 CTS_ENCP_SEL_MASK, 2 << CTS_ENCP_SEL_SHIFT);
919 /* enable vclk_div6 gate */
920 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
921 VCLK_DIV6_EN, VCLK_DIV6_EN);
924 /* select vclk_div6 for enci */
925 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
926 CTS_ENCI_SEL_MASK, 3 << CTS_ENCI_SEL_SHIFT);
928 /* select vclk_div6 for encp */
929 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
930 CTS_ENCP_SEL_MASK, 3 << CTS_ENCP_SEL_SHIFT);
933 /* enable vclk_div12 gate */
934 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
935 VCLK_DIV12_EN, VCLK_DIV12_EN);
938 /* select vclk_div12 for enci */
939 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
940 CTS_ENCI_SEL_MASK, 4 << CTS_ENCI_SEL_SHIFT);
942 /* select vclk_div12 for encp */
943 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
944 CTS_ENCP_SEL_MASK, 4 << CTS_ENCP_SEL_SHIFT);
949 /* Enable ENCI clock gate */
950 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
951 CTS_ENCI_EN, CTS_ENCI_EN);
953 /* Enable ENCP clock gate */
954 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
955 CTS_ENCP_EN, CTS_ENCP_EN);
957 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN);
960 void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
961 unsigned int vclk_freq, unsigned int venc_freq,
962 unsigned int dac_freq, bool hdmi_use_enci)
964 bool vic_alternate_clock = false;
966 unsigned int hdmi_tx_div;
967 unsigned int venc_div;
969 if (target == MESON_VCLK_TARGET_CVBS) {
970 meson_venci_cvbs_clock_config(priv);
972 } else if (target == MESON_VCLK_TARGET_DMT) {
973 /* The DMT clock path is fixed after the PLL:
974 * - automatic PLL freq + OD management
975 * - vid_pll_div = VID_PLL_DIV_5
981 meson_vclk_set(priv, vclk_freq * 10, 0, 0, 0,
982 VID_PLL_DIV_5, 2, 1, 1, false, false);
986 hdmi_tx_div = vclk_freq / dac_freq;
988 if (hdmi_tx_div == 0) {
989 pr_err("Fatal Error, invalid HDMI-TX freq %d\n",
994 venc_div = vclk_freq / venc_freq;
997 pr_err("Fatal Error, invalid HDMI venc freq %d\n",
1002 for (freq = 0 ; params[freq].pixel_freq ; ++freq) {
1003 if (vclk_freq == params[freq].pixel_freq ||
1004 vclk_freq == FREQ_1000_1001(params[freq].pixel_freq)) {
1005 if (vclk_freq != params[freq].pixel_freq)
1006 vic_alternate_clock = true;
1008 vic_alternate_clock = false;
1010 if (freq == MESON_VCLK_HDMI_ENCI_54000 &&
1014 if (freq == MESON_VCLK_HDMI_DDR_54000 &&
1018 if (freq == MESON_VCLK_HDMI_DDR_148500 &&
1019 dac_freq == vclk_freq)
1022 if (freq == MESON_VCLK_HDMI_148500 &&
1023 dac_freq != vclk_freq)
1029 if (!params[freq].pixel_freq) {
1030 pr_err("Fatal Error, invalid HDMI vclk freq %d\n", vclk_freq);
1034 meson_vclk_set(priv, params[freq].pll_base_freq,
1035 params[freq].pll_od1, params[freq].pll_od2,
1036 params[freq].pll_od3, params[freq].vid_pll_div,
1037 params[freq].vclk_div, hdmi_tx_div, venc_div,
1038 hdmi_use_enci, vic_alternate_clock);
1040 EXPORT_SYMBOL_GPL(meson_vclk_setup);