drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include "i915_drv.h"
  31 #include "intel_drv.h"
  32 #include "../../../platform/x86/intel_ips.h"
  33 #include <linux/module.h>
  34 #include <drm/drm_atomic_helper.h>
  35
  36 /**
  37  * DOC: RC6
  38  *
  39  * RC6 is a special power stage which allows the GPU to enter an very
  40  * low-voltage mode when idle, using down to 0V while at this stage.  This
  41  * stage is entered automatically when the GPU is idle when RC6 support is
  42  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  43  *
  44  * There are different RC6 modes available in Intel GPU, which differentiate
  45  * among each other with the latency required to enter and leave RC6 and
  46  * voltage consumed by the GPU in different states.
  47  *
  48  * The combination of the following flags define which states GPU is allowed
  49  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  50  * RC6pp is deepest RC6. Their support by hardware varies according to the
  51  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  52  * which brings the most power savings; deeper states save more power, but
  53  * require higher latency to switch to and wake up.
  54  */
  55 #define INTEL_RC6_ENABLE                        (1<<0)
  56 #define INTEL_RC6p_ENABLE                       (1<<1)
  57 #define INTEL_RC6pp_ENABLE                      (1<<2)
  58
  59 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
  60 {
  61         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
  62         I915_WRITE(CHICKEN_PAR1_1,
  63                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  64
  65         /*
  66          * Display WA#0390: skl,bxt,kbl,glk
  67          *
  68          * Must match Sampler, Pixel Back End, and Media
  69          * (0xE194 bit 8, 0x7014 bit 13, 0x4DDC bits 27 and 31).
  70          *
  71          * Including bits outside the page in the hash would
  72          * require 2 (or 4?) MiB alignment of resources. Just
  73          * assume the defaul hashing mode which only uses bits
  74          * within the page.
  75          */
  76         I915_WRITE(CHICKEN_PAR1_1,
  77                    I915_READ(CHICKEN_PAR1_1) & ~SKL_RC_HASH_OUTSIDE);
  78
  79         I915_WRITE(GEN8_CONFIG0,
  80                    I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
  81
  82         /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
  83         I915_WRITE(GEN8_CHICKEN_DCPR_1,
  84                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  85
  86         /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
  87         /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
  88         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
  89                    DISP_FBC_WM_DIS |
  90                    DISP_FBC_MEMORY_WAKE);
  91
  92         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
  93         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
  94                    ILK_DPFC_DISABLE_DUMMY0);
  95
  96         if (IS_SKYLAKE(dev_priv)) {
  97                 /* WaDisableDopClockGating */
  98                 I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
  99                            & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 100         }
 101 }
 102
 103 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
 104 {
 105         gen9_init_clock_gating(dev_priv);
 106
 107         /* WaDisableSDEUnitClockGating:bxt */
 108         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 109                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 110
 111         /*
 112          * FIXME:
 113          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
 114          */
 115         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 116                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 117
 118         /*
 119          * Wa: Backlight PWM may stop in the asserted state, causing backlight
 120          * to stay fully on.
 121          */
 122         I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 123                    PWM1_GATING_DIS | PWM2_GATING_DIS);
 124 }
 125
 126 static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
 127 {
 128         gen9_init_clock_gating(dev_priv);
 129
 130         /*
 131          * WaDisablePWMClockGating:glk
 132          * Backlight PWM may stop in the asserted state, causing backlight
 133          * to stay fully on.
 134          */
 135         I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 136                    PWM1_GATING_DIS | PWM2_GATING_DIS);
 137
 138         /* WaDDIIOTimeout:glk */
 139         if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) {
 140                 u32 val = I915_READ(CHICKEN_MISC_2);
 141                 val &= ~(GLK_CL0_PWR_DOWN |
 142                          GLK_CL1_PWR_DOWN |
 143                          GLK_CL2_PWR_DOWN);
 144                 I915_WRITE(CHICKEN_MISC_2, val);
 145         }
 146
 147 }
 148
 149 static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
 150 {
 151         u32 tmp;
 152
 153         tmp = I915_READ(CLKCFG);
 154
 155         switch (tmp & CLKCFG_FSB_MASK) {
 156         case CLKCFG_FSB_533:
 157                 dev_priv->fsb_freq = 533; /* 133*4 */
 158                 break;
 159         case CLKCFG_FSB_800:
 160                 dev_priv->fsb_freq = 800; /* 200*4 */
 161                 break;
 162         case CLKCFG_FSB_667:
 163                 dev_priv->fsb_freq =  667; /* 167*4 */
 164                 break;
 165         case CLKCFG_FSB_400:
 166                 dev_priv->fsb_freq = 400; /* 100*4 */
 167                 break;
 168         }
 169
 170         switch (tmp & CLKCFG_MEM_MASK) {
 171         case CLKCFG_MEM_533:
 172                 dev_priv->mem_freq = 533;
 173                 break;
 174         case CLKCFG_MEM_667:
 175                 dev_priv->mem_freq = 667;
 176                 break;
 177         case CLKCFG_MEM_800:
 178                 dev_priv->mem_freq = 800;
 179                 break;
 180         }
 181
 182         /* detect pineview DDR3 setting */
 183         tmp = I915_READ(CSHRDDR3CTL);
 184         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 185 }
 186
 187 static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
 188 {
 189         u16 ddrpll, csipll;
 190
 191         ddrpll = I915_READ16(DDRMPLL1);
 192         csipll = I915_READ16(CSIPLL0);
 193
 194         switch (ddrpll & 0xff) {
 195         case 0xc:
 196                 dev_priv->mem_freq = 800;
 197                 break;
 198         case 0x10:
 199                 dev_priv->mem_freq = 1066;
 200                 break;
 201         case 0x14:
 202                 dev_priv->mem_freq = 1333;
 203                 break;
 204         case 0x18:
 205                 dev_priv->mem_freq = 1600;
 206                 break;
 207         default:
 208                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 209                                  ddrpll & 0xff);
 210                 dev_priv->mem_freq = 0;
 211                 break;
 212         }
 213
 214         dev_priv->ips.r_t = dev_priv->mem_freq;
 215
 216         switch (csipll & 0x3ff) {
 217         case 0x00c:
 218                 dev_priv->fsb_freq = 3200;
 219                 break;
 220         case 0x00e:
 221                 dev_priv->fsb_freq = 3733;
 222                 break;
 223         case 0x010:
 224                 dev_priv->fsb_freq = 4266;
 225                 break;
 226         case 0x012:
 227                 dev_priv->fsb_freq = 4800;
 228                 break;
 229         case 0x014:
 230                 dev_priv->fsb_freq = 5333;
 231                 break;
 232         case 0x016:
 233                 dev_priv->fsb_freq = 5866;
 234                 break;
 235         case 0x018:
 236                 dev_priv->fsb_freq = 6400;
 237                 break;
 238         default:
 239                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 240                                  csipll & 0x3ff);
 241                 dev_priv->fsb_freq = 0;
 242                 break;
 243         }
 244
 245         if (dev_priv->fsb_freq == 3200) {
 246                 dev_priv->ips.c_m = 0;
 247         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 248                 dev_priv->ips.c_m = 1;
 249         } else {
 250                 dev_priv->ips.c_m = 2;
 251         }
 252 }
 253
 254 static const struct cxsr_latency cxsr_latency_table[] = {
 255         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 256         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 257         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 258         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 259         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 260
 261         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 262         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 263         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 264         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 265         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 266
 267         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 268         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 269         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 270         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 271         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 272
 273         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 274         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 275         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 276         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 277         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 278
 279         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 280         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 281         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 282         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 283         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 284
 285         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 286         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 287         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 288         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 289         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 290 };
 291
 292 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
 293                                                          bool is_ddr3,
 294                                                          int fsb,
 295                                                          int mem)
 296 {
 297         const struct cxsr_latency *latency;
 298         int i;
 299
 300         if (fsb == 0 || mem == 0)
 301                 return NULL;
 302
 303         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 304                 latency = &cxsr_latency_table[i];
 305                 if (is_desktop == latency->is_desktop &&
 306                     is_ddr3 == latency->is_ddr3 &&
 307                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 308                         return latency;
 309         }
 310
 311         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 312
 313         return NULL;
 314 }
 315
 316 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 317 {
 318         u32 val;
 319
 320         mutex_lock(&dev_priv->rps.hw_lock);
 321
 322         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 323         if (enable)
 324                 val &= ~FORCE_DDR_HIGH_FREQ;
 325         else
 326                 val |= FORCE_DDR_HIGH_FREQ;
 327         val &= ~FORCE_DDR_LOW_FREQ;
 328         val |= FORCE_DDR_FREQ_REQ_ACK;
 329         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 330
 331         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 332                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 333                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 334
 335         mutex_unlock(&dev_priv->rps.hw_lock);
 336 }
 337
 338 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 339 {
 340         u32 val;
 341
 342         mutex_lock(&dev_priv->rps.hw_lock);
 343
 344         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 345         if (enable)
 346                 val |= DSP_MAXFIFO_PM5_ENABLE;
 347         else
 348                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 349         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 350
 351         mutex_unlock(&dev_priv->rps.hw_lock);
 352 }
 353
 354 #define FW_WM(value, plane) \
 355         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 356
 357 static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 358 {
 359         bool was_enabled;
 360         u32 val;
 361
 362         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 363                 was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 364                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 365                 POSTING_READ(FW_BLC_SELF_VLV);
 366         } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
 367                 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
 368                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 369                 POSTING_READ(FW_BLC_SELF);
 370         } else if (IS_PINEVIEW(dev_priv)) {
 371                 val = I915_READ(DSPFW3);
 372                 was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
 373                 if (enable)
 374                         val |= PINEVIEW_SELF_REFRESH_EN;
 375                 else
 376                         val &= ~PINEVIEW_SELF_REFRESH_EN;
 377                 I915_WRITE(DSPFW3, val);
 378                 POSTING_READ(DSPFW3);
 379         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
 380                 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
 381                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 382                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 383                 I915_WRITE(FW_BLC_SELF, val);
 384                 POSTING_READ(FW_BLC_SELF);
 385         } else if (IS_I915GM(dev_priv)) {
 386                 /*
 387                  * FIXME can't find a bit like this for 915G, and
 388                  * and yet it does have the related watermark in
 389                  * FW_BLC_SELF. What's going on?
 390                  */
 391                 was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
 392                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 393                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 394                 I915_WRITE(INSTPM, val);
 395                 POSTING_READ(INSTPM);
 396         } else {
 397                 return false;
 398         }
 399
 400         trace_intel_memory_cxsr(dev_priv, was_enabled, enable);
 401
 402         DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n",
 403                       enableddisabled(enable),
 404                       enableddisabled(was_enabled));
 405
 406         return was_enabled;
 407 }
 408
 409 /**
 410  * intel_set_memory_cxsr - Configure CxSR state
 411  * @dev_priv: i915 device
 412  * @enable: Allow vs. disallow CxSR
 413  *
 414  * Allow or disallow the system to enter a special CxSR
 415  * (C-state self refresh) state. What typically happens in CxSR mode
 416  * is that several display FIFOs may get combined into a single larger
 417  * FIFO for a particular plane (so called max FIFO mode) to allow the
 418  * system to defer memory fetches longer, and the memory will enter
 419  * self refresh.
 420  *
 421  * Note that enabling CxSR does not guarantee that the system enter
 422  * this special mode, nor does it guarantee that the system stays
 423  * in that mode once entered. So this just allows/disallows the system
 424  * to autonomously utilize the CxSR mode. Other factors such as core
 425  * C-states will affect when/if the system actually enters/exits the
 426  * CxSR mode.
 427  *
 428  * Note that on VLV/CHV this actually only controls the max FIFO mode,
 429  * and the system is free to enter/exit memory self refresh at any time
 430  * even when the use of CxSR has been disallowed.
 431  *
 432  * While the system is actually in the CxSR/max FIFO mode, some plane
 433  * control registers will not get latched on vblank. Thus in order to
 434  * guarantee the system will respond to changes in the plane registers
 435  * we must always disallow CxSR prior to making changes to those registers.
 436  * Unfortunately the system will re-evaluate the CxSR conditions at
 437  * frame start which happens after vblank start (which is when the plane
 438  * registers would get latched), so we can't proceed with the plane update
 439  * during the same frame where we disallowed CxSR.
 440  *
 441  * Certain platforms also have a deeper HPLL SR mode. Fortunately the
 442  * HPLL SR mode depends on CxSR itself, so we don't have to hand hold
 443  * the hardware w.r.t. HPLL SR when writing to plane registers.
 444  * Disallowing just CxSR is sufficient.
 445  */
 446 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 447 {
 448         bool ret;
 449
 450         mutex_lock(&dev_priv->wm.wm_mutex);
 451         ret = _intel_set_memory_cxsr(dev_priv, enable);
 452         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 453                 dev_priv->wm.vlv.cxsr = enable;
 454         else if (IS_G4X(dev_priv))
 455                 dev_priv->wm.g4x.cxsr = enable;
 456         mutex_unlock(&dev_priv->wm.wm_mutex);
 457
 458         return ret;
 459 }
 460
 461 /*
 462  * Latency for FIFO fetches is dependent on several factors:
 463  *   - memory configuration (speed, channels)
 464  *   - chipset
 465  *   - current MCH state
 466  * It can be fairly high in some situations, so here we assume a fairly
 467  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 468  * set this value too high, the FIFO will fetch frequently to stay full)
 469  * and power consumption (set it too low to save power and we might see
 470  * FIFO underruns and display "flicker").
 471  *
 472  * A value of 5us seems to be a good balance; safe for very low end
 473  * platforms but not overly aggressive on lower latency configs.
 474  */
 475 static const int pessimal_latency_ns = 5000;
 476
 477 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 478         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 479
 480 static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
 481 {
 482         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 483         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 484         struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
 485         enum pipe pipe = crtc->pipe;
 486         int sprite0_start, sprite1_start;
 487
 488         switch (pipe) {
 489                 uint32_t dsparb, dsparb2, dsparb3;
 490         case PIPE_A:
 491                 dsparb = I915_READ(DSPARB);
 492                 dsparb2 = I915_READ(DSPARB2);
 493                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 494                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 495                 break;
 496         case PIPE_B:
 497                 dsparb = I915_READ(DSPARB);
 498                 dsparb2 = I915_READ(DSPARB2);
 499                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 500                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 501                 break;
 502         case PIPE_C:
 503                 dsparb2 = I915_READ(DSPARB2);
 504                 dsparb3 = I915_READ(DSPARB3);
 505                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 506                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 507                 break;
 508         default:
 509                 MISSING_CASE(pipe);
 510                 return;
 511         }
 512
 513         fifo_state->plane[PLANE_PRIMARY] = sprite0_start;
 514         fifo_state->plane[PLANE_SPRITE0] = sprite1_start - sprite0_start;
 515         fifo_state->plane[PLANE_SPRITE1] = 511 - sprite1_start;
 516         fifo_state->plane[PLANE_CURSOR] = 63;
 517 }
 518
 519 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 520 {
 521         uint32_t dsparb = I915_READ(DSPARB);
 522         int size;
 523
 524         size = dsparb & 0x7f;
 525         if (plane)
 526                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 527
 528         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 529                       plane ? "B" : "A", size);
 530
 531         return size;
 532 }
 533
 534 static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 535 {
 536         uint32_t dsparb = I915_READ(DSPARB);
 537         int size;
 538
 539         size = dsparb & 0x1ff;
 540         if (plane)
 541                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 542         size >>= 1; /* Convert to cachelines */
 543
 544         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 545                       plane ? "B" : "A", size);
 546
 547         return size;
 548 }
 549
 550 static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 551 {
 552         uint32_t dsparb = I915_READ(DSPARB);
 553         int size;
 554
 555         size = dsparb & 0x7f;
 556         size >>= 2; /* Convert to cachelines */
 557
 558         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 559                       plane ? "B" : "A",
 560                       size);
 561
 562         return size;
 563 }
 564
 565 /* Pineview has different values for various configs */
 566 static const struct intel_watermark_params pineview_display_wm = {
 567         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 568         .max_wm = PINEVIEW_MAX_WM,
 569         .default_wm = PINEVIEW_DFT_WM,
 570         .guard_size = PINEVIEW_GUARD_WM,
 571         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 572 };
 573 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 574         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 575         .max_wm = PINEVIEW_MAX_WM,
 576         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 577         .guard_size = PINEVIEW_GUARD_WM,
 578         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 579 };
 580 static const struct intel_watermark_params pineview_cursor_wm = {
 581         .fifo_size = PINEVIEW_CURSOR_FIFO,
 582         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 583         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 584         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 585         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 586 };
 587 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 588         .fifo_size = PINEVIEW_CURSOR_FIFO,
 589         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 590         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 591         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 592         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 593 };
 594 static const struct intel_watermark_params i965_cursor_wm_info = {
 595         .fifo_size = I965_CURSOR_FIFO,
 596         .max_wm = I965_CURSOR_MAX_WM,
 597         .default_wm = I965_CURSOR_DFT_WM,
 598         .guard_size = 2,
 599         .cacheline_size = I915_FIFO_LINE_SIZE,
 600 };
 601 static const struct intel_watermark_params i945_wm_info = {
 602         .fifo_size = I945_FIFO_SIZE,
 603         .max_wm = I915_MAX_WM,
 604         .default_wm = 1,
 605         .guard_size = 2,
 606         .cacheline_size = I915_FIFO_LINE_SIZE,
 607 };
 608 static const struct intel_watermark_params i915_wm_info = {
 609         .fifo_size = I915_FIFO_SIZE,
 610         .max_wm = I915_MAX_WM,
 611         .default_wm = 1,
 612         .guard_size = 2,
 613         .cacheline_size = I915_FIFO_LINE_SIZE,
 614 };
 615 static const struct intel_watermark_params i830_a_wm_info = {
 616         .fifo_size = I855GM_FIFO_SIZE,
 617         .max_wm = I915_MAX_WM,
 618         .default_wm = 1,
 619         .guard_size = 2,
 620         .cacheline_size = I830_FIFO_LINE_SIZE,
 621 };
 622 static const struct intel_watermark_params i830_bc_wm_info = {
 623         .fifo_size = I855GM_FIFO_SIZE,
 624         .max_wm = I915_MAX_WM/2,
 625         .default_wm = 1,
 626         .guard_size = 2,
 627         .cacheline_size = I830_FIFO_LINE_SIZE,
 628 };
 629 static const struct intel_watermark_params i845_wm_info = {
 630         .fifo_size = I830_FIFO_SIZE,
 631         .max_wm = I915_MAX_WM,
 632         .default_wm = 1,
 633         .guard_size = 2,
 634         .cacheline_size = I830_FIFO_LINE_SIZE,
 635 };
 636
 637 /**
 638  * intel_wm_method1 - Method 1 / "small buffer" watermark formula
 639  * @pixel_rate: Pipe pixel rate in kHz
 640  * @cpp: Plane bytes per pixel
 641  * @latency: Memory wakeup latency in 0.1us units
 642  *
 643  * Compute the watermark using the method 1 or "small buffer"
 644  * formula. The caller may additonally add extra cachelines
 645  * to account for TLB misses and clock crossings.
 646  *
 647  * This method is concerned with the short term drain rate
 648  * of the FIFO, ie. it does not account for blanking periods
 649  * which would effectively reduce the average drain rate across
 650  * a longer period. The name "small" refers to the fact the
 651  * FIFO is relatively small compared to the amount of data
 652  * fetched.
 653  *
 654  * The FIFO level vs. time graph might look something like:
 655  *
 656  *   |\   |\
 657  *   | \  | \
 658  * __---__---__ (- plane active, _ blanking)
 659  * -> time
 660  *
 661  * or perhaps like this:
 662  *
 663  *   |\|\  |\|\
 664  * __----__----__ (- plane active, _ blanking)
 665  * -> time
 666  *
 667  * Returns:
 668  * The watermark in bytes
 669  */
 670 static unsigned int intel_wm_method1(unsigned int pixel_rate,
 671                                      unsigned int cpp,
 672                                      unsigned int latency)
 673 {
 674         uint64_t ret;
 675
 676         ret = (uint64_t) pixel_rate * cpp * latency;
 677         ret = DIV_ROUND_UP_ULL(ret, 10000);
 678
 679         return ret;
 680 }
 681
 682 /**
 683  * intel_wm_method2 - Method 2 / "large buffer" watermark formula
 684  * @pixel_rate: Pipe pixel rate in kHz
 685  * @htotal: Pipe horizontal total
 686  * @width: Plane width in pixels
 687  * @cpp: Plane bytes per pixel
 688  * @latency: Memory wakeup latency in 0.1us units
 689  *
 690  * Compute the watermark using the method 2 or "large buffer"
 691  * formula. The caller may additonally add extra cachelines
 692  * to account for TLB misses and clock crossings.
 693  *
 694  * This method is concerned with the long term drain rate
 695  * of the FIFO, ie. it does account for blanking periods
 696  * which effectively reduce the average drain rate across
 697  * a longer period. The name "large" refers to the fact the
 698  * FIFO is relatively large compared to the amount of data
 699  * fetched.
 700  *
 701  * The FIFO level vs. time graph might look something like:
 702  *
 703  *    |\___       |\___
 704  *    |    \___   |    \___
 705  *    |        \  |        \
 706  * __ --__--__--__--__--__--__ (- plane active, _ blanking)
 707  * -> time
 708  *
 709  * Returns:
 710  * The watermark in bytes
 711  */
 712 static unsigned int intel_wm_method2(unsigned int pixel_rate,
 713                                      unsigned int htotal,
 714                                      unsigned int width,
 715                                      unsigned int cpp,
 716                                      unsigned int latency)
 717 {
 718         unsigned int ret;
 719
 720         /*
 721          * FIXME remove once all users are computing
 722          * watermarks in the correct place.
 723          */
 724         if (WARN_ON_ONCE(htotal == 0))
 725                 htotal = 1;
 726
 727         ret = (latency * pixel_rate) / (htotal * 10000);
 728         ret = (ret + 1) * width * cpp;
 729
 730         return ret;
 731 }
 732
 733 /**
 734  * intel_calculate_wm - calculate watermark level
 735  * @pixel_rate: pixel clock
 736  * @wm: chip FIFO params
 737  * @cpp: bytes per pixel
 738  * @latency_ns: memory latency for the platform
 739  *
 740  * Calculate the watermark level (the level at which the display plane will
 741  * start fetching from memory again).  Each chip has a different display
 742  * FIFO size and allocation, so the caller needs to figure that out and pass
 743  * in the correct intel_watermark_params structure.
 744  *
 745  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 746  * on the pixel size.  When it reaches the watermark level, it'll start
 747  * fetching FIFO line sized based chunks from memory until the FIFO fills
 748  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 749  * will occur, and a display engine hang could result.
 750  */
 751 static unsigned int intel_calculate_wm(int pixel_rate,
 752                                        const struct intel_watermark_params *wm,
 753                                        int fifo_size, int cpp,
 754                                        unsigned int latency_ns)
 755 {
 756         int entries, wm_size;
 757
 758         /*
 759          * Note: we need to make sure we don't overflow for various clock &
 760          * latency values.
 761          * clocks go from a few thousand to several hundred thousand.
 762          * latency is usually a few thousand
 763          */
 764         entries = intel_wm_method1(pixel_rate, cpp,
 765                                    latency_ns / 100);
 766         entries = DIV_ROUND_UP(entries, wm->cacheline_size) +
 767                 wm->guard_size;
 768         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries);
 769
 770         wm_size = fifo_size - entries;
 771         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
 772
 773         /* Don't promote wm_size to unsigned... */
 774         if (wm_size > wm->max_wm)
 775                 wm_size = wm->max_wm;
 776         if (wm_size <= 0)
 777                 wm_size = wm->default_wm;
 778
 779         /*
 780          * Bspec seems to indicate that the value shouldn't be lower than
 781          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 782          * Lets go for 8 which is the burst size since certain platforms
 783          * already use a hardcoded 8 (which is what the spec says should be
 784          * done).
 785          */
 786         if (wm_size <= 8)
 787                 wm_size = 8;
 788
 789         return wm_size;
 790 }
 791
 792 static bool is_disabling(int old, int new, int threshold)
 793 {
 794         return old >= threshold && new < threshold;
 795 }
 796
 797 static bool is_enabling(int old, int new, int threshold)
 798 {
 799         return old < threshold && new >= threshold;
 800 }
 801
 802 static int intel_wm_num_levels(struct drm_i915_private *dev_priv)
 803 {
 804         return dev_priv->wm.max_level + 1;
 805 }
 806
 807 static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
 808                                    const struct intel_plane_state *plane_state)
 809 {
 810         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 811
 812         /* FIXME check the 'enable' instead */
 813         if (!crtc_state->base.active)
 814                 return false;
 815
 816         /*
 817          * Treat cursor with fb as always visible since cursor updates
 818          * can happen faster than the vrefresh rate, and the current
 819          * watermark code doesn't handle that correctly. Cursor updates
 820          * which set/clear the fb or change the cursor size are going
 821          * to get throttled by intel_legacy_cursor_update() to work
 822          * around this problem with the watermark code.
 823          */
 824         if (plane->id == PLANE_CURSOR)
 825                 return plane_state->base.fb != NULL;
 826         else
 827                 return plane_state->base.visible;
 828 }
 829
 830 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
 831 {
 832         struct intel_crtc *crtc, *enabled = NULL;
 833
 834         for_each_intel_crtc(&dev_priv->drm, crtc) {
 835                 if (intel_crtc_active(crtc)) {
 836                         if (enabled)
 837                                 return NULL;
 838                         enabled = crtc;
 839                 }
 840         }
 841
 842         return enabled;
 843 }
 844
 845 static void pineview_update_wm(struct intel_crtc *unused_crtc)
 846 {
 847         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
 848         struct intel_crtc *crtc;
 849         const struct cxsr_latency *latency;
 850         u32 reg;
 851         unsigned int wm;
 852
 853         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
 854                                          dev_priv->is_ddr3,
 855                                          dev_priv->fsb_freq,
 856                                          dev_priv->mem_freq);
 857         if (!latency) {
 858                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 859                 intel_set_memory_cxsr(dev_priv, false);
 860                 return;
 861         }
 862
 863         crtc = single_enabled_crtc(dev_priv);
 864         if (crtc) {
 865                 const struct drm_display_mode *adjusted_mode =
 866                         &crtc->config->base.adjusted_mode;
 867                 const struct drm_framebuffer *fb =
 868                         crtc->base.primary->state->fb;
 869                 int cpp = fb->format->cpp[0];
 870                 int clock = adjusted_mode->crtc_clock;
 871
 872                 /* Display SR */
 873                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 874                                         pineview_display_wm.fifo_size,
 875                                         cpp, latency->display_sr);
 876                 reg = I915_READ(DSPFW1);
 877                 reg &= ~DSPFW_SR_MASK;
 878                 reg |= FW_WM(wm, SR);
 879                 I915_WRITE(DSPFW1, reg);
 880                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 881
 882                 /* cursor SR */
 883                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 884                                         pineview_display_wm.fifo_size,
 885                                         4, latency->cursor_sr);
 886                 reg = I915_READ(DSPFW3);
 887                 reg &= ~DSPFW_CURSOR_SR_MASK;
 888                 reg |= FW_WM(wm, CURSOR_SR);
 889                 I915_WRITE(DSPFW3, reg);
 890
 891                 /* Display HPLL off SR */
 892                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 893                                         pineview_display_hplloff_wm.fifo_size,
 894                                         cpp, latency->display_hpll_disable);
 895                 reg = I915_READ(DSPFW3);
 896                 reg &= ~DSPFW_HPLL_SR_MASK;
 897                 reg |= FW_WM(wm, HPLL_SR);
 898                 I915_WRITE(DSPFW3, reg);
 899
 900                 /* cursor HPLL off SR */
 901                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 902                                         pineview_display_hplloff_wm.fifo_size,
 903                                         4, latency->cursor_hpll_disable);
 904                 reg = I915_READ(DSPFW3);
 905                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 906                 reg |= FW_WM(wm, HPLL_CURSOR);
 907                 I915_WRITE(DSPFW3, reg);
 908                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 909
 910                 intel_set_memory_cxsr(dev_priv, true);
 911         } else {
 912                 intel_set_memory_cxsr(dev_priv, false);
 913         }
 914 }
 915
 916 /*
 917  * Documentation says:
 918  * "If the line size is small, the TLB fetches can get in the way of the
 919  *  data fetches, causing some lag in the pixel data return which is not
 920  *  accounted for in the above formulas. The following adjustment only
 921  *  needs to be applied if eight whole lines fit in the buffer at once.
 922  *  The WM is adjusted upwards by the difference between the FIFO size
 923  *  and the size of 8 whole lines. This adjustment is always performed
 924  *  in the actual pixel depth regardless of whether FBC is enabled or not."
 925  */
 926 static int g4x_tlb_miss_wa(int fifo_size, int width, int cpp)
 927 {
 928         int tlb_miss = fifo_size * 64 - width * cpp * 8;
 929
 930         return max(0, tlb_miss);
 931 }
 932
 933 static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
 934                                 const struct g4x_wm_values *wm)
 935 {
 936         enum pipe pipe;
 937
 938         for_each_pipe(dev_priv, pipe)
 939                 trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
 940
 941         I915_WRITE(DSPFW1,
 942                    FW_WM(wm->sr.plane, SR) |
 943                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
 944                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
 945                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
 946         I915_WRITE(DSPFW2,
 947                    (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
 948                    FW_WM(wm->sr.fbc, FBC_SR) |
 949                    FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
 950                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
 951                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
 952                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
 953         I915_WRITE(DSPFW3,
 954                    (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
 955                    FW_WM(wm->sr.cursor, CURSOR_SR) |
 956                    FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
 957                    FW_WM(wm->hpll.plane, HPLL_SR));
 958
 959         POSTING_READ(DSPFW1);
 960 }
 961
 962 #define FW_WM_VLV(value, plane) \
 963         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 964
 965 static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
 966                                 const struct vlv_wm_values *wm)
 967 {
 968         enum pipe pipe;
 969
 970         for_each_pipe(dev_priv, pipe) {
 971                 trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
 972
 973                 I915_WRITE(VLV_DDL(pipe),
 974                            (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
 975                            (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
 976                            (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
 977                            (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
 978         }
 979
 980         /*
 981          * Zero the (unused) WM1 watermarks, and also clear all the
 982          * high order bits so that there are no out of bounds values
 983          * present in the registers during the reprogramming.
 984          */
 985         I915_WRITE(DSPHOWM, 0);
 986         I915_WRITE(DSPHOWM1, 0);
 987         I915_WRITE(DSPFW4, 0);
 988         I915_WRITE(DSPFW5, 0);
 989         I915_WRITE(DSPFW6, 0);
 990
 991         I915_WRITE(DSPFW1,
 992                    FW_WM(wm->sr.plane, SR) |
 993                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
 994                    FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
 995                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
 996         I915_WRITE(DSPFW2,
 997                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
 998                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
 999                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
1000         I915_WRITE(DSPFW3,
1001                    FW_WM(wm->sr.cursor, CURSOR_SR));
1002
1003         if (IS_CHERRYVIEW(dev_priv)) {
1004                 I915_WRITE(DSPFW7_CHV,
1005                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1006                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1007                 I915_WRITE(DSPFW8_CHV,
1008                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
1009                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
1010                 I915_WRITE(DSPFW9_CHV,
1011                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
1012                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
1013                 I915_WRITE(DSPHOWM,
1014                            FW_WM(wm->sr.plane >> 9, SR_HI) |
1015                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
1016                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
1017                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
1018                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1019                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1020                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1021                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1022                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1023                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1024         } else {
1025                 I915_WRITE(DSPFW7,
1026                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1027                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1028                 I915_WRITE(DSPHOWM,
1029                            FW_WM(wm->sr.plane >> 9, SR_HI) |
1030                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1031                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1032                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1033                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1034                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1035                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1036         }
1037
1038         POSTING_READ(DSPFW1);
1039 }
1040
1041 #undef FW_WM_VLV
1042
1043 static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv)
1044 {
1045         /* all latencies in usec */
1046         dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
1047         dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
1048         dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
1049
1050         dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;
1051 }
1052
1053 static int g4x_plane_fifo_size(enum plane_id plane_id, int level)
1054 {
1055         /*
1056          * DSPCNTR[13] supposedly controls whether the
1057          * primary plane can use the FIFO space otherwise
1058          * reserved for the sprite plane. It's not 100% clear
1059          * what the actual FIFO size is, but it looks like we
1060          * can happily set both primary and sprite watermarks
1061          * up to 127 cachelines. So that would seem to mean
1062          * that either DSPCNTR[13] doesn't do anything, or that
1063          * the total FIFO is >= 256 cachelines in size. Either
1064          * way, we don't seem to have to worry about this
1065          * repartitioning as the maximum watermark value the
1066          * register can hold for each plane is lower than the
1067          * minimum FIFO size.
1068          */
1069         switch (plane_id) {
1070         case PLANE_CURSOR:
1071                 return 63;
1072         case PLANE_PRIMARY:
1073                 return level == G4X_WM_LEVEL_NORMAL ? 127 : 511;
1074         case PLANE_SPRITE0:
1075                 return level == G4X_WM_LEVEL_NORMAL ? 127 : 0;
1076         default:
1077                 MISSING_CASE(plane_id);
1078                 return 0;
1079         }
1080 }
1081
1082 static int g4x_fbc_fifo_size(int level)
1083 {
1084         switch (level) {
1085         case G4X_WM_LEVEL_SR:
1086                 return 7;
1087         case G4X_WM_LEVEL_HPLL:
1088                 return 15;
1089         default:
1090                 MISSING_CASE(level);
1091                 return 0;
1092         }
1093 }
1094
1095 static uint16_t g4x_compute_wm(const struct intel_crtc_state *crtc_state,
1096                                const struct intel_plane_state *plane_state,
1097                                int level)
1098 {
1099         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1100         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1101         const struct drm_display_mode *adjusted_mode =
1102                 &crtc_state->base.adjusted_mode;
1103         int clock, htotal, cpp, width, wm;
1104         int latency = dev_priv->wm.pri_latency[level] * 10;
1105
1106         if (latency == 0)
1107                 return USHRT_MAX;
1108
1109         if (!intel_wm_plane_visible(crtc_state, plane_state))
1110                 return 0;
1111
1112         /*
1113          * Not 100% sure which way ELK should go here as the
1114          * spec only says CL/CTG should assume 32bpp and BW
1115          * doesn't need to. But as these things followed the
1116          * mobile vs. desktop lines on gen3 as well, let's
1117          * assume ELK doesn't need this.
1118          *
1119          * The spec also fails to list such a restriction for
1120          * the HPLL watermark, which seems a little strange.
1121          * Let's use 32bpp for the HPLL watermark as well.
1122          */
1123         if (IS_GM45(dev_priv) && plane->id == PLANE_PRIMARY &&
1124             level != G4X_WM_LEVEL_NORMAL)
1125                 cpp = 4;
1126         else
1127                 cpp = plane_state->base.fb->format->cpp[0];
1128
1129         clock = adjusted_mode->crtc_clock;
1130         htotal = adjusted_mode->crtc_htotal;
1131
1132         if (plane->id == PLANE_CURSOR)
1133                 width = plane_state->base.crtc_w;
1134         else
1135                 width = drm_rect_width(&plane_state->base.dst);
1136
1137         if (plane->id == PLANE_CURSOR) {
1138                 wm = intel_wm_method2(clock, htotal, width, cpp, latency);
1139         } else if (plane->id == PLANE_PRIMARY &&
1140                    level == G4X_WM_LEVEL_NORMAL) {
1141                 wm = intel_wm_method1(clock, cpp, latency);
1142         } else {
1143                 int small, large;
1144
1145                 small = intel_wm_method1(clock, cpp, latency);
1146                 large = intel_wm_method2(clock, htotal, width, cpp, latency);
1147
1148                 wm = min(small, large);
1149         }
1150
1151         wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level),
1152                               width, cpp);
1153
1154         wm = DIV_ROUND_UP(wm, 64) + 2;
1155
1156         return min_t(int, wm, USHRT_MAX);
1157 }
1158
1159 static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1160                                  int level, enum plane_id plane_id, u16 value)
1161 {
1162         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1163         bool dirty = false;
1164
1165         for (; level < intel_wm_num_levels(dev_priv); level++) {
1166                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1167
1168                 dirty |= raw->plane[plane_id] != value;
1169                 raw->plane[plane_id] = value;
1170         }
1171
1172         return dirty;
1173 }
1174
1175 static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
1176                                int level, u16 value)
1177 {
1178         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1179         bool dirty = false;
1180
1181         /* NORMAL level doesn't have an FBC watermark */
1182         level = max(level, G4X_WM_LEVEL_SR);
1183
1184         for (; level < intel_wm_num_levels(dev_priv); level++) {
1185                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1186
1187                 dirty |= raw->fbc != value;
1188                 raw->fbc = value;
1189         }
1190
1191         return dirty;
1192 }
1193
1194 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1195                                    const struct intel_plane_state *pstate,
1196                                    uint32_t pri_val);
1197
1198 static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1199                                      const struct intel_plane_state *plane_state)
1200 {
1201         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1202         int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1203         enum plane_id plane_id = plane->id;
1204         bool dirty = false;
1205         int level;
1206
1207         if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1208                 dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1209                 if (plane_id == PLANE_PRIMARY)
1210                         dirty |= g4x_raw_fbc_wm_set(crtc_state, 0, 0);
1211                 goto out;
1212         }
1213
1214         for (level = 0; level < num_levels; level++) {
1215                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1216                 int wm, max_wm;
1217
1218                 wm = g4x_compute_wm(crtc_state, plane_state, level);
1219                 max_wm = g4x_plane_fifo_size(plane_id, level);
1220
1221                 if (wm > max_wm)
1222                         break;
1223
1224                 dirty |= raw->plane[plane_id] != wm;
1225                 raw->plane[plane_id] = wm;
1226
1227                 if (plane_id != PLANE_PRIMARY ||
1228                     level == G4X_WM_LEVEL_NORMAL)
1229                         continue;
1230
1231                 wm = ilk_compute_fbc_wm(crtc_state, plane_state,
1232                                         raw->plane[plane_id]);
1233                 max_wm = g4x_fbc_fifo_size(level);
1234
1235                 /*
1236                  * FBC wm is not mandatory as we
1237                  * can always just disable its use.
1238                  */
1239                 if (wm > max_wm)
1240                         wm = USHRT_MAX;
1241
1242                 dirty |= raw->fbc != wm;
1243                 raw->fbc = wm;
1244         }
1245
1246         /* mark watermarks as invalid */
1247         dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1248
1249         if (plane_id == PLANE_PRIMARY)
1250                 dirty |= g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
1251
1252  out:
1253         if (dirty) {
1254                 DRM_DEBUG_KMS("%s watermarks: normal=%d, SR=%d, HPLL=%d\n",
1255                               plane->base.name,
1256                               crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],
1257                               crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],
1258                               crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
1259
1260                 if (plane_id == PLANE_PRIMARY)
1261                         DRM_DEBUG_KMS("FBC watermarks: SR=%d, HPLL=%d\n",
1262                                       crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,
1263                                       crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);
1264         }
1265
1266         return dirty;
1267 }
1268
1269 static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1270                                       enum plane_id plane_id, int level)
1271 {
1272         const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1273
1274         return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level);
1275 }
1276
1277 static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
1278                                      int level)
1279 {
1280         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1281
1282         if (level > dev_priv->wm.max_level)
1283                 return false;
1284
1285         return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1286                 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1287                 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1288 }
1289
1290 /* mark all levels starting from 'level' as invalid */
1291 static void g4x_invalidate_wms(struct intel_crtc *crtc,
1292                                struct g4x_wm_state *wm_state, int level)
1293 {
1294         if (level <= G4X_WM_LEVEL_NORMAL) {
1295                 enum plane_id plane_id;
1296
1297                 for_each_plane_id_on_crtc(crtc, plane_id)
1298                         wm_state->wm.plane[plane_id] = USHRT_MAX;
1299         }
1300
1301         if (level <= G4X_WM_LEVEL_SR) {
1302                 wm_state->cxsr = false;
1303                 wm_state->sr.cursor = USHRT_MAX;
1304                 wm_state->sr.plane = USHRT_MAX;
1305                 wm_state->sr.fbc = USHRT_MAX;
1306         }
1307
1308         if (level <= G4X_WM_LEVEL_HPLL) {
1309                 wm_state->hpll_en = false;
1310                 wm_state->hpll.cursor = USHRT_MAX;
1311                 wm_state->hpll.plane = USHRT_MAX;
1312                 wm_state->hpll.fbc = USHRT_MAX;
1313         }
1314 }
1315
1316 static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1317 {
1318         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1319         struct intel_atomic_state *state =
1320                 to_intel_atomic_state(crtc_state->base.state);
1321         struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
1322         int num_active_planes = hweight32(crtc_state->active_planes &
1323                                           ~BIT(PLANE_CURSOR));
1324         const struct g4x_pipe_wm *raw;
1325         struct intel_plane_state *plane_state;
1326         struct intel_plane *plane;
1327         enum plane_id plane_id;
1328         int i, level;
1329         unsigned int dirty = 0;
1330
1331         for_each_intel_plane_in_state(state, plane, plane_state, i) {
1332                 const struct intel_plane_state *old_plane_state =
1333                         to_intel_plane_state(plane->base.state);
1334
1335                 if (plane_state->base.crtc != &crtc->base &&
1336                     old_plane_state->base.crtc != &crtc->base)
1337                         continue;
1338
1339                 if (g4x_raw_plane_wm_compute(crtc_state, plane_state))
1340                         dirty |= BIT(plane->id);
1341         }
1342
1343         if (!dirty)
1344                 return 0;
1345
1346         level = G4X_WM_LEVEL_NORMAL;
1347         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1348                 goto out;
1349
1350         raw = &crtc_state->wm.g4x.raw[level];
1351         for_each_plane_id_on_crtc(crtc, plane_id)
1352                 wm_state->wm.plane[plane_id] = raw->plane[plane_id];
1353
1354         level = G4X_WM_LEVEL_SR;
1355
1356         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1357                 goto out;
1358
1359         raw = &crtc_state->wm.g4x.raw[level];
1360         wm_state->sr.plane = raw->plane[PLANE_PRIMARY];
1361         wm_state->sr.cursor = raw->plane[PLANE_CURSOR];
1362         wm_state->sr.fbc = raw->fbc;
1363
1364         wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY);
1365
1366         level = G4X_WM_LEVEL_HPLL;
1367
1368         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1369                 goto out;
1370
1371         raw = &crtc_state->wm.g4x.raw[level];
1372         wm_state->hpll.plane = raw->plane[PLANE_PRIMARY];
1373         wm_state->hpll.cursor = raw->plane[PLANE_CURSOR];
1374         wm_state->hpll.fbc = raw->fbc;
1375
1376         wm_state->hpll_en = wm_state->cxsr;
1377
1378         level++;
1379
1380  out:
1381         if (level == G4X_WM_LEVEL_NORMAL)
1382                 return -EINVAL;
1383
1384         /* invalidate the higher levels */
1385         g4x_invalidate_wms(crtc, wm_state, level);
1386
1387         /*
1388          * Determine if the FBC watermark(s) can be used. IF
1389          * this isn't the case we prefer to disable the FBC
1390          ( watermark(s) rather than disable the SR/HPLL
1391          * level(s) entirely.
1392          */
1393         wm_state->fbc_en = level > G4X_WM_LEVEL_NORMAL;
1394
1395         if (level >= G4X_WM_LEVEL_SR &&
1396             wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR))
1397                 wm_state->fbc_en = false;
1398         else if (level >= G4X_WM_LEVEL_HPLL &&
1399                  wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))
1400                 wm_state->fbc_en = false;
1401
1402         return 0;
1403 }
1404
1405 static int g4x_compute_intermediate_wm(struct drm_device *dev,
1406                                        struct intel_crtc *crtc,
1407                                        struct intel_crtc_state *crtc_state)
1408 {
1409         struct g4x_wm_state *intermediate = &crtc_state->wm.g4x.intermediate;
1410         const struct g4x_wm_state *optimal = &crtc_state->wm.g4x.optimal;
1411         const struct g4x_wm_state *active = &crtc->wm.active.g4x;
1412         enum plane_id plane_id;
1413
1414         intermediate->cxsr = optimal->cxsr && active->cxsr &&
1415                 !crtc_state->disable_cxsr;
1416         intermediate->hpll_en = optimal->hpll_en && active->hpll_en &&
1417                 !crtc_state->disable_cxsr;
1418         intermediate->fbc_en = optimal->fbc_en && active->fbc_en;
1419
1420         for_each_plane_id_on_crtc(crtc, plane_id) {
1421                 intermediate->wm.plane[plane_id] =
1422                         max(optimal->wm.plane[plane_id],
1423                             active->wm.plane[plane_id]);
1424
1425                 WARN_ON(intermediate->wm.plane[plane_id] >
1426                         g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL));
1427         }
1428
1429         intermediate->sr.plane = max(optimal->sr.plane,
1430                                      active->sr.plane);
1431         intermediate->sr.cursor = max(optimal->sr.cursor,
1432                                       active->sr.cursor);
1433         intermediate->sr.fbc = max(optimal->sr.fbc,
1434                                    active->sr.fbc);
1435
1436         intermediate->hpll.plane = max(optimal->hpll.plane,
1437                                        active->hpll.plane);
1438         intermediate->hpll.cursor = max(optimal->hpll.cursor,
1439                                         active->hpll.cursor);
1440         intermediate->hpll.fbc = max(optimal->hpll.fbc,
1441                                      active->hpll.fbc);
1442
1443         WARN_ON((intermediate->sr.plane >
1444                  g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_SR) ||
1445                  intermediate->sr.cursor >
1446                  g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_SR)) &&
1447                 intermediate->cxsr);
1448         WARN_ON((intermediate->sr.plane >
1449                  g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) ||
1450                  intermediate->sr.cursor >
1451                  g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) &&
1452                 intermediate->hpll_en);
1453
1454         WARN_ON(intermediate->sr.fbc > g4x_fbc_fifo_size(1) &&
1455                 intermediate->fbc_en && intermediate->cxsr);
1456         WARN_ON(intermediate->hpll.fbc > g4x_fbc_fifo_size(2) &&
1457                 intermediate->fbc_en && intermediate->hpll_en);
1458
1459         /*
1460          * If our intermediate WM are identical to the final WM, then we can
1461          * omit the post-vblank programming; only update if it's different.
1462          */
1463         if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
1464                 crtc_state->wm.need_postvbl_update = true;
1465
1466         return 0;
1467 }
1468
1469 static void g4x_merge_wm(struct drm_i915_private *dev_priv,
1470                          struct g4x_wm_values *wm)
1471 {
1472         struct intel_crtc *crtc;
1473         int num_active_crtcs = 0;
1474
1475         wm->cxsr = true;
1476         wm->hpll_en = true;
1477         wm->fbc_en = true;
1478
1479         for_each_intel_crtc(&dev_priv->drm, crtc) {
1480                 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1481
1482                 if (!crtc->active)
1483                         continue;
1484
1485                 if (!wm_state->cxsr)
1486                         wm->cxsr = false;
1487                 if (!wm_state->hpll_en)
1488                         wm->hpll_en = false;
1489                 if (!wm_state->fbc_en)
1490                         wm->fbc_en = false;
1491
1492                 num_active_crtcs++;
1493         }
1494
1495         if (num_active_crtcs != 1) {
1496                 wm->cxsr = false;
1497                 wm->hpll_en = false;
1498                 wm->fbc_en = false;
1499         }
1500
1501         for_each_intel_crtc(&dev_priv->drm, crtc) {
1502                 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1503                 enum pipe pipe = crtc->pipe;
1504
1505                 wm->pipe[pipe] = wm_state->wm;
1506                 if (crtc->active && wm->cxsr)
1507                         wm->sr = wm_state->sr;
1508                 if (crtc->active && wm->hpll_en)
1509                         wm->hpll = wm_state->hpll;
1510         }
1511 }
1512
1513 static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
1514 {
1515         struct g4x_wm_values *old_wm = &dev_priv->wm.g4x;
1516         struct g4x_wm_values new_wm = {};
1517
1518         g4x_merge_wm(dev_priv, &new_wm);
1519
1520         if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
1521                 return;
1522
1523         if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
1524                 _intel_set_memory_cxsr(dev_priv, false);
1525
1526         g4x_write_wm_values(dev_priv, &new_wm);
1527
1528         if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
1529                 _intel_set_memory_cxsr(dev_priv, true);
1530
1531         *old_wm = new_wm;
1532 }
1533
1534 static void g4x_initial_watermarks(struct intel_atomic_state *state,
1535                                    struct intel_crtc_state *crtc_state)
1536 {
1537         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1538         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1539
1540         mutex_lock(&dev_priv->wm.wm_mutex);
1541         crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
1542         g4x_program_watermarks(dev_priv);
1543         mutex_unlock(&dev_priv->wm.wm_mutex);
1544 }
1545
1546 static void g4x_optimize_watermarks(struct intel_atomic_state *state,
1547                                     struct intel_crtc_state *crtc_state)
1548 {
1549         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1550         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1551
1552         if (!crtc_state->wm.need_postvbl_update)
1553                 return;
1554
1555         mutex_lock(&dev_priv->wm.wm_mutex);
1556         intel_crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
1557         g4x_program_watermarks(dev_priv);
1558         mutex_unlock(&dev_priv->wm.wm_mutex);
1559 }
1560
1561 /* latency must be in 0.1us units. */
1562 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
1563                                    unsigned int htotal,
1564                                    unsigned int width,
1565                                    unsigned int cpp,
1566                                    unsigned int latency)
1567 {
1568         unsigned int ret;
1569
1570         ret = intel_wm_method2(pixel_rate, htotal,
1571                                width, cpp, latency);
1572         ret = DIV_ROUND_UP(ret, 64);
1573
1574         return ret;
1575 }
1576
1577 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
1578 {
1579         /* all latencies in usec */
1580         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
1581
1582         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
1583
1584         if (IS_CHERRYVIEW(dev_priv)) {
1585                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
1586                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
1587
1588                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
1589         }
1590 }
1591
1592 static uint16_t vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
1593                                      const struct intel_plane_state *plane_state,
1594                                      int level)
1595 {
1596         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1597         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1598         const struct drm_display_mode *adjusted_mode =
1599                 &crtc_state->base.adjusted_mode;
1600         int clock, htotal, cpp, width, wm;
1601
1602         if (dev_priv->wm.pri_latency[level] == 0)
1603                 return USHRT_MAX;
1604
1605         if (!intel_wm_plane_visible(crtc_state, plane_state))
1606                 return 0;
1607
1608         cpp = plane_state->base.fb->format->cpp[0];
1609         clock = adjusted_mode->crtc_clock;
1610         htotal = adjusted_mode->crtc_htotal;
1611         width = crtc_state->pipe_src_w;
1612
1613         if (plane->id == PLANE_CURSOR) {
1614                 /*
1615                  * FIXME the formula gives values that are
1616                  * too big for the cursor FIFO, and hence we
1617                  * would never be able to use cursors. For
1618                  * now just hardcode the watermark.
1619                  */
1620                 wm = 63;
1621         } else {
1622                 wm = vlv_wm_method2(clock, htotal, width, cpp,
1623                                     dev_priv->wm.pri_latency[level] * 10);
1624         }
1625
1626         return min_t(int, wm, USHRT_MAX);
1627 }
1628
1629 static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
1630 {
1631         return (active_planes & (BIT(PLANE_SPRITE0) |
1632                                  BIT(PLANE_SPRITE1))) == BIT(PLANE_SPRITE1);
1633 }
1634
1635 static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
1636 {
1637         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1638         const struct g4x_pipe_wm *raw =
1639                 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
1640         struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
1641         unsigned int active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1642         int num_active_planes = hweight32(active_planes);
1643         const int fifo_size = 511;
1644         int fifo_extra, fifo_left = fifo_size;
1645         int sprite0_fifo_extra = 0;
1646         unsigned int total_rate;
1647         enum plane_id plane_id;
1648
1649         /*
1650          * When enabling sprite0 after sprite1 has already been enabled
1651          * we tend to get an underrun unless sprite0 already has some
1652          * FIFO space allcoated. Hence we always allocate at least one
1653          * cacheline for sprite0 whenever sprite1 is enabled.
1654          *
1655          * All other plane enable sequences appear immune to this problem.
1656          */
1657         if (vlv_need_sprite0_fifo_workaround(active_planes))
1658                 sprite0_fifo_extra = 1;
1659
1660         total_rate = raw->plane[PLANE_PRIMARY] +
1661                 raw->plane[PLANE_SPRITE0] +
1662                 raw->plane[PLANE_SPRITE1] +
1663                 sprite0_fifo_extra;
1664
1665         if (total_rate > fifo_size)
1666                 return -EINVAL;
1667
1668         if (total_rate == 0)
1669                 total_rate = 1;
1670
1671         for_each_plane_id_on_crtc(crtc, plane_id) {
1672                 unsigned int rate;
1673
1674                 if ((active_planes & BIT(plane_id)) == 0) {
1675                         fifo_state->plane[plane_id] = 0;
1676                         continue;
1677                 }
1678
1679                 rate = raw->plane[plane_id];
1680                 fifo_state->plane[plane_id] = fifo_size * rate / total_rate;
1681                 fifo_left -= fifo_state->plane[plane_id];
1682         }
1683
1684         fifo_state->plane[PLANE_SPRITE0] += sprite0_fifo_extra;
1685         fifo_left -= sprite0_fifo_extra;
1686
1687         fifo_state->plane[PLANE_CURSOR] = 63;
1688
1689         fifo_extra = DIV_ROUND_UP(fifo_left, num_active_planes ?: 1);
1690
1691         /* spread the remainder evenly */
1692         for_each_plane_id_on_crtc(crtc, plane_id) {
1693                 int plane_extra;
1694
1695                 if (fifo_left == 0)
1696                         break;
1697
1698                 if ((active_planes & BIT(plane_id)) == 0)
1699                         continue;
1700
1701                 plane_extra = min(fifo_extra, fifo_left);
1702                 fifo_state->plane[plane_id] += plane_extra;
1703                 fifo_left -= plane_extra;
1704         }
1705
1706         WARN_ON(active_planes != 0 && fifo_left != 0);
1707
1708         /* give it all to the first plane if none are active */
1709         if (active_planes == 0) {
1710                 WARN_ON(fifo_left != fifo_size);
1711                 fifo_state->plane[PLANE_PRIMARY] = fifo_left;
1712         }
1713
1714         return 0;
1715 }
1716
1717 /* mark all levels starting from 'level' as invalid */
1718 static void vlv_invalidate_wms(struct intel_crtc *crtc,
1719                                struct vlv_wm_state *wm_state, int level)
1720 {
1721         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1722
1723         for (; level < intel_wm_num_levels(dev_priv); level++) {
1724                 enum plane_id plane_id;
1725
1726                 for_each_plane_id_on_crtc(crtc, plane_id)
1727                         wm_state->wm[level].plane[plane_id] = USHRT_MAX;
1728
1729                 wm_state->sr[level].cursor = USHRT_MAX;
1730                 wm_state->sr[level].plane = USHRT_MAX;
1731         }
1732 }
1733
1734 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
1735 {
1736         if (wm > fifo_size)
1737                 return USHRT_MAX;
1738         else
1739                 return fifo_size - wm;
1740 }
1741
1742 /*
1743  * Starting from 'level' set all higher
1744  * levels to 'value' in the "raw" watermarks.
1745  */
1746 static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1747                                  int level, enum plane_id plane_id, u16 value)
1748 {
1749         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1750         int num_levels = intel_wm_num_levels(dev_priv);
1751         bool dirty = false;
1752
1753         for (; level < num_levels; level++) {
1754                 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1755
1756                 dirty |= raw->plane[plane_id] != value;
1757                 raw->plane[plane_id] = value;
1758         }
1759
1760         return dirty;
1761 }
1762
1763 static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1764                                      const struct intel_plane_state *plane_state)
1765 {
1766         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1767         enum plane_id plane_id = plane->id;
1768         int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1769         int level;
1770         bool dirty = false;
1771
1772         if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1773                 dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1774                 goto out;
1775         }
1776
1777         for (level = 0; level < num_levels; level++) {
1778                 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1779                 int wm = vlv_compute_wm_level(crtc_state, plane_state, level);
1780                 int max_wm = plane_id == PLANE_CURSOR ? 63 : 511;
1781
1782                 if (wm > max_wm)
1783                         break;
1784
1785                 dirty |= raw->plane[plane_id] != wm;
1786                 raw->plane[plane_id] = wm;
1787         }
1788
1789         /* mark all higher levels as invalid */
1790         dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1791
1792 out:
1793         if (dirty)
1794                 DRM_DEBUG_KMS("%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n",
1795                               plane->base.name,
1796                               crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
1797                               crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],
1798                               crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);
1799
1800         return dirty;
1801 }
1802
1803 static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1804                                       enum plane_id plane_id, int level)
1805 {
1806         const struct g4x_pipe_wm *raw =
1807                 &crtc_state->wm.vlv.raw[level];
1808         const struct vlv_fifo_state *fifo_state =
1809                 &crtc_state->wm.vlv.fifo_state;
1810
1811         return raw->plane[plane_id] <= fifo_state->plane[plane_id];
1812 }
1813
1814 static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level)
1815 {
1816         return vlv_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1817                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1818                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE1, level) &&
1819                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1820 }
1821
1822 static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1823 {
1824         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1825         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1826         struct intel_atomic_state *state =
1827                 to_intel_atomic_state(crtc_state->base.state);
1828         struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
1829         const struct vlv_fifo_state *fifo_state =
1830                 &crtc_state->wm.vlv.fifo_state;
1831         int num_active_planes = hweight32(crtc_state->active_planes &
1832                                           ~BIT(PLANE_CURSOR));
1833         bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base);
1834         struct intel_plane_state *plane_state;
1835         struct intel_plane *plane;
1836         enum plane_id plane_id;
1837         int level, ret, i;
1838         unsigned int dirty = 0;
1839
1840         for_each_intel_plane_in_state(state, plane, plane_state, i) {
1841                 const struct intel_plane_state *old_plane_state =
1842                         to_intel_plane_state(plane->base.state);
1843
1844                 if (plane_state->base.crtc != &crtc->base &&
1845                     old_plane_state->base.crtc != &crtc->base)
1846                         continue;
1847
1848                 if (vlv_raw_plane_wm_compute(crtc_state, plane_state))
1849                         dirty |= BIT(plane->id);
1850         }
1851
1852         /*
1853          * DSPARB registers may have been reset due to the
1854          * power well being turned off. Make sure we restore
1855          * them to a consistent state even if no primary/sprite
1856          * planes are initially active.
1857          */
1858         if (needs_modeset)
1859                 crtc_state->fifo_changed = true;
1860
1861         if (!dirty)
1862                 return 0;
1863
1864         /* cursor changes don't warrant a FIFO recompute */
1865         if (dirty & ~BIT(PLANE_CURSOR)) {
1866                 const struct intel_crtc_state *old_crtc_state =
1867                         to_intel_crtc_state(crtc->base.state);
1868                 const struct vlv_fifo_state *old_fifo_state =
1869                         &old_crtc_state->wm.vlv.fifo_state;
1870
1871                 ret = vlv_compute_fifo(crtc_state);
1872                 if (ret)
1873                         return ret;
1874
1875                 if (needs_modeset ||
1876                     memcmp(old_fifo_state, fifo_state,
1877                            sizeof(*fifo_state)) != 0)
1878                         crtc_state->fifo_changed = true;
1879         }
1880
1881         /* initially allow all levels */
1882         wm_state->num_levels = intel_wm_num_levels(dev_priv);
1883         /*
1884          * Note that enabling cxsr with no primary/sprite planes
1885          * enabled can wedge the pipe. Hence we only allow cxsr
1886          * with exactly one enabled primary/sprite plane.
1887          */
1888         wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1;
1889
1890         for (level = 0; level < wm_state->num_levels; level++) {
1891                 const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1892                 const int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1893
1894                 if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
1895                         break;
1896
1897                 for_each_plane_id_on_crtc(crtc, plane_id) {
1898                         wm_state->wm[level].plane[plane_id] =
1899                                 vlv_invert_wm_value(raw->plane[plane_id],
1900                                                     fifo_state->plane[plane_id]);
1901                 }
1902
1903                 wm_state->sr[level].plane =
1904                         vlv_invert_wm_value(max3(raw->plane[PLANE_PRIMARY],
1905                                                  raw->plane[PLANE_SPRITE0],
1906                                                  raw->plane[PLANE_SPRITE1]),
1907                                             sr_fifo_size);
1908
1909                 wm_state->sr[level].cursor =
1910                         vlv_invert_wm_value(raw->plane[PLANE_CURSOR],
1911                                             63);
1912         }
1913
1914         if (level == 0)
1915                 return -EINVAL;
1916
1917         /* limit to only levels we can actually handle */
1918         wm_state->num_levels = level;
1919
1920         /* invalidate the higher levels */
1921         vlv_invalidate_wms(crtc, wm_state, level);
1922
1923         return 0;
1924 }
1925
1926 #define VLV_FIFO(plane, value) \
1927         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1928
1929 static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
1930                                    struct intel_crtc_state *crtc_state)
1931 {
1932         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1933         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1934         const struct vlv_fifo_state *fifo_state =
1935                 &crtc_state->wm.vlv.fifo_state;
1936         int sprite0_start, sprite1_start, fifo_size;
1937
1938         if (!crtc_state->fifo_changed)
1939                 return;
1940
1941         sprite0_start = fifo_state->plane[PLANE_PRIMARY];
1942         sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start;
1943         fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start;
1944
1945         WARN_ON(fifo_state->plane[PLANE_CURSOR] != 63);
1946         WARN_ON(fifo_size != 511);
1947
1948         trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size);
1949
1950         /*
1951          * uncore.lock serves a double purpose here. It allows us to
1952          * use the less expensive I915_{READ,WRITE}_FW() functions, and
1953          * it protects the DSPARB registers from getting clobbered by
1954          * parallel updates from multiple pipes.
1955          *
1956          * intel_pipe_update_start() has already disabled interrupts
1957          * for us, so a plain spin_lock() is sufficient here.
1958          */
1959         spin_lock(&dev_priv->uncore.lock);
1960
1961         switch (crtc->pipe) {
1962                 uint32_t dsparb, dsparb2, dsparb3;
1963         case PIPE_A:
1964                 dsparb = I915_READ_FW(DSPARB);
1965                 dsparb2 = I915_READ_FW(DSPARB2);
1966
1967                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1968                             VLV_FIFO(SPRITEB, 0xff));
1969                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1970                            VLV_FIFO(SPRITEB, sprite1_start));
1971
1972                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1973                              VLV_FIFO(SPRITEB_HI, 0x1));
1974                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1975                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1976
1977                 I915_WRITE_FW(DSPARB, dsparb);
1978                 I915_WRITE_FW(DSPARB2, dsparb2);
1979                 break;
1980         case PIPE_B:
1981                 dsparb = I915_READ_FW(DSPARB);
1982                 dsparb2 = I915_READ_FW(DSPARB2);
1983
1984                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1985                             VLV_FIFO(SPRITED, 0xff));
1986                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1987                            VLV_FIFO(SPRITED, sprite1_start));
1988
1989                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1990                              VLV_FIFO(SPRITED_HI, 0xff));
1991                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1992                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1993
1994                 I915_WRITE_FW(DSPARB, dsparb);
1995                 I915_WRITE_FW(DSPARB2, dsparb2);
1996                 break;
1997         case PIPE_C:
1998                 dsparb3 = I915_READ_FW(DSPARB3);
1999                 dsparb2 = I915_READ_FW(DSPARB2);
2000
2001                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
2002                              VLV_FIFO(SPRITEF, 0xff));
2003                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
2004                             VLV_FIFO(SPRITEF, sprite1_start));
2005
2006                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
2007                              VLV_FIFO(SPRITEF_HI, 0xff));
2008                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
2009                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
2010
2011                 I915_WRITE_FW(DSPARB3, dsparb3);
2012                 I915_WRITE_FW(DSPARB2, dsparb2);
2013                 break;
2014         default:
2015                 break;
2016         }
2017
2018         POSTING_READ_FW(DSPARB);
2019
2020         spin_unlock(&dev_priv->uncore.lock);
2021 }
2022
2023 #undef VLV_FIFO
2024
2025 static int vlv_compute_intermediate_wm(struct drm_device *dev,
2026                                        struct intel_crtc *crtc,
2027                                        struct intel_crtc_state *crtc_state)
2028 {
2029         struct vlv_wm_state *intermediate = &crtc_state->wm.vlv.intermediate;
2030         const struct vlv_wm_state *optimal = &crtc_state->wm.vlv.optimal;
2031         const struct vlv_wm_state *active = &crtc->wm.active.vlv;
2032         int level;
2033
2034         intermediate->num_levels = min(optimal->num_levels, active->num_levels);
2035         intermediate->cxsr = optimal->cxsr && active->cxsr &&
2036                 !crtc_state->disable_cxsr;
2037
2038         for (level = 0; level < intermediate->num_levels; level++) {
2039                 enum plane_id plane_id;
2040
2041                 for_each_plane_id_on_crtc(crtc, plane_id) {
2042                         intermediate->wm[level].plane[plane_id] =
2043                                 min(optimal->wm[level].plane[plane_id],
2044                                     active->wm[level].plane[plane_id]);
2045                 }
2046
2047                 intermediate->sr[level].plane = min(optimal->sr[level].plane,
2048                                                     active->sr[level].plane);
2049                 intermediate->sr[level].cursor = min(optimal->sr[level].cursor,
2050                                                      active->sr[level].cursor);
2051         }
2052
2053         vlv_invalidate_wms(crtc, intermediate, level);
2054
2055         /*
2056          * If our intermediate WM are identical to the final WM, then we can
2057          * omit the post-vblank programming; only update if it's different.
2058          */
2059         if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
2060                 crtc_state->wm.need_postvbl_update = true;
2061
2062         return 0;
2063 }
2064
2065 static void vlv_merge_wm(struct drm_i915_private *dev_priv,
2066                          struct vlv_wm_values *wm)
2067 {
2068         struct intel_crtc *crtc;
2069         int num_active_crtcs = 0;
2070
2071         wm->level = dev_priv->wm.max_level;
2072         wm->cxsr = true;
2073
2074         for_each_intel_crtc(&dev_priv->drm, crtc) {
2075                 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2076
2077                 if (!crtc->active)
2078                         continue;
2079
2080                 if (!wm_state->cxsr)
2081                         wm->cxsr = false;
2082
2083                 num_active_crtcs++;
2084                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
2085         }
2086
2087         if (num_active_crtcs != 1)
2088                 wm->cxsr = false;
2089
2090         if (num_active_crtcs > 1)
2091                 wm->level = VLV_WM_LEVEL_PM2;
2092
2093         for_each_intel_crtc(&dev_priv->drm, crtc) {
2094                 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2095                 enum pipe pipe = crtc->pipe;
2096
2097                 wm->pipe[pipe] = wm_state->wm[wm->level];
2098                 if (crtc->active && wm->cxsr)
2099                         wm->sr = wm_state->sr[wm->level];
2100
2101                 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
2102                 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
2103                 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
2104                 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
2105         }
2106 }
2107
2108 static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
2109 {
2110         struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
2111         struct vlv_wm_values new_wm = {};
2112
2113         vlv_merge_wm(dev_priv, &new_wm);
2114
2115         if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
2116                 return;
2117
2118         if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2119                 chv_set_memory_dvfs(dev_priv, false);
2120
2121         if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2122                 chv_set_memory_pm5(dev_priv, false);
2123
2124         if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
2125                 _intel_set_memory_cxsr(dev_priv, false);
2126
2127         vlv_write_wm_values(dev_priv, &new_wm);
2128
2129         if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
2130                 _intel_set_memory_cxsr(dev_priv, true);
2131
2132         if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2133                 chv_set_memory_pm5(dev_priv, true);
2134
2135         if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2136                 chv_set_memory_dvfs(dev_priv, true);
2137
2138         *old_wm = new_wm;
2139 }
2140
2141 static void vlv_initial_watermarks(struct intel_atomic_state *state,
2142                                    struct intel_crtc_state *crtc_state)
2143 {
2144         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2145         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2146
2147         mutex_lock(&dev_priv->wm.wm_mutex);
2148         crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
2149         vlv_program_watermarks(dev_priv);
2150         mutex_unlock(&dev_priv->wm.wm_mutex);
2151 }
2152
2153 static void vlv_optimize_watermarks(struct intel_atomic_state *state,
2154                                     struct intel_crtc_state *crtc_state)
2155 {
2156         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2157         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2158
2159         if (!crtc_state->wm.need_postvbl_update)
2160                 return;
2161
2162         mutex_lock(&dev_priv->wm.wm_mutex);
2163         intel_crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
2164         vlv_program_watermarks(dev_priv);
2165         mutex_unlock(&dev_priv->wm.wm_mutex);
2166 }
2167
2168 static void i965_update_wm(struct intel_crtc *unused_crtc)
2169 {
2170         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2171         struct intel_crtc *crtc;
2172         int srwm = 1;
2173         int cursor_sr = 16;
2174         bool cxsr_enabled;
2175
2176         /* Calc sr entries for one plane configs */
2177         crtc = single_enabled_crtc(dev_priv);
2178         if (crtc) {
2179                 /* self-refresh has much higher latency */
2180                 static const int sr_latency_ns = 12000;
2181                 const struct drm_display_mode *adjusted_mode =
2182                         &crtc->config->base.adjusted_mode;
2183                 const struct drm_framebuffer *fb =
2184                         crtc->base.primary->state->fb;
2185                 int clock = adjusted_mode->crtc_clock;
2186                 int htotal = adjusted_mode->crtc_htotal;
2187                 int hdisplay = crtc->config->pipe_src_w;
2188                 int cpp = fb->format->cpp[0];
2189                 int entries;
2190
2191                 entries = intel_wm_method2(clock, htotal,
2192                                            hdisplay, cpp, sr_latency_ns / 100);
2193                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
2194                 srwm = I965_FIFO_SIZE - entries;
2195                 if (srwm < 0)
2196                         srwm = 1;
2197                 srwm &= 0x1ff;
2198                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
2199                               entries, srwm);
2200
2201                 entries = intel_wm_method2(clock, htotal,
2202                                            crtc->base.cursor->state->crtc_w, 4,
2203                                            sr_latency_ns / 100);
2204                 entries = DIV_ROUND_UP(entries,
2205                                        i965_cursor_wm_info.cacheline_size) +
2206                         i965_cursor_wm_info.guard_size;
2207
2208                 cursor_sr = i965_cursor_wm_info.fifo_size - entries;
2209                 if (cursor_sr > i965_cursor_wm_info.max_wm)
2210                         cursor_sr = i965_cursor_wm_info.max_wm;
2211
2212                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
2213                               "cursor %d\n", srwm, cursor_sr);
2214
2215                 cxsr_enabled = true;
2216         } else {
2217                 cxsr_enabled = false;
2218                 /* Turn off self refresh if both pipes are enabled */
2219                 intel_set_memory_cxsr(dev_priv, false);
2220         }
2221
2222         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2223                       srwm);
2224
2225         /* 965 has limitations... */
2226         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
2227                    FW_WM(8, CURSORB) |
2228                    FW_WM(8, PLANEB) |
2229                    FW_WM(8, PLANEA));
2230         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
2231                    FW_WM(8, PLANEC_OLD));
2232         /* update cursor SR watermark */
2233         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
2234
2235         if (cxsr_enabled)
2236                 intel_set_memory_cxsr(dev_priv, true);
2237 }
2238
2239 #undef FW_WM
2240
2241 static void i9xx_update_wm(struct intel_crtc *unused_crtc)
2242 {
2243         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2244         const struct intel_watermark_params *wm_info;
2245         uint32_t fwater_lo;
2246         uint32_t fwater_hi;
2247         int cwm, srwm = 1;
2248         int fifo_size;
2249         int planea_wm, planeb_wm;
2250         struct intel_crtc *crtc, *enabled = NULL;
2251
2252         if (IS_I945GM(dev_priv))
2253                 wm_info = &i945_wm_info;
2254         else if (!IS_GEN2(dev_priv))
2255                 wm_info = &i915_wm_info;
2256         else
2257                 wm_info = &i830_a_wm_info;
2258
2259         fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
2260         crtc = intel_get_crtc_for_plane(dev_priv, 0);
2261         if (intel_crtc_active(crtc)) {
2262                 const struct drm_display_mode *adjusted_mode =
2263                         &crtc->config->base.adjusted_mode;
2264                 const struct drm_framebuffer *fb =
2265                         crtc->base.primary->state->fb;
2266                 int cpp;
2267
2268                 if (IS_GEN2(dev_priv))
2269                         cpp = 4;
2270                 else
2271                         cpp = fb->format->cpp[0];
2272
2273                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2274                                                wm_info, fifo_size, cpp,
2275                                                pessimal_latency_ns);
2276                 enabled = crtc;
2277         } else {
2278                 planea_wm = fifo_size - wm_info->guard_size;
2279                 if (planea_wm > (long)wm_info->max_wm)
2280                         planea_wm = wm_info->max_wm;
2281         }
2282
2283         if (IS_GEN2(dev_priv))
2284                 wm_info = &i830_bc_wm_info;
2285
2286         fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
2287         crtc = intel_get_crtc_for_plane(dev_priv, 1);
2288         if (intel_crtc_active(crtc)) {
2289                 const struct drm_display_mode *adjusted_mode =
2290                         &crtc->config->base.adjusted_mode;
2291                 const struct drm_framebuffer *fb =
2292                         crtc->base.primary->state->fb;
2293                 int cpp;
2294
2295                 if (IS_GEN2(dev_priv))
2296                         cpp = 4;
2297                 else
2298                         cpp = fb->format->cpp[0];
2299
2300                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2301                                                wm_info, fifo_size, cpp,
2302                                                pessimal_latency_ns);
2303                 if (enabled == NULL)
2304                         enabled = crtc;
2305                 else
2306                         enabled = NULL;
2307         } else {
2308                 planeb_wm = fifo_size - wm_info->guard_size;
2309                 if (planeb_wm > (long)wm_info->max_wm)
2310                         planeb_wm = wm_info->max_wm;
2311         }
2312
2313         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2314
2315         if (IS_I915GM(dev_priv) && enabled) {
2316                 struct drm_i915_gem_object *obj;
2317
2318                 obj = intel_fb_obj(enabled->base.primary->state->fb);
2319
2320                 /* self-refresh seems busted with untiled */
2321                 if (!i915_gem_object_is_tiled(obj))
2322                         enabled = NULL;
2323         }
2324
2325         /*
2326          * Overlay gets an aggressive default since video jitter is bad.
2327          */
2328         cwm = 2;
2329
2330         /* Play safe and disable self-refresh before adjusting watermarks. */
2331         intel_set_memory_cxsr(dev_priv, false);
2332
2333         /* Calc sr entries for one plane configs */
2334         if (HAS_FW_BLC(dev_priv) && enabled) {
2335                 /* self-refresh has much higher latency */
2336                 static const int sr_latency_ns = 6000;
2337                 const struct drm_display_mode *adjusted_mode =
2338                         &enabled->config->base.adjusted_mode;
2339                 const struct drm_framebuffer *fb =
2340                         enabled->base.primary->state->fb;
2341                 int clock = adjusted_mode->crtc_clock;
2342                 int htotal = adjusted_mode->crtc_htotal;
2343                 int hdisplay = enabled->config->pipe_src_w;
2344                 int cpp;
2345                 int entries;
2346
2347                 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2348                         cpp = 4;
2349                 else
2350                         cpp = fb->format->cpp[0];
2351
2352                 entries = intel_wm_method2(clock, htotal, hdisplay, cpp,
2353                                            sr_latency_ns / 100);
2354                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
2355                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
2356                 srwm = wm_info->fifo_size - entries;
2357                 if (srwm < 0)
2358                         srwm = 1;
2359
2360                 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
2361                         I915_WRITE(FW_BLC_SELF,
2362                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
2363                 else
2364                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
2365         }
2366
2367         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2368                       planea_wm, planeb_wm, cwm, srwm);
2369
2370         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2371         fwater_hi = (cwm & 0x1f);
2372
2373         /* Set request length to 8 cachelines per fetch */
2374         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2375         fwater_hi = fwater_hi | (1 << 8);
2376
2377         I915_WRITE(FW_BLC, fwater_lo);
2378         I915_WRITE(FW_BLC2, fwater_hi);
2379
2380         if (enabled)
2381                 intel_set_memory_cxsr(dev_priv, true);
2382 }
2383
2384 static void i845_update_wm(struct intel_crtc *unused_crtc)
2385 {
2386         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2387         struct intel_crtc *crtc;
2388         const struct drm_display_mode *adjusted_mode;
2389         uint32_t fwater_lo;
2390         int planea_wm;
2391
2392         crtc = single_enabled_crtc(dev_priv);
2393         if (crtc == NULL)
2394                 return;
2395
2396         adjusted_mode = &crtc->config->base.adjusted_mode;
2397         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2398                                        &i845_wm_info,
2399                                        dev_priv->display.get_fifo_size(dev_priv, 0),
2400                                        4, pessimal_latency_ns);
2401         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2402         fwater_lo |= (3<<8) | planea_wm;
2403
2404         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2405
2406         I915_WRITE(FW_BLC, fwater_lo);
2407 }
2408
2409 /* latency must be in 0.1us units. */
2410 static unsigned int ilk_wm_method1(unsigned int pixel_rate,
2411                                    unsigned int cpp,
2412                                    unsigned int latency)
2413 {
2414         unsigned int ret;
2415
2416         ret = intel_wm_method1(pixel_rate, cpp, latency);
2417         ret = DIV_ROUND_UP(ret, 64) + 2;
2418
2419         return ret;
2420 }
2421
2422 /* latency must be in 0.1us units. */
2423 static unsigned int ilk_wm_method2(unsigned int pixel_rate,
2424                                    unsigned int htotal,
2425                                    unsigned int width,
2426                                    unsigned int cpp,
2427                                    unsigned int latency)
2428 {
2429         unsigned int ret;
2430
2431         ret = intel_wm_method2(pixel_rate, htotal,
2432                                width, cpp, latency);
2433         ret = DIV_ROUND_UP(ret, 64) + 2;
2434
2435         return ret;
2436 }
2437
2438 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2439                            uint8_t cpp)
2440 {
2441         /*
2442          * Neither of these should be possible since this function shouldn't be
2443          * called if the CRTC is off or the plane is invisible.  But let's be
2444          * extra paranoid to avoid a potential divide-by-zero if we screw up
2445          * elsewhere in the driver.
2446          */
2447         if (WARN_ON(!cpp))
2448                 return 0;
2449         if (WARN_ON(!horiz_pixels))
2450                 return 0;
2451
2452         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
2453 }
2454
2455 struct ilk_wm_maximums {
2456         uint16_t pri;
2457         uint16_t spr;
2458         uint16_t cur;
2459         uint16_t fbc;
2460 };
2461
2462 /*
2463  * For both WM_PIPE and WM_LP.
2464  * mem_value must be in 0.1us units.
2465  */
2466 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
2467                                    const struct intel_plane_state *pstate,
2468                                    uint32_t mem_value,
2469                                    bool is_lp)
2470 {
2471         uint32_t method1, method2;
2472         int cpp;
2473
2474         if (!intel_wm_plane_visible(cstate, pstate))
2475                 return 0;
2476
2477         cpp = pstate->base.fb->format->cpp[0];
2478
2479         method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
2480
2481         if (!is_lp)
2482                 return method1;
2483
2484         method2 = ilk_wm_method2(cstate->pixel_rate,
2485                                  cstate->base.adjusted_mode.crtc_htotal,
2486                                  drm_rect_width(&pstate->base.dst),
2487                                  cpp, mem_value);
2488
2489         return min(method1, method2);
2490 }
2491
2492 /*
2493  * For both WM_PIPE and WM_LP.
2494  * mem_value must be in 0.1us units.
2495  */
2496 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
2497                                    const struct intel_plane_state *pstate,
2498                                    uint32_t mem_value)
2499 {
2500         uint32_t method1, method2;
2501         int cpp;
2502
2503         if (!intel_wm_plane_visible(cstate, pstate))
2504                 return 0;
2505
2506         cpp = pstate->base.fb->format->cpp[0];
2507
2508         method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
2509         method2 = ilk_wm_method2(cstate->pixel_rate,
2510                                  cstate->base.adjusted_mode.crtc_htotal,
2511                                  drm_rect_width(&pstate->base.dst),
2512                                  cpp, mem_value);
2513         return min(method1, method2);
2514 }
2515
2516 /*
2517  * For both WM_PIPE and WM_LP.
2518  * mem_value must be in 0.1us units.
2519  */
2520 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
2521                                    const struct intel_plane_state *pstate,
2522                                    uint32_t mem_value)
2523 {
2524         int cpp;
2525
2526         if (!intel_wm_plane_visible(cstate, pstate))
2527                 return 0;
2528
2529         cpp = pstate->base.fb->format->cpp[0];
2530
2531         return ilk_wm_method2(cstate->pixel_rate,
2532                               cstate->base.adjusted_mode.crtc_htotal,
2533                               pstate->base.crtc_w, cpp, mem_value);
2534 }
2535
2536 /* Only for WM_LP. */
2537 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
2538                                    const struct intel_plane_state *pstate,
2539                                    uint32_t pri_val)
2540 {
2541         int cpp;
2542
2543         if (!intel_wm_plane_visible(cstate, pstate))
2544                 return 0;
2545
2546         cpp = pstate->base.fb->format->cpp[0];
2547
2548         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
2549 }
2550
2551 static unsigned int
2552 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
2553 {
2554         if (INTEL_GEN(dev_priv) >= 8)
2555                 return 3072;
2556         else if (INTEL_GEN(dev_priv) >= 7)
2557                 return 768;
2558         else
2559                 return 512;
2560 }
2561
2562 static unsigned int
2563 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
2564                      int level, bool is_sprite)
2565 {
2566         if (INTEL_GEN(dev_priv) >= 8)
2567                 /* BDW primary/sprite plane watermarks */
2568                 return level == 0 ? 255 : 2047;
2569         else if (INTEL_GEN(dev_priv) >= 7)
2570                 /* IVB/HSW primary/sprite plane watermarks */
2571                 return level == 0 ? 127 : 1023;
2572         else if (!is_sprite)
2573                 /* ILK/SNB primary plane watermarks */
2574                 return level == 0 ? 127 : 511;
2575         else
2576                 /* ILK/SNB sprite plane watermarks */
2577                 return level == 0 ? 63 : 255;
2578 }
2579
2580 static unsigned int
2581 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
2582 {
2583         if (INTEL_GEN(dev_priv) >= 7)
2584                 return level == 0 ? 63 : 255;
2585         else
2586                 return level == 0 ? 31 : 63;
2587 }
2588
2589 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
2590 {
2591         if (INTEL_GEN(dev_priv) >= 8)
2592                 return 31;
2593         else
2594                 return 15;
2595 }
2596
2597 /* Calculate the maximum primary/sprite plane watermark */
2598 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2599                                      int level,
2600                                      const struct intel_wm_config *config,
2601                                      enum intel_ddb_partitioning ddb_partitioning,
2602                                      bool is_sprite)
2603 {
2604         struct drm_i915_private *dev_priv = to_i915(dev);
2605         unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
2606
2607         /* if sprites aren't enabled, sprites get nothing */
2608         if (is_sprite && !config->sprites_enabled)
2609                 return 0;
2610
2611         /* HSW allows LP1+ watermarks even with multiple pipes */
2612         if (level == 0 || config->num_pipes_active > 1) {
2613                 fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
2614
2615                 /*
2616                  * For some reason the non self refresh
2617                  * FIFO size is only half of the self
2618                  * refresh FIFO size on ILK/SNB.
2619                  */
2620                 if (INTEL_GEN(dev_priv) <= 6)
2621                         fifo_size /= 2;
2622         }
2623
2624         if (config->sprites_enabled) {
2625                 /* level 0 is always calculated with 1:1 split */
2626                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2627                         if (is_sprite)
2628                                 fifo_size *= 5;
2629                         fifo_size /= 6;
2630                 } else {
2631                         fifo_size /= 2;
2632                 }
2633         }
2634
2635         /* clamp to max that the registers can hold */
2636         return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
2637 }
2638
2639 /* Calculate the maximum cursor plane watermark */
2640 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2641                                       int level,
2642                                       const struct intel_wm_config *config)
2643 {
2644         /* HSW LP1+ watermarks w/ multiple pipes */
2645         if (level > 0 && config->num_pipes_active > 1)
2646                 return 64;
2647
2648         /* otherwise just report max that registers can hold */
2649         return ilk_cursor_wm_reg_max(to_i915(dev), level);
2650 }
2651
2652 static void ilk_compute_wm_maximums(const struct drm_device *dev,
2653                                     int level,
2654                                     const struct intel_wm_config *config,
2655                                     enum intel_ddb_partitioning ddb_partitioning,
2656                                     struct ilk_wm_maximums *max)
2657 {
2658         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2659         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2660         max->cur = ilk_cursor_wm_max(dev, level, config);
2661         max->fbc = ilk_fbc_wm_reg_max(to_i915(dev));
2662 }
2663
2664 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
2665                                         int level,
2666                                         struct ilk_wm_maximums *max)
2667 {
2668         max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
2669         max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
2670         max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
2671         max->fbc = ilk_fbc_wm_reg_max(dev_priv);
2672 }
2673
2674 static bool ilk_validate_wm_level(int level,
2675                                   const struct ilk_wm_maximums *max,
2676                                   struct intel_wm_level *result)
2677 {
2678         bool ret;
2679
2680         /* already determined to be invalid? */
2681         if (!result->enable)
2682                 return false;
2683
2684         result->enable = result->pri_val <= max->pri &&
2685                          result->spr_val <= max->spr &&
2686                          result->cur_val <= max->cur;
2687
2688         ret = result->enable;
2689
2690         /*
2691          * HACK until we can pre-compute everything,
2692          * and thus fail gracefully if LP0 watermarks
2693          * are exceeded...
2694          */
2695         if (level == 0 && !result->enable) {
2696                 if (result->pri_val > max->pri)
2697                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2698                                       level, result->pri_val, max->pri);
2699                 if (result->spr_val > max->spr)
2700                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2701                                       level, result->spr_val, max->spr);
2702                 if (result->cur_val > max->cur)
2703                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2704                                       level, result->cur_val, max->cur);
2705
2706                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2707                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2708                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2709                 result->enable = true;
2710         }
2711
2712         return ret;
2713 }
2714
2715 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2716                                  const struct intel_crtc *intel_crtc,
2717                                  int level,
2718                                  struct intel_crtc_state *cstate,
2719                                  struct intel_plane_state *pristate,
2720                                  struct intel_plane_state *sprstate,
2721                                  struct intel_plane_state *curstate,
2722                                  struct intel_wm_level *result)
2723 {
2724         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2725         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2726         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2727
2728         /* WM1+ latency values stored in 0.5us units */
2729         if (level > 0) {
2730                 pri_latency *= 5;
2731                 spr_latency *= 5;
2732                 cur_latency *= 5;
2733         }
2734
2735         if (pristate) {
2736                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2737                                                      pri_latency, level);
2738                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2739         }
2740
2741         if (sprstate)
2742                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2743
2744         if (curstate)
2745                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2746
2747         result->enable = true;
2748 }
2749
2750 static uint32_t
2751 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2752 {
2753         const struct intel_atomic_state *intel_state =
2754                 to_intel_atomic_state(cstate->base.state);
2755         const struct drm_display_mode *adjusted_mode =
2756                 &cstate->base.adjusted_mode;
2757         u32 linetime, ips_linetime;
2758
2759         if (!cstate->base.active)
2760                 return 0;
2761         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2762                 return 0;
2763         if (WARN_ON(intel_state->cdclk.logical.cdclk == 0))
2764                 return 0;
2765
2766         /* The WM are computed with base on how long it takes to fill a single
2767          * row at the given clock rate, multiplied by 8.
2768          * */
2769         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2770                                      adjusted_mode->crtc_clock);
2771         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2772                                          intel_state->cdclk.logical.cdclk);
2773
2774         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2775                PIPE_WM_LINETIME_TIME(linetime);
2776 }
2777
2778 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2779                                   uint16_t wm[8])
2780 {
2781         if (INTEL_GEN(dev_priv) >= 9) {
2782                 uint32_t val;
2783                 int ret, i;
2784                 int level, max_level = ilk_wm_max_level(dev_priv);
2785
2786                 /* read the first set of memory latencies[0:3] */
2787                 val = 0; /* data0 to be programmed to 0 for first set */
2788                 mutex_lock(&dev_priv->rps.hw_lock);
2789                 ret = sandybridge_pcode_read(dev_priv,
2790                                              GEN9_PCODE_READ_MEM_LATENCY,
2791                                              &val);
2792                 mutex_unlock(&dev_priv->rps.hw_lock);
2793
2794                 if (ret) {
2795                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2796                         return;
2797                 }
2798
2799                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2800                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2801                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2802                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2803                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2804                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2805                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2806
2807                 /* read the second set of memory latencies[4:7] */
2808                 val = 1; /* data0 to be programmed to 1 for second set */
2809                 mutex_lock(&dev_priv->rps.hw_lock);
2810                 ret = sandybridge_pcode_read(dev_priv,
2811                                              GEN9_PCODE_READ_MEM_LATENCY,
2812                                              &val);
2813                 mutex_unlock(&dev_priv->rps.hw_lock);
2814                 if (ret) {
2815                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2816                         return;
2817                 }
2818
2819                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2820                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2821                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2822                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2823                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2824                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2825                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2826
2827                 /*
2828                  * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2829                  * need to be disabled. We make sure to sanitize the values out
2830                  * of the punit to satisfy this requirement.
2831                  */
2832                 for (level = 1; level <= max_level; level++) {
2833                         if (wm[level] == 0) {
2834                                 for (i = level + 1; i <= max_level; i++)
2835                                         wm[i] = 0;
2836                                 break;
2837                         }
2838                 }
2839
2840                 /*
2841                  * WaWmMemoryReadLatency:skl+,glk
2842                  *
2843                  * punit doesn't take into account the read latency so we need
2844                  * to add 2us to the various latency levels we retrieve from the
2845                  * punit when level 0 response data us 0us.
2846                  */
2847                 if (wm[0] == 0) {
2848                         wm[0] += 2;
2849                         for (level = 1; level <= max_level; level++) {
2850                                 if (wm[level] == 0)
2851                                         break;
2852                                 wm[level] += 2;
2853                         }
2854                 }
2855
2856         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2857                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2858
2859                 wm[0] = (sskpd >> 56) & 0xFF;
2860                 if (wm[0] == 0)
2861                         wm[0] = sskpd & 0xF;
2862                 wm[1] = (sskpd >> 4) & 0xFF;
2863                 wm[2] = (sskpd >> 12) & 0xFF;
2864                 wm[3] = (sskpd >> 20) & 0x1FF;
2865                 wm[4] = (sskpd >> 32) & 0x1FF;
2866         } else if (INTEL_GEN(dev_priv) >= 6) {
2867                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2868
2869                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2870                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2871                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2872                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2873         } else if (INTEL_GEN(dev_priv) >= 5) {
2874                 uint32_t mltr = I915_READ(MLTR_ILK);
2875
2876                 /* ILK primary LP0 latency is 700 ns */
2877                 wm[0] = 7;
2878                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2879                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2880         } else {
2881                 MISSING_CASE(INTEL_DEVID(dev_priv));
2882         }
2883 }
2884
2885 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2886                                        uint16_t wm[5])
2887 {
2888         /* ILK sprite LP0 latency is 1300 ns */
2889         if (IS_GEN5(dev_priv))
2890                 wm[0] = 13;
2891 }
2892
2893 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2894                                        uint16_t wm[5])
2895 {
2896         /* ILK cursor LP0 latency is 1300 ns */
2897         if (IS_GEN5(dev_priv))
2898                 wm[0] = 13;
2899
2900         /* WaDoubleCursorLP3Latency:ivb */
2901         if (IS_IVYBRIDGE(dev_priv))
2902                 wm[3] *= 2;
2903 }
2904
2905 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2906 {
2907         /* how many WM levels are we expecting */
2908         if (INTEL_GEN(dev_priv) >= 9)
2909                 return 7;
2910         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2911                 return 4;
2912         else if (INTEL_GEN(dev_priv) >= 6)
2913                 return 3;
2914         else
2915                 return 2;
2916 }
2917
2918 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2919                                    const char *name,
2920                                    const uint16_t wm[8])
2921 {
2922         int level, max_level = ilk_wm_max_level(dev_priv);
2923
2924         for (level = 0; level <= max_level; level++) {
2925                 unsigned int latency = wm[level];
2926
2927                 if (latency == 0) {
2928                         DRM_ERROR("%s WM%d latency not provided\n",
2929                                   name, level);
2930                         continue;
2931                 }
2932
2933                 /*
2934                  * - latencies are in us on gen9.
2935                  * - before then, WM1+ latency values are in 0.5us units
2936                  */
2937                 if (INTEL_GEN(dev_priv) >= 9)
2938                         latency *= 10;
2939                 else if (level > 0)
2940                         latency *= 5;
2941
2942                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2943                               name, level, wm[level],
2944                               latency / 10, latency % 10);
2945         }
2946 }
2947
2948 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2949                                     uint16_t wm[5], uint16_t min)
2950 {
2951         int level, max_level = ilk_wm_max_level(dev_priv);
2952
2953         if (wm[0] >= min)
2954                 return false;
2955
2956         wm[0] = max(wm[0], min);
2957         for (level = 1; level <= max_level; level++)
2958                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2959
2960         return true;
2961 }
2962
2963 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
2964 {
2965         bool changed;
2966
2967         /*
2968          * The BIOS provided WM memory latency values are often
2969          * inadequate for high resolution displays. Adjust them.
2970          */
2971         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2972                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2973                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2974
2975         if (!changed)
2976                 return;
2977
2978         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2979         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2980         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2981         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2982 }
2983
2984 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
2985 {
2986         intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
2987
2988         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2989                sizeof(dev_priv->wm.pri_latency));
2990         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2991                sizeof(dev_priv->wm.pri_latency));
2992
2993         intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
2994         intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
2995
2996         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2997         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2998         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2999
3000         if (IS_GEN6(dev_priv))
3001                 snb_wm_latency_quirk(dev_priv);
3002 }
3003
3004 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
3005 {
3006         intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
3007         intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
3008 }
3009
3010 static bool ilk_validate_pipe_wm(struct drm_device *dev,
3011                                  struct intel_pipe_wm *pipe_wm)
3012 {
3013         /* LP0 watermark maximums depend on this pipe alone */
3014         const struct intel_wm_config config = {
3015                 .num_pipes_active = 1,
3016                 .sprites_enabled = pipe_wm->sprites_enabled,
3017                 .sprites_scaled = pipe_wm->sprites_scaled,
3018         };
3019         struct ilk_wm_maximums max;
3020
3021         /* LP0 watermarks always use 1/2 DDB partitioning */
3022         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
3023
3024         /* At least LP0 must be valid */
3025         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
3026                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
3027                 return false;
3028         }
3029
3030         return true;
3031 }
3032
3033 /* Compute new watermarks for the pipe */
3034 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
3035 {
3036         struct drm_atomic_state *state = cstate->base.state;
3037         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3038         struct intel_pipe_wm *pipe_wm;
3039         struct drm_device *dev = state->dev;
3040         const struct drm_i915_private *dev_priv = to_i915(dev);
3041         struct intel_plane *intel_plane;
3042         struct intel_plane_state *pristate = NULL;
3043         struct intel_plane_state *sprstate = NULL;
3044         struct intel_plane_state *curstate = NULL;
3045         int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
3046         struct ilk_wm_maximums max;
3047
3048         pipe_wm = &cstate->wm.ilk.optimal;
3049
3050         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3051                 struct intel_plane_state *ps;
3052
3053                 ps = intel_atomic_get_existing_plane_state(state,
3054                                                            intel_plane);
3055                 if (!ps)
3056                         continue;
3057
3058                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
3059                         pristate = ps;
3060                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
3061                         sprstate = ps;
3062                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
3063                         curstate = ps;
3064         }
3065
3066         pipe_wm->pipe_enabled = cstate->base.active;
3067         if (sprstate) {
3068                 pipe_wm->sprites_enabled = sprstate->base.visible;
3069                 pipe_wm->sprites_scaled = sprstate->base.visible &&
3070                         (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
3071                          drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
3072         }
3073
3074         usable_level = max_level;
3075
3076         /* ILK/SNB: LP2+ watermarks only w/o sprites */
3077         if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
3078                 usable_level = 1;
3079
3080         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
3081         if (pipe_wm->sprites_scaled)
3082                 usable_level = 0;
3083
3084         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
3085                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
3086
3087         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
3088         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
3089
3090         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3091                 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
3092
3093         if (!ilk_validate_pipe_wm(dev, pipe_wm))
3094                 return -EINVAL;
3095
3096         ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
3097
3098         for (level = 1; level <= max_level; level++) {
3099                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
3100
3101                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
3102                                      pristate, sprstate, curstate, wm);
3103
3104                 /*
3105                  * Disable any watermark level that exceeds the
3106                  * register maximums since such watermarks are
3107                  * always invalid.
3108                  */
3109                 if (level > usable_level)
3110                         continue;
3111
3112                 if (ilk_validate_wm_level(level, &max, wm))
3113                         pipe_wm->wm[level] = *wm;
3114                 else
3115                         usable_level = level;
3116         }
3117
3118         return 0;
3119 }
3120
3121 /*
3122  * Build a set of 'intermediate' watermark values that satisfy both the old
3123  * state and the new state.  These can be programmed to the hardware
3124  * immediately.
3125  */
3126 static int ilk_compute_intermediate_wm(struct drm_device *dev,
3127                                        struct intel_crtc *intel_crtc,
3128                                        struct intel_crtc_state *newstate)
3129 {
3130         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
3131         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
3132         int level, max_level = ilk_wm_max_level(to_i915(dev));
3133
3134         /*
3135          * Start with the final, target watermarks, then combine with the
3136          * currently active watermarks to get values that are safe both before
3137          * and after the vblank.
3138          */
3139         *a = newstate->wm.ilk.optimal;
3140         a->pipe_enabled |= b->pipe_enabled;
3141         a->sprites_enabled |= b->sprites_enabled;
3142         a->sprites_scaled |= b->sprites_scaled;
3143
3144         for (level = 0; level <= max_level; level++) {
3145                 struct intel_wm_level *a_wm = &a->wm[level];
3146                 const struct intel_wm_level *b_wm = &b->wm[level];
3147
3148                 a_wm->enable &= b_wm->enable;
3149                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
3150                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
3151                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
3152                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
3153         }
3154
3155         /*
3156          * We need to make sure that these merged watermark values are
3157          * actually a valid configuration themselves.  If they're not,
3158          * there's no safe way to transition from the old state to
3159          * the new state, so we need to fail the atomic transaction.
3160          */
3161         if (!ilk_validate_pipe_wm(dev, a))
3162                 return -EINVAL;
3163
3164         /*
3165          * If our intermediate WM are identical to the final WM, then we can
3166          * omit the post-vblank programming; only update if it's different.
3167          */
3168         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) != 0)
3169                 newstate->wm.need_postvbl_update = true;
3170
3171         return 0;
3172 }
3173
3174 /*
3175  * Merge the watermarks from all active pipes for a specific level.
3176  */
3177 static void ilk_merge_wm_level(struct drm_device *dev,
3178                                int level,
3179                                struct intel_wm_level *ret_wm)
3180 {
3181         const struct intel_crtc *intel_crtc;
3182
3183         ret_wm->enable = true;
3184
3185         for_each_intel_crtc(dev, intel_crtc) {
3186                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
3187                 const struct intel_wm_level *wm = &active->wm[level];
3188
3189                 if (!active->pipe_enabled)
3190                         continue;
3191
3192                 /*
3193                  * The watermark values may have been used in the past,
3194                  * so we must maintain them in the registers for some
3195                  * time even if the level is now disabled.
3196                  */
3197                 if (!wm->enable)
3198                         ret_wm->enable = false;
3199
3200                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
3201                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
3202                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
3203                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
3204         }
3205 }
3206
3207 /*
3208  * Merge all low power watermarks for all active pipes.
3209  */
3210 static void ilk_wm_merge(struct drm_device *dev,
3211                          const struct intel_wm_config *config,
3212                          const struct ilk_wm_maximums *max,
3213                          struct intel_pipe_wm *merged)
3214 {
3215         struct drm_i915_private *dev_priv = to_i915(dev);
3216         int level, max_level = ilk_wm_max_level(dev_priv);
3217         int last_enabled_level = max_level;
3218
3219         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
3220         if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
3221             config->num_pipes_active > 1)
3222                 last_enabled_level = 0;
3223
3224         /* ILK: FBC WM must be disabled always */
3225         merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
3226
3227         /* merge each WM1+ level */
3228         for (level = 1; level <= max_level; level++) {
3229                 struct intel_wm_level *wm = &merged->wm[level];
3230
3231                 ilk_merge_wm_level(dev, level, wm);
3232
3233                 if (level > last_enabled_level)
3234                         wm->enable = false;
3235                 else if (!ilk_validate_wm_level(level, max, wm))
3236                         /* make sure all following levels get disabled */
3237                         last_enabled_level = level - 1;
3238
3239                 /*
3240                  * The spec says it is preferred to disable
3241                  * FBC WMs instead of disabling a WM level.
3242                  */
3243                 if (wm->fbc_val > max->fbc) {
3244                         if (wm->enable)
3245                                 merged->fbc_wm_enabled = false;
3246                         wm->fbc_val = 0;
3247                 }
3248         }
3249
3250         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
3251         /*
3252          * FIXME this is racy. FBC might get enabled later.
3253          * What we should check here is whether FBC can be
3254          * enabled sometime later.
3255          */
3256         if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
3257             intel_fbc_is_active(dev_priv)) {
3258                 for (level = 2; level <= max_level; level++) {
3259                         struct intel_wm_level *wm = &merged->wm[level];
3260
3261                         wm->enable = false;
3262                 }
3263         }
3264 }
3265
3266 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
3267 {
3268         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
3269         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
3270 }
3271
3272 /* The value we need to program into the WM_LPx latency field */
3273 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
3274 {
3275         struct drm_i915_private *dev_priv = to_i915(dev);
3276
3277         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3278                 return 2 * level;
3279         else
3280                 return dev_priv->wm.pri_latency[level];
3281 }
3282
3283 static void ilk_compute_wm_results(struct drm_device *dev,
3284                                    const struct intel_pipe_wm *merged,
3285                                    enum intel_ddb_partitioning partitioning,
3286                                    struct ilk_wm_values *results)
3287 {
3288         struct drm_i915_private *dev_priv = to_i915(dev);
3289         struct intel_crtc *intel_crtc;
3290         int level, wm_lp;
3291
3292         results->enable_fbc_wm = merged->fbc_wm_enabled;
3293         results->partitioning = partitioning;
3294
3295         /* LP1+ register values */
3296         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3297                 const struct intel_wm_level *r;
3298
3299                 level = ilk_wm_lp_to_level(wm_lp, merged);
3300
3301                 r = &merged->wm[level];
3302
3303                 /*
3304                  * Maintain the watermark values even if the level is
3305                  * disabled. Doing otherwise could cause underruns.
3306                  */
3307                 results->wm_lp[wm_lp - 1] =
3308                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
3309                         (r->pri_val << WM1_LP_SR_SHIFT) |
3310                         r->cur_val;
3311
3312                 if (r->enable)
3313                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
3314
3315                 if (INTEL_GEN(dev_priv) >= 8)
3316                         results->wm_lp[wm_lp - 1] |=
3317                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
3318                 else
3319                         results->wm_lp[wm_lp - 1] |=
3320                                 r->fbc_val << WM1_LP_FBC_SHIFT;
3321
3322                 /*
3323                  * Always set WM1S_LP_EN when spr_val != 0, even if the
3324                  * level is disabled. Doing otherwise could cause underruns.
3325                  */
3326                 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
3327                         WARN_ON(wm_lp != 1);
3328                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
3329                 } else
3330                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
3331         }
3332
3333         /* LP0 register values */
3334         for_each_intel_crtc(dev, intel_crtc) {
3335                 enum pipe pipe = intel_crtc->pipe;
3336                 const struct intel_wm_level *r =
3337                         &intel_crtc->wm.active.ilk.wm[0];
3338
3339                 if (WARN_ON(!r->enable))
3340                         continue;
3341
3342                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
3343
3344                 results->wm_pipe[pipe] =
3345                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
3346                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
3347                         r->cur_val;
3348         }
3349 }
3350
3351 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
3352  * case both are at the same level. Prefer r1 in case they're the same. */
3353 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
3354                                                   struct intel_pipe_wm *r1,
3355                                                   struct intel_pipe_wm *r2)
3356 {
3357         int level, max_level = ilk_wm_max_level(to_i915(dev));
3358         int level1 = 0, level2 = 0;
3359
3360         for (level = 1; level <= max_level; level++) {
3361                 if (r1->wm[level].enable)
3362                         level1 = level;
3363                 if (r2->wm[level].enable)
3364                         level2 = level;
3365         }
3366
3367         if (level1 == level2) {
3368                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
3369                         return r2;
3370                 else
3371                         return r1;
3372         } else if (level1 > level2) {
3373                 return r1;
3374         } else {
3375                 return r2;
3376         }
3377 }
3378
3379 /* dirty bits used to track which watermarks need changes */
3380 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
3381 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
3382 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
3383 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
3384 #define WM_DIRTY_FBC (1 << 24)
3385 #define WM_DIRTY_DDB (1 << 25)
3386
3387 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
3388                                          const struct ilk_wm_values *old,
3389                                          const struct ilk_wm_values *new)
3390 {
3391         unsigned int dirty = 0;
3392         enum pipe pipe;
3393         int wm_lp;
3394
3395         for_each_pipe(dev_priv, pipe) {
3396                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
3397                         dirty |= WM_DIRTY_LINETIME(pipe);
3398                         /* Must disable LP1+ watermarks too */
3399                         dirty |= WM_DIRTY_LP_ALL;
3400                 }
3401
3402                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
3403                         dirty |= WM_DIRTY_PIPE(pipe);
3404                         /* Must disable LP1+ watermarks too */
3405                         dirty |= WM_DIRTY_LP_ALL;
3406                 }
3407         }
3408
3409         if (old->enable_fbc_wm != new->enable_fbc_wm) {
3410                 dirty |= WM_DIRTY_FBC;
3411                 /* Must disable LP1+ watermarks too */
3412                 dirty |= WM_DIRTY_LP_ALL;
3413         }
3414
3415         if (old->partitioning != new->partitioning) {
3416                 dirty |= WM_DIRTY_DDB;
3417                 /* Must disable LP1+ watermarks too */
3418                 dirty |= WM_DIRTY_LP_ALL;
3419         }
3420
3421         /* LP1+ watermarks already deemed dirty, no need to continue */
3422         if (dirty & WM_DIRTY_LP_ALL)
3423                 return dirty;
3424
3425         /* Find the lowest numbered LP1+ watermark in need of an update... */
3426         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3427                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
3428                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
3429                         break;
3430         }
3431
3432         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
3433         for (; wm_lp <= 3; wm_lp++)
3434                 dirty |= WM_DIRTY_LP(wm_lp);
3435
3436         return dirty;
3437 }
3438
3439 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
3440                                unsigned int dirty)
3441 {
3442         struct ilk_wm_values *previous = &dev_priv->wm.hw;
3443         bool changed = false;
3444
3445         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
3446                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
3447                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
3448                 changed = true;
3449         }
3450         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
3451                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
3452                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
3453                 changed = true;
3454         }
3455         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
3456                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
3457                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
3458                 changed = true;
3459         }
3460
3461         /*
3462          * Don't touch WM1S_LP_EN here.
3463          * Doing so could cause underruns.
3464          */
3465
3466         return changed;
3467 }
3468
3469 /*
3470  * The spec says we shouldn't write when we don't need, because every write
3471  * causes WMs to be re-evaluated, expending some power.
3472  */
3473 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
3474                                 struct ilk_wm_values *results)
3475 {
3476         struct ilk_wm_values *previous = &dev_priv->wm.hw;
3477         unsigned int dirty;
3478         uint32_t val;
3479
3480         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
3481         if (!dirty)
3482                 return;
3483
3484         _ilk_disable_lp_wm(dev_priv, dirty);
3485
3486         if (dirty & WM_DIRTY_PIPE(PIPE_A))
3487                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
3488         if (dirty & WM_DIRTY_PIPE(PIPE_B))
3489                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
3490         if (dirty & WM_DIRTY_PIPE(PIPE_C))
3491                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
3492
3493         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
3494                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
3495         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
3496                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
3497         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
3498                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
3499
3500         if (dirty & WM_DIRTY_DDB) {
3501                 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3502                         val = I915_READ(WM_MISC);
3503                         if (results->partitioning == INTEL_DDB_PART_1_2)
3504                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
3505                         else
3506                                 val |= WM_MISC_DATA_PARTITION_5_6;
3507                         I915_WRITE(WM_MISC, val);
3508                 } else {
3509                         val = I915_READ(DISP_ARB_CTL2);
3510                         if (results->partitioning == INTEL_DDB_PART_1_2)
3511                                 val &= ~DISP_DATA_PARTITION_5_6;
3512                         else
3513                                 val |= DISP_DATA_PARTITION_5_6;
3514                         I915_WRITE(DISP_ARB_CTL2, val);
3515                 }
3516         }
3517
3518         if (dirty & WM_DIRTY_FBC) {
3519                 val = I915_READ(DISP_ARB_CTL);
3520                 if (results->enable_fbc_wm)
3521                         val &= ~DISP_FBC_WM_DIS;
3522                 else
3523                         val |= DISP_FBC_WM_DIS;
3524                 I915_WRITE(DISP_ARB_CTL, val);
3525         }
3526
3527         if (dirty & WM_DIRTY_LP(1) &&
3528             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
3529                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
3530
3531         if (INTEL_GEN(dev_priv) >= 7) {
3532                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
3533                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
3534                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
3535                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
3536         }
3537
3538         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
3539                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
3540         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
3541                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
3542         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
3543                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
3544
3545         dev_priv->wm.hw = *results;
3546 }
3547
3548 bool ilk_disable_lp_wm(struct drm_device *dev)
3549 {
3550         struct drm_i915_private *dev_priv = to_i915(dev);
3551
3552         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
3553 }
3554
3555 /*
3556  * FIXME: We still don't have the proper code detect if we need to apply the WA,
3557  * so assume we'll always need it in order to avoid underruns.
3558  */
3559 static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
3560 {
3561         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3562
3563         if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
3564                 return true;
3565
3566         return false;
3567 }
3568
3569 static bool
3570 intel_has_sagv(struct drm_i915_private *dev_priv)
3571 {
3572         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
3573             IS_CANNONLAKE(dev_priv))
3574                 return true;
3575
3576         if (IS_SKYLAKE(dev_priv) &&
3577             dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
3578                 return true;
3579
3580         return false;
3581 }
3582
3583 /*
3584  * SAGV dynamically adjusts the system agent voltage and clock frequencies
3585  * depending on power and performance requirements. The display engine access
3586  * to system memory is blocked during the adjustment time. Because of the
3587  * blocking time, having this enabled can cause full system hangs and/or pipe
3588  * underruns if we don't meet all of the following requirements:
3589  *
3590  *  - <= 1 pipe enabled
3591  *  - All planes can enable watermarks for latencies >= SAGV engine block time
3592  *  - We're not using an interlaced display configuration
3593  */
3594 int
3595 intel_enable_sagv(struct drm_i915_private *dev_priv)
3596 {
3597         int ret;
3598
3599         if (!intel_has_sagv(dev_priv))
3600                 return 0;
3601
3602         if (dev_priv->sagv_status == I915_SAGV_ENABLED)
3603                 return 0;
3604
3605         DRM_DEBUG_KMS("Enabling the SAGV\n");
3606         mutex_lock(&dev_priv->rps.hw_lock);
3607
3608         ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3609                                       GEN9_SAGV_ENABLE);
3610
3611         /* We don't need to wait for the SAGV when enabling */
3612         mutex_unlock(&dev_priv->rps.hw_lock);
3613
3614         /*
3615          * Some skl systems, pre-release machines in particular,
3616          * don't actually have an SAGV.
3617          */
3618         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3619                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3620                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3621                 return 0;
3622         } else if (ret < 0) {
3623                 DRM_ERROR("Failed to enable the SAGV\n");
3624                 return ret;
3625         }
3626
3627         dev_priv->sagv_status = I915_SAGV_ENABLED;
3628         return 0;
3629 }
3630
3631 int
3632 intel_disable_sagv(struct drm_i915_private *dev_priv)
3633 {
3634         int ret;
3635
3636         if (!intel_has_sagv(dev_priv))
3637                 return 0;
3638
3639         if (dev_priv->sagv_status == I915_SAGV_DISABLED)
3640                 return 0;
3641
3642         DRM_DEBUG_KMS("Disabling the SAGV\n");
3643         mutex_lock(&dev_priv->rps.hw_lock);
3644
3645         /* bspec says to keep retrying for at least 1 ms */
3646         ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3647                                 GEN9_SAGV_DISABLE,
3648                                 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
3649                                 1);
3650         mutex_unlock(&dev_priv->rps.hw_lock);
3651
3652         /*
3653          * Some skl systems, pre-release machines in particular,
3654          * don't actually have an SAGV.
3655          */
3656         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3657                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3658                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3659                 return 0;
3660         } else if (ret < 0) {
3661                 DRM_ERROR("Failed to disable the SAGV (%d)\n", ret);
3662                 return ret;
3663         }
3664
3665         dev_priv->sagv_status = I915_SAGV_DISABLED;
3666         return 0;
3667 }
3668
3669 bool intel_can_enable_sagv(struct drm_atomic_state *state)
3670 {
3671         struct drm_device *dev = state->dev;
3672         struct drm_i915_private *dev_priv = to_i915(dev);
3673         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3674         struct intel_crtc *crtc;
3675         struct intel_plane *plane;
3676         struct intel_crtc_state *cstate;
3677         enum pipe pipe;
3678         int level, latency;
3679         int sagv_block_time_us = IS_GEN9(dev_priv) ? 30 : 20;
3680
3681         if (!intel_has_sagv(dev_priv))
3682                 return false;
3683
3684         /*
3685          * SKL+ workaround: bspec recommends we disable the SAGV when we have
3686          * more then one pipe enabled
3687          *
3688          * If there are no active CRTCs, no additional checks need be performed
3689          */
3690         if (hweight32(intel_state->active_crtcs) == 0)
3691                 return true;
3692         else if (hweight32(intel_state->active_crtcs) > 1)
3693                 return false;
3694
3695         /* Since we're now guaranteed to only have one active CRTC... */
3696         pipe = ffs(intel_state->active_crtcs) - 1;
3697         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
3698         cstate = to_intel_crtc_state(crtc->base.state);
3699
3700         if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3701                 return false;
3702
3703         for_each_intel_plane_on_crtc(dev, crtc, plane) {
3704                 struct skl_plane_wm *wm =
3705                         &cstate->wm.skl.optimal.planes[plane->id];
3706
3707                 /* Skip this plane if it's not enabled */
3708                 if (!wm->wm[0].plane_en)
3709                         continue;
3710
3711                 /* Find the highest enabled wm level for this plane */
3712                 for (level = ilk_wm_max_level(dev_priv);
3713                      !wm->wm[level].plane_en; --level)
3714                      { }
3715
3716                 latency = dev_priv->wm.skl_latency[level];
3717
3718                 if (skl_needs_memory_bw_wa(intel_state) &&
3719                     plane->base.state->fb->modifier ==
3720                     I915_FORMAT_MOD_X_TILED)
3721                         latency += 15;
3722
3723                 /*
3724                  * If any of the planes on this pipe don't enable wm levels that
3725                  * incur memory latencies higher than sagv_block_time_us we
3726                  * can't enable the SAGV.
3727                  */
3728                 if (latency < sagv_block_time_us)
3729                         return false;
3730         }
3731
3732         return true;
3733 }
3734
3735 static void
3736 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3737                                    const struct intel_crtc_state *cstate,
3738                                    struct skl_ddb_entry *alloc, /* out */
3739                                    int *num_active /* out */)
3740 {
3741         struct drm_atomic_state *state = cstate->base.state;
3742         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3743         struct drm_i915_private *dev_priv = to_i915(dev);
3744         struct drm_crtc *for_crtc = cstate->base.crtc;
3745         unsigned int pipe_size, ddb_size;
3746         int nth_active_pipe;
3747
3748         if (WARN_ON(!state) || !cstate->base.active) {
3749                 alloc->start = 0;
3750                 alloc->end = 0;
3751                 *num_active = hweight32(dev_priv->active_crtcs);
3752                 return;
3753         }
3754
3755         if (intel_state->active_pipe_changes)
3756                 *num_active = hweight32(intel_state->active_crtcs);
3757         else
3758                 *num_active = hweight32(dev_priv->active_crtcs);
3759
3760         ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3761         WARN_ON(ddb_size == 0);
3762
3763         ddb_size -= 4; /* 4 blocks for bypass path allocation */
3764
3765         /*
3766          * If the state doesn't change the active CRTC's, then there's
3767          * no need to recalculate; the existing pipe allocation limits
3768          * should remain unchanged.  Note that we're safe from racing
3769          * commits since any racing commit that changes the active CRTC
3770          * list would need to grab _all_ crtc locks, including the one
3771          * we currently hold.
3772          */
3773         if (!intel_state->active_pipe_changes) {
3774                 /*
3775                  * alloc may be cleared by clear_intel_crtc_state,
3776                  * copy from old state to be sure
3777                  */
3778                 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
3779                 return;
3780         }
3781
3782         nth_active_pipe = hweight32(intel_state->active_crtcs &
3783                                     (drm_crtc_mask(for_crtc) - 1));
3784         pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3785         alloc->start = nth_active_pipe * ddb_size / *num_active;
3786         alloc->end = alloc->start + pipe_size;
3787 }
3788
3789 static unsigned int skl_cursor_allocation(int num_active)
3790 {
3791         if (num_active == 1)
3792                 return 32;
3793
3794         return 8;
3795 }
3796
3797 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3798 {
3799         entry->start = reg & 0x3ff;
3800         entry->end = (reg >> 16) & 0x3ff;
3801         if (entry->end)
3802                 entry->end += 1;
3803 }
3804
3805 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3806                           struct skl_ddb_allocation *ddb /* out */)
3807 {
3808         struct intel_crtc *crtc;
3809
3810         memset(ddb, 0, sizeof(*ddb));
3811
3812         for_each_intel_crtc(&dev_priv->drm, crtc) {
3813                 enum intel_display_power_domain power_domain;
3814                 enum plane_id plane_id;
3815                 enum pipe pipe = crtc->pipe;
3816
3817                 power_domain = POWER_DOMAIN_PIPE(pipe);
3818                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3819                         continue;
3820
3821                 for_each_plane_id_on_crtc(crtc, plane_id) {
3822                         u32 val;
3823
3824                         if (plane_id != PLANE_CURSOR)
3825                                 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
3826                         else
3827                                 val = I915_READ(CUR_BUF_CFG(pipe));
3828
3829                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
3830                 }
3831
3832                 intel_display_power_put(dev_priv, power_domain);
3833         }
3834 }
3835
3836 /*
3837  * Determines the downscale amount of a plane for the purposes of watermark calculations.
3838  * The bspec defines downscale amount as:
3839  *
3840  * """
3841  * Horizontal down scale amount = maximum[1, Horizontal source size /
3842  *                                           Horizontal destination size]
3843  * Vertical down scale amount = maximum[1, Vertical source size /
3844  *                                         Vertical destination size]
3845  * Total down scale amount = Horizontal down scale amount *
3846  *                           Vertical down scale amount
3847  * """
3848  *
3849  * Return value is provided in 16.16 fixed point form to retain fractional part.
3850  * Caller should take care of dividing & rounding off the value.
3851  */
3852 static uint_fixed_16_16_t
3853 skl_plane_downscale_amount(const struct intel_crtc_state *cstate,
3854                            const struct intel_plane_state *pstate)
3855 {
3856         struct intel_plane *plane = to_intel_plane(pstate->base.plane);
3857         uint32_t src_w, src_h, dst_w, dst_h;
3858         uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
3859         uint_fixed_16_16_t downscale_h, downscale_w;
3860
3861         if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
3862                 return u32_to_fixed16(0);
3863
3864         /* n.b., src is 16.16 fixed point, dst is whole integer */
3865         if (plane->id == PLANE_CURSOR) {
3866                 /*
3867                  * Cursors only support 0/180 degree rotation,
3868                  * hence no need to account for rotation here.
3869                  */
3870                 src_w = pstate->base.src_w >> 16;
3871                 src_h = pstate->base.src_h >> 16;
3872                 dst_w = pstate->base.crtc_w;
3873                 dst_h = pstate->base.crtc_h;
3874         } else {
3875                 /*
3876                  * Src coordinates are already rotated by 270 degrees for
3877                  * the 90/270 degree plane rotation cases (to match the
3878                  * GTT mapping), hence no need to account for rotation here.
3879                  */
3880                 src_w = drm_rect_width(&pstate->base.src) >> 16;
3881                 src_h = drm_rect_height(&pstate->base.src) >> 16;
3882                 dst_w = drm_rect_width(&pstate->base.dst);
3883                 dst_h = drm_rect_height(&pstate->base.dst);
3884         }
3885
3886         fp_w_ratio = div_fixed16(src_w, dst_w);
3887         fp_h_ratio = div_fixed16(src_h, dst_h);
3888         downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
3889         downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
3890
3891         return mul_fixed16(downscale_w, downscale_h);
3892 }
3893
3894 static uint_fixed_16_16_t
3895 skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
3896 {
3897         uint_fixed_16_16_t pipe_downscale = u32_to_fixed16(1);
3898
3899         if (!crtc_state->base.enable)
3900                 return pipe_downscale;
3901
3902         if (crtc_state->pch_pfit.enabled) {
3903                 uint32_t src_w, src_h, dst_w, dst_h;
3904                 uint32_t pfit_size = crtc_state->pch_pfit.size;
3905                 uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
3906                 uint_fixed_16_16_t downscale_h, downscale_w;
3907
3908                 src_w = crtc_state->pipe_src_w;
3909                 src_h = crtc_state->pipe_src_h;
3910                 dst_w = pfit_size >> 16;
3911                 dst_h = pfit_size & 0xffff;
3912
3913                 if (!dst_w || !dst_h)
3914                         return pipe_downscale;
3915
3916                 fp_w_ratio = div_fixed16(src_w, dst_w);
3917                 fp_h_ratio = div_fixed16(src_h, dst_h);
3918                 downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
3919                 downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
3920
3921                 pipe_downscale = mul_fixed16(downscale_w, downscale_h);
3922         }
3923
3924         return pipe_downscale;
3925 }
3926
3927 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
3928                                   struct intel_crtc_state *cstate)
3929 {
3930         struct drm_crtc_state *crtc_state = &cstate->base;
3931         struct drm_atomic_state *state = crtc_state->state;
3932         struct drm_plane *plane;
3933         const struct drm_plane_state *pstate;
3934         struct intel_plane_state *intel_pstate;
3935         int crtc_clock, dotclk;
3936         uint32_t pipe_max_pixel_rate;
3937         uint_fixed_16_16_t pipe_downscale;
3938         uint_fixed_16_16_t max_downscale = u32_to_fixed16(1);
3939
3940         if (!cstate->base.enable)
3941                 return 0;
3942
3943         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
3944                 uint_fixed_16_16_t plane_downscale;
3945                 uint_fixed_16_16_t fp_9_div_8 = div_fixed16(9, 8);
3946                 int bpp;
3947
3948                 if (!intel_wm_plane_visible(cstate,
3949                                             to_intel_plane_state(pstate)))
3950                         continue;
3951
3952                 if (WARN_ON(!pstate->fb))
3953                         return -EINVAL;
3954
3955                 intel_pstate = to_intel_plane_state(pstate);
3956                 plane_downscale = skl_plane_downscale_amount(cstate,
3957                                                              intel_pstate);
3958                 bpp = pstate->fb->format->cpp[0] * 8;
3959                 if (bpp == 64)
3960                         plane_downscale = mul_fixed16(plane_downscale,
3961                                                       fp_9_div_8);
3962
3963                 max_downscale = max_fixed16(plane_downscale, max_downscale);
3964         }
3965         pipe_downscale = skl_pipe_downscale_amount(cstate);
3966
3967         pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
3968
3969         crtc_clock = crtc_state->adjusted_mode.crtc_clock;
3970         dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
3971
3972         if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)))
3973                 dotclk *= 2;
3974
3975         pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
3976
3977         if (pipe_max_pixel_rate < crtc_clock) {
3978                 DRM_DEBUG_KMS("Max supported pixel clock with scaling exceeded\n");
3979                 return -EINVAL;
3980         }
3981
3982         return 0;
3983 }
3984
3985 static unsigned int
3986 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3987                              const struct drm_plane_state *pstate,
3988                              int y)
3989 {
3990         struct intel_plane *plane = to_intel_plane(pstate->plane);
3991         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3992         uint32_t data_rate;
3993         uint32_t width = 0, height = 0;
3994         struct drm_framebuffer *fb;
3995         u32 format;
3996         uint_fixed_16_16_t down_scale_amount;
3997
3998         if (!intel_pstate->base.visible)
3999                 return 0;
4000
4001         fb = pstate->fb;
4002         format = fb->format->format;
4003
4004         if (plane->id == PLANE_CURSOR)
4005                 return 0;
4006         if (y && format != DRM_FORMAT_NV12)
4007                 return 0;
4008
4009         /*
4010          * Src coordinates are already rotated by 270 degrees for
4011          * the 90/270 degree plane rotation cases (to match the
4012          * GTT mapping), hence no need to account for rotation here.
4013          */
4014         width = drm_rect_width(&intel_pstate->base.src) >> 16;
4015         height = drm_rect_height(&intel_pstate->base.src) >> 16;
4016
4017         /* for planar format */
4018         if (format == DRM_FORMAT_NV12) {
4019                 if (y)  /* y-plane data rate */
4020                         data_rate = width * height *
4021                                 fb->format->cpp[0];
4022                 else    /* uv-plane data rate */
4023                         data_rate = (width / 2) * (height / 2) *
4024                                 fb->format->cpp[1];
4025         } else {
4026                 /* for packed formats */
4027                 data_rate = width * height * fb->format->cpp[0];
4028         }
4029
4030         down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
4031
4032         return mul_round_up_u32_fixed16(data_rate, down_scale_amount);
4033 }
4034
4035 /*
4036  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
4037  * a 8192x4096@32bpp framebuffer:
4038  *   3 * 4096 * 8192  * 4 < 2^32
4039  */
4040 static unsigned int
4041 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
4042                                  unsigned *plane_data_rate,
4043                                  unsigned *plane_y_data_rate)
4044 {
4045         struct drm_crtc_state *cstate = &intel_cstate->base;
4046         struct drm_atomic_state *state = cstate->state;
4047         struct drm_plane *plane;
4048         const struct drm_plane_state *pstate;
4049         unsigned int total_data_rate = 0;
4050
4051         if (WARN_ON(!state))
4052                 return 0;
4053
4054         /* Calculate and cache data rate for each plane */
4055         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
4056                 enum plane_id plane_id = to_intel_plane(plane)->id;
4057                 unsigned int rate;
4058
4059                 /* packed/uv */
4060                 rate = skl_plane_relative_data_rate(intel_cstate,
4061                                                     pstate, 0);
4062                 plane_data_rate[plane_id] = rate;
4063
4064                 total_data_rate += rate;
4065
4066                 /* y-plane */
4067                 rate = skl_plane_relative_data_rate(intel_cstate,
4068                                                     pstate, 1);
4069                 plane_y_data_rate[plane_id] = rate;
4070
4071                 total_data_rate += rate;
4072         }
4073
4074         return total_data_rate;
4075 }
4076
4077 static uint16_t
4078 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
4079                   const int y)
4080 {
4081         struct drm_framebuffer *fb = pstate->fb;
4082         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
4083         uint32_t src_w, src_h;
4084         uint32_t min_scanlines = 8;
4085         uint8_t plane_bpp;
4086
4087         if (WARN_ON(!fb))
4088                 return 0;
4089
4090         /* For packed formats, no y-plane, return 0 */
4091         if (y && fb->format->format != DRM_FORMAT_NV12)
4092                 return 0;
4093
4094         /* For Non Y-tile return 8-blocks */
4095         if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
4096             fb->modifier != I915_FORMAT_MOD_Yf_TILED &&
4097             fb->modifier != I915_FORMAT_MOD_Y_TILED_CCS &&
4098             fb->modifier != I915_FORMAT_MOD_Yf_TILED_CCS)
4099                 return 8;
4100
4101         /*
4102          * Src coordinates are already rotated by 270 degrees for
4103          * the 90/270 degree plane rotation cases (to match the
4104          * GTT mapping), hence no need to account for rotation here.
4105          */
4106         src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
4107         src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
4108
4109         /* Halve UV plane width and height for NV12 */
4110         if (fb->format->format == DRM_FORMAT_NV12 && !y) {
4111                 src_w /= 2;
4112                 src_h /= 2;
4113         }
4114
4115         if (fb->format->format == DRM_FORMAT_NV12 && !y)
4116                 plane_bpp = fb->format->cpp[1];
4117         else
4118                 plane_bpp = fb->format->cpp[0];
4119
4120         if (drm_rotation_90_or_270(pstate->rotation)) {
4121                 switch (plane_bpp) {
4122                 case 1:
4123                         min_scanlines = 32;
4124                         break;
4125                 case 2:
4126                         min_scanlines = 16;
4127                         break;
4128                 case 4:
4129                         min_scanlines = 8;
4130                         break;
4131                 case 8:
4132                         min_scanlines = 4;
4133                         break;
4134                 default:
4135                         WARN(1, "Unsupported pixel depth %u for rotation",
4136                              plane_bpp);
4137                         min_scanlines = 32;
4138                 }
4139         }
4140
4141         return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
4142 }
4143
4144 static void
4145 skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
4146                  uint16_t *minimum, uint16_t *y_minimum)
4147 {
4148         const struct drm_plane_state *pstate;
4149         struct drm_plane *plane;
4150
4151         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
4152                 enum plane_id plane_id = to_intel_plane(plane)->id;
4153
4154                 if (plane_id == PLANE_CURSOR)
4155                         continue;
4156
4157                 if (!pstate->visible)
4158                         continue;
4159
4160                 minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
4161                 y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
4162         }
4163
4164         minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
4165 }
4166
4167 static int
4168 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
4169                       struct skl_ddb_allocation *ddb /* out */)
4170 {
4171         struct drm_atomic_state *state = cstate->base.state;
4172         struct drm_crtc *crtc = cstate->base.crtc;
4173         struct drm_device *dev = crtc->dev;
4174         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4175         enum pipe pipe = intel_crtc->pipe;
4176         struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
4177         uint16_t alloc_size, start;
4178         uint16_t minimum[I915_MAX_PLANES] = {};
4179         uint16_t y_minimum[I915_MAX_PLANES] = {};
4180         unsigned int total_data_rate;
4181         enum plane_id plane_id;
4182         int num_active;
4183         unsigned plane_data_rate[I915_MAX_PLANES] = {};
4184         unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
4185         uint16_t total_min_blocks = 0;
4186
4187         /* Clear the partitioning for disabled planes. */
4188         memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
4189         memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
4190
4191         if (WARN_ON(!state))
4192                 return 0;
4193
4194         if (!cstate->base.active) {
4195                 alloc->start = alloc->end = 0;
4196                 return 0;
4197         }
4198
4199         skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
4200         alloc_size = skl_ddb_entry_size(alloc);
4201         if (alloc_size == 0)
4202                 return 0;
4203
4204         skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
4205
4206         /*
4207          * 1. Allocate the mininum required blocks for each active plane
4208          * and allocate the cursor, it doesn't require extra allocation
4209          * proportional to the data rate.
4210          */
4211
4212         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4213                 total_min_blocks += minimum[plane_id];
4214                 total_min_blocks += y_minimum[plane_id];
4215         }
4216
4217         if (total_min_blocks > alloc_size) {
4218                 DRM_DEBUG_KMS("Requested display configuration exceeds system DDB limitations");
4219                 DRM_DEBUG_KMS("minimum required %d/%d\n", total_min_blocks,
4220                                                         alloc_size);
4221                 return -EINVAL;
4222         }
4223
4224         alloc_size -= total_min_blocks;
4225         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
4226         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
4227
4228         /*
4229          * 2. Distribute the remaining space in proportion to the amount of
4230          * data each plane needs to fetch from memory.
4231          *
4232          * FIXME: we may not allocate every single block here.
4233          */
4234         total_data_rate = skl_get_total_relative_data_rate(cstate,
4235                                                            plane_data_rate,
4236                                                            plane_y_data_rate);
4237         if (total_data_rate == 0)
4238                 return 0;
4239
4240         start = alloc->start;
4241         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4242                 unsigned int data_rate, y_data_rate;
4243                 uint16_t plane_blocks, y_plane_blocks = 0;
4244
4245                 if (plane_id == PLANE_CURSOR)
4246                         continue;
4247
4248                 data_rate = plane_data_rate[plane_id];
4249
4250                 /*
4251                  * allocation for (packed formats) or (uv-plane part of planar format):
4252                  * promote the expression to 64 bits to avoid overflowing, the
4253                  * result is < available as data_rate / total_data_rate < 1
4254                  */
4255                 plane_blocks = minimum[plane_id];
4256                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
4257                                         total_data_rate);
4258
4259                 /* Leave disabled planes at (0,0) */
4260                 if (data_rate) {
4261                         ddb->plane[pipe][plane_id].start = start;
4262                         ddb->plane[pipe][plane_id].end = start + plane_blocks;
4263                 }
4264
4265                 start += plane_blocks;
4266
4267                 /*
4268                  * allocation for y_plane part of planar format:
4269                  */
4270                 y_data_rate = plane_y_data_rate[plane_id];
4271
4272                 y_plane_blocks = y_minimum[plane_id];
4273                 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
4274                                         total_data_rate);
4275
4276                 if (y_data_rate) {
4277                         ddb->y_plane[pipe][plane_id].start = start;
4278                         ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
4279                 }
4280
4281                 start += y_plane_blocks;
4282         }
4283
4284         return 0;
4285 }
4286
4287 /*
4288  * The max latency should be 257 (max the punit can code is 255 and we add 2us
4289  * for the read latency) and cpp should always be <= 8, so that
4290  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
4291  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
4292 */
4293 static uint_fixed_16_16_t
4294 skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
4295                uint8_t cpp, uint32_t latency)
4296 {
4297         uint32_t wm_intermediate_val;
4298         uint_fixed_16_16_t ret;
4299
4300         if (latency == 0)
4301                 return FP_16_16_MAX;
4302
4303         wm_intermediate_val = latency * pixel_rate * cpp;
4304         ret = div_fixed16(wm_intermediate_val, 1000 * 512);
4305
4306         if (INTEL_GEN(dev_priv) >= 10)
4307                 ret = add_fixed16_u32(ret, 1);
4308
4309         return ret;
4310 }
4311
4312 static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
4313                         uint32_t pipe_htotal,
4314                         uint32_t latency,
4315                         uint_fixed_16_16_t plane_blocks_per_line)
4316 {
4317         uint32_t wm_intermediate_val;
4318         uint_fixed_16_16_t ret;
4319
4320         if (latency == 0)
4321                 return FP_16_16_MAX;
4322
4323         wm_intermediate_val = latency * pixel_rate;
4324         wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val,
4325                                            pipe_htotal * 1000);
4326         ret = mul_u32_fixed16(wm_intermediate_val, plane_blocks_per_line);
4327         return ret;
4328 }
4329
4330 static uint_fixed_16_16_t
4331 intel_get_linetime_us(struct intel_crtc_state *cstate)
4332 {
4333         uint32_t pixel_rate;
4334         uint32_t crtc_htotal;
4335         uint_fixed_16_16_t linetime_us;
4336
4337         if (!cstate->base.active)
4338                 return u32_to_fixed16(0);
4339
4340         pixel_rate = cstate->pixel_rate;
4341
4342         if (WARN_ON(pixel_rate == 0))
4343                 return u32_to_fixed16(0);
4344
4345         crtc_htotal = cstate->base.adjusted_mode.crtc_htotal;
4346         linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
4347
4348         return linetime_us;
4349 }
4350
4351 static uint32_t
4352 skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
4353                               const struct intel_plane_state *pstate)
4354 {
4355         uint64_t adjusted_pixel_rate;
4356         uint_fixed_16_16_t downscale_amount;
4357
4358         /* Shouldn't reach here on disabled planes... */
4359         if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
4360                 return 0;
4361
4362         /*
4363          * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
4364          * with additional adjustments for plane-specific scaling.
4365          */
4366         adjusted_pixel_rate = cstate->pixel_rate;
4367         downscale_amount = skl_plane_downscale_amount(cstate, pstate);
4368
4369         return mul_round_up_u32_fixed16(adjusted_pixel_rate,
4370                                             downscale_amount);
4371 }
4372
4373 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
4374                                 struct intel_crtc_state *cstate,
4375                                 const struct intel_plane_state *intel_pstate,
4376                                 uint16_t ddb_allocation,
4377                                 int level,
4378                                 uint16_t *out_blocks, /* out */
4379                                 uint8_t *out_lines, /* out */
4380                                 bool *enabled /* out */)
4381 {
4382         struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
4383         const struct drm_plane_state *pstate = &intel_pstate->base;
4384         const struct drm_framebuffer *fb = pstate->fb;
4385         uint32_t latency = dev_priv->wm.skl_latency[level];
4386         uint_fixed_16_16_t method1, method2;
4387         uint_fixed_16_16_t plane_blocks_per_line;
4388         uint_fixed_16_16_t selected_result;
4389         uint32_t interm_pbpl;
4390         uint32_t plane_bytes_per_line;
4391         uint32_t res_blocks, res_lines;
4392         uint8_t cpp;
4393         uint32_t width = 0;
4394         uint32_t plane_pixel_rate;
4395         uint_fixed_16_16_t y_tile_minimum;
4396         uint32_t y_min_scanlines;
4397         struct intel_atomic_state *state =
4398                 to_intel_atomic_state(cstate->base.state);
4399         bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
4400         bool y_tiled, x_tiled;
4401
4402         if (latency == 0 ||
4403             !intel_wm_plane_visible(cstate, intel_pstate)) {
4404                 *enabled = false;
4405                 return 0;
4406         }
4407
4408         y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
4409                   fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
4410                   fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
4411                   fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
4412         x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
4413
4414         /* Display WA #1141: kbl,cfl */
4415         if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) &&
4416             dev_priv->ipc_enabled)
4417                 latency += 4;
4418
4419         if (apply_memory_bw_wa && x_tiled)
4420                 latency += 15;
4421
4422         if (plane->id == PLANE_CURSOR) {
4423                 width = intel_pstate->base.crtc_w;
4424         } else {
4425                 /*
4426                  * Src coordinates are already rotated by 270 degrees for
4427                  * the 90/270 degree plane rotation cases (to match the
4428                  * GTT mapping), hence no need to account for rotation here.
4429                  */
4430                 width = drm_rect_width(&intel_pstate->base.src) >> 16;
4431         }
4432
4433         cpp = (fb->format->format == DRM_FORMAT_NV12) ? fb->format->cpp[1] :
4434                                                         fb->format->cpp[0];
4435         plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
4436
4437         if (drm_rotation_90_or_270(pstate->rotation)) {
4438
4439                 switch (cpp) {
4440                 case 1:
4441                         y_min_scanlines = 16;
4442                         break;
4443                 case 2:
4444                         y_min_scanlines = 8;
4445                         break;
4446                 case 4:
4447                         y_min_scanlines = 4;
4448                         break;
4449                 default:
4450                         MISSING_CASE(cpp);
4451                         return -EINVAL;
4452                 }
4453         } else {
4454                 y_min_scanlines = 4;
4455         }
4456
4457         if (apply_memory_bw_wa)
4458                 y_min_scanlines *= 2;
4459
4460         plane_bytes_per_line = width * cpp;
4461         if (y_tiled) {
4462                 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line *
4463                                            y_min_scanlines, 512);
4464
4465                 if (INTEL_GEN(dev_priv) >= 10)
4466                         interm_pbpl++;
4467
4468                 plane_blocks_per_line = div_fixed16(interm_pbpl,
4469                                                         y_min_scanlines);
4470         } else if (x_tiled && INTEL_GEN(dev_priv) == 9) {
4471                 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512);
4472                 plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
4473         } else {
4474                 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
4475                 plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
4476         }
4477
4478         method1 = skl_wm_method1(dev_priv, plane_pixel_rate, cpp, latency);
4479         method2 = skl_wm_method2(plane_pixel_rate,
4480                                  cstate->base.adjusted_mode.crtc_htotal,
4481                                  latency,
4482                                  plane_blocks_per_line);
4483
4484         y_tile_minimum = mul_u32_fixed16(y_min_scanlines,
4485                                          plane_blocks_per_line);
4486
4487         if (y_tiled) {
4488                 selected_result = max_fixed16(method2, y_tile_minimum);
4489         } else {
4490                 uint32_t linetime_us;
4491
4492                 linetime_us = fixed16_to_u32_round_up(
4493                                 intel_get_linetime_us(cstate));
4494                 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
4495                     (plane_bytes_per_line / 512 < 1))
4496                         selected_result = method2;
4497                 else if (ddb_allocation >=
4498                          fixed16_to_u32_round_up(plane_blocks_per_line))
4499                         selected_result = min_fixed16(method1, method2);
4500                 else if (latency >= linetime_us)
4501                         selected_result = min_fixed16(method1, method2);
4502                 else
4503                         selected_result = method1;
4504         }
4505
4506         res_blocks = fixed16_to_u32_round_up(selected_result) + 1;
4507         res_lines = div_round_up_fixed16(selected_result,
4508                                          plane_blocks_per_line);
4509
4510         /* Display WA #1125: skl,bxt,kbl,glk */
4511         if (level == 0 &&
4512             (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
4513              fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
4514                 res_blocks += fixed16_to_u32_round_up(y_tile_minimum);
4515
4516         /* Display WA #1126: skl,bxt,kbl,glk */
4517         if (level >= 1 && level <= 7) {
4518                 if (y_tiled) {
4519                         res_blocks += fixed16_to_u32_round_up(y_tile_minimum);
4520                         res_lines += y_min_scanlines;
4521                 } else {
4522                         res_blocks++;
4523                 }
4524         }
4525
4526         if (res_blocks >= ddb_allocation || res_lines > 31) {
4527                 *enabled = false;
4528
4529                 /*
4530                  * If there are no valid level 0 watermarks, then we can't
4531                  * support this display configuration.
4532                  */
4533                 if (level) {
4534                         return 0;
4535                 } else {
4536                         struct drm_plane *plane = pstate->plane;
4537
4538                         DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
4539                         DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n",
4540                                       plane->base.id, plane->name,
4541                                       res_blocks, ddb_allocation, res_lines);
4542                         return -EINVAL;
4543                 }
4544         }
4545
4546         *out_blocks = res_blocks;
4547         *out_lines = res_lines;
4548         *enabled = true;
4549
4550         return 0;
4551 }
4552
4553 static int
4554 skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
4555                       struct skl_ddb_allocation *ddb,
4556                       struct intel_crtc_state *cstate,
4557                       const struct intel_plane_state *intel_pstate,
4558                       struct skl_plane_wm *wm)
4559 {
4560         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4561         struct drm_plane *plane = intel_pstate->base.plane;
4562         struct intel_plane *intel_plane = to_intel_plane(plane);
4563         uint16_t ddb_blocks;
4564         enum pipe pipe = intel_crtc->pipe;
4565         int level, max_level = ilk_wm_max_level(dev_priv);
4566         int ret;
4567
4568         if (WARN_ON(!intel_pstate->base.fb))
4569                 return -EINVAL;
4570
4571         ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
4572
4573         for (level = 0; level <= max_level; level++) {
4574                 struct skl_wm_level *result = &wm->wm[level];
4575
4576                 ret = skl_compute_plane_wm(dev_priv,
4577                                            cstate,
4578                                            intel_pstate,
4579                                            ddb_blocks,
4580                                            level,
4581                                            &result->plane_res_b,
4582                                            &result->plane_res_l,
4583                                            &result->plane_en);
4584                 if (ret)
4585                         return ret;
4586         }
4587
4588         return 0;
4589 }
4590
4591 static uint32_t
4592 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
4593 {
4594         struct drm_atomic_state *state = cstate->base.state;
4595         struct drm_i915_private *dev_priv = to_i915(state->dev);
4596         uint_fixed_16_16_t linetime_us;
4597         uint32_t linetime_wm;
4598
4599         linetime_us = intel_get_linetime_us(cstate);
4600
4601         if (is_fixed16_zero(linetime_us))
4602                 return 0;
4603
4604         linetime_wm = fixed16_to_u32_round_up(mul_u32_fixed16(8, linetime_us));
4605
4606         /* Display WA #1135: bxt. */
4607         if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled)
4608                 linetime_wm = DIV_ROUND_UP(linetime_wm, 2);
4609
4610         return linetime_wm;
4611 }
4612
4613 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
4614                                       struct skl_wm_level *trans_wm /* out */)
4615 {
4616         if (!cstate->base.active)
4617                 return;
4618
4619         /* Until we know more, just disable transition WMs */
4620         trans_wm->plane_en = false;
4621 }
4622
4623 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
4624                              struct skl_ddb_allocation *ddb,
4625                              struct skl_pipe_wm *pipe_wm)
4626 {
4627         struct drm_device *dev = cstate->base.crtc->dev;
4628         struct drm_crtc_state *crtc_state = &cstate->base;
4629         const struct drm_i915_private *dev_priv = to_i915(dev);
4630         struct drm_plane *plane;
4631         const struct drm_plane_state *pstate;
4632         struct skl_plane_wm *wm;
4633         int ret;
4634
4635         /*
4636          * We'll only calculate watermarks for planes that are actually
4637          * enabled, so make sure all other planes are set as disabled.
4638          */
4639         memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
4640
4641         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
4642                 const struct intel_plane_state *intel_pstate =
4643                                                 to_intel_plane_state(pstate);
4644                 enum plane_id plane_id = to_intel_plane(plane)->id;
4645
4646                 wm = &pipe_wm->planes[plane_id];
4647
4648                 ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
4649                                             intel_pstate, wm);
4650                 if (ret)
4651                         return ret;
4652                 skl_compute_transition_wm(cstate, &wm->trans_wm);
4653         }
4654         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
4655
4656         return 0;
4657 }
4658
4659 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
4660                                 i915_reg_t reg,
4661                                 const struct skl_ddb_entry *entry)
4662 {
4663         if (entry->end)
4664                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
4665         else
4666                 I915_WRITE(reg, 0);
4667 }
4668
4669 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
4670                                i915_reg_t reg,
4671                                const struct skl_wm_level *level)
4672 {
4673         uint32_t val = 0;
4674
4675         if (level->plane_en) {
4676                 val |= PLANE_WM_EN;
4677                 val |= level->plane_res_b;
4678                 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
4679         }
4680
4681         I915_WRITE(reg, val);
4682 }
4683
4684 static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
4685                                const struct skl_plane_wm *wm,
4686                                const struct skl_ddb_allocation *ddb,
4687                                enum plane_id plane_id)
4688 {
4689         struct drm_crtc *crtc = &intel_crtc->base;
4690         struct drm_device *dev = crtc->dev;
4691         struct drm_i915_private *dev_priv = to_i915(dev);
4692         int level, max_level = ilk_wm_max_level(dev_priv);
4693         enum pipe pipe = intel_crtc->pipe;
4694
4695         for (level = 0; level <= max_level; level++) {
4696                 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
4697                                    &wm->wm[level]);
4698         }
4699         skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
4700                            &wm->trans_wm);
4701
4702         skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
4703                             &ddb->plane[pipe][plane_id]);
4704         skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
4705                             &ddb->y_plane[pipe][plane_id]);
4706 }
4707
4708 static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
4709                                 const struct skl_plane_wm *wm,
4710                                 const struct skl_ddb_allocation *ddb)
4711 {
4712         struct drm_crtc *crtc = &intel_crtc->base;
4713         struct drm_device *dev = crtc->dev;
4714         struct drm_i915_private *dev_priv = to_i915(dev);
4715         int level, max_level = ilk_wm_max_level(dev_priv);
4716         enum pipe pipe = intel_crtc->pipe;
4717
4718         for (level = 0; level <= max_level; level++) {
4719                 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
4720                                    &wm->wm[level]);
4721         }
4722         skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
4723
4724         skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4725                             &ddb->plane[pipe][PLANE_CURSOR]);
4726 }
4727
4728 bool skl_wm_level_equals(const struct skl_wm_level *l1,
4729                          const struct skl_wm_level *l2)
4730 {
4731         if (l1->plane_en != l2->plane_en)
4732                 return false;
4733
4734         /* If both planes aren't enabled, the rest shouldn't matter */
4735         if (!l1->plane_en)
4736                 return true;
4737
4738         return (l1->plane_res_l == l2->plane_res_l &&
4739                 l1->plane_res_b == l2->plane_res_b);
4740 }
4741
4742 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
4743                                            const struct skl_ddb_entry *b)
4744 {
4745         return a->start < b->end && b->start < a->end;
4746 }
4747
4748 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
4749                                  const struct skl_ddb_entry *ddb,
4750                                  int ignore)
4751 {
4752         int i;
4753
4754         for (i = 0; i < I915_MAX_PIPES; i++)
4755                 if (i != ignore && entries[i] &&
4756                     skl_ddb_entries_overlap(ddb, entries[i]))
4757                         return true;
4758
4759         return false;
4760 }
4761
4762 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
4763                               const struct skl_pipe_wm *old_pipe_wm,
4764                               struct skl_pipe_wm *pipe_wm, /* out */
4765                               struct skl_ddb_allocation *ddb, /* out */
4766                               bool *changed /* out */)
4767 {
4768         struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
4769         int ret;
4770
4771         ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
4772         if (ret)
4773                 return ret;
4774
4775         if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
4776                 *changed = false;
4777         else
4778                 *changed = true;
4779
4780         return 0;
4781 }
4782
4783 static uint32_t
4784 pipes_modified(struct drm_atomic_state *state)
4785 {
4786         struct drm_crtc *crtc;
4787         struct drm_crtc_state *cstate;
4788         uint32_t i, ret = 0;
4789
4790         for_each_new_crtc_in_state(state, crtc, cstate, i)
4791                 ret |= drm_crtc_mask(crtc);
4792
4793         return ret;
4794 }
4795
4796 static int
4797 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
4798 {
4799         struct drm_atomic_state *state = cstate->base.state;
4800         struct drm_device *dev = state->dev;
4801         struct drm_crtc *crtc = cstate->base.crtc;
4802         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4803         struct drm_i915_private *dev_priv = to_i915(dev);
4804         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4805         struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4806         struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
4807         struct drm_plane_state *plane_state;
4808         struct drm_plane *plane;
4809         enum pipe pipe = intel_crtc->pipe;
4810
4811         WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
4812
4813         drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
4814                 enum plane_id plane_id = to_intel_plane(plane)->id;
4815
4816                 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
4817                                         &new_ddb->plane[pipe][plane_id]) &&
4818                     skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
4819                                         &new_ddb->y_plane[pipe][plane_id]))
4820                         continue;
4821
4822                 plane_state = drm_atomic_get_plane_state(state, plane);
4823                 if (IS_ERR(plane_state))
4824                         return PTR_ERR(plane_state);
4825         }
4826
4827         return 0;
4828 }
4829
4830 static int
4831 skl_compute_ddb(struct drm_atomic_state *state)
4832 {
4833         struct drm_device *dev = state->dev;
4834         struct drm_i915_private *dev_priv = to_i915(dev);
4835         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4836         struct intel_crtc *intel_crtc;
4837         struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
4838         uint32_t realloc_pipes = pipes_modified(state);
4839         int ret;
4840
4841         /*
4842          * If this is our first atomic update following hardware readout,
4843          * we can't trust the DDB that the BIOS programmed for us.  Let's
4844          * pretend that all pipes switched active status so that we'll
4845          * ensure a full DDB recompute.
4846          */
4847         if (dev_priv->wm.distrust_bios_wm) {
4848                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4849                                        state->acquire_ctx);
4850                 if (ret)
4851                         return ret;
4852
4853                 intel_state->active_pipe_changes = ~0;
4854
4855                 /*
4856                  * We usually only initialize intel_state->active_crtcs if we
4857                  * we're doing a modeset; make sure this field is always
4858                  * initialized during the sanitization process that happens
4859                  * on the first commit too.
4860                  */
4861                 if (!intel_state->modeset)
4862                         intel_state->active_crtcs = dev_priv->active_crtcs;
4863         }
4864
4865         /*
4866          * If the modeset changes which CRTC's are active, we need to
4867          * recompute the DDB allocation for *all* active pipes, even
4868          * those that weren't otherwise being modified in any way by this
4869          * atomic commit.  Due to the shrinking of the per-pipe allocations
4870          * when new active CRTC's are added, it's possible for a pipe that
4871          * we were already using and aren't changing at all here to suddenly
4872          * become invalid if its DDB needs exceeds its new allocation.
4873          *
4874          * Note that if we wind up doing a full DDB recompute, we can't let
4875          * any other display updates race with this transaction, so we need
4876          * to grab the lock on *all* CRTC's.
4877          */
4878         if (intel_state->active_pipe_changes) {
4879                 realloc_pipes = ~0;
4880                 intel_state->wm_results.dirty_pipes = ~0;
4881         }
4882
4883         /*
4884          * We're not recomputing for the pipes not included in the commit, so
4885          * make sure we start with the current state.
4886          */
4887         memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4888
4889         for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4890                 struct intel_crtc_state *cstate;
4891
4892                 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4893                 if (IS_ERR(cstate))
4894                         return PTR_ERR(cstate);
4895
4896                 ret = skl_allocate_pipe_ddb(cstate, ddb);
4897                 if (ret)
4898                         return ret;
4899
4900                 ret = skl_ddb_add_affected_planes(cstate);
4901                 if (ret)
4902                         return ret;
4903         }
4904
4905         return 0;
4906 }
4907
4908 static void
4909 skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4910                      struct skl_wm_values *src,
4911                      enum pipe pipe)
4912 {
4913         memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4914                sizeof(dst->ddb.y_plane[pipe]));
4915         memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4916                sizeof(dst->ddb.plane[pipe]));
4917 }
4918
4919 static void
4920 skl_print_wm_changes(const struct drm_atomic_state *state)
4921 {
4922         const struct drm_device *dev = state->dev;
4923         const struct drm_i915_private *dev_priv = to_i915(dev);
4924         const struct intel_atomic_state *intel_state =
4925                 to_intel_atomic_state(state);
4926         const struct drm_crtc *crtc;
4927         const struct drm_crtc_state *cstate;
4928         const struct intel_plane *intel_plane;
4929         const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4930         const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4931         int i;
4932
4933         for_each_new_crtc_in_state(state, crtc, cstate, i) {
4934                 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4935                 enum pipe pipe = intel_crtc->pipe;
4936
4937                 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4938                         enum plane_id plane_id = intel_plane->id;
4939                         const struct skl_ddb_entry *old, *new;
4940
4941                         old = &old_ddb->plane[pipe][plane_id];
4942                         new = &new_ddb->plane[pipe][plane_id];
4943
4944                         if (skl_ddb_entry_equal(old, new))
4945                                 continue;
4946
4947                         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4948                                          intel_plane->base.base.id,
4949                                          intel_plane->base.name,
4950                                          old->start, old->end,
4951                                          new->start, new->end);
4952                 }
4953         }
4954 }
4955
4956 static int
4957 skl_compute_wm(struct drm_atomic_state *state)
4958 {
4959         struct drm_crtc *crtc;
4960         struct drm_crtc_state *cstate;
4961         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4962         struct skl_wm_values *results = &intel_state->wm_results;
4963         struct drm_device *dev = state->dev;
4964         struct skl_pipe_wm *pipe_wm;
4965         bool changed = false;
4966         int ret, i;
4967
4968         /*
4969          * When we distrust bios wm we always need to recompute to set the
4970          * expected DDB allocations for each CRTC.
4971          */
4972         if (to_i915(dev)->wm.distrust_bios_wm)
4973                 changed = true;
4974
4975         /*
4976          * If this transaction isn't actually touching any CRTC's, don't
4977          * bother with watermark calculation.  Note that if we pass this
4978          * test, we're guaranteed to hold at least one CRTC state mutex,
4979          * which means we can safely use values like dev_priv->active_crtcs
4980          * since any racing commits that want to update them would need to
4981          * hold _all_ CRTC state mutexes.
4982          */
4983         for_each_new_crtc_in_state(state, crtc, cstate, i)
4984                 changed = true;
4985
4986         if (!changed)
4987                 return 0;
4988
4989         /* Clear all dirty flags */
4990         results->dirty_pipes = 0;
4991
4992         ret = skl_compute_ddb(state);
4993         if (ret)
4994                 return ret;
4995
4996         /*
4997          * Calculate WM's for all pipes that are part of this transaction.
4998          * Note that the DDB allocation above may have added more CRTC's that
4999          * weren't otherwise being modified (and set bits in dirty_pipes) if
5000          * pipe allocations had to change.
5001          *
5002          * FIXME:  Now that we're doing this in the atomic check phase, we
5003          * should allow skl_update_pipe_wm() to return failure in cases where
5004          * no suitable watermark values can be found.
5005          */
5006         for_each_new_crtc_in_state(state, crtc, cstate, i) {
5007                 struct intel_crtc_state *intel_cstate =
5008                         to_intel_crtc_state(cstate);
5009                 const struct skl_pipe_wm *old_pipe_wm =
5010                         &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
5011
5012                 pipe_wm = &intel_cstate->wm.skl.optimal;
5013                 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
5014                                          &results->ddb, &changed);
5015                 if (ret)
5016                         return ret;
5017
5018                 if (changed)
5019                         results->dirty_pipes |= drm_crtc_mask(crtc);
5020
5021                 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
5022                         /* This pipe's WM's did not change */
5023                         continue;
5024
5025                 intel_cstate->update_wm_pre = true;
5026         }
5027
5028         skl_print_wm_changes(state);
5029
5030         return 0;
5031 }
5032
5033 static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
5034                                       struct intel_crtc_state *cstate)
5035 {
5036         struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
5037         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5038         struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
5039         const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
5040         enum pipe pipe = crtc->pipe;
5041         enum plane_id plane_id;
5042
5043         if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
5044                 return;
5045
5046         I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
5047
5048         for_each_plane_id_on_crtc(crtc, plane_id) {
5049                 if (plane_id != PLANE_CURSOR)
5050                         skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id],
5051                                            ddb, plane_id);
5052                 else
5053                         skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id],
5054                                             ddb);
5055         }
5056 }
5057
5058 static void skl_initial_wm(struct intel_atomic_state *state,
5059                            struct intel_crtc_state *cstate)
5060 {
5061         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
5062         struct drm_device *dev = intel_crtc->base.dev;
5063         struct drm_i915_private *dev_priv = to_i915(dev);
5064         struct skl_wm_values *results = &state->wm_results;
5065         struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
5066         enum pipe pipe = intel_crtc->pipe;
5067
5068         if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
5069                 return;
5070
5071         mutex_lock(&dev_priv->wm.wm_mutex);
5072
5073         if (cstate->base.active_changed)
5074                 skl_atomic_update_crtc_wm(state, cstate);
5075
5076         skl_copy_wm_for_pipe(hw_vals, results, pipe);
5077
5078         mutex_unlock(&dev_priv->wm.wm_mutex);
5079 }
5080
5081 static void ilk_compute_wm_config(struct drm_device *dev,
5082                                   struct intel_wm_config *config)
5083 {
5084         struct intel_crtc *crtc;
5085
5086         /* Compute the currently _active_ config */
5087         for_each_intel_crtc(dev, crtc) {
5088                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
5089
5090                 if (!wm->pipe_enabled)
5091                         continue;
5092
5093                 config->sprites_enabled |= wm->sprites_enabled;
5094                 config->sprites_scaled |= wm->sprites_scaled;
5095                 config->num_pipes_active++;
5096         }
5097 }
5098
5099 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
5100 {
5101         struct drm_device *dev = &dev_priv->drm;
5102         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
5103         struct ilk_wm_maximums max;
5104         struct intel_wm_config config = {};
5105         struct ilk_wm_values results = {};
5106         enum intel_ddb_partitioning partitioning;
5107
5108         ilk_compute_wm_config(dev, &config);
5109
5110         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
5111         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
5112
5113         /* 5/6 split only in single pipe config on IVB+ */
5114         if (INTEL_GEN(dev_priv) >= 7 &&
5115             config.num_pipes_active == 1 && config.sprites_enabled) {
5116                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
5117                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
5118
5119                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
5120         } else {
5121                 best_lp_wm = &lp_wm_1_2;
5122         }
5123
5124         partitioning = (best_lp_wm == &lp_wm_1_2) ?
5125                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
5126
5127         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
5128
5129         ilk_write_wm_values(dev_priv, &results);
5130 }
5131
5132 static void ilk_initial_watermarks(struct intel_atomic_state *state,
5133                                    struct intel_crtc_state *cstate)
5134 {
5135         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
5136         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
5137
5138         mutex_lock(&dev_priv->wm.wm_mutex);
5139         intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
5140         ilk_program_watermarks(dev_priv);
5141         mutex_unlock(&dev_priv->wm.wm_mutex);
5142 }
5143
5144 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
5145                                     struct intel_crtc_state *cstate)
5146 {
5147         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
5148         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
5149
5150         mutex_lock(&dev_priv->wm.wm_mutex);
5151         if (cstate->wm.need_postvbl_update) {
5152                 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
5153                 ilk_program_watermarks(dev_priv);
5154         }
5155         mutex_unlock(&dev_priv->wm.wm_mutex);
5156 }
5157
5158 static inline void skl_wm_level_from_reg_val(uint32_t val,
5159                                              struct skl_wm_level *level)
5160 {
5161         level->plane_en = val & PLANE_WM_EN;
5162         level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
5163         level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
5164                 PLANE_WM_LINES_MASK;
5165 }
5166
5167 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
5168                               struct skl_pipe_wm *out)
5169 {
5170         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5171         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5172         enum pipe pipe = intel_crtc->pipe;
5173         int level, max_level;
5174         enum plane_id plane_id;
5175         uint32_t val;
5176
5177         max_level = ilk_wm_max_level(dev_priv);
5178
5179         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
5180                 struct skl_plane_wm *wm = &out->planes[plane_id];
5181
5182                 for (level = 0; level <= max_level; level++) {
5183                         if (plane_id != PLANE_CURSOR)
5184                                 val = I915_READ(PLANE_WM(pipe, plane_id, level));
5185                         else
5186                                 val = I915_READ(CUR_WM(pipe, level));
5187
5188                         skl_wm_level_from_reg_val(val, &wm->wm[level]);
5189                 }
5190
5191                 if (plane_id != PLANE_CURSOR)
5192                         val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
5193                 else
5194                         val = I915_READ(CUR_WM_TRANS(pipe));
5195
5196                 skl_wm_level_from_reg_val(val, &wm->trans_wm);
5197         }
5198
5199         if (!intel_crtc->active)
5200                 return;
5201
5202         out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
5203 }
5204
5205 void skl_wm_get_hw_state(struct drm_device *dev)
5206 {
5207         struct drm_i915_private *dev_priv = to_i915(dev);
5208         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
5209         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
5210         struct drm_crtc *crtc;
5211         struct intel_crtc *intel_crtc;
5212         struct intel_crtc_state *cstate;
5213
5214         skl_ddb_get_hw_state(dev_priv, ddb);
5215         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5216                 intel_crtc = to_intel_crtc(crtc);
5217                 cstate = to_intel_crtc_state(crtc->state);
5218
5219                 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
5220
5221                 if (intel_crtc->active)
5222                         hw->dirty_pipes |= drm_crtc_mask(crtc);
5223         }
5224
5225         if (dev_priv->active_crtcs) {
5226                 /* Fully recompute DDB on first atomic commit */
5227                 dev_priv->wm.distrust_bios_wm = true;
5228         } else {
5229                 /* Easy/common case; just sanitize DDB now if everything off */
5230                 memset(ddb, 0, sizeof(*ddb));
5231         }
5232 }
5233
5234 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
5235 {
5236         struct drm_device *dev = crtc->dev;
5237         struct drm_i915_private *dev_priv = to_i915(dev);
5238         struct ilk_wm_values *hw = &dev_priv->wm.hw;
5239         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5240         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
5241         struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
5242         enum pipe pipe = intel_crtc->pipe;
5243         static const i915_reg_t wm0_pipe_reg[] = {
5244                 [PIPE_A] = WM0_PIPEA_ILK,
5245                 [PIPE_B] = WM0_PIPEB_ILK,
5246                 [PIPE_C] = WM0_PIPEC_IVB,
5247         };
5248
5249         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
5250         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5251                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
5252
5253         memset(active, 0, sizeof(*active));
5254
5255         active->pipe_enabled = intel_crtc->active;
5256
5257         if (active->pipe_enabled) {
5258                 u32 tmp = hw->wm_pipe[pipe];
5259
5260                 /*
5261                  * For active pipes LP0 watermark is marked as
5262                  * enabled, and LP1+ watermaks as disabled since
5263                  * we can't really reverse compute them in case
5264                  * multiple pipes are active.
5265                  */
5266                 active->wm[0].enable = true;
5267                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
5268                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
5269                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
5270                 active->linetime = hw->wm_linetime[pipe];
5271         } else {
5272                 int level, max_level = ilk_wm_max_level(dev_priv);
5273
5274                 /*
5275                  * For inactive pipes, all watermark levels
5276                  * should be marked as enabled but zeroed,
5277                  * which is what we'd compute them to.
5278                  */
5279                 for (level = 0; level <= max_level; level++)
5280                         active->wm[level].enable = true;
5281         }
5282
5283         intel_crtc->wm.active.ilk = *active;
5284 }
5285
5286 #define _FW_WM(value, plane) \
5287         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
5288 #define _FW_WM_VLV(value, plane) \
5289         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
5290
5291 static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
5292                                struct g4x_wm_values *wm)
5293 {
5294         uint32_t tmp;
5295
5296         tmp = I915_READ(DSPFW1);
5297         wm->sr.plane = _FW_WM(tmp, SR);
5298         wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
5299         wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
5300         wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
5301
5302         tmp = I915_READ(DSPFW2);
5303         wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
5304         wm->sr.fbc = _FW_WM(tmp, FBC_SR);
5305         wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
5306         wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);
5307         wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
5308         wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
5309
5310         tmp = I915_READ(DSPFW3);
5311         wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
5312         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
5313         wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
5314         wm->hpll.plane = _FW_WM(tmp, HPLL_SR);
5315 }
5316
5317 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
5318                                struct vlv_wm_values *wm)
5319 {
5320         enum pipe pipe;
5321         uint32_t tmp;
5322
5323         for_each_pipe(dev_priv, pipe) {
5324                 tmp = I915_READ(VLV_DDL(pipe));
5325
5326                 wm->ddl[pipe].plane[PLANE_PRIMARY] =
5327                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5328                 wm->ddl[pipe].plane[PLANE_CURSOR] =
5329                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5330                 wm->ddl[pipe].plane[PLANE_SPRITE0] =
5331                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5332                 wm->ddl[pipe].plane[PLANE_SPRITE1] =
5333                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5334         }
5335
5336         tmp = I915_READ(DSPFW1);
5337         wm->sr.plane = _FW_WM(tmp, SR);
5338         wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
5339         wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
5340         wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
5341
5342         tmp = I915_READ(DSPFW2);
5343         wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
5344         wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
5345         wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
5346
5347         tmp = I915_READ(DSPFW3);
5348         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
5349
5350         if (IS_CHERRYVIEW(dev_priv)) {
5351                 tmp = I915_READ(DSPFW7_CHV);
5352                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
5353                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
5354
5355                 tmp = I915_READ(DSPFW8_CHV);
5356                 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
5357                 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
5358
5359                 tmp = I915_READ(DSPFW9_CHV);
5360                 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
5361                 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
5362
5363                 tmp = I915_READ(DSPHOWM);
5364                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
5365                 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
5366                 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
5367                 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
5368                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
5369                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
5370                 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
5371                 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
5372                 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
5373                 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
5374         } else {
5375                 tmp = I915_READ(DSPFW7);
5376                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
5377                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
5378
5379                 tmp = I915_READ(DSPHOWM);
5380                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
5381                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
5382                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
5383                 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
5384                 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
5385                 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
5386                 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
5387         }
5388 }
5389
5390 #undef _FW_WM
5391 #undef _FW_WM_VLV
5392
5393 void g4x_wm_get_hw_state(struct drm_device *dev)
5394 {
5395         struct drm_i915_private *dev_priv = to_i915(dev);
5396         struct g4x_wm_values *wm = &dev_priv->wm.g4x;
5397         struct intel_crtc *crtc;
5398
5399         g4x_read_wm_values(dev_priv, wm);
5400
5401         wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
5402
5403         for_each_intel_crtc(dev, crtc) {
5404                 struct intel_crtc_state *crtc_state =
5405                         to_intel_crtc_state(crtc->base.state);
5406                 struct g4x_wm_state *active = &crtc->wm.active.g4x;
5407                 struct g4x_pipe_wm *raw;
5408                 enum pipe pipe = crtc->pipe;
5409                 enum plane_id plane_id;
5410                 int level, max_level;
5411
5412                 active->cxsr = wm->cxsr;
5413                 active->hpll_en = wm->hpll_en;
5414                 active->fbc_en = wm->fbc_en;
5415
5416                 active->sr = wm->sr;
5417                 active->hpll = wm->hpll;
5418
5419                 for_each_plane_id_on_crtc(crtc, plane_id) {
5420                         active->wm.plane[plane_id] =
5421                                 wm->pipe[pipe].plane[plane_id];
5422                 }
5423
5424                 if (wm->cxsr && wm->hpll_en)
5425                         max_level = G4X_WM_LEVEL_HPLL;
5426                 else if (wm->cxsr)
5427                         max_level = G4X_WM_LEVEL_SR;
5428                 else
5429                         max_level = G4X_WM_LEVEL_NORMAL;
5430
5431                 level = G4X_WM_LEVEL_NORMAL;
5432                 raw = &crtc_state->wm.g4x.raw[level];
5433                 for_each_plane_id_on_crtc(crtc, plane_id)
5434                         raw->plane[plane_id] = active->wm.plane[plane_id];
5435
5436                 if (++level > max_level)
5437                         goto out;
5438
5439                 raw = &crtc_state->wm.g4x.raw[level];
5440                 raw->plane[PLANE_PRIMARY] = active->sr.plane;
5441                 raw->plane[PLANE_CURSOR] = active->sr.cursor;
5442                 raw->plane[PLANE_SPRITE0] = 0;
5443                 raw->fbc = active->sr.fbc;
5444
5445                 if (++level > max_level)
5446                         goto out;
5447
5448                 raw = &crtc_state->wm.g4x.raw[level];
5449                 raw->plane[PLANE_PRIMARY] = active->hpll.plane;
5450                 raw->plane[PLANE_CURSOR] = active->hpll.cursor;
5451                 raw->plane[PLANE_SPRITE0] = 0;
5452                 raw->fbc = active->hpll.fbc;
5453
5454         out:
5455                 for_each_plane_id_on_crtc(crtc, plane_id)
5456                         g4x_raw_plane_wm_set(crtc_state, level,
5457                                              plane_id, USHRT_MAX);
5458                 g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
5459
5460                 crtc_state->wm.g4x.optimal = *active;
5461                 crtc_state->wm.g4x.intermediate = *active;
5462
5463                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n",
5464                               pipe_name(pipe),
5465                               wm->pipe[pipe].plane[PLANE_PRIMARY],
5466                               wm->pipe[pipe].plane[PLANE_CURSOR],
5467                               wm->pipe[pipe].plane[PLANE_SPRITE0]);
5468         }
5469
5470         DRM_DEBUG_KMS("Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n",
5471                       wm->sr.plane, wm->sr.cursor, wm->sr.fbc);
5472         DRM_DEBUG_KMS("Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n",
5473                       wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc);
5474         DRM_DEBUG_KMS("Initial SR=%s HPLL=%s FBC=%s\n",
5475                       yesno(wm->cxsr), yesno(wm->hpll_en), yesno(wm->fbc_en));
5476 }
5477
5478 void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
5479 {
5480         struct intel_plane *plane;
5481         struct intel_crtc *crtc;
5482
5483         mutex_lock(&dev_priv->wm.wm_mutex);
5484
5485         for_each_intel_plane(&dev_priv->drm, plane) {
5486                 struct intel_crtc *crtc =
5487                         intel_get_crtc_for_pipe(dev_priv, plane->pipe);
5488                 struct intel_crtc_state *crtc_state =
5489                         to_intel_crtc_state(crtc->base.state);
5490                 struct intel_plane_state *plane_state =
5491                         to_intel_plane_state(plane->base.state);
5492                 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
5493                 enum plane_id plane_id = plane->id;
5494                 int level;
5495
5496                 if (plane_state->base.visible)
5497                         continue;
5498
5499                 for (level = 0; level < 3; level++) {
5500                         struct g4x_pipe_wm *raw =
5501                                 &crtc_state->wm.g4x.raw[level];
5502
5503                         raw->plane[plane_id] = 0;
5504                         wm_state->wm.plane[plane_id] = 0;
5505                 }
5506
5507                 if (plane_id == PLANE_PRIMARY) {
5508                         for (level = 0; level < 3; level++) {
5509                                 struct g4x_pipe_wm *raw =
5510                                         &crtc_state->wm.g4x.raw[level];
5511                                 raw->fbc = 0;
5512                         }
5513
5514                         wm_state->sr.fbc = 0;
5515                         wm_state->hpll.fbc = 0;
5516                         wm_state->fbc_en = false;
5517                 }
5518         }
5519
5520         for_each_intel_crtc(&dev_priv->drm, crtc) {
5521                 struct intel_crtc_state *crtc_state =
5522                         to_intel_crtc_state(crtc->base.state);
5523
5524                 crtc_state->wm.g4x.intermediate =
5525                         crtc_state->wm.g4x.optimal;
5526                 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
5527         }
5528
5529         g4x_program_watermarks(dev_priv);
5530
5531         mutex_unlock(&dev_priv->wm.wm_mutex);
5532 }
5533
5534 void vlv_wm_get_hw_state(struct drm_device *dev)
5535 {
5536         struct drm_i915_private *dev_priv = to_i915(dev);
5537         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
5538         struct intel_crtc *crtc;
5539         u32 val;
5540
5541         vlv_read_wm_values(dev_priv, wm);
5542
5543         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
5544         wm->level = VLV_WM_LEVEL_PM2;
5545
5546         if (IS_CHERRYVIEW(dev_priv)) {
5547                 mutex_lock(&dev_priv->rps.hw_lock);
5548
5549                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5550                 if (val & DSP_MAXFIFO_PM5_ENABLE)
5551                         wm->level = VLV_WM_LEVEL_PM5;
5552
5553                 /*
5554                  * If DDR DVFS is disabled in the BIOS, Punit
5555                  * will never ack the request. So if that happens
5556                  * assume we don't have to enable/disable DDR DVFS
5557                  * dynamically. To test that just set the REQ_ACK
5558                  * bit to poke the Punit, but don't change the
5559                  * HIGH/LOW bits so that we don't actually change
5560                  * the current state.
5561                  */
5562                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
5563                 val |= FORCE_DDR_FREQ_REQ_ACK;
5564                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
5565
5566                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
5567                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
5568                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
5569                                       "assuming DDR DVFS is disabled\n");
5570                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
5571                 } else {
5572                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
5573                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
5574                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
5575                 }
5576
5577                 mutex_unlock(&dev_priv->rps.hw_lock);
5578         }
5579
5580         for_each_intel_crtc(dev, crtc) {
5581                 struct intel_crtc_state *crtc_state =
5582                         to_intel_crtc_state(crtc->base.state);
5583                 struct vlv_wm_state *active = &crtc->wm.active.vlv;
5584                 const struct vlv_fifo_state *fifo_state =
5585                         &crtc_state->wm.vlv.fifo_state;
5586                 enum pipe pipe = crtc->pipe;
5587                 enum plane_id plane_id;
5588                 int level;
5589
5590                 vlv_get_fifo_size(crtc_state);
5591
5592                 active->num_levels = wm->level + 1;
5593                 active->cxsr = wm->cxsr;
5594
5595                 for (level = 0; level < active->num_levels; level++) {
5596                         struct g4x_pipe_wm *raw =
5597                                 &crtc_state->wm.vlv.raw[level];
5598
5599                         active->sr[level].plane = wm->sr.plane;
5600                         active->sr[level].cursor = wm->sr.cursor;
5601
5602                         for_each_plane_id_on_crtc(crtc, plane_id) {
5603                                 active->wm[level].plane[plane_id] =
5604                                         wm->pipe[pipe].plane[plane_id];
5605
5606                                 raw->plane[plane_id] =
5607                                         vlv_invert_wm_value(active->wm[level].plane[plane_id],
5608                                                             fifo_state->plane[plane_id]);
5609                         }
5610                 }
5611
5612                 for_each_plane_id_on_crtc(crtc, plane_id)
5613                         vlv_raw_plane_wm_set(crtc_state, level,
5614                                              plane_id, USHRT_MAX);
5615                 vlv_invalidate_wms(crtc, active, level);
5616
5617                 crtc_state->wm.vlv.optimal = *active;
5618                 crtc_state->wm.vlv.intermediate = *active;
5619
5620                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
5621                               pipe_name(pipe),
5622                               wm->pipe[pipe].plane[PLANE_PRIMARY],
5623                               wm->pipe[pipe].plane[PLANE_CURSOR],
5624                               wm->pipe[pipe].plane[PLANE_SPRITE0],
5625                               wm->pipe[pipe].plane[PLANE_SPRITE1]);
5626         }
5627
5628         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
5629                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
5630 }
5631
5632 void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
5633 {
5634         struct intel_plane *plane;
5635         struct intel_crtc *crtc;
5636
5637         mutex_lock(&dev_priv->wm.wm_mutex);
5638
5639         for_each_intel_plane(&dev_priv->drm, plane) {
5640                 struct intel_crtc *crtc =
5641                         intel_get_crtc_for_pipe(dev_priv, plane->pipe);
5642                 struct intel_crtc_state *crtc_state =
5643                         to_intel_crtc_state(crtc->base.state);
5644                 struct intel_plane_state *plane_state =
5645                         to_intel_plane_state(plane->base.state);
5646                 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
5647                 const struct vlv_fifo_state *fifo_state =
5648                         &crtc_state->wm.vlv.fifo_state;
5649                 enum plane_id plane_id = plane->id;
5650                 int level;
5651
5652                 if (plane_state->base.visible)
5653                         continue;
5654
5655                 for (level = 0; level < wm_state->num_levels; level++) {
5656                         struct g4x_pipe_wm *raw =
5657                                 &crtc_state->wm.vlv.raw[level];
5658
5659                         raw->plane[plane_id] = 0;
5660
5661                         wm_state->wm[level].plane[plane_id] =
5662                                 vlv_invert_wm_value(raw->plane[plane_id],
5663                                                     fifo_state->plane[plane_id]);
5664                 }
5665         }
5666
5667         for_each_intel_crtc(&dev_priv->drm, crtc) {
5668                 struct intel_crtc_state *crtc_state =
5669                         to_intel_crtc_state(crtc->base.state);
5670
5671                 crtc_state->wm.vlv.intermediate =
5672                         crtc_state->wm.vlv.optimal;
5673                 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
5674         }
5675
5676         vlv_program_watermarks(dev_priv);
5677
5678         mutex_unlock(&dev_priv->wm.wm_mutex);
5679 }
5680
5681 void ilk_wm_get_hw_state(struct drm_device *dev)
5682 {
5683         struct drm_i915_private *dev_priv = to_i915(dev);
5684         struct ilk_wm_values *hw = &dev_priv->wm.hw;
5685         struct drm_crtc *crtc;
5686
5687         for_each_crtc(dev, crtc)
5688                 ilk_pipe_wm_get_hw_state(crtc);
5689
5690         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
5691         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
5692         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
5693
5694         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
5695         if (INTEL_GEN(dev_priv) >= 7) {
5696                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
5697                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
5698         }
5699
5700         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5701                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
5702                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
5703         else if (IS_IVYBRIDGE(dev_priv))
5704                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
5705                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
5706
5707         hw->enable_fbc_wm =
5708                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
5709 }
5710
5711 /**
5712  * intel_update_watermarks - update FIFO watermark values based on current modes
5713  *
5714  * Calculate watermark values for the various WM regs based on current mode
5715  * and plane configuration.
5716  *
5717  * There are several cases to deal with here:
5718  *   - normal (i.e. non-self-refresh)
5719  *   - self-refresh (SR) mode
5720  *   - lines are large relative to FIFO size (buffer can hold up to 2)
5721  *   - lines are small relative to FIFO size (buffer can hold more than 2
5722  *     lines), so need to account for TLB latency
5723  *
5724  *   The normal calculation is:
5725  *     watermark = dotclock * bytes per pixel * latency
5726  *   where latency is platform & configuration dependent (we assume pessimal
5727  *   values here).
5728  *
5729  *   The SR calculation is:
5730  *     watermark = (trunc(latency/line time)+1) * surface width *
5731  *       bytes per pixel
5732  *   where
5733  *     line time = htotal / dotclock
5734  *     surface width = hdisplay for normal plane and 64 for cursor
5735  *   and latency is assumed to be high, as above.
5736  *
5737  * The final value programmed to the register should always be rounded up,
5738  * and include an extra 2 entries to account for clock crossings.
5739  *
5740  * We don't use the sprite, so we can ignore that.  And on Crestline we have
5741  * to set the non-SR watermarks to 8.
5742  */
5743 void intel_update_watermarks(struct intel_crtc *crtc)
5744 {
5745         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5746
5747         if (dev_priv->display.update_wm)
5748                 dev_priv->display.update_wm(crtc);
5749 }
5750
5751 /*
5752  * Lock protecting IPS related data structures
5753  */
5754 DEFINE_SPINLOCK(mchdev_lock);
5755
5756 /* Global for IPS driver to get at the current i915 device. Protected by
5757  * mchdev_lock. */
5758 static struct drm_i915_private *i915_mch_dev;
5759
5760 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
5761 {
5762         u16 rgvswctl;
5763
5764         lockdep_assert_held(&mchdev_lock);
5765
5766         rgvswctl = I915_READ16(MEMSWCTL);
5767         if (rgvswctl & MEMCTL_CMD_STS) {
5768                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5769                 return false; /* still busy with another command */
5770         }
5771
5772         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5773                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5774         I915_WRITE16(MEMSWCTL, rgvswctl);
5775         POSTING_READ16(MEMSWCTL);
5776
5777         rgvswctl |= MEMCTL_CMD_STS;
5778         I915_WRITE16(MEMSWCTL, rgvswctl);
5779
5780         return true;
5781 }
5782
5783 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
5784 {
5785         u32 rgvmodectl;
5786         u8 fmax, fmin, fstart, vstart;
5787
5788         spin_lock_irq(&mchdev_lock);
5789
5790         rgvmodectl = I915_READ(MEMMODECTL);
5791
5792         /* Enable temp reporting */
5793         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5794         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5795
5796         /* 100ms RC evaluation intervals */
5797         I915_WRITE(RCUPEI, 100000);
5798         I915_WRITE(RCDNEI, 100000);
5799
5800         /* Set max/min thresholds to 90ms and 80ms respectively */
5801         I915_WRITE(RCBMAXAVG, 90000);
5802         I915_WRITE(RCBMINAVG, 80000);
5803
5804         I915_WRITE(MEMIHYST, 1);
5805
5806         /* Set up min, max, and cur for interrupt handling */
5807         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5808         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5809         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5810                 MEMMODE_FSTART_SHIFT;
5811
5812         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
5813                 PXVFREQ_PX_SHIFT;
5814
5815         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
5816         dev_priv->ips.fstart = fstart;
5817
5818         dev_priv->ips.max_delay = fstart;
5819         dev_priv->ips.min_delay = fmin;
5820         dev_priv->ips.cur_delay = fstart;
5821
5822         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5823                          fmax, fmin, fstart);
5824
5825         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5826
5827         /*
5828          * Interrupts will be enabled in ironlake_irq_postinstall
5829          */
5830
5831         I915_WRITE(VIDSTART, vstart);
5832         POSTING_READ(VIDSTART);
5833
5834         rgvmodectl |= MEMMODE_SWMODE_EN;
5835         I915_WRITE(MEMMODECTL, rgvmodectl);
5836
5837         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5838                 DRM_ERROR("stuck trying to change perf mode\n");
5839         mdelay(1);
5840
5841         ironlake_set_drps(dev_priv, fstart);
5842
5843         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
5844                 I915_READ(DDREC) + I915_READ(CSIEC);
5845         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
5846         dev_priv->ips.last_count2 = I915_READ(GFXEC);
5847         dev_priv->ips.last_time2 = ktime_get_raw_ns();
5848
5849         spin_unlock_irq(&mchdev_lock);
5850 }
5851
5852 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
5853 {
5854         u16 rgvswctl;
5855
5856         spin_lock_irq(&mchdev_lock);
5857
5858         rgvswctl = I915_READ16(MEMSWCTL);
5859
5860         /* Ack interrupts, disable EFC interrupt */
5861         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5862         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5863         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5864         I915_WRITE(DEIIR, DE_PCU_EVENT);
5865         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5866
5867         /* Go back to the starting frequency */
5868         ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
5869         mdelay(1);
5870         rgvswctl |= MEMCTL_CMD_STS;
5871         I915_WRITE(MEMSWCTL, rgvswctl);
5872         mdelay(1);
5873
5874         spin_unlock_irq(&mchdev_lock);
5875 }
5876
5877 /* There's a funny hw issue where the hw returns all 0 when reading from
5878  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
5879  * ourselves, instead of doing a rmw cycle (which might result in us clearing
5880  * all limits and the gpu stuck at whatever frequency it is at atm).
5881  */
5882 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
5883 {
5884         u32 limits;
5885
5886         /* Only set the down limit when we've reached the lowest level to avoid
5887          * getting more interrupts, otherwise leave this clear. This prevents a
5888          * race in the hw when coming out of rc6: There's a tiny window where
5889          * the hw runs at the minimal clock before selecting the desired
5890          * frequency, if the down threshold expires in that window we will not
5891          * receive a down interrupt. */
5892         if (INTEL_GEN(dev_priv) >= 9) {
5893                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
5894                 if (val <= dev_priv->rps.min_freq_softlimit)
5895                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
5896         } else {
5897                 limits = dev_priv->rps.max_freq_softlimit << 24;
5898                 if (val <= dev_priv->rps.min_freq_softlimit)
5899                         limits |= dev_priv->rps.min_freq_softlimit << 16;
5900         }
5901
5902         return limits;
5903 }
5904
5905 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
5906 {
5907         int new_power;
5908         u32 threshold_up = 0, threshold_down = 0; /* in % */
5909         u32 ei_up = 0, ei_down = 0;
5910
5911         new_power = dev_priv->rps.power;
5912         switch (dev_priv->rps.power) {
5913         case LOW_POWER:
5914                 if (val > dev_priv->rps.efficient_freq + 1 &&
5915                     val > dev_priv->rps.cur_freq)
5916                         new_power = BETWEEN;
5917                 break;
5918
5919         case BETWEEN:
5920                 if (val <= dev_priv->rps.efficient_freq &&
5921                     val < dev_priv->rps.cur_freq)
5922                         new_power = LOW_POWER;
5923                 else if (val >= dev_priv->rps.rp0_freq &&
5924                          val > dev_priv->rps.cur_freq)
5925                         new_power = HIGH_POWER;
5926                 break;
5927
5928         case HIGH_POWER:
5929                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
5930                     val < dev_priv->rps.cur_freq)
5931                         new_power = BETWEEN;
5932                 break;
5933         }
5934         /* Max/min bins are special */
5935         if (val <= dev_priv->rps.min_freq_softlimit)
5936                 new_power = LOW_POWER;
5937         if (val >= dev_priv->rps.max_freq_softlimit)
5938                 new_power = HIGH_POWER;
5939         if (new_power == dev_priv->rps.power)
5940                 return;
5941
5942         /* Note the units here are not exactly 1us, but 1280ns. */
5943         switch (new_power) {
5944         case LOW_POWER:
5945                 /* Upclock if more than 95% busy over 16ms */
5946                 ei_up = 16000;
5947                 threshold_up = 95;
5948
5949                 /* Downclock if less than 85% busy over 32ms */
5950                 ei_down = 32000;
5951                 threshold_down = 85;
5952                 break;
5953
5954         case BETWEEN:
5955                 /* Upclock if more than 90% busy over 13ms */
5956                 ei_up = 13000;
5957                 threshold_up = 90;
5958
5959                 /* Downclock if less than 75% busy over 32ms */
5960                 ei_down = 32000;
5961                 threshold_down = 75;
5962                 break;
5963
5964         case HIGH_POWER:
5965                 /* Upclock if more than 85% busy over 10ms */
5966                 ei_up = 10000;
5967                 threshold_up = 85;
5968
5969                 /* Downclock if less than 60% busy over 32ms */
5970                 ei_down = 32000;
5971                 threshold_down = 60;
5972                 break;
5973         }
5974
5975         /* When byt can survive without system hang with dynamic
5976          * sw freq adjustments, this restriction can be lifted.
5977          */
5978         if (IS_VALLEYVIEW(dev_priv))
5979                 goto skip_hw_write;
5980
5981         I915_WRITE(GEN6_RP_UP_EI,
5982                    GT_INTERVAL_FROM_US(dev_priv, ei_up));
5983         I915_WRITE(GEN6_RP_UP_THRESHOLD,
5984                    GT_INTERVAL_FROM_US(dev_priv,
5985                                        ei_up * threshold_up / 100));
5986
5987         I915_WRITE(GEN6_RP_DOWN_EI,
5988                    GT_INTERVAL_FROM_US(dev_priv, ei_down));
5989         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
5990                    GT_INTERVAL_FROM_US(dev_priv,
5991                                        ei_down * threshold_down / 100));
5992
5993         I915_WRITE(GEN6_RP_CONTROL,
5994                    GEN6_RP_MEDIA_TURBO |
5995                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5996                    GEN6_RP_MEDIA_IS_GFX |
5997                    GEN6_RP_ENABLE |
5998                    GEN6_RP_UP_BUSY_AVG |
5999                    GEN6_RP_DOWN_IDLE_AVG);
6000
6001 skip_hw_write:
6002         dev_priv->rps.power = new_power;
6003         dev_priv->rps.up_threshold = threshold_up;
6004         dev_priv->rps.down_threshold = threshold_down;
6005         dev_priv->rps.last_adj = 0;
6006 }
6007
6008 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
6009 {
6010         u32 mask = 0;
6011
6012         /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
6013         if (val > dev_priv->rps.min_freq_softlimit)
6014                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
6015         if (val < dev_priv->rps.max_freq_softlimit)
6016                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
6017
6018         mask &= dev_priv->pm_rps_events;
6019
6020         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
6021 }
6022
6023 /* gen6_set_rps is called to update the frequency request, but should also be
6024  * called when the range (min_delay and max_delay) is modified so that we can
6025  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
6026 static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
6027 {
6028         /* min/max delay may still have been modified so be sure to
6029          * write the limits value.
6030          */
6031         if (val != dev_priv->rps.cur_freq) {
6032                 gen6_set_rps_thresholds(dev_priv, val);
6033
6034                 if (INTEL_GEN(dev_priv) >= 9)
6035                         I915_WRITE(GEN6_RPNSWREQ,
6036                                    GEN9_FREQUENCY(val));
6037                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6038                         I915_WRITE(GEN6_RPNSWREQ,
6039                                    HSW_FREQUENCY(val));
6040                 else
6041                         I915_WRITE(GEN6_RPNSWREQ,
6042                                    GEN6_FREQUENCY(val) |
6043                                    GEN6_OFFSET(0) |
6044                                    GEN6_AGGRESSIVE_TURBO);
6045         }
6046
6047         /* Make sure we continue to get interrupts
6048          * until we hit the minimum or maximum frequencies.
6049          */
6050         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
6051         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
6052
6053         dev_priv->rps.cur_freq = val;
6054         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
6055
6056         return 0;
6057 }
6058
6059 static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
6060 {
6061         int err;
6062
6063         if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
6064                       "Odd GPU freq value\n"))
6065                 val &= ~1;
6066
6067         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
6068
6069         if (val != dev_priv->rps.cur_freq) {
6070                 err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
6071                 if (err)
6072                         return err;
6073
6074                 gen6_set_rps_thresholds(dev_priv, val);
6075         }
6076
6077         dev_priv->rps.cur_freq = val;
6078         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
6079
6080         return 0;
6081 }
6082
6083 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
6084  *
6085  * * If Gfx is Idle, then
6086  * 1. Forcewake Media well.
6087  * 2. Request idle freq.
6088  * 3. Release Forcewake of Media well.
6089 */
6090 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
6091 {
6092         u32 val = dev_priv->rps.idle_freq;
6093         int err;
6094
6095         if (dev_priv->rps.cur_freq <= val)
6096                 return;
6097
6098         /* The punit delays the write of the frequency and voltage until it
6099          * determines the GPU is awake. During normal usage we don't want to
6100          * waste power changing the frequency if the GPU is sleeping (rc6).
6101          * However, the GPU and driver is now idle and we do not want to delay
6102          * switching to minimum voltage (reducing power whilst idle) as we do
6103          * not expect to be woken in the near future and so must flush the
6104          * change by waking the device.
6105          *
6106          * We choose to take the media powerwell (either would do to trick the
6107          * punit into committing the voltage change) as that takes a lot less
6108          * power than the render powerwell.
6109          */
6110         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
6111         err = valleyview_set_rps(dev_priv, val);
6112         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
6113
6114         if (err)
6115                 DRM_ERROR("Failed to set RPS for idle\n");
6116 }
6117
6118 void gen6_rps_busy(struct drm_i915_private *dev_priv)
6119 {
6120         mutex_lock(&dev_priv->rps.hw_lock);
6121         if (dev_priv->rps.enabled) {
6122                 u8 freq;
6123
6124                 if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED)
6125                         gen6_rps_reset_ei(dev_priv);
6126                 I915_WRITE(GEN6_PMINTRMSK,
6127                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
6128
6129                 gen6_enable_rps_interrupts(dev_priv);
6130
6131                 /* Use the user's desired frequency as a guide, but for better
6132                  * performance, jump directly to RPe as our starting frequency.
6133                  */
6134                 freq = max(dev_priv->rps.cur_freq,
6135                            dev_priv->rps.efficient_freq);
6136
6137                 if (intel_set_rps(dev_priv,
6138                                   clamp(freq,
6139                                         dev_priv->rps.min_freq_softlimit,
6140                                         dev_priv->rps.max_freq_softlimit)))
6141                         DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
6142         }
6143         mutex_unlock(&dev_priv->rps.hw_lock);
6144 }
6145
6146 void gen6_rps_idle(struct drm_i915_private *dev_priv)
6147 {
6148         /* Flush our bottom-half so that it does not race with us
6149          * setting the idle frequency and so that it is bounded by
6150          * our rpm wakeref. And then disable the interrupts to stop any
6151          * futher RPS reclocking whilst we are asleep.
6152          */
6153         gen6_disable_rps_interrupts(dev_priv);
6154
6155         mutex_lock(&dev_priv->rps.hw_lock);
6156         if (dev_priv->rps.enabled) {
6157                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6158                         vlv_set_rps_idle(dev_priv);
6159                 else
6160                         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
6161                 dev_priv->rps.last_adj = 0;
6162                 I915_WRITE(GEN6_PMINTRMSK,
6163                            gen6_sanitize_rps_pm_mask(dev_priv, ~0));
6164         }
6165         mutex_unlock(&dev_priv->rps.hw_lock);
6166 }
6167
6168 void gen6_rps_boost(struct drm_i915_gem_request *rq,
6169                     struct intel_rps_client *rps)
6170 {
6171         struct drm_i915_private *i915 = rq->i915;
6172         bool boost;
6173
6174         /* This is intentionally racy! We peek at the state here, then
6175          * validate inside the RPS worker.
6176          */
6177         if (!i915->rps.enabled)
6178                 return;
6179
6180         boost = false;
6181         spin_lock_irq(&rq->lock);
6182         if (!rq->waitboost && !i915_gem_request_completed(rq)) {
6183                 atomic_inc(&i915->rps.num_waiters);
6184                 rq->waitboost = true;
6185                 boost = true;
6186         }
6187         spin_unlock_irq(&rq->lock);
6188         if (!boost)
6189                 return;
6190
6191         if (READ_ONCE(i915->rps.cur_freq) < i915->rps.boost_freq)
6192                 schedule_work(&i915->rps.work);
6193
6194         atomic_inc(rps ? &rps->boosts : &i915->rps.boosts);
6195 }
6196
6197 int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
6198 {
6199         int err;
6200
6201         lockdep_assert_held(&dev_priv->rps.hw_lock);
6202         GEM_BUG_ON(val > dev_priv->rps.max_freq);
6203         GEM_BUG_ON(val < dev_priv->rps.min_freq);
6204
6205         if (!dev_priv->rps.enabled) {
6206                 dev_priv->rps.cur_freq = val;
6207                 return 0;
6208         }
6209
6210         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6211                 err = valleyview_set_rps(dev_priv, val);
6212         else
6213                 err = gen6_set_rps(dev_priv, val);
6214
6215         return err;
6216 }
6217
6218 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
6219 {
6220         I915_WRITE(GEN6_RC_CONTROL, 0);
6221         I915_WRITE(GEN9_PG_ENABLE, 0);
6222 }
6223
6224 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
6225 {
6226         I915_WRITE(GEN6_RP_CONTROL, 0);
6227 }
6228
6229 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
6230 {
6231         I915_WRITE(GEN6_RC_CONTROL, 0);
6232         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6233         I915_WRITE(GEN6_RP_CONTROL, 0);
6234 }
6235
6236 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
6237 {
6238         I915_WRITE(GEN6_RC_CONTROL, 0);
6239 }
6240
6241 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
6242 {
6243         /* we're doing forcewake before Disabling RC6,
6244          * This what the BIOS expects when going into suspend */
6245         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6246
6247         I915_WRITE(GEN6_RC_CONTROL, 0);
6248
6249         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6250 }
6251
6252 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
6253 {
6254         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6255                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
6256                         mode = GEN6_RC_CTL_RC6_ENABLE;
6257                 else
6258                         mode = 0;
6259         }
6260         if (HAS_RC6p(dev_priv))
6261                 DRM_DEBUG_DRIVER("Enabling RC6 states: "
6262                                  "RC6 %s RC6p %s RC6pp %s\n",
6263                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
6264                                  onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
6265                                  onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
6266
6267         else
6268                 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
6269                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
6270 }
6271
6272 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
6273 {
6274         struct i915_ggtt *ggtt = &dev_priv->ggtt;
6275         bool enable_rc6 = true;
6276         unsigned long rc6_ctx_base;
6277         u32 rc_ctl;
6278         int rc_sw_target;
6279
6280         rc_ctl = I915_READ(GEN6_RC_CONTROL);
6281         rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
6282                        RC_SW_TARGET_STATE_SHIFT;
6283         DRM_DEBUG_DRIVER("BIOS enabled RC states: "
6284                          "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
6285                          onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
6286                          onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
6287                          rc_sw_target);
6288
6289         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
6290                 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
6291                 enable_rc6 = false;
6292         }
6293
6294         /*
6295          * The exact context size is not known for BXT, so assume a page size
6296          * for this check.
6297          */
6298         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
6299         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
6300               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
6301                                         ggtt->stolen_reserved_size))) {
6302                 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
6303                 enable_rc6 = false;
6304         }
6305
6306         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
6307               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
6308               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
6309               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
6310                 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
6311                 enable_rc6 = false;
6312         }
6313
6314         if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
6315             !I915_READ(GEN8_PUSHBUS_ENABLE) ||
6316             !I915_READ(GEN8_PUSHBUS_SHIFT)) {
6317                 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
6318                 enable_rc6 = false;
6319         }
6320
6321         if (!I915_READ(GEN6_GFXPAUSE)) {
6322                 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
6323                 enable_rc6 = false;
6324         }
6325
6326         if (!I915_READ(GEN8_MISC_CTRL0)) {
6327                 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
6328                 enable_rc6 = false;
6329         }
6330
6331         return enable_rc6;
6332 }
6333
6334 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
6335 {
6336         /* No RC6 before Ironlake and code is gone for ilk. */
6337         if (INTEL_INFO(dev_priv)->gen < 6)
6338                 return 0;
6339
6340         if (!enable_rc6)
6341                 return 0;
6342
6343         if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
6344                 DRM_INFO("RC6 disabled by BIOS\n");
6345                 return 0;
6346         }
6347
6348         /* Respect the kernel parameter if it is set */
6349         if (enable_rc6 >= 0) {
6350                 int mask;
6351
6352                 if (HAS_RC6p(dev_priv))
6353                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
6354                                INTEL_RC6pp_ENABLE;
6355                 else
6356                         mask = INTEL_RC6_ENABLE;
6357
6358                 if ((enable_rc6 & mask) != enable_rc6)
6359                         DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
6360                                          "(requested %d, valid %d)\n",
6361                                          enable_rc6 & mask, enable_rc6, mask);
6362
6363                 return enable_rc6 & mask;
6364         }
6365
6366         if (IS_IVYBRIDGE(dev_priv))
6367                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
6368
6369         return INTEL_RC6_ENABLE;
6370 }
6371
6372 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
6373 {
6374         /* All of these values are in units of 50MHz */
6375
6376         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
6377         if (IS_GEN9_LP(dev_priv)) {
6378                 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
6379                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
6380                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
6381                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
6382         } else {
6383                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6384                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
6385                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
6386                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
6387         }
6388         /* hw_max = RP0 until we check for overclocking */
6389         dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
6390
6391         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
6392         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
6393             IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
6394                 u32 ddcc_status = 0;
6395
6396                 if (sandybridge_pcode_read(dev_priv,
6397                                            HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
6398                                            &ddcc_status) == 0)
6399                         dev_priv->rps.efficient_freq =
6400                                 clamp_t(u8,
6401                                         ((ddcc_status >> 8) & 0xff),
6402                                         dev_priv->rps.min_freq,
6403                                         dev_priv->rps.max_freq);
6404         }
6405
6406         if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
6407                 /* Store the frequency values in 16.66 MHZ units, which is
6408                  * the natural hardware unit for SKL
6409                  */
6410                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
6411                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
6412                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
6413                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
6414                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
6415         }
6416 }
6417
6418 static void reset_rps(struct drm_i915_private *dev_priv,
6419                       int (*set)(struct drm_i915_private *, u8))
6420 {
6421         u8 freq = dev_priv->rps.cur_freq;
6422
6423         /* force a reset */
6424         dev_priv->rps.power = -1;
6425         dev_priv->rps.cur_freq = -1;
6426
6427         if (set(dev_priv, freq))
6428                 DRM_ERROR("Failed to reset RPS to initial values\n");
6429 }
6430
6431 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
6432 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
6433 {
6434         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6435
6436         /* Program defaults and thresholds for RPS*/
6437         I915_WRITE(GEN6_RC_VIDEO_FREQ,
6438                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
6439
6440         /* 1 second timeout*/
6441         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
6442                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
6443
6444         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
6445
6446         /* Leaning on the below call to gen6_set_rps to program/setup the
6447          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
6448          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
6449         reset_rps(dev_priv, gen6_set_rps);
6450
6451         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6452 }
6453
6454 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
6455 {
6456         struct intel_engine_cs *engine;
6457         enum intel_engine_id id;
6458         uint32_t rc6_mask = 0;
6459
6460         /* 1a: Software RC state - RC0 */
6461         I915_WRITE(GEN6_RC_STATE, 0);
6462
6463         /* 1b: Get forcewake during program sequence. Although the driver
6464          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6465         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6466
6467         /* 2a: Disable RC states. */
6468         I915_WRITE(GEN6_RC_CONTROL, 0);
6469
6470         /* 2b: Program RC6 thresholds.*/
6471
6472         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
6473         if (IS_SKYLAKE(dev_priv))
6474                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
6475         else
6476                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
6477         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6478         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6479         for_each_engine(engine, dev_priv, id)
6480                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6481
6482         if (HAS_GUC(dev_priv))
6483                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
6484
6485         I915_WRITE(GEN6_RC_SLEEP, 0);
6486
6487         /* 2c: Program Coarse Power Gating Policies. */
6488         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
6489         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
6490
6491         /* 3a: Enable RC6 */
6492         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6493                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
6494         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
6495         I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
6496         I915_WRITE(GEN6_RC_CONTROL,
6497                    GEN6_RC_CTL_HW_ENABLE | GEN6_RC_CTL_EI_MODE(1) | rc6_mask);
6498
6499         /*
6500          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
6501          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
6502          */
6503         if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
6504                 I915_WRITE(GEN9_PG_ENABLE, 0);
6505         else
6506                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
6507                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
6508
6509         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6510 }
6511
6512 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6513 {
6514         struct intel_engine_cs *engine;
6515         enum intel_engine_id id;
6516         uint32_t rc6_mask = 0;
6517
6518         /* 1a: Software RC state - RC0 */
6519         I915_WRITE(GEN6_RC_STATE, 0);
6520
6521         /* 1c & 1d: Get forcewake during program sequence. Although the driver
6522          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6523         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6524
6525         /* 2a: Disable RC states. */
6526         I915_WRITE(GEN6_RC_CONTROL, 0);
6527
6528         /* 2b: Program RC6 thresholds.*/
6529         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6530         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6531         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6532         for_each_engine(engine, dev_priv, id)
6533                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6534         I915_WRITE(GEN6_RC_SLEEP, 0);
6535         if (IS_BROADWELL(dev_priv))
6536                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
6537         else
6538                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6539
6540         /* 3: Enable RC6 */
6541         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6542                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
6543         intel_print_rc6_info(dev_priv, rc6_mask);
6544         if (IS_BROADWELL(dev_priv))
6545                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
6546                                 GEN7_RC_CTL_TO_MODE |
6547                                 rc6_mask);
6548         else
6549                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
6550                                 GEN6_RC_CTL_EI_MODE(1) |
6551                                 rc6_mask);
6552
6553         /* 4 Program defaults and thresholds for RPS*/
6554         I915_WRITE(GEN6_RPNSWREQ,
6555                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
6556         I915_WRITE(GEN6_RC_VIDEO_FREQ,
6557                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
6558         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
6559         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
6560
6561         /* Docs recommend 900MHz, and 300 MHz respectively */
6562         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6563                    dev_priv->rps.max_freq_softlimit << 24 |
6564                    dev_priv->rps.min_freq_softlimit << 16);
6565
6566         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
6567         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
6568         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
6569         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
6570
6571         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6572
6573         /* 5: Enable RPS */
6574         I915_WRITE(GEN6_RP_CONTROL,
6575                    GEN6_RP_MEDIA_TURBO |
6576                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6577                    GEN6_RP_MEDIA_IS_GFX |
6578                    GEN6_RP_ENABLE |
6579                    GEN6_RP_UP_BUSY_AVG |
6580                    GEN6_RP_DOWN_IDLE_AVG);
6581
6582         /* 6: Ring frequency + overclocking (our driver does this later */
6583
6584         reset_rps(dev_priv, gen6_set_rps);
6585
6586         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6587 }
6588
6589 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
6590 {
6591         struct intel_engine_cs *engine;
6592         enum intel_engine_id id;
6593         u32 rc6vids, rc6_mask = 0;
6594         u32 gtfifodbg;
6595         int rc6_mode;
6596         int ret;
6597
6598         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6599
6600         /* Here begins a magic sequence of register writes to enable
6601          * auto-downclocking.
6602          *
6603          * Perhaps there might be some value in exposing these to
6604          * userspace...
6605          */
6606         I915_WRITE(GEN6_RC_STATE, 0);
6607
6608         /* Clear the DBG now so we don't confuse earlier errors */
6609         gtfifodbg = I915_READ(GTFIFODBG);
6610         if (gtfifodbg) {
6611                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
6612                 I915_WRITE(GTFIFODBG, gtfifodbg);
6613         }
6614
6615         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6616
6617         /* disable the counters and set deterministic thresholds */
6618         I915_WRITE(GEN6_RC_CONTROL, 0);
6619
6620         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6621         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6622         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6623         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6624         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6625
6626         for_each_engine(engine, dev_priv, id)
6627                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6628
6629         I915_WRITE(GEN6_RC_SLEEP, 0);
6630         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
6631         if (IS_IVYBRIDGE(dev_priv))
6632                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
6633         else
6634                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
6635         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
6636         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6637
6638         /* Check if we are enabling RC6 */
6639         rc6_mode = intel_enable_rc6();
6640         if (rc6_mode & INTEL_RC6_ENABLE)
6641                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
6642
6643         /* We don't use those on Haswell */
6644         if (!IS_HASWELL(dev_priv)) {
6645                 if (rc6_mode & INTEL_RC6p_ENABLE)
6646                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
6647
6648                 if (rc6_mode & INTEL_RC6pp_ENABLE)
6649                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
6650         }
6651
6652         intel_print_rc6_info(dev_priv, rc6_mask);
6653
6654         I915_WRITE(GEN6_RC_CONTROL,
6655                    rc6_mask |
6656                    GEN6_RC_CTL_EI_MODE(1) |
6657                    GEN6_RC_CTL_HW_ENABLE);
6658
6659         /* Power down if completely idle for over 50ms */
6660         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
6661         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6662
6663         reset_rps(dev_priv, gen6_set_rps);
6664
6665         rc6vids = 0;
6666         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
6667         if (IS_GEN6(dev_priv) && ret) {
6668                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
6669         } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
6670                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
6671                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
6672                 rc6vids &= 0xffff00;
6673                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
6674                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
6675                 if (ret)
6676                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
6677         }
6678
6679         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6680 }
6681
6682 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
6683 {
6684         int min_freq = 15;
6685         unsigned int gpu_freq;
6686         unsigned int max_ia_freq, min_ring_freq;
6687         unsigned int max_gpu_freq, min_gpu_freq;
6688         int scaling_factor = 180;
6689         struct cpufreq_policy *policy;
6690
6691         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6692
6693         policy = cpufreq_cpu_get(0);
6694         if (policy) {
6695                 max_ia_freq = policy->cpuinfo.max_freq;
6696                 cpufreq_cpu_put(policy);
6697         } else {
6698                 /*
6699                  * Default to measured freq if none found, PCU will ensure we
6700                  * don't go over
6701                  */
6702                 max_ia_freq = tsc_khz;
6703         }
6704
6705         /* Convert from kHz to MHz */
6706         max_ia_freq /= 1000;
6707
6708         min_ring_freq = I915_READ(DCLK) & 0xf;
6709         /* convert DDR frequency from units of 266.6MHz to bandwidth */
6710         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
6711
6712         if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
6713                 /* Convert GT frequency to 50 HZ units */
6714                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
6715                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
6716         } else {
6717                 min_gpu_freq = dev_priv->rps.min_freq;
6718                 max_gpu_freq = dev_priv->rps.max_freq;
6719         }
6720
6721         /*
6722          * For each potential GPU frequency, load a ring frequency we'd like
6723          * to use for memory access.  We do this by specifying the IA frequency
6724          * the PCU should use as a reference to determine the ring frequency.
6725          */
6726         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
6727                 int diff = max_gpu_freq - gpu_freq;
6728                 unsigned int ia_freq = 0, ring_freq = 0;
6729
6730                 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
6731                         /*
6732                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
6733                          * No floor required for ring frequency on SKL.
6734                          */
6735                         ring_freq = gpu_freq;
6736                 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
6737                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
6738                         ring_freq = max(min_ring_freq, gpu_freq);
6739                 } else if (IS_HASWELL(dev_priv)) {
6740                         ring_freq = mult_frac(gpu_freq, 5, 4);
6741                         ring_freq = max(min_ring_freq, ring_freq);
6742                         /* leave ia_freq as the default, chosen by cpufreq */
6743                 } else {
6744                         /* On older processors, there is no separate ring
6745                          * clock domain, so in order to boost the bandwidth
6746                          * of the ring, we need to upclock the CPU (ia_freq).
6747                          *
6748                          * For GPU frequencies less than 750MHz,
6749                          * just use the lowest ring freq.
6750                          */
6751                         if (gpu_freq < min_freq)
6752                                 ia_freq = 800;
6753                         else
6754                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
6755                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
6756                 }
6757
6758                 sandybridge_pcode_write(dev_priv,
6759                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
6760                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
6761                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
6762                                         gpu_freq);
6763         }
6764 }
6765
6766 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
6767 {
6768         u32 val, rp0;
6769
6770         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
6771
6772         switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
6773         case 8:
6774                 /* (2 * 4) config */
6775                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
6776                 break;
6777         case 12:
6778                 /* (2 * 6) config */
6779                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
6780                 break;
6781         case 16:
6782                 /* (2 * 8) config */
6783         default:
6784                 /* Setting (2 * 8) Min RP0 for any other combination */
6785                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
6786                 break;
6787         }
6788
6789         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
6790
6791         return rp0;
6792 }
6793
6794 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
6795 {
6796         u32 val, rpe;
6797
6798         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
6799         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
6800
6801         return rpe;
6802 }
6803
6804 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
6805 {
6806         u32 val, rp1;
6807
6808         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
6809         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
6810
6811         return rp1;
6812 }
6813
6814 static u32 cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
6815 {
6816         u32 val, rpn;
6817
6818         val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
6819         rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
6820                        FB_GFX_FREQ_FUSE_MASK);
6821
6822         return rpn;
6823 }
6824
6825 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
6826 {
6827         u32 val, rp1;
6828
6829         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
6830
6831         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
6832
6833         return rp1;
6834 }
6835
6836 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
6837 {
6838         u32 val, rp0;
6839
6840         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
6841
6842         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
6843         /* Clamp to max */
6844         rp0 = min_t(u32, rp0, 0xea);
6845
6846         return rp0;
6847 }
6848
6849 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
6850 {
6851         u32 val, rpe;
6852
6853         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
6854         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
6855         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
6856         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
6857
6858         return rpe;
6859 }
6860
6861 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
6862 {
6863         u32 val;
6864
6865         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
6866         /*
6867          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
6868          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
6869          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
6870          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
6871          * to make sure it matches what Punit accepts.
6872          */
6873         return max_t(u32, val, 0xc0);
6874 }
6875
6876 /* Check that the pctx buffer wasn't move under us. */
6877 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
6878 {
6879         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
6880
6881         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
6882                              dev_priv->vlv_pctx->stolen->start);
6883 }
6884
6885
6886 /* Check that the pcbr address is not empty. */
6887 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
6888 {
6889         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
6890
6891         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
6892 }
6893
6894 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
6895 {
6896         struct i915_ggtt *ggtt = &dev_priv->ggtt;
6897         unsigned long pctx_paddr, paddr;
6898         u32 pcbr;
6899         int pctx_size = 32*1024;
6900
6901         pcbr = I915_READ(VLV_PCBR);
6902         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
6903                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
6904                 paddr = (dev_priv->mm.stolen_base +
6905                          (ggtt->stolen_size - pctx_size));
6906
6907                 pctx_paddr = (paddr & (~4095));
6908                 I915_WRITE(VLV_PCBR, pctx_paddr);
6909         }
6910
6911         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
6912 }
6913
6914 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
6915 {
6916         struct drm_i915_gem_object *pctx;
6917         unsigned long pctx_paddr;
6918         u32 pcbr;
6919         int pctx_size = 24*1024;
6920
6921         pcbr = I915_READ(VLV_PCBR);
6922         if (pcbr) {
6923                 /* BIOS set it up already, grab the pre-alloc'd space */
6924                 int pcbr_offset;
6925
6926                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
6927                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv,
6928                                                                       pcbr_offset,
6929                                                                       I915_GTT_OFFSET_NONE,
6930                                                                       pctx_size);
6931                 goto out;
6932         }
6933
6934         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
6935
6936         /*
6937          * From the Gunit register HAS:
6938          * The Gfx driver is expected to program this register and ensure
6939          * proper allocation within Gfx stolen memory.  For example, this
6940          * register should be programmed such than the PCBR range does not
6941          * overlap with other ranges, such as the frame buffer, protected
6942          * memory, or any other relevant ranges.
6943          */
6944         pctx = i915_gem_object_create_stolen(dev_priv, pctx_size);
6945         if (!pctx) {
6946                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
6947                 goto out;
6948         }
6949
6950         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
6951         I915_WRITE(VLV_PCBR, pctx_paddr);
6952
6953 out:
6954         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
6955         dev_priv->vlv_pctx = pctx;
6956 }
6957
6958 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
6959 {
6960         if (WARN_ON(!dev_priv->vlv_pctx))
6961                 return;
6962
6963         i915_gem_object_put(dev_priv->vlv_pctx);
6964         dev_priv->vlv_pctx = NULL;
6965 }
6966
6967 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
6968 {
6969         dev_priv->rps.gpll_ref_freq =
6970                 vlv_get_cck_clock(dev_priv, "GPLL ref",
6971                                   CCK_GPLL_CLOCK_CONTROL,
6972                                   dev_priv->czclk_freq);
6973
6974         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
6975                          dev_priv->rps.gpll_ref_freq);
6976 }
6977
6978 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
6979 {
6980         u32 val;
6981
6982         valleyview_setup_pctx(dev_priv);
6983
6984         vlv_init_gpll_ref_freq(dev_priv);
6985
6986         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6987         switch ((val >> 6) & 3) {
6988         case 0:
6989         case 1:
6990                 dev_priv->mem_freq = 800;
6991                 break;
6992         case 2:
6993                 dev_priv->mem_freq = 1066;
6994                 break;
6995         case 3:
6996                 dev_priv->mem_freq = 1333;
6997                 break;
6998         }
6999         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
7000
7001         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
7002         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
7003         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7004                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
7005                          dev_priv->rps.max_freq);
7006
7007         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
7008         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7009                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
7010                          dev_priv->rps.efficient_freq);
7011
7012         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
7013         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7014                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7015                          dev_priv->rps.rp1_freq);
7016
7017         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
7018         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7019                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
7020                          dev_priv->rps.min_freq);
7021 }
7022
7023 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
7024 {
7025         u32 val;
7026
7027         cherryview_setup_pctx(dev_priv);
7028
7029         vlv_init_gpll_ref_freq(dev_priv);
7030
7031         mutex_lock(&dev_priv->sb_lock);
7032         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
7033         mutex_unlock(&dev_priv->sb_lock);
7034
7035         switch ((val >> 2) & 0x7) {
7036         case 3:
7037                 dev_priv->mem_freq = 2000;
7038                 break;
7039         default:
7040                 dev_priv->mem_freq = 1600;
7041                 break;
7042         }
7043         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
7044
7045         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
7046         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
7047         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7048                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
7049                          dev_priv->rps.max_freq);
7050
7051         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
7052         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7053                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
7054                          dev_priv->rps.efficient_freq);
7055
7056         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
7057         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7058                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7059                          dev_priv->rps.rp1_freq);
7060
7061         dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
7062         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7063                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
7064                          dev_priv->rps.min_freq);
7065
7066         WARN_ONCE((dev_priv->rps.max_freq |
7067                    dev_priv->rps.efficient_freq |
7068                    dev_priv->rps.rp1_freq |
7069                    dev_priv->rps.min_freq) & 1,
7070                   "Odd GPU freq values\n");
7071 }
7072
7073 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
7074 {
7075         valleyview_cleanup_pctx(dev_priv);
7076 }
7077
7078 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
7079 {
7080         struct intel_engine_cs *engine;
7081         enum intel_engine_id id;
7082         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
7083
7084         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7085
7086         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
7087                                              GT_FIFO_FREE_ENTRIES_CHV);
7088         if (gtfifodbg) {
7089                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
7090                                  gtfifodbg);
7091                 I915_WRITE(GTFIFODBG, gtfifodbg);
7092         }
7093
7094         cherryview_check_pctx(dev_priv);
7095
7096         /* 1a & 1b: Get forcewake during program sequence. Although the driver
7097          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
7098         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7099
7100         /*  Disable RC states. */
7101         I915_WRITE(GEN6_RC_CONTROL, 0);
7102
7103         /* 2a: Program RC6 thresholds.*/
7104         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
7105         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
7106         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
7107
7108         for_each_engine(engine, dev_priv, id)
7109                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7110         I915_WRITE(GEN6_RC_SLEEP, 0);
7111
7112         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
7113         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
7114
7115         /* allows RC6 residency counter to work */
7116         I915_WRITE(VLV_COUNTER_CONTROL,
7117                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
7118                                       VLV_MEDIA_RC6_COUNT_EN |
7119                                       VLV_RENDER_RC6_COUNT_EN));
7120
7121         /* For now we assume BIOS is allocating and populating the PCBR  */
7122         pcbr = I915_READ(VLV_PCBR);
7123
7124         /* 3: Enable RC6 */
7125         if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
7126             (pcbr >> VLV_PCBR_ADDR_SHIFT))
7127                 rc6_mode = GEN7_RC_CTL_TO_MODE;
7128
7129         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
7130
7131         /* 4 Program defaults and thresholds for RPS*/
7132         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7133         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
7134         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
7135         I915_WRITE(GEN6_RP_UP_EI, 66000);
7136         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
7137
7138         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7139
7140         /* 5: Enable RPS */
7141         I915_WRITE(GEN6_RP_CONTROL,
7142                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
7143                    GEN6_RP_MEDIA_IS_GFX |
7144                    GEN6_RP_ENABLE |
7145                    GEN6_RP_UP_BUSY_AVG |
7146                    GEN6_RP_DOWN_IDLE_AVG);
7147
7148         /* Setting Fixed Bias */
7149         val = VLV_OVERRIDE_EN |
7150                   VLV_SOC_TDP_EN |
7151                   CHV_BIAS_CPU_50_SOC_50;
7152         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
7153
7154         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
7155
7156         /* RPS code assumes GPLL is used */
7157         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
7158
7159         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
7160         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
7161
7162         reset_rps(dev_priv, valleyview_set_rps);
7163
7164         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7165 }
7166
7167 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
7168 {
7169         struct intel_engine_cs *engine;
7170         enum intel_engine_id id;
7171         u32 gtfifodbg, val, rc6_mode = 0;
7172
7173         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7174
7175         valleyview_check_pctx(dev_priv);
7176
7177         gtfifodbg = I915_READ(GTFIFODBG);
7178         if (gtfifodbg) {
7179                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
7180                                  gtfifodbg);
7181                 I915_WRITE(GTFIFODBG, gtfifodbg);
7182         }
7183
7184         /* If VLV, Forcewake all wells, else re-direct to regular path */
7185         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7186
7187         /*  Disable RC states. */
7188         I915_WRITE(GEN6_RC_CONTROL, 0);
7189
7190         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7191         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
7192         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
7193         I915_WRITE(GEN6_RP_UP_EI, 66000);
7194         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
7195
7196         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7197
7198         I915_WRITE(GEN6_RP_CONTROL,
7199                    GEN6_RP_MEDIA_TURBO |
7200                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
7201                    GEN6_RP_MEDIA_IS_GFX |
7202                    GEN6_RP_ENABLE |
7203                    GEN6_RP_UP_BUSY_AVG |
7204                    GEN6_RP_DOWN_IDLE_CONT);
7205
7206         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
7207         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7208         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7209
7210         for_each_engine(engine, dev_priv, id)
7211                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7212
7213         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
7214
7215         /* allows RC6 residency counter to work */
7216         I915_WRITE(VLV_COUNTER_CONTROL,
7217                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
7218                                       VLV_MEDIA_RC0_COUNT_EN |
7219                                       VLV_RENDER_RC0_COUNT_EN |
7220                                       VLV_MEDIA_RC6_COUNT_EN |
7221                                       VLV_RENDER_RC6_COUNT_EN));
7222
7223         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
7224                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
7225
7226         intel_print_rc6_info(dev_priv, rc6_mode);
7227
7228         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
7229
7230         /* Setting Fixed Bias */
7231         val = VLV_OVERRIDE_EN |
7232                   VLV_SOC_TDP_EN |
7233                   VLV_BIAS_CPU_125_SOC_875;
7234         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
7235
7236         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
7237
7238         /* RPS code assumes GPLL is used */
7239         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
7240
7241         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
7242         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
7243
7244         reset_rps(dev_priv, valleyview_set_rps);
7245
7246         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7247 }
7248
7249 static unsigned long intel_pxfreq(u32 vidfreq)
7250 {
7251         unsigned long freq;
7252         int div = (vidfreq & 0x3f0000) >> 16;
7253         int post = (vidfreq & 0x3000) >> 12;
7254         int pre = (vidfreq & 0x7);
7255
7256         if (!pre)
7257                 return 0;
7258
7259         freq = ((div * 133333) / ((1<<post) * pre));
7260
7261         return freq;
7262 }
7263
7264 static const struct cparams {
7265         u16 i;
7266         u16 t;
7267         u16 m;
7268         u16 c;
7269 } cparams[] = {
7270         { 1, 1333, 301, 28664 },
7271         { 1, 1066, 294, 24460 },
7272         { 1, 800, 294, 25192 },
7273         { 0, 1333, 276, 27605 },
7274         { 0, 1066, 276, 27605 },
7275         { 0, 800, 231, 23784 },
7276 };
7277
7278 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
7279 {
7280         u64 total_count, diff, ret;
7281         u32 count1, count2, count3, m = 0, c = 0;
7282         unsigned long now = jiffies_to_msecs(jiffies), diff1;
7283         int i;
7284
7285         lockdep_assert_held(&mchdev_lock);
7286
7287         diff1 = now - dev_priv->ips.last_time1;
7288
7289         /* Prevent division-by-zero if we are asking too fast.
7290          * Also, we don't get interesting results if we are polling
7291          * faster than once in 10ms, so just return the saved value
7292          * in such cases.
7293          */
7294         if (diff1 <= 10)
7295                 return dev_priv->ips.chipset_power;
7296
7297         count1 = I915_READ(DMIEC);
7298         count2 = I915_READ(DDREC);
7299         count3 = I915_READ(CSIEC);
7300
7301         total_count = count1 + count2 + count3;
7302
7303         /* FIXME: handle per-counter overflow */
7304         if (total_count < dev_priv->ips.last_count1) {
7305                 diff = ~0UL - dev_priv->ips.last_count1;
7306                 diff += total_count;
7307         } else {
7308                 diff = total_count - dev_priv->ips.last_count1;
7309         }
7310
7311         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
7312                 if (cparams[i].i == dev_priv->ips.c_m &&
7313                     cparams[i].t == dev_priv->ips.r_t) {
7314                         m = cparams[i].m;
7315                         c = cparams[i].c;
7316                         break;
7317                 }
7318         }
7319
7320         diff = div_u64(diff, diff1);
7321         ret = ((m * diff) + c);
7322         ret = div_u64(ret, 10);
7323
7324         dev_priv->ips.last_count1 = total_count;
7325         dev_priv->ips.last_time1 = now;
7326
7327         dev_priv->ips.chipset_power = ret;
7328
7329         return ret;
7330 }
7331
7332 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
7333 {
7334         unsigned long val;
7335
7336         if (INTEL_INFO(dev_priv)->gen != 5)
7337                 return 0;
7338
7339         spin_lock_irq(&mchdev_lock);
7340
7341         val = __i915_chipset_val(dev_priv);
7342
7343         spin_unlock_irq(&mchdev_lock);
7344
7345         return val;
7346 }
7347
7348 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
7349 {
7350         unsigned long m, x, b;
7351         u32 tsfs;
7352
7353         tsfs = I915_READ(TSFS);
7354
7355         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
7356         x = I915_READ8(TR1);
7357
7358         b = tsfs & TSFS_INTR_MASK;
7359
7360         return ((m * x) / 127) - b;
7361 }
7362
7363 static int _pxvid_to_vd(u8 pxvid)
7364 {
7365         if (pxvid == 0)
7366                 return 0;
7367
7368         if (pxvid >= 8 && pxvid < 31)
7369                 pxvid = 31;
7370
7371         return (pxvid + 2) * 125;
7372 }
7373
7374 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
7375 {
7376         const int vd = _pxvid_to_vd(pxvid);
7377         const int vm = vd - 1125;
7378
7379         if (INTEL_INFO(dev_priv)->is_mobile)
7380                 return vm > 0 ? vm : 0;
7381
7382         return vd;
7383 }
7384
7385 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
7386 {
7387         u64 now, diff, diffms;
7388         u32 count;
7389
7390         lockdep_assert_held(&mchdev_lock);
7391
7392         now = ktime_get_raw_ns();
7393         diffms = now - dev_priv->ips.last_time2;
7394         do_div(diffms, NSEC_PER_MSEC);
7395
7396         /* Don't divide by 0 */
7397         if (!diffms)
7398                 return;
7399
7400         count = I915_READ(GFXEC);
7401
7402         if (count < dev_priv->ips.last_count2) {
7403                 diff = ~0UL - dev_priv->ips.last_count2;
7404                 diff += count;
7405         } else {
7406                 diff = count - dev_priv->ips.last_count2;
7407         }
7408
7409         dev_priv->ips.last_count2 = count;
7410         dev_priv->ips.last_time2 = now;
7411
7412         /* More magic constants... */
7413         diff = diff * 1181;
7414         diff = div_u64(diff, diffms * 10);
7415         dev_priv->ips.gfx_power = diff;
7416 }
7417
7418 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
7419 {
7420         if (INTEL_INFO(dev_priv)->gen != 5)
7421                 return;
7422
7423         spin_lock_irq(&mchdev_lock);
7424
7425         __i915_update_gfx_val(dev_priv);
7426
7427         spin_unlock_irq(&mchdev_lock);
7428 }
7429
7430 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
7431 {
7432         unsigned long t, corr, state1, corr2, state2;
7433         u32 pxvid, ext_v;
7434
7435         lockdep_assert_held(&mchdev_lock);
7436
7437         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
7438         pxvid = (pxvid >> 24) & 0x7f;
7439         ext_v = pvid_to_extvid(dev_priv, pxvid);
7440
7441         state1 = ext_v;
7442
7443         t = i915_mch_val(dev_priv);
7444
7445         /* Revel in the empirically derived constants */
7446
7447         /* Correction factor in 1/100000 units */
7448         if (t > 80)
7449                 corr = ((t * 2349) + 135940);
7450         else if (t >= 50)
7451                 corr = ((t * 964) + 29317);
7452         else /* < 50 */
7453                 corr = ((t * 301) + 1004);
7454
7455         corr = corr * ((150142 * state1) / 10000 - 78642);
7456         corr /= 100000;
7457         corr2 = (corr * dev_priv->ips.corr);
7458
7459         state2 = (corr2 * state1) / 10000;
7460         state2 /= 100; /* convert to mW */
7461
7462         __i915_update_gfx_val(dev_priv);
7463
7464         return dev_priv->ips.gfx_power + state2;
7465 }
7466
7467 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
7468 {
7469         unsigned long val;
7470
7471         if (INTEL_INFO(dev_priv)->gen != 5)
7472                 return 0;
7473
7474         spin_lock_irq(&mchdev_lock);
7475
7476         val = __i915_gfx_val(dev_priv);
7477
7478         spin_unlock_irq(&mchdev_lock);
7479
7480         return val;
7481 }
7482
7483 /**
7484  * i915_read_mch_val - return value for IPS use
7485  *
7486  * Calculate and return a value for the IPS driver to use when deciding whether
7487  * we have thermal and power headroom to increase CPU or GPU power budget.
7488  */
7489 unsigned long i915_read_mch_val(void)
7490 {
7491         struct drm_i915_private *dev_priv;
7492         unsigned long chipset_val, graphics_val, ret = 0;
7493
7494         spin_lock_irq(&mchdev_lock);
7495         if (!i915_mch_dev)
7496                 goto out_unlock;
7497         dev_priv = i915_mch_dev;
7498
7499         chipset_val = __i915_chipset_val(dev_priv);
7500         graphics_val = __i915_gfx_val(dev_priv);
7501
7502         ret = chipset_val + graphics_val;
7503
7504 out_unlock:
7505         spin_unlock_irq(&mchdev_lock);
7506
7507         return ret;
7508 }
7509 EXPORT_SYMBOL_GPL(i915_read_mch_val);
7510
7511 /**
7512  * i915_gpu_raise - raise GPU frequency limit
7513  *
7514  * Raise the limit; IPS indicates we have thermal headroom.
7515  */
7516 bool i915_gpu_raise(void)
7517 {
7518         struct drm_i915_private *dev_priv;
7519         bool ret = true;
7520
7521         spin_lock_irq(&mchdev_lock);
7522         if (!i915_mch_dev) {
7523                 ret = false;
7524                 goto out_unlock;
7525         }
7526         dev_priv = i915_mch_dev;
7527
7528         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
7529                 dev_priv->ips.max_delay--;
7530
7531 out_unlock:
7532         spin_unlock_irq(&mchdev_lock);
7533
7534         return ret;
7535 }
7536 EXPORT_SYMBOL_GPL(i915_gpu_raise);
7537
7538 /**
7539  * i915_gpu_lower - lower GPU frequency limit
7540  *
7541  * IPS indicates we're close to a thermal limit, so throttle back the GPU
7542  * frequency maximum.
7543  */
7544 bool i915_gpu_lower(void)
7545 {
7546         struct drm_i915_private *dev_priv;
7547         bool ret = true;
7548
7549         spin_lock_irq(&mchdev_lock);
7550         if (!i915_mch_dev) {
7551                 ret = false;
7552                 goto out_unlock;
7553         }
7554         dev_priv = i915_mch_dev;
7555
7556         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
7557                 dev_priv->ips.max_delay++;
7558
7559 out_unlock:
7560         spin_unlock_irq(&mchdev_lock);
7561
7562         return ret;
7563 }
7564 EXPORT_SYMBOL_GPL(i915_gpu_lower);
7565
7566 /**
7567  * i915_gpu_busy - indicate GPU business to IPS
7568  *
7569  * Tell the IPS driver whether or not the GPU is busy.
7570  */
7571 bool i915_gpu_busy(void)
7572 {
7573         bool ret = false;
7574
7575         spin_lock_irq(&mchdev_lock);
7576         if (i915_mch_dev)
7577                 ret = i915_mch_dev->gt.awake;
7578         spin_unlock_irq(&mchdev_lock);
7579
7580         return ret;
7581 }
7582 EXPORT_SYMBOL_GPL(i915_gpu_busy);
7583
7584 /**
7585  * i915_gpu_turbo_disable - disable graphics turbo
7586  *
7587  * Disable graphics turbo by resetting the max frequency and setting the
7588  * current frequency to the default.
7589  */
7590 bool i915_gpu_turbo_disable(void)
7591 {
7592         struct drm_i915_private *dev_priv;
7593         bool ret = true;
7594
7595         spin_lock_irq(&mchdev_lock);
7596         if (!i915_mch_dev) {
7597                 ret = false;
7598                 goto out_unlock;
7599         }
7600         dev_priv = i915_mch_dev;
7601
7602         dev_priv->ips.max_delay = dev_priv->ips.fstart;
7603
7604         if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
7605                 ret = false;
7606
7607 out_unlock:
7608         spin_unlock_irq(&mchdev_lock);
7609
7610         return ret;
7611 }
7612 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
7613
7614 /**
7615  * Tells the intel_ips driver that the i915 driver is now loaded, if
7616  * IPS got loaded first.
7617  *
7618  * This awkward dance is so that neither module has to depend on the
7619  * other in order for IPS to do the appropriate communication of
7620  * GPU turbo limits to i915.
7621  */
7622 static void
7623 ips_ping_for_i915_load(void)
7624 {
7625         void (*link)(void);
7626
7627         link = symbol_get(ips_link_to_i915_driver);
7628         if (link) {
7629                 link();
7630                 symbol_put(ips_link_to_i915_driver);
7631         }
7632 }
7633
7634 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
7635 {
7636         /* We only register the i915 ips part with intel-ips once everything is
7637          * set up, to avoid intel-ips sneaking in and reading bogus values. */
7638         spin_lock_irq(&mchdev_lock);
7639         i915_mch_dev = dev_priv;
7640         spin_unlock_irq(&mchdev_lock);
7641
7642         ips_ping_for_i915_load();
7643 }
7644
7645 void intel_gpu_ips_teardown(void)
7646 {
7647         spin_lock_irq(&mchdev_lock);
7648         i915_mch_dev = NULL;
7649         spin_unlock_irq(&mchdev_lock);
7650 }
7651
7652 static void intel_init_emon(struct drm_i915_private *dev_priv)
7653 {
7654         u32 lcfuse;
7655         u8 pxw[16];
7656         int i;
7657
7658         /* Disable to program */
7659         I915_WRITE(ECR, 0);
7660         POSTING_READ(ECR);
7661
7662         /* Program energy weights for various events */
7663         I915_WRITE(SDEW, 0x15040d00);
7664         I915_WRITE(CSIEW0, 0x007f0000);
7665         I915_WRITE(CSIEW1, 0x1e220004);
7666         I915_WRITE(CSIEW2, 0x04000004);
7667
7668         for (i = 0; i < 5; i++)
7669                 I915_WRITE(PEW(i), 0);
7670         for (i = 0; i < 3; i++)
7671                 I915_WRITE(DEW(i), 0);
7672
7673         /* Program P-state weights to account for frequency power adjustment */
7674         for (i = 0; i < 16; i++) {
7675                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
7676                 unsigned long freq = intel_pxfreq(pxvidfreq);
7677                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7678                         PXVFREQ_PX_SHIFT;
7679                 unsigned long val;
7680
7681                 val = vid * vid;
7682                 val *= (freq / 1000);
7683                 val *= 255;
7684                 val /= (127*127*900);
7685                 if (val > 0xff)
7686                         DRM_ERROR("bad pxval: %ld\n", val);
7687                 pxw[i] = val;
7688         }
7689         /* Render standby states get 0 weight */
7690         pxw[14] = 0;
7691         pxw[15] = 0;
7692
7693         for (i = 0; i < 4; i++) {
7694                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7695                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7696                 I915_WRITE(PXW(i), val);
7697         }
7698
7699         /* Adjust magic regs to magic values (more experimental results) */
7700         I915_WRITE(OGW0, 0);
7701         I915_WRITE(OGW1, 0);
7702         I915_WRITE(EG0, 0x00007f00);
7703         I915_WRITE(EG1, 0x0000000e);
7704         I915_WRITE(EG2, 0x000e0000);
7705         I915_WRITE(EG3, 0x68000300);
7706         I915_WRITE(EG4, 0x42000000);
7707         I915_WRITE(EG5, 0x00140031);
7708         I915_WRITE(EG6, 0);
7709         I915_WRITE(EG7, 0);
7710
7711         for (i = 0; i < 8; i++)
7712                 I915_WRITE(PXWL(i), 0);
7713
7714         /* Enable PMON + select events */
7715         I915_WRITE(ECR, 0x80000019);
7716
7717         lcfuse = I915_READ(LCFUSE02);
7718
7719         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
7720 }
7721
7722 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
7723 {
7724         /*
7725          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7726          * requirement.
7727          */
7728         if (!i915.enable_rc6) {
7729                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7730                 intel_runtime_pm_get(dev_priv);
7731         }
7732
7733         mutex_lock(&dev_priv->drm.struct_mutex);
7734         mutex_lock(&dev_priv->rps.hw_lock);
7735
7736         /* Initialize RPS limits (for userspace) */
7737         if (IS_CHERRYVIEW(dev_priv))
7738                 cherryview_init_gt_powersave(dev_priv);
7739         else if (IS_VALLEYVIEW(dev_priv))
7740                 valleyview_init_gt_powersave(dev_priv);
7741         else if (INTEL_GEN(dev_priv) >= 6)
7742                 gen6_init_rps_frequencies(dev_priv);
7743
7744         /* Derive initial user preferences/limits from the hardware limits */
7745         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
7746         dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
7747
7748         dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
7749         dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
7750
7751         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
7752                 dev_priv->rps.min_freq_softlimit =
7753                         max_t(int,
7754                               dev_priv->rps.efficient_freq,
7755                               intel_freq_opcode(dev_priv, 450));
7756
7757         /* After setting max-softlimit, find the overclock max freq */
7758         if (IS_GEN6(dev_priv) ||
7759             IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
7760                 u32 params = 0;
7761
7762                 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
7763                 if (params & BIT(31)) { /* OC supported */
7764                         DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
7765                                          (dev_priv->rps.max_freq & 0xff) * 50,
7766                                          (params & 0xff) * 50);
7767                         dev_priv->rps.max_freq = params & 0xff;
7768                 }
7769         }
7770
7771         /* Finally allow us to boost to max by default */
7772         dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
7773
7774         mutex_unlock(&dev_priv->rps.hw_lock);
7775         mutex_unlock(&dev_priv->drm.struct_mutex);
7776
7777         intel_autoenable_gt_powersave(dev_priv);
7778 }
7779
7780 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
7781 {
7782         if (IS_VALLEYVIEW(dev_priv))
7783                 valleyview_cleanup_gt_powersave(dev_priv);
7784
7785         if (!i915.enable_rc6)
7786                 intel_runtime_pm_put(dev_priv);
7787 }
7788
7789 /**
7790  * intel_suspend_gt_powersave - suspend PM work and helper threads
7791  * @dev_priv: i915 device
7792  *
7793  * We don't want to disable RC6 or other features here, we just want
7794  * to make sure any work we've queued has finished and won't bother
7795  * us while we're suspended.
7796  */
7797 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
7798 {
7799         if (INTEL_GEN(dev_priv) < 6)
7800                 return;
7801
7802         if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
7803                 intel_runtime_pm_put(dev_priv);
7804
7805         /* gen6_rps_idle() will be called later to disable interrupts */
7806 }
7807
7808 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
7809 {
7810         dev_priv->rps.enabled = true; /* force disabling */
7811         intel_disable_gt_powersave(dev_priv);
7812
7813         gen6_reset_rps_interrupts(dev_priv);
7814 }
7815
7816 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
7817 {
7818         if (!READ_ONCE(dev_priv->rps.enabled))
7819                 return;
7820
7821         mutex_lock(&dev_priv->rps.hw_lock);
7822
7823         if (INTEL_GEN(dev_priv) >= 9) {
7824                 gen9_disable_rc6(dev_priv);
7825                 gen9_disable_rps(dev_priv);
7826         } else if (IS_CHERRYVIEW(dev_priv)) {
7827                 cherryview_disable_rps(dev_priv);
7828         } else if (IS_VALLEYVIEW(dev_priv)) {
7829                 valleyview_disable_rps(dev_priv);
7830         } else if (INTEL_GEN(dev_priv) >= 6) {
7831                 gen6_disable_rps(dev_priv);
7832         }  else if (IS_IRONLAKE_M(dev_priv)) {
7833                 ironlake_disable_drps(dev_priv);
7834         }
7835
7836         dev_priv->rps.enabled = false;
7837         mutex_unlock(&dev_priv->rps.hw_lock);
7838 }
7839
7840 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
7841 {
7842         /* We shouldn't be disabling as we submit, so this should be less
7843          * racy than it appears!
7844          */
7845         if (READ_ONCE(dev_priv->rps.enabled))
7846                 return;
7847
7848         /* Powersaving is controlled by the host when inside a VM */
7849         if (intel_vgpu_active(dev_priv))
7850                 return;
7851
7852         mutex_lock(&dev_priv->rps.hw_lock);
7853
7854         if (IS_CHERRYVIEW(dev_priv)) {
7855                 cherryview_enable_rps(dev_priv);
7856         } else if (IS_VALLEYVIEW(dev_priv)) {
7857                 valleyview_enable_rps(dev_priv);
7858         } else if (INTEL_GEN(dev_priv) >= 9) {
7859                 gen9_enable_rc6(dev_priv);
7860                 gen9_enable_rps(dev_priv);
7861                 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
7862                         gen6_update_ring_freq(dev_priv);
7863         } else if (IS_BROADWELL(dev_priv)) {
7864                 gen8_enable_rps(dev_priv);
7865                 gen6_update_ring_freq(dev_priv);
7866         } else if (INTEL_GEN(dev_priv) >= 6) {
7867                 gen6_enable_rps(dev_priv);
7868                 gen6_update_ring_freq(dev_priv);
7869         } else if (IS_IRONLAKE_M(dev_priv)) {
7870                 ironlake_enable_drps(dev_priv);
7871                 intel_init_emon(dev_priv);
7872         }
7873
7874         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
7875         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
7876
7877         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
7878         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
7879
7880         dev_priv->rps.enabled = true;
7881         mutex_unlock(&dev_priv->rps.hw_lock);
7882 }
7883
7884 static void __intel_autoenable_gt_powersave(struct work_struct *work)
7885 {
7886         struct drm_i915_private *dev_priv =
7887                 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
7888         struct intel_engine_cs *rcs;
7889         struct drm_i915_gem_request *req;
7890
7891         if (READ_ONCE(dev_priv->rps.enabled))
7892                 goto out;
7893
7894         rcs = dev_priv->engine[RCS];
7895         if (rcs->last_retired_context)
7896                 goto out;
7897
7898         if (!rcs->init_context)
7899                 goto out;
7900
7901         mutex_lock(&dev_priv->drm.struct_mutex);
7902
7903         req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
7904         if (IS_ERR(req))
7905                 goto unlock;
7906
7907         if (!i915.enable_execlists && i915_switch_context(req) == 0)
7908                 rcs->init_context(req);
7909
7910         /* Mark the device busy, calling intel_enable_gt_powersave() */
7911         i915_add_request(req);
7912
7913 unlock:
7914         mutex_unlock(&dev_priv->drm.struct_mutex);
7915 out:
7916         intel_runtime_pm_put(dev_priv);
7917 }
7918
7919 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
7920 {
7921         if (READ_ONCE(dev_priv->rps.enabled))
7922                 return;
7923
7924         if (IS_IRONLAKE_M(dev_priv)) {
7925                 ironlake_enable_drps(dev_priv);
7926                 intel_init_emon(dev_priv);
7927         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
7928                 /*
7929                  * PCU communication is slow and this doesn't need to be
7930                  * done at any specific time, so do this out of our fast path
7931                  * to make resume and init faster.
7932                  *
7933                  * We depend on the HW RC6 power context save/restore
7934                  * mechanism when entering D3 through runtime PM suspend. So
7935                  * disable RPM until RPS/RC6 is properly setup. We can only
7936                  * get here via the driver load/system resume/runtime resume
7937                  * paths, so the _noresume version is enough (and in case of
7938                  * runtime resume it's necessary).
7939                  */
7940                 if (queue_delayed_work(dev_priv->wq,
7941                                        &dev_priv->rps.autoenable_work,
7942                                        round_jiffies_up_relative(HZ)))
7943                         intel_runtime_pm_get_noresume(dev_priv);
7944         }
7945 }
7946
7947 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
7948 {
7949         /*
7950          * On Ibex Peak and Cougar Point, we need to disable clock
7951          * gating for the panel power sequencer or it will fail to
7952          * start up when no ports are active.
7953          */
7954         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7955 }
7956
7957 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
7958 {
7959         enum pipe pipe;
7960
7961         for_each_pipe(dev_priv, pipe) {
7962                 I915_WRITE(DSPCNTR(pipe),
7963                            I915_READ(DSPCNTR(pipe)) |
7964                            DISPPLANE_TRICKLE_FEED_DISABLE);
7965
7966                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
7967                 POSTING_READ(DSPSURF(pipe));
7968         }
7969 }
7970
7971 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
7972 {
7973         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
7974         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
7975         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
7976
7977         /*
7978          * Don't touch WM1S_LP_EN here.
7979          * Doing so could cause underruns.
7980          */
7981 }
7982
7983 static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
7984 {
7985         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7986
7987         /*
7988          * Required for FBC
7989          * WaFbcDisableDpfcClockGating:ilk
7990          */
7991         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
7992                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
7993                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
7994
7995         I915_WRITE(PCH_3DCGDIS0,
7996                    MARIUNIT_CLOCK_GATE_DISABLE |
7997                    SVSMUNIT_CLOCK_GATE_DISABLE);
7998         I915_WRITE(PCH_3DCGDIS1,
7999                    VFMUNIT_CLOCK_GATE_DISABLE);
8000
8001         /*
8002          * According to the spec the following bits should be set in
8003          * order to enable memory self-refresh
8004          * The bit 22/21 of 0x42004
8005          * The bit 5 of 0x42020
8006          * The bit 15 of 0x45000
8007          */
8008         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8009                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
8010                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8011         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
8012         I915_WRITE(DISP_ARB_CTL,
8013                    (I915_READ(DISP_ARB_CTL) |
8014                     DISP_FBC_WM_DIS));
8015
8016         ilk_init_lp_watermarks(dev_priv);
8017
8018         /*
8019          * Based on the document from hardware guys the following bits
8020          * should be set unconditionally in order to enable FBC.
8021          * The bit 22 of 0x42000
8022          * The bit 22 of 0x42004
8023          * The bit 7,8,9 of 0x42020.
8024          */
8025         if (IS_IRONLAKE_M(dev_priv)) {
8026                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
8027                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8028                            I915_READ(ILK_DISPLAY_CHICKEN1) |
8029                            ILK_FBCQ_DIS);
8030                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8031                            I915_READ(ILK_DISPLAY_CHICKEN2) |
8032                            ILK_DPARB_GATE);
8033         }
8034
8035         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
8036
8037         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8038                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8039                    ILK_ELPIN_409_SELECT);
8040         I915_WRITE(_3D_CHICKEN2,
8041                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8042                    _3D_CHICKEN2_WM_READ_PIPELINED);
8043
8044         /* WaDisableRenderCachePipelinedFlush:ilk */
8045         I915_WRITE(CACHE_MODE_0,
8046                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
8047
8048         /* WaDisable_RenderCache_OperationalFlush:ilk */
8049         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8050
8051         g4x_disable_trickle_feed(dev_priv);
8052
8053         ibx_init_clock_gating(dev_priv);
8054 }
8055
8056 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
8057 {
8058         int pipe;
8059         uint32_t val;
8060
8061         /*
8062          * On Ibex Peak and Cougar Point, we need to disable clock
8063          * gating for the panel power sequencer or it will fail to
8064          * start up when no ports are active.
8065          */
8066         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
8067                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
8068                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
8069         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8070                    DPLS_EDP_PPS_FIX_DIS);
8071         /* The below fixes the weird display corruption, a few pixels shifted
8072          * downward, on (only) LVDS of some HP laptops with IVY.
8073          */
8074         for_each_pipe(dev_priv, pipe) {
8075                 val = I915_READ(TRANS_CHICKEN2(pipe));
8076                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
8077                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
8078                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
8079                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
8080                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
8081                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
8082                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
8083                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
8084         }
8085         /* WADP0ClockGatingDisable */
8086         for_each_pipe(dev_priv, pipe) {
8087                 I915_WRITE(TRANS_CHICKEN1(pipe),
8088                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
8089         }
8090 }
8091
8092 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
8093 {
8094         uint32_t tmp;
8095
8096         tmp = I915_READ(MCH_SSKPD);
8097         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
8098                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
8099                               tmp);
8100 }
8101
8102 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
8103 {
8104         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
8105
8106         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
8107
8108         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8109                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8110                    ILK_ELPIN_409_SELECT);
8111
8112         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
8113         I915_WRITE(_3D_CHICKEN,
8114                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
8115
8116         /* WaDisable_RenderCache_OperationalFlush:snb */
8117         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8118
8119         /*
8120          * BSpec recoomends 8x4 when MSAA is used,
8121          * however in practice 16x4 seems fastest.
8122          *
8123          * Note that PS/WM thread counts depend on the WIZ hashing
8124          * disable bit, which we don't touch here, but it's good
8125          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8126          */
8127         I915_WRITE(GEN6_GT_MODE,
8128                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8129
8130         ilk_init_lp_watermarks(dev_priv);
8131
8132         I915_WRITE(CACHE_MODE_0,
8133                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
8134
8135         I915_WRITE(GEN6_UCGCTL1,
8136                    I915_READ(GEN6_UCGCTL1) |
8137                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
8138                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
8139
8140         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8141          * gating disable must be set.  Failure to set it results in
8142          * flickering pixels due to Z write ordering failures after
8143          * some amount of runtime in the Mesa "fire" demo, and Unigine
8144          * Sanctuary and Tropics, and apparently anything else with
8145          * alpha test or pixel discard.
8146          *
8147          * According to the spec, bit 11 (RCCUNIT) must also be set,
8148          * but we didn't debug actual testcases to find it out.
8149          *
8150          * WaDisableRCCUnitClockGating:snb
8151          * WaDisableRCPBUnitClockGating:snb
8152          */
8153         I915_WRITE(GEN6_UCGCTL2,
8154                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8155                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8156
8157         /* WaStripsFansDisableFastClipPerformanceFix:snb */
8158         I915_WRITE(_3D_CHICKEN3,
8159                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
8160
8161         /*
8162          * Bspec says:
8163          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
8164          * 3DSTATE_SF number of SF output attributes is more than 16."
8165          */
8166         I915_WRITE(_3D_CHICKEN3,
8167                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
8168
8169         /*
8170          * According to the spec the following bits should be
8171          * set in order to enable memory self-refresh and fbc:
8172          * The bit21 and bit22 of 0x42000
8173          * The bit21 and bit22 of 0x42004
8174          * The bit5 and bit7 of 0x42020
8175          * The bit14 of 0x70180
8176          * The bit14 of 0x71180
8177          *
8178          * WaFbcAsynchFlipDisableFbcQueue:snb
8179          */
8180         I915_WRITE(ILK_DISPLAY_CHICKEN1,
8181                    I915_READ(ILK_DISPLAY_CHICKEN1) |
8182                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8183         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8184                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8185                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8186         I915_WRITE(ILK_DSPCLK_GATE_D,
8187                    I915_READ(ILK_DSPCLK_GATE_D) |
8188                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
8189                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
8190
8191         g4x_disable_trickle_feed(dev_priv);
8192
8193         cpt_init_clock_gating(dev_priv);
8194
8195         gen6_check_mch_setup(dev_priv);
8196 }
8197
8198 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
8199 {
8200         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
8201
8202         /*
8203          * WaVSThreadDispatchOverride:ivb,vlv
8204          *
8205          * This actually overrides the dispatch
8206          * mode for all thread types.
8207          */
8208         reg &= ~GEN7_FF_SCHED_MASK;
8209         reg |= GEN7_FF_TS_SCHED_HW;
8210         reg |= GEN7_FF_VS_SCHED_HW;
8211         reg |= GEN7_FF_DS_SCHED_HW;
8212
8213         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
8214 }
8215
8216 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
8217 {
8218         /*
8219          * TODO: this bit should only be enabled when really needed, then
8220          * disabled when not needed anymore in order to save power.
8221          */
8222         if (HAS_PCH_LPT_LP(dev_priv))
8223                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
8224                            I915_READ(SOUTH_DSPCLK_GATE_D) |
8225                            PCH_LP_PARTITION_LEVEL_DISABLE);
8226
8227         /* WADPOClockGatingDisable:hsw */
8228         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
8229                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
8230                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
8231 }
8232
8233 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
8234 {
8235         if (HAS_PCH_LPT_LP(dev_priv)) {
8236                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
8237
8238                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8239                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8240         }
8241 }
8242
8243 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
8244                                    int general_prio_credits,
8245                                    int high_prio_credits)
8246 {
8247         u32 misccpctl;
8248
8249         /* WaTempDisableDOPClkGating:bdw */
8250         misccpctl = I915_READ(GEN7_MISCCPCTL);
8251         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
8252
8253         I915_WRITE(GEN8_L3SQCREG1,
8254                    L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
8255                    L3_HIGH_PRIO_CREDITS(high_prio_credits));
8256
8257         /*
8258          * Wait at least 100 clocks before re-enabling clock gating.
8259          * See the definition of L3SQCREG1 in BSpec.
8260          */
8261         POSTING_READ(GEN8_L3SQCREG1);
8262         udelay(1);
8263         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
8264 }
8265
8266 static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
8267 {
8268         gen9_init_clock_gating(dev_priv);
8269
8270         /* WaDisableSDEUnitClockGating:kbl */
8271         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
8272                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
8273                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8274
8275         /* WaDisableGamClockGating:kbl */
8276         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
8277                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
8278                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
8279
8280         /* WaFbcNukeOnHostModify:kbl,cfl */
8281         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
8282                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
8283 }
8284
8285 static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
8286 {
8287         gen9_init_clock_gating(dev_priv);
8288
8289         /* WAC6entrylatency:skl */
8290         I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
8291                    FBC_LLC_FULLY_OPEN);
8292
8293         /* WaFbcNukeOnHostModify:skl */
8294         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
8295                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
8296 }
8297
8298 static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
8299 {
8300         enum pipe pipe;
8301
8302         ilk_init_lp_watermarks(dev_priv);
8303
8304         /* WaSwitchSolVfFArbitrationPriority:bdw */
8305         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
8306
8307         /* WaPsrDPAMaskVBlankInSRD:bdw */
8308         I915_WRITE(CHICKEN_PAR1_1,
8309                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
8310
8311         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
8312         for_each_pipe(dev_priv, pipe) {
8313                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
8314                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
8315                            BDW_DPRS_MASK_VBLANK_SRD);
8316         }
8317
8318         /* WaVSRefCountFullforceMissDisable:bdw */
8319         /* WaDSRefCountFullforceMissDisable:bdw */
8320         I915_WRITE(GEN7_FF_THREAD_MODE,
8321                    I915_READ(GEN7_FF_THREAD_MODE) &
8322                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
8323
8324         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
8325                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
8326
8327         /* WaDisableSDEUnitClockGating:bdw */
8328         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
8329                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8330
8331         /* WaProgramL3SqcReg1Default:bdw */
8332         gen8_set_l3sqc_credits(dev_priv, 30, 2);
8333
8334         /*
8335          * WaGttCachingOffByDefault:bdw
8336          * GTT cache may not work with big pages, so if those
8337          * are ever enabled GTT cache may need to be disabled.
8338          */
8339         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
8340
8341         /* WaKVMNotificationOnConfigChange:bdw */
8342         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
8343                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
8344
8345         lpt_init_clock_gating(dev_priv);
8346
8347         /* WaDisableDopClockGating:bdw
8348          *
8349          * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
8350          * clock gating.
8351          */
8352         I915_WRITE(GEN6_UCGCTL1,
8353                    I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
8354 }
8355
8356 static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
8357 {
8358         ilk_init_lp_watermarks(dev_priv);
8359
8360         /* L3 caching of data atomics doesn't work -- disable it. */
8361         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
8362         I915_WRITE(HSW_ROW_CHICKEN3,
8363                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
8364
8365         /* This is required by WaCatErrorRejectionIssue:hsw */
8366         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8367                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8368                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8369
8370         /* WaVSRefCountFullforceMissDisable:hsw */
8371         I915_WRITE(GEN7_FF_THREAD_MODE,
8372                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
8373
8374         /* WaDisable_RenderCache_OperationalFlush:hsw */
8375         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8376
8377         /* enable HiZ Raw Stall Optimization */
8378         I915_WRITE(CACHE_MODE_0_GEN7,
8379                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
8380
8381         /* WaDisable4x2SubspanOptimization:hsw */
8382         I915_WRITE(CACHE_MODE_1,
8383                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
8384
8385         /*
8386          * BSpec recommends 8x4 when MSAA is used,
8387          * however in practice 16x4 seems fastest.
8388          *
8389          * Note that PS/WM thread counts depend on the WIZ hashing
8390          * disable bit, which we don't touch here, but it's good
8391          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8392          */
8393         I915_WRITE(GEN7_GT_MODE,
8394                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8395
8396         /* WaSampleCChickenBitEnable:hsw */
8397         I915_WRITE(HALF_SLICE_CHICKEN3,
8398                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
8399
8400         /* WaSwitchSolVfFArbitrationPriority:hsw */
8401         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
8402
8403         /* WaRsPkgCStateDisplayPMReq:hsw */
8404         I915_WRITE(CHICKEN_PAR1_1,
8405                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
8406
8407         lpt_init_clock_gating(dev_priv);
8408 }
8409
8410 static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
8411 {
8412         uint32_t snpcr;
8413
8414         ilk_init_lp_watermarks(dev_priv);
8415
8416         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
8417
8418         /* WaDisableEarlyCull:ivb */
8419         I915_WRITE(_3D_CHICKEN3,
8420                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
8421
8422         /* WaDisableBackToBackFlipFix:ivb */
8423         I915_WRITE(IVB_CHICKEN3,
8424                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8425                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
8426
8427         /* WaDisablePSDDualDispatchEnable:ivb */
8428         if (IS_IVB_GT1(dev_priv))
8429                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
8430                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
8431
8432         /* WaDisable_RenderCache_OperationalFlush:ivb */
8433         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8434
8435         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
8436         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8437                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8438
8439         /* WaApplyL3ControlAndL3ChickenMode:ivb */
8440         I915_WRITE(GEN7_L3CNTLREG1,
8441                         GEN7_WA_FOR_GEN7_L3_CONTROL);
8442         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8443                    GEN7_WA_L3_CHICKEN_MODE);
8444         if (IS_IVB_GT1(dev_priv))
8445                 I915_WRITE(GEN7_ROW_CHICKEN2,
8446                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8447         else {
8448                 /* must write both registers */
8449                 I915_WRITE(GEN7_ROW_CHICKEN2,
8450                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8451                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
8452                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8453         }
8454
8455         /* WaForceL3Serialization:ivb */
8456         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
8457                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
8458
8459         /*
8460          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8461          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
8462          */
8463         I915_WRITE(GEN6_UCGCTL2,
8464                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8465
8466         /* This is required by WaCatErrorRejectionIssue:ivb */
8467         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8468                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8469                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8470
8471         g4x_disable_trickle_feed(dev_priv);
8472
8473         gen7_setup_fixed_func_scheduler(dev_priv);
8474
8475         if (0) { /* causes HiZ corruption on ivb:gt1 */
8476                 /* enable HiZ Raw Stall Optimization */
8477                 I915_WRITE(CACHE_MODE_0_GEN7,
8478                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
8479         }
8480
8481         /* WaDisable4x2SubspanOptimization:ivb */
8482         I915_WRITE(CACHE_MODE_1,
8483                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
8484
8485         /*
8486          * BSpec recommends 8x4 when MSAA is used,
8487          * however in practice 16x4 seems fastest.
8488          *
8489          * Note that PS/WM thread counts depend on the WIZ hashing
8490          * disable bit, which we don't touch here, but it's good
8491          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8492          */
8493         I915_WRITE(GEN7_GT_MODE,
8494                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8495
8496         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
8497         snpcr &= ~GEN6_MBC_SNPCR_MASK;
8498         snpcr |= GEN6_MBC_SNPCR_MED;
8499         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
8500
8501         if (!HAS_PCH_NOP(dev_priv))
8502                 cpt_init_clock_gating(dev_priv);
8503
8504         gen6_check_mch_setup(dev_priv);
8505 }
8506
8507 static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
8508 {
8509         /* WaDisableEarlyCull:vlv */
8510         I915_WRITE(_3D_CHICKEN3,
8511                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
8512
8513         /* WaDisableBackToBackFlipFix:vlv */
8514         I915_WRITE(IVB_CHICKEN3,
8515                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8516                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
8517
8518         /* WaPsdDispatchEnable:vlv */
8519         /* WaDisablePSDDualDispatchEnable:vlv */
8520         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
8521                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
8522                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
8523
8524         /* WaDisable_RenderCache_OperationalFlush:vlv */
8525         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8526
8527         /* WaForceL3Serialization:vlv */
8528         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
8529                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
8530
8531         /* WaDisableDopClockGating:vlv */
8532         I915_WRITE(GEN7_ROW_CHICKEN2,
8533                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8534
8535         /* This is required by WaCatErrorRejectionIssue:vlv */
8536         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8537                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8538                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8539
8540         gen7_setup_fixed_func_scheduler(dev_priv);
8541
8542         /*
8543          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8544          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
8545          */
8546         I915_WRITE(GEN6_UCGCTL2,
8547                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8548
8549         /* WaDisableL3Bank2xClockGate:vlv
8550          * Disabling L3 clock gating- MMIO 940c[25] = 1
8551          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
8552         I915_WRITE(GEN7_UCGCTL4,
8553                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
8554
8555         /*
8556          * BSpec says this must be set, even though
8557          * WaDisable4x2SubspanOptimization isn't listed for VLV.
8558          */
8559         I915_WRITE(CACHE_MODE_1,
8560                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
8561
8562         /*
8563          * BSpec recommends 8x4 when MSAA is used,
8564          * however in practice 16x4 seems fastest.
8565          *
8566          * Note that PS/WM thread counts depend on the WIZ hashing
8567          * disable bit, which we don't touch here, but it's good
8568          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8569          */
8570         I915_WRITE(GEN7_GT_MODE,
8571                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8572
8573         /*
8574          * WaIncreaseL3CreditsForVLVB0:vlv
8575          * This is the hardware default actually.
8576          */
8577         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
8578
8579         /*
8580          * WaDisableVLVClockGating_VBIIssue:vlv
8581          * Disable clock gating on th GCFG unit to prevent a delay
8582          * in the reporting of vblank events.
8583          */
8584         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
8585 }
8586
8587 static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
8588 {
8589         /* WaVSRefCountFullforceMissDisable:chv */
8590         /* WaDSRefCountFullforceMissDisable:chv */
8591         I915_WRITE(GEN7_FF_THREAD_MODE,
8592                    I915_READ(GEN7_FF_THREAD_MODE) &
8593                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
8594
8595         /* WaDisableSemaphoreAndSyncFlipWait:chv */
8596         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
8597                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
8598
8599         /* WaDisableCSUnitClockGating:chv */
8600         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
8601                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
8602
8603         /* WaDisableSDEUnitClockGating:chv */
8604         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
8605                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8606
8607         /*
8608          * WaProgramL3SqcReg1Default:chv
8609          * See gfxspecs/Related Documents/Performance Guide/
8610          * LSQC Setting Recommendations.
8611          */
8612         gen8_set_l3sqc_credits(dev_priv, 38, 2);
8613
8614         /*
8615          * GTT cache may not work with big pages, so if those
8616          * are ever enabled GTT cache may need to be disabled.
8617          */
8618         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
8619 }
8620
8621 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
8622 {
8623         uint32_t dspclk_gate;
8624
8625         I915_WRITE(RENCLK_GATE_D1, 0);
8626         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8627                    GS_UNIT_CLOCK_GATE_DISABLE |
8628                    CL_UNIT_CLOCK_GATE_DISABLE);
8629         I915_WRITE(RAMCLK_GATE_D, 0);
8630         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8631                 OVRUNIT_CLOCK_GATE_DISABLE |
8632                 OVCUNIT_CLOCK_GATE_DISABLE;
8633         if (IS_GM45(dev_priv))
8634                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8635         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8636
8637         /* WaDisableRenderCachePipelinedFlush */
8638         I915_WRITE(CACHE_MODE_0,
8639                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
8640
8641         /* WaDisable_RenderCache_OperationalFlush:g4x */
8642         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8643
8644         g4x_disable_trickle_feed(dev_priv);
8645 }
8646
8647 static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
8648 {
8649         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8650         I915_WRITE(RENCLK_GATE_D2, 0);
8651         I915_WRITE(DSPCLK_GATE_D, 0);
8652         I915_WRITE(RAMCLK_GATE_D, 0);
8653         I915_WRITE16(DEUC, 0);
8654         I915_WRITE(MI_ARB_STATE,
8655                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
8656
8657         /* WaDisable_RenderCache_OperationalFlush:gen4 */
8658         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8659 }
8660
8661 static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
8662 {
8663         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8664                    I965_RCC_CLOCK_GATE_DISABLE |
8665                    I965_RCPB_CLOCK_GATE_DISABLE |
8666                    I965_ISC_CLOCK_GATE_DISABLE |
8667                    I965_FBC_CLOCK_GATE_DISABLE);
8668         I915_WRITE(RENCLK_GATE_D2, 0);
8669         I915_WRITE(MI_ARB_STATE,
8670                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
8671
8672         /* WaDisable_RenderCache_OperationalFlush:gen4 */
8673         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8674 }
8675
8676 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
8677 {
8678         u32 dstate = I915_READ(D_STATE);
8679
8680         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8681                 DSTATE_DOT_CLOCK_GATING;
8682         I915_WRITE(D_STATE, dstate);
8683
8684         if (IS_PINEVIEW(dev_priv))
8685                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
8686
8687         /* IIR "flip pending" means done if this bit is set */
8688         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
8689
8690         /* interrupts should cause a wake up from C3 */
8691         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
8692
8693         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
8694         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
8695
8696         I915_WRITE(MI_ARB_STATE,
8697                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
8698 }
8699
8700 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
8701 {
8702         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8703
8704         /* interrupts should cause a wake up from C3 */
8705         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
8706                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
8707
8708         I915_WRITE(MEM_MODE,
8709                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
8710 }
8711
8712 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
8713 {
8714         I915_WRITE(MEM_MODE,
8715                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
8716                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
8717 }
8718
8719 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
8720 {
8721         dev_priv->display.init_clock_gating(dev_priv);
8722 }
8723
8724 void intel_suspend_hw(struct drm_i915_private *dev_priv)
8725 {
8726         if (HAS_PCH_LPT(dev_priv))
8727                 lpt_suspend_hw(dev_priv);
8728 }
8729
8730 static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
8731 {
8732         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
8733 }
8734
8735 /**
8736  * intel_init_clock_gating_hooks - setup the clock gating hooks
8737  * @dev_priv: device private
8738  *
8739  * Setup the hooks that configure which clocks of a given platform can be
8740  * gated and also apply various GT and display specific workarounds for these
8741  * platforms. Note that some GT specific workarounds are applied separately
8742  * when GPU contexts or batchbuffers start their execution.
8743  */
8744 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
8745 {
8746         if (IS_SKYLAKE(dev_priv))
8747                 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
8748         else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
8749                 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
8750         else if (IS_BROXTON(dev_priv))
8751                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
8752         else if (IS_GEMINILAKE(dev_priv))
8753                 dev_priv->display.init_clock_gating = glk_init_clock_gating;
8754         else if (IS_BROADWELL(dev_priv))
8755                 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
8756         else if (IS_CHERRYVIEW(dev_priv))
8757                 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
8758         else if (IS_HASWELL(dev_priv))
8759                 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
8760         else if (IS_IVYBRIDGE(dev_priv))
8761                 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8762         else if (IS_VALLEYVIEW(dev_priv))
8763                 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
8764         else if (IS_GEN6(dev_priv))
8765                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8766         else if (IS_GEN5(dev_priv))
8767                 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8768         else if (IS_G4X(dev_priv))
8769                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8770         else if (IS_I965GM(dev_priv))
8771                 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8772         else if (IS_I965G(dev_priv))
8773                 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8774         else if (IS_GEN3(dev_priv))
8775                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8776         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
8777                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8778         else if (IS_GEN2(dev_priv))
8779                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8780         else {
8781                 MISSING_CASE(INTEL_DEVID(dev_priv));
8782                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
8783         }
8784 }
8785
8786 /* Set up chip specific power management-related functions */
8787 void intel_init_pm(struct drm_i915_private *dev_priv)
8788 {
8789         intel_fbc_init(dev_priv);
8790
8791         /* For cxsr */
8792         if (IS_PINEVIEW(dev_priv))
8793                 i915_pineview_get_mem_freq(dev_priv);
8794         else if (IS_GEN5(dev_priv))
8795                 i915_ironlake_get_mem_freq(dev_priv);
8796
8797         /* For FIFO watermark updates */
8798         if (INTEL_GEN(dev_priv) >= 9) {
8799                 skl_setup_wm_latency(dev_priv);
8800                 dev_priv->display.initial_watermarks = skl_initial_wm;
8801                 dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
8802                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
8803         } else if (HAS_PCH_SPLIT(dev_priv)) {
8804                 ilk_setup_wm_latency(dev_priv);
8805
8806                 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
8807                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
8808                     (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
8809                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
8810                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
8811                         dev_priv->display.compute_intermediate_wm =
8812                                 ilk_compute_intermediate_wm;
8813                         dev_priv->display.initial_watermarks =
8814                                 ilk_initial_watermarks;
8815                         dev_priv->display.optimize_watermarks =
8816                                 ilk_optimize_watermarks;
8817                 } else {
8818                         DRM_DEBUG_KMS("Failed to read display plane latency. "
8819                                       "Disable CxSR\n");
8820                 }
8821         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
8822                 vlv_setup_wm_latency(dev_priv);
8823                 dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;
8824                 dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;
8825                 dev_priv->display.initial_watermarks = vlv_initial_watermarks;
8826                 dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;
8827                 dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo;
8828         } else if (IS_G4X(dev_priv)) {
8829                 g4x_setup_wm_latency(dev_priv);
8830                 dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm;
8831                 dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm;
8832                 dev_priv->display.initial_watermarks = g4x_initial_watermarks;
8833                 dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;
8834         } else if (IS_PINEVIEW(dev_priv)) {
8835                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
8836                                             dev_priv->is_ddr3,
8837                                             dev_priv->fsb_freq,
8838                                             dev_priv->mem_freq)) {
8839                         DRM_INFO("failed to find known CxSR latency "
8840                                  "(found ddr%s fsb freq %d, mem freq %d), "
8841                                  "disabling CxSR\n",
8842                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
8843                                  dev_priv->fsb_freq, dev_priv->mem_freq);
8844                         /* Disable CxSR and never update its watermark again */
8845                         intel_set_memory_cxsr(dev_priv, false);
8846                         dev_priv->display.update_wm = NULL;
8847                 } else
8848                         dev_priv->display.update_wm = pineview_update_wm;
8849         } else if (IS_GEN4(dev_priv)) {
8850                 dev_priv->display.update_wm = i965_update_wm;
8851         } else if (IS_GEN3(dev_priv)) {
8852                 dev_priv->display.update_wm = i9xx_update_wm;
8853                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8854         } else if (IS_GEN2(dev_priv)) {
8855                 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
8856                         dev_priv->display.update_wm = i845_update_wm;
8857                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
8858                 } else {
8859                         dev_priv->display.update_wm = i9xx_update_wm;
8860                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
8861                 }
8862         } else {
8863                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
8864         }
8865 }
8866
8867 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
8868 {
8869         uint32_t flags =
8870                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
8871
8872         switch (flags) {
8873         case GEN6_PCODE_SUCCESS:
8874                 return 0;
8875         case GEN6_PCODE_UNIMPLEMENTED_CMD:
8876                 return -ENODEV;
8877         case GEN6_PCODE_ILLEGAL_CMD:
8878                 return -ENXIO;
8879         case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
8880         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
8881                 return -EOVERFLOW;
8882         case GEN6_PCODE_TIMEOUT:
8883                 return -ETIMEDOUT;
8884         default:
8885                 MISSING_CASE(flags);
8886                 return 0;
8887         }
8888 }
8889
8890 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
8891 {
8892         uint32_t flags =
8893                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
8894
8895         switch (flags) {
8896         case GEN6_PCODE_SUCCESS:
8897                 return 0;
8898         case GEN6_PCODE_ILLEGAL_CMD:
8899                 return -ENXIO;
8900         case GEN7_PCODE_TIMEOUT:
8901                 return -ETIMEDOUT;
8902         case GEN7_PCODE_ILLEGAL_DATA:
8903                 return -EINVAL;
8904         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
8905                 return -EOVERFLOW;
8906         default:
8907                 MISSING_CASE(flags);
8908                 return 0;
8909         }
8910 }
8911
8912 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
8913 {
8914         int status;
8915
8916         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
8917
8918         /* GEN6_PCODE_* are outside of the forcewake domain, we can
8919          * use te fw I915_READ variants to reduce the amount of work
8920          * required when reading/writing.
8921          */
8922
8923         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
8924                 DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps\n",
8925                                  mbox, __builtin_return_address(0));
8926                 return -EAGAIN;
8927         }
8928
8929         I915_WRITE_FW(GEN6_PCODE_DATA, *val);
8930         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
8931         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
8932
8933         if (__intel_wait_for_register_fw(dev_priv,
8934                                          GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
8935                                          500, 0, NULL)) {
8936                 DRM_ERROR("timeout waiting for pcode read (from mbox %x) to finish for %ps\n",
8937                           mbox, __builtin_return_address(0));
8938                 return -ETIMEDOUT;
8939         }
8940
8941         *val = I915_READ_FW(GEN6_PCODE_DATA);
8942         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
8943
8944         if (INTEL_GEN(dev_priv) > 6)
8945                 status = gen7_check_mailbox_status(dev_priv);
8946         else
8947                 status = gen6_check_mailbox_status(dev_priv);
8948
8949         if (status) {
8950                 DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
8951                                  mbox, __builtin_return_address(0), status);
8952                 return status;
8953         }
8954
8955         return 0;
8956 }
8957
8958 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
8959                             u32 mbox, u32 val)
8960 {
8961         int status;
8962
8963         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
8964
8965         /* GEN6_PCODE_* are outside of the forcewake domain, we can
8966          * use te fw I915_READ variants to reduce the amount of work
8967          * required when reading/writing.
8968          */
8969
8970         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
8971                 DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps\n",
8972                                  val, mbox, __builtin_return_address(0));
8973                 return -EAGAIN;
8974         }
8975
8976         I915_WRITE_FW(GEN6_PCODE_DATA, val);
8977         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
8978         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
8979
8980         if (__intel_wait_for_register_fw(dev_priv,
8981                                          GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
8982                                          500, 0, NULL)) {
8983                 DRM_ERROR("timeout waiting for pcode write of 0x%08x to mbox %x to finish for %ps\n",
8984                           val, mbox, __builtin_return_address(0));
8985                 return -ETIMEDOUT;
8986         }
8987
8988         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
8989
8990         if (INTEL_GEN(dev_priv) > 6)
8991                 status = gen7_check_mailbox_status(dev_priv);
8992         else
8993                 status = gen6_check_mailbox_status(dev_priv);
8994
8995         if (status) {
8996                 DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
8997                                  val, mbox, __builtin_return_address(0), status);
8998                 return status;
8999         }
9000
9001         return 0;
9002 }
9003
9004 static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
9005                                   u32 request, u32 reply_mask, u32 reply,
9006                                   u32 *status)
9007 {
9008         u32 val = request;
9009
9010         *status = sandybridge_pcode_read(dev_priv, mbox, &val);
9011
9012         return *status || ((val & reply_mask) == reply);
9013 }
9014
9015 /**
9016  * skl_pcode_request - send PCODE request until acknowledgment
9017  * @dev_priv: device private
9018  * @mbox: PCODE mailbox ID the request is targeted for
9019  * @request: request ID
9020  * @reply_mask: mask used to check for request acknowledgment
9021  * @reply: value used to check for request acknowledgment
9022  * @timeout_base_ms: timeout for polling with preemption enabled
9023  *
9024  * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
9025  * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
9026  * The request is acknowledged once the PCODE reply dword equals @reply after
9027  * applying @reply_mask. Polling is first attempted with preemption enabled
9028  * for @timeout_base_ms and if this times out for another 50 ms with
9029  * preemption disabled.
9030  *
9031  * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
9032  * other error as reported by PCODE.
9033  */
9034 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
9035                       u32 reply_mask, u32 reply, int timeout_base_ms)
9036 {
9037         u32 status;
9038         int ret;
9039
9040         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
9041
9042 #define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
9043                                    &status)
9044
9045         /*
9046          * Prime the PCODE by doing a request first. Normally it guarantees
9047          * that a subsequent request, at most @timeout_base_ms later, succeeds.
9048          * _wait_for() doesn't guarantee when its passed condition is evaluated
9049          * first, so send the first request explicitly.
9050          */
9051         if (COND) {
9052                 ret = 0;
9053                 goto out;
9054         }
9055         ret = _wait_for(COND, timeout_base_ms * 1000, 10);
9056         if (!ret)
9057                 goto out;
9058
9059         /*
9060          * The above can time out if the number of requests was low (2 in the
9061          * worst case) _and_ PCODE was busy for some reason even after a
9062          * (queued) request and @timeout_base_ms delay. As a workaround retry
9063          * the poll with preemption disabled to maximize the number of
9064          * requests. Increase the timeout from @timeout_base_ms to 50ms to
9065          * account for interrupts that could reduce the number of these
9066          * requests, and for any quirks of the PCODE firmware that delays
9067          * the request completion.
9068          */
9069         DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
9070         WARN_ON_ONCE(timeout_base_ms > 3);
9071         preempt_disable();
9072         ret = wait_for_atomic(COND, 50);
9073         preempt_enable();
9074
9075 out:
9076         return ret ? ret : status;
9077 #undef COND
9078 }
9079
9080 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
9081 {
9082         /*
9083          * N = val - 0xb7
9084          * Slow = Fast = GPLL ref * N
9085          */
9086         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
9087 }
9088
9089 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
9090 {
9091         return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
9092 }
9093
9094 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
9095 {
9096         /*
9097          * N = val / 2
9098          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
9099          */
9100         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
9101 }
9102
9103 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
9104 {
9105         /* CHV needs even values */
9106         return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
9107 }
9108
9109 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
9110 {
9111         if (INTEL_GEN(dev_priv) >= 9)
9112                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
9113                                          GEN9_FREQ_SCALER);
9114         else if (IS_CHERRYVIEW(dev_priv))
9115                 return chv_gpu_freq(dev_priv, val);
9116         else if (IS_VALLEYVIEW(dev_priv))
9117                 return byt_gpu_freq(dev_priv, val);
9118         else
9119                 return val * GT_FREQUENCY_MULTIPLIER;
9120 }
9121
9122 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
9123 {
9124         if (INTEL_GEN(dev_priv) >= 9)
9125                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
9126                                          GT_FREQUENCY_MULTIPLIER);
9127         else if (IS_CHERRYVIEW(dev_priv))
9128                 return chv_freq_opcode(dev_priv, val);
9129         else if (IS_VALLEYVIEW(dev_priv))
9130                 return byt_freq_opcode(dev_priv, val);
9131         else
9132                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
9133 }
9134
9135 struct request_boost {
9136         struct work_struct work;
9137         struct drm_i915_gem_request *req;
9138 };
9139
9140 static void __intel_rps_boost_work(struct work_struct *work)
9141 {
9142         struct request_boost *boost = container_of(work, struct request_boost, work);
9143         struct drm_i915_gem_request *req = boost->req;
9144
9145         if (!i915_gem_request_completed(req))
9146                 gen6_rps_boost(req, NULL);
9147
9148         i915_gem_request_put(req);
9149         kfree(boost);
9150 }
9151
9152 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
9153 {
9154         struct request_boost *boost;
9155
9156         if (req == NULL || INTEL_GEN(req->i915) < 6)
9157                 return;
9158
9159         if (i915_gem_request_completed(req))
9160                 return;
9161
9162         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
9163         if (boost == NULL)
9164                 return;
9165
9166         boost->req = i915_gem_request_get(req);
9167
9168         INIT_WORK(&boost->work, __intel_rps_boost_work);
9169         queue_work(req->i915->wq, &boost->work);
9170 }
9171
9172 void intel_pm_setup(struct drm_i915_private *dev_priv)
9173 {
9174         mutex_init(&dev_priv->rps.hw_lock);
9175
9176         INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
9177                           __intel_autoenable_gt_powersave);
9178         atomic_set(&dev_priv->rps.num_waiters, 0);
9179
9180         dev_priv->pm.suspended = false;
9181         atomic_set(&dev_priv->pm.wakeref_count, 0);
9182 }
9183
9184 static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
9185                              const i915_reg_t reg)
9186 {
9187         u32 lower, upper, tmp;
9188         int loop = 2;
9189
9190         /* The register accessed do not need forcewake. We borrow
9191          * uncore lock to prevent concurrent access to range reg.
9192          */
9193         spin_lock_irq(&dev_priv->uncore.lock);
9194
9195         /* vlv and chv residency counters are 40 bits in width.
9196          * With a control bit, we can choose between upper or lower
9197          * 32bit window into this counter.
9198          *
9199          * Although we always use the counter in high-range mode elsewhere,
9200          * userspace may attempt to read the value before rc6 is initialised,
9201          * before we have set the default VLV_COUNTER_CONTROL value. So always
9202          * set the high bit to be safe.
9203          */
9204         I915_WRITE_FW(VLV_COUNTER_CONTROL,
9205                       _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
9206         upper = I915_READ_FW(reg);
9207         do {
9208                 tmp = upper;
9209
9210                 I915_WRITE_FW(VLV_COUNTER_CONTROL,
9211                               _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
9212                 lower = I915_READ_FW(reg);
9213
9214                 I915_WRITE_FW(VLV_COUNTER_CONTROL,
9215                               _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
9216                 upper = I915_READ_FW(reg);
9217         } while (upper != tmp && --loop);
9218
9219         /* Everywhere else we always use VLV_COUNTER_CONTROL with the
9220          * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
9221          * now.
9222          */
9223
9224         spin_unlock_irq(&dev_priv->uncore.lock);
9225
9226         return lower | (u64)upper << 8;
9227 }
9228
9229 u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
9230                            const i915_reg_t reg)
9231 {
9232         u64 time_hw, units, div;
9233
9234         if (!intel_enable_rc6())
9235                 return 0;
9236
9237         intel_runtime_pm_get(dev_priv);
9238
9239         /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
9240         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
9241                 units = 1000;
9242                 div = dev_priv->czclk_freq;
9243
9244                 time_hw = vlv_residency_raw(dev_priv, reg);
9245         } else if (IS_GEN9_LP(dev_priv)) {
9246                 units = 1000;
9247                 div = 1200;             /* 833.33ns */
9248
9249                 time_hw = I915_READ(reg);
9250         } else {
9251                 units = 128000; /* 1.28us */
9252                 div = 100000;
9253
9254                 time_hw = I915_READ(reg);
9255         }
9256
9257         intel_runtime_pm_put(dev_priv);
9258         return DIV_ROUND_UP_ULL(time_hw * units, div);
9259 }