drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include "i915_drv.h"
  31 #include "intel_drv.h"
  32 #include "../../../platform/x86/intel_ips.h"
  33 #include <linux/module.h>
  34 #include <drm/drm_atomic_helper.h>
  35
  36 /**
  37  * DOC: RC6
  38  *
  39  * RC6 is a special power stage which allows the GPU to enter an very
  40  * low-voltage mode when idle, using down to 0V while at this stage.  This
  41  * stage is entered automatically when the GPU is idle when RC6 support is
  42  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  43  *
  44  * There are different RC6 modes available in Intel GPU, which differentiate
  45  * among each other with the latency required to enter and leave RC6 and
  46  * voltage consumed by the GPU in different states.
  47  *
  48  * The combination of the following flags define which states GPU is allowed
  49  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  50  * RC6pp is deepest RC6. Their support by hardware varies according to the
  51  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  52  * which brings the most power savings; deeper states save more power, but
  53  * require higher latency to switch to and wake up.
  54  */
  55 #define INTEL_RC6_ENABLE                        (1<<0)
  56 #define INTEL_RC6p_ENABLE                       (1<<1)
  57 #define INTEL_RC6pp_ENABLE                      (1<<2)
  58
  59 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
  60 {
  61         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
  62         I915_WRITE(CHICKEN_PAR1_1,
  63                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  64
  65         /*
  66          * Display WA#0390: skl,bxt,kbl,glk
  67          *
  68          * Must match Sampler, Pixel Back End, and Media
  69          * (0xE194 bit 8, 0x7014 bit 13, 0x4DDC bits 27 and 31).
  70          *
  71          * Including bits outside the page in the hash would
  72          * require 2 (or 4?) MiB alignment of resources. Just
  73          * assume the defaul hashing mode which only uses bits
  74          * within the page.
  75          */
  76         I915_WRITE(CHICKEN_PAR1_1,
  77                    I915_READ(CHICKEN_PAR1_1) & ~SKL_RC_HASH_OUTSIDE);
  78
  79         I915_WRITE(GEN8_CONFIG0,
  80                    I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
  81
  82         /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
  83         I915_WRITE(GEN8_CHICKEN_DCPR_1,
  84                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  85
  86         /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
  87         /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
  88         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
  89                    DISP_FBC_WM_DIS |
  90                    DISP_FBC_MEMORY_WAKE);
  91
  92         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
  93         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
  94                    ILK_DPFC_DISABLE_DUMMY0);
  95
  96         if (IS_SKYLAKE(dev_priv)) {
  97                 /* WaDisableDopClockGating */
  98                 I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
  99                            & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 100         }
 101 }
 102
 103 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
 104 {
 105         gen9_init_clock_gating(dev_priv);
 106
 107         /* WaDisableSDEUnitClockGating:bxt */
 108         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 109                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 110
 111         /*
 112          * FIXME:
 113          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
 114          */
 115         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 116                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 117
 118         /*
 119          * Wa: Backlight PWM may stop in the asserted state, causing backlight
 120          * to stay fully on.
 121          */
 122         I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 123                    PWM1_GATING_DIS | PWM2_GATING_DIS);
 124 }
 125
 126 static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
 127 {
 128         gen9_init_clock_gating(dev_priv);
 129
 130         /*
 131          * WaDisablePWMClockGating:glk
 132          * Backlight PWM may stop in the asserted state, causing backlight
 133          * to stay fully on.
 134          */
 135         I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 136                    PWM1_GATING_DIS | PWM2_GATING_DIS);
 137
 138         /* WaDDIIOTimeout:glk */
 139         if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) {
 140                 u32 val = I915_READ(CHICKEN_MISC_2);
 141                 val &= ~(GLK_CL0_PWR_DOWN |
 142                          GLK_CL1_PWR_DOWN |
 143                          GLK_CL2_PWR_DOWN);
 144                 I915_WRITE(CHICKEN_MISC_2, val);
 145         }
 146
 147 }
 148
 149 static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
 150 {
 151         u32 tmp;
 152
 153         tmp = I915_READ(CLKCFG);
 154
 155         switch (tmp & CLKCFG_FSB_MASK) {
 156         case CLKCFG_FSB_533:
 157                 dev_priv->fsb_freq = 533; /* 133*4 */
 158                 break;
 159         case CLKCFG_FSB_800:
 160                 dev_priv->fsb_freq = 800; /* 200*4 */
 161                 break;
 162         case CLKCFG_FSB_667:
 163                 dev_priv->fsb_freq =  667; /* 167*4 */
 164                 break;
 165         case CLKCFG_FSB_400:
 166                 dev_priv->fsb_freq = 400; /* 100*4 */
 167                 break;
 168         }
 169
 170         switch (tmp & CLKCFG_MEM_MASK) {
 171         case CLKCFG_MEM_533:
 172                 dev_priv->mem_freq = 533;
 173                 break;
 174         case CLKCFG_MEM_667:
 175                 dev_priv->mem_freq = 667;
 176                 break;
 177         case CLKCFG_MEM_800:
 178                 dev_priv->mem_freq = 800;
 179                 break;
 180         }
 181
 182         /* detect pineview DDR3 setting */
 183         tmp = I915_READ(CSHRDDR3CTL);
 184         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 185 }
 186
 187 static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
 188 {
 189         u16 ddrpll, csipll;
 190
 191         ddrpll = I915_READ16(DDRMPLL1);
 192         csipll = I915_READ16(CSIPLL0);
 193
 194         switch (ddrpll & 0xff) {
 195         case 0xc:
 196                 dev_priv->mem_freq = 800;
 197                 break;
 198         case 0x10:
 199                 dev_priv->mem_freq = 1066;
 200                 break;
 201         case 0x14:
 202                 dev_priv->mem_freq = 1333;
 203                 break;
 204         case 0x18:
 205                 dev_priv->mem_freq = 1600;
 206                 break;
 207         default:
 208                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 209                                  ddrpll & 0xff);
 210                 dev_priv->mem_freq = 0;
 211                 break;
 212         }
 213
 214         dev_priv->ips.r_t = dev_priv->mem_freq;
 215
 216         switch (csipll & 0x3ff) {
 217         case 0x00c:
 218                 dev_priv->fsb_freq = 3200;
 219                 break;
 220         case 0x00e:
 221                 dev_priv->fsb_freq = 3733;
 222                 break;
 223         case 0x010:
 224                 dev_priv->fsb_freq = 4266;
 225                 break;
 226         case 0x012:
 227                 dev_priv->fsb_freq = 4800;
 228                 break;
 229         case 0x014:
 230                 dev_priv->fsb_freq = 5333;
 231                 break;
 232         case 0x016:
 233                 dev_priv->fsb_freq = 5866;
 234                 break;
 235         case 0x018:
 236                 dev_priv->fsb_freq = 6400;
 237                 break;
 238         default:
 239                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 240                                  csipll & 0x3ff);
 241                 dev_priv->fsb_freq = 0;
 242                 break;
 243         }
 244
 245         if (dev_priv->fsb_freq == 3200) {
 246                 dev_priv->ips.c_m = 0;
 247         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 248                 dev_priv->ips.c_m = 1;
 249         } else {
 250                 dev_priv->ips.c_m = 2;
 251         }
 252 }
 253
 254 static const struct cxsr_latency cxsr_latency_table[] = {
 255         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 256         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 257         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 258         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 259         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 260
 261         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 262         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 263         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 264         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 265         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 266
 267         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 268         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 269         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 270         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 271         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 272
 273         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 274         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 275         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 276         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 277         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 278
 279         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 280         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 281         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 282         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 283         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 284
 285         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 286         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 287         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 288         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 289         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 290 };
 291
 292 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
 293                                                          bool is_ddr3,
 294                                                          int fsb,
 295                                                          int mem)
 296 {
 297         const struct cxsr_latency *latency;
 298         int i;
 299
 300         if (fsb == 0 || mem == 0)
 301                 return NULL;
 302
 303         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 304                 latency = &cxsr_latency_table[i];
 305                 if (is_desktop == latency->is_desktop &&
 306                     is_ddr3 == latency->is_ddr3 &&
 307                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 308                         return latency;
 309         }
 310
 311         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 312
 313         return NULL;
 314 }
 315
 316 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 317 {
 318         u32 val;
 319
 320         mutex_lock(&dev_priv->rps.hw_lock);
 321
 322         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 323         if (enable)
 324                 val &= ~FORCE_DDR_HIGH_FREQ;
 325         else
 326                 val |= FORCE_DDR_HIGH_FREQ;
 327         val &= ~FORCE_DDR_LOW_FREQ;
 328         val |= FORCE_DDR_FREQ_REQ_ACK;
 329         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 330
 331         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 332                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 333                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 334
 335         mutex_unlock(&dev_priv->rps.hw_lock);
 336 }
 337
 338 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 339 {
 340         u32 val;
 341
 342         mutex_lock(&dev_priv->rps.hw_lock);
 343
 344         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 345         if (enable)
 346                 val |= DSP_MAXFIFO_PM5_ENABLE;
 347         else
 348                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 349         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 350
 351         mutex_unlock(&dev_priv->rps.hw_lock);
 352 }
 353
 354 #define FW_WM(value, plane) \
 355         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 356
 357 static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 358 {
 359         bool was_enabled;
 360         u32 val;
 361
 362         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 363                 was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 364                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 365                 POSTING_READ(FW_BLC_SELF_VLV);
 366         } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
 367                 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
 368                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 369                 POSTING_READ(FW_BLC_SELF);
 370         } else if (IS_PINEVIEW(dev_priv)) {
 371                 val = I915_READ(DSPFW3);
 372                 was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
 373                 if (enable)
 374                         val |= PINEVIEW_SELF_REFRESH_EN;
 375                 else
 376                         val &= ~PINEVIEW_SELF_REFRESH_EN;
 377                 I915_WRITE(DSPFW3, val);
 378                 POSTING_READ(DSPFW3);
 379         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
 380                 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
 381                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 382                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 383                 I915_WRITE(FW_BLC_SELF, val);
 384                 POSTING_READ(FW_BLC_SELF);
 385         } else if (IS_I915GM(dev_priv)) {
 386                 /*
 387                  * FIXME can't find a bit like this for 915G, and
 388                  * and yet it does have the related watermark in
 389                  * FW_BLC_SELF. What's going on?
 390                  */
 391                 was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
 392                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 393                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 394                 I915_WRITE(INSTPM, val);
 395                 POSTING_READ(INSTPM);
 396         } else {
 397                 return false;
 398         }
 399
 400         trace_intel_memory_cxsr(dev_priv, was_enabled, enable);
 401
 402         DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n",
 403                       enableddisabled(enable),
 404                       enableddisabled(was_enabled));
 405
 406         return was_enabled;
 407 }
 408
 409 /**
 410  * intel_set_memory_cxsr - Configure CxSR state
 411  * @dev_priv: i915 device
 412  * @enable: Allow vs. disallow CxSR
 413  *
 414  * Allow or disallow the system to enter a special CxSR
 415  * (C-state self refresh) state. What typically happens in CxSR mode
 416  * is that several display FIFOs may get combined into a single larger
 417  * FIFO for a particular plane (so called max FIFO mode) to allow the
 418  * system to defer memory fetches longer, and the memory will enter
 419  * self refresh.
 420  *
 421  * Note that enabling CxSR does not guarantee that the system enter
 422  * this special mode, nor does it guarantee that the system stays
 423  * in that mode once entered. So this just allows/disallows the system
 424  * to autonomously utilize the CxSR mode. Other factors such as core
 425  * C-states will affect when/if the system actually enters/exits the
 426  * CxSR mode.
 427  *
 428  * Note that on VLV/CHV this actually only controls the max FIFO mode,
 429  * and the system is free to enter/exit memory self refresh at any time
 430  * even when the use of CxSR has been disallowed.
 431  *
 432  * While the system is actually in the CxSR/max FIFO mode, some plane
 433  * control registers will not get latched on vblank. Thus in order to
 434  * guarantee the system will respond to changes in the plane registers
 435  * we must always disallow CxSR prior to making changes to those registers.
 436  * Unfortunately the system will re-evaluate the CxSR conditions at
 437  * frame start which happens after vblank start (which is when the plane
 438  * registers would get latched), so we can't proceed with the plane update
 439  * during the same frame where we disallowed CxSR.
 440  *
 441  * Certain platforms also have a deeper HPLL SR mode. Fortunately the
 442  * HPLL SR mode depends on CxSR itself, so we don't have to hand hold
 443  * the hardware w.r.t. HPLL SR when writing to plane registers.
 444  * Disallowing just CxSR is sufficient.
 445  */
 446 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 447 {
 448         bool ret;
 449
 450         mutex_lock(&dev_priv->wm.wm_mutex);
 451         ret = _intel_set_memory_cxsr(dev_priv, enable);
 452         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 453                 dev_priv->wm.vlv.cxsr = enable;
 454         else if (IS_G4X(dev_priv))
 455                 dev_priv->wm.g4x.cxsr = enable;
 456         mutex_unlock(&dev_priv->wm.wm_mutex);
 457
 458         return ret;
 459 }
 460
 461 /*
 462  * Latency for FIFO fetches is dependent on several factors:
 463  *   - memory configuration (speed, channels)
 464  *   - chipset
 465  *   - current MCH state
 466  * It can be fairly high in some situations, so here we assume a fairly
 467  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 468  * set this value too high, the FIFO will fetch frequently to stay full)
 469  * and power consumption (set it too low to save power and we might see
 470  * FIFO underruns and display "flicker").
 471  *
 472  * A value of 5us seems to be a good balance; safe for very low end
 473  * platforms but not overly aggressive on lower latency configs.
 474  */
 475 static const int pessimal_latency_ns = 5000;
 476
 477 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 478         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 479
 480 static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
 481 {
 482         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 483         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 484         struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
 485         enum pipe pipe = crtc->pipe;
 486         int sprite0_start, sprite1_start;
 487
 488         switch (pipe) {
 489                 uint32_t dsparb, dsparb2, dsparb3;
 490         case PIPE_A:
 491                 dsparb = I915_READ(DSPARB);
 492                 dsparb2 = I915_READ(DSPARB2);
 493                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 494                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 495                 break;
 496         case PIPE_B:
 497                 dsparb = I915_READ(DSPARB);
 498                 dsparb2 = I915_READ(DSPARB2);
 499                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 500                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 501                 break;
 502         case PIPE_C:
 503                 dsparb2 = I915_READ(DSPARB2);
 504                 dsparb3 = I915_READ(DSPARB3);
 505                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 506                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 507                 break;
 508         default:
 509                 MISSING_CASE(pipe);
 510                 return;
 511         }
 512
 513         fifo_state->plane[PLANE_PRIMARY] = sprite0_start;
 514         fifo_state->plane[PLANE_SPRITE0] = sprite1_start - sprite0_start;
 515         fifo_state->plane[PLANE_SPRITE1] = 511 - sprite1_start;
 516         fifo_state->plane[PLANE_CURSOR] = 63;
 517 }
 518
 519 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 520 {
 521         uint32_t dsparb = I915_READ(DSPARB);
 522         int size;
 523
 524         size = dsparb & 0x7f;
 525         if (plane)
 526                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 527
 528         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 529                       plane ? "B" : "A", size);
 530
 531         return size;
 532 }
 533
 534 static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 535 {
 536         uint32_t dsparb = I915_READ(DSPARB);
 537         int size;
 538
 539         size = dsparb & 0x1ff;
 540         if (plane)
 541                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 542         size >>= 1; /* Convert to cachelines */
 543
 544         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 545                       plane ? "B" : "A", size);
 546
 547         return size;
 548 }
 549
 550 static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 551 {
 552         uint32_t dsparb = I915_READ(DSPARB);
 553         int size;
 554
 555         size = dsparb & 0x7f;
 556         size >>= 2; /* Convert to cachelines */
 557
 558         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 559                       plane ? "B" : "A",
 560                       size);
 561
 562         return size;
 563 }
 564
 565 /* Pineview has different values for various configs */
 566 static const struct intel_watermark_params pineview_display_wm = {
 567         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 568         .max_wm = PINEVIEW_MAX_WM,
 569         .default_wm = PINEVIEW_DFT_WM,
 570         .guard_size = PINEVIEW_GUARD_WM,
 571         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 572 };
 573 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 574         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 575         .max_wm = PINEVIEW_MAX_WM,
 576         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 577         .guard_size = PINEVIEW_GUARD_WM,
 578         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 579 };
 580 static const struct intel_watermark_params pineview_cursor_wm = {
 581         .fifo_size = PINEVIEW_CURSOR_FIFO,
 582         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 583         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 584         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 585         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 586 };
 587 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 588         .fifo_size = PINEVIEW_CURSOR_FIFO,
 589         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 590         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 591         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 592         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 593 };
 594 static const struct intel_watermark_params i965_cursor_wm_info = {
 595         .fifo_size = I965_CURSOR_FIFO,
 596         .max_wm = I965_CURSOR_MAX_WM,
 597         .default_wm = I965_CURSOR_DFT_WM,
 598         .guard_size = 2,
 599         .cacheline_size = I915_FIFO_LINE_SIZE,
 600 };
 601 static const struct intel_watermark_params i945_wm_info = {
 602         .fifo_size = I945_FIFO_SIZE,
 603         .max_wm = I915_MAX_WM,
 604         .default_wm = 1,
 605         .guard_size = 2,
 606         .cacheline_size = I915_FIFO_LINE_SIZE,
 607 };
 608 static const struct intel_watermark_params i915_wm_info = {
 609         .fifo_size = I915_FIFO_SIZE,
 610         .max_wm = I915_MAX_WM,
 611         .default_wm = 1,
 612         .guard_size = 2,
 613         .cacheline_size = I915_FIFO_LINE_SIZE,
 614 };
 615 static const struct intel_watermark_params i830_a_wm_info = {
 616         .fifo_size = I855GM_FIFO_SIZE,
 617         .max_wm = I915_MAX_WM,
 618         .default_wm = 1,
 619         .guard_size = 2,
 620         .cacheline_size = I830_FIFO_LINE_SIZE,
 621 };
 622 static const struct intel_watermark_params i830_bc_wm_info = {
 623         .fifo_size = I855GM_FIFO_SIZE,
 624         .max_wm = I915_MAX_WM/2,
 625         .default_wm = 1,
 626         .guard_size = 2,
 627         .cacheline_size = I830_FIFO_LINE_SIZE,
 628 };
 629 static const struct intel_watermark_params i845_wm_info = {
 630         .fifo_size = I830_FIFO_SIZE,
 631         .max_wm = I915_MAX_WM,
 632         .default_wm = 1,
 633         .guard_size = 2,
 634         .cacheline_size = I830_FIFO_LINE_SIZE,
 635 };
 636
 637 /**
 638  * intel_wm_method1 - Method 1 / "small buffer" watermark formula
 639  * @pixel_rate: Pipe pixel rate in kHz
 640  * @cpp: Plane bytes per pixel
 641  * @latency: Memory wakeup latency in 0.1us units
 642  *
 643  * Compute the watermark using the method 1 or "small buffer"
 644  * formula. The caller may additonally add extra cachelines
 645  * to account for TLB misses and clock crossings.
 646  *
 647  * This method is concerned with the short term drain rate
 648  * of the FIFO, ie. it does not account for blanking periods
 649  * which would effectively reduce the average drain rate across
 650  * a longer period. The name "small" refers to the fact the
 651  * FIFO is relatively small compared to the amount of data
 652  * fetched.
 653  *
 654  * The FIFO level vs. time graph might look something like:
 655  *
 656  *   |\   |\
 657  *   | \  | \
 658  * __---__---__ (- plane active, _ blanking)
 659  * -> time
 660  *
 661  * or perhaps like this:
 662  *
 663  *   |\|\  |\|\
 664  * __----__----__ (- plane active, _ blanking)
 665  * -> time
 666  *
 667  * Returns:
 668  * The watermark in bytes
 669  */
 670 static unsigned int intel_wm_method1(unsigned int pixel_rate,
 671                                      unsigned int cpp,
 672                                      unsigned int latency)
 673 {
 674         uint64_t ret;
 675
 676         ret = (uint64_t) pixel_rate * cpp * latency;
 677         ret = DIV_ROUND_UP_ULL(ret, 10000);
 678
 679         return ret;
 680 }
 681
 682 /**
 683  * intel_wm_method2 - Method 2 / "large buffer" watermark formula
 684  * @pixel_rate: Pipe pixel rate in kHz
 685  * @htotal: Pipe horizontal total
 686  * @width: Plane width in pixels
 687  * @cpp: Plane bytes per pixel
 688  * @latency: Memory wakeup latency in 0.1us units
 689  *
 690  * Compute the watermark using the method 2 or "large buffer"
 691  * formula. The caller may additonally add extra cachelines
 692  * to account for TLB misses and clock crossings.
 693  *
 694  * This method is concerned with the long term drain rate
 695  * of the FIFO, ie. it does account for blanking periods
 696  * which effectively reduce the average drain rate across
 697  * a longer period. The name "large" refers to the fact the
 698  * FIFO is relatively large compared to the amount of data
 699  * fetched.
 700  *
 701  * The FIFO level vs. time graph might look something like:
 702  *
 703  *    |\___       |\___
 704  *    |    \___   |    \___
 705  *    |        \  |        \
 706  * __ --__--__--__--__--__--__ (- plane active, _ blanking)
 707  * -> time
 708  *
 709  * Returns:
 710  * The watermark in bytes
 711  */
 712 static unsigned int intel_wm_method2(unsigned int pixel_rate,
 713                                      unsigned int htotal,
 714                                      unsigned int width,
 715                                      unsigned int cpp,
 716                                      unsigned int latency)
 717 {
 718         unsigned int ret;
 719
 720         /*
 721          * FIXME remove once all users are computing
 722          * watermarks in the correct place.
 723          */
 724         if (WARN_ON_ONCE(htotal == 0))
 725                 htotal = 1;
 726
 727         ret = (latency * pixel_rate) / (htotal * 10000);
 728         ret = (ret + 1) * width * cpp;
 729
 730         return ret;
 731 }
 732
 733 /**
 734  * intel_calculate_wm - calculate watermark level
 735  * @pixel_rate: pixel clock
 736  * @wm: chip FIFO params
 737  * @cpp: bytes per pixel
 738  * @latency_ns: memory latency for the platform
 739  *
 740  * Calculate the watermark level (the level at which the display plane will
 741  * start fetching from memory again).  Each chip has a different display
 742  * FIFO size and allocation, so the caller needs to figure that out and pass
 743  * in the correct intel_watermark_params structure.
 744  *
 745  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 746  * on the pixel size.  When it reaches the watermark level, it'll start
 747  * fetching FIFO line sized based chunks from memory until the FIFO fills
 748  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 749  * will occur, and a display engine hang could result.
 750  */
 751 static unsigned int intel_calculate_wm(int pixel_rate,
 752                                        const struct intel_watermark_params *wm,
 753                                        int fifo_size, int cpp,
 754                                        unsigned int latency_ns)
 755 {
 756         int entries, wm_size;
 757
 758         /*
 759          * Note: we need to make sure we don't overflow for various clock &
 760          * latency values.
 761          * clocks go from a few thousand to several hundred thousand.
 762          * latency is usually a few thousand
 763          */
 764         entries = intel_wm_method1(pixel_rate, cpp,
 765                                    latency_ns / 100);
 766         entries = DIV_ROUND_UP(entries, wm->cacheline_size) +
 767                 wm->guard_size;
 768         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries);
 769
 770         wm_size = fifo_size - entries;
 771         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
 772
 773         /* Don't promote wm_size to unsigned... */
 774         if (wm_size > wm->max_wm)
 775                 wm_size = wm->max_wm;
 776         if (wm_size <= 0)
 777                 wm_size = wm->default_wm;
 778
 779         /*
 780          * Bspec seems to indicate that the value shouldn't be lower than
 781          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 782          * Lets go for 8 which is the burst size since certain platforms
 783          * already use a hardcoded 8 (which is what the spec says should be
 784          * done).
 785          */
 786         if (wm_size <= 8)
 787                 wm_size = 8;
 788
 789         return wm_size;
 790 }
 791
 792 static bool is_disabling(int old, int new, int threshold)
 793 {
 794         return old >= threshold && new < threshold;
 795 }
 796
 797 static bool is_enabling(int old, int new, int threshold)
 798 {
 799         return old < threshold && new >= threshold;
 800 }
 801
 802 static int intel_wm_num_levels(struct drm_i915_private *dev_priv)
 803 {
 804         return dev_priv->wm.max_level + 1;
 805 }
 806
 807 static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
 808                                    const struct intel_plane_state *plane_state)
 809 {
 810         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 811
 812         /* FIXME check the 'enable' instead */
 813         if (!crtc_state->base.active)
 814                 return false;
 815
 816         /*
 817          * Treat cursor with fb as always visible since cursor updates
 818          * can happen faster than the vrefresh rate, and the current
 819          * watermark code doesn't handle that correctly. Cursor updates
 820          * which set/clear the fb or change the cursor size are going
 821          * to get throttled by intel_legacy_cursor_update() to work
 822          * around this problem with the watermark code.
 823          */
 824         if (plane->id == PLANE_CURSOR)
 825                 return plane_state->base.fb != NULL;
 826         else
 827                 return plane_state->base.visible;
 828 }
 829
 830 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
 831 {
 832         struct intel_crtc *crtc, *enabled = NULL;
 833
 834         for_each_intel_crtc(&dev_priv->drm, crtc) {
 835                 if (intel_crtc_active(crtc)) {
 836                         if (enabled)
 837                                 return NULL;
 838                         enabled = crtc;
 839                 }
 840         }
 841
 842         return enabled;
 843 }
 844
 845 static void pineview_update_wm(struct intel_crtc *unused_crtc)
 846 {
 847         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
 848         struct intel_crtc *crtc;
 849         const struct cxsr_latency *latency;
 850         u32 reg;
 851         unsigned int wm;
 852
 853         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
 854                                          dev_priv->is_ddr3,
 855                                          dev_priv->fsb_freq,
 856                                          dev_priv->mem_freq);
 857         if (!latency) {
 858                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 859                 intel_set_memory_cxsr(dev_priv, false);
 860                 return;
 861         }
 862
 863         crtc = single_enabled_crtc(dev_priv);
 864         if (crtc) {
 865                 const struct drm_display_mode *adjusted_mode =
 866                         &crtc->config->base.adjusted_mode;
 867                 const struct drm_framebuffer *fb =
 868                         crtc->base.primary->state->fb;
 869                 int cpp = fb->format->cpp[0];
 870                 int clock = adjusted_mode->crtc_clock;
 871
 872                 /* Display SR */
 873                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 874                                         pineview_display_wm.fifo_size,
 875                                         cpp, latency->display_sr);
 876                 reg = I915_READ(DSPFW1);
 877                 reg &= ~DSPFW_SR_MASK;
 878                 reg |= FW_WM(wm, SR);
 879                 I915_WRITE(DSPFW1, reg);
 880                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 881
 882                 /* cursor SR */
 883                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 884                                         pineview_display_wm.fifo_size,
 885                                         4, latency->cursor_sr);
 886                 reg = I915_READ(DSPFW3);
 887                 reg &= ~DSPFW_CURSOR_SR_MASK;
 888                 reg |= FW_WM(wm, CURSOR_SR);
 889                 I915_WRITE(DSPFW3, reg);
 890
 891                 /* Display HPLL off SR */
 892                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 893                                         pineview_display_hplloff_wm.fifo_size,
 894                                         cpp, latency->display_hpll_disable);
 895                 reg = I915_READ(DSPFW3);
 896                 reg &= ~DSPFW_HPLL_SR_MASK;
 897                 reg |= FW_WM(wm, HPLL_SR);
 898                 I915_WRITE(DSPFW3, reg);
 899
 900                 /* cursor HPLL off SR */
 901                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 902                                         pineview_display_hplloff_wm.fifo_size,
 903                                         4, latency->cursor_hpll_disable);
 904                 reg = I915_READ(DSPFW3);
 905                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 906                 reg |= FW_WM(wm, HPLL_CURSOR);
 907                 I915_WRITE(DSPFW3, reg);
 908                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 909
 910                 intel_set_memory_cxsr(dev_priv, true);
 911         } else {
 912                 intel_set_memory_cxsr(dev_priv, false);
 913         }
 914 }
 915
 916 /*
 917  * Documentation says:
 918  * "If the line size is small, the TLB fetches can get in the way of the
 919  *  data fetches, causing some lag in the pixel data return which is not
 920  *  accounted for in the above formulas. The following adjustment only
 921  *  needs to be applied if eight whole lines fit in the buffer at once.
 922  *  The WM is adjusted upwards by the difference between the FIFO size
 923  *  and the size of 8 whole lines. This adjustment is always performed
 924  *  in the actual pixel depth regardless of whether FBC is enabled or not."
 925  */
 926 static int g4x_tlb_miss_wa(int fifo_size, int width, int cpp)
 927 {
 928         int tlb_miss = fifo_size * 64 - width * cpp * 8;
 929
 930         return max(0, tlb_miss);
 931 }
 932
 933 static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
 934                                 const struct g4x_wm_values *wm)
 935 {
 936         enum pipe pipe;
 937
 938         for_each_pipe(dev_priv, pipe)
 939                 trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
 940
 941         I915_WRITE(DSPFW1,
 942                    FW_WM(wm->sr.plane, SR) |
 943                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
 944                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
 945                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
 946         I915_WRITE(DSPFW2,
 947                    (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
 948                    FW_WM(wm->sr.fbc, FBC_SR) |
 949                    FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
 950                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
 951                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
 952                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
 953         I915_WRITE(DSPFW3,
 954                    (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
 955                    FW_WM(wm->sr.cursor, CURSOR_SR) |
 956                    FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
 957                    FW_WM(wm->hpll.plane, HPLL_SR));
 958
 959         POSTING_READ(DSPFW1);
 960 }
 961
 962 #define FW_WM_VLV(value, plane) \
 963         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 964
 965 static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
 966                                 const struct vlv_wm_values *wm)
 967 {
 968         enum pipe pipe;
 969
 970         for_each_pipe(dev_priv, pipe) {
 971                 trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
 972
 973                 I915_WRITE(VLV_DDL(pipe),
 974                            (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
 975                            (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
 976                            (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
 977                            (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
 978         }
 979
 980         /*
 981          * Zero the (unused) WM1 watermarks, and also clear all the
 982          * high order bits so that there are no out of bounds values
 983          * present in the registers during the reprogramming.
 984          */
 985         I915_WRITE(DSPHOWM, 0);
 986         I915_WRITE(DSPHOWM1, 0);
 987         I915_WRITE(DSPFW4, 0);
 988         I915_WRITE(DSPFW5, 0);
 989         I915_WRITE(DSPFW6, 0);
 990
 991         I915_WRITE(DSPFW1,
 992                    FW_WM(wm->sr.plane, SR) |
 993                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
 994                    FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
 995                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
 996         I915_WRITE(DSPFW2,
 997                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
 998                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
 999                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
1000         I915_WRITE(DSPFW3,
1001                    FW_WM(wm->sr.cursor, CURSOR_SR));
1002
1003         if (IS_CHERRYVIEW(dev_priv)) {
1004                 I915_WRITE(DSPFW7_CHV,
1005                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1006                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1007                 I915_WRITE(DSPFW8_CHV,
1008                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
1009                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
1010                 I915_WRITE(DSPFW9_CHV,
1011                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
1012                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
1013                 I915_WRITE(DSPHOWM,
1014                            FW_WM(wm->sr.plane >> 9, SR_HI) |
1015                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
1016                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
1017                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
1018                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1019                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1020                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1021                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1022                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1023                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1024         } else {
1025                 I915_WRITE(DSPFW7,
1026                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1027                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1028                 I915_WRITE(DSPHOWM,
1029                            FW_WM(wm->sr.plane >> 9, SR_HI) |
1030                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1031                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1032                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1033                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1034                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1035                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1036         }
1037
1038         POSTING_READ(DSPFW1);
1039 }
1040
1041 #undef FW_WM_VLV
1042
1043 static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv)
1044 {
1045         /* all latencies in usec */
1046         dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
1047         dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
1048         dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
1049
1050         dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;
1051 }
1052
1053 static int g4x_plane_fifo_size(enum plane_id plane_id, int level)
1054 {
1055         /*
1056          * DSPCNTR[13] supposedly controls whether the
1057          * primary plane can use the FIFO space otherwise
1058          * reserved for the sprite plane. It's not 100% clear
1059          * what the actual FIFO size is, but it looks like we
1060          * can happily set both primary and sprite watermarks
1061          * up to 127 cachelines. So that would seem to mean
1062          * that either DSPCNTR[13] doesn't do anything, or that
1063          * the total FIFO is >= 256 cachelines in size. Either
1064          * way, we don't seem to have to worry about this
1065          * repartitioning as the maximum watermark value the
1066          * register can hold for each plane is lower than the
1067          * minimum FIFO size.
1068          */
1069         switch (plane_id) {
1070         case PLANE_CURSOR:
1071                 return 63;
1072         case PLANE_PRIMARY:
1073                 return level == G4X_WM_LEVEL_NORMAL ? 127 : 511;
1074         case PLANE_SPRITE0:
1075                 return level == G4X_WM_LEVEL_NORMAL ? 127 : 0;
1076         default:
1077                 MISSING_CASE(plane_id);
1078                 return 0;
1079         }
1080 }
1081
1082 static int g4x_fbc_fifo_size(int level)
1083 {
1084         switch (level) {
1085         case G4X_WM_LEVEL_SR:
1086                 return 7;
1087         case G4X_WM_LEVEL_HPLL:
1088                 return 15;
1089         default:
1090                 MISSING_CASE(level);
1091                 return 0;
1092         }
1093 }
1094
1095 static uint16_t g4x_compute_wm(const struct intel_crtc_state *crtc_state,
1096                                const struct intel_plane_state *plane_state,
1097                                int level)
1098 {
1099         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1100         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1101         const struct drm_display_mode *adjusted_mode =
1102                 &crtc_state->base.adjusted_mode;
1103         int clock, htotal, cpp, width, wm;
1104         int latency = dev_priv->wm.pri_latency[level] * 10;
1105
1106         if (latency == 0)
1107                 return USHRT_MAX;
1108
1109         if (!intel_wm_plane_visible(crtc_state, plane_state))
1110                 return 0;
1111
1112         /*
1113          * Not 100% sure which way ELK should go here as the
1114          * spec only says CL/CTG should assume 32bpp and BW
1115          * doesn't need to. But as these things followed the
1116          * mobile vs. desktop lines on gen3 as well, let's
1117          * assume ELK doesn't need this.
1118          *
1119          * The spec also fails to list such a restriction for
1120          * the HPLL watermark, which seems a little strange.
1121          * Let's use 32bpp for the HPLL watermark as well.
1122          */
1123         if (IS_GM45(dev_priv) && plane->id == PLANE_PRIMARY &&
1124             level != G4X_WM_LEVEL_NORMAL)
1125                 cpp = 4;
1126         else
1127                 cpp = plane_state->base.fb->format->cpp[0];
1128
1129         clock = adjusted_mode->crtc_clock;
1130         htotal = adjusted_mode->crtc_htotal;
1131
1132         if (plane->id == PLANE_CURSOR)
1133                 width = plane_state->base.crtc_w;
1134         else
1135                 width = drm_rect_width(&plane_state->base.dst);
1136
1137         if (plane->id == PLANE_CURSOR) {
1138                 wm = intel_wm_method2(clock, htotal, width, cpp, latency);
1139         } else if (plane->id == PLANE_PRIMARY &&
1140                    level == G4X_WM_LEVEL_NORMAL) {
1141                 wm = intel_wm_method1(clock, cpp, latency);
1142         } else {
1143                 int small, large;
1144
1145                 small = intel_wm_method1(clock, cpp, latency);
1146                 large = intel_wm_method2(clock, htotal, width, cpp, latency);
1147
1148                 wm = min(small, large);
1149         }
1150
1151         wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level),
1152                               width, cpp);
1153
1154         wm = DIV_ROUND_UP(wm, 64) + 2;
1155
1156         return min_t(int, wm, USHRT_MAX);
1157 }
1158
1159 static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1160                                  int level, enum plane_id plane_id, u16 value)
1161 {
1162         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1163         bool dirty = false;
1164
1165         for (; level < intel_wm_num_levels(dev_priv); level++) {
1166                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1167
1168                 dirty |= raw->plane[plane_id] != value;
1169                 raw->plane[plane_id] = value;
1170         }
1171
1172         return dirty;
1173 }
1174
1175 static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
1176                                int level, u16 value)
1177 {
1178         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1179         bool dirty = false;
1180
1181         /* NORMAL level doesn't have an FBC watermark */
1182         level = max(level, G4X_WM_LEVEL_SR);
1183
1184         for (; level < intel_wm_num_levels(dev_priv); level++) {
1185                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1186
1187                 dirty |= raw->fbc != value;
1188                 raw->fbc = value;
1189         }
1190
1191         return dirty;
1192 }
1193
1194 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1195                                    const struct intel_plane_state *pstate,
1196                                    uint32_t pri_val);
1197
1198 static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1199                                      const struct intel_plane_state *plane_state)
1200 {
1201         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1202         int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1203         enum plane_id plane_id = plane->id;
1204         bool dirty = false;
1205         int level;
1206
1207         if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1208                 dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1209                 if (plane_id == PLANE_PRIMARY)
1210                         dirty |= g4x_raw_fbc_wm_set(crtc_state, 0, 0);
1211                 goto out;
1212         }
1213
1214         for (level = 0; level < num_levels; level++) {
1215                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1216                 int wm, max_wm;
1217
1218                 wm = g4x_compute_wm(crtc_state, plane_state, level);
1219                 max_wm = g4x_plane_fifo_size(plane_id, level);
1220
1221                 if (wm > max_wm)
1222                         break;
1223
1224                 dirty |= raw->plane[plane_id] != wm;
1225                 raw->plane[plane_id] = wm;
1226
1227                 if (plane_id != PLANE_PRIMARY ||
1228                     level == G4X_WM_LEVEL_NORMAL)
1229                         continue;
1230
1231                 wm = ilk_compute_fbc_wm(crtc_state, plane_state,
1232                                         raw->plane[plane_id]);
1233                 max_wm = g4x_fbc_fifo_size(level);
1234
1235                 /*
1236                  * FBC wm is not mandatory as we
1237                  * can always just disable its use.
1238                  */
1239                 if (wm > max_wm)
1240                         wm = USHRT_MAX;
1241
1242                 dirty |= raw->fbc != wm;
1243                 raw->fbc = wm;
1244         }
1245
1246         /* mark watermarks as invalid */
1247         dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1248
1249         if (plane_id == PLANE_PRIMARY)
1250                 dirty |= g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
1251
1252  out:
1253         if (dirty) {
1254                 DRM_DEBUG_KMS("%s watermarks: normal=%d, SR=%d, HPLL=%d\n",
1255                               plane->base.name,
1256                               crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],
1257                               crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],
1258                               crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
1259
1260                 if (plane_id == PLANE_PRIMARY)
1261                         DRM_DEBUG_KMS("FBC watermarks: SR=%d, HPLL=%d\n",
1262                                       crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,
1263                                       crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);
1264         }
1265
1266         return dirty;
1267 }
1268
1269 static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1270                                       enum plane_id plane_id, int level)
1271 {
1272         const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1273
1274         return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level);
1275 }
1276
1277 static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
1278                                      int level)
1279 {
1280         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1281
1282         if (level > dev_priv->wm.max_level)
1283                 return false;
1284
1285         return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1286                 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1287                 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1288 }
1289
1290 /* mark all levels starting from 'level' as invalid */
1291 static void g4x_invalidate_wms(struct intel_crtc *crtc,
1292                                struct g4x_wm_state *wm_state, int level)
1293 {
1294         if (level <= G4X_WM_LEVEL_NORMAL) {
1295                 enum plane_id plane_id;
1296
1297                 for_each_plane_id_on_crtc(crtc, plane_id)
1298                         wm_state->wm.plane[plane_id] = USHRT_MAX;
1299         }
1300
1301         if (level <= G4X_WM_LEVEL_SR) {
1302                 wm_state->cxsr = false;
1303                 wm_state->sr.cursor = USHRT_MAX;
1304                 wm_state->sr.plane = USHRT_MAX;
1305                 wm_state->sr.fbc = USHRT_MAX;
1306         }
1307
1308         if (level <= G4X_WM_LEVEL_HPLL) {
1309                 wm_state->hpll_en = false;
1310                 wm_state->hpll.cursor = USHRT_MAX;
1311                 wm_state->hpll.plane = USHRT_MAX;
1312                 wm_state->hpll.fbc = USHRT_MAX;
1313         }
1314 }
1315
1316 static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1317 {
1318         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1319         struct intel_atomic_state *state =
1320                 to_intel_atomic_state(crtc_state->base.state);
1321         struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
1322         int num_active_planes = hweight32(crtc_state->active_planes &
1323                                           ~BIT(PLANE_CURSOR));
1324         const struct g4x_pipe_wm *raw;
1325         struct intel_plane_state *plane_state;
1326         struct intel_plane *plane;
1327         enum plane_id plane_id;
1328         int i, level;
1329         unsigned int dirty = 0;
1330
1331         for_each_intel_plane_in_state(state, plane, plane_state, i) {
1332                 const struct intel_plane_state *old_plane_state =
1333                         to_intel_plane_state(plane->base.state);
1334
1335                 if (plane_state->base.crtc != &crtc->base &&
1336                     old_plane_state->base.crtc != &crtc->base)
1337                         continue;
1338
1339                 if (g4x_raw_plane_wm_compute(crtc_state, plane_state))
1340                         dirty |= BIT(plane->id);
1341         }
1342
1343         if (!dirty)
1344                 return 0;
1345
1346         level = G4X_WM_LEVEL_NORMAL;
1347         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1348                 goto out;
1349
1350         raw = &crtc_state->wm.g4x.raw[level];
1351         for_each_plane_id_on_crtc(crtc, plane_id)
1352                 wm_state->wm.plane[plane_id] = raw->plane[plane_id];
1353
1354         level = G4X_WM_LEVEL_SR;
1355
1356         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1357                 goto out;
1358
1359         raw = &crtc_state->wm.g4x.raw[level];
1360         wm_state->sr.plane = raw->plane[PLANE_PRIMARY];
1361         wm_state->sr.cursor = raw->plane[PLANE_CURSOR];
1362         wm_state->sr.fbc = raw->fbc;
1363
1364         wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY);
1365
1366         level = G4X_WM_LEVEL_HPLL;
1367
1368         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1369                 goto out;
1370
1371         raw = &crtc_state->wm.g4x.raw[level];
1372         wm_state->hpll.plane = raw->plane[PLANE_PRIMARY];
1373         wm_state->hpll.cursor = raw->plane[PLANE_CURSOR];
1374         wm_state->hpll.fbc = raw->fbc;
1375
1376         wm_state->hpll_en = wm_state->cxsr;
1377
1378         level++;
1379
1380  out:
1381         if (level == G4X_WM_LEVEL_NORMAL)
1382                 return -EINVAL;
1383
1384         /* invalidate the higher levels */
1385         g4x_invalidate_wms(crtc, wm_state, level);
1386
1387         /*
1388          * Determine if the FBC watermark(s) can be used. IF
1389          * this isn't the case we prefer to disable the FBC
1390          ( watermark(s) rather than disable the SR/HPLL
1391          * level(s) entirely.
1392          */
1393         wm_state->fbc_en = level > G4X_WM_LEVEL_NORMAL;
1394
1395         if (level >= G4X_WM_LEVEL_SR &&
1396             wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR))
1397                 wm_state->fbc_en = false;
1398         else if (level >= G4X_WM_LEVEL_HPLL &&
1399                  wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))
1400                 wm_state->fbc_en = false;
1401
1402         return 0;
1403 }
1404
1405 static int g4x_compute_intermediate_wm(struct drm_device *dev,
1406                                        struct intel_crtc *crtc,
1407                                        struct intel_crtc_state *crtc_state)
1408 {
1409         struct g4x_wm_state *intermediate = &crtc_state->wm.g4x.intermediate;
1410         const struct g4x_wm_state *optimal = &crtc_state->wm.g4x.optimal;
1411         const struct g4x_wm_state *active = &crtc->wm.active.g4x;
1412         enum plane_id plane_id;
1413
1414         intermediate->cxsr = optimal->cxsr && active->cxsr &&
1415                 !crtc_state->disable_cxsr;
1416         intermediate->hpll_en = optimal->hpll_en && active->hpll_en &&
1417                 !crtc_state->disable_cxsr;
1418         intermediate->fbc_en = optimal->fbc_en && active->fbc_en;
1419
1420         for_each_plane_id_on_crtc(crtc, plane_id) {
1421                 intermediate->wm.plane[plane_id] =
1422                         max(optimal->wm.plane[plane_id],
1423                             active->wm.plane[plane_id]);
1424
1425                 WARN_ON(intermediate->wm.plane[plane_id] >
1426                         g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL));
1427         }
1428
1429         intermediate->sr.plane = max(optimal->sr.plane,
1430                                      active->sr.plane);
1431         intermediate->sr.cursor = max(optimal->sr.cursor,
1432                                       active->sr.cursor);
1433         intermediate->sr.fbc = max(optimal->sr.fbc,
1434                                    active->sr.fbc);
1435
1436         intermediate->hpll.plane = max(optimal->hpll.plane,
1437                                        active->hpll.plane);
1438         intermediate->hpll.cursor = max(optimal->hpll.cursor,
1439                                         active->hpll.cursor);
1440         intermediate->hpll.fbc = max(optimal->hpll.fbc,
1441                                      active->hpll.fbc);
1442
1443         WARN_ON((intermediate->sr.plane >
1444                  g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_SR) ||
1445                  intermediate->sr.cursor >
1446                  g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_SR)) &&
1447                 intermediate->cxsr);
1448         WARN_ON((intermediate->sr.plane >
1449                  g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) ||
1450                  intermediate->sr.cursor >
1451                  g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) &&
1452                 intermediate->hpll_en);
1453
1454         WARN_ON(intermediate->sr.fbc > g4x_fbc_fifo_size(1) &&
1455                 intermediate->fbc_en && intermediate->cxsr);
1456         WARN_ON(intermediate->hpll.fbc > g4x_fbc_fifo_size(2) &&
1457                 intermediate->fbc_en && intermediate->hpll_en);
1458
1459         /*
1460          * If our intermediate WM are identical to the final WM, then we can
1461          * omit the post-vblank programming; only update if it's different.
1462          */
1463         if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
1464                 crtc_state->wm.need_postvbl_update = true;
1465
1466         return 0;
1467 }
1468
1469 static void g4x_merge_wm(struct drm_i915_private *dev_priv,
1470                          struct g4x_wm_values *wm)
1471 {
1472         struct intel_crtc *crtc;
1473         int num_active_crtcs = 0;
1474
1475         wm->cxsr = true;
1476         wm->hpll_en = true;
1477         wm->fbc_en = true;
1478
1479         for_each_intel_crtc(&dev_priv->drm, crtc) {
1480                 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1481
1482                 if (!crtc->active)
1483                         continue;
1484
1485                 if (!wm_state->cxsr)
1486                         wm->cxsr = false;
1487                 if (!wm_state->hpll_en)
1488                         wm->hpll_en = false;
1489                 if (!wm_state->fbc_en)
1490                         wm->fbc_en = false;
1491
1492                 num_active_crtcs++;
1493         }
1494
1495         if (num_active_crtcs != 1) {
1496                 wm->cxsr = false;
1497                 wm->hpll_en = false;
1498                 wm->fbc_en = false;
1499         }
1500
1501         for_each_intel_crtc(&dev_priv->drm, crtc) {
1502                 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1503                 enum pipe pipe = crtc->pipe;
1504
1505                 wm->pipe[pipe] = wm_state->wm;
1506                 if (crtc->active && wm->cxsr)
1507                         wm->sr = wm_state->sr;
1508                 if (crtc->active && wm->hpll_en)
1509                         wm->hpll = wm_state->hpll;
1510         }
1511 }
1512
1513 static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
1514 {
1515         struct g4x_wm_values *old_wm = &dev_priv->wm.g4x;
1516         struct g4x_wm_values new_wm = {};
1517
1518         g4x_merge_wm(dev_priv, &new_wm);
1519
1520         if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
1521                 return;
1522
1523         if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
1524                 _intel_set_memory_cxsr(dev_priv, false);
1525
1526         g4x_write_wm_values(dev_priv, &new_wm);
1527
1528         if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
1529                 _intel_set_memory_cxsr(dev_priv, true);
1530
1531         *old_wm = new_wm;
1532 }
1533
1534 static void g4x_initial_watermarks(struct intel_atomic_state *state,
1535                                    struct intel_crtc_state *crtc_state)
1536 {
1537         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1538         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1539
1540         mutex_lock(&dev_priv->wm.wm_mutex);
1541         crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
1542         g4x_program_watermarks(dev_priv);
1543         mutex_unlock(&dev_priv->wm.wm_mutex);
1544 }
1545
1546 static void g4x_optimize_watermarks(struct intel_atomic_state *state,
1547                                     struct intel_crtc_state *crtc_state)
1548 {
1549         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1550         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1551
1552         if (!crtc_state->wm.need_postvbl_update)
1553                 return;
1554
1555         mutex_lock(&dev_priv->wm.wm_mutex);
1556         intel_crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
1557         g4x_program_watermarks(dev_priv);
1558         mutex_unlock(&dev_priv->wm.wm_mutex);
1559 }
1560
1561 /* latency must be in 0.1us units. */
1562 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
1563                                    unsigned int htotal,
1564                                    unsigned int width,
1565                                    unsigned int cpp,
1566                                    unsigned int latency)
1567 {
1568         unsigned int ret;
1569
1570         ret = intel_wm_method2(pixel_rate, htotal,
1571                                width, cpp, latency);
1572         ret = DIV_ROUND_UP(ret, 64);
1573
1574         return ret;
1575 }
1576
1577 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
1578 {
1579         /* all latencies in usec */
1580         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
1581
1582         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
1583
1584         if (IS_CHERRYVIEW(dev_priv)) {
1585                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
1586                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
1587
1588                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
1589         }
1590 }
1591
1592 static uint16_t vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
1593                                      const struct intel_plane_state *plane_state,
1594                                      int level)
1595 {
1596         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1597         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1598         const struct drm_display_mode *adjusted_mode =
1599                 &crtc_state->base.adjusted_mode;
1600         int clock, htotal, cpp, width, wm;
1601
1602         if (dev_priv->wm.pri_latency[level] == 0)
1603                 return USHRT_MAX;
1604
1605         if (!intel_wm_plane_visible(crtc_state, plane_state))
1606                 return 0;
1607
1608         cpp = plane_state->base.fb->format->cpp[0];
1609         clock = adjusted_mode->crtc_clock;
1610         htotal = adjusted_mode->crtc_htotal;
1611         width = crtc_state->pipe_src_w;
1612
1613         if (plane->id == PLANE_CURSOR) {
1614                 /*
1615                  * FIXME the formula gives values that are
1616                  * too big for the cursor FIFO, and hence we
1617                  * would never be able to use cursors. For
1618                  * now just hardcode the watermark.
1619                  */
1620                 wm = 63;
1621         } else {
1622                 wm = vlv_wm_method2(clock, htotal, width, cpp,
1623                                     dev_priv->wm.pri_latency[level] * 10);
1624         }
1625
1626         return min_t(int, wm, USHRT_MAX);
1627 }
1628
1629 static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
1630 {
1631         return (active_planes & (BIT(PLANE_SPRITE0) |
1632                                  BIT(PLANE_SPRITE1))) == BIT(PLANE_SPRITE1);
1633 }
1634
1635 static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
1636 {
1637         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1638         const struct g4x_pipe_wm *raw =
1639                 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
1640         struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
1641         unsigned int active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1642         int num_active_planes = hweight32(active_planes);
1643         const int fifo_size = 511;
1644         int fifo_extra, fifo_left = fifo_size;
1645         int sprite0_fifo_extra = 0;
1646         unsigned int total_rate;
1647         enum plane_id plane_id;
1648
1649         /*
1650          * When enabling sprite0 after sprite1 has already been enabled
1651          * we tend to get an underrun unless sprite0 already has some
1652          * FIFO space allcoated. Hence we always allocate at least one
1653          * cacheline for sprite0 whenever sprite1 is enabled.
1654          *
1655          * All other plane enable sequences appear immune to this problem.
1656          */
1657         if (vlv_need_sprite0_fifo_workaround(active_planes))
1658                 sprite0_fifo_extra = 1;
1659
1660         total_rate = raw->plane[PLANE_PRIMARY] +
1661                 raw->plane[PLANE_SPRITE0] +
1662                 raw->plane[PLANE_SPRITE1] +
1663                 sprite0_fifo_extra;
1664
1665         if (total_rate > fifo_size)
1666                 return -EINVAL;
1667
1668         if (total_rate == 0)
1669                 total_rate = 1;
1670
1671         for_each_plane_id_on_crtc(crtc, plane_id) {
1672                 unsigned int rate;
1673
1674                 if ((active_planes & BIT(plane_id)) == 0) {
1675                         fifo_state->plane[plane_id] = 0;
1676                         continue;
1677                 }
1678
1679                 rate = raw->plane[plane_id];
1680                 fifo_state->plane[plane_id] = fifo_size * rate / total_rate;
1681                 fifo_left -= fifo_state->plane[plane_id];
1682         }
1683
1684         fifo_state->plane[PLANE_SPRITE0] += sprite0_fifo_extra;
1685         fifo_left -= sprite0_fifo_extra;
1686
1687         fifo_state->plane[PLANE_CURSOR] = 63;
1688
1689         fifo_extra = DIV_ROUND_UP(fifo_left, num_active_planes ?: 1);
1690
1691         /* spread the remainder evenly */
1692         for_each_plane_id_on_crtc(crtc, plane_id) {
1693                 int plane_extra;
1694
1695                 if (fifo_left == 0)
1696                         break;
1697
1698                 if ((active_planes & BIT(plane_id)) == 0)
1699                         continue;
1700
1701                 plane_extra = min(fifo_extra, fifo_left);
1702                 fifo_state->plane[plane_id] += plane_extra;
1703                 fifo_left -= plane_extra;
1704         }
1705
1706         WARN_ON(active_planes != 0 && fifo_left != 0);
1707
1708         /* give it all to the first plane if none are active */
1709         if (active_planes == 0) {
1710                 WARN_ON(fifo_left != fifo_size);
1711                 fifo_state->plane[PLANE_PRIMARY] = fifo_left;
1712         }
1713
1714         return 0;
1715 }
1716
1717 /* mark all levels starting from 'level' as invalid */
1718 static void vlv_invalidate_wms(struct intel_crtc *crtc,
1719                                struct vlv_wm_state *wm_state, int level)
1720 {
1721         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1722
1723         for (; level < intel_wm_num_levels(dev_priv); level++) {
1724                 enum plane_id plane_id;
1725
1726                 for_each_plane_id_on_crtc(crtc, plane_id)
1727                         wm_state->wm[level].plane[plane_id] = USHRT_MAX;
1728
1729                 wm_state->sr[level].cursor = USHRT_MAX;
1730                 wm_state->sr[level].plane = USHRT_MAX;
1731         }
1732 }
1733
1734 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
1735 {
1736         if (wm > fifo_size)
1737                 return USHRT_MAX;
1738         else
1739                 return fifo_size - wm;
1740 }
1741
1742 /*
1743  * Starting from 'level' set all higher
1744  * levels to 'value' in the "raw" watermarks.
1745  */
1746 static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1747                                  int level, enum plane_id plane_id, u16 value)
1748 {
1749         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1750         int num_levels = intel_wm_num_levels(dev_priv);
1751         bool dirty = false;
1752
1753         for (; level < num_levels; level++) {
1754                 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1755
1756                 dirty |= raw->plane[plane_id] != value;
1757                 raw->plane[plane_id] = value;
1758         }
1759
1760         return dirty;
1761 }
1762
1763 static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1764                                      const struct intel_plane_state *plane_state)
1765 {
1766         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1767         enum plane_id plane_id = plane->id;
1768         int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1769         int level;
1770         bool dirty = false;
1771
1772         if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1773                 dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1774                 goto out;
1775         }
1776
1777         for (level = 0; level < num_levels; level++) {
1778                 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1779                 int wm = vlv_compute_wm_level(crtc_state, plane_state, level);
1780                 int max_wm = plane_id == PLANE_CURSOR ? 63 : 511;
1781
1782                 if (wm > max_wm)
1783                         break;
1784
1785                 dirty |= raw->plane[plane_id] != wm;
1786                 raw->plane[plane_id] = wm;
1787         }
1788
1789         /* mark all higher levels as invalid */
1790         dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1791
1792 out:
1793         if (dirty)
1794                 DRM_DEBUG_KMS("%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n",
1795                               plane->base.name,
1796                               crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
1797                               crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],
1798                               crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);
1799
1800         return dirty;
1801 }
1802
1803 static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1804                                       enum plane_id plane_id, int level)
1805 {
1806         const struct g4x_pipe_wm *raw =
1807                 &crtc_state->wm.vlv.raw[level];
1808         const struct vlv_fifo_state *fifo_state =
1809                 &crtc_state->wm.vlv.fifo_state;
1810
1811         return raw->plane[plane_id] <= fifo_state->plane[plane_id];
1812 }
1813
1814 static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level)
1815 {
1816         return vlv_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1817                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1818                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE1, level) &&
1819                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1820 }
1821
1822 static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1823 {
1824         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1825         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1826         struct intel_atomic_state *state =
1827                 to_intel_atomic_state(crtc_state->base.state);
1828         struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
1829         const struct vlv_fifo_state *fifo_state =
1830                 &crtc_state->wm.vlv.fifo_state;
1831         int num_active_planes = hweight32(crtc_state->active_planes &
1832                                           ~BIT(PLANE_CURSOR));
1833         bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base);
1834         struct intel_plane_state *plane_state;
1835         struct intel_plane *plane;
1836         enum plane_id plane_id;
1837         int level, ret, i;
1838         unsigned int dirty = 0;
1839
1840         for_each_intel_plane_in_state(state, plane, plane_state, i) {
1841                 const struct intel_plane_state *old_plane_state =
1842                         to_intel_plane_state(plane->base.state);
1843
1844                 if (plane_state->base.crtc != &crtc->base &&
1845                     old_plane_state->base.crtc != &crtc->base)
1846                         continue;
1847
1848                 if (vlv_raw_plane_wm_compute(crtc_state, plane_state))
1849                         dirty |= BIT(plane->id);
1850         }
1851
1852         /*
1853          * DSPARB registers may have been reset due to the
1854          * power well being turned off. Make sure we restore
1855          * them to a consistent state even if no primary/sprite
1856          * planes are initially active.
1857          */
1858         if (needs_modeset)
1859                 crtc_state->fifo_changed = true;
1860
1861         if (!dirty)
1862                 return 0;
1863
1864         /* cursor changes don't warrant a FIFO recompute */
1865         if (dirty & ~BIT(PLANE_CURSOR)) {
1866                 const struct intel_crtc_state *old_crtc_state =
1867                         to_intel_crtc_state(crtc->base.state);
1868                 const struct vlv_fifo_state *old_fifo_state =
1869                         &old_crtc_state->wm.vlv.fifo_state;
1870
1871                 ret = vlv_compute_fifo(crtc_state);
1872                 if (ret)
1873                         return ret;
1874
1875                 if (needs_modeset ||
1876                     memcmp(old_fifo_state, fifo_state,
1877                            sizeof(*fifo_state)) != 0)
1878                         crtc_state->fifo_changed = true;
1879         }
1880
1881         /* initially allow all levels */
1882         wm_state->num_levels = intel_wm_num_levels(dev_priv);
1883         /*
1884          * Note that enabling cxsr with no primary/sprite planes
1885          * enabled can wedge the pipe. Hence we only allow cxsr
1886          * with exactly one enabled primary/sprite plane.
1887          */
1888         wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1;
1889
1890         for (level = 0; level < wm_state->num_levels; level++) {
1891                 const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1892                 const int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1893
1894                 if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
1895                         break;
1896
1897                 for_each_plane_id_on_crtc(crtc, plane_id) {
1898                         wm_state->wm[level].plane[plane_id] =
1899                                 vlv_invert_wm_value(raw->plane[plane_id],
1900                                                     fifo_state->plane[plane_id]);
1901                 }
1902
1903                 wm_state->sr[level].plane =
1904                         vlv_invert_wm_value(max3(raw->plane[PLANE_PRIMARY],
1905                                                  raw->plane[PLANE_SPRITE0],
1906                                                  raw->plane[PLANE_SPRITE1]),
1907                                             sr_fifo_size);
1908
1909                 wm_state->sr[level].cursor =
1910                         vlv_invert_wm_value(raw->plane[PLANE_CURSOR],
1911                                             63);
1912         }
1913
1914         if (level == 0)
1915                 return -EINVAL;
1916
1917         /* limit to only levels we can actually handle */
1918         wm_state->num_levels = level;
1919
1920         /* invalidate the higher levels */
1921         vlv_invalidate_wms(crtc, wm_state, level);
1922
1923         return 0;
1924 }
1925
1926 #define VLV_FIFO(plane, value) \
1927         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1928
1929 static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
1930                                    struct intel_crtc_state *crtc_state)
1931 {
1932         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1933         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1934         const struct vlv_fifo_state *fifo_state =
1935                 &crtc_state->wm.vlv.fifo_state;
1936         int sprite0_start, sprite1_start, fifo_size;
1937
1938         if (!crtc_state->fifo_changed)
1939                 return;
1940
1941         sprite0_start = fifo_state->plane[PLANE_PRIMARY];
1942         sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start;
1943         fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start;
1944
1945         WARN_ON(fifo_state->plane[PLANE_CURSOR] != 63);
1946         WARN_ON(fifo_size != 511);
1947
1948         trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size);
1949
1950         /*
1951          * uncore.lock serves a double purpose here. It allows us to
1952          * use the less expensive I915_{READ,WRITE}_FW() functions, and
1953          * it protects the DSPARB registers from getting clobbered by
1954          * parallel updates from multiple pipes.
1955          *
1956          * intel_pipe_update_start() has already disabled interrupts
1957          * for us, so a plain spin_lock() is sufficient here.
1958          */
1959         spin_lock(&dev_priv->uncore.lock);
1960
1961         switch (crtc->pipe) {
1962                 uint32_t dsparb, dsparb2, dsparb3;
1963         case PIPE_A:
1964                 dsparb = I915_READ_FW(DSPARB);
1965                 dsparb2 = I915_READ_FW(DSPARB2);
1966
1967                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1968                             VLV_FIFO(SPRITEB, 0xff));
1969                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1970                            VLV_FIFO(SPRITEB, sprite1_start));
1971
1972                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1973                              VLV_FIFO(SPRITEB_HI, 0x1));
1974                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1975                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1976
1977                 I915_WRITE_FW(DSPARB, dsparb);
1978                 I915_WRITE_FW(DSPARB2, dsparb2);
1979                 break;
1980         case PIPE_B:
1981                 dsparb = I915_READ_FW(DSPARB);
1982                 dsparb2 = I915_READ_FW(DSPARB2);
1983
1984                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1985                             VLV_FIFO(SPRITED, 0xff));
1986                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1987                            VLV_FIFO(SPRITED, sprite1_start));
1988
1989                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1990                              VLV_FIFO(SPRITED_HI, 0xff));
1991                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1992                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1993
1994                 I915_WRITE_FW(DSPARB, dsparb);
1995                 I915_WRITE_FW(DSPARB2, dsparb2);
1996                 break;
1997         case PIPE_C:
1998                 dsparb3 = I915_READ_FW(DSPARB3);
1999                 dsparb2 = I915_READ_FW(DSPARB2);
2000
2001                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
2002                              VLV_FIFO(SPRITEF, 0xff));
2003                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
2004                             VLV_FIFO(SPRITEF, sprite1_start));
2005
2006                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
2007                              VLV_FIFO(SPRITEF_HI, 0xff));
2008                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
2009                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
2010
2011                 I915_WRITE_FW(DSPARB3, dsparb3);
2012                 I915_WRITE_FW(DSPARB2, dsparb2);
2013                 break;
2014         default:
2015                 break;
2016         }
2017
2018         POSTING_READ_FW(DSPARB);
2019
2020         spin_unlock(&dev_priv->uncore.lock);
2021 }
2022
2023 #undef VLV_FIFO
2024
2025 static int vlv_compute_intermediate_wm(struct drm_device *dev,
2026                                        struct intel_crtc *crtc,
2027                                        struct intel_crtc_state *crtc_state)
2028 {
2029         struct vlv_wm_state *intermediate = &crtc_state->wm.vlv.intermediate;
2030         const struct vlv_wm_state *optimal = &crtc_state->wm.vlv.optimal;
2031         const struct vlv_wm_state *active = &crtc->wm.active.vlv;
2032         int level;
2033
2034         intermediate->num_levels = min(optimal->num_levels, active->num_levels);
2035         intermediate->cxsr = optimal->cxsr && active->cxsr &&
2036                 !crtc_state->disable_cxsr;
2037
2038         for (level = 0; level < intermediate->num_levels; level++) {
2039                 enum plane_id plane_id;
2040
2041                 for_each_plane_id_on_crtc(crtc, plane_id) {
2042                         intermediate->wm[level].plane[plane_id] =
2043                                 min(optimal->wm[level].plane[plane_id],
2044                                     active->wm[level].plane[plane_id]);
2045                 }
2046
2047                 intermediate->sr[level].plane = min(optimal->sr[level].plane,
2048                                                     active->sr[level].plane);
2049                 intermediate->sr[level].cursor = min(optimal->sr[level].cursor,
2050                                                      active->sr[level].cursor);
2051         }
2052
2053         vlv_invalidate_wms(crtc, intermediate, level);
2054
2055         /*
2056          * If our intermediate WM are identical to the final WM, then we can
2057          * omit the post-vblank programming; only update if it's different.
2058          */
2059         if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
2060                 crtc_state->wm.need_postvbl_update = true;
2061
2062         return 0;
2063 }
2064
2065 static void vlv_merge_wm(struct drm_i915_private *dev_priv,
2066                          struct vlv_wm_values *wm)
2067 {
2068         struct intel_crtc *crtc;
2069         int num_active_crtcs = 0;
2070
2071         wm->level = dev_priv->wm.max_level;
2072         wm->cxsr = true;
2073
2074         for_each_intel_crtc(&dev_priv->drm, crtc) {
2075                 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2076
2077                 if (!crtc->active)
2078                         continue;
2079
2080                 if (!wm_state->cxsr)
2081                         wm->cxsr = false;
2082
2083                 num_active_crtcs++;
2084                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
2085         }
2086
2087         if (num_active_crtcs != 1)
2088                 wm->cxsr = false;
2089
2090         if (num_active_crtcs > 1)
2091                 wm->level = VLV_WM_LEVEL_PM2;
2092
2093         for_each_intel_crtc(&dev_priv->drm, crtc) {
2094                 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2095                 enum pipe pipe = crtc->pipe;
2096
2097                 wm->pipe[pipe] = wm_state->wm[wm->level];
2098                 if (crtc->active && wm->cxsr)
2099                         wm->sr = wm_state->sr[wm->level];
2100
2101                 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
2102                 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
2103                 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
2104                 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
2105         }
2106 }
2107
2108 static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
2109 {
2110         struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
2111         struct vlv_wm_values new_wm = {};
2112
2113         vlv_merge_wm(dev_priv, &new_wm);
2114
2115         if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
2116                 return;
2117
2118         if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2119                 chv_set_memory_dvfs(dev_priv, false);
2120
2121         if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2122                 chv_set_memory_pm5(dev_priv, false);
2123
2124         if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
2125                 _intel_set_memory_cxsr(dev_priv, false);
2126
2127         vlv_write_wm_values(dev_priv, &new_wm);
2128
2129         if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
2130                 _intel_set_memory_cxsr(dev_priv, true);
2131
2132         if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2133                 chv_set_memory_pm5(dev_priv, true);
2134
2135         if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2136                 chv_set_memory_dvfs(dev_priv, true);
2137
2138         *old_wm = new_wm;
2139 }
2140
2141 static void vlv_initial_watermarks(struct intel_atomic_state *state,
2142                                    struct intel_crtc_state *crtc_state)
2143 {
2144         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2145         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2146
2147         mutex_lock(&dev_priv->wm.wm_mutex);
2148         crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
2149         vlv_program_watermarks(dev_priv);
2150         mutex_unlock(&dev_priv->wm.wm_mutex);
2151 }
2152
2153 static void vlv_optimize_watermarks(struct intel_atomic_state *state,
2154                                     struct intel_crtc_state *crtc_state)
2155 {
2156         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2157         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2158
2159         if (!crtc_state->wm.need_postvbl_update)
2160                 return;
2161
2162         mutex_lock(&dev_priv->wm.wm_mutex);
2163         intel_crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
2164         vlv_program_watermarks(dev_priv);
2165         mutex_unlock(&dev_priv->wm.wm_mutex);
2166 }
2167
2168 static void i965_update_wm(struct intel_crtc *unused_crtc)
2169 {
2170         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2171         struct intel_crtc *crtc;
2172         int srwm = 1;
2173         int cursor_sr = 16;
2174         bool cxsr_enabled;
2175
2176         /* Calc sr entries for one plane configs */
2177         crtc = single_enabled_crtc(dev_priv);
2178         if (crtc) {
2179                 /* self-refresh has much higher latency */
2180                 static const int sr_latency_ns = 12000;
2181                 const struct drm_display_mode *adjusted_mode =
2182                         &crtc->config->base.adjusted_mode;
2183                 const struct drm_framebuffer *fb =
2184                         crtc->base.primary->state->fb;
2185                 int clock = adjusted_mode->crtc_clock;
2186                 int htotal = adjusted_mode->crtc_htotal;
2187                 int hdisplay = crtc->config->pipe_src_w;
2188                 int cpp = fb->format->cpp[0];
2189                 int entries;
2190
2191                 entries = intel_wm_method2(clock, htotal,
2192                                            hdisplay, cpp, sr_latency_ns / 100);
2193                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
2194                 srwm = I965_FIFO_SIZE - entries;
2195                 if (srwm < 0)
2196                         srwm = 1;
2197                 srwm &= 0x1ff;
2198                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
2199                               entries, srwm);
2200
2201                 entries = intel_wm_method2(clock, htotal,
2202                                            crtc->base.cursor->state->crtc_w, 4,
2203                                            sr_latency_ns / 100);
2204                 entries = DIV_ROUND_UP(entries,
2205                                        i965_cursor_wm_info.cacheline_size) +
2206                         i965_cursor_wm_info.guard_size;
2207
2208                 cursor_sr = i965_cursor_wm_info.fifo_size - entries;
2209                 if (cursor_sr > i965_cursor_wm_info.max_wm)
2210                         cursor_sr = i965_cursor_wm_info.max_wm;
2211
2212                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
2213                               "cursor %d\n", srwm, cursor_sr);
2214
2215                 cxsr_enabled = true;
2216         } else {
2217                 cxsr_enabled = false;
2218                 /* Turn off self refresh if both pipes are enabled */
2219                 intel_set_memory_cxsr(dev_priv, false);
2220         }
2221
2222         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2223                       srwm);
2224
2225         /* 965 has limitations... */
2226         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
2227                    FW_WM(8, CURSORB) |
2228                    FW_WM(8, PLANEB) |
2229                    FW_WM(8, PLANEA));
2230         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
2231                    FW_WM(8, PLANEC_OLD));
2232         /* update cursor SR watermark */
2233         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
2234
2235         if (cxsr_enabled)
2236                 intel_set_memory_cxsr(dev_priv, true);
2237 }
2238
2239 #undef FW_WM
2240
2241 static void i9xx_update_wm(struct intel_crtc *unused_crtc)
2242 {
2243         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2244         const struct intel_watermark_params *wm_info;
2245         uint32_t fwater_lo;
2246         uint32_t fwater_hi;
2247         int cwm, srwm = 1;
2248         int fifo_size;
2249         int planea_wm, planeb_wm;
2250         struct intel_crtc *crtc, *enabled = NULL;
2251
2252         if (IS_I945GM(dev_priv))
2253                 wm_info = &i945_wm_info;
2254         else if (!IS_GEN2(dev_priv))
2255                 wm_info = &i915_wm_info;
2256         else
2257                 wm_info = &i830_a_wm_info;
2258
2259         fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
2260         crtc = intel_get_crtc_for_plane(dev_priv, 0);
2261         if (intel_crtc_active(crtc)) {
2262                 const struct drm_display_mode *adjusted_mode =
2263                         &crtc->config->base.adjusted_mode;
2264                 const struct drm_framebuffer *fb =
2265                         crtc->base.primary->state->fb;
2266                 int cpp;
2267
2268                 if (IS_GEN2(dev_priv))
2269                         cpp = 4;
2270                 else
2271                         cpp = fb->format->cpp[0];
2272
2273                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2274                                                wm_info, fifo_size, cpp,
2275                                                pessimal_latency_ns);
2276                 enabled = crtc;
2277         } else {
2278                 planea_wm = fifo_size - wm_info->guard_size;
2279                 if (planea_wm > (long)wm_info->max_wm)
2280                         planea_wm = wm_info->max_wm;
2281         }
2282
2283         if (IS_GEN2(dev_priv))
2284                 wm_info = &i830_bc_wm_info;
2285
2286         fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
2287         crtc = intel_get_crtc_for_plane(dev_priv, 1);
2288         if (intel_crtc_active(crtc)) {
2289                 const struct drm_display_mode *adjusted_mode =
2290                         &crtc->config->base.adjusted_mode;
2291                 const struct drm_framebuffer *fb =
2292                         crtc->base.primary->state->fb;
2293                 int cpp;
2294
2295                 if (IS_GEN2(dev_priv))
2296                         cpp = 4;
2297                 else
2298                         cpp = fb->format->cpp[0];
2299
2300                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2301                                                wm_info, fifo_size, cpp,
2302                                                pessimal_latency_ns);
2303                 if (enabled == NULL)
2304                         enabled = crtc;
2305                 else
2306                         enabled = NULL;
2307         } else {
2308                 planeb_wm = fifo_size - wm_info->guard_size;
2309                 if (planeb_wm > (long)wm_info->max_wm)
2310                         planeb_wm = wm_info->max_wm;
2311         }
2312
2313         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2314
2315         if (IS_I915GM(dev_priv) && enabled) {
2316                 struct drm_i915_gem_object *obj;
2317
2318                 obj = intel_fb_obj(enabled->base.primary->state->fb);
2319
2320                 /* self-refresh seems busted with untiled */
2321                 if (!i915_gem_object_is_tiled(obj))
2322                         enabled = NULL;
2323         }
2324
2325         /*
2326          * Overlay gets an aggressive default since video jitter is bad.
2327          */
2328         cwm = 2;
2329
2330         /* Play safe and disable self-refresh before adjusting watermarks. */
2331         intel_set_memory_cxsr(dev_priv, false);
2332
2333         /* Calc sr entries for one plane configs */
2334         if (HAS_FW_BLC(dev_priv) && enabled) {
2335                 /* self-refresh has much higher latency */
2336                 static const int sr_latency_ns = 6000;
2337                 const struct drm_display_mode *adjusted_mode =
2338                         &enabled->config->base.adjusted_mode;
2339                 const struct drm_framebuffer *fb =
2340                         enabled->base.primary->state->fb;
2341                 int clock = adjusted_mode->crtc_clock;
2342                 int htotal = adjusted_mode->crtc_htotal;
2343                 int hdisplay = enabled->config->pipe_src_w;
2344                 int cpp;
2345                 int entries;
2346
2347                 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2348                         cpp = 4;
2349                 else
2350                         cpp = fb->format->cpp[0];
2351
2352                 entries = intel_wm_method2(clock, htotal, hdisplay, cpp,
2353                                            sr_latency_ns / 100);
2354                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
2355                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
2356                 srwm = wm_info->fifo_size - entries;
2357                 if (srwm < 0)
2358                         srwm = 1;
2359
2360                 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
2361                         I915_WRITE(FW_BLC_SELF,
2362                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
2363                 else
2364                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
2365         }
2366
2367         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2368                       planea_wm, planeb_wm, cwm, srwm);
2369
2370         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2371         fwater_hi = (cwm & 0x1f);
2372
2373         /* Set request length to 8 cachelines per fetch */
2374         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2375         fwater_hi = fwater_hi | (1 << 8);
2376
2377         I915_WRITE(FW_BLC, fwater_lo);
2378         I915_WRITE(FW_BLC2, fwater_hi);
2379
2380         if (enabled)
2381                 intel_set_memory_cxsr(dev_priv, true);
2382 }
2383
2384 static void i845_update_wm(struct intel_crtc *unused_crtc)
2385 {
2386         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2387         struct intel_crtc *crtc;
2388         const struct drm_display_mode *adjusted_mode;
2389         uint32_t fwater_lo;
2390         int planea_wm;
2391
2392         crtc = single_enabled_crtc(dev_priv);
2393         if (crtc == NULL)
2394                 return;
2395
2396         adjusted_mode = &crtc->config->base.adjusted_mode;
2397         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2398                                        &i845_wm_info,
2399                                        dev_priv->display.get_fifo_size(dev_priv, 0),
2400                                        4, pessimal_latency_ns);
2401         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2402         fwater_lo |= (3<<8) | planea_wm;
2403
2404         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2405
2406         I915_WRITE(FW_BLC, fwater_lo);
2407 }
2408
2409 /* latency must be in 0.1us units. */
2410 static unsigned int ilk_wm_method1(unsigned int pixel_rate,
2411                                    unsigned int cpp,
2412                                    unsigned int latency)
2413 {
2414         unsigned int ret;
2415
2416         ret = intel_wm_method1(pixel_rate, cpp, latency);
2417         ret = DIV_ROUND_UP(ret, 64) + 2;
2418
2419         return ret;
2420 }
2421
2422 /* latency must be in 0.1us units. */
2423 static unsigned int ilk_wm_method2(unsigned int pixel_rate,
2424                                    unsigned int htotal,
2425                                    unsigned int width,
2426                                    unsigned int cpp,
2427                                    unsigned int latency)
2428 {
2429         unsigned int ret;
2430
2431         ret = intel_wm_method2(pixel_rate, htotal,
2432                                width, cpp, latency);
2433         ret = DIV_ROUND_UP(ret, 64) + 2;
2434
2435         return ret;
2436 }
2437
2438 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2439                            uint8_t cpp)
2440 {
2441         /*
2442          * Neither of these should be possible since this function shouldn't be
2443          * called if the CRTC is off or the plane is invisible.  But let's be
2444          * extra paranoid to avoid a potential divide-by-zero if we screw up
2445          * elsewhere in the driver.
2446          */
2447         if (WARN_ON(!cpp))
2448                 return 0;
2449         if (WARN_ON(!horiz_pixels))
2450                 return 0;
2451
2452         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
2453 }
2454
2455 struct ilk_wm_maximums {
2456         uint16_t pri;
2457         uint16_t spr;
2458         uint16_t cur;
2459         uint16_t fbc;
2460 };
2461
2462 /*
2463  * For both WM_PIPE and WM_LP.
2464  * mem_value must be in 0.1us units.
2465  */
2466 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
2467                                    const struct intel_plane_state *pstate,
2468                                    uint32_t mem_value,
2469                                    bool is_lp)
2470 {
2471         uint32_t method1, method2;
2472         int cpp;
2473
2474         if (!intel_wm_plane_visible(cstate, pstate))
2475                 return 0;
2476
2477         cpp = pstate->base.fb->format->cpp[0];
2478
2479         method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
2480
2481         if (!is_lp)
2482                 return method1;
2483
2484         method2 = ilk_wm_method2(cstate->pixel_rate,
2485                                  cstate->base.adjusted_mode.crtc_htotal,
2486                                  drm_rect_width(&pstate->base.dst),
2487                                  cpp, mem_value);
2488
2489         return min(method1, method2);
2490 }
2491
2492 /*
2493  * For both WM_PIPE and WM_LP.
2494  * mem_value must be in 0.1us units.
2495  */
2496 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
2497                                    const struct intel_plane_state *pstate,
2498                                    uint32_t mem_value)
2499 {
2500         uint32_t method1, method2;
2501         int cpp;
2502
2503         if (!intel_wm_plane_visible(cstate, pstate))
2504                 return 0;
2505
2506         cpp = pstate->base.fb->format->cpp[0];
2507
2508         method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
2509         method2 = ilk_wm_method2(cstate->pixel_rate,
2510                                  cstate->base.adjusted_mode.crtc_htotal,
2511                                  drm_rect_width(&pstate->base.dst),
2512                                  cpp, mem_value);
2513         return min(method1, method2);
2514 }
2515
2516 /*
2517  * For both WM_PIPE and WM_LP.
2518  * mem_value must be in 0.1us units.
2519  */
2520 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
2521                                    const struct intel_plane_state *pstate,
2522                                    uint32_t mem_value)
2523 {
2524         int cpp;
2525
2526         if (!intel_wm_plane_visible(cstate, pstate))
2527                 return 0;
2528
2529         cpp = pstate->base.fb->format->cpp[0];
2530
2531         return ilk_wm_method2(cstate->pixel_rate,
2532                               cstate->base.adjusted_mode.crtc_htotal,
2533                               pstate->base.crtc_w, cpp, mem_value);
2534 }
2535
2536 /* Only for WM_LP. */
2537 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
2538                                    const struct intel_plane_state *pstate,
2539                                    uint32_t pri_val)
2540 {
2541         int cpp;
2542
2543         if (!intel_wm_plane_visible(cstate, pstate))
2544                 return 0;
2545
2546         cpp = pstate->base.fb->format->cpp[0];
2547
2548         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
2549 }
2550
2551 static unsigned int
2552 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
2553 {
2554         if (INTEL_GEN(dev_priv) >= 8)
2555                 return 3072;
2556         else if (INTEL_GEN(dev_priv) >= 7)
2557                 return 768;
2558         else
2559                 return 512;
2560 }
2561
2562 static unsigned int
2563 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
2564                      int level, bool is_sprite)
2565 {
2566         if (INTEL_GEN(dev_priv) >= 8)
2567                 /* BDW primary/sprite plane watermarks */
2568                 return level == 0 ? 255 : 2047;
2569         else if (INTEL_GEN(dev_priv) >= 7)
2570                 /* IVB/HSW primary/sprite plane watermarks */
2571                 return level == 0 ? 127 : 1023;
2572         else if (!is_sprite)
2573                 /* ILK/SNB primary plane watermarks */
2574                 return level == 0 ? 127 : 511;
2575         else
2576                 /* ILK/SNB sprite plane watermarks */
2577                 return level == 0 ? 63 : 255;
2578 }
2579
2580 static unsigned int
2581 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
2582 {
2583         if (INTEL_GEN(dev_priv) >= 7)
2584                 return level == 0 ? 63 : 255;
2585         else
2586                 return level == 0 ? 31 : 63;
2587 }
2588
2589 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
2590 {
2591         if (INTEL_GEN(dev_priv) >= 8)
2592                 return 31;
2593         else
2594                 return 15;
2595 }
2596
2597 /* Calculate the maximum primary/sprite plane watermark */
2598 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2599                                      int level,
2600                                      const struct intel_wm_config *config,
2601                                      enum intel_ddb_partitioning ddb_partitioning,
2602                                      bool is_sprite)
2603 {
2604         struct drm_i915_private *dev_priv = to_i915(dev);
2605         unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
2606
2607         /* if sprites aren't enabled, sprites get nothing */
2608         if (is_sprite && !config->sprites_enabled)
2609                 return 0;
2610
2611         /* HSW allows LP1+ watermarks even with multiple pipes */
2612         if (level == 0 || config->num_pipes_active > 1) {
2613                 fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
2614
2615                 /*
2616                  * For some reason the non self refresh
2617                  * FIFO size is only half of the self
2618                  * refresh FIFO size on ILK/SNB.
2619                  */
2620                 if (INTEL_GEN(dev_priv) <= 6)
2621                         fifo_size /= 2;
2622         }
2623
2624         if (config->sprites_enabled) {
2625                 /* level 0 is always calculated with 1:1 split */
2626                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2627                         if (is_sprite)
2628                                 fifo_size *= 5;
2629                         fifo_size /= 6;
2630                 } else {
2631                         fifo_size /= 2;
2632                 }
2633         }
2634
2635         /* clamp to max that the registers can hold */
2636         return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
2637 }
2638
2639 /* Calculate the maximum cursor plane watermark */
2640 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2641                                       int level,
2642                                       const struct intel_wm_config *config)
2643 {
2644         /* HSW LP1+ watermarks w/ multiple pipes */
2645         if (level > 0 && config->num_pipes_active > 1)
2646                 return 64;
2647
2648         /* otherwise just report max that registers can hold */
2649         return ilk_cursor_wm_reg_max(to_i915(dev), level);
2650 }
2651
2652 static void ilk_compute_wm_maximums(const struct drm_device *dev,
2653                                     int level,
2654                                     const struct intel_wm_config *config,
2655                                     enum intel_ddb_partitioning ddb_partitioning,
2656                                     struct ilk_wm_maximums *max)
2657 {
2658         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2659         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2660         max->cur = ilk_cursor_wm_max(dev, level, config);
2661         max->fbc = ilk_fbc_wm_reg_max(to_i915(dev));
2662 }
2663
2664 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
2665                                         int level,
2666                                         struct ilk_wm_maximums *max)
2667 {
2668         max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
2669         max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
2670         max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
2671         max->fbc = ilk_fbc_wm_reg_max(dev_priv);
2672 }
2673
2674 static bool ilk_validate_wm_level(int level,
2675                                   const struct ilk_wm_maximums *max,
2676                                   struct intel_wm_level *result)
2677 {
2678         bool ret;
2679
2680         /* already determined to be invalid? */
2681         if (!result->enable)
2682                 return false;
2683
2684         result->enable = result->pri_val <= max->pri &&
2685                          result->spr_val <= max->spr &&
2686                          result->cur_val <= max->cur;
2687
2688         ret = result->enable;
2689
2690         /*
2691          * HACK until we can pre-compute everything,
2692          * and thus fail gracefully if LP0 watermarks
2693          * are exceeded...
2694          */
2695         if (level == 0 && !result->enable) {
2696                 if (result->pri_val > max->pri)
2697                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2698                                       level, result->pri_val, max->pri);
2699                 if (result->spr_val > max->spr)
2700                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2701                                       level, result->spr_val, max->spr);
2702                 if (result->cur_val > max->cur)
2703                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2704                                       level, result->cur_val, max->cur);
2705
2706                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2707                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2708                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2709                 result->enable = true;
2710         }
2711
2712         return ret;
2713 }
2714
2715 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2716                                  const struct intel_crtc *intel_crtc,
2717                                  int level,
2718                                  struct intel_crtc_state *cstate,
2719                                  const struct intel_plane_state *pristate,
2720                                  const struct intel_plane_state *sprstate,
2721                                  const struct intel_plane_state *curstate,
2722                                  struct intel_wm_level *result)
2723 {
2724         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2725         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2726         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2727
2728         /* WM1+ latency values stored in 0.5us units */
2729         if (level > 0) {
2730                 pri_latency *= 5;
2731                 spr_latency *= 5;
2732                 cur_latency *= 5;
2733         }
2734
2735         if (pristate) {
2736                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2737                                                      pri_latency, level);
2738                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2739         }
2740
2741         if (sprstate)
2742                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2743
2744         if (curstate)
2745                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2746
2747         result->enable = true;
2748 }
2749
2750 static uint32_t
2751 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2752 {
2753         const struct intel_atomic_state *intel_state =
2754                 to_intel_atomic_state(cstate->base.state);
2755         const struct drm_display_mode *adjusted_mode =
2756                 &cstate->base.adjusted_mode;
2757         u32 linetime, ips_linetime;
2758
2759         if (!cstate->base.active)
2760                 return 0;
2761         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2762                 return 0;
2763         if (WARN_ON(intel_state->cdclk.logical.cdclk == 0))
2764                 return 0;
2765
2766         /* The WM are computed with base on how long it takes to fill a single
2767          * row at the given clock rate, multiplied by 8.
2768          * */
2769         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2770                                      adjusted_mode->crtc_clock);
2771         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2772                                          intel_state->cdclk.logical.cdclk);
2773
2774         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2775                PIPE_WM_LINETIME_TIME(linetime);
2776 }
2777
2778 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2779                                   uint16_t wm[8])
2780 {
2781         if (INTEL_GEN(dev_priv) >= 9) {
2782                 uint32_t val;
2783                 int ret, i;
2784                 int level, max_level = ilk_wm_max_level(dev_priv);
2785
2786                 /* read the first set of memory latencies[0:3] */
2787                 val = 0; /* data0 to be programmed to 0 for first set */
2788                 mutex_lock(&dev_priv->rps.hw_lock);
2789                 ret = sandybridge_pcode_read(dev_priv,
2790                                              GEN9_PCODE_READ_MEM_LATENCY,
2791                                              &val);
2792                 mutex_unlock(&dev_priv->rps.hw_lock);
2793
2794                 if (ret) {
2795                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2796                         return;
2797                 }
2798
2799                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2800                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2801                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2802                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2803                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2804                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2805                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2806
2807                 /* read the second set of memory latencies[4:7] */
2808                 val = 1; /* data0 to be programmed to 1 for second set */
2809                 mutex_lock(&dev_priv->rps.hw_lock);
2810                 ret = sandybridge_pcode_read(dev_priv,
2811                                              GEN9_PCODE_READ_MEM_LATENCY,
2812                                              &val);
2813                 mutex_unlock(&dev_priv->rps.hw_lock);
2814                 if (ret) {
2815                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2816                         return;
2817                 }
2818
2819                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2820                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2821                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2822                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2823                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2824                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2825                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2826
2827                 /*
2828                  * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2829                  * need to be disabled. We make sure to sanitize the values out
2830                  * of the punit to satisfy this requirement.
2831                  */
2832                 for (level = 1; level <= max_level; level++) {
2833                         if (wm[level] == 0) {
2834                                 for (i = level + 1; i <= max_level; i++)
2835                                         wm[i] = 0;
2836                                 break;
2837                         }
2838                 }
2839
2840                 /*
2841                  * WaWmMemoryReadLatency:skl+,glk
2842                  *
2843                  * punit doesn't take into account the read latency so we need
2844                  * to add 2us to the various latency levels we retrieve from the
2845                  * punit when level 0 response data us 0us.
2846                  */
2847                 if (wm[0] == 0) {
2848                         wm[0] += 2;
2849                         for (level = 1; level <= max_level; level++) {
2850                                 if (wm[level] == 0)
2851                                         break;
2852                                 wm[level] += 2;
2853                         }
2854                 }
2855
2856         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2857                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2858
2859                 wm[0] = (sskpd >> 56) & 0xFF;
2860                 if (wm[0] == 0)
2861                         wm[0] = sskpd & 0xF;
2862                 wm[1] = (sskpd >> 4) & 0xFF;
2863                 wm[2] = (sskpd >> 12) & 0xFF;
2864                 wm[3] = (sskpd >> 20) & 0x1FF;
2865                 wm[4] = (sskpd >> 32) & 0x1FF;
2866         } else if (INTEL_GEN(dev_priv) >= 6) {
2867                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2868
2869                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2870                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2871                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2872                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2873         } else if (INTEL_GEN(dev_priv) >= 5) {
2874                 uint32_t mltr = I915_READ(MLTR_ILK);
2875
2876                 /* ILK primary LP0 latency is 700 ns */
2877                 wm[0] = 7;
2878                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2879                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2880         } else {
2881                 MISSING_CASE(INTEL_DEVID(dev_priv));
2882         }
2883 }
2884
2885 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2886                                        uint16_t wm[5])
2887 {
2888         /* ILK sprite LP0 latency is 1300 ns */
2889         if (IS_GEN5(dev_priv))
2890                 wm[0] = 13;
2891 }
2892
2893 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2894                                        uint16_t wm[5])
2895 {
2896         /* ILK cursor LP0 latency is 1300 ns */
2897         if (IS_GEN5(dev_priv))
2898                 wm[0] = 13;
2899
2900         /* WaDoubleCursorLP3Latency:ivb */
2901         if (IS_IVYBRIDGE(dev_priv))
2902                 wm[3] *= 2;
2903 }
2904
2905 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2906 {
2907         /* how many WM levels are we expecting */
2908         if (INTEL_GEN(dev_priv) >= 9)
2909                 return 7;
2910         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2911                 return 4;
2912         else if (INTEL_GEN(dev_priv) >= 6)
2913                 return 3;
2914         else
2915                 return 2;
2916 }
2917
2918 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2919                                    const char *name,
2920                                    const uint16_t wm[8])
2921 {
2922         int level, max_level = ilk_wm_max_level(dev_priv);
2923
2924         for (level = 0; level <= max_level; level++) {
2925                 unsigned int latency = wm[level];
2926
2927                 if (latency == 0) {
2928                         DRM_ERROR("%s WM%d latency not provided\n",
2929                                   name, level);
2930                         continue;
2931                 }
2932
2933                 /*
2934                  * - latencies are in us on gen9.
2935                  * - before then, WM1+ latency values are in 0.5us units
2936                  */
2937                 if (INTEL_GEN(dev_priv) >= 9)
2938                         latency *= 10;
2939                 else if (level > 0)
2940                         latency *= 5;
2941
2942                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2943                               name, level, wm[level],
2944                               latency / 10, latency % 10);
2945         }
2946 }
2947
2948 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2949                                     uint16_t wm[5], uint16_t min)
2950 {
2951         int level, max_level = ilk_wm_max_level(dev_priv);
2952
2953         if (wm[0] >= min)
2954                 return false;
2955
2956         wm[0] = max(wm[0], min);
2957         for (level = 1; level <= max_level; level++)
2958                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2959
2960         return true;
2961 }
2962
2963 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
2964 {
2965         bool changed;
2966
2967         /*
2968          * The BIOS provided WM memory latency values are often
2969          * inadequate for high resolution displays. Adjust them.
2970          */
2971         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2972                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2973                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2974
2975         if (!changed)
2976                 return;
2977
2978         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2979         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2980         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2981         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2982 }
2983
2984 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
2985 {
2986         intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
2987
2988         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2989                sizeof(dev_priv->wm.pri_latency));
2990         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2991                sizeof(dev_priv->wm.pri_latency));
2992
2993         intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
2994         intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
2995
2996         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2997         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2998         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2999
3000         if (IS_GEN6(dev_priv))
3001                 snb_wm_latency_quirk(dev_priv);
3002 }
3003
3004 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
3005 {
3006         intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
3007         intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
3008 }
3009
3010 static bool ilk_validate_pipe_wm(struct drm_device *dev,
3011                                  struct intel_pipe_wm *pipe_wm)
3012 {
3013         /* LP0 watermark maximums depend on this pipe alone */
3014         const struct intel_wm_config config = {
3015                 .num_pipes_active = 1,
3016                 .sprites_enabled = pipe_wm->sprites_enabled,
3017                 .sprites_scaled = pipe_wm->sprites_scaled,
3018         };
3019         struct ilk_wm_maximums max;
3020
3021         /* LP0 watermarks always use 1/2 DDB partitioning */
3022         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
3023
3024         /* At least LP0 must be valid */
3025         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
3026                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
3027                 return false;
3028         }
3029
3030         return true;
3031 }
3032
3033 /* Compute new watermarks for the pipe */
3034 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
3035 {
3036         struct drm_atomic_state *state = cstate->base.state;
3037         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3038         struct intel_pipe_wm *pipe_wm;
3039         struct drm_device *dev = state->dev;
3040         const struct drm_i915_private *dev_priv = to_i915(dev);
3041         struct drm_plane *plane;
3042         const struct drm_plane_state *plane_state;
3043         const struct intel_plane_state *pristate = NULL;
3044         const struct intel_plane_state *sprstate = NULL;
3045         const struct intel_plane_state *curstate = NULL;
3046         int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
3047         struct ilk_wm_maximums max;
3048
3049         pipe_wm = &cstate->wm.ilk.optimal;
3050
3051         drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, &cstate->base) {
3052                 const struct intel_plane_state *ps = to_intel_plane_state(plane_state);
3053
3054                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
3055                         pristate = ps;
3056                 else if (plane->type == DRM_PLANE_TYPE_OVERLAY)
3057                         sprstate = ps;
3058                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
3059                         curstate = ps;
3060         }
3061
3062         pipe_wm->pipe_enabled = cstate->base.active;
3063         if (sprstate) {
3064                 pipe_wm->sprites_enabled = sprstate->base.visible;
3065                 pipe_wm->sprites_scaled = sprstate->base.visible &&
3066                         (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
3067                          drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
3068         }
3069
3070         usable_level = max_level;
3071
3072         /* ILK/SNB: LP2+ watermarks only w/o sprites */
3073         if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
3074                 usable_level = 1;
3075
3076         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
3077         if (pipe_wm->sprites_scaled)
3078                 usable_level = 0;
3079
3080         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
3081         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
3082                              pristate, sprstate, curstate, &pipe_wm->wm[0]);
3083
3084         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3085                 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
3086
3087         if (!ilk_validate_pipe_wm(dev, pipe_wm))
3088                 return -EINVAL;
3089
3090         ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
3091
3092         for (level = 1; level <= usable_level; level++) {
3093                 struct intel_wm_level *wm = &pipe_wm->wm[level];
3094
3095                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
3096                                      pristate, sprstate, curstate, wm);
3097
3098                 /*
3099                  * Disable any watermark level that exceeds the
3100                  * register maximums since such watermarks are
3101                  * always invalid.
3102                  */
3103                 if (!ilk_validate_wm_level(level, &max, wm)) {
3104                         memset(wm, 0, sizeof(*wm));
3105                         break;
3106                 }
3107         }
3108
3109         return 0;
3110 }
3111
3112 /*
3113  * Build a set of 'intermediate' watermark values that satisfy both the old
3114  * state and the new state.  These can be programmed to the hardware
3115  * immediately.
3116  */
3117 static int ilk_compute_intermediate_wm(struct drm_device *dev,
3118                                        struct intel_crtc *intel_crtc,
3119                                        struct intel_crtc_state *newstate)
3120 {
3121         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
3122         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
3123         int level, max_level = ilk_wm_max_level(to_i915(dev));
3124
3125         /*
3126          * Start with the final, target watermarks, then combine with the
3127          * currently active watermarks to get values that are safe both before
3128          * and after the vblank.
3129          */
3130         *a = newstate->wm.ilk.optimal;
3131         a->pipe_enabled |= b->pipe_enabled;
3132         a->sprites_enabled |= b->sprites_enabled;
3133         a->sprites_scaled |= b->sprites_scaled;
3134
3135         for (level = 0; level <= max_level; level++) {
3136                 struct intel_wm_level *a_wm = &a->wm[level];
3137                 const struct intel_wm_level *b_wm = &b->wm[level];
3138
3139                 a_wm->enable &= b_wm->enable;
3140                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
3141                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
3142                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
3143                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
3144         }
3145
3146         /*
3147          * We need to make sure that these merged watermark values are
3148          * actually a valid configuration themselves.  If they're not,
3149          * there's no safe way to transition from the old state to
3150          * the new state, so we need to fail the atomic transaction.
3151          */
3152         if (!ilk_validate_pipe_wm(dev, a))
3153                 return -EINVAL;
3154
3155         /*
3156          * If our intermediate WM are identical to the final WM, then we can
3157          * omit the post-vblank programming; only update if it's different.
3158          */
3159         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) != 0)
3160                 newstate->wm.need_postvbl_update = true;
3161
3162         return 0;
3163 }
3164
3165 /*
3166  * Merge the watermarks from all active pipes for a specific level.
3167  */
3168 static void ilk_merge_wm_level(struct drm_device *dev,
3169                                int level,
3170                                struct intel_wm_level *ret_wm)
3171 {
3172         const struct intel_crtc *intel_crtc;
3173
3174         ret_wm->enable = true;
3175
3176         for_each_intel_crtc(dev, intel_crtc) {
3177                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
3178                 const struct intel_wm_level *wm = &active->wm[level];
3179
3180                 if (!active->pipe_enabled)
3181                         continue;
3182
3183                 /*
3184                  * The watermark values may have been used in the past,
3185                  * so we must maintain them in the registers for some
3186                  * time even if the level is now disabled.
3187                  */
3188                 if (!wm->enable)
3189                         ret_wm->enable = false;
3190
3191                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
3192                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
3193                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
3194                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
3195         }
3196 }
3197
3198 /*
3199  * Merge all low power watermarks for all active pipes.
3200  */
3201 static void ilk_wm_merge(struct drm_device *dev,
3202                          const struct intel_wm_config *config,
3203                          const struct ilk_wm_maximums *max,
3204                          struct intel_pipe_wm *merged)
3205 {
3206         struct drm_i915_private *dev_priv = to_i915(dev);
3207         int level, max_level = ilk_wm_max_level(dev_priv);
3208         int last_enabled_level = max_level;
3209
3210         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
3211         if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
3212             config->num_pipes_active > 1)
3213                 last_enabled_level = 0;
3214
3215         /* ILK: FBC WM must be disabled always */
3216         merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
3217
3218         /* merge each WM1+ level */
3219         for (level = 1; level <= max_level; level++) {
3220                 struct intel_wm_level *wm = &merged->wm[level];
3221
3222                 ilk_merge_wm_level(dev, level, wm);
3223
3224                 if (level > last_enabled_level)
3225                         wm->enable = false;
3226                 else if (!ilk_validate_wm_level(level, max, wm))
3227                         /* make sure all following levels get disabled */
3228                         last_enabled_level = level - 1;
3229
3230                 /*
3231                  * The spec says it is preferred to disable
3232                  * FBC WMs instead of disabling a WM level.
3233                  */
3234                 if (wm->fbc_val > max->fbc) {
3235                         if (wm->enable)
3236                                 merged->fbc_wm_enabled = false;
3237                         wm->fbc_val = 0;
3238                 }
3239         }
3240
3241         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
3242         /*
3243          * FIXME this is racy. FBC might get enabled later.
3244          * What we should check here is whether FBC can be
3245          * enabled sometime later.
3246          */
3247         if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
3248             intel_fbc_is_active(dev_priv)) {
3249                 for (level = 2; level <= max_level; level++) {
3250                         struct intel_wm_level *wm = &merged->wm[level];
3251
3252                         wm->enable = false;
3253                 }
3254         }
3255 }
3256
3257 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
3258 {
3259         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
3260         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
3261 }
3262
3263 /* The value we need to program into the WM_LPx latency field */
3264 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
3265 {
3266         struct drm_i915_private *dev_priv = to_i915(dev);
3267
3268         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3269                 return 2 * level;
3270         else
3271                 return dev_priv->wm.pri_latency[level];
3272 }
3273
3274 static void ilk_compute_wm_results(struct drm_device *dev,
3275                                    const struct intel_pipe_wm *merged,
3276                                    enum intel_ddb_partitioning partitioning,
3277                                    struct ilk_wm_values *results)
3278 {
3279         struct drm_i915_private *dev_priv = to_i915(dev);
3280         struct intel_crtc *intel_crtc;
3281         int level, wm_lp;
3282
3283         results->enable_fbc_wm = merged->fbc_wm_enabled;
3284         results->partitioning = partitioning;
3285
3286         /* LP1+ register values */
3287         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3288                 const struct intel_wm_level *r;
3289
3290                 level = ilk_wm_lp_to_level(wm_lp, merged);
3291
3292                 r = &merged->wm[level];
3293
3294                 /*
3295                  * Maintain the watermark values even if the level is
3296                  * disabled. Doing otherwise could cause underruns.
3297                  */
3298                 results->wm_lp[wm_lp - 1] =
3299                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
3300                         (r->pri_val << WM1_LP_SR_SHIFT) |
3301                         r->cur_val;
3302
3303                 if (r->enable)
3304                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
3305
3306                 if (INTEL_GEN(dev_priv) >= 8)
3307                         results->wm_lp[wm_lp - 1] |=
3308                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
3309                 else
3310                         results->wm_lp[wm_lp - 1] |=
3311                                 r->fbc_val << WM1_LP_FBC_SHIFT;
3312
3313                 /*
3314                  * Always set WM1S_LP_EN when spr_val != 0, even if the
3315                  * level is disabled. Doing otherwise could cause underruns.
3316                  */
3317                 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
3318                         WARN_ON(wm_lp != 1);
3319                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
3320                 } else
3321                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
3322         }
3323
3324         /* LP0 register values */
3325         for_each_intel_crtc(dev, intel_crtc) {
3326                 enum pipe pipe = intel_crtc->pipe;
3327                 const struct intel_wm_level *r =
3328                         &intel_crtc->wm.active.ilk.wm[0];
3329
3330                 if (WARN_ON(!r->enable))
3331                         continue;
3332
3333                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
3334
3335                 results->wm_pipe[pipe] =
3336                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
3337                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
3338                         r->cur_val;
3339         }
3340 }
3341
3342 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
3343  * case both are at the same level. Prefer r1 in case they're the same. */
3344 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
3345                                                   struct intel_pipe_wm *r1,
3346                                                   struct intel_pipe_wm *r2)
3347 {
3348         int level, max_level = ilk_wm_max_level(to_i915(dev));
3349         int level1 = 0, level2 = 0;
3350
3351         for (level = 1; level <= max_level; level++) {
3352                 if (r1->wm[level].enable)
3353                         level1 = level;
3354                 if (r2->wm[level].enable)
3355                         level2 = level;
3356         }
3357
3358         if (level1 == level2) {
3359                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
3360                         return r2;
3361                 else
3362                         return r1;
3363         } else if (level1 > level2) {
3364                 return r1;
3365         } else {
3366                 return r2;
3367         }
3368 }
3369
3370 /* dirty bits used to track which watermarks need changes */
3371 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
3372 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
3373 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
3374 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
3375 #define WM_DIRTY_FBC (1 << 24)
3376 #define WM_DIRTY_DDB (1 << 25)
3377
3378 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
3379                                          const struct ilk_wm_values *old,
3380                                          const struct ilk_wm_values *new)
3381 {
3382         unsigned int dirty = 0;
3383         enum pipe pipe;
3384         int wm_lp;
3385
3386         for_each_pipe(dev_priv, pipe) {
3387                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
3388                         dirty |= WM_DIRTY_LINETIME(pipe);
3389                         /* Must disable LP1+ watermarks too */
3390                         dirty |= WM_DIRTY_LP_ALL;
3391                 }
3392
3393                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
3394                         dirty |= WM_DIRTY_PIPE(pipe);
3395                         /* Must disable LP1+ watermarks too */
3396                         dirty |= WM_DIRTY_LP_ALL;
3397                 }
3398         }
3399
3400         if (old->enable_fbc_wm != new->enable_fbc_wm) {
3401                 dirty |= WM_DIRTY_FBC;
3402                 /* Must disable LP1+ watermarks too */
3403                 dirty |= WM_DIRTY_LP_ALL;
3404         }
3405
3406         if (old->partitioning != new->partitioning) {
3407                 dirty |= WM_DIRTY_DDB;
3408                 /* Must disable LP1+ watermarks too */
3409                 dirty |= WM_DIRTY_LP_ALL;
3410         }
3411
3412         /* LP1+ watermarks already deemed dirty, no need to continue */
3413         if (dirty & WM_DIRTY_LP_ALL)
3414                 return dirty;
3415
3416         /* Find the lowest numbered LP1+ watermark in need of an update... */
3417         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3418                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
3419                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
3420                         break;
3421         }
3422
3423         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
3424         for (; wm_lp <= 3; wm_lp++)
3425                 dirty |= WM_DIRTY_LP(wm_lp);
3426
3427         return dirty;
3428 }
3429
3430 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
3431                                unsigned int dirty)
3432 {
3433         struct ilk_wm_values *previous = &dev_priv->wm.hw;
3434         bool changed = false;
3435
3436         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
3437                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
3438                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
3439                 changed = true;
3440         }
3441         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
3442                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
3443                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
3444                 changed = true;
3445         }
3446         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
3447                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
3448                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
3449                 changed = true;
3450         }
3451
3452         /*
3453          * Don't touch WM1S_LP_EN here.
3454          * Doing so could cause underruns.
3455          */
3456
3457         return changed;
3458 }
3459
3460 /*
3461  * The spec says we shouldn't write when we don't need, because every write
3462  * causes WMs to be re-evaluated, expending some power.
3463  */
3464 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
3465                                 struct ilk_wm_values *results)
3466 {
3467         struct ilk_wm_values *previous = &dev_priv->wm.hw;
3468         unsigned int dirty;
3469         uint32_t val;
3470
3471         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
3472         if (!dirty)
3473                 return;
3474
3475         _ilk_disable_lp_wm(dev_priv, dirty);
3476
3477         if (dirty & WM_DIRTY_PIPE(PIPE_A))
3478                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
3479         if (dirty & WM_DIRTY_PIPE(PIPE_B))
3480                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
3481         if (dirty & WM_DIRTY_PIPE(PIPE_C))
3482                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
3483
3484         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
3485                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
3486         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
3487                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
3488         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
3489                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
3490
3491         if (dirty & WM_DIRTY_DDB) {
3492                 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3493                         val = I915_READ(WM_MISC);
3494                         if (results->partitioning == INTEL_DDB_PART_1_2)
3495                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
3496                         else
3497                                 val |= WM_MISC_DATA_PARTITION_5_6;
3498                         I915_WRITE(WM_MISC, val);
3499                 } else {
3500                         val = I915_READ(DISP_ARB_CTL2);
3501                         if (results->partitioning == INTEL_DDB_PART_1_2)
3502                                 val &= ~DISP_DATA_PARTITION_5_6;
3503                         else
3504                                 val |= DISP_DATA_PARTITION_5_6;
3505                         I915_WRITE(DISP_ARB_CTL2, val);
3506                 }
3507         }
3508
3509         if (dirty & WM_DIRTY_FBC) {
3510                 val = I915_READ(DISP_ARB_CTL);
3511                 if (results->enable_fbc_wm)
3512                         val &= ~DISP_FBC_WM_DIS;
3513                 else
3514                         val |= DISP_FBC_WM_DIS;
3515                 I915_WRITE(DISP_ARB_CTL, val);
3516         }
3517
3518         if (dirty & WM_DIRTY_LP(1) &&
3519             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
3520                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
3521
3522         if (INTEL_GEN(dev_priv) >= 7) {
3523                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
3524                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
3525                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
3526                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
3527         }
3528
3529         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
3530                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
3531         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
3532                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
3533         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
3534                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
3535
3536         dev_priv->wm.hw = *results;
3537 }
3538
3539 bool ilk_disable_lp_wm(struct drm_device *dev)
3540 {
3541         struct drm_i915_private *dev_priv = to_i915(dev);
3542
3543         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
3544 }
3545
3546 /*
3547  * FIXME: We still don't have the proper code detect if we need to apply the WA,
3548  * so assume we'll always need it in order to avoid underruns.
3549  */
3550 static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
3551 {
3552         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3553
3554         if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
3555                 return true;
3556
3557         return false;
3558 }
3559
3560 static bool
3561 intel_has_sagv(struct drm_i915_private *dev_priv)
3562 {
3563         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
3564             IS_CANNONLAKE(dev_priv))
3565                 return true;
3566
3567         if (IS_SKYLAKE(dev_priv) &&
3568             dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
3569                 return true;
3570
3571         return false;
3572 }
3573
3574 /*
3575  * SAGV dynamically adjusts the system agent voltage and clock frequencies
3576  * depending on power and performance requirements. The display engine access
3577  * to system memory is blocked during the adjustment time. Because of the
3578  * blocking time, having this enabled can cause full system hangs and/or pipe
3579  * underruns if we don't meet all of the following requirements:
3580  *
3581  *  - <= 1 pipe enabled
3582  *  - All planes can enable watermarks for latencies >= SAGV engine block time
3583  *  - We're not using an interlaced display configuration
3584  */
3585 int
3586 intel_enable_sagv(struct drm_i915_private *dev_priv)
3587 {
3588         int ret;
3589
3590         if (!intel_has_sagv(dev_priv))
3591                 return 0;
3592
3593         if (dev_priv->sagv_status == I915_SAGV_ENABLED)
3594                 return 0;
3595
3596         DRM_DEBUG_KMS("Enabling the SAGV\n");
3597         mutex_lock(&dev_priv->rps.hw_lock);
3598
3599         ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3600                                       GEN9_SAGV_ENABLE);
3601
3602         /* We don't need to wait for the SAGV when enabling */
3603         mutex_unlock(&dev_priv->rps.hw_lock);
3604
3605         /*
3606          * Some skl systems, pre-release machines in particular,
3607          * don't actually have an SAGV.
3608          */
3609         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3610                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3611                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3612                 return 0;
3613         } else if (ret < 0) {
3614                 DRM_ERROR("Failed to enable the SAGV\n");
3615                 return ret;
3616         }
3617
3618         dev_priv->sagv_status = I915_SAGV_ENABLED;
3619         return 0;
3620 }
3621
3622 int
3623 intel_disable_sagv(struct drm_i915_private *dev_priv)
3624 {
3625         int ret;
3626
3627         if (!intel_has_sagv(dev_priv))
3628                 return 0;
3629
3630         if (dev_priv->sagv_status == I915_SAGV_DISABLED)
3631                 return 0;
3632
3633         DRM_DEBUG_KMS("Disabling the SAGV\n");
3634         mutex_lock(&dev_priv->rps.hw_lock);
3635
3636         /* bspec says to keep retrying for at least 1 ms */
3637         ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3638                                 GEN9_SAGV_DISABLE,
3639                                 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
3640                                 1);
3641         mutex_unlock(&dev_priv->rps.hw_lock);
3642
3643         /*
3644          * Some skl systems, pre-release machines in particular,
3645          * don't actually have an SAGV.
3646          */
3647         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3648                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3649                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3650                 return 0;
3651         } else if (ret < 0) {
3652                 DRM_ERROR("Failed to disable the SAGV (%d)\n", ret);
3653                 return ret;
3654         }
3655
3656         dev_priv->sagv_status = I915_SAGV_DISABLED;
3657         return 0;
3658 }
3659
3660 bool intel_can_enable_sagv(struct drm_atomic_state *state)
3661 {
3662         struct drm_device *dev = state->dev;
3663         struct drm_i915_private *dev_priv = to_i915(dev);
3664         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3665         struct intel_crtc *crtc;
3666         struct intel_plane *plane;
3667         struct intel_crtc_state *cstate;
3668         enum pipe pipe;
3669         int level, latency;
3670         int sagv_block_time_us = IS_GEN9(dev_priv) ? 30 : 20;
3671
3672         if (!intel_has_sagv(dev_priv))
3673                 return false;
3674
3675         /*
3676          * SKL+ workaround: bspec recommends we disable the SAGV when we have
3677          * more then one pipe enabled
3678          *
3679          * If there are no active CRTCs, no additional checks need be performed
3680          */
3681         if (hweight32(intel_state->active_crtcs) == 0)
3682                 return true;
3683         else if (hweight32(intel_state->active_crtcs) > 1)
3684                 return false;
3685
3686         /* Since we're now guaranteed to only have one active CRTC... */
3687         pipe = ffs(intel_state->active_crtcs) - 1;
3688         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
3689         cstate = to_intel_crtc_state(crtc->base.state);
3690
3691         if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3692                 return false;
3693
3694         for_each_intel_plane_on_crtc(dev, crtc, plane) {
3695                 struct skl_plane_wm *wm =
3696                         &cstate->wm.skl.optimal.planes[plane->id];
3697
3698                 /* Skip this plane if it's not enabled */
3699                 if (!wm->wm[0].plane_en)
3700                         continue;
3701
3702                 /* Find the highest enabled wm level for this plane */
3703                 for (level = ilk_wm_max_level(dev_priv);
3704                      !wm->wm[level].plane_en; --level)
3705                      { }
3706
3707                 latency = dev_priv->wm.skl_latency[level];
3708
3709                 if (skl_needs_memory_bw_wa(intel_state) &&
3710                     plane->base.state->fb->modifier ==
3711                     I915_FORMAT_MOD_X_TILED)
3712                         latency += 15;
3713
3714                 /*
3715                  * If any of the planes on this pipe don't enable wm levels that
3716                  * incur memory latencies higher than sagv_block_time_us we
3717                  * can't enable the SAGV.
3718                  */
3719                 if (latency < sagv_block_time_us)
3720                         return false;
3721         }
3722
3723         return true;
3724 }
3725
3726 static void
3727 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3728                                    const struct intel_crtc_state *cstate,
3729                                    struct skl_ddb_entry *alloc, /* out */
3730                                    int *num_active /* out */)
3731 {
3732         struct drm_atomic_state *state = cstate->base.state;
3733         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3734         struct drm_i915_private *dev_priv = to_i915(dev);
3735         struct drm_crtc *for_crtc = cstate->base.crtc;
3736         unsigned int pipe_size, ddb_size;
3737         int nth_active_pipe;
3738
3739         if (WARN_ON(!state) || !cstate->base.active) {
3740                 alloc->start = 0;
3741                 alloc->end = 0;
3742                 *num_active = hweight32(dev_priv->active_crtcs);
3743                 return;
3744         }
3745
3746         if (intel_state->active_pipe_changes)
3747                 *num_active = hweight32(intel_state->active_crtcs);
3748         else
3749                 *num_active = hweight32(dev_priv->active_crtcs);
3750
3751         ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3752         WARN_ON(ddb_size == 0);
3753
3754         ddb_size -= 4; /* 4 blocks for bypass path allocation */
3755
3756         /*
3757          * If the state doesn't change the active CRTC's, then there's
3758          * no need to recalculate; the existing pipe allocation limits
3759          * should remain unchanged.  Note that we're safe from racing
3760          * commits since any racing commit that changes the active CRTC
3761          * list would need to grab _all_ crtc locks, including the one
3762          * we currently hold.
3763          */
3764         if (!intel_state->active_pipe_changes) {
3765                 /*
3766                  * alloc may be cleared by clear_intel_crtc_state,
3767                  * copy from old state to be sure
3768                  */
3769                 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
3770                 return;
3771         }
3772
3773         nth_active_pipe = hweight32(intel_state->active_crtcs &
3774                                     (drm_crtc_mask(for_crtc) - 1));
3775         pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3776         alloc->start = nth_active_pipe * ddb_size / *num_active;
3777         alloc->end = alloc->start + pipe_size;
3778 }
3779
3780 static unsigned int skl_cursor_allocation(int num_active)
3781 {
3782         if (num_active == 1)
3783                 return 32;
3784
3785         return 8;
3786 }
3787
3788 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3789 {
3790         entry->start = reg & 0x3ff;
3791         entry->end = (reg >> 16) & 0x3ff;
3792         if (entry->end)
3793                 entry->end += 1;
3794 }
3795
3796 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3797                           struct skl_ddb_allocation *ddb /* out */)
3798 {
3799         struct intel_crtc *crtc;
3800
3801         memset(ddb, 0, sizeof(*ddb));
3802
3803         for_each_intel_crtc(&dev_priv->drm, crtc) {
3804                 enum intel_display_power_domain power_domain;
3805                 enum plane_id plane_id;
3806                 enum pipe pipe = crtc->pipe;
3807
3808                 power_domain = POWER_DOMAIN_PIPE(pipe);
3809                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3810                         continue;
3811
3812                 for_each_plane_id_on_crtc(crtc, plane_id) {
3813                         u32 val;
3814
3815                         if (plane_id != PLANE_CURSOR)
3816                                 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
3817                         else
3818                                 val = I915_READ(CUR_BUF_CFG(pipe));
3819
3820                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
3821                 }
3822
3823                 intel_display_power_put(dev_priv, power_domain);
3824         }
3825 }
3826
3827 /*
3828  * Determines the downscale amount of a plane for the purposes of watermark calculations.
3829  * The bspec defines downscale amount as:
3830  *
3831  * """
3832  * Horizontal down scale amount = maximum[1, Horizontal source size /
3833  *                                           Horizontal destination size]
3834  * Vertical down scale amount = maximum[1, Vertical source size /
3835  *                                         Vertical destination size]
3836  * Total down scale amount = Horizontal down scale amount *
3837  *                           Vertical down scale amount
3838  * """
3839  *
3840  * Return value is provided in 16.16 fixed point form to retain fractional part.
3841  * Caller should take care of dividing & rounding off the value.
3842  */
3843 static uint_fixed_16_16_t
3844 skl_plane_downscale_amount(const struct intel_crtc_state *cstate,
3845                            const struct intel_plane_state *pstate)
3846 {
3847         struct intel_plane *plane = to_intel_plane(pstate->base.plane);
3848         uint32_t src_w, src_h, dst_w, dst_h;
3849         uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
3850         uint_fixed_16_16_t downscale_h, downscale_w;
3851
3852         if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
3853                 return u32_to_fixed16(0);
3854
3855         /* n.b., src is 16.16 fixed point, dst is whole integer */
3856         if (plane->id == PLANE_CURSOR) {
3857                 /*
3858                  * Cursors only support 0/180 degree rotation,
3859                  * hence no need to account for rotation here.
3860                  */
3861                 src_w = pstate->base.src_w >> 16;
3862                 src_h = pstate->base.src_h >> 16;
3863                 dst_w = pstate->base.crtc_w;
3864                 dst_h = pstate->base.crtc_h;
3865         } else {
3866                 /*
3867                  * Src coordinates are already rotated by 270 degrees for
3868                  * the 90/270 degree plane rotation cases (to match the
3869                  * GTT mapping), hence no need to account for rotation here.
3870                  */
3871                 src_w = drm_rect_width(&pstate->base.src) >> 16;
3872                 src_h = drm_rect_height(&pstate->base.src) >> 16;
3873                 dst_w = drm_rect_width(&pstate->base.dst);
3874                 dst_h = drm_rect_height(&pstate->base.dst);
3875         }
3876
3877         fp_w_ratio = div_fixed16(src_w, dst_w);
3878         fp_h_ratio = div_fixed16(src_h, dst_h);
3879         downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
3880         downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
3881
3882         return mul_fixed16(downscale_w, downscale_h);
3883 }
3884
3885 static uint_fixed_16_16_t
3886 skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
3887 {
3888         uint_fixed_16_16_t pipe_downscale = u32_to_fixed16(1);
3889
3890         if (!crtc_state->base.enable)
3891                 return pipe_downscale;
3892
3893         if (crtc_state->pch_pfit.enabled) {
3894                 uint32_t src_w, src_h, dst_w, dst_h;
3895                 uint32_t pfit_size = crtc_state->pch_pfit.size;
3896                 uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
3897                 uint_fixed_16_16_t downscale_h, downscale_w;
3898
3899                 src_w = crtc_state->pipe_src_w;
3900                 src_h = crtc_state->pipe_src_h;
3901                 dst_w = pfit_size >> 16;
3902                 dst_h = pfit_size & 0xffff;
3903
3904                 if (!dst_w || !dst_h)
3905                         return pipe_downscale;
3906
3907                 fp_w_ratio = div_fixed16(src_w, dst_w);
3908                 fp_h_ratio = div_fixed16(src_h, dst_h);
3909                 downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
3910                 downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
3911
3912                 pipe_downscale = mul_fixed16(downscale_w, downscale_h);
3913         }
3914
3915         return pipe_downscale;
3916 }
3917
3918 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
3919                                   struct intel_crtc_state *cstate)
3920 {
3921         struct drm_crtc_state *crtc_state = &cstate->base;
3922         struct drm_atomic_state *state = crtc_state->state;
3923         struct drm_plane *plane;
3924         const struct drm_plane_state *pstate;
3925         struct intel_plane_state *intel_pstate;
3926         int crtc_clock, dotclk;
3927         uint32_t pipe_max_pixel_rate;
3928         uint_fixed_16_16_t pipe_downscale;
3929         uint_fixed_16_16_t max_downscale = u32_to_fixed16(1);
3930
3931         if (!cstate->base.enable)
3932                 return 0;
3933
3934         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
3935                 uint_fixed_16_16_t plane_downscale;
3936                 uint_fixed_16_16_t fp_9_div_8 = div_fixed16(9, 8);
3937                 int bpp;
3938
3939                 if (!intel_wm_plane_visible(cstate,
3940                                             to_intel_plane_state(pstate)))
3941                         continue;
3942
3943                 if (WARN_ON(!pstate->fb))
3944                         return -EINVAL;
3945
3946                 intel_pstate = to_intel_plane_state(pstate);
3947                 plane_downscale = skl_plane_downscale_amount(cstate,
3948                                                              intel_pstate);
3949                 bpp = pstate->fb->format->cpp[0] * 8;
3950                 if (bpp == 64)
3951                         plane_downscale = mul_fixed16(plane_downscale,
3952                                                       fp_9_div_8);
3953
3954                 max_downscale = max_fixed16(plane_downscale, max_downscale);
3955         }
3956         pipe_downscale = skl_pipe_downscale_amount(cstate);
3957
3958         pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
3959
3960         crtc_clock = crtc_state->adjusted_mode.crtc_clock;
3961         dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
3962
3963         if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)))
3964                 dotclk *= 2;
3965
3966         pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
3967
3968         if (pipe_max_pixel_rate < crtc_clock) {
3969                 DRM_DEBUG_KMS("Max supported pixel clock with scaling exceeded\n");
3970                 return -EINVAL;
3971         }
3972
3973         return 0;
3974 }
3975
3976 static unsigned int
3977 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3978                              const struct drm_plane_state *pstate,
3979                              int y)
3980 {
3981         struct intel_plane *plane = to_intel_plane(pstate->plane);
3982         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3983         uint32_t data_rate;
3984         uint32_t width = 0, height = 0;
3985         struct drm_framebuffer *fb;
3986         u32 format;
3987         uint_fixed_16_16_t down_scale_amount;
3988
3989         if (!intel_pstate->base.visible)
3990                 return 0;
3991
3992         fb = pstate->fb;
3993         format = fb->format->format;
3994
3995         if (plane->id == PLANE_CURSOR)
3996                 return 0;
3997         if (y && format != DRM_FORMAT_NV12)
3998                 return 0;
3999
4000         /*
4001          * Src coordinates are already rotated by 270 degrees for
4002          * the 90/270 degree plane rotation cases (to match the
4003          * GTT mapping), hence no need to account for rotation here.
4004          */
4005         width = drm_rect_width(&intel_pstate->base.src) >> 16;
4006         height = drm_rect_height(&intel_pstate->base.src) >> 16;
4007
4008         /* for planar format */
4009         if (format == DRM_FORMAT_NV12) {
4010                 if (y)  /* y-plane data rate */
4011                         data_rate = width * height *
4012                                 fb->format->cpp[0];
4013                 else    /* uv-plane data rate */
4014                         data_rate = (width / 2) * (height / 2) *
4015                                 fb->format->cpp[1];
4016         } else {
4017                 /* for packed formats */
4018                 data_rate = width * height * fb->format->cpp[0];
4019         }
4020
4021         down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
4022
4023         return mul_round_up_u32_fixed16(data_rate, down_scale_amount);
4024 }
4025
4026 /*
4027  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
4028  * a 8192x4096@32bpp framebuffer:
4029  *   3 * 4096 * 8192  * 4 < 2^32
4030  */
4031 static unsigned int
4032 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
4033                                  unsigned *plane_data_rate,
4034                                  unsigned *plane_y_data_rate)
4035 {
4036         struct drm_crtc_state *cstate = &intel_cstate->base;
4037         struct drm_atomic_state *state = cstate->state;
4038         struct drm_plane *plane;
4039         const struct drm_plane_state *pstate;
4040         unsigned int total_data_rate = 0;
4041
4042         if (WARN_ON(!state))
4043                 return 0;
4044
4045         /* Calculate and cache data rate for each plane */
4046         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
4047                 enum plane_id plane_id = to_intel_plane(plane)->id;
4048                 unsigned int rate;
4049
4050                 /* packed/uv */
4051                 rate = skl_plane_relative_data_rate(intel_cstate,
4052                                                     pstate, 0);
4053                 plane_data_rate[plane_id] = rate;
4054
4055                 total_data_rate += rate;
4056
4057                 /* y-plane */
4058                 rate = skl_plane_relative_data_rate(intel_cstate,
4059                                                     pstate, 1);
4060                 plane_y_data_rate[plane_id] = rate;
4061
4062                 total_data_rate += rate;
4063         }
4064
4065         return total_data_rate;
4066 }
4067
4068 static uint16_t
4069 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
4070                   const int y)
4071 {
4072         struct drm_framebuffer *fb = pstate->fb;
4073         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
4074         uint32_t src_w, src_h;
4075         uint32_t min_scanlines = 8;
4076         uint8_t plane_bpp;
4077
4078         if (WARN_ON(!fb))
4079                 return 0;
4080
4081         /* For packed formats, no y-plane, return 0 */
4082         if (y && fb->format->format != DRM_FORMAT_NV12)
4083                 return 0;
4084
4085         /* For Non Y-tile return 8-blocks */
4086         if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
4087             fb->modifier != I915_FORMAT_MOD_Yf_TILED &&
4088             fb->modifier != I915_FORMAT_MOD_Y_TILED_CCS &&
4089             fb->modifier != I915_FORMAT_MOD_Yf_TILED_CCS)
4090                 return 8;
4091
4092         /*
4093          * Src coordinates are already rotated by 270 degrees for
4094          * the 90/270 degree plane rotation cases (to match the
4095          * GTT mapping), hence no need to account for rotation here.
4096          */
4097         src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
4098         src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
4099
4100         /* Halve UV plane width and height for NV12 */
4101         if (fb->format->format == DRM_FORMAT_NV12 && !y) {
4102                 src_w /= 2;
4103                 src_h /= 2;
4104         }
4105
4106         if (fb->format->format == DRM_FORMAT_NV12 && !y)
4107                 plane_bpp = fb->format->cpp[1];
4108         else
4109                 plane_bpp = fb->format->cpp[0];
4110
4111         if (drm_rotation_90_or_270(pstate->rotation)) {
4112                 switch (plane_bpp) {
4113                 case 1:
4114                         min_scanlines = 32;
4115                         break;
4116                 case 2:
4117                         min_scanlines = 16;
4118                         break;
4119                 case 4:
4120                         min_scanlines = 8;
4121                         break;
4122                 case 8:
4123                         min_scanlines = 4;
4124                         break;
4125                 default:
4126                         WARN(1, "Unsupported pixel depth %u for rotation",
4127                              plane_bpp);
4128                         min_scanlines = 32;
4129                 }
4130         }
4131
4132         return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
4133 }
4134
4135 static void
4136 skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
4137                  uint16_t *minimum, uint16_t *y_minimum)
4138 {
4139         const struct drm_plane_state *pstate;
4140         struct drm_plane *plane;
4141
4142         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
4143                 enum plane_id plane_id = to_intel_plane(plane)->id;
4144
4145                 if (plane_id == PLANE_CURSOR)
4146                         continue;
4147
4148                 if (!pstate->visible)
4149                         continue;
4150
4151                 minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
4152                 y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
4153         }
4154
4155         minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
4156 }
4157
4158 static int
4159 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
4160                       struct skl_ddb_allocation *ddb /* out */)
4161 {
4162         struct drm_atomic_state *state = cstate->base.state;
4163         struct drm_crtc *crtc = cstate->base.crtc;
4164         struct drm_device *dev = crtc->dev;
4165         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4166         enum pipe pipe = intel_crtc->pipe;
4167         struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
4168         uint16_t alloc_size, start;
4169         uint16_t minimum[I915_MAX_PLANES] = {};
4170         uint16_t y_minimum[I915_MAX_PLANES] = {};
4171         unsigned int total_data_rate;
4172         enum plane_id plane_id;
4173         int num_active;
4174         unsigned plane_data_rate[I915_MAX_PLANES] = {};
4175         unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
4176         uint16_t total_min_blocks = 0;
4177
4178         /* Clear the partitioning for disabled planes. */
4179         memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
4180         memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
4181
4182         if (WARN_ON(!state))
4183                 return 0;
4184
4185         if (!cstate->base.active) {
4186                 alloc->start = alloc->end = 0;
4187                 return 0;
4188         }
4189
4190         skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
4191         alloc_size = skl_ddb_entry_size(alloc);
4192         if (alloc_size == 0)
4193                 return 0;
4194
4195         skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
4196
4197         /*
4198          * 1. Allocate the mininum required blocks for each active plane
4199          * and allocate the cursor, it doesn't require extra allocation
4200          * proportional to the data rate.
4201          */
4202
4203         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4204                 total_min_blocks += minimum[plane_id];
4205                 total_min_blocks += y_minimum[plane_id];
4206         }
4207
4208         if (total_min_blocks > alloc_size) {
4209                 DRM_DEBUG_KMS("Requested display configuration exceeds system DDB limitations");
4210                 DRM_DEBUG_KMS("minimum required %d/%d\n", total_min_blocks,
4211                                                         alloc_size);
4212                 return -EINVAL;
4213         }
4214
4215         alloc_size -= total_min_blocks;
4216         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
4217         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
4218
4219         /*
4220          * 2. Distribute the remaining space in proportion to the amount of
4221          * data each plane needs to fetch from memory.
4222          *
4223          * FIXME: we may not allocate every single block here.
4224          */
4225         total_data_rate = skl_get_total_relative_data_rate(cstate,
4226                                                            plane_data_rate,
4227                                                            plane_y_data_rate);
4228         if (total_data_rate == 0)
4229                 return 0;
4230
4231         start = alloc->start;
4232         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4233                 unsigned int data_rate, y_data_rate;
4234                 uint16_t plane_blocks, y_plane_blocks = 0;
4235
4236                 if (plane_id == PLANE_CURSOR)
4237                         continue;
4238
4239                 data_rate = plane_data_rate[plane_id];
4240
4241                 /*
4242                  * allocation for (packed formats) or (uv-plane part of planar format):
4243                  * promote the expression to 64 bits to avoid overflowing, the
4244                  * result is < available as data_rate / total_data_rate < 1
4245                  */
4246                 plane_blocks = minimum[plane_id];
4247                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
4248                                         total_data_rate);
4249
4250                 /* Leave disabled planes at (0,0) */
4251                 if (data_rate) {
4252                         ddb->plane[pipe][plane_id].start = start;
4253                         ddb->plane[pipe][plane_id].end = start + plane_blocks;
4254                 }
4255
4256                 start += plane_blocks;
4257
4258                 /*
4259                  * allocation for y_plane part of planar format:
4260                  */
4261                 y_data_rate = plane_y_data_rate[plane_id];
4262
4263                 y_plane_blocks = y_minimum[plane_id];
4264                 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
4265                                         total_data_rate);
4266
4267                 if (y_data_rate) {
4268                         ddb->y_plane[pipe][plane_id].start = start;
4269                         ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
4270                 }
4271
4272                 start += y_plane_blocks;
4273         }
4274
4275         return 0;
4276 }
4277
4278 /*
4279  * The max latency should be 257 (max the punit can code is 255 and we add 2us
4280  * for the read latency) and cpp should always be <= 8, so that
4281  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
4282  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
4283 */
4284 static uint_fixed_16_16_t
4285 skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
4286                uint8_t cpp, uint32_t latency)
4287 {
4288         uint32_t wm_intermediate_val;
4289         uint_fixed_16_16_t ret;
4290
4291         if (latency == 0)
4292                 return FP_16_16_MAX;
4293
4294         wm_intermediate_val = latency * pixel_rate * cpp;
4295         ret = div_fixed16(wm_intermediate_val, 1000 * 512);
4296
4297         if (INTEL_GEN(dev_priv) >= 10)
4298                 ret = add_fixed16_u32(ret, 1);
4299
4300         return ret;
4301 }
4302
4303 static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
4304                         uint32_t pipe_htotal,
4305                         uint32_t latency,
4306                         uint_fixed_16_16_t plane_blocks_per_line)
4307 {
4308         uint32_t wm_intermediate_val;
4309         uint_fixed_16_16_t ret;
4310
4311         if (latency == 0)
4312                 return FP_16_16_MAX;
4313
4314         wm_intermediate_val = latency * pixel_rate;
4315         wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val,
4316                                            pipe_htotal * 1000);
4317         ret = mul_u32_fixed16(wm_intermediate_val, plane_blocks_per_line);
4318         return ret;
4319 }
4320
4321 static uint_fixed_16_16_t
4322 intel_get_linetime_us(struct intel_crtc_state *cstate)
4323 {
4324         uint32_t pixel_rate;
4325         uint32_t crtc_htotal;
4326         uint_fixed_16_16_t linetime_us;
4327
4328         if (!cstate->base.active)
4329                 return u32_to_fixed16(0);
4330
4331         pixel_rate = cstate->pixel_rate;
4332
4333         if (WARN_ON(pixel_rate == 0))
4334                 return u32_to_fixed16(0);
4335
4336         crtc_htotal = cstate->base.adjusted_mode.crtc_htotal;
4337         linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
4338
4339         return linetime_us;
4340 }
4341
4342 static uint32_t
4343 skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
4344                               const struct intel_plane_state *pstate)
4345 {
4346         uint64_t adjusted_pixel_rate;
4347         uint_fixed_16_16_t downscale_amount;
4348
4349         /* Shouldn't reach here on disabled planes... */
4350         if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
4351                 return 0;
4352
4353         /*
4354          * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
4355          * with additional adjustments for plane-specific scaling.
4356          */
4357         adjusted_pixel_rate = cstate->pixel_rate;
4358         downscale_amount = skl_plane_downscale_amount(cstate, pstate);
4359
4360         return mul_round_up_u32_fixed16(adjusted_pixel_rate,
4361                                             downscale_amount);
4362 }
4363
4364 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
4365                                 struct intel_crtc_state *cstate,
4366                                 const struct intel_plane_state *intel_pstate,
4367                                 uint16_t ddb_allocation,
4368                                 int level,
4369                                 uint16_t *out_blocks, /* out */
4370                                 uint8_t *out_lines, /* out */
4371                                 bool *enabled /* out */)
4372 {
4373         struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
4374         const struct drm_plane_state *pstate = &intel_pstate->base;
4375         const struct drm_framebuffer *fb = pstate->fb;
4376         uint32_t latency = dev_priv->wm.skl_latency[level];
4377         uint_fixed_16_16_t method1, method2;
4378         uint_fixed_16_16_t plane_blocks_per_line;
4379         uint_fixed_16_16_t selected_result;
4380         uint32_t interm_pbpl;
4381         uint32_t plane_bytes_per_line;
4382         uint32_t res_blocks, res_lines;
4383         uint8_t cpp;
4384         uint32_t width = 0;
4385         uint32_t plane_pixel_rate;
4386         uint_fixed_16_16_t y_tile_minimum;
4387         uint32_t y_min_scanlines;
4388         struct intel_atomic_state *state =
4389                 to_intel_atomic_state(cstate->base.state);
4390         bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
4391         bool y_tiled, x_tiled;
4392
4393         if (latency == 0 ||
4394             !intel_wm_plane_visible(cstate, intel_pstate)) {
4395                 *enabled = false;
4396                 return 0;
4397         }
4398
4399         y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
4400                   fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
4401                   fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
4402                   fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
4403         x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
4404
4405         /* Display WA #1141: kbl,cfl */
4406         if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) &&
4407             dev_priv->ipc_enabled)
4408                 latency += 4;
4409
4410         if (apply_memory_bw_wa && x_tiled)
4411                 latency += 15;
4412
4413         if (plane->id == PLANE_CURSOR) {
4414                 width = intel_pstate->base.crtc_w;
4415         } else {
4416                 /*
4417                  * Src coordinates are already rotated by 270 degrees for
4418                  * the 90/270 degree plane rotation cases (to match the
4419                  * GTT mapping), hence no need to account for rotation here.
4420                  */
4421                 width = drm_rect_width(&intel_pstate->base.src) >> 16;
4422         }
4423
4424         cpp = (fb->format->format == DRM_FORMAT_NV12) ? fb->format->cpp[1] :
4425                                                         fb->format->cpp[0];
4426         plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
4427
4428         if (drm_rotation_90_or_270(pstate->rotation)) {
4429
4430                 switch (cpp) {
4431                 case 1:
4432                         y_min_scanlines = 16;
4433                         break;
4434                 case 2:
4435                         y_min_scanlines = 8;
4436                         break;
4437                 case 4:
4438                         y_min_scanlines = 4;
4439                         break;
4440                 default:
4441                         MISSING_CASE(cpp);
4442                         return -EINVAL;
4443                 }
4444         } else {
4445                 y_min_scanlines = 4;
4446         }
4447
4448         if (apply_memory_bw_wa)
4449                 y_min_scanlines *= 2;
4450
4451         plane_bytes_per_line = width * cpp;
4452         if (y_tiled) {
4453                 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line *
4454                                            y_min_scanlines, 512);
4455
4456                 if (INTEL_GEN(dev_priv) >= 10)
4457                         interm_pbpl++;
4458
4459                 plane_blocks_per_line = div_fixed16(interm_pbpl,
4460                                                         y_min_scanlines);
4461         } else if (x_tiled && INTEL_GEN(dev_priv) == 9) {
4462                 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512);
4463                 plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
4464         } else {
4465                 interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
4466                 plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
4467         }
4468
4469         method1 = skl_wm_method1(dev_priv, plane_pixel_rate, cpp, latency);
4470         method2 = skl_wm_method2(plane_pixel_rate,
4471                                  cstate->base.adjusted_mode.crtc_htotal,
4472                                  latency,
4473                                  plane_blocks_per_line);
4474
4475         y_tile_minimum = mul_u32_fixed16(y_min_scanlines,
4476                                          plane_blocks_per_line);
4477
4478         if (y_tiled) {
4479                 selected_result = max_fixed16(method2, y_tile_minimum);
4480         } else {
4481                 uint32_t linetime_us;
4482
4483                 linetime_us = fixed16_to_u32_round_up(
4484                                 intel_get_linetime_us(cstate));
4485                 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
4486                     (plane_bytes_per_line / 512 < 1))
4487                         selected_result = method2;
4488                 else if (ddb_allocation >=
4489                          fixed16_to_u32_round_up(plane_blocks_per_line))
4490                         selected_result = min_fixed16(method1, method2);
4491                 else if (latency >= linetime_us)
4492                         selected_result = min_fixed16(method1, method2);
4493                 else
4494                         selected_result = method1;
4495         }
4496
4497         res_blocks = fixed16_to_u32_round_up(selected_result) + 1;
4498         res_lines = div_round_up_fixed16(selected_result,
4499                                          plane_blocks_per_line);
4500
4501         /* Display WA #1125: skl,bxt,kbl,glk */
4502         if (level == 0 &&
4503             (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
4504              fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS))
4505                 res_blocks += fixed16_to_u32_round_up(y_tile_minimum);
4506
4507         /* Display WA #1126: skl,bxt,kbl,glk */
4508         if (level >= 1 && level <= 7) {
4509                 if (y_tiled) {
4510                         res_blocks += fixed16_to_u32_round_up(y_tile_minimum);
4511                         res_lines += y_min_scanlines;
4512                 } else {
4513                         res_blocks++;
4514                 }
4515         }
4516
4517         if (res_blocks >= ddb_allocation || res_lines > 31) {
4518                 *enabled = false;
4519
4520                 /*
4521                  * If there are no valid level 0 watermarks, then we can't
4522                  * support this display configuration.
4523                  */
4524                 if (level) {
4525                         return 0;
4526                 } else {
4527                         struct drm_plane *plane = pstate->plane;
4528
4529                         DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
4530                         DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n",
4531                                       plane->base.id, plane->name,
4532                                       res_blocks, ddb_allocation, res_lines);
4533                         return -EINVAL;
4534                 }
4535         }
4536
4537         *out_blocks = res_blocks;
4538         *out_lines = res_lines;
4539         *enabled = true;
4540
4541         return 0;
4542 }
4543
4544 static int
4545 skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
4546                       struct skl_ddb_allocation *ddb,
4547                       struct intel_crtc_state *cstate,
4548                       const struct intel_plane_state *intel_pstate,
4549                       struct skl_plane_wm *wm)
4550 {
4551         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4552         struct drm_plane *plane = intel_pstate->base.plane;
4553         struct intel_plane *intel_plane = to_intel_plane(plane);
4554         uint16_t ddb_blocks;
4555         enum pipe pipe = intel_crtc->pipe;
4556         int level, max_level = ilk_wm_max_level(dev_priv);
4557         int ret;
4558
4559         if (WARN_ON(!intel_pstate->base.fb))
4560                 return -EINVAL;
4561
4562         ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
4563
4564         for (level = 0; level <= max_level; level++) {
4565                 struct skl_wm_level *result = &wm->wm[level];
4566
4567                 ret = skl_compute_plane_wm(dev_priv,
4568                                            cstate,
4569                                            intel_pstate,
4570                                            ddb_blocks,
4571                                            level,
4572                                            &result->plane_res_b,
4573                                            &result->plane_res_l,
4574                                            &result->plane_en);
4575                 if (ret)
4576                         return ret;
4577         }
4578
4579         return 0;
4580 }
4581
4582 static uint32_t
4583 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
4584 {
4585         struct drm_atomic_state *state = cstate->base.state;
4586         struct drm_i915_private *dev_priv = to_i915(state->dev);
4587         uint_fixed_16_16_t linetime_us;
4588         uint32_t linetime_wm;
4589
4590         linetime_us = intel_get_linetime_us(cstate);
4591
4592         if (is_fixed16_zero(linetime_us))
4593                 return 0;
4594
4595         linetime_wm = fixed16_to_u32_round_up(mul_u32_fixed16(8, linetime_us));
4596
4597         /* Display WA #1135: bxt. */
4598         if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled)
4599                 linetime_wm = DIV_ROUND_UP(linetime_wm, 2);
4600
4601         return linetime_wm;
4602 }
4603
4604 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
4605                                       struct skl_wm_level *trans_wm /* out */)
4606 {
4607         if (!cstate->base.active)
4608                 return;
4609
4610         /* Until we know more, just disable transition WMs */
4611         trans_wm->plane_en = false;
4612 }
4613
4614 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
4615                              struct skl_ddb_allocation *ddb,
4616                              struct skl_pipe_wm *pipe_wm)
4617 {
4618         struct drm_device *dev = cstate->base.crtc->dev;
4619         struct drm_crtc_state *crtc_state = &cstate->base;
4620         const struct drm_i915_private *dev_priv = to_i915(dev);
4621         struct drm_plane *plane;
4622         const struct drm_plane_state *pstate;
4623         struct skl_plane_wm *wm;
4624         int ret;
4625
4626         /*
4627          * We'll only calculate watermarks for planes that are actually
4628          * enabled, so make sure all other planes are set as disabled.
4629          */
4630         memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
4631
4632         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
4633                 const struct intel_plane_state *intel_pstate =
4634                                                 to_intel_plane_state(pstate);
4635                 enum plane_id plane_id = to_intel_plane(plane)->id;
4636
4637                 wm = &pipe_wm->planes[plane_id];
4638
4639                 ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
4640                                             intel_pstate, wm);
4641                 if (ret)
4642                         return ret;
4643                 skl_compute_transition_wm(cstate, &wm->trans_wm);
4644         }
4645         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
4646
4647         return 0;
4648 }
4649
4650 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
4651                                 i915_reg_t reg,
4652                                 const struct skl_ddb_entry *entry)
4653 {
4654         if (entry->end)
4655                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
4656         else
4657                 I915_WRITE(reg, 0);
4658 }
4659
4660 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
4661                                i915_reg_t reg,
4662                                const struct skl_wm_level *level)
4663 {
4664         uint32_t val = 0;
4665
4666         if (level->plane_en) {
4667                 val |= PLANE_WM_EN;
4668                 val |= level->plane_res_b;
4669                 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
4670         }
4671
4672         I915_WRITE(reg, val);
4673 }
4674
4675 static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
4676                                const struct skl_plane_wm *wm,
4677                                const struct skl_ddb_allocation *ddb,
4678                                enum plane_id plane_id)
4679 {
4680         struct drm_crtc *crtc = &intel_crtc->base;
4681         struct drm_device *dev = crtc->dev;
4682         struct drm_i915_private *dev_priv = to_i915(dev);
4683         int level, max_level = ilk_wm_max_level(dev_priv);
4684         enum pipe pipe = intel_crtc->pipe;
4685
4686         for (level = 0; level <= max_level; level++) {
4687                 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
4688                                    &wm->wm[level]);
4689         }
4690         skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
4691                            &wm->trans_wm);
4692
4693         skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
4694                             &ddb->plane[pipe][plane_id]);
4695         skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
4696                             &ddb->y_plane[pipe][plane_id]);
4697 }
4698
4699 static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
4700                                 const struct skl_plane_wm *wm,
4701                                 const struct skl_ddb_allocation *ddb)
4702 {
4703         struct drm_crtc *crtc = &intel_crtc->base;
4704         struct drm_device *dev = crtc->dev;
4705         struct drm_i915_private *dev_priv = to_i915(dev);
4706         int level, max_level = ilk_wm_max_level(dev_priv);
4707         enum pipe pipe = intel_crtc->pipe;
4708
4709         for (level = 0; level <= max_level; level++) {
4710                 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
4711                                    &wm->wm[level]);
4712         }
4713         skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
4714
4715         skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4716                             &ddb->plane[pipe][PLANE_CURSOR]);
4717 }
4718
4719 bool skl_wm_level_equals(const struct skl_wm_level *l1,
4720                          const struct skl_wm_level *l2)
4721 {
4722         if (l1->plane_en != l2->plane_en)
4723                 return false;
4724
4725         /* If both planes aren't enabled, the rest shouldn't matter */
4726         if (!l1->plane_en)
4727                 return true;
4728
4729         return (l1->plane_res_l == l2->plane_res_l &&
4730                 l1->plane_res_b == l2->plane_res_b);
4731 }
4732
4733 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
4734                                            const struct skl_ddb_entry *b)
4735 {
4736         return a->start < b->end && b->start < a->end;
4737 }
4738
4739 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
4740                                  const struct skl_ddb_entry *ddb,
4741                                  int ignore)
4742 {
4743         int i;
4744
4745         for (i = 0; i < I915_MAX_PIPES; i++)
4746                 if (i != ignore && entries[i] &&
4747                     skl_ddb_entries_overlap(ddb, entries[i]))
4748                         return true;
4749
4750         return false;
4751 }
4752
4753 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
4754                               const struct skl_pipe_wm *old_pipe_wm,
4755                               struct skl_pipe_wm *pipe_wm, /* out */
4756                               struct skl_ddb_allocation *ddb, /* out */
4757                               bool *changed /* out */)
4758 {
4759         struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
4760         int ret;
4761
4762         ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
4763         if (ret)
4764                 return ret;
4765
4766         if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
4767                 *changed = false;
4768         else
4769                 *changed = true;
4770
4771         return 0;
4772 }
4773
4774 static uint32_t
4775 pipes_modified(struct drm_atomic_state *state)
4776 {
4777         struct drm_crtc *crtc;
4778         struct drm_crtc_state *cstate;
4779         uint32_t i, ret = 0;
4780
4781         for_each_new_crtc_in_state(state, crtc, cstate, i)
4782                 ret |= drm_crtc_mask(crtc);
4783
4784         return ret;
4785 }
4786
4787 static int
4788 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
4789 {
4790         struct drm_atomic_state *state = cstate->base.state;
4791         struct drm_device *dev = state->dev;
4792         struct drm_crtc *crtc = cstate->base.crtc;
4793         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4794         struct drm_i915_private *dev_priv = to_i915(dev);
4795         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4796         struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4797         struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
4798         struct drm_plane_state *plane_state;
4799         struct drm_plane *plane;
4800         enum pipe pipe = intel_crtc->pipe;
4801
4802         WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
4803
4804         drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
4805                 enum plane_id plane_id = to_intel_plane(plane)->id;
4806
4807                 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
4808                                         &new_ddb->plane[pipe][plane_id]) &&
4809                     skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
4810                                         &new_ddb->y_plane[pipe][plane_id]))
4811                         continue;
4812
4813                 plane_state = drm_atomic_get_plane_state(state, plane);
4814                 if (IS_ERR(plane_state))
4815                         return PTR_ERR(plane_state);
4816         }
4817
4818         return 0;
4819 }
4820
4821 static int
4822 skl_compute_ddb(struct drm_atomic_state *state)
4823 {
4824         struct drm_device *dev = state->dev;
4825         struct drm_i915_private *dev_priv = to_i915(dev);
4826         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4827         struct intel_crtc *intel_crtc;
4828         struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
4829         uint32_t realloc_pipes = pipes_modified(state);
4830         int ret;
4831
4832         /*
4833          * If this is our first atomic update following hardware readout,
4834          * we can't trust the DDB that the BIOS programmed for us.  Let's
4835          * pretend that all pipes switched active status so that we'll
4836          * ensure a full DDB recompute.
4837          */
4838         if (dev_priv->wm.distrust_bios_wm) {
4839                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4840                                        state->acquire_ctx);
4841                 if (ret)
4842                         return ret;
4843
4844                 intel_state->active_pipe_changes = ~0;
4845
4846                 /*
4847                  * We usually only initialize intel_state->active_crtcs if we
4848                  * we're doing a modeset; make sure this field is always
4849                  * initialized during the sanitization process that happens
4850                  * on the first commit too.
4851                  */
4852                 if (!intel_state->modeset)
4853                         intel_state->active_crtcs = dev_priv->active_crtcs;
4854         }
4855
4856         /*
4857          * If the modeset changes which CRTC's are active, we need to
4858          * recompute the DDB allocation for *all* active pipes, even
4859          * those that weren't otherwise being modified in any way by this
4860          * atomic commit.  Due to the shrinking of the per-pipe allocations
4861          * when new active CRTC's are added, it's possible for a pipe that
4862          * we were already using and aren't changing at all here to suddenly
4863          * become invalid if its DDB needs exceeds its new allocation.
4864          *
4865          * Note that if we wind up doing a full DDB recompute, we can't let
4866          * any other display updates race with this transaction, so we need
4867          * to grab the lock on *all* CRTC's.
4868          */
4869         if (intel_state->active_pipe_changes) {
4870                 realloc_pipes = ~0;
4871                 intel_state->wm_results.dirty_pipes = ~0;
4872         }
4873
4874         /*
4875          * We're not recomputing for the pipes not included in the commit, so
4876          * make sure we start with the current state.
4877          */
4878         memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4879
4880         for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4881                 struct intel_crtc_state *cstate;
4882
4883                 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4884                 if (IS_ERR(cstate))
4885                         return PTR_ERR(cstate);
4886
4887                 ret = skl_allocate_pipe_ddb(cstate, ddb);
4888                 if (ret)
4889                         return ret;
4890
4891                 ret = skl_ddb_add_affected_planes(cstate);
4892                 if (ret)
4893                         return ret;
4894         }
4895
4896         return 0;
4897 }
4898
4899 static void
4900 skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4901                      struct skl_wm_values *src,
4902                      enum pipe pipe)
4903 {
4904         memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4905                sizeof(dst->ddb.y_plane[pipe]));
4906         memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4907                sizeof(dst->ddb.plane[pipe]));
4908 }
4909
4910 static void
4911 skl_print_wm_changes(const struct drm_atomic_state *state)
4912 {
4913         const struct drm_device *dev = state->dev;
4914         const struct drm_i915_private *dev_priv = to_i915(dev);
4915         const struct intel_atomic_state *intel_state =
4916                 to_intel_atomic_state(state);
4917         const struct drm_crtc *crtc;
4918         const struct drm_crtc_state *cstate;
4919         const struct intel_plane *intel_plane;
4920         const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4921         const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4922         int i;
4923
4924         for_each_new_crtc_in_state(state, crtc, cstate, i) {
4925                 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4926                 enum pipe pipe = intel_crtc->pipe;
4927
4928                 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4929                         enum plane_id plane_id = intel_plane->id;
4930                         const struct skl_ddb_entry *old, *new;
4931
4932                         old = &old_ddb->plane[pipe][plane_id];
4933                         new = &new_ddb->plane[pipe][plane_id];
4934
4935                         if (skl_ddb_entry_equal(old, new))
4936                                 continue;
4937
4938                         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4939                                          intel_plane->base.base.id,
4940                                          intel_plane->base.name,
4941                                          old->start, old->end,
4942                                          new->start, new->end);
4943                 }
4944         }
4945 }
4946
4947 static int
4948 skl_compute_wm(struct drm_atomic_state *state)
4949 {
4950         struct drm_crtc *crtc;
4951         struct drm_crtc_state *cstate;
4952         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4953         struct skl_wm_values *results = &intel_state->wm_results;
4954         struct drm_device *dev = state->dev;
4955         struct skl_pipe_wm *pipe_wm;
4956         bool changed = false;
4957         int ret, i;
4958
4959         /*
4960          * When we distrust bios wm we always need to recompute to set the
4961          * expected DDB allocations for each CRTC.
4962          */
4963         if (to_i915(dev)->wm.distrust_bios_wm)
4964                 changed = true;
4965
4966         /*
4967          * If this transaction isn't actually touching any CRTC's, don't
4968          * bother with watermark calculation.  Note that if we pass this
4969          * test, we're guaranteed to hold at least one CRTC state mutex,
4970          * which means we can safely use values like dev_priv->active_crtcs
4971          * since any racing commits that want to update them would need to
4972          * hold _all_ CRTC state mutexes.
4973          */
4974         for_each_new_crtc_in_state(state, crtc, cstate, i)
4975                 changed = true;
4976
4977         if (!changed)
4978                 return 0;
4979
4980         /* Clear all dirty flags */
4981         results->dirty_pipes = 0;
4982
4983         ret = skl_compute_ddb(state);
4984         if (ret)
4985                 return ret;
4986
4987         /*
4988          * Calculate WM's for all pipes that are part of this transaction.
4989          * Note that the DDB allocation above may have added more CRTC's that
4990          * weren't otherwise being modified (and set bits in dirty_pipes) if
4991          * pipe allocations had to change.
4992          *
4993          * FIXME:  Now that we're doing this in the atomic check phase, we
4994          * should allow skl_update_pipe_wm() to return failure in cases where
4995          * no suitable watermark values can be found.
4996          */
4997         for_each_new_crtc_in_state(state, crtc, cstate, i) {
4998                 struct intel_crtc_state *intel_cstate =
4999                         to_intel_crtc_state(cstate);
5000                 const struct skl_pipe_wm *old_pipe_wm =
5001                         &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
5002
5003                 pipe_wm = &intel_cstate->wm.skl.optimal;
5004                 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
5005                                          &results->ddb, &changed);
5006                 if (ret)
5007                         return ret;
5008
5009                 if (changed)
5010                         results->dirty_pipes |= drm_crtc_mask(crtc);
5011
5012                 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
5013                         /* This pipe's WM's did not change */
5014                         continue;
5015
5016                 intel_cstate->update_wm_pre = true;
5017         }
5018
5019         skl_print_wm_changes(state);
5020
5021         return 0;
5022 }
5023
5024 static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
5025                                       struct intel_crtc_state *cstate)
5026 {
5027         struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
5028         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5029         struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
5030         const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
5031         enum pipe pipe = crtc->pipe;
5032         enum plane_id plane_id;
5033
5034         if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
5035                 return;
5036
5037         I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
5038
5039         for_each_plane_id_on_crtc(crtc, plane_id) {
5040                 if (plane_id != PLANE_CURSOR)
5041                         skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id],
5042                                            ddb, plane_id);
5043                 else
5044                         skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id],
5045                                             ddb);
5046         }
5047 }
5048
5049 static void skl_initial_wm(struct intel_atomic_state *state,
5050                            struct intel_crtc_state *cstate)
5051 {
5052         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
5053         struct drm_device *dev = intel_crtc->base.dev;
5054         struct drm_i915_private *dev_priv = to_i915(dev);
5055         struct skl_wm_values *results = &state->wm_results;
5056         struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
5057         enum pipe pipe = intel_crtc->pipe;
5058
5059         if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
5060                 return;
5061
5062         mutex_lock(&dev_priv->wm.wm_mutex);
5063
5064         if (cstate->base.active_changed)
5065                 skl_atomic_update_crtc_wm(state, cstate);
5066
5067         skl_copy_wm_for_pipe(hw_vals, results, pipe);
5068
5069         mutex_unlock(&dev_priv->wm.wm_mutex);
5070 }
5071
5072 static void ilk_compute_wm_config(struct drm_device *dev,
5073                                   struct intel_wm_config *config)
5074 {
5075         struct intel_crtc *crtc;
5076
5077         /* Compute the currently _active_ config */
5078         for_each_intel_crtc(dev, crtc) {
5079                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
5080
5081                 if (!wm->pipe_enabled)
5082                         continue;
5083
5084                 config->sprites_enabled |= wm->sprites_enabled;
5085                 config->sprites_scaled |= wm->sprites_scaled;
5086                 config->num_pipes_active++;
5087         }
5088 }
5089
5090 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
5091 {
5092         struct drm_device *dev = &dev_priv->drm;
5093         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
5094         struct ilk_wm_maximums max;
5095         struct intel_wm_config config = {};
5096         struct ilk_wm_values results = {};
5097         enum intel_ddb_partitioning partitioning;
5098
5099         ilk_compute_wm_config(dev, &config);
5100
5101         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
5102         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
5103
5104         /* 5/6 split only in single pipe config on IVB+ */
5105         if (INTEL_GEN(dev_priv) >= 7 &&
5106             config.num_pipes_active == 1 && config.sprites_enabled) {
5107                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
5108                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
5109
5110                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
5111         } else {
5112                 best_lp_wm = &lp_wm_1_2;
5113         }
5114
5115         partitioning = (best_lp_wm == &lp_wm_1_2) ?
5116                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
5117
5118         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
5119
5120         ilk_write_wm_values(dev_priv, &results);
5121 }
5122
5123 static void ilk_initial_watermarks(struct intel_atomic_state *state,
5124                                    struct intel_crtc_state *cstate)
5125 {
5126         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
5127         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
5128
5129         mutex_lock(&dev_priv->wm.wm_mutex);
5130         intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
5131         ilk_program_watermarks(dev_priv);
5132         mutex_unlock(&dev_priv->wm.wm_mutex);
5133 }
5134
5135 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
5136                                     struct intel_crtc_state *cstate)
5137 {
5138         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
5139         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
5140
5141         mutex_lock(&dev_priv->wm.wm_mutex);
5142         if (cstate->wm.need_postvbl_update) {
5143                 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
5144                 ilk_program_watermarks(dev_priv);
5145         }
5146         mutex_unlock(&dev_priv->wm.wm_mutex);
5147 }
5148
5149 static inline void skl_wm_level_from_reg_val(uint32_t val,
5150                                              struct skl_wm_level *level)
5151 {
5152         level->plane_en = val & PLANE_WM_EN;
5153         level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
5154         level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
5155                 PLANE_WM_LINES_MASK;
5156 }
5157
5158 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
5159                               struct skl_pipe_wm *out)
5160 {
5161         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5163         enum pipe pipe = intel_crtc->pipe;
5164         int level, max_level;
5165         enum plane_id plane_id;
5166         uint32_t val;
5167
5168         max_level = ilk_wm_max_level(dev_priv);
5169
5170         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
5171                 struct skl_plane_wm *wm = &out->planes[plane_id];
5172
5173                 for (level = 0; level <= max_level; level++) {
5174                         if (plane_id != PLANE_CURSOR)
5175                                 val = I915_READ(PLANE_WM(pipe, plane_id, level));
5176                         else
5177                                 val = I915_READ(CUR_WM(pipe, level));
5178
5179                         skl_wm_level_from_reg_val(val, &wm->wm[level]);
5180                 }
5181
5182                 if (plane_id != PLANE_CURSOR)
5183                         val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
5184                 else
5185                         val = I915_READ(CUR_WM_TRANS(pipe));
5186
5187                 skl_wm_level_from_reg_val(val, &wm->trans_wm);
5188         }
5189
5190         if (!intel_crtc->active)
5191                 return;
5192
5193         out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
5194 }
5195
5196 void skl_wm_get_hw_state(struct drm_device *dev)
5197 {
5198         struct drm_i915_private *dev_priv = to_i915(dev);
5199         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
5200         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
5201         struct drm_crtc *crtc;
5202         struct intel_crtc *intel_crtc;
5203         struct intel_crtc_state *cstate;
5204
5205         skl_ddb_get_hw_state(dev_priv, ddb);
5206         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5207                 intel_crtc = to_intel_crtc(crtc);
5208                 cstate = to_intel_crtc_state(crtc->state);
5209
5210                 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
5211
5212                 if (intel_crtc->active)
5213                         hw->dirty_pipes |= drm_crtc_mask(crtc);
5214         }
5215
5216         if (dev_priv->active_crtcs) {
5217                 /* Fully recompute DDB on first atomic commit */
5218                 dev_priv->wm.distrust_bios_wm = true;
5219         } else {
5220                 /* Easy/common case; just sanitize DDB now if everything off */
5221                 memset(ddb, 0, sizeof(*ddb));
5222         }
5223 }
5224
5225 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
5226 {
5227         struct drm_device *dev = crtc->dev;
5228         struct drm_i915_private *dev_priv = to_i915(dev);
5229         struct ilk_wm_values *hw = &dev_priv->wm.hw;
5230         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5231         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
5232         struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
5233         enum pipe pipe = intel_crtc->pipe;
5234         static const i915_reg_t wm0_pipe_reg[] = {
5235                 [PIPE_A] = WM0_PIPEA_ILK,
5236                 [PIPE_B] = WM0_PIPEB_ILK,
5237                 [PIPE_C] = WM0_PIPEC_IVB,
5238         };
5239
5240         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
5241         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5242                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
5243
5244         memset(active, 0, sizeof(*active));
5245
5246         active->pipe_enabled = intel_crtc->active;
5247
5248         if (active->pipe_enabled) {
5249                 u32 tmp = hw->wm_pipe[pipe];
5250
5251                 /*
5252                  * For active pipes LP0 watermark is marked as
5253                  * enabled, and LP1+ watermaks as disabled since
5254                  * we can't really reverse compute them in case
5255                  * multiple pipes are active.
5256                  */
5257                 active->wm[0].enable = true;
5258                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
5259                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
5260                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
5261                 active->linetime = hw->wm_linetime[pipe];
5262         } else {
5263                 int level, max_level = ilk_wm_max_level(dev_priv);
5264
5265                 /*
5266                  * For inactive pipes, all watermark levels
5267                  * should be marked as enabled but zeroed,
5268                  * which is what we'd compute them to.
5269                  */
5270                 for (level = 0; level <= max_level; level++)
5271                         active->wm[level].enable = true;
5272         }
5273
5274         intel_crtc->wm.active.ilk = *active;
5275 }
5276
5277 #define _FW_WM(value, plane) \
5278         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
5279 #define _FW_WM_VLV(value, plane) \
5280         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
5281
5282 static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
5283                                struct g4x_wm_values *wm)
5284 {
5285         uint32_t tmp;
5286
5287         tmp = I915_READ(DSPFW1);
5288         wm->sr.plane = _FW_WM(tmp, SR);
5289         wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
5290         wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
5291         wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
5292
5293         tmp = I915_READ(DSPFW2);
5294         wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
5295         wm->sr.fbc = _FW_WM(tmp, FBC_SR);
5296         wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
5297         wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);
5298         wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
5299         wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
5300
5301         tmp = I915_READ(DSPFW3);
5302         wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
5303         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
5304         wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
5305         wm->hpll.plane = _FW_WM(tmp, HPLL_SR);
5306 }
5307
5308 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
5309                                struct vlv_wm_values *wm)
5310 {
5311         enum pipe pipe;
5312         uint32_t tmp;
5313
5314         for_each_pipe(dev_priv, pipe) {
5315                 tmp = I915_READ(VLV_DDL(pipe));
5316
5317                 wm->ddl[pipe].plane[PLANE_PRIMARY] =
5318                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5319                 wm->ddl[pipe].plane[PLANE_CURSOR] =
5320                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5321                 wm->ddl[pipe].plane[PLANE_SPRITE0] =
5322                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5323                 wm->ddl[pipe].plane[PLANE_SPRITE1] =
5324                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5325         }
5326
5327         tmp = I915_READ(DSPFW1);
5328         wm->sr.plane = _FW_WM(tmp, SR);
5329         wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
5330         wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
5331         wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
5332
5333         tmp = I915_READ(DSPFW2);
5334         wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
5335         wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
5336         wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
5337
5338         tmp = I915_READ(DSPFW3);
5339         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
5340
5341         if (IS_CHERRYVIEW(dev_priv)) {
5342                 tmp = I915_READ(DSPFW7_CHV);
5343                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
5344                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
5345
5346                 tmp = I915_READ(DSPFW8_CHV);
5347                 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
5348                 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
5349
5350                 tmp = I915_READ(DSPFW9_CHV);
5351                 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
5352                 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
5353
5354                 tmp = I915_READ(DSPHOWM);
5355                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
5356                 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
5357                 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
5358                 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
5359                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
5360                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
5361                 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
5362                 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
5363                 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
5364                 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
5365         } else {
5366                 tmp = I915_READ(DSPFW7);
5367                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
5368                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
5369
5370                 tmp = I915_READ(DSPHOWM);
5371                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
5372                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
5373                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
5374                 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
5375                 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
5376                 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
5377                 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
5378         }
5379 }
5380
5381 #undef _FW_WM
5382 #undef _FW_WM_VLV
5383
5384 void g4x_wm_get_hw_state(struct drm_device *dev)
5385 {
5386         struct drm_i915_private *dev_priv = to_i915(dev);
5387         struct g4x_wm_values *wm = &dev_priv->wm.g4x;
5388         struct intel_crtc *crtc;
5389
5390         g4x_read_wm_values(dev_priv, wm);
5391
5392         wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
5393
5394         for_each_intel_crtc(dev, crtc) {
5395                 struct intel_crtc_state *crtc_state =
5396                         to_intel_crtc_state(crtc->base.state);
5397                 struct g4x_wm_state *active = &crtc->wm.active.g4x;
5398                 struct g4x_pipe_wm *raw;
5399                 enum pipe pipe = crtc->pipe;
5400                 enum plane_id plane_id;
5401                 int level, max_level;
5402
5403                 active->cxsr = wm->cxsr;
5404                 active->hpll_en = wm->hpll_en;
5405                 active->fbc_en = wm->fbc_en;
5406
5407                 active->sr = wm->sr;
5408                 active->hpll = wm->hpll;
5409
5410                 for_each_plane_id_on_crtc(crtc, plane_id) {
5411                         active->wm.plane[plane_id] =
5412                                 wm->pipe[pipe].plane[plane_id];
5413                 }
5414
5415                 if (wm->cxsr && wm->hpll_en)
5416                         max_level = G4X_WM_LEVEL_HPLL;
5417                 else if (wm->cxsr)
5418                         max_level = G4X_WM_LEVEL_SR;
5419                 else
5420                         max_level = G4X_WM_LEVEL_NORMAL;
5421
5422                 level = G4X_WM_LEVEL_NORMAL;
5423                 raw = &crtc_state->wm.g4x.raw[level];
5424                 for_each_plane_id_on_crtc(crtc, plane_id)
5425                         raw->plane[plane_id] = active->wm.plane[plane_id];
5426
5427                 if (++level > max_level)
5428                         goto out;
5429
5430                 raw = &crtc_state->wm.g4x.raw[level];
5431                 raw->plane[PLANE_PRIMARY] = active->sr.plane;
5432                 raw->plane[PLANE_CURSOR] = active->sr.cursor;
5433                 raw->plane[PLANE_SPRITE0] = 0;
5434                 raw->fbc = active->sr.fbc;
5435
5436                 if (++level > max_level)
5437                         goto out;
5438
5439                 raw = &crtc_state->wm.g4x.raw[level];
5440                 raw->plane[PLANE_PRIMARY] = active->hpll.plane;
5441                 raw->plane[PLANE_CURSOR] = active->hpll.cursor;
5442                 raw->plane[PLANE_SPRITE0] = 0;
5443                 raw->fbc = active->hpll.fbc;
5444
5445         out:
5446                 for_each_plane_id_on_crtc(crtc, plane_id)
5447                         g4x_raw_plane_wm_set(crtc_state, level,
5448                                              plane_id, USHRT_MAX);
5449                 g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
5450
5451                 crtc_state->wm.g4x.optimal = *active;
5452                 crtc_state->wm.g4x.intermediate = *active;
5453
5454                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n",
5455                               pipe_name(pipe),
5456                               wm->pipe[pipe].plane[PLANE_PRIMARY],
5457                               wm->pipe[pipe].plane[PLANE_CURSOR],
5458                               wm->pipe[pipe].plane[PLANE_SPRITE0]);
5459         }
5460
5461         DRM_DEBUG_KMS("Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n",
5462                       wm->sr.plane, wm->sr.cursor, wm->sr.fbc);
5463         DRM_DEBUG_KMS("Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n",
5464                       wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc);
5465         DRM_DEBUG_KMS("Initial SR=%s HPLL=%s FBC=%s\n",
5466                       yesno(wm->cxsr), yesno(wm->hpll_en), yesno(wm->fbc_en));
5467 }
5468
5469 void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
5470 {
5471         struct intel_plane *plane;
5472         struct intel_crtc *crtc;
5473
5474         mutex_lock(&dev_priv->wm.wm_mutex);
5475
5476         for_each_intel_plane(&dev_priv->drm, plane) {
5477                 struct intel_crtc *crtc =
5478                         intel_get_crtc_for_pipe(dev_priv, plane->pipe);
5479                 struct intel_crtc_state *crtc_state =
5480                         to_intel_crtc_state(crtc->base.state);
5481                 struct intel_plane_state *plane_state =
5482                         to_intel_plane_state(plane->base.state);
5483                 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
5484                 enum plane_id plane_id = plane->id;
5485                 int level;
5486
5487                 if (plane_state->base.visible)
5488                         continue;
5489
5490                 for (level = 0; level < 3; level++) {
5491                         struct g4x_pipe_wm *raw =
5492                                 &crtc_state->wm.g4x.raw[level];
5493
5494                         raw->plane[plane_id] = 0;
5495                         wm_state->wm.plane[plane_id] = 0;
5496                 }
5497
5498                 if (plane_id == PLANE_PRIMARY) {
5499                         for (level = 0; level < 3; level++) {
5500                                 struct g4x_pipe_wm *raw =
5501                                         &crtc_state->wm.g4x.raw[level];
5502                                 raw->fbc = 0;
5503                         }
5504
5505                         wm_state->sr.fbc = 0;
5506                         wm_state->hpll.fbc = 0;
5507                         wm_state->fbc_en = false;
5508                 }
5509         }
5510
5511         for_each_intel_crtc(&dev_priv->drm, crtc) {
5512                 struct intel_crtc_state *crtc_state =
5513                         to_intel_crtc_state(crtc->base.state);
5514
5515                 crtc_state->wm.g4x.intermediate =
5516                         crtc_state->wm.g4x.optimal;
5517                 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
5518         }
5519
5520         g4x_program_watermarks(dev_priv);
5521
5522         mutex_unlock(&dev_priv->wm.wm_mutex);
5523 }
5524
5525 void vlv_wm_get_hw_state(struct drm_device *dev)
5526 {
5527         struct drm_i915_private *dev_priv = to_i915(dev);
5528         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
5529         struct intel_crtc *crtc;
5530         u32 val;
5531
5532         vlv_read_wm_values(dev_priv, wm);
5533
5534         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
5535         wm->level = VLV_WM_LEVEL_PM2;
5536
5537         if (IS_CHERRYVIEW(dev_priv)) {
5538                 mutex_lock(&dev_priv->rps.hw_lock);
5539
5540                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5541                 if (val & DSP_MAXFIFO_PM5_ENABLE)
5542                         wm->level = VLV_WM_LEVEL_PM5;
5543
5544                 /*
5545                  * If DDR DVFS is disabled in the BIOS, Punit
5546                  * will never ack the request. So if that happens
5547                  * assume we don't have to enable/disable DDR DVFS
5548                  * dynamically. To test that just set the REQ_ACK
5549                  * bit to poke the Punit, but don't change the
5550                  * HIGH/LOW bits so that we don't actually change
5551                  * the current state.
5552                  */
5553                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
5554                 val |= FORCE_DDR_FREQ_REQ_ACK;
5555                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
5556
5557                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
5558                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
5559                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
5560                                       "assuming DDR DVFS is disabled\n");
5561                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
5562                 } else {
5563                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
5564                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
5565                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
5566                 }
5567
5568                 mutex_unlock(&dev_priv->rps.hw_lock);
5569         }
5570
5571         for_each_intel_crtc(dev, crtc) {
5572                 struct intel_crtc_state *crtc_state =
5573                         to_intel_crtc_state(crtc->base.state);
5574                 struct vlv_wm_state *active = &crtc->wm.active.vlv;
5575                 const struct vlv_fifo_state *fifo_state =
5576                         &crtc_state->wm.vlv.fifo_state;
5577                 enum pipe pipe = crtc->pipe;
5578                 enum plane_id plane_id;
5579                 int level;
5580
5581                 vlv_get_fifo_size(crtc_state);
5582
5583                 active->num_levels = wm->level + 1;
5584                 active->cxsr = wm->cxsr;
5585
5586                 for (level = 0; level < active->num_levels; level++) {
5587                         struct g4x_pipe_wm *raw =
5588                                 &crtc_state->wm.vlv.raw[level];
5589
5590                         active->sr[level].plane = wm->sr.plane;
5591                         active->sr[level].cursor = wm->sr.cursor;
5592
5593                         for_each_plane_id_on_crtc(crtc, plane_id) {
5594                                 active->wm[level].plane[plane_id] =
5595                                         wm->pipe[pipe].plane[plane_id];
5596
5597                                 raw->plane[plane_id] =
5598                                         vlv_invert_wm_value(active->wm[level].plane[plane_id],
5599                                                             fifo_state->plane[plane_id]);
5600                         }
5601                 }
5602
5603                 for_each_plane_id_on_crtc(crtc, plane_id)
5604                         vlv_raw_plane_wm_set(crtc_state, level,
5605                                              plane_id, USHRT_MAX);
5606                 vlv_invalidate_wms(crtc, active, level);
5607
5608                 crtc_state->wm.vlv.optimal = *active;
5609                 crtc_state->wm.vlv.intermediate = *active;
5610
5611                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
5612                               pipe_name(pipe),
5613                               wm->pipe[pipe].plane[PLANE_PRIMARY],
5614                               wm->pipe[pipe].plane[PLANE_CURSOR],
5615                               wm->pipe[pipe].plane[PLANE_SPRITE0],
5616                               wm->pipe[pipe].plane[PLANE_SPRITE1]);
5617         }
5618
5619         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
5620                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
5621 }
5622
5623 void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
5624 {
5625         struct intel_plane *plane;
5626         struct intel_crtc *crtc;
5627
5628         mutex_lock(&dev_priv->wm.wm_mutex);
5629
5630         for_each_intel_plane(&dev_priv->drm, plane) {
5631                 struct intel_crtc *crtc =
5632                         intel_get_crtc_for_pipe(dev_priv, plane->pipe);
5633                 struct intel_crtc_state *crtc_state =
5634                         to_intel_crtc_state(crtc->base.state);
5635                 struct intel_plane_state *plane_state =
5636                         to_intel_plane_state(plane->base.state);
5637                 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
5638                 const struct vlv_fifo_state *fifo_state =
5639                         &crtc_state->wm.vlv.fifo_state;
5640                 enum plane_id plane_id = plane->id;
5641                 int level;
5642
5643                 if (plane_state->base.visible)
5644                         continue;
5645
5646                 for (level = 0; level < wm_state->num_levels; level++) {
5647                         struct g4x_pipe_wm *raw =
5648                                 &crtc_state->wm.vlv.raw[level];
5649
5650                         raw->plane[plane_id] = 0;
5651
5652                         wm_state->wm[level].plane[plane_id] =
5653                                 vlv_invert_wm_value(raw->plane[plane_id],
5654                                                     fifo_state->plane[plane_id]);
5655                 }
5656         }
5657
5658         for_each_intel_crtc(&dev_priv->drm, crtc) {
5659                 struct intel_crtc_state *crtc_state =
5660                         to_intel_crtc_state(crtc->base.state);
5661
5662                 crtc_state->wm.vlv.intermediate =
5663                         crtc_state->wm.vlv.optimal;
5664                 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
5665         }
5666
5667         vlv_program_watermarks(dev_priv);
5668
5669         mutex_unlock(&dev_priv->wm.wm_mutex);
5670 }
5671
5672 void ilk_wm_get_hw_state(struct drm_device *dev)
5673 {
5674         struct drm_i915_private *dev_priv = to_i915(dev);
5675         struct ilk_wm_values *hw = &dev_priv->wm.hw;
5676         struct drm_crtc *crtc;
5677
5678         for_each_crtc(dev, crtc)
5679                 ilk_pipe_wm_get_hw_state(crtc);
5680
5681         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
5682         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
5683         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
5684
5685         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
5686         if (INTEL_GEN(dev_priv) >= 7) {
5687                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
5688                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
5689         }
5690
5691         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5692                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
5693                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
5694         else if (IS_IVYBRIDGE(dev_priv))
5695                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
5696                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
5697
5698         hw->enable_fbc_wm =
5699                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
5700 }
5701
5702 /**
5703  * intel_update_watermarks - update FIFO watermark values based on current modes
5704  *
5705  * Calculate watermark values for the various WM regs based on current mode
5706  * and plane configuration.
5707  *
5708  * There are several cases to deal with here:
5709  *   - normal (i.e. non-self-refresh)
5710  *   - self-refresh (SR) mode
5711  *   - lines are large relative to FIFO size (buffer can hold up to 2)
5712  *   - lines are small relative to FIFO size (buffer can hold more than 2
5713  *     lines), so need to account for TLB latency
5714  *
5715  *   The normal calculation is:
5716  *     watermark = dotclock * bytes per pixel * latency
5717  *   where latency is platform & configuration dependent (we assume pessimal
5718  *   values here).
5719  *
5720  *   The SR calculation is:
5721  *     watermark = (trunc(latency/line time)+1) * surface width *
5722  *       bytes per pixel
5723  *   where
5724  *     line time = htotal / dotclock
5725  *     surface width = hdisplay for normal plane and 64 for cursor
5726  *   and latency is assumed to be high, as above.
5727  *
5728  * The final value programmed to the register should always be rounded up,
5729  * and include an extra 2 entries to account for clock crossings.
5730  *
5731  * We don't use the sprite, so we can ignore that.  And on Crestline we have
5732  * to set the non-SR watermarks to 8.
5733  */
5734 void intel_update_watermarks(struct intel_crtc *crtc)
5735 {
5736         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5737
5738         if (dev_priv->display.update_wm)
5739                 dev_priv->display.update_wm(crtc);
5740 }
5741
5742 /*
5743  * Lock protecting IPS related data structures
5744  */
5745 DEFINE_SPINLOCK(mchdev_lock);
5746
5747 /* Global for IPS driver to get at the current i915 device. Protected by
5748  * mchdev_lock. */
5749 static struct drm_i915_private *i915_mch_dev;
5750
5751 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
5752 {
5753         u16 rgvswctl;
5754
5755         lockdep_assert_held(&mchdev_lock);
5756
5757         rgvswctl = I915_READ16(MEMSWCTL);
5758         if (rgvswctl & MEMCTL_CMD_STS) {
5759                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5760                 return false; /* still busy with another command */
5761         }
5762
5763         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5764                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5765         I915_WRITE16(MEMSWCTL, rgvswctl);
5766         POSTING_READ16(MEMSWCTL);
5767
5768         rgvswctl |= MEMCTL_CMD_STS;
5769         I915_WRITE16(MEMSWCTL, rgvswctl);
5770
5771         return true;
5772 }
5773
5774 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
5775 {
5776         u32 rgvmodectl;
5777         u8 fmax, fmin, fstart, vstart;
5778
5779         spin_lock_irq(&mchdev_lock);
5780
5781         rgvmodectl = I915_READ(MEMMODECTL);
5782
5783         /* Enable temp reporting */
5784         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5785         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5786
5787         /* 100ms RC evaluation intervals */
5788         I915_WRITE(RCUPEI, 100000);
5789         I915_WRITE(RCDNEI, 100000);
5790
5791         /* Set max/min thresholds to 90ms and 80ms respectively */
5792         I915_WRITE(RCBMAXAVG, 90000);
5793         I915_WRITE(RCBMINAVG, 80000);
5794
5795         I915_WRITE(MEMIHYST, 1);
5796
5797         /* Set up min, max, and cur for interrupt handling */
5798         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5799         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5800         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5801                 MEMMODE_FSTART_SHIFT;
5802
5803         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
5804                 PXVFREQ_PX_SHIFT;
5805
5806         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
5807         dev_priv->ips.fstart = fstart;
5808
5809         dev_priv->ips.max_delay = fstart;
5810         dev_priv->ips.min_delay = fmin;
5811         dev_priv->ips.cur_delay = fstart;
5812
5813         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5814                          fmax, fmin, fstart);
5815
5816         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5817
5818         /*
5819          * Interrupts will be enabled in ironlake_irq_postinstall
5820          */
5821
5822         I915_WRITE(VIDSTART, vstart);
5823         POSTING_READ(VIDSTART);
5824
5825         rgvmodectl |= MEMMODE_SWMODE_EN;
5826         I915_WRITE(MEMMODECTL, rgvmodectl);
5827
5828         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5829                 DRM_ERROR("stuck trying to change perf mode\n");
5830         mdelay(1);
5831
5832         ironlake_set_drps(dev_priv, fstart);
5833
5834         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
5835                 I915_READ(DDREC) + I915_READ(CSIEC);
5836         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
5837         dev_priv->ips.last_count2 = I915_READ(GFXEC);
5838         dev_priv->ips.last_time2 = ktime_get_raw_ns();
5839
5840         spin_unlock_irq(&mchdev_lock);
5841 }
5842
5843 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
5844 {
5845         u16 rgvswctl;
5846
5847         spin_lock_irq(&mchdev_lock);
5848
5849         rgvswctl = I915_READ16(MEMSWCTL);
5850
5851         /* Ack interrupts, disable EFC interrupt */
5852         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5853         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5854         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5855         I915_WRITE(DEIIR, DE_PCU_EVENT);
5856         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5857
5858         /* Go back to the starting frequency */
5859         ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
5860         mdelay(1);
5861         rgvswctl |= MEMCTL_CMD_STS;
5862         I915_WRITE(MEMSWCTL, rgvswctl);
5863         mdelay(1);
5864
5865         spin_unlock_irq(&mchdev_lock);
5866 }
5867
5868 /* There's a funny hw issue where the hw returns all 0 when reading from
5869  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
5870  * ourselves, instead of doing a rmw cycle (which might result in us clearing
5871  * all limits and the gpu stuck at whatever frequency it is at atm).
5872  */
5873 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
5874 {
5875         u32 limits;
5876
5877         /* Only set the down limit when we've reached the lowest level to avoid
5878          * getting more interrupts, otherwise leave this clear. This prevents a
5879          * race in the hw when coming out of rc6: There's a tiny window where
5880          * the hw runs at the minimal clock before selecting the desired
5881          * frequency, if the down threshold expires in that window we will not
5882          * receive a down interrupt. */
5883         if (INTEL_GEN(dev_priv) >= 9) {
5884                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
5885                 if (val <= dev_priv->rps.min_freq_softlimit)
5886                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
5887         } else {
5888                 limits = dev_priv->rps.max_freq_softlimit << 24;
5889                 if (val <= dev_priv->rps.min_freq_softlimit)
5890                         limits |= dev_priv->rps.min_freq_softlimit << 16;
5891         }
5892
5893         return limits;
5894 }
5895
5896 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
5897 {
5898         int new_power;
5899         u32 threshold_up = 0, threshold_down = 0; /* in % */
5900         u32 ei_up = 0, ei_down = 0;
5901
5902         new_power = dev_priv->rps.power;
5903         switch (dev_priv->rps.power) {
5904         case LOW_POWER:
5905                 if (val > dev_priv->rps.efficient_freq + 1 &&
5906                     val > dev_priv->rps.cur_freq)
5907                         new_power = BETWEEN;
5908                 break;
5909
5910         case BETWEEN:
5911                 if (val <= dev_priv->rps.efficient_freq &&
5912                     val < dev_priv->rps.cur_freq)
5913                         new_power = LOW_POWER;
5914                 else if (val >= dev_priv->rps.rp0_freq &&
5915                          val > dev_priv->rps.cur_freq)
5916                         new_power = HIGH_POWER;
5917                 break;
5918
5919         case HIGH_POWER:
5920                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
5921                     val < dev_priv->rps.cur_freq)
5922                         new_power = BETWEEN;
5923                 break;
5924         }
5925         /* Max/min bins are special */
5926         if (val <= dev_priv->rps.min_freq_softlimit)
5927                 new_power = LOW_POWER;
5928         if (val >= dev_priv->rps.max_freq_softlimit)
5929                 new_power = HIGH_POWER;
5930         if (new_power == dev_priv->rps.power)
5931                 return;
5932
5933         /* Note the units here are not exactly 1us, but 1280ns. */
5934         switch (new_power) {
5935         case LOW_POWER:
5936                 /* Upclock if more than 95% busy over 16ms */
5937                 ei_up = 16000;
5938                 threshold_up = 95;
5939
5940                 /* Downclock if less than 85% busy over 32ms */
5941                 ei_down = 32000;
5942                 threshold_down = 85;
5943                 break;
5944
5945         case BETWEEN:
5946                 /* Upclock if more than 90% busy over 13ms */
5947                 ei_up = 13000;
5948                 threshold_up = 90;
5949
5950                 /* Downclock if less than 75% busy over 32ms */
5951                 ei_down = 32000;
5952                 threshold_down = 75;
5953                 break;
5954
5955         case HIGH_POWER:
5956                 /* Upclock if more than 85% busy over 10ms */
5957                 ei_up = 10000;
5958                 threshold_up = 85;
5959
5960                 /* Downclock if less than 60% busy over 32ms */
5961                 ei_down = 32000;
5962                 threshold_down = 60;
5963                 break;
5964         }
5965
5966         /* When byt can survive without system hang with dynamic
5967          * sw freq adjustments, this restriction can be lifted.
5968          */
5969         if (IS_VALLEYVIEW(dev_priv))
5970                 goto skip_hw_write;
5971
5972         I915_WRITE(GEN6_RP_UP_EI,
5973                    GT_INTERVAL_FROM_US(dev_priv, ei_up));
5974         I915_WRITE(GEN6_RP_UP_THRESHOLD,
5975                    GT_INTERVAL_FROM_US(dev_priv,
5976                                        ei_up * threshold_up / 100));
5977
5978         I915_WRITE(GEN6_RP_DOWN_EI,
5979                    GT_INTERVAL_FROM_US(dev_priv, ei_down));
5980         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
5981                    GT_INTERVAL_FROM_US(dev_priv,
5982                                        ei_down * threshold_down / 100));
5983
5984         I915_WRITE(GEN6_RP_CONTROL,
5985                    GEN6_RP_MEDIA_TURBO |
5986                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5987                    GEN6_RP_MEDIA_IS_GFX |
5988                    GEN6_RP_ENABLE |
5989                    GEN6_RP_UP_BUSY_AVG |
5990                    GEN6_RP_DOWN_IDLE_AVG);
5991
5992 skip_hw_write:
5993         dev_priv->rps.power = new_power;
5994         dev_priv->rps.up_threshold = threshold_up;
5995         dev_priv->rps.down_threshold = threshold_down;
5996         dev_priv->rps.last_adj = 0;
5997 }
5998
5999 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
6000 {
6001         u32 mask = 0;
6002
6003         /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
6004         if (val > dev_priv->rps.min_freq_softlimit)
6005                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
6006         if (val < dev_priv->rps.max_freq_softlimit)
6007                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
6008
6009         mask &= dev_priv->pm_rps_events;
6010
6011         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
6012 }
6013
6014 /* gen6_set_rps is called to update the frequency request, but should also be
6015  * called when the range (min_delay and max_delay) is modified so that we can
6016  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
6017 static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
6018 {
6019         /* min/max delay may still have been modified so be sure to
6020          * write the limits value.
6021          */
6022         if (val != dev_priv->rps.cur_freq) {
6023                 gen6_set_rps_thresholds(dev_priv, val);
6024
6025                 if (INTEL_GEN(dev_priv) >= 9)
6026                         I915_WRITE(GEN6_RPNSWREQ,
6027                                    GEN9_FREQUENCY(val));
6028                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6029                         I915_WRITE(GEN6_RPNSWREQ,
6030                                    HSW_FREQUENCY(val));
6031                 else
6032                         I915_WRITE(GEN6_RPNSWREQ,
6033                                    GEN6_FREQUENCY(val) |
6034                                    GEN6_OFFSET(0) |
6035                                    GEN6_AGGRESSIVE_TURBO);
6036         }
6037
6038         /* Make sure we continue to get interrupts
6039          * until we hit the minimum or maximum frequencies.
6040          */
6041         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
6042         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
6043
6044         dev_priv->rps.cur_freq = val;
6045         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
6046
6047         return 0;
6048 }
6049
6050 static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
6051 {
6052         int err;
6053
6054         if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
6055                       "Odd GPU freq value\n"))
6056                 val &= ~1;
6057
6058         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
6059
6060         if (val != dev_priv->rps.cur_freq) {
6061                 err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
6062                 if (err)
6063                         return err;
6064
6065                 gen6_set_rps_thresholds(dev_priv, val);
6066         }
6067
6068         dev_priv->rps.cur_freq = val;
6069         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
6070
6071         return 0;
6072 }
6073
6074 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
6075  *
6076  * * If Gfx is Idle, then
6077  * 1. Forcewake Media well.
6078  * 2. Request idle freq.
6079  * 3. Release Forcewake of Media well.
6080 */
6081 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
6082 {
6083         u32 val = dev_priv->rps.idle_freq;
6084         int err;
6085
6086         if (dev_priv->rps.cur_freq <= val)
6087                 return;
6088
6089         /* The punit delays the write of the frequency and voltage until it
6090          * determines the GPU is awake. During normal usage we don't want to
6091          * waste power changing the frequency if the GPU is sleeping (rc6).
6092          * However, the GPU and driver is now idle and we do not want to delay
6093          * switching to minimum voltage (reducing power whilst idle) as we do
6094          * not expect to be woken in the near future and so must flush the
6095          * change by waking the device.
6096          *
6097          * We choose to take the media powerwell (either would do to trick the
6098          * punit into committing the voltage change) as that takes a lot less
6099          * power than the render powerwell.
6100          */
6101         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
6102         err = valleyview_set_rps(dev_priv, val);
6103         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
6104
6105         if (err)
6106                 DRM_ERROR("Failed to set RPS for idle\n");
6107 }
6108
6109 void gen6_rps_busy(struct drm_i915_private *dev_priv)
6110 {
6111         mutex_lock(&dev_priv->rps.hw_lock);
6112         if (dev_priv->rps.enabled) {
6113                 u8 freq;
6114
6115                 if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED)
6116                         gen6_rps_reset_ei(dev_priv);
6117                 I915_WRITE(GEN6_PMINTRMSK,
6118                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
6119
6120                 gen6_enable_rps_interrupts(dev_priv);
6121
6122                 /* Use the user's desired frequency as a guide, but for better
6123                  * performance, jump directly to RPe as our starting frequency.
6124                  */
6125                 freq = max(dev_priv->rps.cur_freq,
6126                            dev_priv->rps.efficient_freq);
6127
6128                 if (intel_set_rps(dev_priv,
6129                                   clamp(freq,
6130                                         dev_priv->rps.min_freq_softlimit,
6131                                         dev_priv->rps.max_freq_softlimit)))
6132                         DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
6133         }
6134         mutex_unlock(&dev_priv->rps.hw_lock);
6135 }
6136
6137 void gen6_rps_idle(struct drm_i915_private *dev_priv)
6138 {
6139         /* Flush our bottom-half so that it does not race with us
6140          * setting the idle frequency and so that it is bounded by
6141          * our rpm wakeref. And then disable the interrupts to stop any
6142          * futher RPS reclocking whilst we are asleep.
6143          */
6144         gen6_disable_rps_interrupts(dev_priv);
6145
6146         mutex_lock(&dev_priv->rps.hw_lock);
6147         if (dev_priv->rps.enabled) {
6148                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6149                         vlv_set_rps_idle(dev_priv);
6150                 else
6151                         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
6152                 dev_priv->rps.last_adj = 0;
6153                 I915_WRITE(GEN6_PMINTRMSK,
6154                            gen6_sanitize_rps_pm_mask(dev_priv, ~0));
6155         }
6156         mutex_unlock(&dev_priv->rps.hw_lock);
6157 }
6158
6159 void gen6_rps_boost(struct drm_i915_gem_request *rq,
6160                     struct intel_rps_client *rps)
6161 {
6162         struct drm_i915_private *i915 = rq->i915;
6163         bool boost;
6164
6165         /* This is intentionally racy! We peek at the state here, then
6166          * validate inside the RPS worker.
6167          */
6168         if (!i915->rps.enabled)
6169                 return;
6170
6171         boost = false;
6172         spin_lock_irq(&rq->lock);
6173         if (!rq->waitboost && !i915_gem_request_completed(rq)) {
6174                 atomic_inc(&i915->rps.num_waiters);
6175                 rq->waitboost = true;
6176                 boost = true;
6177         }
6178         spin_unlock_irq(&rq->lock);
6179         if (!boost)
6180                 return;
6181
6182         if (READ_ONCE(i915->rps.cur_freq) < i915->rps.boost_freq)
6183                 schedule_work(&i915->rps.work);
6184
6185         atomic_inc(rps ? &rps->boosts : &i915->rps.boosts);
6186 }
6187
6188 int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
6189 {
6190         int err;
6191
6192         lockdep_assert_held(&dev_priv->rps.hw_lock);
6193         GEM_BUG_ON(val > dev_priv->rps.max_freq);
6194         GEM_BUG_ON(val < dev_priv->rps.min_freq);
6195
6196         if (!dev_priv->rps.enabled) {
6197                 dev_priv->rps.cur_freq = val;
6198                 return 0;
6199         }
6200
6201         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6202                 err = valleyview_set_rps(dev_priv, val);
6203         else
6204                 err = gen6_set_rps(dev_priv, val);
6205
6206         return err;
6207 }
6208
6209 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
6210 {
6211         I915_WRITE(GEN6_RC_CONTROL, 0);
6212         I915_WRITE(GEN9_PG_ENABLE, 0);
6213 }
6214
6215 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
6216 {
6217         I915_WRITE(GEN6_RP_CONTROL, 0);
6218 }
6219
6220 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
6221 {
6222         I915_WRITE(GEN6_RC_CONTROL, 0);
6223         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6224         I915_WRITE(GEN6_RP_CONTROL, 0);
6225 }
6226
6227 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
6228 {
6229         I915_WRITE(GEN6_RC_CONTROL, 0);
6230 }
6231
6232 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
6233 {
6234         /* we're doing forcewake before Disabling RC6,
6235          * This what the BIOS expects when going into suspend */
6236         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6237
6238         I915_WRITE(GEN6_RC_CONTROL, 0);
6239
6240         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6241 }
6242
6243 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
6244 {
6245         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6246                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
6247                         mode = GEN6_RC_CTL_RC6_ENABLE;
6248                 else
6249                         mode = 0;
6250         }
6251         if (HAS_RC6p(dev_priv))
6252                 DRM_DEBUG_DRIVER("Enabling RC6 states: "
6253                                  "RC6 %s RC6p %s RC6pp %s\n",
6254                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
6255                                  onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
6256                                  onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
6257
6258         else
6259                 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
6260                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
6261 }
6262
6263 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
6264 {
6265         struct i915_ggtt *ggtt = &dev_priv->ggtt;
6266         bool enable_rc6 = true;
6267         unsigned long rc6_ctx_base;
6268         u32 rc_ctl;
6269         int rc_sw_target;
6270
6271         rc_ctl = I915_READ(GEN6_RC_CONTROL);
6272         rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
6273                        RC_SW_TARGET_STATE_SHIFT;
6274         DRM_DEBUG_DRIVER("BIOS enabled RC states: "
6275                          "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
6276                          onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
6277                          onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
6278                          rc_sw_target);
6279
6280         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
6281                 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
6282                 enable_rc6 = false;
6283         }
6284
6285         /*
6286          * The exact context size is not known for BXT, so assume a page size
6287          * for this check.
6288          */
6289         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
6290         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
6291               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
6292                                         ggtt->stolen_reserved_size))) {
6293                 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
6294                 enable_rc6 = false;
6295         }
6296
6297         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
6298               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
6299               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
6300               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
6301                 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
6302                 enable_rc6 = false;
6303         }
6304
6305         if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
6306             !I915_READ(GEN8_PUSHBUS_ENABLE) ||
6307             !I915_READ(GEN8_PUSHBUS_SHIFT)) {
6308                 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
6309                 enable_rc6 = false;
6310         }
6311
6312         if (!I915_READ(GEN6_GFXPAUSE)) {
6313                 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
6314                 enable_rc6 = false;
6315         }
6316
6317         if (!I915_READ(GEN8_MISC_CTRL0)) {
6318                 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
6319                 enable_rc6 = false;
6320         }
6321
6322         return enable_rc6;
6323 }
6324
6325 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
6326 {
6327         /* No RC6 before Ironlake and code is gone for ilk. */
6328         if (INTEL_INFO(dev_priv)->gen < 6)
6329                 return 0;
6330
6331         if (!enable_rc6)
6332                 return 0;
6333
6334         if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
6335                 DRM_INFO("RC6 disabled by BIOS\n");
6336                 return 0;
6337         }
6338
6339         /* Respect the kernel parameter if it is set */
6340         if (enable_rc6 >= 0) {
6341                 int mask;
6342
6343                 if (HAS_RC6p(dev_priv))
6344                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
6345                                INTEL_RC6pp_ENABLE;
6346                 else
6347                         mask = INTEL_RC6_ENABLE;
6348
6349                 if ((enable_rc6 & mask) != enable_rc6)
6350                         DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
6351                                          "(requested %d, valid %d)\n",
6352                                          enable_rc6 & mask, enable_rc6, mask);
6353
6354                 return enable_rc6 & mask;
6355         }
6356
6357         if (IS_IVYBRIDGE(dev_priv))
6358                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
6359
6360         return INTEL_RC6_ENABLE;
6361 }
6362
6363 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
6364 {
6365         /* All of these values are in units of 50MHz */
6366
6367         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
6368         if (IS_GEN9_LP(dev_priv)) {
6369                 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
6370                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
6371                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
6372                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
6373         } else {
6374                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6375                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
6376                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
6377                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
6378         }
6379         /* hw_max = RP0 until we check for overclocking */
6380         dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
6381
6382         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
6383         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
6384             IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
6385                 u32 ddcc_status = 0;
6386
6387                 if (sandybridge_pcode_read(dev_priv,
6388                                            HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
6389                                            &ddcc_status) == 0)
6390                         dev_priv->rps.efficient_freq =
6391                                 clamp_t(u8,
6392                                         ((ddcc_status >> 8) & 0xff),
6393                                         dev_priv->rps.min_freq,
6394                                         dev_priv->rps.max_freq);
6395         }
6396
6397         if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
6398                 /* Store the frequency values in 16.66 MHZ units, which is
6399                  * the natural hardware unit for SKL
6400                  */
6401                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
6402                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
6403                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
6404                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
6405                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
6406         }
6407 }
6408
6409 static void reset_rps(struct drm_i915_private *dev_priv,
6410                       int (*set)(struct drm_i915_private *, u8))
6411 {
6412         u8 freq = dev_priv->rps.cur_freq;
6413
6414         /* force a reset */
6415         dev_priv->rps.power = -1;
6416         dev_priv->rps.cur_freq = -1;
6417
6418         if (set(dev_priv, freq))
6419                 DRM_ERROR("Failed to reset RPS to initial values\n");
6420 }
6421
6422 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
6423 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
6424 {
6425         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6426
6427         /* Program defaults and thresholds for RPS*/
6428         I915_WRITE(GEN6_RC_VIDEO_FREQ,
6429                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
6430
6431         /* 1 second timeout*/
6432         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
6433                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
6434
6435         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
6436
6437         /* Leaning on the below call to gen6_set_rps to program/setup the
6438          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
6439          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
6440         reset_rps(dev_priv, gen6_set_rps);
6441
6442         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6443 }
6444
6445 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
6446 {
6447         struct intel_engine_cs *engine;
6448         enum intel_engine_id id;
6449         uint32_t rc6_mask = 0;
6450
6451         /* 1a: Software RC state - RC0 */
6452         I915_WRITE(GEN6_RC_STATE, 0);
6453
6454         /* 1b: Get forcewake during program sequence. Although the driver
6455          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6456         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6457
6458         /* 2a: Disable RC states. */
6459         I915_WRITE(GEN6_RC_CONTROL, 0);
6460
6461         /* 2b: Program RC6 thresholds.*/
6462
6463         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
6464         if (IS_SKYLAKE(dev_priv))
6465                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
6466         else
6467                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
6468         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6469         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6470         for_each_engine(engine, dev_priv, id)
6471                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6472
6473         if (HAS_GUC(dev_priv))
6474                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
6475
6476         I915_WRITE(GEN6_RC_SLEEP, 0);
6477
6478         /* 2c: Program Coarse Power Gating Policies. */
6479         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
6480         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
6481
6482         /* 3a: Enable RC6 */
6483         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6484                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
6485         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
6486         I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
6487         I915_WRITE(GEN6_RC_CONTROL,
6488                    GEN6_RC_CTL_HW_ENABLE | GEN6_RC_CTL_EI_MODE(1) | rc6_mask);
6489
6490         /*
6491          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
6492          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
6493          */
6494         if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
6495                 I915_WRITE(GEN9_PG_ENABLE, 0);
6496         else
6497                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
6498                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
6499
6500         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6501 }
6502
6503 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6504 {
6505         struct intel_engine_cs *engine;
6506         enum intel_engine_id id;
6507         uint32_t rc6_mask = 0;
6508
6509         /* 1a: Software RC state - RC0 */
6510         I915_WRITE(GEN6_RC_STATE, 0);
6511
6512         /* 1c & 1d: Get forcewake during program sequence. Although the driver
6513          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6514         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6515
6516         /* 2a: Disable RC states. */
6517         I915_WRITE(GEN6_RC_CONTROL, 0);
6518
6519         /* 2b: Program RC6 thresholds.*/
6520         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6521         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6522         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6523         for_each_engine(engine, dev_priv, id)
6524                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6525         I915_WRITE(GEN6_RC_SLEEP, 0);
6526         if (IS_BROADWELL(dev_priv))
6527                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
6528         else
6529                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6530
6531         /* 3: Enable RC6 */
6532         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6533                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
6534         intel_print_rc6_info(dev_priv, rc6_mask);
6535         if (IS_BROADWELL(dev_priv))
6536                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
6537                                 GEN7_RC_CTL_TO_MODE |
6538                                 rc6_mask);
6539         else
6540                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
6541                                 GEN6_RC_CTL_EI_MODE(1) |
6542                                 rc6_mask);
6543
6544         /* 4 Program defaults and thresholds for RPS*/
6545         I915_WRITE(GEN6_RPNSWREQ,
6546                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
6547         I915_WRITE(GEN6_RC_VIDEO_FREQ,
6548                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
6549         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
6550         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
6551
6552         /* Docs recommend 900MHz, and 300 MHz respectively */
6553         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6554                    dev_priv->rps.max_freq_softlimit << 24 |
6555                    dev_priv->rps.min_freq_softlimit << 16);
6556
6557         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
6558         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
6559         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
6560         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
6561
6562         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6563
6564         /* 5: Enable RPS */
6565         I915_WRITE(GEN6_RP_CONTROL,
6566                    GEN6_RP_MEDIA_TURBO |
6567                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6568                    GEN6_RP_MEDIA_IS_GFX |
6569                    GEN6_RP_ENABLE |
6570                    GEN6_RP_UP_BUSY_AVG |
6571                    GEN6_RP_DOWN_IDLE_AVG);
6572
6573         /* 6: Ring frequency + overclocking (our driver does this later */
6574
6575         reset_rps(dev_priv, gen6_set_rps);
6576
6577         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6578 }
6579
6580 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
6581 {
6582         struct intel_engine_cs *engine;
6583         enum intel_engine_id id;
6584         u32 rc6vids, rc6_mask = 0;
6585         u32 gtfifodbg;
6586         int rc6_mode;
6587         int ret;
6588
6589         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6590
6591         /* Here begins a magic sequence of register writes to enable
6592          * auto-downclocking.
6593          *
6594          * Perhaps there might be some value in exposing these to
6595          * userspace...
6596          */
6597         I915_WRITE(GEN6_RC_STATE, 0);
6598
6599         /* Clear the DBG now so we don't confuse earlier errors */
6600         gtfifodbg = I915_READ(GTFIFODBG);
6601         if (gtfifodbg) {
6602                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
6603                 I915_WRITE(GTFIFODBG, gtfifodbg);
6604         }
6605
6606         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6607
6608         /* disable the counters and set deterministic thresholds */
6609         I915_WRITE(GEN6_RC_CONTROL, 0);
6610
6611         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6612         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6613         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6614         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6615         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6616
6617         for_each_engine(engine, dev_priv, id)
6618                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6619
6620         I915_WRITE(GEN6_RC_SLEEP, 0);
6621         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
6622         if (IS_IVYBRIDGE(dev_priv))
6623                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
6624         else
6625                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
6626         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
6627         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6628
6629         /* Check if we are enabling RC6 */
6630         rc6_mode = intel_enable_rc6();
6631         if (rc6_mode & INTEL_RC6_ENABLE)
6632                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
6633
6634         /* We don't use those on Haswell */
6635         if (!IS_HASWELL(dev_priv)) {
6636                 if (rc6_mode & INTEL_RC6p_ENABLE)
6637                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
6638
6639                 if (rc6_mode & INTEL_RC6pp_ENABLE)
6640                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
6641         }
6642
6643         intel_print_rc6_info(dev_priv, rc6_mask);
6644
6645         I915_WRITE(GEN6_RC_CONTROL,
6646                    rc6_mask |
6647                    GEN6_RC_CTL_EI_MODE(1) |
6648                    GEN6_RC_CTL_HW_ENABLE);
6649
6650         /* Power down if completely idle for over 50ms */
6651         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
6652         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6653
6654         reset_rps(dev_priv, gen6_set_rps);
6655
6656         rc6vids = 0;
6657         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
6658         if (IS_GEN6(dev_priv) && ret) {
6659                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
6660         } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
6661                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
6662                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
6663                 rc6vids &= 0xffff00;
6664                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
6665                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
6666                 if (ret)
6667                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
6668         }
6669
6670         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6671 }
6672
6673 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
6674 {
6675         int min_freq = 15;
6676         unsigned int gpu_freq;
6677         unsigned int max_ia_freq, min_ring_freq;
6678         unsigned int max_gpu_freq, min_gpu_freq;
6679         int scaling_factor = 180;
6680         struct cpufreq_policy *policy;
6681
6682         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6683
6684         policy = cpufreq_cpu_get(0);
6685         if (policy) {
6686                 max_ia_freq = policy->cpuinfo.max_freq;
6687                 cpufreq_cpu_put(policy);
6688         } else {
6689                 /*
6690                  * Default to measured freq if none found, PCU will ensure we
6691                  * don't go over
6692                  */
6693                 max_ia_freq = tsc_khz;
6694         }
6695
6696         /* Convert from kHz to MHz */
6697         max_ia_freq /= 1000;
6698
6699         min_ring_freq = I915_READ(DCLK) & 0xf;
6700         /* convert DDR frequency from units of 266.6MHz to bandwidth */
6701         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
6702
6703         if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
6704                 /* Convert GT frequency to 50 HZ units */
6705                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
6706                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
6707         } else {
6708                 min_gpu_freq = dev_priv->rps.min_freq;
6709                 max_gpu_freq = dev_priv->rps.max_freq;
6710         }
6711
6712         /*
6713          * For each potential GPU frequency, load a ring frequency we'd like
6714          * to use for memory access.  We do this by specifying the IA frequency
6715          * the PCU should use as a reference to determine the ring frequency.
6716          */
6717         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
6718                 int diff = max_gpu_freq - gpu_freq;
6719                 unsigned int ia_freq = 0, ring_freq = 0;
6720
6721                 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
6722                         /*
6723                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
6724                          * No floor required for ring frequency on SKL.
6725                          */
6726                         ring_freq = gpu_freq;
6727                 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
6728                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
6729                         ring_freq = max(min_ring_freq, gpu_freq);
6730                 } else if (IS_HASWELL(dev_priv)) {
6731                         ring_freq = mult_frac(gpu_freq, 5, 4);
6732                         ring_freq = max(min_ring_freq, ring_freq);
6733                         /* leave ia_freq as the default, chosen by cpufreq */
6734                 } else {
6735                         /* On older processors, there is no separate ring
6736                          * clock domain, so in order to boost the bandwidth
6737                          * of the ring, we need to upclock the CPU (ia_freq).
6738                          *
6739                          * For GPU frequencies less than 750MHz,
6740                          * just use the lowest ring freq.
6741                          */
6742                         if (gpu_freq < min_freq)
6743                                 ia_freq = 800;
6744                         else
6745                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
6746                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
6747                 }
6748
6749                 sandybridge_pcode_write(dev_priv,
6750                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
6751                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
6752                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
6753                                         gpu_freq);
6754         }
6755 }
6756
6757 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
6758 {
6759         u32 val, rp0;
6760
6761         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
6762
6763         switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
6764         case 8:
6765                 /* (2 * 4) config */
6766                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
6767                 break;
6768         case 12:
6769                 /* (2 * 6) config */
6770                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
6771                 break;
6772         case 16:
6773                 /* (2 * 8) config */
6774         default:
6775                 /* Setting (2 * 8) Min RP0 for any other combination */
6776                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
6777                 break;
6778         }
6779
6780         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
6781
6782         return rp0;
6783 }
6784
6785 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
6786 {
6787         u32 val, rpe;
6788
6789         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
6790         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
6791
6792         return rpe;
6793 }
6794
6795 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
6796 {
6797         u32 val, rp1;
6798
6799         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
6800         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
6801
6802         return rp1;
6803 }
6804
6805 static u32 cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
6806 {
6807         u32 val, rpn;
6808
6809         val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
6810         rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
6811                        FB_GFX_FREQ_FUSE_MASK);
6812
6813         return rpn;
6814 }
6815
6816 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
6817 {
6818         u32 val, rp1;
6819
6820         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
6821
6822         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
6823
6824         return rp1;
6825 }
6826
6827 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
6828 {
6829         u32 val, rp0;
6830
6831         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
6832
6833         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
6834         /* Clamp to max */
6835         rp0 = min_t(u32, rp0, 0xea);
6836
6837         return rp0;
6838 }
6839
6840 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
6841 {
6842         u32 val, rpe;
6843
6844         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
6845         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
6846         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
6847         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
6848
6849         return rpe;
6850 }
6851
6852 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
6853 {
6854         u32 val;
6855
6856         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
6857         /*
6858          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
6859          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
6860          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
6861          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
6862          * to make sure it matches what Punit accepts.
6863          */
6864         return max_t(u32, val, 0xc0);
6865 }
6866
6867 /* Check that the pctx buffer wasn't move under us. */
6868 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
6869 {
6870         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
6871
6872         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
6873                              dev_priv->vlv_pctx->stolen->start);
6874 }
6875
6876
6877 /* Check that the pcbr address is not empty. */
6878 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
6879 {
6880         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
6881
6882         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
6883 }
6884
6885 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
6886 {
6887         struct i915_ggtt *ggtt = &dev_priv->ggtt;
6888         unsigned long pctx_paddr, paddr;
6889         u32 pcbr;
6890         int pctx_size = 32*1024;
6891
6892         pcbr = I915_READ(VLV_PCBR);
6893         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
6894                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
6895                 paddr = (dev_priv->mm.stolen_base +
6896                          (ggtt->stolen_size - pctx_size));
6897
6898                 pctx_paddr = (paddr & (~4095));
6899                 I915_WRITE(VLV_PCBR, pctx_paddr);
6900         }
6901
6902         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
6903 }
6904
6905 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
6906 {
6907         struct drm_i915_gem_object *pctx;
6908         unsigned long pctx_paddr;
6909         u32 pcbr;
6910         int pctx_size = 24*1024;
6911
6912         pcbr = I915_READ(VLV_PCBR);
6913         if (pcbr) {
6914                 /* BIOS set it up already, grab the pre-alloc'd space */
6915                 int pcbr_offset;
6916
6917                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
6918                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv,
6919                                                                       pcbr_offset,
6920                                                                       I915_GTT_OFFSET_NONE,
6921                                                                       pctx_size);
6922                 goto out;
6923         }
6924
6925         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
6926
6927         /*
6928          * From the Gunit register HAS:
6929          * The Gfx driver is expected to program this register and ensure
6930          * proper allocation within Gfx stolen memory.  For example, this
6931          * register should be programmed such than the PCBR range does not
6932          * overlap with other ranges, such as the frame buffer, protected
6933          * memory, or any other relevant ranges.
6934          */
6935         pctx = i915_gem_object_create_stolen(dev_priv, pctx_size);
6936         if (!pctx) {
6937                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
6938                 goto out;
6939         }
6940
6941         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
6942         I915_WRITE(VLV_PCBR, pctx_paddr);
6943
6944 out:
6945         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
6946         dev_priv->vlv_pctx = pctx;
6947 }
6948
6949 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
6950 {
6951         if (WARN_ON(!dev_priv->vlv_pctx))
6952                 return;
6953
6954         i915_gem_object_put(dev_priv->vlv_pctx);
6955         dev_priv->vlv_pctx = NULL;
6956 }
6957
6958 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
6959 {
6960         dev_priv->rps.gpll_ref_freq =
6961                 vlv_get_cck_clock(dev_priv, "GPLL ref",
6962                                   CCK_GPLL_CLOCK_CONTROL,
6963                                   dev_priv->czclk_freq);
6964
6965         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
6966                          dev_priv->rps.gpll_ref_freq);
6967 }
6968
6969 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
6970 {
6971         u32 val;
6972
6973         valleyview_setup_pctx(dev_priv);
6974
6975         vlv_init_gpll_ref_freq(dev_priv);
6976
6977         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6978         switch ((val >> 6) & 3) {
6979         case 0:
6980         case 1:
6981                 dev_priv->mem_freq = 800;
6982                 break;
6983         case 2:
6984                 dev_priv->mem_freq = 1066;
6985                 break;
6986         case 3:
6987                 dev_priv->mem_freq = 1333;
6988                 break;
6989         }
6990         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
6991
6992         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
6993         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
6994         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
6995                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
6996                          dev_priv->rps.max_freq);
6997
6998         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
6999         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7000                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
7001                          dev_priv->rps.efficient_freq);
7002
7003         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
7004         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7005                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7006                          dev_priv->rps.rp1_freq);
7007
7008         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
7009         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7010                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
7011                          dev_priv->rps.min_freq);
7012 }
7013
7014 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
7015 {
7016         u32 val;
7017
7018         cherryview_setup_pctx(dev_priv);
7019
7020         vlv_init_gpll_ref_freq(dev_priv);
7021
7022         mutex_lock(&dev_priv->sb_lock);
7023         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
7024         mutex_unlock(&dev_priv->sb_lock);
7025
7026         switch ((val >> 2) & 0x7) {
7027         case 3:
7028                 dev_priv->mem_freq = 2000;
7029                 break;
7030         default:
7031                 dev_priv->mem_freq = 1600;
7032                 break;
7033         }
7034         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
7035
7036         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
7037         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
7038         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7039                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
7040                          dev_priv->rps.max_freq);
7041
7042         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
7043         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7044                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
7045                          dev_priv->rps.efficient_freq);
7046
7047         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
7048         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7049                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7050                          dev_priv->rps.rp1_freq);
7051
7052         dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
7053         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7054                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
7055                          dev_priv->rps.min_freq);
7056
7057         WARN_ONCE((dev_priv->rps.max_freq |
7058                    dev_priv->rps.efficient_freq |
7059                    dev_priv->rps.rp1_freq |
7060                    dev_priv->rps.min_freq) & 1,
7061                   "Odd GPU freq values\n");
7062 }
7063
7064 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
7065 {
7066         valleyview_cleanup_pctx(dev_priv);
7067 }
7068
7069 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
7070 {
7071         struct intel_engine_cs *engine;
7072         enum intel_engine_id id;
7073         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
7074
7075         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7076
7077         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
7078                                              GT_FIFO_FREE_ENTRIES_CHV);
7079         if (gtfifodbg) {
7080                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
7081                                  gtfifodbg);
7082                 I915_WRITE(GTFIFODBG, gtfifodbg);
7083         }
7084
7085         cherryview_check_pctx(dev_priv);
7086
7087         /* 1a & 1b: Get forcewake during program sequence. Although the driver
7088          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
7089         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7090
7091         /*  Disable RC states. */
7092         I915_WRITE(GEN6_RC_CONTROL, 0);
7093
7094         /* 2a: Program RC6 thresholds.*/
7095         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
7096         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
7097         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
7098
7099         for_each_engine(engine, dev_priv, id)
7100                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7101         I915_WRITE(GEN6_RC_SLEEP, 0);
7102
7103         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
7104         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
7105
7106         /* allows RC6 residency counter to work */
7107         I915_WRITE(VLV_COUNTER_CONTROL,
7108                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
7109                                       VLV_MEDIA_RC6_COUNT_EN |
7110                                       VLV_RENDER_RC6_COUNT_EN));
7111
7112         /* For now we assume BIOS is allocating and populating the PCBR  */
7113         pcbr = I915_READ(VLV_PCBR);
7114
7115         /* 3: Enable RC6 */
7116         if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
7117             (pcbr >> VLV_PCBR_ADDR_SHIFT))
7118                 rc6_mode = GEN7_RC_CTL_TO_MODE;
7119
7120         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
7121
7122         /* 4 Program defaults and thresholds for RPS*/
7123         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7124         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
7125         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
7126         I915_WRITE(GEN6_RP_UP_EI, 66000);
7127         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
7128
7129         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7130
7131         /* 5: Enable RPS */
7132         I915_WRITE(GEN6_RP_CONTROL,
7133                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
7134                    GEN6_RP_MEDIA_IS_GFX |
7135                    GEN6_RP_ENABLE |
7136                    GEN6_RP_UP_BUSY_AVG |
7137                    GEN6_RP_DOWN_IDLE_AVG);
7138
7139         /* Setting Fixed Bias */
7140         val = VLV_OVERRIDE_EN |
7141                   VLV_SOC_TDP_EN |
7142                   CHV_BIAS_CPU_50_SOC_50;
7143         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
7144
7145         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
7146
7147         /* RPS code assumes GPLL is used */
7148         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
7149
7150         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
7151         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
7152
7153         reset_rps(dev_priv, valleyview_set_rps);
7154
7155         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7156 }
7157
7158 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
7159 {
7160         struct intel_engine_cs *engine;
7161         enum intel_engine_id id;
7162         u32 gtfifodbg, val, rc6_mode = 0;
7163
7164         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7165
7166         valleyview_check_pctx(dev_priv);
7167
7168         gtfifodbg = I915_READ(GTFIFODBG);
7169         if (gtfifodbg) {
7170                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
7171                                  gtfifodbg);
7172                 I915_WRITE(GTFIFODBG, gtfifodbg);
7173         }
7174
7175         /* If VLV, Forcewake all wells, else re-direct to regular path */
7176         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7177
7178         /*  Disable RC states. */
7179         I915_WRITE(GEN6_RC_CONTROL, 0);
7180
7181         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7182         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
7183         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
7184         I915_WRITE(GEN6_RP_UP_EI, 66000);
7185         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
7186
7187         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7188
7189         I915_WRITE(GEN6_RP_CONTROL,
7190                    GEN6_RP_MEDIA_TURBO |
7191                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
7192                    GEN6_RP_MEDIA_IS_GFX |
7193                    GEN6_RP_ENABLE |
7194                    GEN6_RP_UP_BUSY_AVG |
7195                    GEN6_RP_DOWN_IDLE_CONT);
7196
7197         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
7198         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7199         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7200
7201         for_each_engine(engine, dev_priv, id)
7202                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7203
7204         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
7205
7206         /* allows RC6 residency counter to work */
7207         I915_WRITE(VLV_COUNTER_CONTROL,
7208                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
7209                                       VLV_MEDIA_RC0_COUNT_EN |
7210                                       VLV_RENDER_RC0_COUNT_EN |
7211                                       VLV_MEDIA_RC6_COUNT_EN |
7212                                       VLV_RENDER_RC6_COUNT_EN));
7213
7214         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
7215                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
7216
7217         intel_print_rc6_info(dev_priv, rc6_mode);
7218
7219         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
7220
7221         /* Setting Fixed Bias */
7222         val = VLV_OVERRIDE_EN |
7223                   VLV_SOC_TDP_EN |
7224                   VLV_BIAS_CPU_125_SOC_875;
7225         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
7226
7227         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
7228
7229         /* RPS code assumes GPLL is used */
7230         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
7231
7232         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
7233         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
7234
7235         reset_rps(dev_priv, valleyview_set_rps);
7236
7237         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7238 }
7239
7240 static unsigned long intel_pxfreq(u32 vidfreq)
7241 {
7242         unsigned long freq;
7243         int div = (vidfreq & 0x3f0000) >> 16;
7244         int post = (vidfreq & 0x3000) >> 12;
7245         int pre = (vidfreq & 0x7);
7246
7247         if (!pre)
7248                 return 0;
7249
7250         freq = ((div * 133333) / ((1<<post) * pre));
7251
7252         return freq;
7253 }
7254
7255 static const struct cparams {
7256         u16 i;
7257         u16 t;
7258         u16 m;
7259         u16 c;
7260 } cparams[] = {
7261         { 1, 1333, 301, 28664 },
7262         { 1, 1066, 294, 24460 },
7263         { 1, 800, 294, 25192 },
7264         { 0, 1333, 276, 27605 },
7265         { 0, 1066, 276, 27605 },
7266         { 0, 800, 231, 23784 },
7267 };
7268
7269 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
7270 {
7271         u64 total_count, diff, ret;
7272         u32 count1, count2, count3, m = 0, c = 0;
7273         unsigned long now = jiffies_to_msecs(jiffies), diff1;
7274         int i;
7275
7276         lockdep_assert_held(&mchdev_lock);
7277
7278         diff1 = now - dev_priv->ips.last_time1;
7279
7280         /* Prevent division-by-zero if we are asking too fast.
7281          * Also, we don't get interesting results if we are polling
7282          * faster than once in 10ms, so just return the saved value
7283          * in such cases.
7284          */
7285         if (diff1 <= 10)
7286                 return dev_priv->ips.chipset_power;
7287
7288         count1 = I915_READ(DMIEC);
7289         count2 = I915_READ(DDREC);
7290         count3 = I915_READ(CSIEC);
7291
7292         total_count = count1 + count2 + count3;
7293
7294         /* FIXME: handle per-counter overflow */
7295         if (total_count < dev_priv->ips.last_count1) {
7296                 diff = ~0UL - dev_priv->ips.last_count1;
7297                 diff += total_count;
7298         } else {
7299                 diff = total_count - dev_priv->ips.last_count1;
7300         }
7301
7302         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
7303                 if (cparams[i].i == dev_priv->ips.c_m &&
7304                     cparams[i].t == dev_priv->ips.r_t) {
7305                         m = cparams[i].m;
7306                         c = cparams[i].c;
7307                         break;
7308                 }
7309         }
7310
7311         diff = div_u64(diff, diff1);
7312         ret = ((m * diff) + c);
7313         ret = div_u64(ret, 10);
7314
7315         dev_priv->ips.last_count1 = total_count;
7316         dev_priv->ips.last_time1 = now;
7317
7318         dev_priv->ips.chipset_power = ret;
7319
7320         return ret;
7321 }
7322
7323 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
7324 {
7325         unsigned long val;
7326
7327         if (INTEL_INFO(dev_priv)->gen != 5)
7328                 return 0;
7329
7330         spin_lock_irq(&mchdev_lock);
7331
7332         val = __i915_chipset_val(dev_priv);
7333
7334         spin_unlock_irq(&mchdev_lock);
7335
7336         return val;
7337 }
7338
7339 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
7340 {
7341         unsigned long m, x, b;
7342         u32 tsfs;
7343
7344         tsfs = I915_READ(TSFS);
7345
7346         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
7347         x = I915_READ8(TR1);
7348
7349         b = tsfs & TSFS_INTR_MASK;
7350
7351         return ((m * x) / 127) - b;
7352 }
7353
7354 static int _pxvid_to_vd(u8 pxvid)
7355 {
7356         if (pxvid == 0)
7357                 return 0;
7358
7359         if (pxvid >= 8 && pxvid < 31)
7360                 pxvid = 31;
7361
7362         return (pxvid + 2) * 125;
7363 }
7364
7365 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
7366 {
7367         const int vd = _pxvid_to_vd(pxvid);
7368         const int vm = vd - 1125;
7369
7370         if (INTEL_INFO(dev_priv)->is_mobile)
7371                 return vm > 0 ? vm : 0;
7372
7373         return vd;
7374 }
7375
7376 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
7377 {
7378         u64 now, diff, diffms;
7379         u32 count;
7380
7381         lockdep_assert_held(&mchdev_lock);
7382
7383         now = ktime_get_raw_ns();
7384         diffms = now - dev_priv->ips.last_time2;
7385         do_div(diffms, NSEC_PER_MSEC);
7386
7387         /* Don't divide by 0 */
7388         if (!diffms)
7389                 return;
7390
7391         count = I915_READ(GFXEC);
7392
7393         if (count < dev_priv->ips.last_count2) {
7394                 diff = ~0UL - dev_priv->ips.last_count2;
7395                 diff += count;
7396         } else {
7397                 diff = count - dev_priv->ips.last_count2;
7398         }
7399
7400         dev_priv->ips.last_count2 = count;
7401         dev_priv->ips.last_time2 = now;
7402
7403         /* More magic constants... */
7404         diff = diff * 1181;
7405         diff = div_u64(diff, diffms * 10);
7406         dev_priv->ips.gfx_power = diff;
7407 }
7408
7409 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
7410 {
7411         if (INTEL_INFO(dev_priv)->gen != 5)
7412                 return;
7413
7414         spin_lock_irq(&mchdev_lock);
7415
7416         __i915_update_gfx_val(dev_priv);
7417
7418         spin_unlock_irq(&mchdev_lock);
7419 }
7420
7421 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
7422 {
7423         unsigned long t, corr, state1, corr2, state2;
7424         u32 pxvid, ext_v;
7425
7426         lockdep_assert_held(&mchdev_lock);
7427
7428         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
7429         pxvid = (pxvid >> 24) & 0x7f;
7430         ext_v = pvid_to_extvid(dev_priv, pxvid);
7431
7432         state1 = ext_v;
7433
7434         t = i915_mch_val(dev_priv);
7435
7436         /* Revel in the empirically derived constants */
7437
7438         /* Correction factor in 1/100000 units */
7439         if (t > 80)
7440                 corr = ((t * 2349) + 135940);
7441         else if (t >= 50)
7442                 corr = ((t * 964) + 29317);
7443         else /* < 50 */
7444                 corr = ((t * 301) + 1004);
7445
7446         corr = corr * ((150142 * state1) / 10000 - 78642);
7447         corr /= 100000;
7448         corr2 = (corr * dev_priv->ips.corr);
7449
7450         state2 = (corr2 * state1) / 10000;
7451         state2 /= 100; /* convert to mW */
7452
7453         __i915_update_gfx_val(dev_priv);
7454
7455         return dev_priv->ips.gfx_power + state2;
7456 }
7457
7458 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
7459 {
7460         unsigned long val;
7461
7462         if (INTEL_INFO(dev_priv)->gen != 5)
7463                 return 0;
7464
7465         spin_lock_irq(&mchdev_lock);
7466
7467         val = __i915_gfx_val(dev_priv);
7468
7469         spin_unlock_irq(&mchdev_lock);
7470
7471         return val;
7472 }
7473
7474 /**
7475  * i915_read_mch_val - return value for IPS use
7476  *
7477  * Calculate and return a value for the IPS driver to use when deciding whether
7478  * we have thermal and power headroom to increase CPU or GPU power budget.
7479  */
7480 unsigned long i915_read_mch_val(void)
7481 {
7482         struct drm_i915_private *dev_priv;
7483         unsigned long chipset_val, graphics_val, ret = 0;
7484
7485         spin_lock_irq(&mchdev_lock);
7486         if (!i915_mch_dev)
7487                 goto out_unlock;
7488         dev_priv = i915_mch_dev;
7489
7490         chipset_val = __i915_chipset_val(dev_priv);
7491         graphics_val = __i915_gfx_val(dev_priv);
7492
7493         ret = chipset_val + graphics_val;
7494
7495 out_unlock:
7496         spin_unlock_irq(&mchdev_lock);
7497
7498         return ret;
7499 }
7500 EXPORT_SYMBOL_GPL(i915_read_mch_val);
7501
7502 /**
7503  * i915_gpu_raise - raise GPU frequency limit
7504  *
7505  * Raise the limit; IPS indicates we have thermal headroom.
7506  */
7507 bool i915_gpu_raise(void)
7508 {
7509         struct drm_i915_private *dev_priv;
7510         bool ret = true;
7511
7512         spin_lock_irq(&mchdev_lock);
7513         if (!i915_mch_dev) {
7514                 ret = false;
7515                 goto out_unlock;
7516         }
7517         dev_priv = i915_mch_dev;
7518
7519         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
7520                 dev_priv->ips.max_delay--;
7521
7522 out_unlock:
7523         spin_unlock_irq(&mchdev_lock);
7524
7525         return ret;
7526 }
7527 EXPORT_SYMBOL_GPL(i915_gpu_raise);
7528
7529 /**
7530  * i915_gpu_lower - lower GPU frequency limit
7531  *
7532  * IPS indicates we're close to a thermal limit, so throttle back the GPU
7533  * frequency maximum.
7534  */
7535 bool i915_gpu_lower(void)
7536 {
7537         struct drm_i915_private *dev_priv;
7538         bool ret = true;
7539
7540         spin_lock_irq(&mchdev_lock);
7541         if (!i915_mch_dev) {
7542                 ret = false;
7543                 goto out_unlock;
7544         }
7545         dev_priv = i915_mch_dev;
7546
7547         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
7548                 dev_priv->ips.max_delay++;
7549
7550 out_unlock:
7551         spin_unlock_irq(&mchdev_lock);
7552
7553         return ret;
7554 }
7555 EXPORT_SYMBOL_GPL(i915_gpu_lower);
7556
7557 /**
7558  * i915_gpu_busy - indicate GPU business to IPS
7559  *
7560  * Tell the IPS driver whether or not the GPU is busy.
7561  */
7562 bool i915_gpu_busy(void)
7563 {
7564         bool ret = false;
7565
7566         spin_lock_irq(&mchdev_lock);
7567         if (i915_mch_dev)
7568                 ret = i915_mch_dev->gt.awake;
7569         spin_unlock_irq(&mchdev_lock);
7570
7571         return ret;
7572 }
7573 EXPORT_SYMBOL_GPL(i915_gpu_busy);
7574
7575 /**
7576  * i915_gpu_turbo_disable - disable graphics turbo
7577  *
7578  * Disable graphics turbo by resetting the max frequency and setting the
7579  * current frequency to the default.
7580  */
7581 bool i915_gpu_turbo_disable(void)
7582 {
7583         struct drm_i915_private *dev_priv;
7584         bool ret = true;
7585
7586         spin_lock_irq(&mchdev_lock);
7587         if (!i915_mch_dev) {
7588                 ret = false;
7589                 goto out_unlock;
7590         }
7591         dev_priv = i915_mch_dev;
7592
7593         dev_priv->ips.max_delay = dev_priv->ips.fstart;
7594
7595         if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
7596                 ret = false;
7597
7598 out_unlock:
7599         spin_unlock_irq(&mchdev_lock);
7600
7601         return ret;
7602 }
7603 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
7604
7605 /**
7606  * Tells the intel_ips driver that the i915 driver is now loaded, if
7607  * IPS got loaded first.
7608  *
7609  * This awkward dance is so that neither module has to depend on the
7610  * other in order for IPS to do the appropriate communication of
7611  * GPU turbo limits to i915.
7612  */
7613 static void
7614 ips_ping_for_i915_load(void)
7615 {
7616         void (*link)(void);
7617
7618         link = symbol_get(ips_link_to_i915_driver);
7619         if (link) {
7620                 link();
7621                 symbol_put(ips_link_to_i915_driver);
7622         }
7623 }
7624
7625 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
7626 {
7627         /* We only register the i915 ips part with intel-ips once everything is
7628          * set up, to avoid intel-ips sneaking in and reading bogus values. */
7629         spin_lock_irq(&mchdev_lock);
7630         i915_mch_dev = dev_priv;
7631         spin_unlock_irq(&mchdev_lock);
7632
7633         ips_ping_for_i915_load();
7634 }
7635
7636 void intel_gpu_ips_teardown(void)
7637 {
7638         spin_lock_irq(&mchdev_lock);
7639         i915_mch_dev = NULL;
7640         spin_unlock_irq(&mchdev_lock);
7641 }
7642
7643 static void intel_init_emon(struct drm_i915_private *dev_priv)
7644 {
7645         u32 lcfuse;
7646         u8 pxw[16];
7647         int i;
7648
7649         /* Disable to program */
7650         I915_WRITE(ECR, 0);
7651         POSTING_READ(ECR);
7652
7653         /* Program energy weights for various events */
7654         I915_WRITE(SDEW, 0x15040d00);
7655         I915_WRITE(CSIEW0, 0x007f0000);
7656         I915_WRITE(CSIEW1, 0x1e220004);
7657         I915_WRITE(CSIEW2, 0x04000004);
7658
7659         for (i = 0; i < 5; i++)
7660                 I915_WRITE(PEW(i), 0);
7661         for (i = 0; i < 3; i++)
7662                 I915_WRITE(DEW(i), 0);
7663
7664         /* Program P-state weights to account for frequency power adjustment */
7665         for (i = 0; i < 16; i++) {
7666                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
7667                 unsigned long freq = intel_pxfreq(pxvidfreq);
7668                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7669                         PXVFREQ_PX_SHIFT;
7670                 unsigned long val;
7671
7672                 val = vid * vid;
7673                 val *= (freq / 1000);
7674                 val *= 255;
7675                 val /= (127*127*900);
7676                 if (val > 0xff)
7677                         DRM_ERROR("bad pxval: %ld\n", val);
7678                 pxw[i] = val;
7679         }
7680         /* Render standby states get 0 weight */
7681         pxw[14] = 0;
7682         pxw[15] = 0;
7683
7684         for (i = 0; i < 4; i++) {
7685                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7686                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7687                 I915_WRITE(PXW(i), val);
7688         }
7689
7690         /* Adjust magic regs to magic values (more experimental results) */
7691         I915_WRITE(OGW0, 0);
7692         I915_WRITE(OGW1, 0);
7693         I915_WRITE(EG0, 0x00007f00);
7694         I915_WRITE(EG1, 0x0000000e);
7695         I915_WRITE(EG2, 0x000e0000);
7696         I915_WRITE(EG3, 0x68000300);
7697         I915_WRITE(EG4, 0x42000000);
7698         I915_WRITE(EG5, 0x00140031);
7699         I915_WRITE(EG6, 0);
7700         I915_WRITE(EG7, 0);
7701
7702         for (i = 0; i < 8; i++)
7703                 I915_WRITE(PXWL(i), 0);
7704
7705         /* Enable PMON + select events */
7706         I915_WRITE(ECR, 0x80000019);
7707
7708         lcfuse = I915_READ(LCFUSE02);
7709
7710         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
7711 }
7712
7713 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
7714 {
7715         /*
7716          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7717          * requirement.
7718          */
7719         if (!i915.enable_rc6) {
7720                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7721                 intel_runtime_pm_get(dev_priv);
7722         }
7723
7724         mutex_lock(&dev_priv->drm.struct_mutex);
7725         mutex_lock(&dev_priv->rps.hw_lock);
7726
7727         /* Initialize RPS limits (for userspace) */
7728         if (IS_CHERRYVIEW(dev_priv))
7729                 cherryview_init_gt_powersave(dev_priv);
7730         else if (IS_VALLEYVIEW(dev_priv))
7731                 valleyview_init_gt_powersave(dev_priv);
7732         else if (INTEL_GEN(dev_priv) >= 6)
7733                 gen6_init_rps_frequencies(dev_priv);
7734
7735         /* Derive initial user preferences/limits from the hardware limits */
7736         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
7737         dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
7738
7739         dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
7740         dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
7741
7742         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
7743                 dev_priv->rps.min_freq_softlimit =
7744                         max_t(int,
7745                               dev_priv->rps.efficient_freq,
7746                               intel_freq_opcode(dev_priv, 450));
7747
7748         /* After setting max-softlimit, find the overclock max freq */
7749         if (IS_GEN6(dev_priv) ||
7750             IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
7751                 u32 params = 0;
7752
7753                 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
7754                 if (params & BIT(31)) { /* OC supported */
7755                         DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
7756                                          (dev_priv->rps.max_freq & 0xff) * 50,
7757                                          (params & 0xff) * 50);
7758                         dev_priv->rps.max_freq = params & 0xff;
7759                 }
7760         }
7761
7762         /* Finally allow us to boost to max by default */
7763         dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
7764
7765         mutex_unlock(&dev_priv->rps.hw_lock);
7766         mutex_unlock(&dev_priv->drm.struct_mutex);
7767
7768         intel_autoenable_gt_powersave(dev_priv);
7769 }
7770
7771 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
7772 {
7773         if (IS_VALLEYVIEW(dev_priv))
7774                 valleyview_cleanup_gt_powersave(dev_priv);
7775
7776         if (!i915.enable_rc6)
7777                 intel_runtime_pm_put(dev_priv);
7778 }
7779
7780 /**
7781  * intel_suspend_gt_powersave - suspend PM work and helper threads
7782  * @dev_priv: i915 device
7783  *
7784  * We don't want to disable RC6 or other features here, we just want
7785  * to make sure any work we've queued has finished and won't bother
7786  * us while we're suspended.
7787  */
7788 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
7789 {
7790         if (INTEL_GEN(dev_priv) < 6)
7791                 return;
7792
7793         if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
7794                 intel_runtime_pm_put(dev_priv);
7795
7796         /* gen6_rps_idle() will be called later to disable interrupts */
7797 }
7798
7799 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
7800 {
7801         dev_priv->rps.enabled = true; /* force disabling */
7802         intel_disable_gt_powersave(dev_priv);
7803
7804         gen6_reset_rps_interrupts(dev_priv);
7805 }
7806
7807 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
7808 {
7809         if (!READ_ONCE(dev_priv->rps.enabled))
7810                 return;
7811
7812         mutex_lock(&dev_priv->rps.hw_lock);
7813
7814         if (INTEL_GEN(dev_priv) >= 9) {
7815                 gen9_disable_rc6(dev_priv);
7816                 gen9_disable_rps(dev_priv);
7817         } else if (IS_CHERRYVIEW(dev_priv)) {
7818                 cherryview_disable_rps(dev_priv);
7819         } else if (IS_VALLEYVIEW(dev_priv)) {
7820                 valleyview_disable_rps(dev_priv);
7821         } else if (INTEL_GEN(dev_priv) >= 6) {
7822                 gen6_disable_rps(dev_priv);
7823         }  else if (IS_IRONLAKE_M(dev_priv)) {
7824                 ironlake_disable_drps(dev_priv);
7825         }
7826
7827         dev_priv->rps.enabled = false;
7828         mutex_unlock(&dev_priv->rps.hw_lock);
7829 }
7830
7831 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
7832 {
7833         /* We shouldn't be disabling as we submit, so this should be less
7834          * racy than it appears!
7835          */
7836         if (READ_ONCE(dev_priv->rps.enabled))
7837                 return;
7838
7839         /* Powersaving is controlled by the host when inside a VM */
7840         if (intel_vgpu_active(dev_priv))
7841                 return;
7842
7843         mutex_lock(&dev_priv->rps.hw_lock);
7844
7845         if (IS_CHERRYVIEW(dev_priv)) {
7846                 cherryview_enable_rps(dev_priv);
7847         } else if (IS_VALLEYVIEW(dev_priv)) {
7848                 valleyview_enable_rps(dev_priv);
7849         } else if (INTEL_GEN(dev_priv) >= 9) {
7850                 gen9_enable_rc6(dev_priv);
7851                 gen9_enable_rps(dev_priv);
7852                 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
7853                         gen6_update_ring_freq(dev_priv);
7854         } else if (IS_BROADWELL(dev_priv)) {
7855                 gen8_enable_rps(dev_priv);
7856                 gen6_update_ring_freq(dev_priv);
7857         } else if (INTEL_GEN(dev_priv) >= 6) {
7858                 gen6_enable_rps(dev_priv);
7859                 gen6_update_ring_freq(dev_priv);
7860         } else if (IS_IRONLAKE_M(dev_priv)) {
7861                 ironlake_enable_drps(dev_priv);
7862                 intel_init_emon(dev_priv);
7863         }
7864
7865         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
7866         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
7867
7868         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
7869         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
7870
7871         dev_priv->rps.enabled = true;
7872         mutex_unlock(&dev_priv->rps.hw_lock);
7873 }
7874
7875 static void __intel_autoenable_gt_powersave(struct work_struct *work)
7876 {
7877         struct drm_i915_private *dev_priv =
7878                 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
7879         struct intel_engine_cs *rcs;
7880         struct drm_i915_gem_request *req;
7881
7882         if (READ_ONCE(dev_priv->rps.enabled))
7883                 goto out;
7884
7885         rcs = dev_priv->engine[RCS];
7886         if (rcs->last_retired_context)
7887                 goto out;
7888
7889         if (!rcs->init_context)
7890                 goto out;
7891
7892         mutex_lock(&dev_priv->drm.struct_mutex);
7893
7894         req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
7895         if (IS_ERR(req))
7896                 goto unlock;
7897
7898         if (!i915.enable_execlists && i915_switch_context(req) == 0)
7899                 rcs->init_context(req);
7900
7901         /* Mark the device busy, calling intel_enable_gt_powersave() */
7902         i915_add_request(req);
7903
7904 unlock:
7905         mutex_unlock(&dev_priv->drm.struct_mutex);
7906 out:
7907         intel_runtime_pm_put(dev_priv);
7908 }
7909
7910 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
7911 {
7912         if (READ_ONCE(dev_priv->rps.enabled))
7913                 return;
7914
7915         if (IS_IRONLAKE_M(dev_priv)) {
7916                 ironlake_enable_drps(dev_priv);
7917                 intel_init_emon(dev_priv);
7918         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
7919                 /*
7920                  * PCU communication is slow and this doesn't need to be
7921                  * done at any specific time, so do this out of our fast path
7922                  * to make resume and init faster.
7923                  *
7924                  * We depend on the HW RC6 power context save/restore
7925                  * mechanism when entering D3 through runtime PM suspend. So
7926                  * disable RPM until RPS/RC6 is properly setup. We can only
7927                  * get here via the driver load/system resume/runtime resume
7928                  * paths, so the _noresume version is enough (and in case of
7929                  * runtime resume it's necessary).
7930                  */
7931                 if (queue_delayed_work(dev_priv->wq,
7932                                        &dev_priv->rps.autoenable_work,
7933                                        round_jiffies_up_relative(HZ)))
7934                         intel_runtime_pm_get_noresume(dev_priv);
7935         }
7936 }
7937
7938 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
7939 {
7940         /*
7941          * On Ibex Peak and Cougar Point, we need to disable clock
7942          * gating for the panel power sequencer or it will fail to
7943          * start up when no ports are active.
7944          */
7945         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7946 }
7947
7948 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
7949 {
7950         enum pipe pipe;
7951
7952         for_each_pipe(dev_priv, pipe) {
7953                 I915_WRITE(DSPCNTR(pipe),
7954                            I915_READ(DSPCNTR(pipe)) |
7955                            DISPPLANE_TRICKLE_FEED_DISABLE);
7956
7957                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
7958                 POSTING_READ(DSPSURF(pipe));
7959         }
7960 }
7961
7962 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
7963 {
7964         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
7965         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
7966         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
7967
7968         /*
7969          * Don't touch WM1S_LP_EN here.
7970          * Doing so could cause underruns.
7971          */
7972 }
7973
7974 static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
7975 {
7976         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7977
7978         /*
7979          * Required for FBC
7980          * WaFbcDisableDpfcClockGating:ilk
7981          */
7982         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
7983                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
7984                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
7985
7986         I915_WRITE(PCH_3DCGDIS0,
7987                    MARIUNIT_CLOCK_GATE_DISABLE |
7988                    SVSMUNIT_CLOCK_GATE_DISABLE);
7989         I915_WRITE(PCH_3DCGDIS1,
7990                    VFMUNIT_CLOCK_GATE_DISABLE);
7991
7992         /*
7993          * According to the spec the following bits should be set in
7994          * order to enable memory self-refresh
7995          * The bit 22/21 of 0x42004
7996          * The bit 5 of 0x42020
7997          * The bit 15 of 0x45000
7998          */
7999         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8000                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
8001                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8002         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
8003         I915_WRITE(DISP_ARB_CTL,
8004                    (I915_READ(DISP_ARB_CTL) |
8005                     DISP_FBC_WM_DIS));
8006
8007         ilk_init_lp_watermarks(dev_priv);
8008
8009         /*
8010          * Based on the document from hardware guys the following bits
8011          * should be set unconditionally in order to enable FBC.
8012          * The bit 22 of 0x42000
8013          * The bit 22 of 0x42004
8014          * The bit 7,8,9 of 0x42020.
8015          */
8016         if (IS_IRONLAKE_M(dev_priv)) {
8017                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
8018                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8019                            I915_READ(ILK_DISPLAY_CHICKEN1) |
8020                            ILK_FBCQ_DIS);
8021                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8022                            I915_READ(ILK_DISPLAY_CHICKEN2) |
8023                            ILK_DPARB_GATE);
8024         }
8025
8026         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
8027
8028         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8029                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8030                    ILK_ELPIN_409_SELECT);
8031         I915_WRITE(_3D_CHICKEN2,
8032                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8033                    _3D_CHICKEN2_WM_READ_PIPELINED);
8034
8035         /* WaDisableRenderCachePipelinedFlush:ilk */
8036         I915_WRITE(CACHE_MODE_0,
8037                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
8038
8039         /* WaDisable_RenderCache_OperationalFlush:ilk */
8040         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8041
8042         g4x_disable_trickle_feed(dev_priv);
8043
8044         ibx_init_clock_gating(dev_priv);
8045 }
8046
8047 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
8048 {
8049         int pipe;
8050         uint32_t val;
8051
8052         /*
8053          * On Ibex Peak and Cougar Point, we need to disable clock
8054          * gating for the panel power sequencer or it will fail to
8055          * start up when no ports are active.
8056          */
8057         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
8058                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
8059                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
8060         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8061                    DPLS_EDP_PPS_FIX_DIS);
8062         /* The below fixes the weird display corruption, a few pixels shifted
8063          * downward, on (only) LVDS of some HP laptops with IVY.
8064          */
8065         for_each_pipe(dev_priv, pipe) {
8066                 val = I915_READ(TRANS_CHICKEN2(pipe));
8067                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
8068                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
8069                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
8070                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
8071                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
8072                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
8073                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
8074                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
8075         }
8076         /* WADP0ClockGatingDisable */
8077         for_each_pipe(dev_priv, pipe) {
8078                 I915_WRITE(TRANS_CHICKEN1(pipe),
8079                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
8080         }
8081 }
8082
8083 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
8084 {
8085         uint32_t tmp;
8086
8087         tmp = I915_READ(MCH_SSKPD);
8088         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
8089                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
8090                               tmp);
8091 }
8092
8093 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
8094 {
8095         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
8096
8097         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
8098
8099         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8100                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8101                    ILK_ELPIN_409_SELECT);
8102
8103         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
8104         I915_WRITE(_3D_CHICKEN,
8105                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
8106
8107         /* WaDisable_RenderCache_OperationalFlush:snb */
8108         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8109
8110         /*
8111          * BSpec recoomends 8x4 when MSAA is used,
8112          * however in practice 16x4 seems fastest.
8113          *
8114          * Note that PS/WM thread counts depend on the WIZ hashing
8115          * disable bit, which we don't touch here, but it's good
8116          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8117          */
8118         I915_WRITE(GEN6_GT_MODE,
8119                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8120
8121         ilk_init_lp_watermarks(dev_priv);
8122
8123         I915_WRITE(CACHE_MODE_0,
8124                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
8125
8126         I915_WRITE(GEN6_UCGCTL1,
8127                    I915_READ(GEN6_UCGCTL1) |
8128                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
8129                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
8130
8131         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8132          * gating disable must be set.  Failure to set it results in
8133          * flickering pixels due to Z write ordering failures after
8134          * some amount of runtime in the Mesa "fire" demo, and Unigine
8135          * Sanctuary and Tropics, and apparently anything else with
8136          * alpha test or pixel discard.
8137          *
8138          * According to the spec, bit 11 (RCCUNIT) must also be set,
8139          * but we didn't debug actual testcases to find it out.
8140          *
8141          * WaDisableRCCUnitClockGating:snb
8142          * WaDisableRCPBUnitClockGating:snb
8143          */
8144         I915_WRITE(GEN6_UCGCTL2,
8145                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8146                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8147
8148         /* WaStripsFansDisableFastClipPerformanceFix:snb */
8149         I915_WRITE(_3D_CHICKEN3,
8150                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
8151
8152         /*
8153          * Bspec says:
8154          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
8155          * 3DSTATE_SF number of SF output attributes is more than 16."
8156          */
8157         I915_WRITE(_3D_CHICKEN3,
8158                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
8159
8160         /*
8161          * According to the spec the following bits should be
8162          * set in order to enable memory self-refresh and fbc:
8163          * The bit21 and bit22 of 0x42000
8164          * The bit21 and bit22 of 0x42004
8165          * The bit5 and bit7 of 0x42020
8166          * The bit14 of 0x70180
8167          * The bit14 of 0x71180
8168          *
8169          * WaFbcAsynchFlipDisableFbcQueue:snb
8170          */
8171         I915_WRITE(ILK_DISPLAY_CHICKEN1,
8172                    I915_READ(ILK_DISPLAY_CHICKEN1) |
8173                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8174         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8175                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8176                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8177         I915_WRITE(ILK_DSPCLK_GATE_D,
8178                    I915_READ(ILK_DSPCLK_GATE_D) |
8179                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
8180                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
8181
8182         g4x_disable_trickle_feed(dev_priv);
8183
8184         cpt_init_clock_gating(dev_priv);
8185
8186         gen6_check_mch_setup(dev_priv);
8187 }
8188
8189 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
8190 {
8191         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
8192
8193         /*
8194          * WaVSThreadDispatchOverride:ivb,vlv
8195          *
8196          * This actually overrides the dispatch
8197          * mode for all thread types.
8198          */
8199         reg &= ~GEN7_FF_SCHED_MASK;
8200         reg |= GEN7_FF_TS_SCHED_HW;
8201         reg |= GEN7_FF_VS_SCHED_HW;
8202         reg |= GEN7_FF_DS_SCHED_HW;
8203
8204         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
8205 }
8206
8207 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
8208 {
8209         /*
8210          * TODO: this bit should only be enabled when really needed, then
8211          * disabled when not needed anymore in order to save power.
8212          */
8213         if (HAS_PCH_LPT_LP(dev_priv))
8214                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
8215                            I915_READ(SOUTH_DSPCLK_GATE_D) |
8216                            PCH_LP_PARTITION_LEVEL_DISABLE);
8217
8218         /* WADPOClockGatingDisable:hsw */
8219         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
8220                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
8221                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
8222 }
8223
8224 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
8225 {
8226         if (HAS_PCH_LPT_LP(dev_priv)) {
8227                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
8228
8229                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8230                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8231         }
8232 }
8233
8234 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
8235                                    int general_prio_credits,
8236                                    int high_prio_credits)
8237 {
8238         u32 misccpctl;
8239         u32 val;
8240
8241         /* WaTempDisableDOPClkGating:bdw */
8242         misccpctl = I915_READ(GEN7_MISCCPCTL);
8243         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
8244
8245         val = I915_READ(GEN8_L3SQCREG1);
8246         val &= ~L3_PRIO_CREDITS_MASK;
8247         val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
8248         val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
8249         I915_WRITE(GEN8_L3SQCREG1, val);
8250
8251         /*
8252          * Wait at least 100 clocks before re-enabling clock gating.
8253          * See the definition of L3SQCREG1 in BSpec.
8254          */
8255         POSTING_READ(GEN8_L3SQCREG1);
8256         udelay(1);
8257         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
8258 }
8259
8260 static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
8261 {
8262         gen9_init_clock_gating(dev_priv);
8263
8264         /* WaDisableSDEUnitClockGating:kbl */
8265         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
8266                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
8267                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8268
8269         /* WaDisableGamClockGating:kbl */
8270         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
8271                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
8272                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
8273
8274         /* WaFbcNukeOnHostModify:kbl,cfl */
8275         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
8276                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
8277 }
8278
8279 static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
8280 {
8281         gen9_init_clock_gating(dev_priv);
8282
8283         /* WAC6entrylatency:skl */
8284         I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
8285                    FBC_LLC_FULLY_OPEN);
8286
8287         /* WaFbcNukeOnHostModify:skl */
8288         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
8289                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
8290 }
8291
8292 static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
8293 {
8294         enum pipe pipe;
8295
8296         ilk_init_lp_watermarks(dev_priv);
8297
8298         /* WaSwitchSolVfFArbitrationPriority:bdw */
8299         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
8300
8301         /* WaPsrDPAMaskVBlankInSRD:bdw */
8302         I915_WRITE(CHICKEN_PAR1_1,
8303                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
8304
8305         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
8306         for_each_pipe(dev_priv, pipe) {
8307                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
8308                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
8309                            BDW_DPRS_MASK_VBLANK_SRD);
8310         }
8311
8312         /* WaVSRefCountFullforceMissDisable:bdw */
8313         /* WaDSRefCountFullforceMissDisable:bdw */
8314         I915_WRITE(GEN7_FF_THREAD_MODE,
8315                    I915_READ(GEN7_FF_THREAD_MODE) &
8316                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
8317
8318         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
8319                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
8320
8321         /* WaDisableSDEUnitClockGating:bdw */
8322         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
8323                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8324
8325         /* WaProgramL3SqcReg1Default:bdw */
8326         gen8_set_l3sqc_credits(dev_priv, 30, 2);
8327
8328         /*
8329          * WaGttCachingOffByDefault:bdw
8330          * GTT cache may not work with big pages, so if those
8331          * are ever enabled GTT cache may need to be disabled.
8332          */
8333         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
8334
8335         /* WaKVMNotificationOnConfigChange:bdw */
8336         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
8337                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
8338
8339         lpt_init_clock_gating(dev_priv);
8340
8341         /* WaDisableDopClockGating:bdw
8342          *
8343          * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
8344          * clock gating.
8345          */
8346         I915_WRITE(GEN6_UCGCTL1,
8347                    I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
8348 }
8349
8350 static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
8351 {
8352         ilk_init_lp_watermarks(dev_priv);
8353
8354         /* L3 caching of data atomics doesn't work -- disable it. */
8355         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
8356         I915_WRITE(HSW_ROW_CHICKEN3,
8357                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
8358
8359         /* This is required by WaCatErrorRejectionIssue:hsw */
8360         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8361                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8362                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8363
8364         /* WaVSRefCountFullforceMissDisable:hsw */
8365         I915_WRITE(GEN7_FF_THREAD_MODE,
8366                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
8367
8368         /* WaDisable_RenderCache_OperationalFlush:hsw */
8369         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8370
8371         /* enable HiZ Raw Stall Optimization */
8372         I915_WRITE(CACHE_MODE_0_GEN7,
8373                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
8374
8375         /* WaDisable4x2SubspanOptimization:hsw */
8376         I915_WRITE(CACHE_MODE_1,
8377                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
8378
8379         /*
8380          * BSpec recommends 8x4 when MSAA is used,
8381          * however in practice 16x4 seems fastest.
8382          *
8383          * Note that PS/WM thread counts depend on the WIZ hashing
8384          * disable bit, which we don't touch here, but it's good
8385          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8386          */
8387         I915_WRITE(GEN7_GT_MODE,
8388                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8389
8390         /* WaSampleCChickenBitEnable:hsw */
8391         I915_WRITE(HALF_SLICE_CHICKEN3,
8392                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
8393
8394         /* WaSwitchSolVfFArbitrationPriority:hsw */
8395         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
8396
8397         /* WaRsPkgCStateDisplayPMReq:hsw */
8398         I915_WRITE(CHICKEN_PAR1_1,
8399                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
8400
8401         lpt_init_clock_gating(dev_priv);
8402 }
8403
8404 static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
8405 {
8406         uint32_t snpcr;
8407
8408         ilk_init_lp_watermarks(dev_priv);
8409
8410         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
8411
8412         /* WaDisableEarlyCull:ivb */
8413         I915_WRITE(_3D_CHICKEN3,
8414                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
8415
8416         /* WaDisableBackToBackFlipFix:ivb */
8417         I915_WRITE(IVB_CHICKEN3,
8418                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8419                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
8420
8421         /* WaDisablePSDDualDispatchEnable:ivb */
8422         if (IS_IVB_GT1(dev_priv))
8423                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
8424                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
8425
8426         /* WaDisable_RenderCache_OperationalFlush:ivb */
8427         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8428
8429         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
8430         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8431                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8432
8433         /* WaApplyL3ControlAndL3ChickenMode:ivb */
8434         I915_WRITE(GEN7_L3CNTLREG1,
8435                         GEN7_WA_FOR_GEN7_L3_CONTROL);
8436         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8437                    GEN7_WA_L3_CHICKEN_MODE);
8438         if (IS_IVB_GT1(dev_priv))
8439                 I915_WRITE(GEN7_ROW_CHICKEN2,
8440                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8441         else {
8442                 /* must write both registers */
8443                 I915_WRITE(GEN7_ROW_CHICKEN2,
8444                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8445                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
8446                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8447         }
8448
8449         /* WaForceL3Serialization:ivb */
8450         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
8451                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
8452
8453         /*
8454          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8455          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
8456          */
8457         I915_WRITE(GEN6_UCGCTL2,
8458                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8459
8460         /* This is required by WaCatErrorRejectionIssue:ivb */
8461         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8462                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8463                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8464
8465         g4x_disable_trickle_feed(dev_priv);
8466
8467         gen7_setup_fixed_func_scheduler(dev_priv);
8468
8469         if (0) { /* causes HiZ corruption on ivb:gt1 */
8470                 /* enable HiZ Raw Stall Optimization */
8471                 I915_WRITE(CACHE_MODE_0_GEN7,
8472                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
8473         }
8474
8475         /* WaDisable4x2SubspanOptimization:ivb */
8476         I915_WRITE(CACHE_MODE_1,
8477                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
8478
8479         /*
8480          * BSpec recommends 8x4 when MSAA is used,
8481          * however in practice 16x4 seems fastest.
8482          *
8483          * Note that PS/WM thread counts depend on the WIZ hashing
8484          * disable bit, which we don't touch here, but it's good
8485          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8486          */
8487         I915_WRITE(GEN7_GT_MODE,
8488                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8489
8490         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
8491         snpcr &= ~GEN6_MBC_SNPCR_MASK;
8492         snpcr |= GEN6_MBC_SNPCR_MED;
8493         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
8494
8495         if (!HAS_PCH_NOP(dev_priv))
8496                 cpt_init_clock_gating(dev_priv);
8497
8498         gen6_check_mch_setup(dev_priv);
8499 }
8500
8501 static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
8502 {
8503         /* WaDisableEarlyCull:vlv */
8504         I915_WRITE(_3D_CHICKEN3,
8505                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
8506
8507         /* WaDisableBackToBackFlipFix:vlv */
8508         I915_WRITE(IVB_CHICKEN3,
8509                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8510                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
8511
8512         /* WaPsdDispatchEnable:vlv */
8513         /* WaDisablePSDDualDispatchEnable:vlv */
8514         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
8515                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
8516                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
8517
8518         /* WaDisable_RenderCache_OperationalFlush:vlv */
8519         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8520
8521         /* WaForceL3Serialization:vlv */
8522         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
8523                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
8524
8525         /* WaDisableDopClockGating:vlv */
8526         I915_WRITE(GEN7_ROW_CHICKEN2,
8527                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8528
8529         /* This is required by WaCatErrorRejectionIssue:vlv */
8530         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8531                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8532                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8533
8534         gen7_setup_fixed_func_scheduler(dev_priv);
8535
8536         /*
8537          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8538          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
8539          */
8540         I915_WRITE(GEN6_UCGCTL2,
8541                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8542
8543         /* WaDisableL3Bank2xClockGate:vlv
8544          * Disabling L3 clock gating- MMIO 940c[25] = 1
8545          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
8546         I915_WRITE(GEN7_UCGCTL4,
8547                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
8548
8549         /*
8550          * BSpec says this must be set, even though
8551          * WaDisable4x2SubspanOptimization isn't listed for VLV.
8552          */
8553         I915_WRITE(CACHE_MODE_1,
8554                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
8555
8556         /*
8557          * BSpec recommends 8x4 when MSAA is used,
8558          * however in practice 16x4 seems fastest.
8559          *
8560          * Note that PS/WM thread counts depend on the WIZ hashing
8561          * disable bit, which we don't touch here, but it's good
8562          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8563          */
8564         I915_WRITE(GEN7_GT_MODE,
8565                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8566
8567         /*
8568          * WaIncreaseL3CreditsForVLVB0:vlv
8569          * This is the hardware default actually.
8570          */
8571         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
8572
8573         /*
8574          * WaDisableVLVClockGating_VBIIssue:vlv
8575          * Disable clock gating on th GCFG unit to prevent a delay
8576          * in the reporting of vblank events.
8577          */
8578         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
8579 }
8580
8581 static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
8582 {
8583         /* WaVSRefCountFullforceMissDisable:chv */
8584         /* WaDSRefCountFullforceMissDisable:chv */
8585         I915_WRITE(GEN7_FF_THREAD_MODE,
8586                    I915_READ(GEN7_FF_THREAD_MODE) &
8587                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
8588
8589         /* WaDisableSemaphoreAndSyncFlipWait:chv */
8590         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
8591                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
8592
8593         /* WaDisableCSUnitClockGating:chv */
8594         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
8595                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
8596
8597         /* WaDisableSDEUnitClockGating:chv */
8598         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
8599                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8600
8601         /*
8602          * WaProgramL3SqcReg1Default:chv
8603          * See gfxspecs/Related Documents/Performance Guide/
8604          * LSQC Setting Recommendations.
8605          */
8606         gen8_set_l3sqc_credits(dev_priv, 38, 2);
8607
8608         /*
8609          * GTT cache may not work with big pages, so if those
8610          * are ever enabled GTT cache may need to be disabled.
8611          */
8612         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
8613 }
8614
8615 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
8616 {
8617         uint32_t dspclk_gate;
8618
8619         I915_WRITE(RENCLK_GATE_D1, 0);
8620         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8621                    GS_UNIT_CLOCK_GATE_DISABLE |
8622                    CL_UNIT_CLOCK_GATE_DISABLE);
8623         I915_WRITE(RAMCLK_GATE_D, 0);
8624         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8625                 OVRUNIT_CLOCK_GATE_DISABLE |
8626                 OVCUNIT_CLOCK_GATE_DISABLE;
8627         if (IS_GM45(dev_priv))
8628                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8629         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8630
8631         /* WaDisableRenderCachePipelinedFlush */
8632         I915_WRITE(CACHE_MODE_0,
8633                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
8634
8635         /* WaDisable_RenderCache_OperationalFlush:g4x */
8636         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8637
8638         g4x_disable_trickle_feed(dev_priv);
8639 }
8640
8641 static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
8642 {
8643         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8644         I915_WRITE(RENCLK_GATE_D2, 0);
8645         I915_WRITE(DSPCLK_GATE_D, 0);
8646         I915_WRITE(RAMCLK_GATE_D, 0);
8647         I915_WRITE16(DEUC, 0);
8648         I915_WRITE(MI_ARB_STATE,
8649                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
8650
8651         /* WaDisable_RenderCache_OperationalFlush:gen4 */
8652         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8653 }
8654
8655 static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
8656 {
8657         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8658                    I965_RCC_CLOCK_GATE_DISABLE |
8659                    I965_RCPB_CLOCK_GATE_DISABLE |
8660                    I965_ISC_CLOCK_GATE_DISABLE |
8661                    I965_FBC_CLOCK_GATE_DISABLE);
8662         I915_WRITE(RENCLK_GATE_D2, 0);
8663         I915_WRITE(MI_ARB_STATE,
8664                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
8665
8666         /* WaDisable_RenderCache_OperationalFlush:gen4 */
8667         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8668 }
8669
8670 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
8671 {
8672         u32 dstate = I915_READ(D_STATE);
8673
8674         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8675                 DSTATE_DOT_CLOCK_GATING;
8676         I915_WRITE(D_STATE, dstate);
8677
8678         if (IS_PINEVIEW(dev_priv))
8679                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
8680
8681         /* IIR "flip pending" means done if this bit is set */
8682         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
8683
8684         /* interrupts should cause a wake up from C3 */
8685         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
8686
8687         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
8688         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
8689
8690         I915_WRITE(MI_ARB_STATE,
8691                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
8692 }
8693
8694 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
8695 {
8696         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8697
8698         /* interrupts should cause a wake up from C3 */
8699         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
8700                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
8701
8702         I915_WRITE(MEM_MODE,
8703                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
8704 }
8705
8706 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
8707 {
8708         I915_WRITE(MEM_MODE,
8709                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
8710                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
8711 }
8712
8713 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
8714 {
8715         dev_priv->display.init_clock_gating(dev_priv);
8716 }
8717
8718 void intel_suspend_hw(struct drm_i915_private *dev_priv)
8719 {
8720         if (HAS_PCH_LPT(dev_priv))
8721                 lpt_suspend_hw(dev_priv);
8722 }
8723
8724 static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
8725 {
8726         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
8727 }
8728
8729 /**
8730  * intel_init_clock_gating_hooks - setup the clock gating hooks
8731  * @dev_priv: device private
8732  *
8733  * Setup the hooks that configure which clocks of a given platform can be
8734  * gated and also apply various GT and display specific workarounds for these
8735  * platforms. Note that some GT specific workarounds are applied separately
8736  * when GPU contexts or batchbuffers start their execution.
8737  */
8738 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
8739 {
8740         if (IS_SKYLAKE(dev_priv))
8741                 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
8742         else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
8743                 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
8744         else if (IS_BROXTON(dev_priv))
8745                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
8746         else if (IS_GEMINILAKE(dev_priv))
8747                 dev_priv->display.init_clock_gating = glk_init_clock_gating;
8748         else if (IS_BROADWELL(dev_priv))
8749                 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
8750         else if (IS_CHERRYVIEW(dev_priv))
8751                 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
8752         else if (IS_HASWELL(dev_priv))
8753                 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
8754         else if (IS_IVYBRIDGE(dev_priv))
8755                 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8756         else if (IS_VALLEYVIEW(dev_priv))
8757                 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
8758         else if (IS_GEN6(dev_priv))
8759                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8760         else if (IS_GEN5(dev_priv))
8761                 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8762         else if (IS_G4X(dev_priv))
8763                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8764         else if (IS_I965GM(dev_priv))
8765                 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8766         else if (IS_I965G(dev_priv))
8767                 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8768         else if (IS_GEN3(dev_priv))
8769                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8770         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
8771                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8772         else if (IS_GEN2(dev_priv))
8773                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8774         else {
8775                 MISSING_CASE(INTEL_DEVID(dev_priv));
8776                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
8777         }
8778 }
8779
8780 /* Set up chip specific power management-related functions */
8781 void intel_init_pm(struct drm_i915_private *dev_priv)
8782 {
8783         intel_fbc_init(dev_priv);
8784
8785         /* For cxsr */
8786         if (IS_PINEVIEW(dev_priv))
8787                 i915_pineview_get_mem_freq(dev_priv);
8788         else if (IS_GEN5(dev_priv))
8789                 i915_ironlake_get_mem_freq(dev_priv);
8790
8791         /* For FIFO watermark updates */
8792         if (INTEL_GEN(dev_priv) >= 9) {
8793                 skl_setup_wm_latency(dev_priv);
8794                 dev_priv->display.initial_watermarks = skl_initial_wm;
8795                 dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
8796                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
8797         } else if (HAS_PCH_SPLIT(dev_priv)) {
8798                 ilk_setup_wm_latency(dev_priv);
8799
8800                 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
8801                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
8802                     (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
8803                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
8804                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
8805                         dev_priv->display.compute_intermediate_wm =
8806                                 ilk_compute_intermediate_wm;
8807                         dev_priv->display.initial_watermarks =
8808                                 ilk_initial_watermarks;
8809                         dev_priv->display.optimize_watermarks =
8810                                 ilk_optimize_watermarks;
8811                 } else {
8812                         DRM_DEBUG_KMS("Failed to read display plane latency. "
8813                                       "Disable CxSR\n");
8814                 }
8815         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
8816                 vlv_setup_wm_latency(dev_priv);
8817                 dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;
8818                 dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;
8819                 dev_priv->display.initial_watermarks = vlv_initial_watermarks;
8820                 dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;
8821                 dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo;
8822         } else if (IS_G4X(dev_priv)) {
8823                 g4x_setup_wm_latency(dev_priv);
8824                 dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm;
8825                 dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm;
8826                 dev_priv->display.initial_watermarks = g4x_initial_watermarks;
8827                 dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;
8828         } else if (IS_PINEVIEW(dev_priv)) {
8829                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
8830                                             dev_priv->is_ddr3,
8831                                             dev_priv->fsb_freq,
8832                                             dev_priv->mem_freq)) {
8833                         DRM_INFO("failed to find known CxSR latency "
8834                                  "(found ddr%s fsb freq %d, mem freq %d), "
8835                                  "disabling CxSR\n",
8836                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
8837                                  dev_priv->fsb_freq, dev_priv->mem_freq);
8838                         /* Disable CxSR and never update its watermark again */
8839                         intel_set_memory_cxsr(dev_priv, false);
8840                         dev_priv->display.update_wm = NULL;
8841                 } else
8842                         dev_priv->display.update_wm = pineview_update_wm;
8843         } else if (IS_GEN4(dev_priv)) {
8844                 dev_priv->display.update_wm = i965_update_wm;
8845         } else if (IS_GEN3(dev_priv)) {
8846                 dev_priv->display.update_wm = i9xx_update_wm;
8847                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8848         } else if (IS_GEN2(dev_priv)) {
8849                 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
8850                         dev_priv->display.update_wm = i845_update_wm;
8851                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
8852                 } else {
8853                         dev_priv->display.update_wm = i9xx_update_wm;
8854                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
8855                 }
8856         } else {
8857                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
8858         }
8859 }
8860
8861 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
8862 {
8863         uint32_t flags =
8864                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
8865
8866         switch (flags) {
8867         case GEN6_PCODE_SUCCESS:
8868                 return 0;
8869         case GEN6_PCODE_UNIMPLEMENTED_CMD:
8870                 return -ENODEV;
8871         case GEN6_PCODE_ILLEGAL_CMD:
8872                 return -ENXIO;
8873         case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
8874         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
8875                 return -EOVERFLOW;
8876         case GEN6_PCODE_TIMEOUT:
8877                 return -ETIMEDOUT;
8878         default:
8879                 MISSING_CASE(flags);
8880                 return 0;
8881         }
8882 }
8883
8884 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
8885 {
8886         uint32_t flags =
8887                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
8888
8889         switch (flags) {
8890         case GEN6_PCODE_SUCCESS:
8891                 return 0;
8892         case GEN6_PCODE_ILLEGAL_CMD:
8893                 return -ENXIO;
8894         case GEN7_PCODE_TIMEOUT:
8895                 return -ETIMEDOUT;
8896         case GEN7_PCODE_ILLEGAL_DATA:
8897                 return -EINVAL;
8898         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
8899                 return -EOVERFLOW;
8900         default:
8901                 MISSING_CASE(flags);
8902                 return 0;
8903         }
8904 }
8905
8906 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
8907 {
8908         int status;
8909
8910         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
8911
8912         /* GEN6_PCODE_* are outside of the forcewake domain, we can
8913          * use te fw I915_READ variants to reduce the amount of work
8914          * required when reading/writing.
8915          */
8916
8917         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
8918                 DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps\n",
8919                                  mbox, __builtin_return_address(0));
8920                 return -EAGAIN;
8921         }
8922
8923         I915_WRITE_FW(GEN6_PCODE_DATA, *val);
8924         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
8925         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
8926
8927         if (__intel_wait_for_register_fw(dev_priv,
8928                                          GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
8929                                          500, 0, NULL)) {
8930                 DRM_ERROR("timeout waiting for pcode read (from mbox %x) to finish for %ps\n",
8931                           mbox, __builtin_return_address(0));
8932                 return -ETIMEDOUT;
8933         }
8934
8935         *val = I915_READ_FW(GEN6_PCODE_DATA);
8936         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
8937
8938         if (INTEL_GEN(dev_priv) > 6)
8939                 status = gen7_check_mailbox_status(dev_priv);
8940         else
8941                 status = gen6_check_mailbox_status(dev_priv);
8942
8943         if (status) {
8944                 DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
8945                                  mbox, __builtin_return_address(0), status);
8946                 return status;
8947         }
8948
8949         return 0;
8950 }
8951
8952 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
8953                             u32 mbox, u32 val)
8954 {
8955         int status;
8956
8957         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
8958
8959         /* GEN6_PCODE_* are outside of the forcewake domain, we can
8960          * use te fw I915_READ variants to reduce the amount of work
8961          * required when reading/writing.
8962          */
8963
8964         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
8965                 DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps\n",
8966                                  val, mbox, __builtin_return_address(0));
8967                 return -EAGAIN;
8968         }
8969
8970         I915_WRITE_FW(GEN6_PCODE_DATA, val);
8971         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
8972         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
8973
8974         if (__intel_wait_for_register_fw(dev_priv,
8975                                          GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
8976                                          500, 0, NULL)) {
8977                 DRM_ERROR("timeout waiting for pcode write of 0x%08x to mbox %x to finish for %ps\n",
8978                           val, mbox, __builtin_return_address(0));
8979                 return -ETIMEDOUT;
8980         }
8981
8982         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
8983
8984         if (INTEL_GEN(dev_priv) > 6)
8985                 status = gen7_check_mailbox_status(dev_priv);
8986         else
8987                 status = gen6_check_mailbox_status(dev_priv);
8988
8989         if (status) {
8990                 DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
8991                                  val, mbox, __builtin_return_address(0), status);
8992                 return status;
8993         }
8994
8995         return 0;
8996 }
8997
8998 static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
8999                                   u32 request, u32 reply_mask, u32 reply,
9000                                   u32 *status)
9001 {
9002         u32 val = request;
9003
9004         *status = sandybridge_pcode_read(dev_priv, mbox, &val);
9005
9006         return *status || ((val & reply_mask) == reply);
9007 }
9008
9009 /**
9010  * skl_pcode_request - send PCODE request until acknowledgment
9011  * @dev_priv: device private
9012  * @mbox: PCODE mailbox ID the request is targeted for
9013  * @request: request ID
9014  * @reply_mask: mask used to check for request acknowledgment
9015  * @reply: value used to check for request acknowledgment
9016  * @timeout_base_ms: timeout for polling with preemption enabled
9017  *
9018  * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
9019  * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
9020  * The request is acknowledged once the PCODE reply dword equals @reply after
9021  * applying @reply_mask. Polling is first attempted with preemption enabled
9022  * for @timeout_base_ms and if this times out for another 50 ms with
9023  * preemption disabled.
9024  *
9025  * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
9026  * other error as reported by PCODE.
9027  */
9028 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
9029                       u32 reply_mask, u32 reply, int timeout_base_ms)
9030 {
9031         u32 status;
9032         int ret;
9033
9034         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
9035
9036 #define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
9037                                    &status)
9038
9039         /*
9040          * Prime the PCODE by doing a request first. Normally it guarantees
9041          * that a subsequent request, at most @timeout_base_ms later, succeeds.
9042          * _wait_for() doesn't guarantee when its passed condition is evaluated
9043          * first, so send the first request explicitly.
9044          */
9045         if (COND) {
9046                 ret = 0;
9047                 goto out;
9048         }
9049         ret = _wait_for(COND, timeout_base_ms * 1000, 10);
9050         if (!ret)
9051                 goto out;
9052
9053         /*
9054          * The above can time out if the number of requests was low (2 in the
9055          * worst case) _and_ PCODE was busy for some reason even after a
9056          * (queued) request and @timeout_base_ms delay. As a workaround retry
9057          * the poll with preemption disabled to maximize the number of
9058          * requests. Increase the timeout from @timeout_base_ms to 50ms to
9059          * account for interrupts that could reduce the number of these
9060          * requests, and for any quirks of the PCODE firmware that delays
9061          * the request completion.
9062          */
9063         DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
9064         WARN_ON_ONCE(timeout_base_ms > 3);
9065         preempt_disable();
9066         ret = wait_for_atomic(COND, 50);
9067         preempt_enable();
9068
9069 out:
9070         return ret ? ret : status;
9071 #undef COND
9072 }
9073
9074 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
9075 {
9076         /*
9077          * N = val - 0xb7
9078          * Slow = Fast = GPLL ref * N
9079          */
9080         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
9081 }
9082
9083 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
9084 {
9085         return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
9086 }
9087
9088 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
9089 {
9090         /*
9091          * N = val / 2
9092          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
9093          */
9094         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
9095 }
9096
9097 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
9098 {
9099         /* CHV needs even values */
9100         return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
9101 }
9102
9103 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
9104 {
9105         if (INTEL_GEN(dev_priv) >= 9)
9106                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
9107                                          GEN9_FREQ_SCALER);
9108         else if (IS_CHERRYVIEW(dev_priv))
9109                 return chv_gpu_freq(dev_priv, val);
9110         else if (IS_VALLEYVIEW(dev_priv))
9111                 return byt_gpu_freq(dev_priv, val);
9112         else
9113                 return val * GT_FREQUENCY_MULTIPLIER;
9114 }
9115
9116 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
9117 {
9118         if (INTEL_GEN(dev_priv) >= 9)
9119                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
9120                                          GT_FREQUENCY_MULTIPLIER);
9121         else if (IS_CHERRYVIEW(dev_priv))
9122                 return chv_freq_opcode(dev_priv, val);
9123         else if (IS_VALLEYVIEW(dev_priv))
9124                 return byt_freq_opcode(dev_priv, val);
9125         else
9126                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
9127 }
9128
9129 struct request_boost {
9130         struct work_struct work;
9131         struct drm_i915_gem_request *req;
9132 };
9133
9134 static void __intel_rps_boost_work(struct work_struct *work)
9135 {
9136         struct request_boost *boost = container_of(work, struct request_boost, work);
9137         struct drm_i915_gem_request *req = boost->req;
9138
9139         if (!i915_gem_request_completed(req))
9140                 gen6_rps_boost(req, NULL);
9141
9142         i915_gem_request_put(req);
9143         kfree(boost);
9144 }
9145
9146 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
9147 {
9148         struct request_boost *boost;
9149
9150         if (req == NULL || INTEL_GEN(req->i915) < 6)
9151                 return;
9152
9153         if (i915_gem_request_completed(req))
9154                 return;
9155
9156         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
9157         if (boost == NULL)
9158                 return;
9159
9160         boost->req = i915_gem_request_get(req);
9161
9162         INIT_WORK(&boost->work, __intel_rps_boost_work);
9163         queue_work(req->i915->wq, &boost->work);
9164 }
9165
9166 void intel_pm_setup(struct drm_i915_private *dev_priv)
9167 {
9168         mutex_init(&dev_priv->rps.hw_lock);
9169
9170         INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
9171                           __intel_autoenable_gt_powersave);
9172         atomic_set(&dev_priv->rps.num_waiters, 0);
9173
9174         dev_priv->pm.suspended = false;
9175         atomic_set(&dev_priv->pm.wakeref_count, 0);
9176 }
9177
9178 static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
9179                              const i915_reg_t reg)
9180 {
9181         u32 lower, upper, tmp;
9182         int loop = 2;
9183
9184         /* The register accessed do not need forcewake. We borrow
9185          * uncore lock to prevent concurrent access to range reg.
9186          */
9187         spin_lock_irq(&dev_priv->uncore.lock);
9188
9189         /* vlv and chv residency counters are 40 bits in width.
9190          * With a control bit, we can choose between upper or lower
9191          * 32bit window into this counter.
9192          *
9193          * Although we always use the counter in high-range mode elsewhere,
9194          * userspace may attempt to read the value before rc6 is initialised,
9195          * before we have set the default VLV_COUNTER_CONTROL value. So always
9196          * set the high bit to be safe.
9197          */
9198         I915_WRITE_FW(VLV_COUNTER_CONTROL,
9199                       _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
9200         upper = I915_READ_FW(reg);
9201         do {
9202                 tmp = upper;
9203
9204                 I915_WRITE_FW(VLV_COUNTER_CONTROL,
9205                               _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
9206                 lower = I915_READ_FW(reg);
9207
9208                 I915_WRITE_FW(VLV_COUNTER_CONTROL,
9209                               _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
9210                 upper = I915_READ_FW(reg);
9211         } while (upper != tmp && --loop);
9212
9213         /* Everywhere else we always use VLV_COUNTER_CONTROL with the
9214          * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
9215          * now.
9216          */
9217
9218         spin_unlock_irq(&dev_priv->uncore.lock);
9219
9220         return lower | (u64)upper << 8;
9221 }
9222
9223 u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
9224                            const i915_reg_t reg)
9225 {
9226         u64 time_hw, units, div;
9227
9228         if (!intel_enable_rc6())
9229                 return 0;
9230
9231         intel_runtime_pm_get(dev_priv);
9232
9233         /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
9234         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
9235                 units = 1000;
9236                 div = dev_priv->czclk_freq;
9237
9238                 time_hw = vlv_residency_raw(dev_priv, reg);
9239         } else if (IS_GEN9_LP(dev_priv)) {
9240                 units = 1000;
9241                 div = 1200;             /* 833.33ns */
9242
9243                 time_hw = I915_READ(reg);
9244         } else {
9245                 units = 128000; /* 1.28us */
9246                 div = 100000;
9247
9248                 time_hw = I915_READ(reg);
9249         }
9250
9251         intel_runtime_pm_put(dev_priv);
9252         return DIV_ROUND_UP_ULL(time_hw * units, div);
9253 }