1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
29 #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
31 #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
33 #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
34 #define _MASKED_BIT_DISABLE(a) ((a) << 16)
37 * The Bridge device's PCI config space has information about the
38 * fb aperture size and the amount of pre-reserved memory.
39 * This is all handled in the intel-gtt.ko module. i915.ko only
40 * cares about the vga bit for the vga rbiter.
42 #define INTEL_GMCH_CTRL 0x52
43 #define INTEL_GMCH_VGA_DISABLE (1 << 1)
44 #define SNB_GMCH_CTRL 0x50
45 #define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */
46 #define SNB_GMCH_GGMS_MASK 0x3
47 #define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */
48 #define SNB_GMCH_GMS_MASK 0x1f
51 /* PCI config space */
53 #define HPLLCC 0xc0 /* 855 only */
54 #define GC_CLOCK_CONTROL_MASK (0xf << 0)
55 #define GC_CLOCK_133_200 (0 << 0)
56 #define GC_CLOCK_100_200 (1 << 0)
57 #define GC_CLOCK_100_133 (2 << 0)
58 #define GC_CLOCK_166_250 (3 << 0)
60 #define GCFGC 0xf0 /* 915+ only */
61 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
62 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
63 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
64 #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
65 #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
66 #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
67 #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
68 #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
69 #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
70 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
71 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
72 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
73 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
74 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
75 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
76 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
77 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
78 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
79 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
80 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
81 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
82 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
83 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
84 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
85 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
86 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
87 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
88 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
89 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
92 /* Graphics reset regs */
93 #define I965_GDRST 0xc0 /* PCI config register */
94 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */
95 #define GRDOM_FULL (0<<2)
96 #define GRDOM_RENDER (1<<2)
97 #define GRDOM_MEDIA (3<<2)
98 #define GRDOM_MASK (3<<2)
99 #define GRDOM_RESET_ENABLE (1<<0)
101 #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
102 #define GEN6_MBC_SNPCR_SHIFT 21
103 #define GEN6_MBC_SNPCR_MASK (3<<21)
104 #define GEN6_MBC_SNPCR_MAX (0<<21)
105 #define GEN6_MBC_SNPCR_MED (1<<21)
106 #define GEN6_MBC_SNPCR_LOW (2<<21)
107 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
109 #define GEN6_MBCTL 0x0907c
110 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
111 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
112 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
113 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
114 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
116 #define GEN6_GDRST 0x941c
117 #define GEN6_GRDOM_FULL (1 << 0)
118 #define GEN6_GRDOM_RENDER (1 << 1)
119 #define GEN6_GRDOM_MEDIA (1 << 2)
120 #define GEN6_GRDOM_BLT (1 << 3)
122 #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
123 #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
124 #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
125 #define PP_DIR_DCLV_2G 0xffffffff
127 #define GAM_ECOCHK 0x4090
128 #define ECOCHK_SNB_BIT (1<<10)
129 #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6)
130 #define ECOCHK_PPGTT_CACHE64B (0x3<<3)
131 #define ECOCHK_PPGTT_CACHE4B (0x0<<3)
132 #define ECOCHK_PPGTT_GFDT_IVB (0x1<<4)
133 #define ECOCHK_PPGTT_LLC_IVB (0x1<<3)
134 #define ECOCHK_PPGTT_UC_HSW (0x1<<3)
135 #define ECOCHK_PPGTT_WT_HSW (0x2<<3)
136 #define ECOCHK_PPGTT_WB_HSW (0x3<<3)
138 #define GAC_ECO_BITS 0x14090
139 #define ECOBITS_SNB_BIT (1<<13)
140 #define ECOBITS_PPGTT_CACHE64B (3<<8)
141 #define ECOBITS_PPGTT_CACHE4B (0<<8)
143 #define GAB_CTL 0x24000
144 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
148 #define VGA_ST01_MDA 0x3ba
149 #define VGA_ST01_CGA 0x3da
151 #define VGA_MSR_WRITE 0x3c2
152 #define VGA_MSR_READ 0x3cc
153 #define VGA_MSR_MEM_EN (1<<1)
154 #define VGA_MSR_CGA_MODE (1<<0)
156 #define VGA_SR_INDEX 0x3c4
158 #define VGA_SR_DATA 0x3c5
160 #define VGA_AR_INDEX 0x3c0
161 #define VGA_AR_VID_EN (1<<5)
162 #define VGA_AR_DATA_WRITE 0x3c0
163 #define VGA_AR_DATA_READ 0x3c1
165 #define VGA_GR_INDEX 0x3ce
166 #define VGA_GR_DATA 0x3cf
168 #define VGA_GR_MEM_READ_MODE_SHIFT 3
169 #define VGA_GR_MEM_READ_MODE_PLANE 1
171 #define VGA_GR_MEM_MODE_MASK 0xc
172 #define VGA_GR_MEM_MODE_SHIFT 2
173 #define VGA_GR_MEM_A0000_AFFFF 0
174 #define VGA_GR_MEM_A0000_BFFFF 1
175 #define VGA_GR_MEM_B0000_B7FFF 2
176 #define VGA_GR_MEM_B0000_BFFFF 3
178 #define VGA_DACMASK 0x3c6
179 #define VGA_DACRX 0x3c7
180 #define VGA_DACWX 0x3c8
181 #define VGA_DACDATA 0x3c9
183 #define VGA_CR_INDEX_MDA 0x3b4
184 #define VGA_CR_DATA_MDA 0x3b5
185 #define VGA_CR_INDEX_CGA 0x3d4
186 #define VGA_CR_DATA_CGA 0x3d5
189 * Memory interface instructions used by the kernel
191 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
193 #define MI_NOOP MI_INSTR(0, 0)
194 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
195 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
196 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
197 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
198 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
199 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
200 #define MI_FLUSH MI_INSTR(0x04, 0)
201 #define MI_READ_FLUSH (1 << 0)
202 #define MI_EXE_FLUSH (1 << 1)
203 #define MI_NO_WRITE_FLUSH (1 << 2)
204 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
205 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
206 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
207 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
208 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
209 #define MI_SUSPEND_FLUSH_EN (1<<0)
210 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
211 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
212 #define MI_OVERLAY_CONTINUE (0x0<<21)
213 #define MI_OVERLAY_ON (0x1<<21)
214 #define MI_OVERLAY_OFF (0x2<<21)
215 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
216 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
217 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
218 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
219 /* IVB has funny definitions for which plane to flip. */
220 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
221 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
222 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
223 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
224 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
225 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
226 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
227 #define MI_ARB_ENABLE (1<<0)
228 #define MI_ARB_DISABLE (0<<0)
230 #define MI_SET_CONTEXT MI_INSTR(0x18, 0)
231 #define MI_MM_SPACE_GTT (1<<8)
232 #define MI_MM_SPACE_PHYSICAL (0<<8)
233 #define MI_SAVE_EXT_STATE_EN (1<<3)
234 #define MI_RESTORE_EXT_STATE_EN (1<<2)
235 #define MI_FORCE_RESTORE (1<<1)
236 #define MI_RESTORE_INHIBIT (1<<0)
237 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
238 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
239 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
240 #define MI_STORE_DWORD_INDEX_SHIFT 2
241 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
242 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
243 * simply ignores the register load under certain conditions.
244 * - One can actually load arbitrary many arbitrary registers: Simply issue x
245 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
247 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
248 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
249 #define MI_FLUSH_DW_STORE_INDEX (1<<21)
250 #define MI_INVALIDATE_TLB (1<<18)
251 #define MI_FLUSH_DW_OP_STOREDW (1<<14)
252 #define MI_INVALIDATE_BSD (1<<7)
253 #define MI_FLUSH_DW_USE_GTT (1<<2)
254 #define MI_FLUSH_DW_USE_PPGTT (0<<2)
255 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
256 #define MI_BATCH_NON_SECURE (1)
257 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
258 #define MI_BATCH_NON_SECURE_I965 (1<<8)
259 #define MI_BATCH_PPGTT_HSW (1<<8)
260 #define MI_BATCH_NON_SECURE_HSW (1<<13)
261 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
262 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
263 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
264 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
265 #define MI_SEMAPHORE_UPDATE (1<<21)
266 #define MI_SEMAPHORE_COMPARE (1<<20)
267 #define MI_SEMAPHORE_REGISTER (1<<18)
268 #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
269 #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
270 #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
271 #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
272 #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
273 #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
274 #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
275 #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
276 #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
277 #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
278 #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
279 #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
280 #define MI_SEMAPHORE_SYNC_INVALID (3<<16)
282 * 3D instructions used by the kernel
284 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
286 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
287 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
288 #define SC_UPDATE_SCISSOR (0x1<<1)
289 #define SC_ENABLE_MASK (0x1<<0)
290 #define SC_ENABLE (0x1<<0)
291 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
292 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
293 #define SCI_YMIN_MASK (0xffff<<16)
294 #define SCI_XMIN_MASK (0xffff<<0)
295 #define SCI_YMAX_MASK (0xffff<<16)
296 #define SCI_XMAX_MASK (0xffff<<0)
297 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
298 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
299 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
300 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
301 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
302 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
303 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
304 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
305 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
306 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
307 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
308 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
309 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
310 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
311 #define BLT_DEPTH_8 (0<<24)
312 #define BLT_DEPTH_16_565 (1<<24)
313 #define BLT_DEPTH_16_1555 (2<<24)
314 #define BLT_DEPTH_32 (3<<24)
315 #define BLT_ROP_GXCOPY (0xcc<<16)
316 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
317 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
318 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
319 #define ASYNC_FLIP (1<<22)
320 #define DISPLAY_PLANE_A (0<<20)
321 #define DISPLAY_PLANE_B (1<<20)
322 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
323 #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
324 #define PIPE_CONTROL_CS_STALL (1<<20)
325 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
326 #define PIPE_CONTROL_QW_WRITE (1<<14)
327 #define PIPE_CONTROL_DEPTH_STALL (1<<13)
328 #define PIPE_CONTROL_WRITE_FLUSH (1<<12)
329 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
330 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
331 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
332 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
333 #define PIPE_CONTROL_NOTIFY (1<<8)
334 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
335 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
336 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
337 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
338 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
339 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
345 #define DEBUG_RESET_I830 0x6070
346 #define DEBUG_RESET_FULL (1<<7)
347 #define DEBUG_RESET_RENDER (1<<8)
348 #define DEBUG_RESET_DISPLAY (1<<9)
353 #define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100)
354 #define IOSF_DEVFN_SHIFT 24
355 #define IOSF_OPCODE_SHIFT 16
356 #define IOSF_PORT_SHIFT 8
357 #define IOSF_BYTE_ENABLES_SHIFT 4
358 #define IOSF_BAR_SHIFT 1
359 #define IOSF_SB_BUSY (1<<0)
360 #define IOSF_PORT_PUNIT 0x4
361 #define IOSF_PORT_NC 0x11
362 #define IOSF_PORT_DPIO 0x12
363 #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
364 #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
366 #define PUNIT_OPCODE_REG_READ 6
367 #define PUNIT_OPCODE_REG_WRITE 7
369 #define PUNIT_REG_GPU_LFM 0xd3
370 #define PUNIT_REG_GPU_FREQ_REQ 0xd4
371 #define PUNIT_REG_GPU_FREQ_STS 0xd8
372 #define GENFREQSTATUS (1<<0)
373 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
375 #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
376 #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
378 #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
379 #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
380 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
381 #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
382 #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
383 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
384 #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
385 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
386 #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
387 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
390 * DPIO - a special bus for various display related registers to hide behind
394 * Note: digital port B is DDI0, digital pot C is DDI1
397 #define DPIO_OPCODE_REG_WRITE 1
398 #define DPIO_OPCODE_REG_READ 0
400 #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)
401 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
402 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
403 #define DPIO_SFR_BYPASS (1<<1)
404 #define DPIO_RESET (1<<0)
406 #define _DPIO_TX3_SWING_CTL4_A 0x690
407 #define _DPIO_TX3_SWING_CTL4_B 0x2a90
408 #define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX_SWING_CTL4_A, \
409 _DPIO_TX3_SWING_CTL4_B)
412 * Per pipe/PLL DPIO regs
414 #define _DPIO_DIV_A 0x800c
415 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
416 #define DPIO_POST_DIV_DAC 0
417 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
418 #define DPIO_POST_DIV_LVDS1 2
419 #define DPIO_POST_DIV_LVDS2 3
420 #define DPIO_K_SHIFT (24) /* 4 bits */
421 #define DPIO_P1_SHIFT (21) /* 3 bits */
422 #define DPIO_P2_SHIFT (16) /* 5 bits */
423 #define DPIO_N_SHIFT (12) /* 4 bits */
424 #define DPIO_ENABLE_CALIBRATION (1<<11)
425 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */
426 #define DPIO_M2DIV_MASK 0xff
427 #define _DPIO_DIV_B 0x802c
428 #define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B)
430 #define _DPIO_REFSFR_A 0x8014
431 #define DPIO_REFSEL_OVERRIDE 27
432 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
433 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
434 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
435 #define DPIO_PLL_REFCLK_SEL_MASK 3
436 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
437 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
438 #define _DPIO_REFSFR_B 0x8034
439 #define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B)
441 #define _DPIO_CORE_CLK_A 0x801c
442 #define _DPIO_CORE_CLK_B 0x803c
443 #define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B)
445 #define _DPIO_IREF_CTL_A 0x8040
446 #define _DPIO_IREF_CTL_B 0x8060
447 #define DPIO_IREF_CTL(pipe) _PIPE(pipe, _DPIO_IREF_CTL_A, _DPIO_IREF_CTL_B)
449 #define DPIO_IREF_BCAST 0xc044
450 #define _DPIO_IREF_A 0x8044
451 #define _DPIO_IREF_B 0x8064
452 #define DPIO_IREF(pipe) _PIPE(pipe, _DPIO_IREF_A, _DPIO_IREF_B)
454 #define _DPIO_PLL_CML_A 0x804c
455 #define _DPIO_PLL_CML_B 0x806c
456 #define DPIO_PLL_CML(pipe) _PIPE(pipe, _DPIO_PLL_CML_A, _DPIO_PLL_CML_B)
458 #define _DPIO_LPF_COEFF_A 0x8048
459 #define _DPIO_LPF_COEFF_B 0x8068
460 #define DPIO_LPF_COEFF(pipe) _PIPE(pipe, _DPIO_LPF_COEFF_A, _DPIO_LPF_COEFF_B)
462 #define DPIO_CALIBRATION 0x80ac
464 #define DPIO_FASTCLK_DISABLE 0x8100
467 * Per DDI channel DPIO regs
470 #define _DPIO_PCS_TX_0 0x8200
471 #define _DPIO_PCS_TX_1 0x8400
472 #define DPIO_PCS_TX_LANE2_RESET (1<<16)
473 #define DPIO_PCS_TX_LANE1_RESET (1<<7)
474 #define DPIO_PCS_TX(port) _PORT(port, _DPIO_PCS_TX_0, _DPIO_PCS_TX_1)
476 #define _DPIO_PCS_CLK_0 0x8204
477 #define _DPIO_PCS_CLK_1 0x8404
478 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
479 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
480 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
481 #define DPIO_PCS_CLK_SOFT_RESET (1<<5)
482 #define DPIO_PCS_CLK(port) _PORT(port, _DPIO_PCS_CLK_0, _DPIO_PCS_CLK_1)
484 #define _DPIO_PCS_CTL_OVR1_A 0x8224
485 #define _DPIO_PCS_CTL_OVR1_B 0x8424
486 #define DPIO_PCS_CTL_OVER1(port) _PORT(port, _DPIO_PCS_CTL_OVR1_A, \
487 _DPIO_PCS_CTL_OVR1_B)
489 #define _DPIO_PCS_STAGGER0_A 0x822c
490 #define _DPIO_PCS_STAGGER0_B 0x842c
491 #define DPIO_PCS_STAGGER0(port) _PORT(port, _DPIO_PCS_STAGGER0_A, \
492 _DPIO_PCS_STAGGER0_B)
494 #define _DPIO_PCS_STAGGER1_A 0x8230
495 #define _DPIO_PCS_STAGGER1_B 0x8430
496 #define DPIO_PCS_STAGGER1(port) _PORT(port, _DPIO_PCS_STAGGER1_A, \
497 _DPIO_PCS_STAGGER1_B)
499 #define _DPIO_PCS_CLOCKBUF0_A 0x8238
500 #define _DPIO_PCS_CLOCKBUF0_B 0x8438
501 #define DPIO_PCS_CLOCKBUF0(port) _PORT(port, _DPIO_PCS_CLOCKBUF0_A, \
502 _DPIO_PCS_CLOCKBUF0_B)
504 #define _DPIO_PCS_CLOCKBUF8_A 0x825c
505 #define _DPIO_PCS_CLOCKBUF8_B 0x845c
506 #define DPIO_PCS_CLOCKBUF8(port) _PORT(port, _DPIO_PCS_CLOCKBUF8_A, \
507 _DPIO_PCS_CLOCKBUF8_B)
509 #define _DPIO_TX_SWING_CTL2_A 0x8288
510 #define _DPIO_TX_SWING_CTL2_B 0x8488
511 #define DPIO_TX_SWING_CTL2(port) _PORT(port, _DPIO_TX_SWING_CTL2_A, \
512 _DPIO_TX_SWING_CTL2_B)
514 #define _DPIO_TX_SWING_CTL3_A 0x828c
515 #define _DPIO_TX_SWING_CTL3_B 0x848c
516 #define DPIO_TX_SWING_CTL3(port) _PORT(port, _DPIO_TX_SWING_CTL3_A, \
517 _DPIO_TX_SWING_CTL3_B)
519 #define _DPIO_TX_SWING_CTL4_A 0x8290
520 #define _DPIO_TX_SWING_CTL4_B 0x8490
521 #define DPIO_TX_SWING_CTL4(port) _PORT(port, _DPIO_TX_SWING_CTL4_A, \
522 _DPIO_TX_SWING_CTL4_B)
524 #define _DPIO_TX_OCALINIT_0 0x8294
525 #define _DPIO_TX_OCALINIT_1 0x8494
526 #define DPIO_TX_OCALINIT_EN (1<<31)
527 #define DPIO_TX_OCALINIT(port) _PORT(port, _DPIO_TX_OCALINIT_0, \
530 #define _DPIO_TX_CTL_0 0x82ac
531 #define _DPIO_TX_CTL_1 0x84ac
532 #define DPIO_TX_CTL(port) _PORT(port, _DPIO_TX_CTL_0, _DPIO_TX_CTL_1)
534 #define _DPIO_TX_LANE_0 0x82b8
535 #define _DPIO_TX_LANE_1 0x84b8
536 #define DPIO_TX_LANE(port) _PORT(port, _DPIO_TX_LANE_0, _DPIO_TX_LANE_1)
538 #define _DPIO_DATA_CHANNEL1 0x8220
539 #define _DPIO_DATA_CHANNEL2 0x8420
540 #define DPIO_DATA_CHANNEL(port) _PORT(port, _DPIO_DATA_CHANNEL1, _DPIO_DATA_CHANNEL2)
542 #define _DPIO_PORT0_PCS0 0x0220
543 #define _DPIO_PORT0_PCS1 0x0420
544 #define _DPIO_PORT1_PCS2 0x2620
545 #define _DPIO_PORT1_PCS3 0x2820
546 #define DPIO_DATA_LANE_A(port) _PORT(port, _DPIO_PORT0_PCS0, _DPIO_PORT1_PCS2)
547 #define DPIO_DATA_LANE_B(port) _PORT(port, _DPIO_PORT0_PCS1, _DPIO_PORT1_PCS3)
548 #define DPIO_DATA_CHANNEL1 0x8220
549 #define DPIO_DATA_CHANNEL2 0x8420
554 #define FENCE_REG_830_0 0x2000
555 #define FENCE_REG_945_8 0x3000
556 #define I830_FENCE_START_MASK 0x07f80000
557 #define I830_FENCE_TILING_Y_SHIFT 12
558 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
559 #define I830_FENCE_PITCH_SHIFT 4
560 #define I830_FENCE_REG_VALID (1<<0)
561 #define I915_FENCE_MAX_PITCH_VAL 4
562 #define I830_FENCE_MAX_PITCH_VAL 6
563 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
565 #define I915_FENCE_START_MASK 0x0ff00000
566 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
568 #define FENCE_REG_965_0 0x03000
569 #define I965_FENCE_PITCH_SHIFT 2
570 #define I965_FENCE_TILING_Y_SHIFT 1
571 #define I965_FENCE_REG_VALID (1<<0)
572 #define I965_FENCE_MAX_PITCH_VAL 0x0400
574 #define FENCE_REG_SANDYBRIDGE_0 0x100000
575 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
576 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
578 /* control register for cpu gtt access */
579 #define TILECTL 0x101000
580 #define TILECTL_SWZCTL (1 << 0)
581 #define TILECTL_TLB_PREFETCH_DIS (1 << 2)
582 #define TILECTL_BACKSNOOP_DIS (1 << 3)
585 * Instruction and interrupt control regs
587 #define PGTBL_ER 0x02024
588 #define RENDER_RING_BASE 0x02000
589 #define BSD_RING_BASE 0x04000
590 #define GEN6_BSD_RING_BASE 0x12000
591 #define VEBOX_RING_BASE 0x1a000
592 #define BLT_RING_BASE 0x22000
593 #define RING_TAIL(base) ((base)+0x30)
594 #define RING_HEAD(base) ((base)+0x34)
595 #define RING_START(base) ((base)+0x38)
596 #define RING_CTL(base) ((base)+0x3c)
597 #define RING_SYNC_0(base) ((base)+0x40)
598 #define RING_SYNC_1(base) ((base)+0x44)
599 #define RING_SYNC_2(base) ((base)+0x48)
600 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
601 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
602 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
603 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
604 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
605 #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
606 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
607 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
608 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
609 #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
610 #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
611 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
612 #define GEN6_NOSYNC 0
613 #define RING_MAX_IDLE(base) ((base)+0x54)
614 #define RING_HWS_PGA(base) ((base)+0x80)
615 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
616 #define ARB_MODE 0x04030
617 #define ARB_MODE_SWIZZLE_SNB (1<<4)
618 #define ARB_MODE_SWIZZLE_IVB (1<<5)
619 #define RENDER_HWS_PGA_GEN7 (0x04080)
620 #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
621 #define DONE_REG 0x40b0
622 #define BSD_HWS_PGA_GEN7 (0x04180)
623 #define BLT_HWS_PGA_GEN7 (0x04280)
624 #define VEBOX_HWS_PGA_GEN7 (0x04380)
625 #define RING_ACTHD(base) ((base)+0x74)
626 #define RING_NOPID(base) ((base)+0x94)
627 #define RING_IMR(base) ((base)+0xa8)
628 #define RING_TIMESTAMP(base) ((base)+0x358)
629 #define TAIL_ADDR 0x001FFFF8
630 #define HEAD_WRAP_COUNT 0xFFE00000
631 #define HEAD_WRAP_ONE 0x00200000
632 #define HEAD_ADDR 0x001FFFFC
633 #define RING_NR_PAGES 0x001FF000
634 #define RING_REPORT_MASK 0x00000006
635 #define RING_REPORT_64K 0x00000002
636 #define RING_REPORT_128K 0x00000004
637 #define RING_NO_REPORT 0x00000000
638 #define RING_VALID_MASK 0x00000001
639 #define RING_VALID 0x00000001
640 #define RING_INVALID 0x00000000
641 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
642 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
643 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
645 #define PRB0_TAIL 0x02030
646 #define PRB0_HEAD 0x02034
647 #define PRB0_START 0x02038
648 #define PRB0_CTL 0x0203c
649 #define PRB1_TAIL 0x02040 /* 915+ only */
650 #define PRB1_HEAD 0x02044 /* 915+ only */
651 #define PRB1_START 0x02048 /* 915+ only */
652 #define PRB1_CTL 0x0204c /* 915+ only */
654 #define IPEIR_I965 0x02064
655 #define IPEHR_I965 0x02068
656 #define INSTDONE_I965 0x0206c
657 #define GEN7_INSTDONE_1 0x0206c
658 #define GEN7_SC_INSTDONE 0x07100
659 #define GEN7_SAMPLER_INSTDONE 0x0e160
660 #define GEN7_ROW_INSTDONE 0x0e164
661 #define I915_NUM_INSTDONE_REG 4
662 #define RING_IPEIR(base) ((base)+0x64)
663 #define RING_IPEHR(base) ((base)+0x68)
664 #define RING_INSTDONE(base) ((base)+0x6c)
665 #define RING_INSTPS(base) ((base)+0x70)
666 #define RING_DMA_FADD(base) ((base)+0x78)
667 #define RING_INSTPM(base) ((base)+0xc0)
668 #define INSTPS 0x02070 /* 965+ only */
669 #define INSTDONE1 0x0207c /* 965+ only */
670 #define ACTHD_I965 0x02074
671 #define HWS_PGA 0x02080
672 #define HWS_ADDRESS_MASK 0xfffff000
673 #define HWS_START_ADDRESS_SHIFT 4
674 #define PWRCTXA 0x2088 /* 965GM+ only */
675 #define PWRCTX_EN (1<<0)
676 #define IPEIR 0x02088
677 #define IPEHR 0x0208c
678 #define INSTDONE 0x02090
679 #define NOPID 0x02094
680 #define HWSTAM 0x02098
681 #define DMA_FADD_I8XX 0x020d0
683 #define ERROR_GEN6 0x040a0
684 #define GEN7_ERR_INT 0x44040
685 #define ERR_INT_POISON (1<<31)
686 #define ERR_INT_MMIO_UNCLAIMED (1<<13)
687 #define ERR_INT_FIFO_UNDERRUN_C (1<<6)
688 #define ERR_INT_FIFO_UNDERRUN_B (1<<3)
689 #define ERR_INT_FIFO_UNDERRUN_A (1<<0)
690 #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
692 #define FPGA_DBG 0x42300
693 #define FPGA_DBG_RM_NOCLAIM (1<<31)
695 #define DERRMR 0x44050
697 /* GM45+ chicken bits -- debug workaround bits that may be required
698 * for various sorts of correct behavior. The top 16 bits of each are
699 * the enables for writing to the corresponding low bit.
701 #define _3D_CHICKEN 0x02084
702 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
703 #define _3D_CHICKEN2 0x0208c
704 /* Disables pipelining of read flushes past the SF-WIZ interface.
705 * Required on all Ironlake steppings according to the B-Spec, but the
706 * particular danger of not doing so is not specified.
708 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
709 #define _3D_CHICKEN3 0x02090
710 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
711 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
713 #define MI_MODE 0x0209c
714 # define VS_TIMER_DISPATCH (1 << 6)
715 # define MI_FLUSH_ENABLE (1 << 12)
716 # define ASYNC_FLIP_PERF_DISABLE (1 << 14)
718 #define GEN6_GT_MODE 0x20d0
719 #define GEN6_GT_MODE_HI (1 << 9)
720 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
722 #define GFX_MODE 0x02520
723 #define GFX_MODE_GEN7 0x0229c
724 #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
725 #define GFX_RUN_LIST_ENABLE (1<<15)
726 #define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
727 #define GFX_SURFACE_FAULT_ENABLE (1<<12)
728 #define GFX_REPLAY_MODE (1<<11)
729 #define GFX_PSMI_GRANULARITY (1<<10)
730 #define GFX_PPGTT_ENABLE (1<<9)
732 #define VLV_DISPLAY_BASE 0x180000
734 #define SCPD0 0x0209c /* 915+ only */
739 #define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
740 #define GCFG_DIS (1<<8)
741 #define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
742 #define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
743 #define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
744 #define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
745 #define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
746 #define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
747 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
751 #define GM45_ERROR_PAGE_TABLE (1<<5)
752 #define GM45_ERROR_MEM_PRIV (1<<4)
753 #define I915_ERROR_PAGE_TABLE (1<<4)
754 #define GM45_ERROR_CP_PRIV (1<<3)
755 #define I915_ERROR_MEMORY_REFRESH (1<<1)
756 #define I915_ERROR_INSTRUCTION (1<<0)
757 #define INSTPM 0x020c0
758 #define INSTPM_SELF_EN (1<<12) /* 915GM only */
759 #define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
760 will not assert AGPBUSY# and will only
761 be delivered when out of C3. */
762 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
763 #define ACTHD 0x020c8
764 #define FW_BLC 0x020d8
765 #define FW_BLC2 0x020dc
766 #define FW_BLC_SELF 0x020e0 /* 915+ only */
767 #define FW_BLC_SELF_EN_MASK (1<<31)
768 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
769 #define FW_BLC_SELF_EN (1<<15) /* 945 only */
770 #define MM_BURST_LENGTH 0x00700000
771 #define MM_FIFO_WATERMARK 0x0001F000
772 #define LM_BURST_LENGTH 0x00000700
773 #define LM_FIFO_WATERMARK 0x0000001F
774 #define MI_ARB_STATE 0x020e4 /* 915+ only */
776 /* Make render/texture TLB fetches lower priorty than associated data
777 * fetches. This is not turned on by default
779 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
781 /* Isoch request wait on GTT enable (Display A/B/C streams).
782 * Make isoch requests stall on the TLB update. May cause
783 * display underruns (test mode only)
785 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
787 /* Block grant count for isoch requests when block count is
788 * set to a finite value.
790 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
791 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
792 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
793 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
794 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
796 /* Enable render writes to complete in C2/C3/C4 power states.
797 * If this isn't enabled, render writes are prevented in low
798 * power states. That seems bad to me.
800 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
802 /* This acknowledges an async flip immediately instead
803 * of waiting for 2TLB fetches.
805 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
807 /* Enables non-sequential data reads through arbiter
809 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
811 /* Disable FSB snooping of cacheable write cycles from binner/render
814 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
816 /* Arbiter time slice for non-isoch streams */
817 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
818 #define MI_ARB_TIME_SLICE_1 (0 << 5)
819 #define MI_ARB_TIME_SLICE_2 (1 << 5)
820 #define MI_ARB_TIME_SLICE_4 (2 << 5)
821 #define MI_ARB_TIME_SLICE_6 (3 << 5)
822 #define MI_ARB_TIME_SLICE_8 (4 << 5)
823 #define MI_ARB_TIME_SLICE_10 (5 << 5)
824 #define MI_ARB_TIME_SLICE_14 (6 << 5)
825 #define MI_ARB_TIME_SLICE_16 (7 << 5)
827 /* Low priority grace period page size */
828 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
829 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
831 /* Disable display A/B trickle feed */
832 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
834 /* Set display plane priority */
835 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
836 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
838 #define CACHE_MODE_0 0x02120 /* 915+ only */
839 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
840 #define CM0_IZ_OPT_DISABLE (1<<6)
841 #define CM0_ZR_OPT_DISABLE (1<<5)
842 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
843 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
844 #define CM0_COLOR_EVICT_DISABLE (1<<3)
845 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
846 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
847 #define BB_ADDR 0x02140 /* 8 bytes */
848 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
849 #define GFX_FLSH_CNTL_GEN6 0x101008
850 #define GFX_FLSH_CNTL_EN (1<<0)
851 #define ECOSKPD 0x021d0
852 #define ECO_GATING_CX_ONLY (1<<3)
853 #define ECO_FLIP_DONE (1<<0)
855 #define CACHE_MODE_1 0x7004 /* IVB+ */
856 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
858 #define GEN6_BLITTER_ECOSKPD 0x221d0
859 #define GEN6_BLITTER_LOCK_SHIFT 16
860 #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
862 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
863 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
864 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
865 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
866 #define GEN6_BSD_GO_INDICATOR (1 << 4)
868 /* On modern GEN architectures interrupt control consists of two sets
869 * of registers. The first set pertains to the ring generating the
870 * interrupt. The second control is for the functional block generating the
871 * interrupt. These are PM, GT, DE, etc.
873 * Luckily *knocks on wood* all the ring interrupt bits match up with the
874 * GT interrupt bits, so we don't need to duplicate the defines.
876 * These defines should cover us well from SNB->HSW with minor exceptions
877 * it can also work on ILK.
879 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
880 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
881 #define GT_BLT_USER_INTERRUPT (1 << 22)
882 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
883 #define GT_BSD_USER_INTERRUPT (1 << 12)
884 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
885 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
886 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
887 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
888 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
889 #define GT_RENDER_USER_INTERRUPT (1 << 0)
891 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
892 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
894 /* These are all the "old" interrupts */
895 #define ILK_BSD_USER_INTERRUPT (1<<5)
896 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
897 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
898 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
899 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
900 #define I915_HWB_OOM_INTERRUPT (1<<13)
901 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
902 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
903 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
904 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
905 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
906 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
907 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
908 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
909 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
910 #define I915_DEBUG_INTERRUPT (1<<2)
911 #define I915_USER_INTERRUPT (1<<1)
912 #define I915_ASLE_INTERRUPT (1<<0)
913 #define I915_BSD_USER_INTERRUPT (1 << 25)
915 #define GEN6_BSD_RNCID 0x12198
917 #define GEN7_FF_THREAD_MODE 0x20a0
918 #define GEN7_FF_SCHED_MASK 0x0077070
919 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
920 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
921 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
922 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
923 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
924 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
925 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
926 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
927 #define GEN7_FF_VS_SCHED_HW (0x0<<12)
928 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
929 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
930 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
931 #define GEN7_FF_DS_SCHED_HW (0x0<<4)
934 * Framebuffer compression (915+ only)
937 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
938 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
939 #define FBC_CONTROL 0x03208
940 #define FBC_CTL_EN (1<<31)
941 #define FBC_CTL_PERIODIC (1<<30)
942 #define FBC_CTL_INTERVAL_SHIFT (16)
943 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
944 #define FBC_CTL_C3_IDLE (1<<13)
945 #define FBC_CTL_STRIDE_SHIFT (5)
946 #define FBC_CTL_FENCENO (1<<0)
947 #define FBC_COMMAND 0x0320c
948 #define FBC_CMD_COMPRESS (1<<0)
949 #define FBC_STATUS 0x03210
950 #define FBC_STAT_COMPRESSING (1<<31)
951 #define FBC_STAT_COMPRESSED (1<<30)
952 #define FBC_STAT_MODIFIED (1<<29)
953 #define FBC_STAT_CURRENT_LINE (1<<0)
954 #define FBC_CONTROL2 0x03214
955 #define FBC_CTL_FENCE_DBL (0<<4)
956 #define FBC_CTL_IDLE_IMM (0<<2)
957 #define FBC_CTL_IDLE_FULL (1<<2)
958 #define FBC_CTL_IDLE_LINE (2<<2)
959 #define FBC_CTL_IDLE_DEBUG (3<<2)
960 #define FBC_CTL_CPU_FENCE (1<<1)
961 #define FBC_CTL_PLANEA (0<<0)
962 #define FBC_CTL_PLANEB (1<<0)
963 #define FBC_FENCE_OFF 0x0321b
964 #define FBC_TAG 0x03300
966 #define FBC_LL_SIZE (1536)
968 /* Framebuffer compression for GM45+ */
969 #define DPFC_CB_BASE 0x3200
970 #define DPFC_CONTROL 0x3208
971 #define DPFC_CTL_EN (1<<31)
972 #define DPFC_CTL_PLANEA (0<<30)
973 #define DPFC_CTL_PLANEB (1<<30)
974 #define IVB_DPFC_CTL_PLANE_SHIFT (29)
975 #define DPFC_CTL_FENCE_EN (1<<29)
976 #define IVB_DPFC_CTL_FENCE_EN (1<<28)
977 #define DPFC_CTL_PERSISTENT_MODE (1<<25)
978 #define DPFC_SR_EN (1<<10)
979 #define DPFC_CTL_LIMIT_1X (0<<6)
980 #define DPFC_CTL_LIMIT_2X (1<<6)
981 #define DPFC_CTL_LIMIT_4X (2<<6)
982 #define DPFC_RECOMP_CTL 0x320c
983 #define DPFC_RECOMP_STALL_EN (1<<27)
984 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
985 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
986 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
987 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
988 #define DPFC_STATUS 0x3210
989 #define DPFC_INVAL_SEG_SHIFT (16)
990 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
991 #define DPFC_COMP_SEG_SHIFT (0)
992 #define DPFC_COMP_SEG_MASK (0x000003ff)
993 #define DPFC_STATUS2 0x3214
994 #define DPFC_FENCE_YOFF 0x3218
995 #define DPFC_CHICKEN 0x3224
996 #define DPFC_HT_MODIFY (1<<31)
998 /* Framebuffer compression for Ironlake */
999 #define ILK_DPFC_CB_BASE 0x43200
1000 #define ILK_DPFC_CONTROL 0x43208
1001 /* The bit 28-8 is reserved */
1002 #define DPFC_RESERVED (0x1FFFFF00)
1003 #define ILK_DPFC_RECOMP_CTL 0x4320c
1004 #define ILK_DPFC_STATUS 0x43210
1005 #define ILK_DPFC_FENCE_YOFF 0x43218
1006 #define ILK_DPFC_CHICKEN 0x43224
1007 #define ILK_FBC_RT_BASE 0x2128
1008 #define ILK_FBC_RT_VALID (1<<0)
1009 #define SNB_FBC_FRONT_BUFFER (1<<1)
1011 #define ILK_DISPLAY_CHICKEN1 0x42000
1012 #define ILK_FBCQ_DIS (1<<22)
1013 #define ILK_PABSTRETCH_DIS (1<<21)
1017 * Framebuffer compression for Sandybridge
1019 * The following two registers are of type GTTMMADR
1021 #define SNB_DPFC_CTL_SA 0x100100
1022 #define SNB_CPU_FENCE_ENABLE (1<<29)
1023 #define DPFC_CPU_FENCE_OFFSET 0x100104
1025 /* Framebuffer compression for Ivybridge */
1026 #define IVB_FBC_RT_BASE 0x7020
1028 #define IPS_CTL 0x43408
1029 #define IPS_ENABLE (1 << 31)
1031 #define MSG_FBC_REND_STATE 0x50380
1032 #define FBC_REND_NUKE (1<<2)
1033 #define FBC_REND_CACHE_CLEAN (1<<1)
1035 #define _HSW_PIPE_SLICE_CHICKEN_1_A 0x420B0
1036 #define _HSW_PIPE_SLICE_CHICKEN_1_B 0x420B4
1037 #define HSW_BYPASS_FBC_QUEUE (1<<22)
1038 #define HSW_PIPE_SLICE_CHICKEN_1(pipe) _PIPE(pipe, + \
1039 _HSW_PIPE_SLICE_CHICKEN_1_A, + \
1040 _HSW_PIPE_SLICE_CHICKEN_1_B)
1042 #define HSW_CLKGATE_DISABLE_PART_1 0x46500
1043 #define HSW_DPFC_GATING_DISABLE (1<<23)
1048 #define GPIOA 0x5010
1049 #define GPIOB 0x5014
1050 #define GPIOC 0x5018
1051 #define GPIOD 0x501c
1052 #define GPIOE 0x5020
1053 #define GPIOF 0x5024
1054 #define GPIOG 0x5028
1055 #define GPIOH 0x502c
1056 # define GPIO_CLOCK_DIR_MASK (1 << 0)
1057 # define GPIO_CLOCK_DIR_IN (0 << 1)
1058 # define GPIO_CLOCK_DIR_OUT (1 << 1)
1059 # define GPIO_CLOCK_VAL_MASK (1 << 2)
1060 # define GPIO_CLOCK_VAL_OUT (1 << 3)
1061 # define GPIO_CLOCK_VAL_IN (1 << 4)
1062 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
1063 # define GPIO_DATA_DIR_MASK (1 << 8)
1064 # define GPIO_DATA_DIR_IN (0 << 9)
1065 # define GPIO_DATA_DIR_OUT (1 << 9)
1066 # define GPIO_DATA_VAL_MASK (1 << 10)
1067 # define GPIO_DATA_VAL_OUT (1 << 11)
1068 # define GPIO_DATA_VAL_IN (1 << 12)
1069 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
1071 #define GMBUS0 0x5100 /* clock/port select */
1072 #define GMBUS_RATE_100KHZ (0<<8)
1073 #define GMBUS_RATE_50KHZ (1<<8)
1074 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
1075 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
1076 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
1077 #define GMBUS_PORT_DISABLED 0
1078 #define GMBUS_PORT_SSC 1
1079 #define GMBUS_PORT_VGADDC 2
1080 #define GMBUS_PORT_PANEL 3
1081 #define GMBUS_PORT_DPC 4 /* HDMIC */
1082 #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
1083 #define GMBUS_PORT_DPD 6 /* HDMID */
1084 #define GMBUS_PORT_RESERVED 7 /* 7 reserved */
1085 #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
1086 #define GMBUS1 0x5104 /* command/status */
1087 #define GMBUS_SW_CLR_INT (1<<31)
1088 #define GMBUS_SW_RDY (1<<30)
1089 #define GMBUS_ENT (1<<29) /* enable timeout */
1090 #define GMBUS_CYCLE_NONE (0<<25)
1091 #define GMBUS_CYCLE_WAIT (1<<25)
1092 #define GMBUS_CYCLE_INDEX (2<<25)
1093 #define GMBUS_CYCLE_STOP (4<<25)
1094 #define GMBUS_BYTE_COUNT_SHIFT 16
1095 #define GMBUS_SLAVE_INDEX_SHIFT 8
1096 #define GMBUS_SLAVE_ADDR_SHIFT 1
1097 #define GMBUS_SLAVE_READ (1<<0)
1098 #define GMBUS_SLAVE_WRITE (0<<0)
1099 #define GMBUS2 0x5108 /* status */
1100 #define GMBUS_INUSE (1<<15)
1101 #define GMBUS_HW_WAIT_PHASE (1<<14)
1102 #define GMBUS_STALL_TIMEOUT (1<<13)
1103 #define GMBUS_INT (1<<12)
1104 #define GMBUS_HW_RDY (1<<11)
1105 #define GMBUS_SATOER (1<<10)
1106 #define GMBUS_ACTIVE (1<<9)
1107 #define GMBUS3 0x510c /* data buffer bytes 3-0 */
1108 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
1109 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
1110 #define GMBUS_NAK_EN (1<<3)
1111 #define GMBUS_IDLE_EN (1<<2)
1112 #define GMBUS_HW_WAIT_EN (1<<1)
1113 #define GMBUS_HW_RDY_EN (1<<0)
1114 #define GMBUS5 0x5120 /* byte index */
1115 #define GMBUS_2BYTE_INDEX_EN (1<<31)
1118 * Clock control & power management
1123 #define VGA_PD 0x6010
1124 #define VGA0_PD_P2_DIV_4 (1 << 7)
1125 #define VGA0_PD_P1_DIV_2 (1 << 5)
1126 #define VGA0_PD_P1_SHIFT 0
1127 #define VGA0_PD_P1_MASK (0x1f << 0)
1128 #define VGA1_PD_P2_DIV_4 (1 << 15)
1129 #define VGA1_PD_P1_DIV_2 (1 << 13)
1130 #define VGA1_PD_P1_SHIFT 8
1131 #define VGA1_PD_P1_MASK (0x1f << 8)
1132 #define _DPLL_A (dev_priv->info->display_mmio_offset + 0x6014)
1133 #define _DPLL_B (dev_priv->info->display_mmio_offset + 0x6018)
1134 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
1135 #define DPLL_VCO_ENABLE (1 << 31)
1136 #define DPLL_SDVO_HIGH_SPEED (1 << 30)
1137 #define DPLL_DVO_2X_MODE (1 << 30)
1138 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
1139 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
1140 #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29)
1141 #define DPLL_VGA_MODE_DIS (1 << 28)
1142 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
1143 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
1144 #define DPLL_MODE_MASK (3 << 26)
1145 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
1146 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
1147 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
1148 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
1149 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
1150 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
1151 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
1152 #define DPLL_LOCK_VLV (1<<15)
1153 #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
1154 #define DPLL_INTEGRATED_CLOCK_VLV (1<<13)
1155 #define DPLL_PORTC_READY_MASK (0xf << 4)
1156 #define DPLL_PORTB_READY_MASK (0xf)
1158 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
1160 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
1161 * this field (only one bit may be set).
1163 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
1164 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
1165 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
1166 /* i830, required in DVO non-gang */
1167 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
1168 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
1169 #define PLL_REF_INPUT_DREFCLK (0 << 13)
1170 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
1171 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
1172 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
1173 #define PLL_REF_INPUT_MASK (3 << 13)
1174 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
1176 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
1177 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
1178 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
1179 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
1180 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
1183 * Parallel to Serial Load Pulse phase selection.
1184 * Selects the phase for the 10X DPLL clock for the PCIe
1185 * digital display port. The range is 4 to 13; 10 or more
1186 * is just a flip delay. The default is 6
1188 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1189 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
1191 * SDVO multiplier for 945G/GM. Not used on 965.
1193 #define SDVO_MULTIPLIER_MASK 0x000000ff
1194 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
1195 #define SDVO_MULTIPLIER_SHIFT_VGA 0
1196 #define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) /* 965+ only */
1198 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1200 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
1202 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
1203 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
1204 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1205 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
1206 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
1208 * SDVO/UDI pixel multiplier.
1210 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1211 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1212 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1213 * dummy bytes in the datastream at an increased clock rate, with both sides of
1214 * the link knowing how many bytes are fill.
1216 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1217 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
1218 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1219 * through an SDVO command.
1221 * This register field has values of multiplication factor minus 1, with
1222 * a maximum multiplier of 5 for SDVO.
1224 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1225 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1227 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1228 * This best be set to the default value (3) or the CRT won't work. No,
1229 * I don't entirely understand what this does...
1231 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1232 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
1233 #define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) /* 965+ only */
1234 #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
1236 #define _FPA0 0x06040
1237 #define _FPA1 0x06044
1238 #define _FPB0 0x06048
1239 #define _FPB1 0x0604c
1240 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
1241 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
1242 #define FP_N_DIV_MASK 0x003f0000
1243 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
1244 #define FP_N_DIV_SHIFT 16
1245 #define FP_M1_DIV_MASK 0x00003f00
1246 #define FP_M1_DIV_SHIFT 8
1247 #define FP_M2_DIV_MASK 0x0000003f
1248 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
1249 #define FP_M2_DIV_SHIFT 0
1250 #define DPLL_TEST 0x606c
1251 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1252 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1253 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1254 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1255 #define DPLLB_TEST_N_BYPASS (1 << 19)
1256 #define DPLLB_TEST_M_BYPASS (1 << 18)
1257 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1258 #define DPLLA_TEST_N_BYPASS (1 << 3)
1259 #define DPLLA_TEST_M_BYPASS (1 << 2)
1260 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1261 #define D_STATE 0x6104
1262 #define DSTATE_GFX_RESET_I830 (1<<6)
1263 #define DSTATE_PLL_D3_OFF (1<<3)
1264 #define DSTATE_GFX_CLOCK_GATING (1<<1)
1265 #define DSTATE_DOT_CLOCK_GATING (1<<0)
1266 #define DSPCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6200)
1267 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
1268 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
1269 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
1270 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
1271 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
1272 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
1273 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
1274 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
1275 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
1276 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
1277 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
1278 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
1279 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
1280 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
1281 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
1282 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
1283 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
1284 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
1285 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
1286 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
1287 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
1288 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
1289 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
1290 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
1291 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
1292 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
1293 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
1294 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
1296 * This bit must be set on the 830 to prevent hangs when turning off the
1299 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
1300 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
1301 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
1302 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
1303 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
1305 #define RENCLK_GATE_D1 0x6204
1306 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
1307 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
1308 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
1309 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
1310 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
1311 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
1312 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
1313 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
1314 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
1315 /** This bit must be unset on 855,865 */
1316 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
1317 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
1318 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
1319 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
1320 /** This bit must be set on 855,865. */
1321 # define SV_CLOCK_GATE_DISABLE (1 << 0)
1322 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
1323 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
1324 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
1325 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
1326 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
1327 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
1328 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
1329 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
1330 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
1331 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
1332 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
1333 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
1334 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
1335 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
1336 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
1337 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
1338 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
1340 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
1341 /** This bit must always be set on 965G/965GM */
1342 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
1343 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
1344 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
1345 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
1346 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
1347 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
1348 /** This bit must always be set on 965G */
1349 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
1350 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
1351 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
1352 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
1353 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
1354 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
1355 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
1356 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
1357 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
1358 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
1359 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
1360 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
1361 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
1362 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
1363 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
1364 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
1365 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
1366 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
1367 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
1369 #define RENCLK_GATE_D2 0x6208
1370 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
1371 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
1372 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
1373 #define RAMCLK_GATE_D 0x6210 /* CRL only */
1374 #define DEUC 0x6214 /* CRL only */
1376 #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)
1377 #define FW_CSPWRDWNEN (1<<15)
1379 #define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
1385 #define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000)
1386 #define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800)
1387 #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
1389 /* MCH MMIO space */
1394 * This mirrors the MCHBAR MMIO space whose location is determined by
1395 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
1396 * every way. It is not accessible from the CP register read instructions.
1399 #define MCHBAR_MIRROR_BASE 0x10000
1401 #define MCHBAR_MIRROR_BASE_SNB 0x140000
1403 /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
1406 /** 915-945 and GM965 MCH register controlling DRAM channel access */
1408 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
1409 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
1410 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
1411 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
1412 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
1413 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
1415 /** Pineview MCH register contains DDR3 setting */
1416 #define CSHRDDR3CTL 0x101a8
1417 #define CSHRDDR3CTL_DDR3 (1 << 2)
1419 /** 965 MCH register controlling DRAM channel configuration */
1420 #define C0DRB3 0x10206
1421 #define C1DRB3 0x10606
1423 /** snb MCH registers for reading the DRAM channel configuration */
1424 #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
1425 #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
1426 #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
1427 #define MAD_DIMM_ECC_MASK (0x3 << 24)
1428 #define MAD_DIMM_ECC_OFF (0x0 << 24)
1429 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
1430 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
1431 #define MAD_DIMM_ECC_ON (0x3 << 24)
1432 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
1433 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
1434 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
1435 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
1436 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
1437 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
1438 #define MAD_DIMM_A_SELECT (0x1 << 16)
1439 /* DIMM sizes are in multiples of 256mb. */
1440 #define MAD_DIMM_B_SIZE_SHIFT 8
1441 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
1442 #define MAD_DIMM_A_SIZE_SHIFT 0
1443 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
1445 /** snb MCH registers for priority tuning */
1446 #define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10)
1447 #define MCH_SSKPD_WM0_MASK 0x3f
1448 #define MCH_SSKPD_WM0_VAL 0xc
1450 /* Clocking configuration register */
1451 #define CLKCFG 0x10c00
1452 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
1453 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
1454 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
1455 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
1456 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
1457 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
1458 /* Note, below two are guess */
1459 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
1460 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
1461 #define CLKCFG_FSB_MASK (7 << 0)
1462 #define CLKCFG_MEM_533 (1 << 4)
1463 #define CLKCFG_MEM_667 (2 << 4)
1464 #define CLKCFG_MEM_800 (3 << 4)
1465 #define CLKCFG_MEM_MASK (7 << 4)
1467 #define TSC1 0x11001
1470 #define TSFS 0x11020
1471 #define TSFS_SLOPE_MASK 0x0000ff00
1472 #define TSFS_SLOPE_SHIFT 8
1473 #define TSFS_INTR_MASK 0x000000ff
1475 #define CRSTANDVID 0x11100
1476 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1477 #define PXVFREQ_PX_MASK 0x7f000000
1478 #define PXVFREQ_PX_SHIFT 24
1479 #define VIDFREQ_BASE 0x11110
1480 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1481 #define VIDFREQ2 0x11114
1482 #define VIDFREQ3 0x11118
1483 #define VIDFREQ4 0x1111c
1484 #define VIDFREQ_P0_MASK 0x1f000000
1485 #define VIDFREQ_P0_SHIFT 24
1486 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
1487 #define VIDFREQ_P0_CSCLK_SHIFT 20
1488 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
1489 #define VIDFREQ_P0_CRCLK_SHIFT 16
1490 #define VIDFREQ_P1_MASK 0x00001f00
1491 #define VIDFREQ_P1_SHIFT 8
1492 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
1493 #define VIDFREQ_P1_CSCLK_SHIFT 4
1494 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
1495 #define INTTOEXT_BASE_ILK 0x11300
1496 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
1497 #define INTTOEXT_MAP3_SHIFT 24
1498 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
1499 #define INTTOEXT_MAP2_SHIFT 16
1500 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
1501 #define INTTOEXT_MAP1_SHIFT 8
1502 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
1503 #define INTTOEXT_MAP0_SHIFT 0
1504 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
1505 #define MEMSWCTL 0x11170 /* Ironlake only */
1506 #define MEMCTL_CMD_MASK 0xe000
1507 #define MEMCTL_CMD_SHIFT 13
1508 #define MEMCTL_CMD_RCLK_OFF 0
1509 #define MEMCTL_CMD_RCLK_ON 1
1510 #define MEMCTL_CMD_CHFREQ 2
1511 #define MEMCTL_CMD_CHVID 3
1512 #define MEMCTL_CMD_VMMOFF 4
1513 #define MEMCTL_CMD_VMMON 5
1514 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
1515 when command complete */
1516 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
1517 #define MEMCTL_FREQ_SHIFT 8
1518 #define MEMCTL_SFCAVM (1<<7)
1519 #define MEMCTL_TGT_VID_MASK 0x007f
1520 #define MEMIHYST 0x1117c
1521 #define MEMINTREN 0x11180 /* 16 bits */
1522 #define MEMINT_RSEXIT_EN (1<<8)
1523 #define MEMINT_CX_SUPR_EN (1<<7)
1524 #define MEMINT_CONT_BUSY_EN (1<<6)
1525 #define MEMINT_AVG_BUSY_EN (1<<5)
1526 #define MEMINT_EVAL_CHG_EN (1<<4)
1527 #define MEMINT_MON_IDLE_EN (1<<3)
1528 #define MEMINT_UP_EVAL_EN (1<<2)
1529 #define MEMINT_DOWN_EVAL_EN (1<<1)
1530 #define MEMINT_SW_CMD_EN (1<<0)
1531 #define MEMINTRSTR 0x11182 /* 16 bits */
1532 #define MEM_RSEXIT_MASK 0xc000
1533 #define MEM_RSEXIT_SHIFT 14
1534 #define MEM_CONT_BUSY_MASK 0x3000
1535 #define MEM_CONT_BUSY_SHIFT 12
1536 #define MEM_AVG_BUSY_MASK 0x0c00
1537 #define MEM_AVG_BUSY_SHIFT 10
1538 #define MEM_EVAL_CHG_MASK 0x0300
1539 #define MEM_EVAL_BUSY_SHIFT 8
1540 #define MEM_MON_IDLE_MASK 0x00c0
1541 #define MEM_MON_IDLE_SHIFT 6
1542 #define MEM_UP_EVAL_MASK 0x0030
1543 #define MEM_UP_EVAL_SHIFT 4
1544 #define MEM_DOWN_EVAL_MASK 0x000c
1545 #define MEM_DOWN_EVAL_SHIFT 2
1546 #define MEM_SW_CMD_MASK 0x0003
1547 #define MEM_INT_STEER_GFX 0
1548 #define MEM_INT_STEER_CMR 1
1549 #define MEM_INT_STEER_SMI 2
1550 #define MEM_INT_STEER_SCI 3
1551 #define MEMINTRSTS 0x11184
1552 #define MEMINT_RSEXIT (1<<7)
1553 #define MEMINT_CONT_BUSY (1<<6)
1554 #define MEMINT_AVG_BUSY (1<<5)
1555 #define MEMINT_EVAL_CHG (1<<4)
1556 #define MEMINT_MON_IDLE (1<<3)
1557 #define MEMINT_UP_EVAL (1<<2)
1558 #define MEMINT_DOWN_EVAL (1<<1)
1559 #define MEMINT_SW_CMD (1<<0)
1560 #define MEMMODECTL 0x11190
1561 #define MEMMODE_BOOST_EN (1<<31)
1562 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1563 #define MEMMODE_BOOST_FREQ_SHIFT 24
1564 #define MEMMODE_IDLE_MODE_MASK 0x00030000
1565 #define MEMMODE_IDLE_MODE_SHIFT 16
1566 #define MEMMODE_IDLE_MODE_EVAL 0
1567 #define MEMMODE_IDLE_MODE_CONT 1
1568 #define MEMMODE_HWIDLE_EN (1<<15)
1569 #define MEMMODE_SWMODE_EN (1<<14)
1570 #define MEMMODE_RCLK_GATE (1<<13)
1571 #define MEMMODE_HW_UPDATE (1<<12)
1572 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
1573 #define MEMMODE_FSTART_SHIFT 8
1574 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
1575 #define MEMMODE_FMAX_SHIFT 4
1576 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
1577 #define RCBMAXAVG 0x1119c
1578 #define MEMSWCTL2 0x1119e /* Cantiga only */
1579 #define SWMEMCMD_RENDER_OFF (0 << 13)
1580 #define SWMEMCMD_RENDER_ON (1 << 13)
1581 #define SWMEMCMD_SWFREQ (2 << 13)
1582 #define SWMEMCMD_TARVID (3 << 13)
1583 #define SWMEMCMD_VRM_OFF (4 << 13)
1584 #define SWMEMCMD_VRM_ON (5 << 13)
1585 #define CMDSTS (1<<12)
1586 #define SFCAVM (1<<11)
1587 #define SWFREQ_MASK 0x0380 /* P0-7 */
1588 #define SWFREQ_SHIFT 7
1589 #define TARVID_MASK 0x001f
1590 #define MEMSTAT_CTG 0x111a0
1591 #define RCBMINAVG 0x111a0
1592 #define RCUPEI 0x111b0
1593 #define RCDNEI 0x111b4
1594 #define RSTDBYCTL 0x111b8
1595 #define RS1EN (1<<31)
1596 #define RS2EN (1<<30)
1597 #define RS3EN (1<<29)
1598 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
1599 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
1600 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
1601 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
1602 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
1603 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
1604 #define RSX_STATUS_MASK (7<<20)
1605 #define RSX_STATUS_ON (0<<20)
1606 #define RSX_STATUS_RC1 (1<<20)
1607 #define RSX_STATUS_RC1E (2<<20)
1608 #define RSX_STATUS_RS1 (3<<20)
1609 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
1610 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
1611 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
1612 #define RSX_STATUS_RSVD2 (7<<20)
1613 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
1614 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
1615 #define JRSC (1<<17) /* rsx coupled to cpu c-state */
1616 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
1617 #define RS1CONTSAV_MASK (3<<14)
1618 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
1619 #define RS1CONTSAV_RSVD (1<<14)
1620 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
1621 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
1622 #define NORMSLEXLAT_MASK (3<<12)
1623 #define SLOW_RS123 (0<<12)
1624 #define SLOW_RS23 (1<<12)
1625 #define SLOW_RS3 (2<<12)
1626 #define NORMAL_RS123 (3<<12)
1627 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
1628 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1629 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
1630 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
1631 #define RS_CSTATE_MASK (3<<4)
1632 #define RS_CSTATE_C367_RS1 (0<<4)
1633 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1634 #define RS_CSTATE_RSVD (2<<4)
1635 #define RS_CSTATE_C367_RS2 (3<<4)
1636 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */
1637 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
1638 #define VIDCTL 0x111c0
1639 #define VIDSTS 0x111c8
1640 #define VIDSTART 0x111cc /* 8 bits */
1641 #define MEMSTAT_ILK 0x111f8
1642 #define MEMSTAT_VID_MASK 0x7f00
1643 #define MEMSTAT_VID_SHIFT 8
1644 #define MEMSTAT_PSTATE_MASK 0x00f8
1645 #define MEMSTAT_PSTATE_SHIFT 3
1646 #define MEMSTAT_MON_ACTV (1<<2)
1647 #define MEMSTAT_SRC_CTL_MASK 0x0003
1648 #define MEMSTAT_SRC_CTL_CORE 0
1649 #define MEMSTAT_SRC_CTL_TRB 1
1650 #define MEMSTAT_SRC_CTL_THM 2
1651 #define MEMSTAT_SRC_CTL_STDBY 3
1652 #define RCPREVBSYTUPAVG 0x113b8
1653 #define RCPREVBSYTDNAVG 0x113bc
1654 #define PMMISC 0x11214
1655 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
1656 #define SDEW 0x1124c
1657 #define CSIEW0 0x11250
1658 #define CSIEW1 0x11254
1659 #define CSIEW2 0x11258
1662 #define MCHAFE 0x112c0
1663 #define CSIEC 0x112e0
1664 #define DMIEC 0x112e4
1665 #define DDREC 0x112e8
1666 #define PEG0EC 0x112ec
1667 #define PEG1EC 0x112f0
1668 #define GFXEC 0x112f4
1669 #define RPPREVBSYTUPAVG 0x113b8
1670 #define RPPREVBSYTDNAVG 0x113bc
1672 #define ECR_GPFE (1<<31)
1673 #define ECR_IMONE (1<<30)
1674 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
1675 #define OGW0 0x11608
1676 #define OGW1 0x1160c
1686 #define PXWL 0x11680
1687 #define LCFUSE02 0x116c0
1688 #define LCFUSE_HIV_MASK 0x000000ff
1689 #define CSIPLL0 0x12c10
1690 #define DDRMPLL1 0X12c20
1691 #define PEG_BAND_GAP_DATA 0x14d68
1693 #define GEN6_GT_THREAD_STATUS_REG 0x13805c
1694 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
1695 #define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
1697 #define GEN6_GT_PERF_STATUS 0x145948
1698 #define GEN6_RP_STATE_LIMITS 0x145994
1699 #define GEN6_RP_STATE_CAP 0x145998
1702 * Logical Context regs
1705 #define CCID_EN (1<<0)
1706 #define CXT_SIZE 0x21a0
1707 #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f)
1708 #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f)
1709 #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f)
1710 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
1711 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
1712 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_POWER_SIZE(cxt_reg) + \
1713 GEN6_CXT_RING_SIZE(cxt_reg) + \
1714 GEN6_CXT_RENDER_SIZE(cxt_reg) + \
1715 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
1716 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
1717 #define GEN7_CXT_SIZE 0x21a8
1718 #define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f)
1719 #define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7)
1720 #define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f)
1721 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
1722 #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7)
1723 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f)
1724 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_POWER_SIZE(ctx_reg) + \
1725 GEN7_CXT_RING_SIZE(ctx_reg) + \
1726 GEN7_CXT_RENDER_SIZE(ctx_reg) + \
1727 GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
1728 GEN7_CXT_GT1_SIZE(ctx_reg) + \
1729 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
1730 /* Haswell does have the CXT_SIZE register however it does not appear to be
1731 * valid. Now, docs explain in dwords what is in the context object. The full
1732 * size is 70720 bytes, however, the power context and execlist context will
1733 * never be saved (power context is stored elsewhere, and execlists don't work
1734 * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages.
1736 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
1742 #define OVADD 0x30000
1743 #define DOVSTA 0x30008
1744 #define OC_BUF (0x3<<20)
1745 #define OGAMC5 0x30010
1746 #define OGAMC4 0x30014
1747 #define OGAMC3 0x30018
1748 #define OGAMC2 0x3001c
1749 #define OGAMC1 0x30020
1750 #define OGAMC0 0x30024
1753 * Display engine regs
1756 /* Pipe A timing regs */
1757 #define _HTOTAL_A (dev_priv->info->display_mmio_offset + 0x60000)
1758 #define _HBLANK_A (dev_priv->info->display_mmio_offset + 0x60004)
1759 #define _HSYNC_A (dev_priv->info->display_mmio_offset + 0x60008)
1760 #define _VTOTAL_A (dev_priv->info->display_mmio_offset + 0x6000c)
1761 #define _VBLANK_A (dev_priv->info->display_mmio_offset + 0x60010)
1762 #define _VSYNC_A (dev_priv->info->display_mmio_offset + 0x60014)
1763 #define _PIPEASRC (dev_priv->info->display_mmio_offset + 0x6001c)
1764 #define _BCLRPAT_A (dev_priv->info->display_mmio_offset + 0x60020)
1765 #define _VSYNCSHIFT_A (dev_priv->info->display_mmio_offset + 0x60028)
1767 /* Pipe B timing regs */
1768 #define _HTOTAL_B (dev_priv->info->display_mmio_offset + 0x61000)
1769 #define _HBLANK_B (dev_priv->info->display_mmio_offset + 0x61004)
1770 #define _HSYNC_B (dev_priv->info->display_mmio_offset + 0x61008)
1771 #define _VTOTAL_B (dev_priv->info->display_mmio_offset + 0x6100c)
1772 #define _VBLANK_B (dev_priv->info->display_mmio_offset + 0x61010)
1773 #define _VSYNC_B (dev_priv->info->display_mmio_offset + 0x61014)
1774 #define _PIPEBSRC (dev_priv->info->display_mmio_offset + 0x6101c)
1775 #define _BCLRPAT_B (dev_priv->info->display_mmio_offset + 0x61020)
1776 #define _VSYNCSHIFT_B (dev_priv->info->display_mmio_offset + 0x61028)
1779 #define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
1780 #define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
1781 #define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B)
1782 #define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B)
1783 #define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B)
1784 #define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B)
1785 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
1786 #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
1788 /* HSW eDP PSR registers */
1789 #define EDP_PSR_CTL 0x64800
1790 #define EDP_PSR_ENABLE (1<<31)
1791 #define EDP_PSR_LINK_DISABLE (0<<27)
1792 #define EDP_PSR_LINK_STANDBY (1<<27)
1793 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
1794 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
1795 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25)
1796 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25)
1797 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25)
1798 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
1799 #define EDP_PSR_SKIP_AUX_EXIT (1<<12)
1800 #define EDP_PSR_TP1_TP2_SEL (0<<11)
1801 #define EDP_PSR_TP1_TP3_SEL (1<<11)
1802 #define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
1803 #define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
1804 #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
1805 #define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
1806 #define EDP_PSR_TP1_TIME_500us (0<<4)
1807 #define EDP_PSR_TP1_TIME_100us (1<<4)
1808 #define EDP_PSR_TP1_TIME_2500us (2<<4)
1809 #define EDP_PSR_TP1_TIME_0us (3<<4)
1810 #define EDP_PSR_IDLE_FRAME_SHIFT 0
1812 #define EDP_PSR_AUX_CTL 0x64810
1813 #define EDP_PSR_AUX_DATA1 0x64814
1814 #define EDP_PSR_DPCD_COMMAND 0x80060000
1815 #define EDP_PSR_AUX_DATA2 0x64818
1816 #define EDP_PSR_DPCD_NORMAL_OPERATION (1<<24)
1817 #define EDP_PSR_AUX_DATA3 0x6481c
1818 #define EDP_PSR_AUX_DATA4 0x64820
1819 #define EDP_PSR_AUX_DATA5 0x64824
1821 #define EDP_PSR_STATUS_CTL 0x64840
1822 #define EDP_PSR_STATUS_STATE_MASK (7<<29)
1823 #define EDP_PSR_STATUS_STATE_IDLE (0<<29)
1824 #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
1825 #define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
1826 #define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
1827 #define EDP_PSR_STATUS_STATE_BUFON (4<<29)
1828 #define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
1829 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
1830 #define EDP_PSR_STATUS_LINK_MASK (3<<26)
1831 #define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26)
1832 #define EDP_PSR_STATUS_LINK_FULL_ON (1<<26)
1833 #define EDP_PSR_STATUS_LINK_STANDBY (2<<26)
1834 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
1835 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
1836 #define EDP_PSR_STATUS_COUNT_SHIFT 16
1837 #define EDP_PSR_STATUS_COUNT_MASK 0xf
1838 #define EDP_PSR_STATUS_AUX_ERROR (1<<15)
1839 #define EDP_PSR_STATUS_AUX_SENDING (1<<12)
1840 #define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
1841 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
1842 #define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
1843 #define EDP_PSR_STATUS_IDLE_MASK 0xf
1845 #define EDP_PSR_PERF_CNT 0x64844
1846 #define EDP_PSR_PERF_CNT_MASK 0xffffff
1848 #define EDP_PSR_DEBUG_CTL 0x64860
1849 #define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
1850 #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
1851 #define EDP_PSR_DEBUG_MASK_HPD (1<<25)
1853 /* VGA port control */
1854 #define ADPA 0x61100
1855 #define PCH_ADPA 0xe1100
1856 #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
1858 #define ADPA_DAC_ENABLE (1<<31)
1859 #define ADPA_DAC_DISABLE 0
1860 #define ADPA_PIPE_SELECT_MASK (1<<30)
1861 #define ADPA_PIPE_A_SELECT 0
1862 #define ADPA_PIPE_B_SELECT (1<<30)
1863 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
1864 /* CPT uses bits 29:30 for pch transcoder select */
1865 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
1866 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
1867 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
1868 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
1869 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
1870 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
1871 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
1872 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
1873 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
1874 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
1875 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
1876 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
1877 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
1878 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
1879 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
1880 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
1881 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
1882 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
1883 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
1884 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
1885 #define ADPA_SETS_HVPOLARITY 0
1886 #define ADPA_VSYNC_CNTL_DISABLE (1<<10)
1887 #define ADPA_VSYNC_CNTL_ENABLE 0
1888 #define ADPA_HSYNC_CNTL_DISABLE (1<<11)
1889 #define ADPA_HSYNC_CNTL_ENABLE 0
1890 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1891 #define ADPA_VSYNC_ACTIVE_LOW 0
1892 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1893 #define ADPA_HSYNC_ACTIVE_LOW 0
1894 #define ADPA_DPMS_MASK (~(3<<10))
1895 #define ADPA_DPMS_ON (0<<10)
1896 #define ADPA_DPMS_SUSPEND (1<<10)
1897 #define ADPA_DPMS_STANDBY (2<<10)
1898 #define ADPA_DPMS_OFF (3<<10)
1901 /* Hotplug control (945+ only) */
1902 #define PORT_HOTPLUG_EN (dev_priv->info->display_mmio_offset + 0x61110)
1903 #define PORTB_HOTPLUG_INT_EN (1 << 29)
1904 #define PORTC_HOTPLUG_INT_EN (1 << 28)
1905 #define PORTD_HOTPLUG_INT_EN (1 << 27)
1906 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
1907 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
1908 #define TV_HOTPLUG_INT_EN (1 << 18)
1909 #define CRT_HOTPLUG_INT_EN (1 << 9)
1910 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
1911 PORTC_HOTPLUG_INT_EN | \
1912 PORTD_HOTPLUG_INT_EN | \
1913 SDVOC_HOTPLUG_INT_EN | \
1914 SDVOB_HOTPLUG_INT_EN | \
1916 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1917 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1918 /* must use period 64 on GM45 according to docs */
1919 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
1920 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1921 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
1922 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1923 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
1924 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
1925 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
1926 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
1927 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1928 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
1929 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1930 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
1932 #define PORT_HOTPLUG_STAT (dev_priv->info->display_mmio_offset + 0x61114)
1933 /* HDMI/DP bits are gen4+ */
1934 #define PORTB_HOTPLUG_LIVE_STATUS (1 << 29)
1935 #define PORTC_HOTPLUG_LIVE_STATUS (1 << 28)
1936 #define PORTD_HOTPLUG_LIVE_STATUS (1 << 27)
1937 #define PORTD_HOTPLUG_INT_STATUS (3 << 21)
1938 #define PORTC_HOTPLUG_INT_STATUS (3 << 19)
1939 #define PORTB_HOTPLUG_INT_STATUS (3 << 17)
1940 /* CRT/TV common between gen3+ */
1941 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
1942 #define TV_HOTPLUG_INT_STATUS (1 << 10)
1943 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1944 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1945 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1946 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1947 /* SDVO is different across gen3/4 */
1948 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
1949 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
1951 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
1952 * since reality corrobates that they're the same as on gen3. But keep these
1953 * bits here (and the comment!) to help any other lost wanderers back onto the
1956 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
1957 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
1958 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
1959 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
1960 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
1961 SDVOB_HOTPLUG_INT_STATUS_G4X | \
1962 SDVOC_HOTPLUG_INT_STATUS_G4X | \
1963 PORTB_HOTPLUG_INT_STATUS | \
1964 PORTC_HOTPLUG_INT_STATUS | \
1965 PORTD_HOTPLUG_INT_STATUS)
1967 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
1968 SDVOB_HOTPLUG_INT_STATUS_I915 | \
1969 SDVOC_HOTPLUG_INT_STATUS_I915 | \
1970 PORTB_HOTPLUG_INT_STATUS | \
1971 PORTC_HOTPLUG_INT_STATUS | \
1972 PORTD_HOTPLUG_INT_STATUS)
1974 /* SDVO and HDMI port control.
1975 * The same register may be used for SDVO or HDMI */
1976 #define GEN3_SDVOB 0x61140
1977 #define GEN3_SDVOC 0x61160
1978 #define GEN4_HDMIB GEN3_SDVOB
1979 #define GEN4_HDMIC GEN3_SDVOC
1980 #define PCH_SDVOB 0xe1140
1981 #define PCH_HDMIB PCH_SDVOB
1982 #define PCH_HDMIC 0xe1150
1983 #define PCH_HDMID 0xe1160
1985 /* Gen 3 SDVO bits: */
1986 #define SDVO_ENABLE (1 << 31)
1987 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
1988 #define SDVO_PIPE_SEL_MASK (1 << 30)
1989 #define SDVO_PIPE_B_SELECT (1 << 30)
1990 #define SDVO_STALL_SELECT (1 << 29)
1991 #define SDVO_INTERRUPT_ENABLE (1 << 26)
1993 * 915G/GM SDVO pixel multiplier.
1994 * Programmed value is multiplier - 1, up to 5x.
1995 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1997 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1998 #define SDVO_PORT_MULTIPLY_SHIFT 23
1999 #define SDVO_PHASE_SELECT_MASK (15 << 19)
2000 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
2001 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
2002 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */
2003 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
2004 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
2005 #define SDVO_DETECTED (1 << 2)
2006 /* Bits to be preserved when writing */
2007 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
2008 SDVO_INTERRUPT_ENABLE)
2009 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
2011 /* Gen 4 SDVO/HDMI bits: */
2012 #define SDVO_COLOR_FORMAT_8bpc (0 << 26)
2013 #define SDVO_ENCODING_SDVO (0 << 10)
2014 #define SDVO_ENCODING_HDMI (2 << 10)
2015 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
2016 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
2017 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
2018 #define SDVO_AUDIO_ENABLE (1 << 6)
2019 /* VSYNC/HSYNC bits new with 965, default is to be set */
2020 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
2021 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
2023 /* Gen 5 (IBX) SDVO/HDMI bits: */
2024 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
2025 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
2027 /* Gen 6 (CPT) SDVO/HDMI bits: */
2028 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
2029 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
2032 /* DVO port control */
2033 #define DVOA 0x61120
2034 #define DVOB 0x61140
2035 #define DVOC 0x61160
2036 #define DVO_ENABLE (1 << 31)
2037 #define DVO_PIPE_B_SELECT (1 << 30)
2038 #define DVO_PIPE_STALL_UNUSED (0 << 28)
2039 #define DVO_PIPE_STALL (1 << 28)
2040 #define DVO_PIPE_STALL_TV (2 << 28)
2041 #define DVO_PIPE_STALL_MASK (3 << 28)
2042 #define DVO_USE_VGA_SYNC (1 << 15)
2043 #define DVO_DATA_ORDER_I740 (0 << 14)
2044 #define DVO_DATA_ORDER_FP (1 << 14)
2045 #define DVO_VSYNC_DISABLE (1 << 11)
2046 #define DVO_HSYNC_DISABLE (1 << 10)
2047 #define DVO_VSYNC_TRISTATE (1 << 9)
2048 #define DVO_HSYNC_TRISTATE (1 << 8)
2049 #define DVO_BORDER_ENABLE (1 << 7)
2050 #define DVO_DATA_ORDER_GBRG (1 << 6)
2051 #define DVO_DATA_ORDER_RGGB (0 << 6)
2052 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
2053 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
2054 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
2055 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
2056 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
2057 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
2058 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
2059 #define DVO_PRESERVE_MASK (0x7<<24)
2060 #define DVOA_SRCDIM 0x61124
2061 #define DVOB_SRCDIM 0x61144
2062 #define DVOC_SRCDIM 0x61164
2063 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
2064 #define DVO_SRCDIM_VERTICAL_SHIFT 0
2066 /* LVDS port control */
2067 #define LVDS 0x61180
2069 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
2070 * the DPLL semantics change when the LVDS is assigned to that pipe.
2072 #define LVDS_PORT_EN (1 << 31)
2073 /* Selects pipe B for LVDS data. Must be set on pre-965. */
2074 #define LVDS_PIPEB_SELECT (1 << 30)
2075 #define LVDS_PIPE_MASK (1 << 30)
2076 #define LVDS_PIPE(pipe) ((pipe) << 30)
2077 /* LVDS dithering flag on 965/g4x platform */
2078 #define LVDS_ENABLE_DITHER (1 << 25)
2079 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
2080 #define LVDS_VSYNC_POLARITY (1 << 21)
2081 #define LVDS_HSYNC_POLARITY (1 << 20)
2083 /* Enable border for unscaled (or aspect-scaled) display */
2084 #define LVDS_BORDER_ENABLE (1 << 15)
2086 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
2089 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
2090 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
2091 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
2093 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
2094 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
2097 #define LVDS_A3_POWER_MASK (3 << 6)
2098 #define LVDS_A3_POWER_DOWN (0 << 6)
2099 #define LVDS_A3_POWER_UP (3 << 6)
2101 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
2104 #define LVDS_CLKB_POWER_MASK (3 << 4)
2105 #define LVDS_CLKB_POWER_DOWN (0 << 4)
2106 #define LVDS_CLKB_POWER_UP (3 << 4)
2108 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
2109 * setting for whether we are in dual-channel mode. The B3 pair will
2110 * additionally only be powered up when LVDS_A3_POWER_UP is set.
2112 #define LVDS_B0B3_POWER_MASK (3 << 2)
2113 #define LVDS_B0B3_POWER_DOWN (0 << 2)
2114 #define LVDS_B0B3_POWER_UP (3 << 2)
2116 /* Video Data Island Packet control */
2117 #define VIDEO_DIP_DATA 0x61178
2118 /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
2119 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
2120 * of the infoframe structure specified by CEA-861. */
2121 #define VIDEO_DIP_DATA_SIZE 32
2122 #define VIDEO_DIP_VSC_DATA_SIZE 36
2123 #define VIDEO_DIP_CTL 0x61170
2125 #define VIDEO_DIP_ENABLE (1 << 31)
2126 #define VIDEO_DIP_PORT_B (1 << 29)
2127 #define VIDEO_DIP_PORT_C (2 << 29)
2128 #define VIDEO_DIP_PORT_D (3 << 29)
2129 #define VIDEO_DIP_PORT_MASK (3 << 29)
2130 #define VIDEO_DIP_ENABLE_GCP (1 << 25)
2131 #define VIDEO_DIP_ENABLE_AVI (1 << 21)
2132 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
2133 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
2134 #define VIDEO_DIP_ENABLE_SPD (8 << 21)
2135 #define VIDEO_DIP_SELECT_AVI (0 << 19)
2136 #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
2137 #define VIDEO_DIP_SELECT_SPD (3 << 19)
2138 #define VIDEO_DIP_SELECT_MASK (3 << 19)
2139 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
2140 #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
2141 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
2142 #define VIDEO_DIP_FREQ_MASK (3 << 16)
2143 /* HSW and later: */
2144 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
2145 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
2146 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
2147 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
2148 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
2149 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
2151 /* Panel power sequencing */
2152 #define PP_STATUS 0x61200
2153 #define PP_ON (1 << 31)
2155 * Indicates that all dependencies of the panel are on:
2159 * - LVDS/DVOB/DVOC on
2161 #define PP_READY (1 << 30)
2162 #define PP_SEQUENCE_NONE (0 << 28)
2163 #define PP_SEQUENCE_POWER_UP (1 << 28)
2164 #define PP_SEQUENCE_POWER_DOWN (2 << 28)
2165 #define PP_SEQUENCE_MASK (3 << 28)
2166 #define PP_SEQUENCE_SHIFT 28
2167 #define PP_CYCLE_DELAY_ACTIVE (1 << 27)
2168 #define PP_SEQUENCE_STATE_MASK 0x0000000f
2169 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
2170 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
2171 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
2172 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
2173 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
2174 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
2175 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
2176 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
2177 #define PP_SEQUENCE_STATE_RESET (0xf << 0)
2178 #define PP_CONTROL 0x61204
2179 #define POWER_TARGET_ON (1 << 0)
2180 #define PP_ON_DELAYS 0x61208
2181 #define PP_OFF_DELAYS 0x6120c
2182 #define PP_DIVISOR 0x61210
2185 #define PFIT_CONTROL (dev_priv->info->display_mmio_offset + 0x61230)
2186 #define PFIT_ENABLE (1 << 31)
2187 #define PFIT_PIPE_MASK (3 << 29)
2188 #define PFIT_PIPE_SHIFT 29
2189 #define VERT_INTERP_DISABLE (0 << 10)
2190 #define VERT_INTERP_BILINEAR (1 << 10)
2191 #define VERT_INTERP_MASK (3 << 10)
2192 #define VERT_AUTO_SCALE (1 << 9)
2193 #define HORIZ_INTERP_DISABLE (0 << 6)
2194 #define HORIZ_INTERP_BILINEAR (1 << 6)
2195 #define HORIZ_INTERP_MASK (3 << 6)
2196 #define HORIZ_AUTO_SCALE (1 << 5)
2197 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
2198 #define PFIT_FILTER_FUZZY (0 << 24)
2199 #define PFIT_SCALING_AUTO (0 << 26)
2200 #define PFIT_SCALING_PROGRAMMED (1 << 26)
2201 #define PFIT_SCALING_PILLAR (2 << 26)
2202 #define PFIT_SCALING_LETTER (3 << 26)
2203 #define PFIT_PGM_RATIOS (dev_priv->info->display_mmio_offset + 0x61234)
2205 #define PFIT_VERT_SCALE_SHIFT 20
2206 #define PFIT_VERT_SCALE_MASK 0xfff00000
2207 #define PFIT_HORIZ_SCALE_SHIFT 4
2208 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
2210 #define PFIT_VERT_SCALE_SHIFT_965 16
2211 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
2212 #define PFIT_HORIZ_SCALE_SHIFT_965 0
2213 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
2215 #define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238)
2217 /* Backlight control */
2218 #define BLC_PWM_CTL2 (dev_priv->info->display_mmio_offset + 0x61250) /* 965+ only */
2219 #define BLM_PWM_ENABLE (1 << 31)
2220 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
2221 #define BLM_PIPE_SELECT (1 << 29)
2222 #define BLM_PIPE_SELECT_IVB (3 << 29)
2223 #define BLM_PIPE_A (0 << 29)
2224 #define BLM_PIPE_B (1 << 29)
2225 #define BLM_PIPE_C (2 << 29) /* ivb + */
2226 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
2227 #define BLM_TRANSCODER_B BLM_PIPE_B
2228 #define BLM_TRANSCODER_C BLM_PIPE_C
2229 #define BLM_TRANSCODER_EDP (3 << 29)
2230 #define BLM_PIPE(pipe) ((pipe) << 29)
2231 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
2232 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
2233 #define BLM_PHASE_IN_ENABLE (1 << 25)
2234 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
2235 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
2236 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
2237 #define BLM_PHASE_IN_COUNT_SHIFT (8)
2238 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
2239 #define BLM_PHASE_IN_INCR_SHIFT (0)
2240 #define BLM_PHASE_IN_INCR_MASK (0xff << 0)
2241 #define BLC_PWM_CTL (dev_priv->info->display_mmio_offset + 0x61254)
2243 * This is the most significant 15 bits of the number of backlight cycles in a
2244 * complete cycle of the modulated backlight control.
2246 * The actual value is this field multiplied by two.
2248 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
2249 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
2250 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
2252 * This is the number of cycles out of the backlight modulation cycle for which
2253 * the backlight is on.
2255 * This field must be no greater than the number of cycles in the complete
2256 * backlight modulation cycle.
2258 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
2259 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
2260 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
2261 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
2263 #define BLC_HIST_CTL (dev_priv->info->display_mmio_offset + 0x61260)
2265 /* New registers for PCH-split platforms. Safe where new bits show up, the
2266 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
2267 #define BLC_PWM_CPU_CTL2 0x48250
2268 #define BLC_PWM_CPU_CTL 0x48254
2270 #define HSW_BLC_PWM2_CTL 0x48350
2272 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
2273 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
2274 #define BLC_PWM_PCH_CTL1 0xc8250
2275 #define BLM_PCH_PWM_ENABLE (1 << 31)
2276 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
2277 #define BLM_PCH_POLARITY (1 << 29)
2278 #define BLC_PWM_PCH_CTL2 0xc8254
2280 #define UTIL_PIN_CTL 0x48400
2281 #define UTIL_PIN_ENABLE (1 << 31)
2283 #define PCH_GTC_CTL 0xe7000
2284 #define PCH_GTC_ENABLE (1 << 31)
2286 /* TV port control */
2287 #define TV_CTL 0x68000
2288 /** Enables the TV encoder */
2289 # define TV_ENC_ENABLE (1 << 31)
2290 /** Sources the TV encoder input from pipe B instead of A. */
2291 # define TV_ENC_PIPEB_SELECT (1 << 30)
2292 /** Outputs composite video (DAC A only) */
2293 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
2294 /** Outputs SVideo video (DAC B/C) */
2295 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
2296 /** Outputs Component video (DAC A/B/C) */
2297 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
2298 /** Outputs Composite and SVideo (DAC A/B/C) */
2299 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
2300 # define TV_TRILEVEL_SYNC (1 << 21)
2301 /** Enables slow sync generation (945GM only) */
2302 # define TV_SLOW_SYNC (1 << 20)
2303 /** Selects 4x oversampling for 480i and 576p */
2304 # define TV_OVERSAMPLE_4X (0 << 18)
2305 /** Selects 2x oversampling for 720p and 1080i */
2306 # define TV_OVERSAMPLE_2X (1 << 18)
2307 /** Selects no oversampling for 1080p */
2308 # define TV_OVERSAMPLE_NONE (2 << 18)
2309 /** Selects 8x oversampling */
2310 # define TV_OVERSAMPLE_8X (3 << 18)
2311 /** Selects progressive mode rather than interlaced */
2312 # define TV_PROGRESSIVE (1 << 17)
2313 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
2314 # define TV_PAL_BURST (1 << 16)
2315 /** Field for setting delay of Y compared to C */
2316 # define TV_YC_SKEW_MASK (7 << 12)
2317 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
2318 # define TV_ENC_SDP_FIX (1 << 11)
2320 * Enables a fix for the 915GM only.
2322 * Not sure what it does.
2324 # define TV_ENC_C0_FIX (1 << 10)
2325 /** Bits that must be preserved by software */
2326 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
2327 # define TV_FUSE_STATE_MASK (3 << 4)
2328 /** Read-only state that reports all features enabled */
2329 # define TV_FUSE_STATE_ENABLED (0 << 4)
2330 /** Read-only state that reports that Macrovision is disabled in hardware*/
2331 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
2332 /** Read-only state that reports that TV-out is disabled in hardware. */
2333 # define TV_FUSE_STATE_DISABLED (2 << 4)
2334 /** Normal operation */
2335 # define TV_TEST_MODE_NORMAL (0 << 0)
2336 /** Encoder test pattern 1 - combo pattern */
2337 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
2338 /** Encoder test pattern 2 - full screen vertical 75% color bars */
2339 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
2340 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
2341 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
2342 /** Encoder test pattern 4 - random noise */
2343 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
2344 /** Encoder test pattern 5 - linear color ramps */
2345 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
2347 * This test mode forces the DACs to 50% of full output.
2349 * This is used for load detection in combination with TVDAC_SENSE_MASK
2351 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
2352 # define TV_TEST_MODE_MASK (7 << 0)
2354 #define TV_DAC 0x68004
2355 # define TV_DAC_SAVE 0x00ffff00
2357 * Reports that DAC state change logic has reported change (RO).
2359 * This gets cleared when TV_DAC_STATE_EN is cleared
2361 # define TVDAC_STATE_CHG (1 << 31)
2362 # define TVDAC_SENSE_MASK (7 << 28)
2363 /** Reports that DAC A voltage is above the detect threshold */
2364 # define TVDAC_A_SENSE (1 << 30)
2365 /** Reports that DAC B voltage is above the detect threshold */
2366 # define TVDAC_B_SENSE (1 << 29)
2367 /** Reports that DAC C voltage is above the detect threshold */
2368 # define TVDAC_C_SENSE (1 << 28)
2370 * Enables DAC state detection logic, for load-based TV detection.
2372 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
2373 * to off, for load detection to work.
2375 # define TVDAC_STATE_CHG_EN (1 << 27)
2376 /** Sets the DAC A sense value to high */
2377 # define TVDAC_A_SENSE_CTL (1 << 26)
2378 /** Sets the DAC B sense value to high */
2379 # define TVDAC_B_SENSE_CTL (1 << 25)
2380 /** Sets the DAC C sense value to high */
2381 # define TVDAC_C_SENSE_CTL (1 << 24)
2382 /** Overrides the ENC_ENABLE and DAC voltage levels */
2383 # define DAC_CTL_OVERRIDE (1 << 7)
2384 /** Sets the slew rate. Must be preserved in software */
2385 # define ENC_TVDAC_SLEW_FAST (1 << 6)
2386 # define DAC_A_1_3_V (0 << 4)
2387 # define DAC_A_1_1_V (1 << 4)
2388 # define DAC_A_0_7_V (2 << 4)
2389 # define DAC_A_MASK (3 << 4)
2390 # define DAC_B_1_3_V (0 << 2)
2391 # define DAC_B_1_1_V (1 << 2)
2392 # define DAC_B_0_7_V (2 << 2)
2393 # define DAC_B_MASK (3 << 2)
2394 # define DAC_C_1_3_V (0 << 0)
2395 # define DAC_C_1_1_V (1 << 0)
2396 # define DAC_C_0_7_V (2 << 0)
2397 # define DAC_C_MASK (3 << 0)
2400 * CSC coefficients are stored in a floating point format with 9 bits of
2401 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
2402 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
2403 * -1 (0x3) being the only legal negative value.
2405 #define TV_CSC_Y 0x68010
2406 # define TV_RY_MASK 0x07ff0000
2407 # define TV_RY_SHIFT 16
2408 # define TV_GY_MASK 0x00000fff
2409 # define TV_GY_SHIFT 0
2411 #define TV_CSC_Y2 0x68014
2412 # define TV_BY_MASK 0x07ff0000
2413 # define TV_BY_SHIFT 16
2415 * Y attenuation for component video.
2417 * Stored in 1.9 fixed point.
2419 # define TV_AY_MASK 0x000003ff
2420 # define TV_AY_SHIFT 0
2422 #define TV_CSC_U 0x68018
2423 # define TV_RU_MASK 0x07ff0000
2424 # define TV_RU_SHIFT 16
2425 # define TV_GU_MASK 0x000007ff
2426 # define TV_GU_SHIFT 0
2428 #define TV_CSC_U2 0x6801c
2429 # define TV_BU_MASK 0x07ff0000
2430 # define TV_BU_SHIFT 16
2432 * U attenuation for component video.
2434 * Stored in 1.9 fixed point.
2436 # define TV_AU_MASK 0x000003ff
2437 # define TV_AU_SHIFT 0
2439 #define TV_CSC_V 0x68020
2440 # define TV_RV_MASK 0x0fff0000
2441 # define TV_RV_SHIFT 16
2442 # define TV_GV_MASK 0x000007ff
2443 # define TV_GV_SHIFT 0
2445 #define TV_CSC_V2 0x68024
2446 # define TV_BV_MASK 0x07ff0000
2447 # define TV_BV_SHIFT 16
2449 * V attenuation for component video.
2451 * Stored in 1.9 fixed point.
2453 # define TV_AV_MASK 0x000007ff
2454 # define TV_AV_SHIFT 0
2456 #define TV_CLR_KNOBS 0x68028
2457 /** 2s-complement brightness adjustment */
2458 # define TV_BRIGHTNESS_MASK 0xff000000
2459 # define TV_BRIGHTNESS_SHIFT 24
2460 /** Contrast adjustment, as a 2.6 unsigned floating point number */
2461 # define TV_CONTRAST_MASK 0x00ff0000
2462 # define TV_CONTRAST_SHIFT 16
2463 /** Saturation adjustment, as a 2.6 unsigned floating point number */
2464 # define TV_SATURATION_MASK 0x0000ff00
2465 # define TV_SATURATION_SHIFT 8
2466 /** Hue adjustment, as an integer phase angle in degrees */
2467 # define TV_HUE_MASK 0x000000ff
2468 # define TV_HUE_SHIFT 0
2470 #define TV_CLR_LEVEL 0x6802c
2471 /** Controls the DAC level for black */
2472 # define TV_BLACK_LEVEL_MASK 0x01ff0000
2473 # define TV_BLACK_LEVEL_SHIFT 16
2474 /** Controls the DAC level for blanking */
2475 # define TV_BLANK_LEVEL_MASK 0x000001ff
2476 # define TV_BLANK_LEVEL_SHIFT 0
2478 #define TV_H_CTL_1 0x68030
2479 /** Number of pixels in the hsync. */
2480 # define TV_HSYNC_END_MASK 0x1fff0000
2481 # define TV_HSYNC_END_SHIFT 16
2482 /** Total number of pixels minus one in the line (display and blanking). */
2483 # define TV_HTOTAL_MASK 0x00001fff
2484 # define TV_HTOTAL_SHIFT 0
2486 #define TV_H_CTL_2 0x68034
2487 /** Enables the colorburst (needed for non-component color) */
2488 # define TV_BURST_ENA (1 << 31)
2489 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
2490 # define TV_HBURST_START_SHIFT 16
2491 # define TV_HBURST_START_MASK 0x1fff0000
2492 /** Length of the colorburst */
2493 # define TV_HBURST_LEN_SHIFT 0
2494 # define TV_HBURST_LEN_MASK 0x0001fff
2496 #define TV_H_CTL_3 0x68038
2497 /** End of hblank, measured in pixels minus one from start of hsync */
2498 # define TV_HBLANK_END_SHIFT 16
2499 # define TV_HBLANK_END_MASK 0x1fff0000
2500 /** Start of hblank, measured in pixels minus one from start of hsync */
2501 # define TV_HBLANK_START_SHIFT 0
2502 # define TV_HBLANK_START_MASK 0x0001fff
2504 #define TV_V_CTL_1 0x6803c
2506 # define TV_NBR_END_SHIFT 16
2507 # define TV_NBR_END_MASK 0x07ff0000
2509 # define TV_VI_END_F1_SHIFT 8
2510 # define TV_VI_END_F1_MASK 0x00003f00
2512 # define TV_VI_END_F2_SHIFT 0
2513 # define TV_VI_END_F2_MASK 0x0000003f
2515 #define TV_V_CTL_2 0x68040
2516 /** Length of vsync, in half lines */
2517 # define TV_VSYNC_LEN_MASK 0x07ff0000
2518 # define TV_VSYNC_LEN_SHIFT 16
2519 /** Offset of the start of vsync in field 1, measured in one less than the
2520 * number of half lines.
2522 # define TV_VSYNC_START_F1_MASK 0x00007f00
2523 # define TV_VSYNC_START_F1_SHIFT 8
2525 * Offset of the start of vsync in field 2, measured in one less than the
2526 * number of half lines.
2528 # define TV_VSYNC_START_F2_MASK 0x0000007f
2529 # define TV_VSYNC_START_F2_SHIFT 0
2531 #define TV_V_CTL_3 0x68044
2532 /** Enables generation of the equalization signal */
2533 # define TV_EQUAL_ENA (1 << 31)
2534 /** Length of vsync, in half lines */
2535 # define TV_VEQ_LEN_MASK 0x007f0000
2536 # define TV_VEQ_LEN_SHIFT 16
2537 /** Offset of the start of equalization in field 1, measured in one less than
2538 * the number of half lines.
2540 # define TV_VEQ_START_F1_MASK 0x0007f00
2541 # define TV_VEQ_START_F1_SHIFT 8
2543 * Offset of the start of equalization in field 2, measured in one less than
2544 * the number of half lines.
2546 # define TV_VEQ_START_F2_MASK 0x000007f
2547 # define TV_VEQ_START_F2_SHIFT 0
2549 #define TV_V_CTL_4 0x68048
2551 * Offset to start of vertical colorburst, measured in one less than the
2552 * number of lines from vertical start.
2554 # define TV_VBURST_START_F1_MASK 0x003f0000
2555 # define TV_VBURST_START_F1_SHIFT 16
2557 * Offset to the end of vertical colorburst, measured in one less than the
2558 * number of lines from the start of NBR.
2560 # define TV_VBURST_END_F1_MASK 0x000000ff
2561 # define TV_VBURST_END_F1_SHIFT 0
2563 #define TV_V_CTL_5 0x6804c
2565 * Offset to start of vertical colorburst, measured in one less than the
2566 * number of lines from vertical start.
2568 # define TV_VBURST_START_F2_MASK 0x003f0000
2569 # define TV_VBURST_START_F2_SHIFT 16
2571 * Offset to the end of vertical colorburst, measured in one less than the
2572 * number of lines from the start of NBR.
2574 # define TV_VBURST_END_F2_MASK 0x000000ff
2575 # define TV_VBURST_END_F2_SHIFT 0
2577 #define TV_V_CTL_6 0x68050
2579 * Offset to start of vertical colorburst, measured in one less than the
2580 * number of lines from vertical start.
2582 # define TV_VBURST_START_F3_MASK 0x003f0000
2583 # define TV_VBURST_START_F3_SHIFT 16
2585 * Offset to the end of vertical colorburst, measured in one less than the
2586 * number of lines from the start of NBR.
2588 # define TV_VBURST_END_F3_MASK 0x000000ff
2589 # define TV_VBURST_END_F3_SHIFT 0
2591 #define TV_V_CTL_7 0x68054
2593 * Offset to start of vertical colorburst, measured in one less than the
2594 * number of lines from vertical start.
2596 # define TV_VBURST_START_F4_MASK 0x003f0000
2597 # define TV_VBURST_START_F4_SHIFT 16
2599 * Offset to the end of vertical colorburst, measured in one less than the
2600 * number of lines from the start of NBR.
2602 # define TV_VBURST_END_F4_MASK 0x000000ff
2603 # define TV_VBURST_END_F4_SHIFT 0
2605 #define TV_SC_CTL_1 0x68060
2606 /** Turns on the first subcarrier phase generation DDA */
2607 # define TV_SC_DDA1_EN (1 << 31)
2608 /** Turns on the first subcarrier phase generation DDA */
2609 # define TV_SC_DDA2_EN (1 << 30)
2610 /** Turns on the first subcarrier phase generation DDA */
2611 # define TV_SC_DDA3_EN (1 << 29)
2612 /** Sets the subcarrier DDA to reset frequency every other field */
2613 # define TV_SC_RESET_EVERY_2 (0 << 24)
2614 /** Sets the subcarrier DDA to reset frequency every fourth field */
2615 # define TV_SC_RESET_EVERY_4 (1 << 24)
2616 /** Sets the subcarrier DDA to reset frequency every eighth field */
2617 # define TV_SC_RESET_EVERY_8 (2 << 24)
2618 /** Sets the subcarrier DDA to never reset the frequency */
2619 # define TV_SC_RESET_NEVER (3 << 24)
2620 /** Sets the peak amplitude of the colorburst.*/
2621 # define TV_BURST_LEVEL_MASK 0x00ff0000
2622 # define TV_BURST_LEVEL_SHIFT 16
2623 /** Sets the increment of the first subcarrier phase generation DDA */
2624 # define TV_SCDDA1_INC_MASK 0x00000fff
2625 # define TV_SCDDA1_INC_SHIFT 0
2627 #define TV_SC_CTL_2 0x68064
2628 /** Sets the rollover for the second subcarrier phase generation DDA */
2629 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
2630 # define TV_SCDDA2_SIZE_SHIFT 16
2631 /** Sets the increent of the second subcarrier phase generation DDA */
2632 # define TV_SCDDA2_INC_MASK 0x00007fff
2633 # define TV_SCDDA2_INC_SHIFT 0
2635 #define TV_SC_CTL_3 0x68068
2636 /** Sets the rollover for the third subcarrier phase generation DDA */
2637 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
2638 # define TV_SCDDA3_SIZE_SHIFT 16
2639 /** Sets the increent of the third subcarrier phase generation DDA */
2640 # define TV_SCDDA3_INC_MASK 0x00007fff
2641 # define TV_SCDDA3_INC_SHIFT 0
2643 #define TV_WIN_POS 0x68070
2644 /** X coordinate of the display from the start of horizontal active */
2645 # define TV_XPOS_MASK 0x1fff0000
2646 # define TV_XPOS_SHIFT 16
2647 /** Y coordinate of the display from the start of vertical active (NBR) */
2648 # define TV_YPOS_MASK 0x00000fff
2649 # define TV_YPOS_SHIFT 0
2651 #define TV_WIN_SIZE 0x68074
2652 /** Horizontal size of the display window, measured in pixels*/
2653 # define TV_XSIZE_MASK 0x1fff0000
2654 # define TV_XSIZE_SHIFT 16
2656 * Vertical size of the display window, measured in pixels.
2658 * Must be even for interlaced modes.
2660 # define TV_YSIZE_MASK 0x00000fff
2661 # define TV_YSIZE_SHIFT 0
2663 #define TV_FILTER_CTL_1 0x68080
2665 * Enables automatic scaling calculation.
2667 * If set, the rest of the registers are ignored, and the calculated values can
2668 * be read back from the register.
2670 # define TV_AUTO_SCALE (1 << 31)
2672 * Disables the vertical filter.
2674 * This is required on modes more than 1024 pixels wide */
2675 # define TV_V_FILTER_BYPASS (1 << 29)
2676 /** Enables adaptive vertical filtering */
2677 # define TV_VADAPT (1 << 28)
2678 # define TV_VADAPT_MODE_MASK (3 << 26)
2679 /** Selects the least adaptive vertical filtering mode */
2680 # define TV_VADAPT_MODE_LEAST (0 << 26)
2681 /** Selects the moderately adaptive vertical filtering mode */
2682 # define TV_VADAPT_MODE_MODERATE (1 << 26)
2683 /** Selects the most adaptive vertical filtering mode */
2684 # define TV_VADAPT_MODE_MOST (3 << 26)
2686 * Sets the horizontal scaling factor.
2688 * This should be the fractional part of the horizontal scaling factor divided
2689 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
2691 * (src width - 1) / ((oversample * dest width) - 1)
2693 # define TV_HSCALE_FRAC_MASK 0x00003fff
2694 # define TV_HSCALE_FRAC_SHIFT 0
2696 #define TV_FILTER_CTL_2 0x68084
2698 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2700 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2702 # define TV_VSCALE_INT_MASK 0x00038000
2703 # define TV_VSCALE_INT_SHIFT 15
2705 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2707 * \sa TV_VSCALE_INT_MASK
2709 # define TV_VSCALE_FRAC_MASK 0x00007fff
2710 # define TV_VSCALE_FRAC_SHIFT 0
2712 #define TV_FILTER_CTL_3 0x68088
2714 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2716 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2718 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2720 # define TV_VSCALE_IP_INT_MASK 0x00038000
2721 # define TV_VSCALE_IP_INT_SHIFT 15
2723 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2725 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2727 * \sa TV_VSCALE_IP_INT_MASK
2729 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
2730 # define TV_VSCALE_IP_FRAC_SHIFT 0
2732 #define TV_CC_CONTROL 0x68090
2733 # define TV_CC_ENABLE (1 << 31)
2735 * Specifies which field to send the CC data in.
2737 * CC data is usually sent in field 0.
2739 # define TV_CC_FID_MASK (1 << 27)
2740 # define TV_CC_FID_SHIFT 27
2741 /** Sets the horizontal position of the CC data. Usually 135. */
2742 # define TV_CC_HOFF_MASK 0x03ff0000
2743 # define TV_CC_HOFF_SHIFT 16
2744 /** Sets the vertical position of the CC data. Usually 21 */
2745 # define TV_CC_LINE_MASK 0x0000003f
2746 # define TV_CC_LINE_SHIFT 0
2748 #define TV_CC_DATA 0x68094
2749 # define TV_CC_RDY (1 << 31)
2750 /** Second word of CC data to be transmitted. */
2751 # define TV_CC_DATA_2_MASK 0x007f0000
2752 # define TV_CC_DATA_2_SHIFT 16
2753 /** First word of CC data to be transmitted. */
2754 # define TV_CC_DATA_1_MASK 0x0000007f
2755 # define TV_CC_DATA_1_SHIFT 0
2757 #define TV_H_LUMA_0 0x68100
2758 #define TV_H_LUMA_59 0x681ec
2759 #define TV_H_CHROMA_0 0x68200
2760 #define TV_H_CHROMA_59 0x682ec
2761 #define TV_V_LUMA_0 0x68300
2762 #define TV_V_LUMA_42 0x683a8
2763 #define TV_V_CHROMA_0 0x68400
2764 #define TV_V_CHROMA_42 0x684a8
2767 #define DP_A 0x64000 /* eDP */
2768 #define DP_B 0x64100
2769 #define DP_C 0x64200
2770 #define DP_D 0x64300
2772 #define DP_PORT_EN (1 << 31)
2773 #define DP_PIPEB_SELECT (1 << 30)
2774 #define DP_PIPE_MASK (1 << 30)
2776 /* Link training mode - select a suitable mode for each stage */
2777 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
2778 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
2779 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
2780 #define DP_LINK_TRAIN_OFF (3 << 28)
2781 #define DP_LINK_TRAIN_MASK (3 << 28)
2782 #define DP_LINK_TRAIN_SHIFT 28
2784 /* CPT Link training mode */
2785 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
2786 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
2787 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
2788 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
2789 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
2790 #define DP_LINK_TRAIN_SHIFT_CPT 8
2792 /* Signal voltages. These are mostly controlled by the other end */
2793 #define DP_VOLTAGE_0_4 (0 << 25)
2794 #define DP_VOLTAGE_0_6 (1 << 25)
2795 #define DP_VOLTAGE_0_8 (2 << 25)
2796 #define DP_VOLTAGE_1_2 (3 << 25)
2797 #define DP_VOLTAGE_MASK (7 << 25)
2798 #define DP_VOLTAGE_SHIFT 25
2800 /* Signal pre-emphasis levels, like voltages, the other end tells us what
2803 #define DP_PRE_EMPHASIS_0 (0 << 22)
2804 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
2805 #define DP_PRE_EMPHASIS_6 (2 << 22)
2806 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
2807 #define DP_PRE_EMPHASIS_MASK (7 << 22)
2808 #define DP_PRE_EMPHASIS_SHIFT 22
2810 /* How many wires to use. I guess 3 was too hard */
2811 #define DP_PORT_WIDTH(width) (((width) - 1) << 19)
2812 #define DP_PORT_WIDTH_MASK (7 << 19)
2814 /* Mystic DPCD version 1.1 special mode */
2815 #define DP_ENHANCED_FRAMING (1 << 18)
2818 #define DP_PLL_FREQ_270MHZ (0 << 16)
2819 #define DP_PLL_FREQ_160MHZ (1 << 16)
2820 #define DP_PLL_FREQ_MASK (3 << 16)
2822 /** locked once port is enabled */
2823 #define DP_PORT_REVERSAL (1 << 15)
2826 #define DP_PLL_ENABLE (1 << 14)
2828 /** sends the clock on lane 15 of the PEG for debug */
2829 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
2831 #define DP_SCRAMBLING_DISABLE (1 << 12)
2832 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
2834 /** limit RGB values to avoid confusing TVs */
2835 #define DP_COLOR_RANGE_16_235 (1 << 8)
2837 /** Turn on the audio link */
2838 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
2840 /** vs and hs sync polarity */
2841 #define DP_SYNC_VS_HIGH (1 << 4)
2842 #define DP_SYNC_HS_HIGH (1 << 3)
2845 #define DP_DETECTED (1 << 2)
2847 /** The aux channel provides a way to talk to the
2848 * signal sink for DDC etc. Max packet size supported
2849 * is 20 bytes in each direction, hence the 5 fixed
2852 #define DPA_AUX_CH_CTL 0x64010
2853 #define DPA_AUX_CH_DATA1 0x64014
2854 #define DPA_AUX_CH_DATA2 0x64018
2855 #define DPA_AUX_CH_DATA3 0x6401c
2856 #define DPA_AUX_CH_DATA4 0x64020
2857 #define DPA_AUX_CH_DATA5 0x64024
2859 #define DPB_AUX_CH_CTL 0x64110
2860 #define DPB_AUX_CH_DATA1 0x64114
2861 #define DPB_AUX_CH_DATA2 0x64118
2862 #define DPB_AUX_CH_DATA3 0x6411c
2863 #define DPB_AUX_CH_DATA4 0x64120
2864 #define DPB_AUX_CH_DATA5 0x64124
2866 #define DPC_AUX_CH_CTL 0x64210
2867 #define DPC_AUX_CH_DATA1 0x64214
2868 #define DPC_AUX_CH_DATA2 0x64218
2869 #define DPC_AUX_CH_DATA3 0x6421c
2870 #define DPC_AUX_CH_DATA4 0x64220
2871 #define DPC_AUX_CH_DATA5 0x64224
2873 #define DPD_AUX_CH_CTL 0x64310
2874 #define DPD_AUX_CH_DATA1 0x64314
2875 #define DPD_AUX_CH_DATA2 0x64318
2876 #define DPD_AUX_CH_DATA3 0x6431c
2877 #define DPD_AUX_CH_DATA4 0x64320
2878 #define DPD_AUX_CH_DATA5 0x64324
2880 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
2881 #define DP_AUX_CH_CTL_DONE (1 << 30)
2882 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
2883 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
2884 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
2885 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
2886 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
2887 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
2888 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
2889 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
2890 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
2891 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
2892 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
2893 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
2894 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
2895 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
2896 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
2897 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
2898 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
2899 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
2900 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
2903 * Computing GMCH M and N values for the Display Port link
2905 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2907 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2909 * The GMCH value is used internally
2911 * bytes_per_pixel is the number of bytes coming out of the plane,
2912 * which is after the LUTs, so we want the bytes for our color format.
2913 * For our current usage, this is always 3, one byte for R, G and B.
2915 #define _PIPEA_DATA_M_G4X 0x70050
2916 #define _PIPEB_DATA_M_G4X 0x71050
2918 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2919 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
2920 #define TU_SIZE_SHIFT 25
2921 #define TU_SIZE_MASK (0x3f << 25)
2923 #define DATA_LINK_M_N_MASK (0xffffff)
2924 #define DATA_LINK_N_MAX (0x800000)
2926 #define _PIPEA_DATA_N_G4X 0x70054
2927 #define _PIPEB_DATA_N_G4X 0x71054
2928 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
2931 * Computing Link M and N values for the Display Port link
2933 * Link M / N = pixel_clock / ls_clk
2935 * (the DP spec calls pixel_clock the 'strm_clk')
2937 * The Link value is transmitted in the Main Stream
2938 * Attributes and VB-ID.
2941 #define _PIPEA_LINK_M_G4X 0x70060
2942 #define _PIPEB_LINK_M_G4X 0x71060
2943 #define PIPEA_DP_LINK_M_MASK (0xffffff)
2945 #define _PIPEA_LINK_N_G4X 0x70064
2946 #define _PIPEB_LINK_N_G4X 0x71064
2947 #define PIPEA_DP_LINK_N_MASK (0xffffff)
2949 #define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
2950 #define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
2951 #define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
2952 #define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
2954 /* Display & cursor control */
2957 #define _PIPEADSL (dev_priv->info->display_mmio_offset + 0x70000)
2958 #define DSL_LINEMASK_GEN2 0x00000fff
2959 #define DSL_LINEMASK_GEN3 0x00001fff
2960 #define _PIPEACONF (dev_priv->info->display_mmio_offset + 0x70008)
2961 #define PIPECONF_ENABLE (1<<31)
2962 #define PIPECONF_DISABLE 0
2963 #define PIPECONF_DOUBLE_WIDE (1<<30)
2964 #define I965_PIPECONF_ACTIVE (1<<30)
2965 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
2966 #define PIPECONF_SINGLE_WIDE 0
2967 #define PIPECONF_PIPE_UNLOCKED 0
2968 #define PIPECONF_PIPE_LOCKED (1<<25)
2969 #define PIPECONF_PALETTE 0
2970 #define PIPECONF_GAMMA (1<<24)
2971 #define PIPECONF_FORCE_BORDER (1<<25)
2972 #define PIPECONF_INTERLACE_MASK (7 << 21)
2973 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
2974 /* Note that pre-gen3 does not support interlaced display directly. Panel
2975 * fitting must be disabled on pre-ilk for interlaced. */
2976 #define PIPECONF_PROGRESSIVE (0 << 21)
2977 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
2978 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
2979 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2980 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
2981 /* Ironlake and later have a complete new set of values for interlaced. PFIT
2982 * means panel fitter required, PF means progressive fetch, DBL means power
2983 * saving pixel doubling. */
2984 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
2985 #define PIPECONF_INTERLACED_ILK (3 << 21)
2986 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
2987 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
2988 #define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
2989 #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
2990 #define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
2991 #define PIPECONF_BPC_MASK (0x7 << 5)
2992 #define PIPECONF_8BPC (0<<5)
2993 #define PIPECONF_10BPC (1<<5)
2994 #define PIPECONF_6BPC (2<<5)
2995 #define PIPECONF_12BPC (3<<5)
2996 #define PIPECONF_DITHER_EN (1<<4)
2997 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
2998 #define PIPECONF_DITHER_TYPE_SP (0<<2)
2999 #define PIPECONF_DITHER_TYPE_ST1 (1<<2)
3000 #define PIPECONF_DITHER_TYPE_ST2 (2<<2)
3001 #define PIPECONF_DITHER_TYPE_TEMP (3<<2)
3002 #define _PIPEASTAT (dev_priv->info->display_mmio_offset + 0x70024)
3003 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
3004 #define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30)
3005 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
3006 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
3007 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
3008 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
3009 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
3010 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
3011 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
3012 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
3013 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
3014 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
3015 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
3016 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
3017 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
3018 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
3019 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
3020 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
3021 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
3022 #define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15)
3023 #define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<14)
3024 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
3025 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
3026 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
3027 #define PLANE_FLIPDONE_INT_STATUS_VLV (1UL<<10)
3028 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
3029 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
3030 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
3031 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
3032 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
3033 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
3034 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
3035 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
3036 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
3037 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
3038 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
3040 #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
3041 #define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF)
3042 #define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
3043 #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
3044 #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
3045 #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
3047 #define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)
3048 #define PIPEB_LINE_COMPARE_INT_EN (1<<29)
3049 #define PIPEB_HLINE_INT_EN (1<<28)
3050 #define PIPEB_VBLANK_INT_EN (1<<27)
3051 #define SPRITED_FLIPDONE_INT_EN (1<<26)
3052 #define SPRITEC_FLIPDONE_INT_EN (1<<25)
3053 #define PLANEB_FLIPDONE_INT_EN (1<<24)
3054 #define PIPEA_LINE_COMPARE_INT_EN (1<<21)
3055 #define PIPEA_HLINE_INT_EN (1<<20)
3056 #define PIPEA_VBLANK_INT_EN (1<<19)
3057 #define SPRITEB_FLIPDONE_INT_EN (1<<18)
3058 #define SPRITEA_FLIPDONE_INT_EN (1<<17)
3059 #define PLANEA_FLIPDONE_INT_EN (1<<16)
3061 #define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV only */
3062 #define CURSORB_INVALID_GTT_INT_EN (1<<23)
3063 #define CURSORA_INVALID_GTT_INT_EN (1<<22)
3064 #define SPRITED_INVALID_GTT_INT_EN (1<<21)
3065 #define SPRITEC_INVALID_GTT_INT_EN (1<<20)
3066 #define PLANEB_INVALID_GTT_INT_EN (1<<19)
3067 #define SPRITEB_INVALID_GTT_INT_EN (1<<18)
3068 #define SPRITEA_INVALID_GTT_INT_EN (1<<17)
3069 #define PLANEA_INVALID_GTT_INT_EN (1<<16)
3070 #define DPINVGTT_EN_MASK 0xff0000
3071 #define CURSORB_INVALID_GTT_STATUS (1<<7)
3072 #define CURSORA_INVALID_GTT_STATUS (1<<6)
3073 #define SPRITED_INVALID_GTT_STATUS (1<<5)
3074 #define SPRITEC_INVALID_GTT_STATUS (1<<4)
3075 #define PLANEB_INVALID_GTT_STATUS (1<<3)
3076 #define SPRITEB_INVALID_GTT_STATUS (1<<2)
3077 #define SPRITEA_INVALID_GTT_STATUS (1<<1)
3078 #define PLANEA_INVALID_GTT_STATUS (1<<0)
3079 #define DPINVGTT_STATUS_MASK 0xff
3081 #define DSPARB 0x70030
3082 #define DSPARB_CSTART_MASK (0x7f << 7)
3083 #define DSPARB_CSTART_SHIFT 7
3084 #define DSPARB_BSTART_MASK (0x7f)
3085 #define DSPARB_BSTART_SHIFT 0
3086 #define DSPARB_BEND_SHIFT 9 /* on 855 */
3087 #define DSPARB_AEND_SHIFT 0
3089 #define DSPFW1 (dev_priv->info->display_mmio_offset + 0x70034)
3090 #define DSPFW_SR_SHIFT 23
3091 #define DSPFW_SR_MASK (0x1ff<<23)
3092 #define DSPFW_CURSORB_SHIFT 16
3093 #define DSPFW_CURSORB_MASK (0x3f<<16)
3094 #define DSPFW_PLANEB_SHIFT 8
3095 #define DSPFW_PLANEB_MASK (0x7f<<8)
3096 #define DSPFW_PLANEA_MASK (0x7f)
3097 #define DSPFW2 (dev_priv->info->display_mmio_offset + 0x70038)
3098 #define DSPFW_CURSORA_MASK 0x00003f00
3099 #define DSPFW_CURSORA_SHIFT 8
3100 #define DSPFW_PLANEC_MASK (0x7f)
3101 #define DSPFW3 (dev_priv->info->display_mmio_offset + 0x7003c)
3102 #define DSPFW_HPLL_SR_EN (1<<31)
3103 #define DSPFW_CURSOR_SR_SHIFT 24
3104 #define PINEVIEW_SELF_REFRESH_EN (1<<30)
3105 #define DSPFW_CURSOR_SR_MASK (0x3f<<24)
3106 #define DSPFW_HPLL_CURSOR_SHIFT 16
3107 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
3108 #define DSPFW_HPLL_SR_MASK (0x1ff)
3109 #define DSPFW4 (dev_priv->info->display_mmio_offset + 0x70070)
3110 #define DSPFW7 (dev_priv->info->display_mmio_offset + 0x7007c)
3112 /* drain latency register values*/
3113 #define DRAIN_LATENCY_PRECISION_32 32
3114 #define DRAIN_LATENCY_PRECISION_16 16
3115 #define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050)
3116 #define DDL_CURSORA_PRECISION_32 (1<<31)
3117 #define DDL_CURSORA_PRECISION_16 (0<<31)
3118 #define DDL_CURSORA_SHIFT 24
3119 #define DDL_PLANEA_PRECISION_32 (1<<7)
3120 #define DDL_PLANEA_PRECISION_16 (0<<7)
3121 #define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054)
3122 #define DDL_CURSORB_PRECISION_32 (1<<31)
3123 #define DDL_CURSORB_PRECISION_16 (0<<31)
3124 #define DDL_CURSORB_SHIFT 24
3125 #define DDL_PLANEB_PRECISION_32 (1<<7)
3126 #define DDL_PLANEB_PRECISION_16 (0<<7)
3128 /* FIFO watermark sizes etc */
3129 #define G4X_FIFO_LINE_SIZE 64
3130 #define I915_FIFO_LINE_SIZE 64
3131 #define I830_FIFO_LINE_SIZE 32
3133 #define VALLEYVIEW_FIFO_SIZE 255
3134 #define G4X_FIFO_SIZE 127
3135 #define I965_FIFO_SIZE 512
3136 #define I945_FIFO_SIZE 127
3137 #define I915_FIFO_SIZE 95
3138 #define I855GM_FIFO_SIZE 127 /* In cachelines */
3139 #define I830_FIFO_SIZE 95
3141 #define VALLEYVIEW_MAX_WM 0xff
3142 #define G4X_MAX_WM 0x3f
3143 #define I915_MAX_WM 0x3f
3145 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
3146 #define PINEVIEW_FIFO_LINE_SIZE 64
3147 #define PINEVIEW_MAX_WM 0x1ff
3148 #define PINEVIEW_DFT_WM 0x3f
3149 #define PINEVIEW_DFT_HPLLOFF_WM 0
3150 #define PINEVIEW_GUARD_WM 10
3151 #define PINEVIEW_CURSOR_FIFO 64
3152 #define PINEVIEW_CURSOR_MAX_WM 0x3f
3153 #define PINEVIEW_CURSOR_DFT_WM 0
3154 #define PINEVIEW_CURSOR_GUARD_WM 5
3156 #define VALLEYVIEW_CURSOR_MAX_WM 64
3157 #define I965_CURSOR_FIFO 64
3158 #define I965_CURSOR_MAX_WM 32
3159 #define I965_CURSOR_DFT_WM 8
3161 /* define the Watermark register on Ironlake */
3162 #define WM0_PIPEA_ILK 0x45100
3163 #define WM0_PIPE_PLANE_MASK (0x7f<<16)
3164 #define WM0_PIPE_PLANE_SHIFT 16
3165 #define WM0_PIPE_SPRITE_MASK (0x3f<<8)
3166 #define WM0_PIPE_SPRITE_SHIFT 8
3167 #define WM0_PIPE_CURSOR_MASK (0x1f)
3169 #define WM0_PIPEB_ILK 0x45104
3170 #define WM0_PIPEC_IVB 0x45200
3171 #define WM1_LP_ILK 0x45108
3172 #define WM1_LP_SR_EN (1<<31)
3173 #define WM1_LP_LATENCY_SHIFT 24
3174 #define WM1_LP_LATENCY_MASK (0x7f<<24)
3175 #define WM1_LP_FBC_MASK (0xf<<20)
3176 #define WM1_LP_FBC_SHIFT 20
3177 #define WM1_LP_SR_MASK (0x1ff<<8)
3178 #define WM1_LP_SR_SHIFT 8
3179 #define WM1_LP_CURSOR_MASK (0x3f)
3180 #define WM2_LP_ILK 0x4510c
3181 #define WM2_LP_EN (1<<31)
3182 #define WM3_LP_ILK 0x45110
3183 #define WM3_LP_EN (1<<31)
3184 #define WM1S_LP_ILK 0x45120
3185 #define WM2S_LP_IVB 0x45124
3186 #define WM3S_LP_IVB 0x45128
3187 #define WM1S_LP_EN (1<<31)
3189 #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
3190 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
3191 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
3193 /* Memory latency timer register */
3194 #define MLTR_ILK 0x11222
3195 #define MLTR_WM1_SHIFT 0
3196 #define MLTR_WM2_SHIFT 8
3197 /* the unit of memory self-refresh latency time is 0.5us */
3198 #define ILK_SRLT_MASK 0x3f
3200 /* define the fifo size on Ironlake */
3201 #define ILK_DISPLAY_FIFO 128
3202 #define ILK_DISPLAY_MAXWM 64
3203 #define ILK_DISPLAY_DFTWM 8
3204 #define ILK_CURSOR_FIFO 32
3205 #define ILK_CURSOR_MAXWM 16
3206 #define ILK_CURSOR_DFTWM 8
3208 #define ILK_DISPLAY_SR_FIFO 512
3209 #define ILK_DISPLAY_MAX_SRWM 0x1ff
3210 #define ILK_DISPLAY_DFT_SRWM 0x3f
3211 #define ILK_CURSOR_SR_FIFO 64
3212 #define ILK_CURSOR_MAX_SRWM 0x3f
3213 #define ILK_CURSOR_DFT_SRWM 8
3215 #define ILK_FIFO_LINE_SIZE 64
3217 /* define the WM info on Sandybridge */
3218 #define SNB_DISPLAY_FIFO 128
3219 #define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */
3220 #define SNB_DISPLAY_DFTWM 8
3221 #define SNB_CURSOR_FIFO 32
3222 #define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */
3223 #define SNB_CURSOR_DFTWM 8
3225 #define SNB_DISPLAY_SR_FIFO 512
3226 #define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */
3227 #define SNB_DISPLAY_DFT_SRWM 0x3f
3228 #define SNB_CURSOR_SR_FIFO 64
3229 #define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */
3230 #define SNB_CURSOR_DFT_SRWM 8
3232 #define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */
3234 #define SNB_FIFO_LINE_SIZE 64
3237 /* the address where we get all kinds of latency value */
3238 #define SSKPD 0x5d10
3239 #define SSKPD_WM_MASK 0x3f
3240 #define SSKPD_WM0_SHIFT 0
3241 #define SSKPD_WM1_SHIFT 8
3242 #define SSKPD_WM2_SHIFT 16
3243 #define SSKPD_WM3_SHIFT 24
3246 * The two pipe frame counter registers are not synchronized, so
3247 * reading a stable value is somewhat tricky. The following code
3251 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
3252 * PIPE_FRAME_HIGH_SHIFT;
3253 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
3254 * PIPE_FRAME_LOW_SHIFT);
3255 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
3256 * PIPE_FRAME_HIGH_SHIFT);
3257 * } while (high1 != high2);
3258 * frame = (high1 << 8) | low1;
3260 #define _PIPEAFRAMEHIGH (dev_priv->info->display_mmio_offset + 0x70040)
3261 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
3262 #define PIPE_FRAME_HIGH_SHIFT 0
3263 #define _PIPEAFRAMEPIXEL (dev_priv->info->display_mmio_offset + 0x70044)
3264 #define PIPE_FRAME_LOW_MASK 0xff000000
3265 #define PIPE_FRAME_LOW_SHIFT 24
3266 #define PIPE_PIXEL_MASK 0x00ffffff
3267 #define PIPE_PIXEL_SHIFT 0
3268 /* GM45+ just has to be different */
3269 #define _PIPEA_FRMCOUNT_GM45 0x70040
3270 #define _PIPEA_FLIPCOUNT_GM45 0x70044
3271 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
3273 /* Cursor A & B regs */
3274 #define _CURACNTR (dev_priv->info->display_mmio_offset + 0x70080)
3275 /* Old style CUR*CNTR flags (desktop 8xx) */
3276 #define CURSOR_ENABLE 0x80000000
3277 #define CURSOR_GAMMA_ENABLE 0x40000000
3278 #define CURSOR_STRIDE_MASK 0x30000000
3279 #define CURSOR_PIPE_CSC_ENABLE (1<<24)
3280 #define CURSOR_FORMAT_SHIFT 24
3281 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
3282 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
3283 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
3284 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
3285 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
3286 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
3287 /* New style CUR*CNTR flags */
3288 #define CURSOR_MODE 0x27
3289 #define CURSOR_MODE_DISABLE 0x00
3290 #define CURSOR_MODE_64_32B_AX 0x07
3291 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
3292 #define MCURSOR_PIPE_SELECT (1 << 28)
3293 #define MCURSOR_PIPE_A 0x00
3294 #define MCURSOR_PIPE_B (1 << 28)
3295 #define MCURSOR_GAMMA_ENABLE (1 << 26)
3296 #define _CURABASE (dev_priv->info->display_mmio_offset + 0x70084)
3297 #define _CURAPOS (dev_priv->info->display_mmio_offset + 0x70088)
3298 #define CURSOR_POS_MASK 0x007FF
3299 #define CURSOR_POS_SIGN 0x8000
3300 #define CURSOR_X_SHIFT 0
3301 #define CURSOR_Y_SHIFT 16
3302 #define CURSIZE 0x700a0
3303 #define _CURBCNTR (dev_priv->info->display_mmio_offset + 0x700c0)
3304 #define _CURBBASE (dev_priv->info->display_mmio_offset + 0x700c4)
3305 #define _CURBPOS (dev_priv->info->display_mmio_offset + 0x700c8)
3307 #define _CURBCNTR_IVB 0x71080
3308 #define _CURBBASE_IVB 0x71084
3309 #define _CURBPOS_IVB 0x71088
3311 #define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
3312 #define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
3313 #define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
3315 #define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB)
3316 #define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB)
3317 #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
3319 /* Display A control */
3320 #define _DSPACNTR (dev_priv->info->display_mmio_offset + 0x70180)
3321 #define DISPLAY_PLANE_ENABLE (1<<31)
3322 #define DISPLAY_PLANE_DISABLE 0
3323 #define DISPPLANE_GAMMA_ENABLE (1<<30)
3324 #define DISPPLANE_GAMMA_DISABLE 0
3325 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
3326 #define DISPPLANE_YUV422 (0x0<<26)
3327 #define DISPPLANE_8BPP (0x2<<26)
3328 #define DISPPLANE_BGRA555 (0x3<<26)
3329 #define DISPPLANE_BGRX555 (0x4<<26)
3330 #define DISPPLANE_BGRX565 (0x5<<26)
3331 #define DISPPLANE_BGRX888 (0x6<<26)
3332 #define DISPPLANE_BGRA888 (0x7<<26)
3333 #define DISPPLANE_RGBX101010 (0x8<<26)
3334 #define DISPPLANE_RGBA101010 (0x9<<26)
3335 #define DISPPLANE_BGRX101010 (0xa<<26)
3336 #define DISPPLANE_RGBX161616 (0xc<<26)
3337 #define DISPPLANE_RGBX888 (0xe<<26)
3338 #define DISPPLANE_RGBA888 (0xf<<26)
3339 #define DISPPLANE_STEREO_ENABLE (1<<25)
3340 #define DISPPLANE_STEREO_DISABLE 0
3341 #define DISPPLANE_PIPE_CSC_ENABLE (1<<24)
3342 #define DISPPLANE_SEL_PIPE_SHIFT 24
3343 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
3344 #define DISPPLANE_SEL_PIPE_A 0
3345 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
3346 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
3347 #define DISPPLANE_SRC_KEY_DISABLE 0
3348 #define DISPPLANE_LINE_DOUBLE (1<<20)
3349 #define DISPPLANE_NO_LINE_DOUBLE 0
3350 #define DISPPLANE_STEREO_POLARITY_FIRST 0
3351 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
3352 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
3353 #define DISPPLANE_TILED (1<<10)
3354 #define _DSPAADDR (dev_priv->info->display_mmio_offset + 0x70184)
3355 #define _DSPASTRIDE (dev_priv->info->display_mmio_offset + 0x70188)
3356 #define _DSPAPOS (dev_priv->info->display_mmio_offset + 0x7018C) /* reserved */
3357 #define _DSPASIZE (dev_priv->info->display_mmio_offset + 0x70190)
3358 #define _DSPASURF (dev_priv->info->display_mmio_offset + 0x7019C) /* 965+ only */
3359 #define _DSPATILEOFF (dev_priv->info->display_mmio_offset + 0x701A4) /* 965+ only */
3360 #define _DSPAOFFSET (dev_priv->info->display_mmio_offset + 0x701A4) /* HSW */
3361 #define _DSPASURFLIVE (dev_priv->info->display_mmio_offset + 0x701AC)
3363 #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
3364 #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
3365 #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
3366 #define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
3367 #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
3368 #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
3369 #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
3370 #define DSPLINOFF(plane) DSPADDR(plane)
3371 #define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET)
3372 #define DSPSURFLIVE(plane) _PIPE(plane, _DSPASURFLIVE, _DSPBSURFLIVE)
3374 /* Display/Sprite base address macros */
3375 #define DISP_BASEADDR_MASK (0xfffff000)
3376 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
3377 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
3378 #define I915_MODIFY_DISPBASE(reg, gfx_addr) \
3379 (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg))))
3382 #define SWF00 (dev_priv->info->display_mmio_offset + 0x71410)
3383 #define SWF01 (dev_priv->info->display_mmio_offset + 0x71414)
3384 #define SWF02 (dev_priv->info->display_mmio_offset + 0x71418)
3385 #define SWF03 (dev_priv->info->display_mmio_offset + 0x7141c)
3386 #define SWF04 (dev_priv->info->display_mmio_offset + 0x71420)
3387 #define SWF05 (dev_priv->info->display_mmio_offset + 0x71424)
3388 #define SWF06 (dev_priv->info->display_mmio_offset + 0x71428)
3389 #define SWF10 (dev_priv->info->display_mmio_offset + 0x70410)
3390 #define SWF11 (dev_priv->info->display_mmio_offset + 0x70414)
3391 #define SWF14 (dev_priv->info->display_mmio_offset + 0x71420)
3392 #define SWF30 (dev_priv->info->display_mmio_offset + 0x72414)
3393 #define SWF31 (dev_priv->info->display_mmio_offset + 0x72418)
3394 #define SWF32 (dev_priv->info->display_mmio_offset + 0x7241c)
3397 #define _PIPEBDSL (dev_priv->info->display_mmio_offset + 0x71000)
3398 #define _PIPEBCONF (dev_priv->info->display_mmio_offset + 0x71008)
3399 #define _PIPEBSTAT (dev_priv->info->display_mmio_offset + 0x71024)
3400 #define _PIPEBFRAMEHIGH (dev_priv->info->display_mmio_offset + 0x71040)
3401 #define _PIPEBFRAMEPIXEL (dev_priv->info->display_mmio_offset + 0x71044)
3402 #define _PIPEB_FRMCOUNT_GM45 0x71040
3403 #define _PIPEB_FLIPCOUNT_GM45 0x71044
3406 /* Display B control */
3407 #define _DSPBCNTR (dev_priv->info->display_mmio_offset + 0x71180)
3408 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
3409 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
3410 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
3411 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
3412 #define _DSPBADDR (dev_priv->info->display_mmio_offset + 0x71184)
3413 #define _DSPBSTRIDE (dev_priv->info->display_mmio_offset + 0x71188)
3414 #define _DSPBPOS (dev_priv->info->display_mmio_offset + 0x7118C)
3415 #define _DSPBSIZE (dev_priv->info->display_mmio_offset + 0x71190)
3416 #define _DSPBSURF (dev_priv->info->display_mmio_offset + 0x7119C)
3417 #define _DSPBTILEOFF (dev_priv->info->display_mmio_offset + 0x711A4)
3418 #define _DSPBOFFSET (dev_priv->info->display_mmio_offset + 0x711A4)
3419 #define _DSPBSURFLIVE (dev_priv->info->display_mmio_offset + 0x711AC)
3421 /* Sprite A control */
3422 #define _DVSACNTR 0x72180
3423 #define DVS_ENABLE (1<<31)
3424 #define DVS_GAMMA_ENABLE (1<<30)
3425 #define DVS_PIXFORMAT_MASK (3<<25)
3426 #define DVS_FORMAT_YUV422 (0<<25)
3427 #define DVS_FORMAT_RGBX101010 (1<<25)
3428 #define DVS_FORMAT_RGBX888 (2<<25)
3429 #define DVS_FORMAT_RGBX161616 (3<<25)
3430 #define DVS_PIPE_CSC_ENABLE (1<<24)
3431 #define DVS_SOURCE_KEY (1<<22)
3432 #define DVS_RGB_ORDER_XBGR (1<<20)
3433 #define DVS_YUV_BYTE_ORDER_MASK (3<<16)
3434 #define DVS_YUV_ORDER_YUYV (0<<16)
3435 #define DVS_YUV_ORDER_UYVY (1<<16)
3436 #define DVS_YUV_ORDER_YVYU (2<<16)
3437 #define DVS_YUV_ORDER_VYUY (3<<16)
3438 #define DVS_DEST_KEY (1<<2)
3439 #define DVS_TRICKLE_FEED_DISABLE (1<<14)
3440 #define DVS_TILED (1<<10)
3441 #define _DVSALINOFF 0x72184
3442 #define _DVSASTRIDE 0x72188
3443 #define _DVSAPOS 0x7218c
3444 #define _DVSASIZE 0x72190
3445 #define _DVSAKEYVAL 0x72194
3446 #define _DVSAKEYMSK 0x72198
3447 #define _DVSASURF 0x7219c
3448 #define _DVSAKEYMAXVAL 0x721a0
3449 #define _DVSATILEOFF 0x721a4
3450 #define _DVSASURFLIVE 0x721ac
3451 #define _DVSASCALE 0x72204
3452 #define DVS_SCALE_ENABLE (1<<31)
3453 #define DVS_FILTER_MASK (3<<29)
3454 #define DVS_FILTER_MEDIUM (0<<29)
3455 #define DVS_FILTER_ENHANCING (1<<29)
3456 #define DVS_FILTER_SOFTENING (2<<29)
3457 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
3458 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
3459 #define _DVSAGAMC 0x72300
3461 #define _DVSBCNTR 0x73180
3462 #define _DVSBLINOFF 0x73184
3463 #define _DVSBSTRIDE 0x73188
3464 #define _DVSBPOS 0x7318c
3465 #define _DVSBSIZE 0x73190
3466 #define _DVSBKEYVAL 0x73194
3467 #define _DVSBKEYMSK 0x73198
3468 #define _DVSBSURF 0x7319c
3469 #define _DVSBKEYMAXVAL 0x731a0
3470 #define _DVSBTILEOFF 0x731a4
3471 #define _DVSBSURFLIVE 0x731ac
3472 #define _DVSBSCALE 0x73204
3473 #define _DVSBGAMC 0x73300
3475 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
3476 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
3477 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
3478 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
3479 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
3480 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
3481 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
3482 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
3483 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
3484 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
3485 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
3486 #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
3488 #define _SPRA_CTL 0x70280
3489 #define SPRITE_ENABLE (1<<31)
3490 #define SPRITE_GAMMA_ENABLE (1<<30)
3491 #define SPRITE_PIXFORMAT_MASK (7<<25)
3492 #define SPRITE_FORMAT_YUV422 (0<<25)
3493 #define SPRITE_FORMAT_RGBX101010 (1<<25)
3494 #define SPRITE_FORMAT_RGBX888 (2<<25)
3495 #define SPRITE_FORMAT_RGBX161616 (3<<25)
3496 #define SPRITE_FORMAT_YUV444 (4<<25)
3497 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
3498 #define SPRITE_PIPE_CSC_ENABLE (1<<24)
3499 #define SPRITE_SOURCE_KEY (1<<22)
3500 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
3501 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
3502 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
3503 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
3504 #define SPRITE_YUV_ORDER_YUYV (0<<16)
3505 #define SPRITE_YUV_ORDER_UYVY (1<<16)
3506 #define SPRITE_YUV_ORDER_YVYU (2<<16)
3507 #define SPRITE_YUV_ORDER_VYUY (3<<16)
3508 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
3509 #define SPRITE_INT_GAMMA_ENABLE (1<<13)
3510 #define SPRITE_TILED (1<<10)
3511 #define SPRITE_DEST_KEY (1<<2)
3512 #define _SPRA_LINOFF 0x70284
3513 #define _SPRA_STRIDE 0x70288
3514 #define _SPRA_POS 0x7028c
3515 #define _SPRA_SIZE 0x70290
3516 #define _SPRA_KEYVAL 0x70294
3517 #define _SPRA_KEYMSK 0x70298
3518 #define _SPRA_SURF 0x7029c
3519 #define _SPRA_KEYMAX 0x702a0
3520 #define _SPRA_TILEOFF 0x702a4
3521 #define _SPRA_OFFSET 0x702a4
3522 #define _SPRA_SURFLIVE 0x702ac
3523 #define _SPRA_SCALE 0x70304
3524 #define SPRITE_SCALE_ENABLE (1<<31)
3525 #define SPRITE_FILTER_MASK (3<<29)
3526 #define SPRITE_FILTER_MEDIUM (0<<29)
3527 #define SPRITE_FILTER_ENHANCING (1<<29)
3528 #define SPRITE_FILTER_SOFTENING (2<<29)
3529 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
3530 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
3531 #define _SPRA_GAMC 0x70400
3533 #define _SPRB_CTL 0x71280
3534 #define _SPRB_LINOFF 0x71284
3535 #define _SPRB_STRIDE 0x71288
3536 #define _SPRB_POS 0x7128c
3537 #define _SPRB_SIZE 0x71290
3538 #define _SPRB_KEYVAL 0x71294
3539 #define _SPRB_KEYMSK 0x71298
3540 #define _SPRB_SURF 0x7129c
3541 #define _SPRB_KEYMAX 0x712a0
3542 #define _SPRB_TILEOFF 0x712a4
3543 #define _SPRB_OFFSET 0x712a4
3544 #define _SPRB_SURFLIVE 0x712ac
3545 #define _SPRB_SCALE 0x71304
3546 #define _SPRB_GAMC 0x71400
3548 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
3549 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
3550 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
3551 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
3552 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
3553 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
3554 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
3555 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
3556 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
3557 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
3558 #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
3559 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
3560 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
3561 #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
3563 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
3564 #define SP_ENABLE (1<<31)
3565 #define SP_GEAMMA_ENABLE (1<<30)
3566 #define SP_PIXFORMAT_MASK (0xf<<26)
3567 #define SP_FORMAT_YUV422 (0<<26)
3568 #define SP_FORMAT_BGR565 (5<<26)
3569 #define SP_FORMAT_BGRX8888 (6<<26)
3570 #define SP_FORMAT_BGRA8888 (7<<26)
3571 #define SP_FORMAT_RGBX1010102 (8<<26)
3572 #define SP_FORMAT_RGBA1010102 (9<<26)
3573 #define SP_FORMAT_RGBX8888 (0xe<<26)
3574 #define SP_FORMAT_RGBA8888 (0xf<<26)
3575 #define SP_SOURCE_KEY (1<<22)
3576 #define SP_YUV_BYTE_ORDER_MASK (3<<16)
3577 #define SP_YUV_ORDER_YUYV (0<<16)
3578 #define SP_YUV_ORDER_UYVY (1<<16)
3579 #define SP_YUV_ORDER_YVYU (2<<16)
3580 #define SP_YUV_ORDER_VYUY (3<<16)
3581 #define SP_TILED (1<<10)
3582 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
3583 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
3584 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
3585 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
3586 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
3587 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
3588 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
3589 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
3590 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
3591 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
3592 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
3594 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
3595 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
3596 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
3597 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
3598 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
3599 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
3600 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
3601 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
3602 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
3603 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
3604 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
3605 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
3607 #define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
3608 #define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
3609 #define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
3610 #define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
3611 #define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
3612 #define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
3613 #define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
3614 #define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
3615 #define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
3616 #define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
3617 #define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
3618 #define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
3621 #define VGACNTRL 0x71400
3622 # define VGA_DISP_DISABLE (1 << 31)
3623 # define VGA_2X_MODE (1 << 30)
3624 # define VGA_PIPE_B_SELECT (1 << 29)
3626 #define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400)
3630 #define CPU_VGACNTRL 0x41000
3632 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
3633 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
3634 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
3635 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
3636 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
3637 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
3638 #define DIGITAL_PORTA_NO_DETECT (0 << 0)
3639 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
3640 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
3642 /* refresh rate hardware control */
3643 #define RR_HW_CTL 0x45300
3644 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
3645 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
3647 #define FDI_PLL_BIOS_0 0x46000
3648 #define FDI_PLL_FB_CLOCK_MASK 0xff
3649 #define FDI_PLL_BIOS_1 0x46004
3650 #define FDI_PLL_BIOS_2 0x46008
3651 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c
3652 #define DISPLAY_PORT_PLL_BIOS_1 0x46010
3653 #define DISPLAY_PORT_PLL_BIOS_2 0x46014
3655 #define PCH_3DCGDIS0 0x46020
3656 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
3657 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
3659 #define PCH_3DCGDIS1 0x46024
3660 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
3662 #define FDI_PLL_FREQ_CTL 0x46030
3663 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
3664 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
3665 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
3668 #define _PIPEA_DATA_M1 (dev_priv->info->display_mmio_offset + 0x60030)
3669 #define PIPE_DATA_M1_OFFSET 0
3670 #define _PIPEA_DATA_N1 (dev_priv->info->display_mmio_offset + 0x60034)
3671 #define PIPE_DATA_N1_OFFSET 0
3673 #define _PIPEA_DATA_M2 (dev_priv->info->display_mmio_offset + 0x60038)
3674 #define PIPE_DATA_M2_OFFSET 0
3675 #define _PIPEA_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6003c)
3676 #define PIPE_DATA_N2_OFFSET 0
3678 #define _PIPEA_LINK_M1 (dev_priv->info->display_mmio_offset + 0x60040)
3679 #define PIPE_LINK_M1_OFFSET 0
3680 #define _PIPEA_LINK_N1 (dev_priv->info->display_mmio_offset + 0x60044)
3681 #define PIPE_LINK_N1_OFFSET 0
3683 #define _PIPEA_LINK_M2 (dev_priv->info->display_mmio_offset + 0x60048)
3684 #define PIPE_LINK_M2_OFFSET 0
3685 #define _PIPEA_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6004c)
3686 #define PIPE_LINK_N2_OFFSET 0
3688 /* PIPEB timing regs are same start from 0x61000 */
3690 #define _PIPEB_DATA_M1 (dev_priv->info->display_mmio_offset + 0x61030)
3691 #define _PIPEB_DATA_N1 (dev_priv->info->display_mmio_offset + 0x61034)
3693 #define _PIPEB_DATA_M2 (dev_priv->info->display_mmio_offset + 0x61038)
3694 #define _PIPEB_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6103c)
3696 #define _PIPEB_LINK_M1 (dev_priv->info->display_mmio_offset + 0x61040)
3697 #define _PIPEB_LINK_N1 (dev_priv->info->display_mmio_offset + 0x61044)
3699 #define _PIPEB_LINK_M2 (dev_priv->info->display_mmio_offset + 0x61048)
3700 #define _PIPEB_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6104c)
3702 #define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
3703 #define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
3704 #define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
3705 #define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
3706 #define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
3707 #define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
3708 #define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
3709 #define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
3711 /* CPU panel fitter */
3712 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
3713 #define _PFA_CTL_1 0x68080
3714 #define _PFB_CTL_1 0x68880
3715 #define PF_ENABLE (1<<31)
3716 #define PF_PIPE_SEL_MASK_IVB (3<<29)
3717 #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
3718 #define PF_FILTER_MASK (3<<23)
3719 #define PF_FILTER_PROGRAMMED (0<<23)
3720 #define PF_FILTER_MED_3x3 (1<<23)
3721 #define PF_FILTER_EDGE_ENHANCE (2<<23)
3722 #define PF_FILTER_EDGE_SOFTEN (3<<23)
3723 #define _PFA_WIN_SZ 0x68074
3724 #define _PFB_WIN_SZ 0x68874
3725 #define _PFA_WIN_POS 0x68070
3726 #define _PFB_WIN_POS 0x68870
3727 #define _PFA_VSCALE 0x68084
3728 #define _PFB_VSCALE 0x68884
3729 #define _PFA_HSCALE 0x68090
3730 #define _PFB_HSCALE 0x68890
3732 #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
3733 #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
3734 #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
3735 #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
3736 #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
3738 /* legacy palette */
3739 #define _LGC_PALETTE_A 0x4a000
3740 #define _LGC_PALETTE_B 0x4a800
3741 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
3743 #define _GAMMA_MODE_A 0x4a480
3744 #define _GAMMA_MODE_B 0x4ac80
3745 #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
3746 #define GAMMA_MODE_MODE_MASK (3 << 0)
3747 #define GAMMA_MODE_MODE_8BIT (0 << 0)
3748 #define GAMMA_MODE_MODE_10BIT (1 << 0)
3749 #define GAMMA_MODE_MODE_12BIT (2 << 0)
3750 #define GAMMA_MODE_MODE_SPLIT (3 << 0)
3753 #define DE_MASTER_IRQ_CONTROL (1 << 31)
3754 #define DE_SPRITEB_FLIP_DONE (1 << 29)
3755 #define DE_SPRITEA_FLIP_DONE (1 << 28)
3756 #define DE_PLANEB_FLIP_DONE (1 << 27)
3757 #define DE_PLANEA_FLIP_DONE (1 << 26)
3758 #define DE_PCU_EVENT (1 << 25)
3759 #define DE_GTT_FAULT (1 << 24)
3760 #define DE_POISON (1 << 23)
3761 #define DE_PERFORM_COUNTER (1 << 22)
3762 #define DE_PCH_EVENT (1 << 21)
3763 #define DE_AUX_CHANNEL_A (1 << 20)
3764 #define DE_DP_A_HOTPLUG (1 << 19)
3765 #define DE_GSE (1 << 18)
3766 #define DE_PIPEB_VBLANK (1 << 15)
3767 #define DE_PIPEB_EVEN_FIELD (1 << 14)
3768 #define DE_PIPEB_ODD_FIELD (1 << 13)
3769 #define DE_PIPEB_LINE_COMPARE (1 << 12)
3770 #define DE_PIPEB_VSYNC (1 << 11)
3771 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
3772 #define DE_PIPEA_VBLANK (1 << 7)
3773 #define DE_PIPEA_EVEN_FIELD (1 << 6)
3774 #define DE_PIPEA_ODD_FIELD (1 << 5)
3775 #define DE_PIPEA_LINE_COMPARE (1 << 4)
3776 #define DE_PIPEA_VSYNC (1 << 3)
3777 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
3779 /* More Ivybridge lolz */
3780 #define DE_ERR_INT_IVB (1<<30)
3781 #define DE_GSE_IVB (1<<29)
3782 #define DE_PCH_EVENT_IVB (1<<28)
3783 #define DE_DP_A_HOTPLUG_IVB (1<<27)
3784 #define DE_AUX_CHANNEL_A_IVB (1<<26)
3785 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
3786 #define DE_PLANEC_FLIP_DONE_IVB (1<<13)
3787 #define DE_PIPEC_VBLANK_IVB (1<<10)
3788 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
3789 #define DE_PLANEB_FLIP_DONE_IVB (1<<8)
3790 #define DE_PIPEB_VBLANK_IVB (1<<5)
3791 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
3792 #define DE_PLANEA_FLIP_DONE_IVB (1<<3)
3793 #define DE_PIPEA_VBLANK_IVB (1<<0)
3795 #define DE_PIPE_VBLANK_ILK(pipe) (1 << ((pipe * 8) + 7))
3796 #define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5))
3798 #define VLV_MASTER_IER 0x4400c /* Gunit master IER */
3799 #define MASTER_INTERRUPT_ENABLE (1<<31)
3801 #define DEISR 0x44000
3802 #define DEIMR 0x44004
3803 #define DEIIR 0x44008
3804 #define DEIER 0x4400c
3806 #define GTISR 0x44010
3807 #define GTIMR 0x44014
3808 #define GTIIR 0x44018
3809 #define GTIER 0x4401c
3811 #define ILK_DISPLAY_CHICKEN2 0x42004
3812 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
3813 #define ILK_ELPIN_409_SELECT (1 << 25)
3814 #define ILK_DPARB_GATE (1<<22)
3815 #define ILK_VSDPFD_FULL (1<<21)
3816 #define ILK_DISPLAY_CHICKEN_FUSES 0x42014
3817 #define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31)
3818 #define ILK_INTERNAL_DISPLAY_DISABLE (1<<30)
3819 #define ILK_DISPLAY_DEBUG_DISABLE (1<<29)
3820 #define ILK_HDCP_DISABLE (1<<25)
3821 #define ILK_eDP_A_DISABLE (1<<24)
3822 #define ILK_DESKTOP (1<<23)
3824 #define ILK_DSPCLK_GATE_D 0x42020
3825 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
3826 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
3827 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
3828 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
3829 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
3831 #define IVB_CHICKEN3 0x4200c
3832 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
3833 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
3835 #define CHICKEN_PAR1_1 0x42080
3836 #define FORCE_ARB_IDLE_PLANES (1 << 14)
3838 #define DISP_ARB_CTL 0x45000
3839 #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
3840 #define DISP_FBC_WM_DIS (1<<15)
3841 #define GEN7_MSG_CTL 0x45010
3842 #define WAIT_FOR_PCH_RESET_ACK (1<<1)
3843 #define WAIT_FOR_PCH_FLR_ACK (1<<0)
3846 #define GEN7_COMMON_SLICE_CHICKEN1 0x7010
3847 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
3849 #define GEN7_L3CNTLREG1 0xB01C
3850 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C
3851 #define GEN7_L3AGDIS (1<<19)
3853 #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
3854 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000
3856 #define GEN7_L3SQCREG4 0xb034
3857 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
3859 /* WaCatErrorRejectionIssue */
3860 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
3861 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
3863 #define HSW_FUSE_STRAP 0x42014
3864 #define HSW_CDCLK_LIMIT (1 << 24)
3868 /* south display engine interrupt: IBX */
3869 #define SDE_AUDIO_POWER_D (1 << 27)
3870 #define SDE_AUDIO_POWER_C (1 << 26)
3871 #define SDE_AUDIO_POWER_B (1 << 25)
3872 #define SDE_AUDIO_POWER_SHIFT (25)
3873 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
3874 #define SDE_GMBUS (1 << 24)
3875 #define SDE_AUDIO_HDCP_TRANSB (1 << 23)
3876 #define SDE_AUDIO_HDCP_TRANSA (1 << 22)
3877 #define SDE_AUDIO_HDCP_MASK (3 << 22)
3878 #define SDE_AUDIO_TRANSB (1 << 21)
3879 #define SDE_AUDIO_TRANSA (1 << 20)
3880 #define SDE_AUDIO_TRANS_MASK (3 << 20)
3881 #define SDE_POISON (1 << 19)
3883 #define SDE_FDI_RXB (1 << 17)
3884 #define SDE_FDI_RXA (1 << 16)
3885 #define SDE_FDI_MASK (3 << 16)
3886 #define SDE_AUXD (1 << 15)
3887 #define SDE_AUXC (1 << 14)
3888 #define SDE_AUXB (1 << 13)
3889 #define SDE_AUX_MASK (7 << 13)
3891 #define SDE_CRT_HOTPLUG (1 << 11)
3892 #define SDE_PORTD_HOTPLUG (1 << 10)
3893 #define SDE_PORTC_HOTPLUG (1 << 9)
3894 #define SDE_PORTB_HOTPLUG (1 << 8)
3895 #define SDE_SDVOB_HOTPLUG (1 << 6)
3896 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
3897 SDE_SDVOB_HOTPLUG | \
3898 SDE_PORTB_HOTPLUG | \
3899 SDE_PORTC_HOTPLUG | \
3901 #define SDE_TRANSB_CRC_DONE (1 << 5)
3902 #define SDE_TRANSB_CRC_ERR (1 << 4)
3903 #define SDE_TRANSB_FIFO_UNDER (1 << 3)
3904 #define SDE_TRANSA_CRC_DONE (1 << 2)
3905 #define SDE_TRANSA_CRC_ERR (1 << 1)
3906 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
3907 #define SDE_TRANS_MASK (0x3f)
3909 /* south display engine interrupt: CPT/PPT */
3910 #define SDE_AUDIO_POWER_D_CPT (1 << 31)
3911 #define SDE_AUDIO_POWER_C_CPT (1 << 30)
3912 #define SDE_AUDIO_POWER_B_CPT (1 << 29)
3913 #define SDE_AUDIO_POWER_SHIFT_CPT 29
3914 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
3915 #define SDE_AUXD_CPT (1 << 27)
3916 #define SDE_AUXC_CPT (1 << 26)
3917 #define SDE_AUXB_CPT (1 << 25)
3918 #define SDE_AUX_MASK_CPT (7 << 25)
3919 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
3920 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
3921 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
3922 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
3923 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
3924 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
3925 SDE_SDVOB_HOTPLUG_CPT | \
3926 SDE_PORTD_HOTPLUG_CPT | \
3927 SDE_PORTC_HOTPLUG_CPT | \
3928 SDE_PORTB_HOTPLUG_CPT)
3929 #define SDE_GMBUS_CPT (1 << 17)
3930 #define SDE_ERROR_CPT (1 << 16)
3931 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
3932 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
3933 #define SDE_FDI_RXC_CPT (1 << 8)
3934 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
3935 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
3936 #define SDE_FDI_RXB_CPT (1 << 4)
3937 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
3938 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
3939 #define SDE_FDI_RXA_CPT (1 << 0)
3940 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
3941 SDE_AUDIO_CP_REQ_B_CPT | \
3942 SDE_AUDIO_CP_REQ_A_CPT)
3943 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
3944 SDE_AUDIO_CP_CHG_B_CPT | \
3945 SDE_AUDIO_CP_CHG_A_CPT)
3946 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
3950 #define SDEISR 0xc4000
3951 #define SDEIMR 0xc4004
3952 #define SDEIIR 0xc4008
3953 #define SDEIER 0xc400c
3955 #define SERR_INT 0xc4040
3956 #define SERR_INT_POISON (1<<31)
3957 #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
3958 #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
3959 #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
3960 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
3962 /* digital port hotplug */
3963 #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
3964 #define PORTD_HOTPLUG_ENABLE (1 << 20)
3965 #define PORTD_PULSE_DURATION_2ms (0)
3966 #define PORTD_PULSE_DURATION_4_5ms (1 << 18)
3967 #define PORTD_PULSE_DURATION_6ms (2 << 18)
3968 #define PORTD_PULSE_DURATION_100ms (3 << 18)
3969 #define PORTD_PULSE_DURATION_MASK (3 << 18)
3970 #define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16)
3971 #define PORTD_HOTPLUG_NO_DETECT (0 << 16)
3972 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
3973 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
3974 #define PORTC_HOTPLUG_ENABLE (1 << 12)
3975 #define PORTC_PULSE_DURATION_2ms (0)
3976 #define PORTC_PULSE_DURATION_4_5ms (1 << 10)
3977 #define PORTC_PULSE_DURATION_6ms (2 << 10)
3978 #define PORTC_PULSE_DURATION_100ms (3 << 10)
3979 #define PORTC_PULSE_DURATION_MASK (3 << 10)
3980 #define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8)
3981 #define PORTC_HOTPLUG_NO_DETECT (0 << 8)
3982 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
3983 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
3984 #define PORTB_HOTPLUG_ENABLE (1 << 4)
3985 #define PORTB_PULSE_DURATION_2ms (0)
3986 #define PORTB_PULSE_DURATION_4_5ms (1 << 2)
3987 #define PORTB_PULSE_DURATION_6ms (2 << 2)
3988 #define PORTB_PULSE_DURATION_100ms (3 << 2)
3989 #define PORTB_PULSE_DURATION_MASK (3 << 2)
3990 #define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0)
3991 #define PORTB_HOTPLUG_NO_DETECT (0 << 0)
3992 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
3993 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
3995 #define PCH_GPIOA 0xc5010
3996 #define PCH_GPIOB 0xc5014
3997 #define PCH_GPIOC 0xc5018
3998 #define PCH_GPIOD 0xc501c
3999 #define PCH_GPIOE 0xc5020
4000 #define PCH_GPIOF 0xc5024
4002 #define PCH_GMBUS0 0xc5100
4003 #define PCH_GMBUS1 0xc5104
4004 #define PCH_GMBUS2 0xc5108
4005 #define PCH_GMBUS3 0xc510c
4006 #define PCH_GMBUS4 0xc5110
4007 #define PCH_GMBUS5 0xc5120
4009 #define _PCH_DPLL_A 0xc6014
4010 #define _PCH_DPLL_B 0xc6018
4011 #define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
4013 #define _PCH_FPA0 0xc6040
4014 #define FP_CB_TUNE (0x3<<22)
4015 #define _PCH_FPA1 0xc6044
4016 #define _PCH_FPB0 0xc6048
4017 #define _PCH_FPB1 0xc604c
4018 #define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
4019 #define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
4021 #define PCH_DPLL_TEST 0xc606c
4023 #define PCH_DREF_CONTROL 0xC6200
4024 #define DREF_CONTROL_MASK 0x7fc3
4025 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
4026 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
4027 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
4028 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
4029 #define DREF_SSC_SOURCE_DISABLE (0<<11)
4030 #define DREF_SSC_SOURCE_ENABLE (2<<11)
4031 #define DREF_SSC_SOURCE_MASK (3<<11)
4032 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
4033 #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
4034 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
4035 #define DREF_NONSPREAD_SOURCE_MASK (3<<9)
4036 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
4037 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
4038 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
4039 #define DREF_SSC4_DOWNSPREAD (0<<6)
4040 #define DREF_SSC4_CENTERSPREAD (1<<6)
4041 #define DREF_SSC1_DISABLE (0<<1)
4042 #define DREF_SSC1_ENABLE (1<<1)
4043 #define DREF_SSC4_DISABLE (0)
4044 #define DREF_SSC4_ENABLE (1)
4046 #define PCH_RAWCLK_FREQ 0xc6204
4047 #define FDL_TP1_TIMER_SHIFT 12
4048 #define FDL_TP1_TIMER_MASK (3<<12)
4049 #define FDL_TP2_TIMER_SHIFT 10
4050 #define FDL_TP2_TIMER_MASK (3<<10)
4051 #define RAWCLK_FREQ_MASK 0x3ff
4053 #define PCH_DPLL_TMR_CFG 0xc6208
4055 #define PCH_SSC4_PARMS 0xc6210
4056 #define PCH_SSC4_AUX_PARMS 0xc6214
4058 #define PCH_DPLL_SEL 0xc7000
4059 #define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4))
4060 #define TRANS_DPLLA_SEL(pipe) 0
4061 #define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3))
4065 #define _PCH_TRANS_HTOTAL_A 0xe0000
4066 #define TRANS_HTOTAL_SHIFT 16
4067 #define TRANS_HACTIVE_SHIFT 0
4068 #define _PCH_TRANS_HBLANK_A 0xe0004
4069 #define TRANS_HBLANK_END_SHIFT 16
4070 #define TRANS_HBLANK_START_SHIFT 0
4071 #define _PCH_TRANS_HSYNC_A 0xe0008
4072 #define TRANS_HSYNC_END_SHIFT 16
4073 #define TRANS_HSYNC_START_SHIFT 0
4074 #define _PCH_TRANS_VTOTAL_A 0xe000c
4075 #define TRANS_VTOTAL_SHIFT 16
4076 #define TRANS_VACTIVE_SHIFT 0
4077 #define _PCH_TRANS_VBLANK_A 0xe0010
4078 #define TRANS_VBLANK_END_SHIFT 16
4079 #define TRANS_VBLANK_START_SHIFT 0
4080 #define _PCH_TRANS_VSYNC_A 0xe0014
4081 #define TRANS_VSYNC_END_SHIFT 16
4082 #define TRANS_VSYNC_START_SHIFT 0
4083 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
4085 #define _PCH_TRANSA_DATA_M1 0xe0030
4086 #define _PCH_TRANSA_DATA_N1 0xe0034
4087 #define _PCH_TRANSA_DATA_M2 0xe0038
4088 #define _PCH_TRANSA_DATA_N2 0xe003c
4089 #define _PCH_TRANSA_LINK_M1 0xe0040
4090 #define _PCH_TRANSA_LINK_N1 0xe0044
4091 #define _PCH_TRANSA_LINK_M2 0xe0048
4092 #define _PCH_TRANSA_LINK_N2 0xe004c
4094 /* Per-transcoder DIP controls */
4096 #define _VIDEO_DIP_CTL_A 0xe0200
4097 #define _VIDEO_DIP_DATA_A 0xe0208
4098 #define _VIDEO_DIP_GCP_A 0xe0210
4100 #define _VIDEO_DIP_CTL_B 0xe1200
4101 #define _VIDEO_DIP_DATA_B 0xe1208
4102 #define _VIDEO_DIP_GCP_B 0xe1210
4104 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
4105 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
4106 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
4108 #define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
4109 #define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
4110 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
4112 #define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
4113 #define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
4114 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
4116 #define VLV_TVIDEO_DIP_CTL(pipe) \
4117 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
4118 #define VLV_TVIDEO_DIP_DATA(pipe) \
4119 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
4120 #define VLV_TVIDEO_DIP_GCP(pipe) \
4121 _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
4123 /* Haswell DIP controls */
4124 #define HSW_VIDEO_DIP_CTL_A 0x60200
4125 #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220
4126 #define HSW_VIDEO_DIP_VS_DATA_A 0x60260
4127 #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
4128 #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
4129 #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320
4130 #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240
4131 #define HSW_VIDEO_DIP_VS_ECC_A 0x60280
4132 #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
4133 #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300
4134 #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344
4135 #define HSW_VIDEO_DIP_GCP_A 0x60210
4137 #define HSW_VIDEO_DIP_CTL_B 0x61200
4138 #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220
4139 #define HSW_VIDEO_DIP_VS_DATA_B 0x61260
4140 #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
4141 #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
4142 #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320
4143 #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240
4144 #define HSW_VIDEO_DIP_VS_ECC_B 0x61280
4145 #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
4146 #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300
4147 #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344
4148 #define HSW_VIDEO_DIP_GCP_B 0x61210
4150 #define HSW_TVIDEO_DIP_CTL(trans) \
4151 _TRANSCODER(trans, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
4152 #define HSW_TVIDEO_DIP_AVI_DATA(trans) \
4153 _TRANSCODER(trans, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
4154 #define HSW_TVIDEO_DIP_SPD_DATA(trans) \
4155 _TRANSCODER(trans, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B)
4156 #define HSW_TVIDEO_DIP_GCP(trans) \
4157 _TRANSCODER(trans, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
4158 #define HSW_TVIDEO_DIP_VSC_DATA(trans) \
4159 _TRANSCODER(trans, HSW_VIDEO_DIP_VSC_DATA_A, HSW_VIDEO_DIP_VSC_DATA_B)
4161 #define HSW_STEREO_3D_CTL_A 0x70020
4162 #define S3D_ENABLE (1<<31)
4163 #define HSW_STEREO_3D_CTL_B 0x71020
4165 #define HSW_STEREO_3D_CTL(trans) \
4166 _TRANSCODER(trans, HSW_STEREO_3D_CTL_A, HSW_STEREO_3D_CTL_A)
4168 #define _PCH_TRANS_HTOTAL_B 0xe1000
4169 #define _PCH_TRANS_HBLANK_B 0xe1004
4170 #define _PCH_TRANS_HSYNC_B 0xe1008
4171 #define _PCH_TRANS_VTOTAL_B 0xe100c
4172 #define _PCH_TRANS_VBLANK_B 0xe1010
4173 #define _PCH_TRANS_VSYNC_B 0xe1014
4174 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
4176 #define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
4177 #define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
4178 #define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
4179 #define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
4180 #define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
4181 #define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
4182 #define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \
4183 _PCH_TRANS_VSYNCSHIFT_B)
4185 #define _PCH_TRANSB_DATA_M1 0xe1030
4186 #define _PCH_TRANSB_DATA_N1 0xe1034
4187 #define _PCH_TRANSB_DATA_M2 0xe1038
4188 #define _PCH_TRANSB_DATA_N2 0xe103c
4189 #define _PCH_TRANSB_LINK_M1 0xe1040
4190 #define _PCH_TRANSB_LINK_N1 0xe1044
4191 #define _PCH_TRANSB_LINK_M2 0xe1048
4192 #define _PCH_TRANSB_LINK_N2 0xe104c
4194 #define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
4195 #define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
4196 #define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
4197 #define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
4198 #define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
4199 #define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
4200 #define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
4201 #define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
4203 #define _PCH_TRANSACONF 0xf0008
4204 #define _PCH_TRANSBCONF 0xf1008
4205 #define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
4206 #define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */
4207 #define TRANS_DISABLE (0<<31)
4208 #define TRANS_ENABLE (1<<31)
4209 #define TRANS_STATE_MASK (1<<30)
4210 #define TRANS_STATE_DISABLE (0<<30)
4211 #define TRANS_STATE_ENABLE (1<<30)
4212 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
4213 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
4214 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
4215 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
4216 #define TRANS_INTERLACE_MASK (7<<21)
4217 #define TRANS_PROGRESSIVE (0<<21)
4218 #define TRANS_INTERLACED (3<<21)
4219 #define TRANS_LEGACY_INTERLACED_ILK (2<<21)
4220 #define TRANS_8BPC (0<<5)
4221 #define TRANS_10BPC (1<<5)
4222 #define TRANS_6BPC (2<<5)
4223 #define TRANS_12BPC (3<<5)
4225 #define _TRANSA_CHICKEN1 0xf0060
4226 #define _TRANSB_CHICKEN1 0xf1060
4227 #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
4228 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
4229 #define _TRANSA_CHICKEN2 0xf0064
4230 #define _TRANSB_CHICKEN2 0xf1064
4231 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
4232 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
4233 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
4234 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
4235 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
4236 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
4238 #define SOUTH_CHICKEN1 0xc2000
4239 #define FDIA_PHASE_SYNC_SHIFT_OVR 19
4240 #define FDIA_PHASE_SYNC_SHIFT_EN 18
4241 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
4242 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
4243 #define FDI_BC_BIFURCATION_SELECT (1 << 12)
4244 #define SOUTH_CHICKEN2 0xc2004
4245 #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
4246 #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
4247 #define DPLS_EDP_PPS_FIX_DIS (1<<0)
4249 #define _FDI_RXA_CHICKEN 0xc200c
4250 #define _FDI_RXB_CHICKEN 0xc2010
4251 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
4252 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
4253 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
4255 #define SOUTH_DSPCLK_GATE_D 0xc2020
4256 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
4257 #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
4260 #define _FDI_TXA_CTL 0x60100
4261 #define _FDI_TXB_CTL 0x61100
4262 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
4263 #define FDI_TX_DISABLE (0<<31)
4264 #define FDI_TX_ENABLE (1<<31)
4265 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
4266 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
4267 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
4268 #define FDI_LINK_TRAIN_NONE (3<<28)
4269 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
4270 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
4271 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
4272 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
4273 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
4274 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
4275 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
4276 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
4277 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
4278 SNB has different settings. */
4279 /* SNB A-stepping */
4280 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
4281 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
4282 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
4283 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
4284 /* SNB B-stepping */
4285 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
4286 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
4287 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
4288 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
4289 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
4290 #define FDI_DP_PORT_WIDTH_SHIFT 19
4291 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
4292 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
4293 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
4294 /* Ironlake: hardwired to 1 */
4295 #define FDI_TX_PLL_ENABLE (1<<14)
4297 /* Ivybridge has different bits for lolz */
4298 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
4299 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
4300 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
4301 #define FDI_LINK_TRAIN_NONE_IVB (3<<8)
4303 /* both Tx and Rx */
4304 #define FDI_COMPOSITE_SYNC (1<<11)
4305 #define FDI_LINK_TRAIN_AUTO (1<<10)
4306 #define FDI_SCRAMBLING_ENABLE (0<<7)
4307 #define FDI_SCRAMBLING_DISABLE (1<<7)
4309 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
4310 #define _FDI_RXA_CTL 0xf000c
4311 #define _FDI_RXB_CTL 0xf100c
4312 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
4313 #define FDI_RX_ENABLE (1<<31)
4314 /* train, dp width same as FDI_TX */
4315 #define FDI_FS_ERRC_ENABLE (1<<27)
4316 #define FDI_FE_ERRC_ENABLE (1<<26)
4317 #define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
4318 #define FDI_8BPC (0<<16)
4319 #define FDI_10BPC (1<<16)
4320 #define FDI_6BPC (2<<16)
4321 #define FDI_12BPC (3<<16)
4322 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
4323 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
4324 #define FDI_RX_PLL_ENABLE (1<<13)
4325 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
4326 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
4327 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
4328 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
4329 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
4330 #define FDI_PCDCLK (1<<4)
4332 #define FDI_AUTO_TRAINING (1<<10)
4333 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
4334 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
4335 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
4336 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
4337 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
4339 #define _FDI_RXA_MISC 0xf0010
4340 #define _FDI_RXB_MISC 0xf1010
4341 #define FDI_RX_PWRDN_LANE1_MASK (3<<26)
4342 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
4343 #define FDI_RX_PWRDN_LANE0_MASK (3<<24)
4344 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
4345 #define FDI_RX_TP1_TO_TP2_48 (2<<20)
4346 #define FDI_RX_TP1_TO_TP2_64 (3<<20)
4347 #define FDI_RX_FDI_DELAY_90 (0x90<<0)
4348 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
4350 #define _FDI_RXA_TUSIZE1 0xf0030
4351 #define _FDI_RXA_TUSIZE2 0xf0038
4352 #define _FDI_RXB_TUSIZE1 0xf1030
4353 #define _FDI_RXB_TUSIZE2 0xf1038
4354 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
4355 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
4357 /* FDI_RX interrupt register format */
4358 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
4359 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
4360 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
4361 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
4362 #define FDI_RX_FS_CODE_ERR (1<<6)
4363 #define FDI_RX_FE_CODE_ERR (1<<5)
4364 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
4365 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
4366 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
4367 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
4368 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
4370 #define _FDI_RXA_IIR 0xf0014
4371 #define _FDI_RXA_IMR 0xf0018
4372 #define _FDI_RXB_IIR 0xf1014
4373 #define _FDI_RXB_IMR 0xf1018
4374 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
4375 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
4377 #define FDI_PLL_CTL_1 0xfe000
4378 #define FDI_PLL_CTL_2 0xfe004
4380 #define PCH_LVDS 0xe1180
4381 #define LVDS_DETECTED (1 << 1)
4383 /* vlv has 2 sets of panel control regs. */
4384 #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
4385 #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
4386 #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
4387 #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
4388 #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
4390 #define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)
4391 #define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)
4392 #define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)
4393 #define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
4394 #define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
4396 #define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
4397 #define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
4398 #define VLV_PIPE_PP_ON_DELAYS(pipe) \
4399 _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
4400 #define VLV_PIPE_PP_OFF_DELAYS(pipe) \
4401 _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
4402 #define VLV_PIPE_PP_DIVISOR(pipe) \
4403 _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
4405 #define PCH_PP_STATUS 0xc7200
4406 #define PCH_PP_CONTROL 0xc7204
4407 #define PANEL_UNLOCK_REGS (0xabcd << 16)
4408 #define PANEL_UNLOCK_MASK (0xffff << 16)
4409 #define EDP_FORCE_VDD (1 << 3)
4410 #define EDP_BLC_ENABLE (1 << 2)
4411 #define PANEL_POWER_RESET (1 << 1)
4412 #define PANEL_POWER_OFF (0 << 0)
4413 #define PANEL_POWER_ON (1 << 0)
4414 #define PCH_PP_ON_DELAYS 0xc7208
4415 #define PANEL_PORT_SELECT_MASK (3 << 30)
4416 #define PANEL_PORT_SELECT_LVDS (0 << 30)
4417 #define PANEL_PORT_SELECT_DPA (1 << 30)
4418 #define EDP_PANEL (1 << 30)
4419 #define PANEL_PORT_SELECT_DPC (2 << 30)
4420 #define PANEL_PORT_SELECT_DPD (3 << 30)
4421 #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
4422 #define PANEL_POWER_UP_DELAY_SHIFT 16
4423 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
4424 #define PANEL_LIGHT_ON_DELAY_SHIFT 0
4426 #define PCH_PP_OFF_DELAYS 0xc720c
4427 #define PANEL_POWER_PORT_SELECT_MASK (0x3 << 30)
4428 #define PANEL_POWER_PORT_LVDS (0 << 30)
4429 #define PANEL_POWER_PORT_DP_A (1 << 30)
4430 #define PANEL_POWER_PORT_DP_C (2 << 30)
4431 #define PANEL_POWER_PORT_DP_D (3 << 30)
4432 #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
4433 #define PANEL_POWER_DOWN_DELAY_SHIFT 16
4434 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
4435 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0
4437 #define PCH_PP_DIVISOR 0xc7210
4438 #define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
4439 #define PP_REFERENCE_DIVIDER_SHIFT 8
4440 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
4441 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0
4443 #define PCH_DP_B 0xe4100
4444 #define PCH_DPB_AUX_CH_CTL 0xe4110
4445 #define PCH_DPB_AUX_CH_DATA1 0xe4114
4446 #define PCH_DPB_AUX_CH_DATA2 0xe4118
4447 #define PCH_DPB_AUX_CH_DATA3 0xe411c
4448 #define PCH_DPB_AUX_CH_DATA4 0xe4120
4449 #define PCH_DPB_AUX_CH_DATA5 0xe4124
4451 #define PCH_DP_C 0xe4200
4452 #define PCH_DPC_AUX_CH_CTL 0xe4210
4453 #define PCH_DPC_AUX_CH_DATA1 0xe4214
4454 #define PCH_DPC_AUX_CH_DATA2 0xe4218
4455 #define PCH_DPC_AUX_CH_DATA3 0xe421c
4456 #define PCH_DPC_AUX_CH_DATA4 0xe4220
4457 #define PCH_DPC_AUX_CH_DATA5 0xe4224
4459 #define PCH_DP_D 0xe4300
4460 #define PCH_DPD_AUX_CH_CTL 0xe4310
4461 #define PCH_DPD_AUX_CH_DATA1 0xe4314
4462 #define PCH_DPD_AUX_CH_DATA2 0xe4318
4463 #define PCH_DPD_AUX_CH_DATA3 0xe431c
4464 #define PCH_DPD_AUX_CH_DATA4 0xe4320
4465 #define PCH_DPD_AUX_CH_DATA5 0xe4324
4468 #define PORT_TRANS_A_SEL_CPT 0
4469 #define PORT_TRANS_B_SEL_CPT (1<<29)
4470 #define PORT_TRANS_C_SEL_CPT (2<<29)
4471 #define PORT_TRANS_SEL_MASK (3<<29)
4472 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
4473 #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
4474 #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
4476 #define TRANS_DP_CTL_A 0xe0300
4477 #define TRANS_DP_CTL_B 0xe1300
4478 #define TRANS_DP_CTL_C 0xe2300
4479 #define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
4480 #define TRANS_DP_OUTPUT_ENABLE (1<<31)
4481 #define TRANS_DP_PORT_SEL_B (0<<29)
4482 #define TRANS_DP_PORT_SEL_C (1<<29)
4483 #define TRANS_DP_PORT_SEL_D (2<<29)
4484 #define TRANS_DP_PORT_SEL_NONE (3<<29)
4485 #define TRANS_DP_PORT_SEL_MASK (3<<29)
4486 #define TRANS_DP_AUDIO_ONLY (1<<26)
4487 #define TRANS_DP_ENH_FRAMING (1<<18)
4488 #define TRANS_DP_8BPC (0<<9)
4489 #define TRANS_DP_10BPC (1<<9)
4490 #define TRANS_DP_6BPC (2<<9)
4491 #define TRANS_DP_12BPC (3<<9)
4492 #define TRANS_DP_BPC_MASK (3<<9)
4493 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
4494 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
4495 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
4496 #define TRANS_DP_HSYNC_ACTIVE_LOW 0
4497 #define TRANS_DP_SYNC_MASK (3<<3)
4499 /* SNB eDP training params */
4500 /* SNB A-stepping */
4501 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
4502 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
4503 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
4504 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
4505 /* SNB B-stepping */
4506 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
4507 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
4508 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
4509 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
4510 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
4511 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
4514 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
4515 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
4516 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
4517 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
4518 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
4519 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
4520 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x33 <<22)
4523 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
4524 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
4525 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
4526 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
4527 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
4529 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
4531 #define FORCEWAKE 0xA18C
4532 #define FORCEWAKE_VLV 0x1300b0
4533 #define FORCEWAKE_ACK_VLV 0x1300b4
4534 #define FORCEWAKE_MEDIA_VLV 0x1300b8
4535 #define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc
4536 #define FORCEWAKE_ACK_HSW 0x130044
4537 #define FORCEWAKE_ACK 0x130090
4538 #define VLV_GTLC_WAKE_CTRL 0x130090
4539 #define VLV_GTLC_PW_STATUS 0x130094
4540 #define FORCEWAKE_MT 0xa188 /* multi-threaded */
4541 #define FORCEWAKE_KERNEL 0x1
4542 #define FORCEWAKE_USER 0x2
4543 #define FORCEWAKE_MT_ACK 0x130040
4544 #define ECOBUS 0xa180
4545 #define FORCEWAKE_MT_ENABLE (1<<5)
4547 #define GTFIFODBG 0x120000
4548 #define GT_FIFO_CPU_ERROR_MASK 7
4549 #define GT_FIFO_OVFERR (1<<2)
4550 #define GT_FIFO_IAWRERR (1<<1)
4551 #define GT_FIFO_IARDERR (1<<0)
4553 #define GT_FIFO_FREE_ENTRIES 0x120008
4554 #define GT_FIFO_NUM_RESERVED_ENTRIES 20
4556 #define HSW_IDICR 0x9008
4557 #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
4558 #define HSW_EDRAM_PRESENT 0x120010
4560 #define GEN6_UCGCTL1 0x9400
4561 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
4562 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
4564 #define GEN6_UCGCTL2 0x9404
4565 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
4566 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
4567 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
4568 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
4569 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
4571 #define GEN7_UCGCTL4 0x940c
4572 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
4574 #define GEN6_RPNSWREQ 0xA008
4575 #define GEN6_TURBO_DISABLE (1<<31)
4576 #define GEN6_FREQUENCY(x) ((x)<<25)
4577 #define HSW_FREQUENCY(x) ((x)<<24)
4578 #define GEN6_OFFSET(x) ((x)<<19)
4579 #define GEN6_AGGRESSIVE_TURBO (0<<15)
4580 #define GEN6_RC_VIDEO_FREQ 0xA00C
4581 #define GEN6_RC_CONTROL 0xA090
4582 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
4583 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
4584 #define GEN6_RC_CTL_RC6_ENABLE (1<<18)
4585 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
4586 #define GEN6_RC_CTL_RC7_ENABLE (1<<22)
4587 #define GEN7_RC_CTL_TO_MODE (1<<28)
4588 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
4589 #define GEN6_RC_CTL_HW_ENABLE (1<<31)
4590 #define GEN6_RP_DOWN_TIMEOUT 0xA010
4591 #define GEN6_RP_INTERRUPT_LIMITS 0xA014
4592 #define GEN6_RPSTAT1 0xA01C
4593 #define GEN6_CAGF_SHIFT 8
4594 #define HSW_CAGF_SHIFT 7
4595 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
4596 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
4597 #define GEN6_RP_CONTROL 0xA024
4598 #define GEN6_RP_MEDIA_TURBO (1<<11)
4599 #define GEN6_RP_MEDIA_MODE_MASK (3<<9)
4600 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
4601 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
4602 #define GEN6_RP_MEDIA_HW_MODE (1<<9)
4603 #define GEN6_RP_MEDIA_SW_MODE (0<<9)
4604 #define GEN6_RP_MEDIA_IS_GFX (1<<8)
4605 #define GEN6_RP_ENABLE (1<<7)
4606 #define GEN6_RP_UP_IDLE_MIN (0x1<<3)
4607 #define GEN6_RP_UP_BUSY_AVG (0x2<<3)
4608 #define GEN6_RP_UP_BUSY_CONT (0x4<<3)
4609 #define GEN7_RP_DOWN_IDLE_AVG (0x2<<0)
4610 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
4611 #define GEN6_RP_UP_THRESHOLD 0xA02C
4612 #define GEN6_RP_DOWN_THRESHOLD 0xA030
4613 #define GEN6_RP_CUR_UP_EI 0xA050
4614 #define GEN6_CURICONT_MASK 0xffffff
4615 #define GEN6_RP_CUR_UP 0xA054
4616 #define GEN6_CURBSYTAVG_MASK 0xffffff
4617 #define GEN6_RP_PREV_UP 0xA058
4618 #define GEN6_RP_CUR_DOWN_EI 0xA05C
4619 #define GEN6_CURIAVG_MASK 0xffffff
4620 #define GEN6_RP_CUR_DOWN 0xA060
4621 #define GEN6_RP_PREV_DOWN 0xA064
4622 #define GEN6_RP_UP_EI 0xA068
4623 #define GEN6_RP_DOWN_EI 0xA06C
4624 #define GEN6_RP_IDLE_HYSTERSIS 0xA070
4625 #define GEN6_RC_STATE 0xA094
4626 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
4627 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
4628 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
4629 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
4630 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
4631 #define GEN6_RC_SLEEP 0xA0B0
4632 #define GEN6_RC1e_THRESHOLD 0xA0B4
4633 #define GEN6_RC6_THRESHOLD 0xA0B8
4634 #define GEN6_RC6p_THRESHOLD 0xA0BC
4635 #define GEN6_RC6pp_THRESHOLD 0xA0C0
4636 #define GEN6_PMINTRMSK 0xA168
4638 #define GEN6_PMISR 0x44020
4639 #define GEN6_PMIMR 0x44024 /* rps_lock */
4640 #define GEN6_PMIIR 0x44028
4641 #define GEN6_PMIER 0x4402C
4642 #define GEN6_PM_MBOX_EVENT (1<<25)
4643 #define GEN6_PM_THERMAL_EVENT (1<<24)
4644 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
4645 #define GEN6_PM_RP_UP_THRESHOLD (1<<5)
4646 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
4647 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
4648 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
4649 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
4650 GEN6_PM_RP_DOWN_THRESHOLD | \
4651 GEN6_PM_RP_DOWN_TIMEOUT)
4653 #define GEN6_GT_GFX_RC6_LOCKED 0x138104
4654 #define GEN6_GT_GFX_RC6 0x138108
4655 #define GEN6_GT_GFX_RC6p 0x13810C
4656 #define GEN6_GT_GFX_RC6pp 0x138110
4658 #define GEN6_PCODE_MAILBOX 0x138124
4659 #define GEN6_PCODE_READY (1<<31)
4660 #define GEN6_READ_OC_PARAMS 0xc
4661 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
4662 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
4663 #define GEN6_PCODE_WRITE_RC6VIDS 0x4
4664 #define GEN6_PCODE_READ_RC6VIDS 0x5
4665 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
4666 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
4667 #define GEN6_PCODE_DATA 0x138128
4668 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
4669 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
4671 #define GEN6_GT_CORE_STATUS 0x138060
4672 #define GEN6_CORE_CPD_STATE_MASK (7<<4)
4673 #define GEN6_RCn_MASK 7
4679 #define GEN7_MISCCPCTL (0x9424)
4680 #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
4683 #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */
4684 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
4685 #define GEN7_PARITY_ERROR_VALID (1<<13)
4686 #define GEN7_L3CDERRST1_BANK_MASK (3<<11)
4687 #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
4688 #define GEN7_PARITY_ERROR_ROW(reg) \
4689 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
4690 #define GEN7_PARITY_ERROR_BANK(reg) \
4691 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
4692 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
4693 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
4694 #define GEN7_L3CDERRST1_ENABLE (1<<7)
4696 #define GEN7_L3LOG_BASE 0xB070
4697 #define GEN7_L3LOG_SIZE 0x80
4699 #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
4700 #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100
4701 #define GEN7_MAX_PS_THREAD_DEP (8<<12)
4702 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
4704 #define GEN7_ROW_CHICKEN2 0xe4f4
4705 #define GEN7_ROW_CHICKEN2_GT2 0xf4f4
4706 #define DOP_CLOCK_GATING_DISABLE (1<<0)
4708 #define G4X_AUD_VID_DID (dev_priv->info->display_mmio_offset + 0x62020)
4709 #define INTEL_AUDIO_DEVCL 0x808629FB
4710 #define INTEL_AUDIO_DEVBLC 0x80862801
4711 #define INTEL_AUDIO_DEVCTG 0x80862802
4713 #define G4X_AUD_CNTL_ST 0x620B4
4714 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
4715 #define G4X_ELDV_DEVCTG (1 << 14)
4716 #define G4X_ELD_ADDR (0xf << 5)
4717 #define G4X_ELD_ACK (1 << 4)
4718 #define G4X_HDMIW_HDMIEDID 0x6210C
4720 #define IBX_HDMIW_HDMIEDID_A 0xE2050
4721 #define IBX_HDMIW_HDMIEDID_B 0xE2150
4722 #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
4723 IBX_HDMIW_HDMIEDID_A, \
4724 IBX_HDMIW_HDMIEDID_B)
4725 #define IBX_AUD_CNTL_ST_A 0xE20B4
4726 #define IBX_AUD_CNTL_ST_B 0xE21B4
4727 #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
4728 IBX_AUD_CNTL_ST_A, \
4730 #define IBX_ELD_BUFFER_SIZE (0x1f << 10)
4731 #define IBX_ELD_ADDRESS (0x1f << 5)
4732 #define IBX_ELD_ACK (1 << 4)
4733 #define IBX_AUD_CNTL_ST2 0xE20C0
4734 #define IBX_ELD_VALIDB (1 << 0)
4735 #define IBX_CP_READYB (1 << 1)
4737 #define CPT_HDMIW_HDMIEDID_A 0xE5050
4738 #define CPT_HDMIW_HDMIEDID_B 0xE5150
4739 #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
4740 CPT_HDMIW_HDMIEDID_A, \
4741 CPT_HDMIW_HDMIEDID_B)
4742 #define CPT_AUD_CNTL_ST_A 0xE50B4
4743 #define CPT_AUD_CNTL_ST_B 0xE51B4
4744 #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
4745 CPT_AUD_CNTL_ST_A, \
4747 #define CPT_AUD_CNTRL_ST2 0xE50C0
4749 /* These are the 4 32-bit write offset registers for each stream
4750 * output buffer. It determines the offset from the
4751 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
4753 #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
4755 #define IBX_AUD_CONFIG_A 0xe2000
4756 #define IBX_AUD_CONFIG_B 0xe2100
4757 #define IBX_AUD_CFG(pipe) _PIPE(pipe, \
4760 #define CPT_AUD_CONFIG_A 0xe5000
4761 #define CPT_AUD_CONFIG_B 0xe5100
4762 #define CPT_AUD_CFG(pipe) _PIPE(pipe, \
4765 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
4766 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
4767 #define AUD_CONFIG_UPPER_N_SHIFT 20
4768 #define AUD_CONFIG_UPPER_N_VALUE (0xff << 20)
4769 #define AUD_CONFIG_LOWER_N_SHIFT 4
4770 #define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4)
4771 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
4772 #define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16)
4773 #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
4776 #define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */
4777 #define HSW_AUD_CONFIG_B 0x65100 /* Audio Configuration Transcoder B */
4778 #define HSW_AUD_CFG(pipe) _PIPE(pipe, \
4782 #define HSW_AUD_MISC_CTRL_A 0x65010 /* Audio Misc Control Convert 1 */
4783 #define HSW_AUD_MISC_CTRL_B 0x65110 /* Audio Misc Control Convert 2 */
4784 #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
4785 HSW_AUD_MISC_CTRL_A, \
4786 HSW_AUD_MISC_CTRL_B)
4788 #define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /* Audio DIP and ELD Control State Transcoder A */
4789 #define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /* Audio DIP and ELD Control State Transcoder B */
4790 #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
4791 HSW_AUD_DIP_ELD_CTRL_ST_A, \
4792 HSW_AUD_DIP_ELD_CTRL_ST_B)
4794 /* Audio Digital Converter */
4795 #define HSW_AUD_DIG_CNVT_1 0x65080 /* Audio Converter 1 */
4796 #define HSW_AUD_DIG_CNVT_2 0x65180 /* Audio Converter 1 */
4797 #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
4798 HSW_AUD_DIG_CNVT_1, \
4800 #define DIP_PORT_SEL_MASK 0x3
4802 #define HSW_AUD_EDID_DATA_A 0x65050
4803 #define HSW_AUD_EDID_DATA_B 0x65150
4804 #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
4805 HSW_AUD_EDID_DATA_A, \
4806 HSW_AUD_EDID_DATA_B)
4808 #define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */
4809 #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */
4810 #define AUDIO_INACTIVE_C (1<<11)
4811 #define AUDIO_INACTIVE_B (1<<7)
4812 #define AUDIO_INACTIVE_A (1<<3)
4813 #define AUDIO_OUTPUT_ENABLE_A (1<<2)
4814 #define AUDIO_OUTPUT_ENABLE_B (1<<6)
4815 #define AUDIO_OUTPUT_ENABLE_C (1<<10)
4816 #define AUDIO_ELD_VALID_A (1<<0)
4817 #define AUDIO_ELD_VALID_B (1<<4)
4818 #define AUDIO_ELD_VALID_C (1<<8)
4819 #define AUDIO_CP_READY_A (1<<1)
4820 #define AUDIO_CP_READY_B (1<<5)
4821 #define AUDIO_CP_READY_C (1<<9)
4823 /* HSW Power Wells */
4824 #define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */
4825 #define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */
4826 #define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */
4827 #define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */
4828 #define HSW_PWR_WELL_ENABLE (1<<31)
4829 #define HSW_PWR_WELL_STATE (1<<30)
4830 #define HSW_PWR_WELL_CTL5 0x45410
4831 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
4832 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
4833 #define HSW_PWR_WELL_FORCE_ON (1<<19)
4834 #define HSW_PWR_WELL_CTL6 0x45414
4836 /* Per-pipe DDI Function Control */
4837 #define TRANS_DDI_FUNC_CTL_A 0x60400
4838 #define TRANS_DDI_FUNC_CTL_B 0x61400
4839 #define TRANS_DDI_FUNC_CTL_C 0x62400
4840 #define TRANS_DDI_FUNC_CTL_EDP 0x6F400
4841 #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \
4842 TRANS_DDI_FUNC_CTL_B)
4843 #define TRANS_DDI_FUNC_ENABLE (1<<31)
4844 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
4845 #define TRANS_DDI_PORT_MASK (7<<28)
4846 #define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
4847 #define TRANS_DDI_PORT_NONE (0<<28)
4848 #define TRANS_DDI_MODE_SELECT_MASK (7<<24)
4849 #define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
4850 #define TRANS_DDI_MODE_SELECT_DVI (1<<24)
4851 #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
4852 #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
4853 #define TRANS_DDI_MODE_SELECT_FDI (4<<24)
4854 #define TRANS_DDI_BPC_MASK (7<<20)
4855 #define TRANS_DDI_BPC_8 (0<<20)
4856 #define TRANS_DDI_BPC_10 (1<<20)
4857 #define TRANS_DDI_BPC_6 (2<<20)
4858 #define TRANS_DDI_BPC_12 (3<<20)
4859 #define TRANS_DDI_PVSYNC (1<<17)
4860 #define TRANS_DDI_PHSYNC (1<<16)
4861 #define TRANS_DDI_EDP_INPUT_MASK (7<<12)
4862 #define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
4863 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
4864 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
4865 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
4866 #define TRANS_DDI_BFI_ENABLE (1<<4)
4868 /* DisplayPort Transport Control */
4869 #define DP_TP_CTL_A 0x64040
4870 #define DP_TP_CTL_B 0x64140
4871 #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
4872 #define DP_TP_CTL_ENABLE (1<<31)
4873 #define DP_TP_CTL_MODE_SST (0<<27)
4874 #define DP_TP_CTL_MODE_MST (1<<27)
4875 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
4876 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
4877 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
4878 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
4879 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
4880 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
4881 #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
4882 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
4883 #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
4885 /* DisplayPort Transport Status */
4886 #define DP_TP_STATUS_A 0x64044
4887 #define DP_TP_STATUS_B 0x64144
4888 #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
4889 #define DP_TP_STATUS_IDLE_DONE (1<<25)
4890 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
4892 /* DDI Buffer Control */
4893 #define DDI_BUF_CTL_A 0x64000
4894 #define DDI_BUF_CTL_B 0x64100
4895 #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
4896 #define DDI_BUF_CTL_ENABLE (1<<31)
4897 #define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */
4898 #define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */
4899 #define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */
4900 #define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */
4901 #define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */
4902 #define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */
4903 #define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */
4904 #define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */
4905 #define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */
4906 #define DDI_BUF_EMP_MASK (0xf<<24)
4907 #define DDI_BUF_PORT_REVERSAL (1<<16)
4908 #define DDI_BUF_IS_IDLE (1<<7)
4909 #define DDI_A_4_LANES (1<<4)
4910 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
4911 #define DDI_INIT_DISPLAY_DETECTED (1<<0)
4913 /* DDI Buffer Translations */
4914 #define DDI_BUF_TRANS_A 0x64E00
4915 #define DDI_BUF_TRANS_B 0x64E60
4916 #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
4918 /* Sideband Interface (SBI) is programmed indirectly, via
4919 * SBI_ADDR, which contains the register offset; and SBI_DATA,
4920 * which contains the payload */
4921 #define SBI_ADDR 0xC6000
4922 #define SBI_DATA 0xC6004
4923 #define SBI_CTL_STAT 0xC6008
4924 #define SBI_CTL_DEST_ICLK (0x0<<16)
4925 #define SBI_CTL_DEST_MPHY (0x1<<16)
4926 #define SBI_CTL_OP_IORD (0x2<<8)
4927 #define SBI_CTL_OP_IOWR (0x3<<8)
4928 #define SBI_CTL_OP_CRRD (0x6<<8)
4929 #define SBI_CTL_OP_CRWR (0x7<<8)
4930 #define SBI_RESPONSE_FAIL (0x1<<1)
4931 #define SBI_RESPONSE_SUCCESS (0x0<<1)
4932 #define SBI_BUSY (0x1<<0)
4933 #define SBI_READY (0x0<<0)
4936 #define SBI_SSCDIVINTPHASE6 0x0600
4937 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1)
4938 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
4939 #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)
4940 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
4941 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
4942 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
4943 #define SBI_SSCCTL 0x020c
4944 #define SBI_SSCCTL6 0x060C
4945 #define SBI_SSCCTL_PATHALT (1<<3)
4946 #define SBI_SSCCTL_DISABLE (1<<0)
4947 #define SBI_SSCAUXDIV6 0x0610
4948 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
4949 #define SBI_DBUFF0 0x2a00
4950 #define SBI_GEN0 0x1f00
4951 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)
4953 /* LPT PIXCLK_GATE */
4954 #define PIXCLK_GATE 0xC6020
4955 #define PIXCLK_GATE_UNGATE (1<<0)
4956 #define PIXCLK_GATE_GATE (0<<0)
4959 #define SPLL_CTL 0x46020
4960 #define SPLL_PLL_ENABLE (1<<31)
4961 #define SPLL_PLL_SSC (1<<28)
4962 #define SPLL_PLL_NON_SSC (2<<28)
4963 #define SPLL_PLL_FREQ_810MHz (0<<26)
4964 #define SPLL_PLL_FREQ_1350MHz (1<<26)
4967 #define WRPLL_CTL1 0x46040
4968 #define WRPLL_CTL2 0x46060
4969 #define WRPLL_PLL_ENABLE (1<<31)
4970 #define WRPLL_PLL_SELECT_SSC (0x01<<28)
4971 #define WRPLL_PLL_SELECT_NON_SSC (0x02<<28)
4972 #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
4973 /* WRPLL divider programming */
4974 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
4975 #define WRPLL_DIVIDER_POST(x) ((x)<<8)
4976 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
4978 /* Port clock selection */
4979 #define PORT_CLK_SEL_A 0x46100
4980 #define PORT_CLK_SEL_B 0x46104
4981 #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
4982 #define PORT_CLK_SEL_LCPLL_2700 (0<<29)
4983 #define PORT_CLK_SEL_LCPLL_1350 (1<<29)
4984 #define PORT_CLK_SEL_LCPLL_810 (2<<29)
4985 #define PORT_CLK_SEL_SPLL (3<<29)
4986 #define PORT_CLK_SEL_WRPLL1 (4<<29)
4987 #define PORT_CLK_SEL_WRPLL2 (5<<29)
4988 #define PORT_CLK_SEL_NONE (7<<29)
4990 /* Transcoder clock selection */
4991 #define TRANS_CLK_SEL_A 0x46140
4992 #define TRANS_CLK_SEL_B 0x46144
4993 #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
4994 /* For each transcoder, we need to select the corresponding port clock */
4995 #define TRANS_CLK_SEL_DISABLED (0x0<<29)
4996 #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
4998 #define _TRANSA_MSA_MISC 0x60410
4999 #define _TRANSB_MSA_MISC 0x61410
5000 #define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \
5002 #define TRANS_MSA_SYNC_CLK (1<<0)
5003 #define TRANS_MSA_6_BPC (0<<5)
5004 #define TRANS_MSA_8_BPC (1<<5)
5005 #define TRANS_MSA_10_BPC (2<<5)
5006 #define TRANS_MSA_12_BPC (3<<5)
5007 #define TRANS_MSA_16_BPC (4<<5)
5010 #define LCPLL_CTL 0x130040
5011 #define LCPLL_PLL_DISABLE (1<<31)
5012 #define LCPLL_PLL_LOCK (1<<30)
5013 #define LCPLL_CLK_FREQ_MASK (3<<26)
5014 #define LCPLL_CLK_FREQ_450 (0<<26)
5015 #define LCPLL_CD_CLOCK_DISABLE (1<<25)
5016 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
5017 #define LCPLL_POWER_DOWN_ALLOW (1<<22)
5018 #define LCPLL_CD_SOURCE_FCLK (1<<21)
5019 #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
5021 #define D_COMP (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
5022 #define D_COMP_RCOMP_IN_PROGRESS (1<<9)
5023 #define D_COMP_COMP_FORCE (1<<8)
5024 #define D_COMP_COMP_DISABLE (1<<0)
5026 /* Pipe WM_LINETIME - watermark line time */
5027 #define PIPE_WM_LINETIME_A 0x45270
5028 #define PIPE_WM_LINETIME_B 0x45274
5029 #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
5031 #define PIPE_WM_LINETIME_MASK (0x1ff)
5032 #define PIPE_WM_LINETIME_TIME(x) ((x))
5033 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
5034 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
5037 #define SFUSE_STRAP 0xc2014
5038 #define SFUSE_STRAP_DDIB_DETECTED (1<<2)
5039 #define SFUSE_STRAP_DDIC_DETECTED (1<<1)
5040 #define SFUSE_STRAP_DDID_DETECTED (1<<0)
5042 #define WM_MISC 0x45260
5043 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
5045 #define WM_DBG 0x45280
5046 #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
5047 #define WM_DBG_DISALLOW_MAXFIFO (1<<1)
5048 #define WM_DBG_DISALLOW_SPRITE (1<<2)
5051 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010
5052 #define _PIPE_A_CSC_COEFF_BY 0x49014
5053 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018
5054 #define _PIPE_A_CSC_COEFF_BU 0x4901c
5055 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
5056 #define _PIPE_A_CSC_COEFF_BV 0x49024
5057 #define _PIPE_A_CSC_MODE 0x49028
5058 #define CSC_BLACK_SCREEN_OFFSET (1 << 2)
5059 #define CSC_POSITION_BEFORE_GAMMA (1 << 1)
5060 #define CSC_MODE_YUV_TO_RGB (1 << 0)
5061 #define _PIPE_A_CSC_PREOFF_HI 0x49030
5062 #define _PIPE_A_CSC_PREOFF_ME 0x49034
5063 #define _PIPE_A_CSC_PREOFF_LO 0x49038
5064 #define _PIPE_A_CSC_POSTOFF_HI 0x49040
5065 #define _PIPE_A_CSC_POSTOFF_ME 0x49044
5066 #define _PIPE_A_CSC_POSTOFF_LO 0x49048
5068 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110
5069 #define _PIPE_B_CSC_COEFF_BY 0x49114
5070 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118
5071 #define _PIPE_B_CSC_COEFF_BU 0x4911c
5072 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120
5073 #define _PIPE_B_CSC_COEFF_BV 0x49124
5074 #define _PIPE_B_CSC_MODE 0x49128
5075 #define _PIPE_B_CSC_PREOFF_HI 0x49130
5076 #define _PIPE_B_CSC_PREOFF_ME 0x49134
5077 #define _PIPE_B_CSC_PREOFF_LO 0x49138
5078 #define _PIPE_B_CSC_POSTOFF_HI 0x49140
5079 #define _PIPE_B_CSC_POSTOFF_ME 0x49144
5080 #define _PIPE_B_CSC_POSTOFF_LO 0x49148
5082 #define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
5083 #define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
5084 #define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
5085 #define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
5086 #define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
5087 #define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
5088 #define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
5089 #define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
5090 #define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
5091 #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
5092 #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
5093 #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
5094 #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
5096 #endif /* _I915_REG_H_ */
git.samba.org / sfrench / cifs-2.6.git / blob