2 * Copyright (c) 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
30 #include <linux/ascii85.h>
31 #include <linux/nmi.h>
32 #include <linux/pagevec.h>
33 #include <linux/scatterlist.h>
34 #include <linux/utsname.h>
35 #include <linux/zlib.h>
37 #include <drm/drm_print.h>
39 #include "display/intel_atomic.h"
40 #include "display/intel_overlay.h"
42 #include "gem/i915_gem_context.h"
43 #include "gem/i915_gem_lmem.h"
44 #include "gt/intel_gt_pm.h"
47 #include "i915_gpu_error.h"
48 #include "i915_memcpy.h"
49 #include "i915_scatterlist.h"
50 #include "intel_csr.h"
52 #define ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
53 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN)
55 static void __sg_set_buf(struct scatterlist *sg,
56 void *addr, unsigned int len, loff_t it)
58 sg->page_link = (unsigned long)virt_to_page(addr);
59 sg->offset = offset_in_page(addr);
64 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len)
69 if (e->bytes + len + 1 <= e->size)
73 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter);
79 if (e->cur == e->end) {
80 struct scatterlist *sgl;
82 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL);
92 (unsigned long)sgl | SG_CHAIN;
98 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1;
101 e->size = ALIGN(len + 1, SZ_64K);
102 e->buf = kmalloc(e->size, ALLOW_FAIL);
104 e->size = PAGE_ALIGN(len + 1);
105 e->buf = kmalloc(e->size, GFP_KERNEL);
116 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
117 const char *fmt, va_list args)
126 len = vsnprintf(NULL, 0, fmt, ap);
133 if (!__i915_error_grow(e, len))
136 GEM_BUG_ON(e->bytes >= e->size);
137 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args);
145 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str)
153 if (!__i915_error_grow(e, len))
156 GEM_BUG_ON(e->bytes + len > e->size);
157 memcpy(e->buf + e->bytes, str, len);
161 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
162 #define err_puts(e, s) i915_error_puts(e, s)
164 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf)
166 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va);
169 static inline struct drm_printer
170 i915_error_printer(struct drm_i915_error_state_buf *e)
172 struct drm_printer p = {
173 .printfn = __i915_printfn_error,
179 /* single threaded page allocator with a reserved stash for emergencies */
180 static void pool_fini(struct pagevec *pv)
185 static int pool_refill(struct pagevec *pv, gfp_t gfp)
187 while (pagevec_space(pv)) {
200 static int pool_init(struct pagevec *pv, gfp_t gfp)
206 err = pool_refill(pv, gfp);
213 static void *pool_alloc(struct pagevec *pv, gfp_t gfp)
218 if (!p && pagevec_count(pv))
219 p = pv->pages[--pv->nr];
221 return p ? page_address(p) : NULL;
224 static void pool_free(struct pagevec *pv, void *addr)
226 struct page *p = virt_to_page(addr);
228 if (pagevec_space(pv))
234 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
236 struct i915_vma_compress {
238 struct z_stream_s zstream;
242 static bool compress_init(struct i915_vma_compress *c)
244 struct z_stream_s *zstream = &c->zstream;
246 if (pool_init(&c->pool, ALLOW_FAIL))
250 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
252 if (!zstream->workspace) {
258 if (i915_has_memcpy_from_wc())
259 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL);
264 static bool compress_start(struct i915_vma_compress *c)
266 struct z_stream_s *zstream = &c->zstream;
267 void *workspace = zstream->workspace;
269 memset(zstream, 0, sizeof(*zstream));
270 zstream->workspace = workspace;
272 return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK;
275 static void *compress_next_page(struct i915_vma_compress *c,
276 struct i915_vma_coredump *dst)
280 if (dst->page_count >= dst->num_pages)
281 return ERR_PTR(-ENOSPC);
283 page = pool_alloc(&c->pool, ALLOW_FAIL);
285 return ERR_PTR(-ENOMEM);
287 return dst->pages[dst->page_count++] = page;
290 static int compress_page(struct i915_vma_compress *c,
292 struct i915_vma_coredump *dst,
295 struct z_stream_s *zstream = &c->zstream;
297 zstream->next_in = src;
298 if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
299 zstream->next_in = c->tmp;
300 zstream->avail_in = PAGE_SIZE;
303 if (zstream->avail_out == 0) {
304 zstream->next_out = compress_next_page(c, dst);
305 if (IS_ERR(zstream->next_out))
306 return PTR_ERR(zstream->next_out);
308 zstream->avail_out = PAGE_SIZE;
311 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK)
313 } while (zstream->avail_in);
315 /* Fallback to uncompressed if we increase size? */
316 if (0 && zstream->total_out > zstream->total_in)
322 static int compress_flush(struct i915_vma_compress *c,
323 struct i915_vma_coredump *dst)
325 struct z_stream_s *zstream = &c->zstream;
328 switch (zlib_deflate(zstream, Z_FINISH)) {
329 case Z_OK: /* more space requested */
330 zstream->next_out = compress_next_page(c, dst);
331 if (IS_ERR(zstream->next_out))
332 return PTR_ERR(zstream->next_out);
334 zstream->avail_out = PAGE_SIZE;
340 default: /* any error */
346 memset(zstream->next_out, 0, zstream->avail_out);
347 dst->unused = zstream->avail_out;
351 static void compress_finish(struct i915_vma_compress *c)
353 zlib_deflateEnd(&c->zstream);
356 static void compress_fini(struct i915_vma_compress *c)
358 kfree(c->zstream.workspace);
360 pool_free(&c->pool, c->tmp);
364 static void err_compression_marker(struct drm_i915_error_state_buf *m)
371 struct i915_vma_compress {
375 static bool compress_init(struct i915_vma_compress *c)
377 return pool_init(&c->pool, ALLOW_FAIL) == 0;
380 static bool compress_start(struct i915_vma_compress *c)
385 static int compress_page(struct i915_vma_compress *c,
387 struct i915_vma_coredump *dst,
392 ptr = pool_alloc(&c->pool, ALLOW_FAIL);
396 if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE)))
397 memcpy(ptr, src, PAGE_SIZE);
398 dst->pages[dst->page_count++] = ptr;
403 static int compress_flush(struct i915_vma_compress *c,
404 struct i915_vma_coredump *dst)
409 static void compress_finish(struct i915_vma_compress *c)
413 static void compress_fini(struct i915_vma_compress *c)
418 static void err_compression_marker(struct drm_i915_error_state_buf *m)
425 static void error_print_instdone(struct drm_i915_error_state_buf *m,
426 const struct intel_engine_coredump *ee)
428 const struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu;
432 err_printf(m, " INSTDONE: 0x%08x\n",
433 ee->instdone.instdone);
435 if (ee->engine->class != RENDER_CLASS || INTEL_GEN(m->i915) <= 3)
438 err_printf(m, " SC_INSTDONE: 0x%08x\n",
439 ee->instdone.slice_common);
441 if (INTEL_GEN(m->i915) <= 6)
444 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
445 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
447 ee->instdone.sampler[slice][subslice]);
449 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
450 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n",
452 ee->instdone.row[slice][subslice]);
454 if (INTEL_GEN(m->i915) < 12)
457 err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n",
458 ee->instdone.slice_common_extra[0]);
459 err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n",
460 ee->instdone.slice_common_extra[1]);
463 static void error_print_request(struct drm_i915_error_state_buf *m,
465 const struct i915_request_coredump *erq)
470 err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, start %08x, head %08x, tail %08x\n",
471 prefix, erq->pid, erq->context, erq->seqno,
472 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
473 &erq->flags) ? "!" : "",
474 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
475 &erq->flags) ? "+" : "",
476 erq->sched_attr.priority,
477 erq->start, erq->head, erq->tail);
480 static void error_print_context(struct drm_i915_error_state_buf *m,
482 const struct i915_gem_context_coredump *ctx)
484 err_printf(m, "%s%s[%d] prio %d, guilty %d active %d\n",
485 header, ctx->comm, ctx->pid, ctx->sched_attr.priority,
486 ctx->guilty, ctx->active);
489 static struct i915_vma_coredump *
490 __find_vma(struct i915_vma_coredump *vma, const char *name)
493 if (strcmp(vma->name, name) == 0)
501 static struct i915_vma_coredump *
502 find_batch(const struct intel_engine_coredump *ee)
504 return __find_vma(ee->vma, "batch");
507 static void error_print_engine(struct drm_i915_error_state_buf *m,
508 const struct intel_engine_coredump *ee)
510 struct i915_vma_coredump *batch;
513 err_printf(m, "%s command stream:\n", ee->engine->name);
514 err_printf(m, " CCID: 0x%08x\n", ee->ccid);
515 err_printf(m, " START: 0x%08x\n", ee->start);
516 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head);
517 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n",
518 ee->tail, ee->rq_post, ee->rq_tail);
519 err_printf(m, " CTL: 0x%08x\n", ee->ctl);
520 err_printf(m, " MODE: 0x%08x\n", ee->mode);
521 err_printf(m, " HWS: 0x%08x\n", ee->hws);
522 err_printf(m, " ACTHD: 0x%08x %08x\n",
523 (u32)(ee->acthd>>32), (u32)ee->acthd);
524 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir);
525 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr);
526 err_printf(m, " ESR: 0x%08x\n", ee->esr);
528 error_print_instdone(m, ee);
530 batch = find_batch(ee);
532 u64 start = batch->gtt_offset;
533 u64 end = start + batch->gtt_size;
535 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n",
536 upper_32_bits(start), lower_32_bits(start),
537 upper_32_bits(end), lower_32_bits(end));
539 if (INTEL_GEN(m->i915) >= 4) {
540 err_printf(m, " BBADDR: 0x%08x_%08x\n",
541 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
542 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate);
543 err_printf(m, " INSTPS: 0x%08x\n", ee->instps);
545 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm);
546 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
547 lower_32_bits(ee->faddr));
548 if (INTEL_GEN(m->i915) >= 6) {
549 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi);
550 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg);
552 if (HAS_PPGTT(m->i915)) {
553 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
555 if (INTEL_GEN(m->i915) >= 8) {
557 for (i = 0; i < 4; i++)
558 err_printf(m, " PDP%d: 0x%016llx\n",
559 i, ee->vm_info.pdp[i]);
561 err_printf(m, " PP_DIR_BASE: 0x%08x\n",
562 ee->vm_info.pp_dir_base);
565 err_printf(m, " engine reset count: %u\n", ee->reset_count);
567 for (n = 0; n < ee->num_ports; n++) {
568 err_printf(m, " ELSP[%d]:", n);
569 error_print_request(m, " ", &ee->execlist[n]);
572 error_print_context(m, " Active context: ", &ee->context);
575 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
580 i915_error_vprintf(e, f, args);
584 static void print_error_vma(struct drm_i915_error_state_buf *m,
585 const struct intel_engine_cs *engine,
586 const struct i915_vma_coredump *vma)
588 char out[ASCII85_BUFSZ];
594 err_printf(m, "%s --- %s = 0x%08x %08x\n",
595 engine ? engine->name : "global", vma->name,
596 upper_32_bits(vma->gtt_offset),
597 lower_32_bits(vma->gtt_offset));
599 if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K)
600 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes);
602 err_compression_marker(m);
603 for (page = 0; page < vma->page_count; page++) {
607 if (page == vma->page_count - 1)
609 len = ascii85_encode_len(len);
611 for (i = 0; i < len; i++)
612 err_puts(m, ascii85_encode(vma->pages[page][i], out));
617 static void err_print_capabilities(struct drm_i915_error_state_buf *m,
618 const struct intel_device_info *info,
619 const struct intel_runtime_info *runtime,
620 const struct intel_driver_caps *caps)
622 struct drm_printer p = i915_error_printer(m);
624 intel_device_info_print_static(info, &p);
625 intel_device_info_print_runtime(runtime, &p);
626 intel_device_info_print_topology(&runtime->sseu, &p);
627 intel_driver_caps_print(caps, &p);
630 static void err_print_params(struct drm_i915_error_state_buf *m,
631 const struct i915_params *params)
633 struct drm_printer p = i915_error_printer(m);
635 i915_params_dump(params, &p);
638 static void err_print_pciid(struct drm_i915_error_state_buf *m,
639 struct drm_i915_private *i915)
641 struct pci_dev *pdev = i915->drm.pdev;
643 err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
644 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
645 err_printf(m, "PCI Subsystem: %04x:%04x\n",
646 pdev->subsystem_vendor,
647 pdev->subsystem_device);
650 static void err_print_uc(struct drm_i915_error_state_buf *m,
651 const struct intel_uc_coredump *error_uc)
653 struct drm_printer p = i915_error_printer(m);
655 intel_uc_fw_dump(&error_uc->guc_fw, &p);
656 intel_uc_fw_dump(&error_uc->huc_fw, &p);
657 print_error_vma(m, NULL, error_uc->guc_log);
660 static void err_free_sgl(struct scatterlist *sgl)
663 struct scatterlist *sg;
665 for (sg = sgl; !sg_is_chain(sg); sg++) {
671 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg);
672 free_page((unsigned long)sgl);
677 static void err_print_gt(struct drm_i915_error_state_buf *m,
678 struct intel_gt_coredump *gt)
680 const struct intel_engine_coredump *ee;
683 err_printf(m, "GT awake: %s\n", yesno(gt->awake));
684 err_printf(m, "EIR: 0x%08x\n", gt->eir);
685 err_printf(m, "IER: 0x%08x\n", gt->ier);
686 for (i = 0; i < gt->ngtier; i++)
687 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]);
688 err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er);
689 err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake);
690 err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr);
692 for (i = 0; i < gt->nfence; i++)
693 err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]);
695 if (IS_GEN_RANGE(m->i915, 6, 11)) {
696 err_printf(m, "ERROR: 0x%08x\n", gt->error);
697 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg);
700 if (INTEL_GEN(m->i915) >= 8)
701 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
702 gt->fault_data1, gt->fault_data0);
704 if (IS_GEN(m->i915, 7))
705 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int);
707 if (IS_GEN_RANGE(m->i915, 8, 11))
708 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache);
710 if (IS_GEN(m->i915, 12))
711 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err);
713 if (INTEL_GEN(m->i915) >= 12) {
716 for (i = 0; i < GEN12_SFC_DONE_MAX; i++)
717 err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i,
720 err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done);
723 for (ee = gt->engine; ee; ee = ee->next) {
724 const struct i915_vma_coredump *vma;
726 error_print_engine(m, ee);
727 for (vma = ee->vma; vma; vma = vma->next)
728 print_error_vma(m, ee->engine, vma);
732 err_print_uc(m, gt->uc);
735 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
736 struct i915_gpu_coredump *error)
738 const struct intel_engine_coredump *ee;
739 struct timespec64 ts;
741 if (*error->error_msg)
742 err_printf(m, "%s\n", error->error_msg);
743 err_printf(m, "Kernel: %s %s\n",
744 init_utsname()->release,
745 init_utsname()->machine);
746 err_printf(m, "Driver: %s\n", DRIVER_DATE);
747 ts = ktime_to_timespec64(error->time);
748 err_printf(m, "Time: %lld s %ld us\n",
749 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
750 ts = ktime_to_timespec64(error->boottime);
751 err_printf(m, "Boottime: %lld s %ld us\n",
752 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
753 ts = ktime_to_timespec64(error->uptime);
754 err_printf(m, "Uptime: %lld s %ld us\n",
755 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
756 err_printf(m, "Capture: %lu jiffies; %d ms ago\n",
757 error->capture, jiffies_to_msecs(jiffies - error->capture));
759 for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next)
760 err_printf(m, "Active process (on ring %s): %s [%d]\n",
765 err_printf(m, "Reset count: %u\n", error->reset_count);
766 err_printf(m, "Suspend count: %u\n", error->suspend_count);
767 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
768 err_printf(m, "Subplatform: 0x%x\n",
769 intel_subplatform(&error->runtime_info,
770 error->device_info.platform));
771 err_print_pciid(m, m->i915);
773 err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
775 if (HAS_CSR(m->i915)) {
776 struct intel_csr *csr = &m->i915->csr;
778 err_printf(m, "DMC loaded: %s\n",
779 yesno(csr->dmc_payload != NULL));
780 err_printf(m, "DMC fw version: %d.%d\n",
781 CSR_VERSION_MAJOR(csr->version),
782 CSR_VERSION_MINOR(csr->version));
785 err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
786 err_printf(m, "PM suspended: %s\n", yesno(error->suspended));
789 err_print_gt(m, error->gt);
792 intel_overlay_print_error_state(m, error->overlay);
795 intel_display_print_error_state(m, error->display);
797 err_print_capabilities(m, &error->device_info, &error->runtime_info,
798 &error->driver_caps);
799 err_print_params(m, &error->params);
802 static int err_print_to_sgl(struct i915_gpu_coredump *error)
804 struct drm_i915_error_state_buf m;
807 return PTR_ERR(error);
809 if (READ_ONCE(error->sgl))
812 memset(&m, 0, sizeof(m));
813 m.i915 = error->i915;
815 __err_print_to_sgl(&m, error);
818 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter);
823 GEM_BUG_ON(m.end < m.cur);
824 sg_mark_end(m.cur - 1);
826 GEM_BUG_ON(m.sgl && !m.cur);
833 if (cmpxchg(&error->sgl, NULL, m.sgl))
839 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error,
840 char *buf, loff_t off, size_t rem)
842 struct scatterlist *sg;
850 err = err_print_to_sgl(error);
854 sg = READ_ONCE(error->fit);
855 if (!sg || off < sg->dma_address)
860 pos = sg->dma_address;
865 if (sg_is_chain(sg)) {
866 sg = sg_chain_ptr(sg);
867 GEM_BUG_ON(sg_is_chain(sg));
871 if (pos + len <= off) {
878 GEM_BUG_ON(off - pos > len);
885 GEM_BUG_ON(!len || len > sg->length);
887 memcpy(buf, page_address(sg_page(sg)) + start, len);
895 WRITE_ONCE(error->fit, sg);
898 } while (!sg_is_last(sg++));
903 static void i915_vma_coredump_free(struct i915_vma_coredump *vma)
906 struct i915_vma_coredump *next = vma->next;
909 for (page = 0; page < vma->page_count; page++)
910 free_page((unsigned long)vma->pages[page]);
917 static void cleanup_params(struct i915_gpu_coredump *error)
919 i915_params_free(&error->params);
922 static void cleanup_uc(struct intel_uc_coredump *uc)
924 kfree(uc->guc_fw.path);
925 kfree(uc->huc_fw.path);
926 i915_vma_coredump_free(uc->guc_log);
931 static void cleanup_gt(struct intel_gt_coredump *gt)
934 struct intel_engine_coredump *ee = gt->engine;
936 gt->engine = ee->next;
938 i915_vma_coredump_free(ee->vma);
948 void __i915_gpu_coredump_free(struct kref *error_ref)
950 struct i915_gpu_coredump *error =
951 container_of(error_ref, typeof(*error), ref);
954 struct intel_gt_coredump *gt = error->gt;
956 error->gt = gt->next;
960 kfree(error->overlay);
961 kfree(error->display);
963 cleanup_params(error);
965 err_free_sgl(error->sgl);
969 static struct i915_vma_coredump *
970 i915_vma_coredump_create(const struct intel_gt *gt,
971 const struct i915_vma *vma,
973 struct i915_vma_compress *compress)
975 struct i915_ggtt *ggtt = gt->ggtt;
976 const u64 slot = ggtt->error_capture.start;
977 struct i915_vma_coredump *dst;
978 unsigned long num_pages;
979 struct sgt_iter iter;
984 if (!vma || !vma->pages || !compress)
987 num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
988 num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
989 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), ALLOW_FAIL);
993 if (!compress_start(compress)) {
998 strcpy(dst->name, name);
1001 dst->gtt_offset = vma->node.start;
1002 dst->gtt_size = vma->node.size;
1003 dst->gtt_page_sizes = vma->page_sizes.gtt;
1004 dst->num_pages = num_pages;
1005 dst->page_count = 0;
1009 if (drm_mm_node_allocated(&ggtt->error_capture)) {
1013 for_each_sgt_daddr(dma, iter, vma->pages) {
1014 ggtt->vm.insert_page(&ggtt->vm, dma, slot,
1015 I915_CACHE_NONE, 0);
1018 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
1019 ret = compress_page(compress,
1020 (void __force *)s, dst,
1022 io_mapping_unmap(s);
1026 } else if (i915_gem_object_is_lmem(vma->obj)) {
1027 struct intel_memory_region *mem = vma->obj->mm.region;
1030 for_each_sgt_daddr(dma, iter, vma->pages) {
1033 s = io_mapping_map_wc(&mem->iomap, dma, PAGE_SIZE);
1034 ret = compress_page(compress,
1035 (void __force *)s, dst,
1037 io_mapping_unmap(s);
1044 for_each_sgt_page(page, iter, vma->pages) {
1047 drm_clflush_pages(&page, 1);
1050 ret = compress_page(compress, s, dst, false);
1053 drm_clflush_pages(&page, 1);
1060 if (ret || compress_flush(compress, dst)) {
1061 while (dst->page_count--)
1062 pool_free(&compress->pool, dst->pages[dst->page_count]);
1066 compress_finish(compress);
1071 static void gt_record_fences(struct intel_gt_coredump *gt)
1073 struct i915_ggtt *ggtt = gt->_gt->ggtt;
1074 struct intel_uncore *uncore = gt->_gt->uncore;
1077 if (INTEL_GEN(uncore->i915) >= 6) {
1078 for (i = 0; i < ggtt->num_fences; i++)
1080 intel_uncore_read64(uncore,
1081 FENCE_REG_GEN6_LO(i));
1082 } else if (INTEL_GEN(uncore->i915) >= 4) {
1083 for (i = 0; i < ggtt->num_fences; i++)
1085 intel_uncore_read64(uncore,
1086 FENCE_REG_965_LO(i));
1088 for (i = 0; i < ggtt->num_fences; i++)
1090 intel_uncore_read(uncore, FENCE_REG(i));
1095 static void engine_record_registers(struct intel_engine_coredump *ee)
1097 const struct intel_engine_cs *engine = ee->engine;
1098 struct drm_i915_private *i915 = engine->i915;
1100 if (INTEL_GEN(i915) >= 6) {
1101 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);
1103 if (INTEL_GEN(i915) >= 12)
1104 ee->fault_reg = intel_uncore_read(engine->uncore,
1105 GEN12_RING_FAULT_REG);
1106 else if (INTEL_GEN(i915) >= 8)
1107 ee->fault_reg = intel_uncore_read(engine->uncore,
1108 GEN8_RING_FAULT_REG);
1110 ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
1113 if (INTEL_GEN(i915) >= 4) {
1114 ee->esr = ENGINE_READ(engine, RING_ESR);
1115 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD);
1116 ee->ipeir = ENGINE_READ(engine, RING_IPEIR);
1117 ee->ipehr = ENGINE_READ(engine, RING_IPEHR);
1118 ee->instps = ENGINE_READ(engine, RING_INSTPS);
1119 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR);
1120 ee->ccid = ENGINE_READ(engine, CCID);
1121 if (INTEL_GEN(i915) >= 8) {
1122 ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32;
1123 ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32;
1125 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE);
1127 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX);
1128 ee->ipeir = ENGINE_READ(engine, IPEIR);
1129 ee->ipehr = ENGINE_READ(engine, IPEHR);
1132 intel_engine_get_instdone(engine, &ee->instdone);
1134 ee->instpm = ENGINE_READ(engine, RING_INSTPM);
1135 ee->acthd = intel_engine_get_active_head(engine);
1136 ee->start = ENGINE_READ(engine, RING_START);
1137 ee->head = ENGINE_READ(engine, RING_HEAD);
1138 ee->tail = ENGINE_READ(engine, RING_TAIL);
1139 ee->ctl = ENGINE_READ(engine, RING_CTL);
1140 if (INTEL_GEN(i915) > 2)
1141 ee->mode = ENGINE_READ(engine, RING_MI_MODE);
1143 if (!HWS_NEEDS_PHYSICAL(i915)) {
1146 if (IS_GEN(i915, 7)) {
1147 switch (engine->id) {
1149 MISSING_CASE(engine->id);
1152 mmio = RENDER_HWS_PGA_GEN7;
1155 mmio = BLT_HWS_PGA_GEN7;
1158 mmio = BSD_HWS_PGA_GEN7;
1161 mmio = VEBOX_HWS_PGA_GEN7;
1164 } else if (IS_GEN(engine->i915, 6)) {
1165 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1167 /* XXX: gen8 returns to sanity */
1168 mmio = RING_HWS_PGA(engine->mmio_base);
1171 ee->hws = intel_uncore_read(engine->uncore, mmio);
1174 ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine);
1176 if (HAS_PPGTT(i915)) {
1179 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);
1181 if (IS_GEN(i915, 6)) {
1182 ee->vm_info.pp_dir_base =
1183 ENGINE_READ(engine, RING_PP_DIR_BASE_READ);
1184 } else if (IS_GEN(i915, 7)) {
1185 ee->vm_info.pp_dir_base =
1186 ENGINE_READ(engine, RING_PP_DIR_BASE);
1187 } else if (INTEL_GEN(i915) >= 8) {
1188 u32 base = engine->mmio_base;
1190 for (i = 0; i < 4; i++) {
1191 ee->vm_info.pdp[i] =
1192 intel_uncore_read(engine->uncore,
1193 GEN8_RING_PDP_UDW(base, i));
1194 ee->vm_info.pdp[i] <<= 32;
1195 ee->vm_info.pdp[i] |=
1196 intel_uncore_read(engine->uncore,
1197 GEN8_RING_PDP_LDW(base, i));
1203 static void record_request(const struct i915_request *request,
1204 struct i915_request_coredump *erq)
1206 const struct i915_gem_context *ctx;
1208 erq->flags = request->fence.flags;
1209 erq->context = request->fence.context;
1210 erq->seqno = request->fence.seqno;
1211 erq->sched_attr = request->sched.attr;
1212 erq->start = i915_ggtt_offset(request->ring->vma);
1213 erq->head = request->head;
1214 erq->tail = request->tail;
1218 ctx = rcu_dereference(request->context->gem_context);
1220 erq->pid = pid_nr(ctx->pid);
1224 static void engine_record_execlists(struct intel_engine_coredump *ee)
1226 const struct intel_engine_execlists * const el = &ee->engine->execlists;
1227 struct i915_request * const *port = el->active;
1231 record_request(*port++, &ee->execlist[n++]);
1236 static bool record_context(struct i915_gem_context_coredump *e,
1237 const struct i915_request *rq)
1239 struct i915_gem_context *ctx;
1240 struct task_struct *task;
1244 ctx = rcu_dereference(rq->context->gem_context);
1245 if (ctx && !kref_get_unless_zero(&ctx->ref))
1252 task = pid_task(ctx->pid, PIDTYPE_PID);
1254 strcpy(e->comm, task->comm);
1259 e->sched_attr = ctx->sched;
1260 e->guilty = atomic_read(&ctx->guilty_count);
1261 e->active = atomic_read(&ctx->active_count);
1263 simulated = i915_gem_context_no_error_capture(ctx);
1265 i915_gem_context_put(ctx);
1269 struct intel_engine_capture_vma {
1270 struct intel_engine_capture_vma *next;
1271 struct i915_vma *vma;
1275 static struct intel_engine_capture_vma *
1276 capture_vma(struct intel_engine_capture_vma *next,
1277 struct i915_vma *vma,
1281 struct intel_engine_capture_vma *c;
1286 c = kmalloc(sizeof(*c), gfp);
1290 if (!i915_active_acquire_if_busy(&vma->active)) {
1295 strcpy(c->name, name);
1296 c->vma = i915_vma_get(vma);
1302 static struct intel_engine_capture_vma *
1303 capture_user(struct intel_engine_capture_vma *capture,
1304 const struct i915_request *rq,
1307 struct i915_capture_list *c;
1309 for (c = rq->capture_list; c; c = c->next)
1310 capture = capture_vma(capture, c->vma, "user", gfp);
1315 static struct i915_vma_coredump *
1316 capture_object(const struct intel_gt *gt,
1317 struct drm_i915_gem_object *obj,
1319 struct i915_vma_compress *compress)
1321 if (obj && i915_gem_object_has_pages(obj)) {
1322 struct i915_vma fake = {
1323 .node = { .start = U64_MAX, .size = obj->base.size },
1324 .size = obj->base.size,
1325 .pages = obj->mm.pages,
1329 return i915_vma_coredump_create(gt, &fake, name, compress);
1335 static void add_vma(struct intel_engine_coredump *ee,
1336 struct i915_vma_coredump *vma)
1339 vma->next = ee->vma;
1344 struct intel_engine_coredump *
1345 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp)
1347 struct intel_engine_coredump *ee;
1349 ee = kzalloc(sizeof(*ee), gfp);
1353 ee->engine = engine;
1355 engine_record_registers(ee);
1356 engine_record_execlists(ee);
1361 struct intel_engine_capture_vma *
1362 intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
1363 struct i915_request *rq,
1366 struct intel_engine_capture_vma *vma = NULL;
1368 ee->simulated |= record_context(&ee->context, rq);
1373 * We need to copy these to an anonymous buffer
1374 * as the simplest method to avoid being overwritten
1377 vma = capture_vma(vma, rq->batch, "batch", gfp);
1378 vma = capture_user(vma, rq, gfp);
1379 vma = capture_vma(vma, rq->ring->vma, "ring", gfp);
1380 vma = capture_vma(vma, rq->context->state, "HW context", gfp);
1382 ee->rq_head = rq->head;
1383 ee->rq_post = rq->postfix;
1384 ee->rq_tail = rq->tail;
1390 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
1391 struct intel_engine_capture_vma *capture,
1392 struct i915_vma_compress *compress)
1394 const struct intel_engine_cs *engine = ee->engine;
1397 struct intel_engine_capture_vma *this = capture;
1398 struct i915_vma *vma = this->vma;
1401 i915_vma_coredump_create(engine->gt,
1405 i915_active_release(&vma->active);
1408 capture = this->next;
1413 i915_vma_coredump_create(engine->gt,
1414 engine->status_page.vma,
1419 i915_vma_coredump_create(engine->gt,
1425 capture_object(engine->gt,
1426 engine->default_state,
1431 static struct intel_engine_coredump *
1432 capture_engine(struct intel_engine_cs *engine,
1433 struct i915_vma_compress *compress)
1435 struct intel_engine_capture_vma *capture = NULL;
1436 struct intel_engine_coredump *ee;
1437 struct i915_request *rq;
1438 unsigned long flags;
1440 ee = intel_engine_coredump_alloc(engine, GFP_KERNEL);
1444 spin_lock_irqsave(&engine->active.lock, flags);
1445 rq = intel_engine_find_active_request(engine);
1447 capture = intel_engine_coredump_add_request(ee, rq,
1449 spin_unlock_irqrestore(&engine->active.lock, flags);
1455 intel_engine_coredump_add_vma(ee, capture, compress);
1461 gt_record_engines(struct intel_gt_coredump *gt,
1462 struct i915_vma_compress *compress)
1464 struct intel_engine_cs *engine;
1465 enum intel_engine_id id;
1467 for_each_engine(engine, gt->_gt, id) {
1468 struct intel_engine_coredump *ee;
1470 /* Refill our page pool before entering atomic section */
1471 pool_refill(&compress->pool, ALLOW_FAIL);
1473 ee = capture_engine(engine, compress);
1477 gt->simulated |= ee->simulated;
1478 if (ee->simulated) {
1483 ee->next = gt->engine;
1488 static struct intel_uc_coredump *
1489 gt_record_uc(struct intel_gt_coredump *gt,
1490 struct i915_vma_compress *compress)
1492 const struct intel_uc *uc = >->_gt->uc;
1493 struct intel_uc_coredump *error_uc;
1495 error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL);
1499 memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw));
1500 memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw));
1502 /* Non-default firmware paths will be specified by the modparam.
1503 * As modparams are generally accesible from the userspace make
1504 * explicit copies of the firmware paths.
1506 error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL);
1507 error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL);
1509 i915_vma_coredump_create(gt->_gt,
1510 uc->guc.log.vma, "GuC log buffer",
1516 static void gt_capture_prepare(struct intel_gt_coredump *gt)
1518 struct i915_ggtt *ggtt = gt->_gt->ggtt;
1520 mutex_lock(&ggtt->error_mutex);
1523 static void gt_capture_finish(struct intel_gt_coredump *gt)
1525 struct i915_ggtt *ggtt = gt->_gt->ggtt;
1527 if (drm_mm_node_allocated(&ggtt->error_capture))
1528 ggtt->vm.clear_range(&ggtt->vm,
1529 ggtt->error_capture.start,
1532 mutex_unlock(&ggtt->error_mutex);
1535 /* Capture all registers which don't fit into another category. */
1536 static void gt_record_regs(struct intel_gt_coredump *gt)
1538 struct intel_uncore *uncore = gt->_gt->uncore;
1539 struct drm_i915_private *i915 = uncore->i915;
1543 * General organization
1544 * 1. Registers specific to a single generation
1545 * 2. Registers which belong to multiple generations
1546 * 3. Feature specific registers.
1547 * 4. Everything else
1548 * Please try to follow the order.
1551 /* 1: Registers specific to a single generation */
1552 if (IS_VALLEYVIEW(i915)) {
1553 gt->gtier[0] = intel_uncore_read(uncore, GTIER);
1554 gt->ier = intel_uncore_read(uncore, VLV_IER);
1555 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV);
1558 if (IS_GEN(i915, 7))
1559 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);
1561 if (INTEL_GEN(i915) >= 12) {
1562 gt->fault_data0 = intel_uncore_read(uncore,
1563 GEN12_FAULT_TLB_DATA0);
1564 gt->fault_data1 = intel_uncore_read(uncore,
1565 GEN12_FAULT_TLB_DATA1);
1566 } else if (INTEL_GEN(i915) >= 8) {
1567 gt->fault_data0 = intel_uncore_read(uncore,
1568 GEN8_FAULT_TLB_DATA0);
1569 gt->fault_data1 = intel_uncore_read(uncore,
1570 GEN8_FAULT_TLB_DATA1);
1573 if (IS_GEN(i915, 6)) {
1574 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE);
1575 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL);
1576 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE);
1579 /* 2: Registers which belong to multiple generations */
1580 if (INTEL_GEN(i915) >= 7)
1581 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
1583 if (INTEL_GEN(i915) >= 6) {
1584 gt->derrmr = intel_uncore_read(uncore, DERRMR);
1585 if (INTEL_GEN(i915) < 12) {
1586 gt->error = intel_uncore_read(uncore, ERROR_GEN6);
1587 gt->done_reg = intel_uncore_read(uncore, DONE_REG);
1591 /* 3: Feature specific registers */
1592 if (IS_GEN_RANGE(i915, 6, 7)) {
1593 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
1594 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS);
1597 if (IS_GEN_RANGE(i915, 8, 11))
1598 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN);
1600 if (IS_GEN(i915, 12))
1601 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG);
1603 if (INTEL_GEN(i915) >= 12) {
1604 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) {
1606 intel_uncore_read(uncore, GEN12_SFC_DONE(i));
1609 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE);
1612 /* 4: Everything else */
1613 if (INTEL_GEN(i915) >= 11) {
1614 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
1616 intel_uncore_read(uncore,
1617 GEN11_RENDER_COPY_INTR_ENABLE);
1619 intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE);
1621 intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE);
1623 intel_uncore_read(uncore,
1624 GEN11_GPM_WGBOXPERF_INTR_ENABLE);
1626 intel_uncore_read(uncore,
1627 GEN11_CRYPTO_RSVD_INTR_ENABLE);
1629 intel_uncore_read(uncore,
1630 GEN11_GUNIT_CSME_INTR_ENABLE);
1632 } else if (INTEL_GEN(i915) >= 8) {
1633 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
1634 for (i = 0; i < 4; i++)
1636 intel_uncore_read(uncore, GEN8_GT_IER(i));
1638 } else if (HAS_PCH_SPLIT(i915)) {
1639 gt->ier = intel_uncore_read(uncore, DEIER);
1640 gt->gtier[0] = intel_uncore_read(uncore, GTIER);
1642 } else if (IS_GEN(i915, 2)) {
1643 gt->ier = intel_uncore_read16(uncore, GEN2_IER);
1644 } else if (!IS_VALLEYVIEW(i915)) {
1645 gt->ier = intel_uncore_read(uncore, GEN2_IER);
1647 gt->eir = intel_uncore_read(uncore, EIR);
1648 gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER);
1652 * Generate a semi-unique error code. The code is not meant to have meaning, The
1653 * code's only purpose is to try to prevent false duplicated bug reports by
1654 * grossly estimating a GPU error state.
1656 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
1657 * the hang if we could strip the GTT offset information from it.
1659 * It's only a small step better than a random number in its current form.
1661 static u32 generate_ecode(const struct intel_engine_coredump *ee)
1664 * IPEHR would be an ideal way to detect errors, as it's the gross
1665 * measure of "the command that hung." However, has some very common
1666 * synchronization commands which almost always appear in the case
1667 * strictly a client bug. Use instdone to differentiate those some.
1669 return ee ? ee->ipehr ^ ee->instdone.instdone : 0;
1672 static const char *error_msg(struct i915_gpu_coredump *error)
1674 struct intel_engine_coredump *first = NULL;
1675 struct intel_gt_coredump *gt;
1676 intel_engine_mask_t engines;
1680 for (gt = error->gt; gt; gt = gt->next) {
1681 struct intel_engine_coredump *cs;
1683 if (gt->engine && !first)
1686 for (cs = gt->engine; cs; cs = cs->next)
1687 engines |= cs->engine->mask;
1690 len = scnprintf(error->error_msg, sizeof(error->error_msg),
1691 "GPU HANG: ecode %d:%x:%08x",
1692 INTEL_GEN(error->i915), engines,
1693 generate_ecode(first));
1694 if (first && first->context.pid) {
1695 /* Just show the first executing process, more is confusing */
1696 len += scnprintf(error->error_msg + len,
1697 sizeof(error->error_msg) - len,
1699 first->context.comm, first->context.pid);
1702 return error->error_msg;
1705 static void capture_gen(struct i915_gpu_coredump *error)
1707 struct drm_i915_private *i915 = error->i915;
1709 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count);
1710 error->suspended = i915->runtime_pm.suspended;
1713 #ifdef CONFIG_INTEL_IOMMU
1714 error->iommu = intel_iommu_gfx_mapped;
1716 error->reset_count = i915_reset_count(&i915->gpu_error);
1717 error->suspend_count = i915->suspend_count;
1719 i915_params_copy(&error->params, &i915_modparams);
1720 memcpy(&error->device_info,
1722 sizeof(error->device_info));
1723 memcpy(&error->runtime_info,
1725 sizeof(error->runtime_info));
1726 error->driver_caps = i915->caps;
1729 struct i915_gpu_coredump *
1730 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp)
1732 struct i915_gpu_coredump *error;
1734 if (!i915_modparams.error_capture)
1737 error = kzalloc(sizeof(*error), gfp);
1741 kref_init(&error->ref);
1744 error->time = ktime_get_real();
1745 error->boottime = ktime_get_boottime();
1746 error->uptime = ktime_sub(ktime_get(), i915->gt.last_init_time);
1747 error->capture = jiffies;
1754 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
1756 struct intel_gt_coredump *
1757 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp)
1759 struct intel_gt_coredump *gc;
1761 gc = kzalloc(sizeof(*gc), gfp);
1766 gc->awake = intel_gt_pm_is_awake(gt);
1769 gt_record_fences(gc);
1774 struct i915_vma_compress *
1775 i915_vma_capture_prepare(struct intel_gt_coredump *gt)
1777 struct i915_vma_compress *compress;
1779 compress = kmalloc(sizeof(*compress), ALLOW_FAIL);
1783 if (!compress_init(compress)) {
1788 gt_capture_prepare(gt);
1793 void i915_vma_capture_finish(struct intel_gt_coredump *gt,
1794 struct i915_vma_compress *compress)
1799 gt_capture_finish(gt);
1801 compress_fini(compress);
1805 struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915)
1807 struct i915_gpu_coredump *error;
1809 /* Check if GPU capture has been disabled */
1810 error = READ_ONCE(i915->gpu_error.first_error);
1814 error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL);
1816 return ERR_PTR(-ENOMEM);
1818 error->gt = intel_gt_coredump_alloc(&i915->gt, ALLOW_FAIL);
1820 struct i915_vma_compress *compress;
1822 compress = i915_vma_capture_prepare(error->gt);
1826 return ERR_PTR(-ENOMEM);
1829 gt_record_engines(error->gt, compress);
1831 if (INTEL_INFO(i915)->has_gt_uc)
1832 error->gt->uc = gt_record_uc(error->gt, compress);
1834 i915_vma_capture_finish(error->gt, compress);
1836 error->simulated |= error->gt->simulated;
1839 error->overlay = intel_overlay_capture_error_state(i915);
1840 error->display = intel_display_capture_error_state(i915);
1845 void i915_error_state_store(struct i915_gpu_coredump *error)
1847 struct drm_i915_private *i915;
1850 if (IS_ERR_OR_NULL(error))
1854 dev_info(i915->drm.dev, "%s\n", error_msg(error));
1856 if (error->simulated ||
1857 cmpxchg(&i915->gpu_error.first_error, NULL, error))
1860 i915_gpu_coredump_get(error);
1862 if (!xchg(&warned, true) &&
1863 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
1864 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1865 pr_info("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1866 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1867 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n");
1868 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1869 i915->drm.primary->index);
1874 * i915_capture_error_state - capture an error record for later analysis
1875 * @i915: i915 device
1877 * Should be called when an error is detected (either a hang or an error
1878 * interrupt) to capture error state from the time of the error. Fills
1879 * out a structure which becomes available in debugfs for user level tools
1882 void i915_capture_error_state(struct drm_i915_private *i915)
1884 struct i915_gpu_coredump *error;
1886 error = i915_gpu_coredump(i915);
1887 if (IS_ERR(error)) {
1888 cmpxchg(&i915->gpu_error.first_error, NULL, error);
1892 i915_error_state_store(error);
1893 i915_gpu_coredump_put(error);
1896 struct i915_gpu_coredump *
1897 i915_first_error_state(struct drm_i915_private *i915)
1899 struct i915_gpu_coredump *error;
1901 spin_lock_irq(&i915->gpu_error.lock);
1902 error = i915->gpu_error.first_error;
1903 if (!IS_ERR_OR_NULL(error))
1904 i915_gpu_coredump_get(error);
1905 spin_unlock_irq(&i915->gpu_error.lock);
1910 void i915_reset_error_state(struct drm_i915_private *i915)
1912 struct i915_gpu_coredump *error;
1914 spin_lock_irq(&i915->gpu_error.lock);
1915 error = i915->gpu_error.first_error;
1916 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */
1917 i915->gpu_error.first_error = NULL;
1918 spin_unlock_irq(&i915->gpu_error.lock);
1920 if (!IS_ERR_OR_NULL(error))
1921 i915_gpu_coredump_put(error);
1924 void i915_disable_error_state(struct drm_i915_private *i915, int err)
1926 spin_lock_irq(&i915->gpu_error.lock);
1927 if (!i915->gpu_error.first_error)
1928 i915->gpu_error.first_error = ERR_PTR(err);
1929 spin_unlock_irq(&i915->gpu_error.lock);