drivers/gpu/drm/i915/i915_gpu_error.c

   1 /*
   2  * Copyright (c) 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *    Mika Kuoppala <mika.kuoppala@intel.com>
  27  *
  28  */
  29
  30 #include <generated/utsrelease.h>
  31 #include <linux/stop_machine.h>
  32 #include <linux/zlib.h>
  33 #include "i915_drv.h"
  34
  35 static const char *engine_str(int engine)
  36 {
  37         switch (engine) {
  38         case RCS: return "render";
  39         case VCS: return "bsd";
  40         case BCS: return "blt";
  41         case VECS: return "vebox";
  42         case VCS2: return "bsd2";
  43         default: return "";
  44         }
  45 }
  46
  47 static const char *tiling_flag(int tiling)
  48 {
  49         switch (tiling) {
  50         default:
  51         case I915_TILING_NONE: return "";
  52         case I915_TILING_X: return " X";
  53         case I915_TILING_Y: return " Y";
  54         }
  55 }
  56
  57 static const char *dirty_flag(int dirty)
  58 {
  59         return dirty ? " dirty" : "";
  60 }
  61
  62 static const char *purgeable_flag(int purgeable)
  63 {
  64         return purgeable ? " purgeable" : "";
  65 }
  66
  67 static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
  68 {
  69
  70         if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
  71                 e->err = -ENOSPC;
  72                 return false;
  73         }
  74
  75         if (e->bytes == e->size - 1 || e->err)
  76                 return false;
  77
  78         return true;
  79 }
  80
  81 static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
  82                               unsigned len)
  83 {
  84         if (e->pos + len <= e->start) {
  85                 e->pos += len;
  86                 return false;
  87         }
  88
  89         /* First vsnprintf needs to fit in its entirety for memmove */
  90         if (len >= e->size) {
  91                 e->err = -EIO;
  92                 return false;
  93         }
  94
  95         return true;
  96 }
  97
  98 static void __i915_error_advance(struct drm_i915_error_state_buf *e,
  99                                  unsigned len)
 100 {
 101         /* If this is first printf in this window, adjust it so that
 102          * start position matches start of the buffer
 103          */
 104
 105         if (e->pos < e->start) {
 106                 const size_t off = e->start - e->pos;
 107
 108                 /* Should not happen but be paranoid */
 109                 if (off > len || e->bytes) {
 110                         e->err = -EIO;
 111                         return;
 112                 }
 113
 114                 memmove(e->buf, e->buf + off, len - off);
 115                 e->bytes = len - off;
 116                 e->pos = e->start;
 117                 return;
 118         }
 119
 120         e->bytes += len;
 121         e->pos += len;
 122 }
 123
 124 __printf(2, 0)
 125 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
 126                                const char *f, va_list args)
 127 {
 128         unsigned len;
 129
 130         if (!__i915_error_ok(e))
 131                 return;
 132
 133         /* Seek the first printf which is hits start position */
 134         if (e->pos < e->start) {
 135                 va_list tmp;
 136
 137                 va_copy(tmp, args);
 138                 len = vsnprintf(NULL, 0, f, tmp);
 139                 va_end(tmp);
 140
 141                 if (!__i915_error_seek(e, len))
 142                         return;
 143         }
 144
 145         len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
 146         if (len >= e->size - e->bytes)
 147                 len = e->size - e->bytes - 1;
 148
 149         __i915_error_advance(e, len);
 150 }
 151
 152 static void i915_error_puts(struct drm_i915_error_state_buf *e,
 153                             const char *str)
 154 {
 155         unsigned len;
 156
 157         if (!__i915_error_ok(e))
 158                 return;
 159
 160         len = strlen(str);
 161
 162         /* Seek the first printf which is hits start position */
 163         if (e->pos < e->start) {
 164                 if (!__i915_error_seek(e, len))
 165                         return;
 166         }
 167
 168         if (len >= e->size - e->bytes)
 169                 len = e->size - e->bytes - 1;
 170         memcpy(e->buf + e->bytes, str, len);
 171
 172         __i915_error_advance(e, len);
 173 }
 174
 175 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
 176 #define err_puts(e, s) i915_error_puts(e, s)
 177
 178 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
 179
 180 struct compress {
 181         struct z_stream_s zstream;
 182         void *tmp;
 183 };
 184
 185 static bool compress_init(struct compress *c)
 186 {
 187         struct z_stream_s *zstream = memset(&c->zstream, 0, sizeof(c->zstream));
 188
 189         zstream->workspace =
 190                 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
 191                         GFP_ATOMIC | __GFP_NOWARN);
 192         if (!zstream->workspace)
 193                 return false;
 194
 195         if (zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) != Z_OK) {
 196                 kfree(zstream->workspace);
 197                 return false;
 198         }
 199
 200         c->tmp = NULL;
 201         if (i915_has_memcpy_from_wc())
 202                 c->tmp = (void *)__get_free_page(GFP_ATOMIC | __GFP_NOWARN);
 203
 204         return true;
 205 }
 206
 207 static int compress_page(struct compress *c,
 208                          void *src,
 209                          struct drm_i915_error_object *dst)
 210 {
 211         struct z_stream_s *zstream = &c->zstream;
 212
 213         zstream->next_in = src;
 214         if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
 215                 zstream->next_in = c->tmp;
 216         zstream->avail_in = PAGE_SIZE;
 217
 218         do {
 219                 if (zstream->avail_out == 0) {
 220                         unsigned long page;
 221
 222                         page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
 223                         if (!page)
 224                                 return -ENOMEM;
 225
 226                         dst->pages[dst->page_count++] = (void *)page;
 227
 228                         zstream->next_out = (void *)page;
 229                         zstream->avail_out = PAGE_SIZE;
 230                 }
 231
 232                 if (zlib_deflate(zstream, Z_SYNC_FLUSH) != Z_OK)
 233                         return -EIO;
 234         } while (zstream->avail_in);
 235
 236         /* Fallback to uncompressed if we increase size? */
 237         if (0 && zstream->total_out > zstream->total_in)
 238                 return -E2BIG;
 239
 240         return 0;
 241 }
 242
 243 static void compress_fini(struct compress *c,
 244                           struct drm_i915_error_object *dst)
 245 {
 246         struct z_stream_s *zstream = &c->zstream;
 247
 248         if (dst) {
 249                 zlib_deflate(zstream, Z_FINISH);
 250                 dst->unused = zstream->avail_out;
 251         }
 252
 253         zlib_deflateEnd(zstream);
 254         kfree(zstream->workspace);
 255
 256         if (c->tmp)
 257                 free_page((unsigned long)c->tmp);
 258 }
 259
 260 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 261 {
 262         err_puts(m, ":");
 263 }
 264
 265 #else
 266
 267 struct compress {
 268 };
 269
 270 static bool compress_init(struct compress *c)
 271 {
 272         return true;
 273 }
 274
 275 static int compress_page(struct compress *c,
 276                          void *src,
 277                          struct drm_i915_error_object *dst)
 278 {
 279         unsigned long page;
 280         void *ptr;
 281
 282         page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
 283         if (!page)
 284                 return -ENOMEM;
 285
 286         ptr = (void *)page;
 287         if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE))
 288                 memcpy(ptr, src, PAGE_SIZE);
 289         dst->pages[dst->page_count++] = ptr;
 290
 291         return 0;
 292 }
 293
 294 static void compress_fini(struct compress *c,
 295                           struct drm_i915_error_object *dst)
 296 {
 297 }
 298
 299 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 300 {
 301         err_puts(m, "~");
 302 }
 303
 304 #endif
 305
 306 static void print_error_buffers(struct drm_i915_error_state_buf *m,
 307                                 const char *name,
 308                                 struct drm_i915_error_buffer *err,
 309                                 int count)
 310 {
 311         int i;
 312
 313         err_printf(m, "%s [%d]:\n", name, count);
 314
 315         while (count--) {
 316                 err_printf(m, "    %08x_%08x %8u %02x %02x [ ",
 317                            upper_32_bits(err->gtt_offset),
 318                            lower_32_bits(err->gtt_offset),
 319                            err->size,
 320                            err->read_domains,
 321                            err->write_domain);
 322                 for (i = 0; i < I915_NUM_ENGINES; i++)
 323                         err_printf(m, "%02x ", err->rseqno[i]);
 324
 325                 err_printf(m, "] %02x", err->wseqno);
 326                 err_puts(m, tiling_flag(err->tiling));
 327                 err_puts(m, dirty_flag(err->dirty));
 328                 err_puts(m, purgeable_flag(err->purgeable));
 329                 err_puts(m, err->userptr ? " userptr" : "");
 330                 err_puts(m, err->engine != -1 ? " " : "");
 331                 err_puts(m, engine_str(err->engine));
 332                 err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
 333
 334                 if (err->name)
 335                         err_printf(m, " (name: %d)", err->name);
 336                 if (err->fence_reg != I915_FENCE_REG_NONE)
 337                         err_printf(m, " (fence: %d)", err->fence_reg);
 338
 339                 err_puts(m, "\n");
 340                 err++;
 341         }
 342 }
 343
 344 static void error_print_instdone(struct drm_i915_error_state_buf *m,
 345                                  const struct drm_i915_error_engine *ee)
 346 {
 347         int slice;
 348         int subslice;
 349
 350         err_printf(m, "  INSTDONE: 0x%08x\n",
 351                    ee->instdone.instdone);
 352
 353         if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3)
 354                 return;
 355
 356         err_printf(m, "  SC_INSTDONE: 0x%08x\n",
 357                    ee->instdone.slice_common);
 358
 359         if (INTEL_GEN(m->i915) <= 6)
 360                 return;
 361
 362         for_each_instdone_slice_subslice(m->i915, slice, subslice)
 363                 err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
 364                            slice, subslice,
 365                            ee->instdone.sampler[slice][subslice]);
 366
 367         for_each_instdone_slice_subslice(m->i915, slice, subslice)
 368                 err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
 369                            slice, subslice,
 370                            ee->instdone.row[slice][subslice]);
 371 }
 372
 373 static void error_print_request(struct drm_i915_error_state_buf *m,
 374                                 const char *prefix,
 375                                 const struct drm_i915_error_request *erq)
 376 {
 377         if (!erq->seqno)
 378                 return;
 379
 380         err_printf(m, "%s pid %d, ban score %d, seqno %8x:%08x, emitted %dms ago, head %08x, tail %08x\n",
 381                    prefix, erq->pid, erq->ban_score,
 382                    erq->context, erq->seqno,
 383                    jiffies_to_msecs(jiffies - erq->jiffies),
 384                    erq->head, erq->tail);
 385 }
 386
 387 static void error_print_context(struct drm_i915_error_state_buf *m,
 388                                 const char *header,
 389                                 const struct drm_i915_error_context *ctx)
 390 {
 391         err_printf(m, "%s%s[%d] user_handle %d hw_id %d, ban score %d guilty %d active %d\n",
 392                    header, ctx->comm, ctx->pid, ctx->handle, ctx->hw_id,
 393                    ctx->ban_score, ctx->guilty, ctx->active);
 394 }
 395
 396 static void error_print_engine(struct drm_i915_error_state_buf *m,
 397                                const struct drm_i915_error_engine *ee)
 398 {
 399         err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
 400         err_printf(m, "  START: 0x%08x\n", ee->start);
 401         err_printf(m, "  HEAD:  0x%08x [0x%08x]\n", ee->head, ee->rq_head);
 402         err_printf(m, "  TAIL:  0x%08x [0x%08x, 0x%08x]\n",
 403                    ee->tail, ee->rq_post, ee->rq_tail);
 404         err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
 405         err_printf(m, "  MODE:  0x%08x\n", ee->mode);
 406         err_printf(m, "  HWS:   0x%08x\n", ee->hws);
 407         err_printf(m, "  ACTHD: 0x%08x %08x\n",
 408                    (u32)(ee->acthd>>32), (u32)ee->acthd);
 409         err_printf(m, "  IPEIR: 0x%08x\n", ee->ipeir);
 410         err_printf(m, "  IPEHR: 0x%08x\n", ee->ipehr);
 411
 412         error_print_instdone(m, ee);
 413
 414         if (ee->batchbuffer) {
 415                 u64 start = ee->batchbuffer->gtt_offset;
 416                 u64 end = start + ee->batchbuffer->gtt_size;
 417
 418                 err_printf(m, "  batch: [0x%08x_%08x, 0x%08x_%08x]\n",
 419                            upper_32_bits(start), lower_32_bits(start),
 420                            upper_32_bits(end), lower_32_bits(end));
 421         }
 422         if (INTEL_GEN(m->i915) >= 4) {
 423                 err_printf(m, "  BBADDR: 0x%08x_%08x\n",
 424                            (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
 425                 err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
 426                 err_printf(m, "  INSTPS: 0x%08x\n", ee->instps);
 427         }
 428         err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
 429         err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
 430                    lower_32_bits(ee->faddr));
 431         if (INTEL_GEN(m->i915) >= 6) {
 432                 err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
 433                 err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
 434                 err_printf(m, "  SYNC_0: 0x%08x\n",
 435                            ee->semaphore_mboxes[0]);
 436                 err_printf(m, "  SYNC_1: 0x%08x\n",
 437                            ee->semaphore_mboxes[1]);
 438                 if (HAS_VEBOX(m->i915))
 439                         err_printf(m, "  SYNC_2: 0x%08x\n",
 440                                    ee->semaphore_mboxes[2]);
 441         }
 442         if (USES_PPGTT(m->i915)) {
 443                 err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
 444
 445                 if (INTEL_GEN(m->i915) >= 8) {
 446                         int i;
 447                         for (i = 0; i < 4; i++)
 448                                 err_printf(m, "  PDP%d: 0x%016llx\n",
 449                                            i, ee->vm_info.pdp[i]);
 450                 } else {
 451                         err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
 452                                    ee->vm_info.pp_dir_base);
 453                 }
 454         }
 455         err_printf(m, "  seqno: 0x%08x\n", ee->seqno);
 456         err_printf(m, "  last_seqno: 0x%08x\n", ee->last_seqno);
 457         err_printf(m, "  waiting: %s\n", yesno(ee->waiting));
 458         err_printf(m, "  ring->head: 0x%08x\n", ee->cpu_ring_head);
 459         err_printf(m, "  ring->tail: 0x%08x\n", ee->cpu_ring_tail);
 460         err_printf(m, "  hangcheck stall: %s\n", yesno(ee->hangcheck_stalled));
 461         err_printf(m, "  hangcheck action: %s\n",
 462                    hangcheck_action_to_str(ee->hangcheck_action));
 463         err_printf(m, "  hangcheck action timestamp: %lu, %u ms ago\n",
 464                    ee->hangcheck_timestamp,
 465                    jiffies_to_msecs(jiffies - ee->hangcheck_timestamp));
 466         err_printf(m, "  engine reset count: %u\n", ee->reset_count);
 467
 468         error_print_request(m, "  ELSP[0]: ", &ee->execlist[0]);
 469         error_print_request(m, "  ELSP[1]: ", &ee->execlist[1]);
 470         error_print_context(m, "  Active context: ", &ee->context);
 471 }
 472
 473 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
 474 {
 475         va_list args;
 476
 477         va_start(args, f);
 478         i915_error_vprintf(e, f, args);
 479         va_end(args);
 480 }
 481
 482 static int
 483 ascii85_encode_len(int len)
 484 {
 485         return DIV_ROUND_UP(len, 4);
 486 }
 487
 488 static bool
 489 ascii85_encode(u32 in, char *out)
 490 {
 491         int i;
 492
 493         if (in == 0)
 494                 return false;
 495
 496         out[5] = '\0';
 497         for (i = 5; i--; ) {
 498                 out[i] = '!' + in % 85;
 499                 in /= 85;
 500         }
 501
 502         return true;
 503 }
 504
 505 static void print_error_obj(struct drm_i915_error_state_buf *m,
 506                             struct intel_engine_cs *engine,
 507                             const char *name,
 508                             struct drm_i915_error_object *obj)
 509 {
 510         char out[6];
 511         int page;
 512
 513         if (!obj)
 514                 return;
 515
 516         if (name) {
 517                 err_printf(m, "%s --- %s = 0x%08x %08x\n",
 518                            engine ? engine->name : "global", name,
 519                            upper_32_bits(obj->gtt_offset),
 520                            lower_32_bits(obj->gtt_offset));
 521         }
 522
 523         err_compression_marker(m);
 524         for (page = 0; page < obj->page_count; page++) {
 525                 int i, len;
 526
 527                 len = PAGE_SIZE;
 528                 if (page == obj->page_count - 1)
 529                         len -= obj->unused;
 530                 len = ascii85_encode_len(len);
 531
 532                 for (i = 0; i < len; i++) {
 533                         if (ascii85_encode(obj->pages[page][i], out))
 534                                 err_puts(m, out);
 535                         else
 536                                 err_puts(m, "z");
 537                 }
 538         }
 539         err_puts(m, "\n");
 540 }
 541
 542 static void err_print_capabilities(struct drm_i915_error_state_buf *m,
 543                                    const struct intel_device_info *info)
 544 {
 545 #define PRINT_FLAG(x)  err_printf(m, #x ": %s\n", yesno(info->x))
 546         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
 547 #undef PRINT_FLAG
 548 }
 549
 550 static __always_inline void err_print_param(struct drm_i915_error_state_buf *m,
 551                                             const char *name,
 552                                             const char *type,
 553                                             const void *x)
 554 {
 555         if (!__builtin_strcmp(type, "bool"))
 556                 err_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x));
 557         else if (!__builtin_strcmp(type, "int"))
 558                 err_printf(m, "i915.%s=%d\n", name, *(const int *)x);
 559         else if (!__builtin_strcmp(type, "unsigned int"))
 560                 err_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x);
 561         else if (!__builtin_strcmp(type, "char *"))
 562                 err_printf(m, "i915.%s=%s\n", name, *(const char **)x);
 563         else
 564                 BUILD_BUG();
 565 }
 566
 567 static void err_print_params(struct drm_i915_error_state_buf *m,
 568                              const struct i915_params *p)
 569 {
 570 #define PRINT(T, x) err_print_param(m, #x, #T, &p->x);
 571         I915_PARAMS_FOR_EACH(PRINT);
 572 #undef PRINT
 573 }
 574
 575 static void err_print_pciid(struct drm_i915_error_state_buf *m,
 576                             struct drm_i915_private *i915)
 577 {
 578         struct pci_dev *pdev = i915->drm.pdev;
 579
 580         err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
 581         err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
 582         err_printf(m, "PCI Subsystem: %04x:%04x\n",
 583                    pdev->subsystem_vendor,
 584                    pdev->subsystem_device);
 585 }
 586
 587 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 588                             const struct i915_gpu_state *error)
 589 {
 590         struct drm_i915_private *dev_priv = m->i915;
 591         struct drm_i915_error_object *obj;
 592         int i, j;
 593
 594         if (!error) {
 595                 err_printf(m, "No error state collected\n");
 596                 return 0;
 597         }
 598
 599         if (*error->error_msg)
 600                 err_printf(m, "%s\n", error->error_msg);
 601         err_printf(m, "Kernel: " UTS_RELEASE "\n");
 602         err_printf(m, "Time: %ld s %ld us\n",
 603                    error->time.tv_sec, error->time.tv_usec);
 604         err_printf(m, "Boottime: %ld s %ld us\n",
 605                    error->boottime.tv_sec, error->boottime.tv_usec);
 606         err_printf(m, "Uptime: %ld s %ld us\n",
 607                    error->uptime.tv_sec, error->uptime.tv_usec);
 608
 609         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 610                 if (error->engine[i].hangcheck_stalled &&
 611                     error->engine[i].context.pid) {
 612                         err_printf(m, "Active process (on ring %s): %s [%d], score %d\n",
 613                                    engine_str(i),
 614                                    error->engine[i].context.comm,
 615                                    error->engine[i].context.pid,
 616                                    error->engine[i].context.ban_score);
 617                 }
 618         }
 619         err_printf(m, "Reset count: %u\n", error->reset_count);
 620         err_printf(m, "Suspend count: %u\n", error->suspend_count);
 621         err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
 622         err_print_pciid(m, error->i915);
 623
 624         err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
 625
 626         if (HAS_CSR(dev_priv)) {
 627                 struct intel_csr *csr = &dev_priv->csr;
 628
 629                 err_printf(m, "DMC loaded: %s\n",
 630                            yesno(csr->dmc_payload != NULL));
 631                 err_printf(m, "DMC fw version: %d.%d\n",
 632                            CSR_VERSION_MAJOR(csr->version),
 633                            CSR_VERSION_MINOR(csr->version));
 634         }
 635
 636         err_printf(m, "GT awake: %s\n", yesno(error->awake));
 637         err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
 638         err_printf(m, "PM suspended: %s\n", yesno(error->suspended));
 639         err_printf(m, "EIR: 0x%08x\n", error->eir);
 640         err_printf(m, "IER: 0x%08x\n", error->ier);
 641         for (i = 0; i < error->ngtier; i++)
 642                 err_printf(m, "GTIER[%d]: 0x%08x\n", i, error->gtier[i]);
 643         err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
 644         err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
 645         err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
 646         err_printf(m, "CCID: 0x%08x\n", error->ccid);
 647         err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
 648
 649         for (i = 0; i < error->nfence; i++)
 650                 err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);
 651
 652         if (INTEL_GEN(dev_priv) >= 6) {
 653                 err_printf(m, "ERROR: 0x%08x\n", error->error);
 654
 655                 if (INTEL_GEN(dev_priv) >= 8)
 656                         err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
 657                                    error->fault_data1, error->fault_data0);
 658
 659                 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
 660         }
 661
 662         if (IS_GEN7(dev_priv))
 663                 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
 664
 665         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 666                 if (error->engine[i].engine_id != -1)
 667                         error_print_engine(m, &error->engine[i]);
 668         }
 669
 670         for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) {
 671                 char buf[128];
 672                 int len, first = 1;
 673
 674                 if (!error->active_vm[i])
 675                         break;
 676
 677                 len = scnprintf(buf, sizeof(buf), "Active (");
 678                 for (j = 0; j < ARRAY_SIZE(error->engine); j++) {
 679                         if (error->engine[j].vm != error->active_vm[i])
 680                                 continue;
 681
 682                         len += scnprintf(buf + len, sizeof(buf), "%s%s",
 683                                          first ? "" : ", ",
 684                                          dev_priv->engine[j]->name);
 685                         first = 0;
 686                 }
 687                 scnprintf(buf + len, sizeof(buf), ")");
 688                 print_error_buffers(m, buf,
 689                                     error->active_bo[i],
 690                                     error->active_bo_count[i]);
 691         }
 692
 693         print_error_buffers(m, "Pinned (global)",
 694                             error->pinned_bo,
 695                             error->pinned_bo_count);
 696
 697         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 698                 const struct drm_i915_error_engine *ee = &error->engine[i];
 699
 700                 obj = ee->batchbuffer;
 701                 if (obj) {
 702                         err_puts(m, dev_priv->engine[i]->name);
 703                         if (ee->context.pid)
 704                                 err_printf(m, " (submitted by %s [%d], ctx %d [%d], score %d)",
 705                                            ee->context.comm,
 706                                            ee->context.pid,
 707                                            ee->context.handle,
 708                                            ee->context.hw_id,
 709                                            ee->context.ban_score);
 710                         err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
 711                                    upper_32_bits(obj->gtt_offset),
 712                                    lower_32_bits(obj->gtt_offset));
 713                         print_error_obj(m, dev_priv->engine[i], NULL, obj);
 714                 }
 715
 716                 for (j = 0; j < ee->user_bo_count; j++)
 717                         print_error_obj(m, dev_priv->engine[i],
 718                                         "user", ee->user_bo[j]);
 719
 720                 if (ee->num_requests) {
 721                         err_printf(m, "%s --- %d requests\n",
 722                                    dev_priv->engine[i]->name,
 723                                    ee->num_requests);
 724                         for (j = 0; j < ee->num_requests; j++)
 725                                 error_print_request(m, " ", &ee->requests[j]);
 726                 }
 727
 728                 if (IS_ERR(ee->waiters)) {
 729                         err_printf(m, "%s --- ? waiters [unable to acquire spinlock]\n",
 730                                    dev_priv->engine[i]->name);
 731                 } else if (ee->num_waiters) {
 732                         err_printf(m, "%s --- %d waiters\n",
 733                                    dev_priv->engine[i]->name,
 734                                    ee->num_waiters);
 735                         for (j = 0; j < ee->num_waiters; j++) {
 736                                 err_printf(m, " seqno 0x%08x for %s [%d]\n",
 737                                            ee->waiters[j].seqno,
 738                                            ee->waiters[j].comm,
 739                                            ee->waiters[j].pid);
 740                         }
 741                 }
 742
 743                 print_error_obj(m, dev_priv->engine[i],
 744                                 "ringbuffer", ee->ringbuffer);
 745
 746                 print_error_obj(m, dev_priv->engine[i],
 747                                 "HW Status", ee->hws_page);
 748
 749                 print_error_obj(m, dev_priv->engine[i],
 750                                 "HW context", ee->ctx);
 751
 752                 print_error_obj(m, dev_priv->engine[i],
 753                                 "WA context", ee->wa_ctx);
 754
 755                 print_error_obj(m, dev_priv->engine[i],
 756                                 "WA batchbuffer", ee->wa_batchbuffer);
 757         }
 758
 759         print_error_obj(m, NULL, "Semaphores", error->semaphore);
 760
 761         print_error_obj(m, NULL, "GuC log buffer", error->guc_log);
 762
 763         if (error->overlay)
 764                 intel_overlay_print_error_state(m, error->overlay);
 765
 766         if (error->display)
 767                 intel_display_print_error_state(m, error->display);
 768
 769         err_print_capabilities(m, &error->device_info);
 770         err_print_params(m, &error->params);
 771
 772         if (m->bytes == 0 && m->err)
 773                 return m->err;
 774
 775         return 0;
 776 }
 777
 778 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
 779                               struct drm_i915_private *i915,
 780                               size_t count, loff_t pos)
 781 {
 782         memset(ebuf, 0, sizeof(*ebuf));
 783         ebuf->i915 = i915;
 784
 785         /* We need to have enough room to store any i915_error_state printf
 786          * so that we can move it to start position.
 787          */
 788         ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
 789         ebuf->buf = kmalloc(ebuf->size,
 790                                 GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN);
 791
 792         if (ebuf->buf == NULL) {
 793                 ebuf->size = PAGE_SIZE;
 794                 ebuf->buf = kmalloc(ebuf->size, GFP_KERNEL);
 795         }
 796
 797         if (ebuf->buf == NULL) {
 798                 ebuf->size = 128;
 799                 ebuf->buf = kmalloc(ebuf->size, GFP_KERNEL);
 800         }
 801
 802         if (ebuf->buf == NULL)
 803                 return -ENOMEM;
 804
 805         ebuf->start = pos;
 806
 807         return 0;
 808 }
 809
 810 static void i915_error_object_free(struct drm_i915_error_object *obj)
 811 {
 812         int page;
 813
 814         if (obj == NULL)
 815                 return;
 816
 817         for (page = 0; page < obj->page_count; page++)
 818                 free_page((unsigned long)obj->pages[page]);
 819
 820         kfree(obj);
 821 }
 822
 823 static __always_inline void free_param(const char *type, void *x)
 824 {
 825         if (!__builtin_strcmp(type, "char *"))
 826                 kfree(*(void **)x);
 827 }
 828
 829 void __i915_gpu_state_free(struct kref *error_ref)
 830 {
 831         struct i915_gpu_state *error =
 832                 container_of(error_ref, typeof(*error), ref);
 833         long i, j;
 834
 835         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 836                 struct drm_i915_error_engine *ee = &error->engine[i];
 837
 838                 for (j = 0; j < ee->user_bo_count; j++)
 839                         i915_error_object_free(ee->user_bo[j]);
 840                 kfree(ee->user_bo);
 841
 842                 i915_error_object_free(ee->batchbuffer);
 843                 i915_error_object_free(ee->wa_batchbuffer);
 844                 i915_error_object_free(ee->ringbuffer);
 845                 i915_error_object_free(ee->hws_page);
 846                 i915_error_object_free(ee->ctx);
 847                 i915_error_object_free(ee->wa_ctx);
 848
 849                 kfree(ee->requests);
 850                 if (!IS_ERR_OR_NULL(ee->waiters))
 851                         kfree(ee->waiters);
 852         }
 853
 854         i915_error_object_free(error->semaphore);
 855         i915_error_object_free(error->guc_log);
 856
 857         for (i = 0; i < ARRAY_SIZE(error->active_bo); i++)
 858                 kfree(error->active_bo[i]);
 859         kfree(error->pinned_bo);
 860
 861         kfree(error->overlay);
 862         kfree(error->display);
 863
 864 #define FREE(T, x) free_param(#T, &error->params.x);
 865         I915_PARAMS_FOR_EACH(FREE);
 866 #undef FREE
 867
 868         kfree(error);
 869 }
 870
 871 static struct drm_i915_error_object *
 872 i915_error_object_create(struct drm_i915_private *i915,
 873                          struct i915_vma *vma)
 874 {
 875         struct i915_ggtt *ggtt = &i915->ggtt;
 876         const u64 slot = ggtt->error_capture.start;
 877         struct drm_i915_error_object *dst;
 878         struct compress compress;
 879         unsigned long num_pages;
 880         struct sgt_iter iter;
 881         dma_addr_t dma;
 882
 883         if (!vma)
 884                 return NULL;
 885
 886         num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
 887         num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
 888         dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *),
 889                       GFP_ATOMIC | __GFP_NOWARN);
 890         if (!dst)
 891                 return NULL;
 892
 893         dst->gtt_offset = vma->node.start;
 894         dst->gtt_size = vma->node.size;
 895         dst->page_count = 0;
 896         dst->unused = 0;
 897
 898         if (!compress_init(&compress)) {
 899                 kfree(dst);
 900                 return NULL;
 901         }
 902
 903         for_each_sgt_dma(dma, iter, vma->pages) {
 904                 void __iomem *s;
 905                 int ret;
 906
 907                 ggtt->base.insert_page(&ggtt->base, dma, slot,
 908                                        I915_CACHE_NONE, 0);
 909
 910                 s = io_mapping_map_atomic_wc(&ggtt->mappable, slot);
 911                 ret = compress_page(&compress, (void  __force *)s, dst);
 912                 io_mapping_unmap_atomic(s);
 913
 914                 if (ret)
 915                         goto unwind;
 916         }
 917         goto out;
 918
 919 unwind:
 920         while (dst->page_count--)
 921                 free_page((unsigned long)dst->pages[dst->page_count]);
 922         kfree(dst);
 923         dst = NULL;
 924
 925 out:
 926         compress_fini(&compress, dst);
 927         ggtt->base.clear_range(&ggtt->base, slot, PAGE_SIZE);
 928         return dst;
 929 }
 930
 931 /* The error capture is special as tries to run underneath the normal
 932  * locking rules - so we use the raw version of the i915_gem_active lookup.
 933  */
 934 static inline uint32_t
 935 __active_get_seqno(struct i915_gem_active *active)
 936 {
 937         struct drm_i915_gem_request *request;
 938
 939         request = __i915_gem_active_peek(active);
 940         return request ? request->global_seqno : 0;
 941 }
 942
 943 static inline int
 944 __active_get_engine_id(struct i915_gem_active *active)
 945 {
 946         struct drm_i915_gem_request *request;
 947
 948         request = __i915_gem_active_peek(active);
 949         return request ? request->engine->id : -1;
 950 }
 951
 952 static void capture_bo(struct drm_i915_error_buffer *err,
 953                        struct i915_vma *vma)
 954 {
 955         struct drm_i915_gem_object *obj = vma->obj;
 956         int i;
 957
 958         err->size = obj->base.size;
 959         err->name = obj->base.name;
 960
 961         for (i = 0; i < I915_NUM_ENGINES; i++)
 962                 err->rseqno[i] = __active_get_seqno(&vma->last_read[i]);
 963         err->wseqno = __active_get_seqno(&obj->frontbuffer_write);
 964         err->engine = __active_get_engine_id(&obj->frontbuffer_write);
 965
 966         err->gtt_offset = vma->node.start;
 967         err->read_domains = obj->base.read_domains;
 968         err->write_domain = obj->base.write_domain;
 969         err->fence_reg = vma->fence ? vma->fence->id : -1;
 970         err->tiling = i915_gem_object_get_tiling(obj);
 971         err->dirty = obj->mm.dirty;
 972         err->purgeable = obj->mm.madv != I915_MADV_WILLNEED;
 973         err->userptr = obj->userptr.mm != NULL;
 974         err->cache_level = obj->cache_level;
 975 }
 976
 977 static u32 capture_error_bo(struct drm_i915_error_buffer *err,
 978                             int count, struct list_head *head,
 979                             bool pinned_only)
 980 {
 981         struct i915_vma *vma;
 982         int i = 0;
 983
 984         list_for_each_entry(vma, head, vm_link) {
 985                 if (pinned_only && !i915_vma_is_pinned(vma))
 986                         continue;
 987
 988                 capture_bo(err++, vma);
 989                 if (++i == count)
 990                         break;
 991         }
 992
 993         return i;
 994 }
 995
 996 /* Generate a semi-unique error code. The code is not meant to have meaning, The
 997  * code's only purpose is to try to prevent false duplicated bug reports by
 998  * grossly estimating a GPU error state.
 999  *
1000  * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
1001  * the hang if we could strip the GTT offset information from it.
1002  *
1003  * It's only a small step better than a random number in its current form.
1004  */
1005 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
1006                                          struct i915_gpu_state *error,
1007                                          int *engine_id)
1008 {
1009         uint32_t error_code = 0;
1010         int i;
1011
1012         /* IPEHR would be an ideal way to detect errors, as it's the gross
1013          * measure of "the command that hung." However, has some very common
1014          * synchronization commands which almost always appear in the case
1015          * strictly a client bug. Use instdone to differentiate those some.
1016          */
1017         for (i = 0; i < I915_NUM_ENGINES; i++) {
1018                 if (error->engine[i].hangcheck_stalled) {
1019                         if (engine_id)
1020                                 *engine_id = i;
1021
1022                         return error->engine[i].ipehr ^
1023                                error->engine[i].instdone.instdone;
1024                 }
1025         }
1026
1027         return error_code;
1028 }
1029
1030 static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
1031                                    struct i915_gpu_state *error)
1032 {
1033         int i;
1034
1035         if (INTEL_GEN(dev_priv) >= 6) {
1036                 for (i = 0; i < dev_priv->num_fence_regs; i++)
1037                         error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
1038         } else if (INTEL_GEN(dev_priv) >= 4) {
1039                 for (i = 0; i < dev_priv->num_fence_regs; i++)
1040                         error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
1041         } else {
1042                 for (i = 0; i < dev_priv->num_fence_regs; i++)
1043                         error->fence[i] = I915_READ(FENCE_REG(i));
1044         }
1045         error->nfence = i;
1046 }
1047
1048 static inline u32
1049 gen8_engine_sync_index(struct intel_engine_cs *engine,
1050                        struct intel_engine_cs *other)
1051 {
1052         int idx;
1053
1054         /*
1055          * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
1056          * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
1057          * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
1058          * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
1059          * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
1060          */
1061
1062         idx = (other - engine) - 1;
1063         if (idx < 0)
1064                 idx += I915_NUM_ENGINES;
1065
1066         return idx;
1067 }
1068
1069 static void gen8_record_semaphore_state(struct i915_gpu_state *error,
1070                                         struct intel_engine_cs *engine,
1071                                         struct drm_i915_error_engine *ee)
1072 {
1073         struct drm_i915_private *dev_priv = engine->i915;
1074         struct intel_engine_cs *to;
1075         enum intel_engine_id id;
1076
1077         if (!error->semaphore)
1078                 return;
1079
1080         for_each_engine(to, dev_priv, id) {
1081                 int idx;
1082                 u16 signal_offset;
1083                 u32 *tmp;
1084
1085                 if (engine == to)
1086                         continue;
1087
1088                 signal_offset =
1089                         (GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1)) / 4;
1090                 tmp = error->semaphore->pages[0];
1091                 idx = gen8_engine_sync_index(engine, to);
1092
1093                 ee->semaphore_mboxes[idx] = tmp[signal_offset];
1094         }
1095 }
1096
1097 static void gen6_record_semaphore_state(struct intel_engine_cs *engine,
1098                                         struct drm_i915_error_engine *ee)
1099 {
1100         struct drm_i915_private *dev_priv = engine->i915;
1101
1102         ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
1103         ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
1104         if (HAS_VEBOX(dev_priv))
1105                 ee->semaphore_mboxes[2] =
1106                         I915_READ(RING_SYNC_2(engine->mmio_base));
1107 }
1108
1109 static void error_record_engine_waiters(struct intel_engine_cs *engine,
1110                                         struct drm_i915_error_engine *ee)
1111 {
1112         struct intel_breadcrumbs *b = &engine->breadcrumbs;
1113         struct drm_i915_error_waiter *waiter;
1114         struct rb_node *rb;
1115         int count;
1116
1117         ee->num_waiters = 0;
1118         ee->waiters = NULL;
1119
1120         if (RB_EMPTY_ROOT(&b->waiters))
1121                 return;
1122
1123         if (!spin_trylock_irq(&b->rb_lock)) {
1124                 ee->waiters = ERR_PTR(-EDEADLK);
1125                 return;
1126         }
1127
1128         count = 0;
1129         for (rb = rb_first(&b->waiters); rb != NULL; rb = rb_next(rb))
1130                 count++;
1131         spin_unlock_irq(&b->rb_lock);
1132
1133         waiter = NULL;
1134         if (count)
1135                 waiter = kmalloc_array(count,
1136                                        sizeof(struct drm_i915_error_waiter),
1137                                        GFP_ATOMIC);
1138         if (!waiter)
1139                 return;
1140
1141         if (!spin_trylock_irq(&b->rb_lock)) {
1142                 kfree(waiter);
1143                 ee->waiters = ERR_PTR(-EDEADLK);
1144                 return;
1145         }
1146
1147         ee->waiters = waiter;
1148         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1149                 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1150
1151                 strcpy(waiter->comm, w->tsk->comm);
1152                 waiter->pid = w->tsk->pid;
1153                 waiter->seqno = w->seqno;
1154                 waiter++;
1155
1156                 if (++ee->num_waiters == count)
1157                         break;
1158         }
1159         spin_unlock_irq(&b->rb_lock);
1160 }
1161
1162 static void error_record_engine_registers(struct i915_gpu_state *error,
1163                                           struct intel_engine_cs *engine,
1164                                           struct drm_i915_error_engine *ee)
1165 {
1166         struct drm_i915_private *dev_priv = engine->i915;
1167
1168         if (INTEL_GEN(dev_priv) >= 6) {
1169                 ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
1170                 ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
1171                 if (INTEL_GEN(dev_priv) >= 8)
1172                         gen8_record_semaphore_state(error, engine, ee);
1173                 else
1174                         gen6_record_semaphore_state(engine, ee);
1175         }
1176
1177         if (INTEL_GEN(dev_priv) >= 4) {
1178                 ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
1179                 ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
1180                 ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
1181                 ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
1182                 ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
1183                 if (INTEL_GEN(dev_priv) >= 8) {
1184                         ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
1185                         ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
1186                 }
1187                 ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
1188         } else {
1189                 ee->faddr = I915_READ(DMA_FADD_I8XX);
1190                 ee->ipeir = I915_READ(IPEIR);
1191                 ee->ipehr = I915_READ(IPEHR);
1192         }
1193
1194         intel_engine_get_instdone(engine, &ee->instdone);
1195
1196         ee->waiting = intel_engine_has_waiter(engine);
1197         ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
1198         ee->acthd = intel_engine_get_active_head(engine);
1199         ee->seqno = intel_engine_get_seqno(engine);
1200         ee->last_seqno = intel_engine_last_submit(engine);
1201         ee->start = I915_READ_START(engine);
1202         ee->head = I915_READ_HEAD(engine);
1203         ee->tail = I915_READ_TAIL(engine);
1204         ee->ctl = I915_READ_CTL(engine);
1205         if (INTEL_GEN(dev_priv) > 2)
1206                 ee->mode = I915_READ_MODE(engine);
1207
1208         if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
1209                 i915_reg_t mmio;
1210
1211                 if (IS_GEN7(dev_priv)) {
1212                         switch (engine->id) {
1213                         default:
1214                         case RCS:
1215                                 mmio = RENDER_HWS_PGA_GEN7;
1216                                 break;
1217                         case BCS:
1218                                 mmio = BLT_HWS_PGA_GEN7;
1219                                 break;
1220                         case VCS:
1221                                 mmio = BSD_HWS_PGA_GEN7;
1222                                 break;
1223                         case VECS:
1224                                 mmio = VEBOX_HWS_PGA_GEN7;
1225                                 break;
1226                         }
1227                 } else if (IS_GEN6(engine->i915)) {
1228                         mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1229                 } else {
1230                         /* XXX: gen8 returns to sanity */
1231                         mmio = RING_HWS_PGA(engine->mmio_base);
1232                 }
1233
1234                 ee->hws = I915_READ(mmio);
1235         }
1236
1237         ee->hangcheck_timestamp = engine->hangcheck.action_timestamp;
1238         ee->hangcheck_action = engine->hangcheck.action;
1239         ee->hangcheck_stalled = engine->hangcheck.stalled;
1240         ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,
1241                                                   engine);
1242
1243         if (USES_PPGTT(dev_priv)) {
1244                 int i;
1245
1246                 ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
1247
1248                 if (IS_GEN6(dev_priv))
1249                         ee->vm_info.pp_dir_base =
1250                                 I915_READ(RING_PP_DIR_BASE_READ(engine));
1251                 else if (IS_GEN7(dev_priv))
1252                         ee->vm_info.pp_dir_base =
1253                                 I915_READ(RING_PP_DIR_BASE(engine));
1254                 else if (INTEL_GEN(dev_priv) >= 8)
1255                         for (i = 0; i < 4; i++) {
1256                                 ee->vm_info.pdp[i] =
1257                                         I915_READ(GEN8_RING_PDP_UDW(engine, i));
1258                                 ee->vm_info.pdp[i] <<= 32;
1259                                 ee->vm_info.pdp[i] |=
1260                                         I915_READ(GEN8_RING_PDP_LDW(engine, i));
1261                         }
1262         }
1263 }
1264
1265 static void record_request(struct drm_i915_gem_request *request,
1266                            struct drm_i915_error_request *erq)
1267 {
1268         erq->context = request->ctx->hw_id;
1269         erq->ban_score = atomic_read(&request->ctx->ban_score);
1270         erq->seqno = request->global_seqno;
1271         erq->jiffies = request->emitted_jiffies;
1272         erq->head = request->head;
1273         erq->tail = request->tail;
1274
1275         rcu_read_lock();
1276         erq->pid = request->ctx->pid ? pid_nr(request->ctx->pid) : 0;
1277         rcu_read_unlock();
1278 }
1279
1280 static void engine_record_requests(struct intel_engine_cs *engine,
1281                                    struct drm_i915_gem_request *first,
1282                                    struct drm_i915_error_engine *ee)
1283 {
1284         struct drm_i915_gem_request *request;
1285         int count;
1286
1287         count = 0;
1288         request = first;
1289         list_for_each_entry_from(request, &engine->timeline->requests, link)
1290                 count++;
1291         if (!count)
1292                 return;
1293
1294         ee->requests = kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC);
1295         if (!ee->requests)
1296                 return;
1297
1298         ee->num_requests = count;
1299
1300         count = 0;
1301         request = first;
1302         list_for_each_entry_from(request, &engine->timeline->requests, link) {
1303                 if (count >= ee->num_requests) {
1304                         /*
1305                          * If the ring request list was changed in
1306                          * between the point where the error request
1307                          * list was created and dimensioned and this
1308                          * point then just exit early to avoid crashes.
1309                          *
1310                          * We don't need to communicate that the
1311                          * request list changed state during error
1312                          * state capture and that the error state is
1313                          * slightly incorrect as a consequence since we
1314                          * are typically only interested in the request
1315                          * list state at the point of error state
1316                          * capture, not in any changes happening during
1317                          * the capture.
1318                          */
1319                         break;
1320                 }
1321
1322                 record_request(request, &ee->requests[count++]);
1323         }
1324         ee->num_requests = count;
1325 }
1326
1327 static void error_record_engine_execlists(struct intel_engine_cs *engine,
1328                                           struct drm_i915_error_engine *ee)
1329 {
1330         const struct execlist_port *port = engine->execlist_port;
1331         unsigned int n;
1332
1333         for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) {
1334                 struct drm_i915_gem_request *rq = port_request(&port[n]);
1335
1336                 if (!rq)
1337                         break;
1338
1339                 record_request(rq, &ee->execlist[n]);
1340         }
1341 }
1342
1343 static void record_context(struct drm_i915_error_context *e,
1344                            struct i915_gem_context *ctx)
1345 {
1346         if (ctx->pid) {
1347                 struct task_struct *task;
1348
1349                 rcu_read_lock();
1350                 task = pid_task(ctx->pid, PIDTYPE_PID);
1351                 if (task) {
1352                         strcpy(e->comm, task->comm);
1353                         e->pid = task->pid;
1354                 }
1355                 rcu_read_unlock();
1356         }
1357
1358         e->handle = ctx->user_handle;
1359         e->hw_id = ctx->hw_id;
1360         e->ban_score = atomic_read(&ctx->ban_score);
1361         e->guilty = atomic_read(&ctx->guilty_count);
1362         e->active = atomic_read(&ctx->active_count);
1363 }
1364
1365 static void request_record_user_bo(struct drm_i915_gem_request *request,
1366                                    struct drm_i915_error_engine *ee)
1367 {
1368         struct i915_gem_capture_list *c;
1369         struct drm_i915_error_object **bo;
1370         long count;
1371
1372         count = 0;
1373         for (c = request->capture_list; c; c = c->next)
1374                 count++;
1375
1376         bo = NULL;
1377         if (count)
1378                 bo = kcalloc(count, sizeof(*bo), GFP_ATOMIC);
1379         if (!bo)
1380                 return;
1381
1382         count = 0;
1383         for (c = request->capture_list; c; c = c->next) {
1384                 bo[count] = i915_error_object_create(request->i915, c->vma);
1385                 if (!bo[count])
1386                         break;
1387                 count++;
1388         }
1389
1390         ee->user_bo = bo;
1391         ee->user_bo_count = count;
1392 }
1393
1394 static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
1395                                   struct i915_gpu_state *error)
1396 {
1397         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1398         int i;
1399
1400         error->semaphore =
1401                 i915_error_object_create(dev_priv, dev_priv->semaphore);
1402
1403         for (i = 0; i < I915_NUM_ENGINES; i++) {
1404                 struct intel_engine_cs *engine = dev_priv->engine[i];
1405                 struct drm_i915_error_engine *ee = &error->engine[i];
1406                 struct drm_i915_gem_request *request;
1407
1408                 ee->engine_id = -1;
1409
1410                 if (!engine)
1411                         continue;
1412
1413                 ee->engine_id = i;
1414
1415                 error_record_engine_registers(error, engine, ee);
1416                 error_record_engine_waiters(engine, ee);
1417                 error_record_engine_execlists(engine, ee);
1418
1419                 request = i915_gem_find_active_request(engine);
1420                 if (request) {
1421                         struct intel_ring *ring;
1422
1423                         ee->vm = request->ctx->ppgtt ?
1424                                 &request->ctx->ppgtt->base : &ggtt->base;
1425
1426                         record_context(&ee->context, request->ctx);
1427
1428                         /* We need to copy these to an anonymous buffer
1429                          * as the simplest method to avoid being overwritten
1430                          * by userspace.
1431                          */
1432                         ee->batchbuffer =
1433                                 i915_error_object_create(dev_priv,
1434                                                          request->batch);
1435
1436                         if (HAS_BROKEN_CS_TLB(dev_priv))
1437                                 ee->wa_batchbuffer =
1438                                         i915_error_object_create(dev_priv,
1439                                                                  engine->scratch);
1440                         request_record_user_bo(request, ee);
1441
1442                         ee->ctx =
1443                                 i915_error_object_create(dev_priv,
1444                                                          request->ctx->engine[i].state);
1445
1446                         error->simulated |=
1447                                 i915_gem_context_no_error_capture(request->ctx);
1448
1449                         ee->rq_head = request->head;
1450                         ee->rq_post = request->postfix;
1451                         ee->rq_tail = request->tail;
1452
1453                         ring = request->ring;
1454                         ee->cpu_ring_head = ring->head;
1455                         ee->cpu_ring_tail = ring->tail;
1456                         ee->ringbuffer =
1457                                 i915_error_object_create(dev_priv, ring->vma);
1458
1459                         engine_record_requests(engine, request, ee);
1460                 }
1461
1462                 ee->hws_page =
1463                         i915_error_object_create(dev_priv,
1464                                                  engine->status_page.vma);
1465
1466                 ee->wa_ctx =
1467                         i915_error_object_create(dev_priv, engine->wa_ctx.vma);
1468         }
1469 }
1470
1471 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
1472                                 struct i915_gpu_state *error,
1473                                 struct i915_address_space *vm,
1474                                 int idx)
1475 {
1476         struct drm_i915_error_buffer *active_bo;
1477         struct i915_vma *vma;
1478         int count;
1479
1480         count = 0;
1481         list_for_each_entry(vma, &vm->active_list, vm_link)
1482                 count++;
1483
1484         active_bo = NULL;
1485         if (count)
1486                 active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC);
1487         if (active_bo)
1488                 count = capture_error_bo(active_bo, count, &vm->active_list, false);
1489         else
1490                 count = 0;
1491
1492         error->active_vm[idx] = vm;
1493         error->active_bo[idx] = active_bo;
1494         error->active_bo_count[idx] = count;
1495 }
1496
1497 static void i915_capture_active_buffers(struct drm_i915_private *dev_priv,
1498                                         struct i915_gpu_state *error)
1499 {
1500         int cnt = 0, i, j;
1501
1502         BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo));
1503         BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm));
1504         BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count));
1505
1506         /* Scan each engine looking for unique active contexts/vm */
1507         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
1508                 struct drm_i915_error_engine *ee = &error->engine[i];
1509                 bool found;
1510
1511                 if (!ee->vm)
1512                         continue;
1513
1514                 found = false;
1515                 for (j = 0; j < i && !found; j++)
1516                         found = error->engine[j].vm == ee->vm;
1517                 if (!found)
1518                         i915_gem_capture_vm(dev_priv, error, ee->vm, cnt++);
1519         }
1520 }
1521
1522 static void i915_capture_pinned_buffers(struct drm_i915_private *dev_priv,
1523                                         struct i915_gpu_state *error)
1524 {
1525         struct i915_address_space *vm = &dev_priv->ggtt.base;
1526         struct drm_i915_error_buffer *bo;
1527         struct i915_vma *vma;
1528         int count_inactive, count_active;
1529
1530         count_inactive = 0;
1531         list_for_each_entry(vma, &vm->active_list, vm_link)
1532                 count_inactive++;
1533
1534         count_active = 0;
1535         list_for_each_entry(vma, &vm->inactive_list, vm_link)
1536                 count_active++;
1537
1538         bo = NULL;
1539         if (count_inactive + count_active)
1540                 bo = kcalloc(count_inactive + count_active,
1541                              sizeof(*bo), GFP_ATOMIC);
1542         if (!bo)
1543                 return;
1544
1545         count_inactive = capture_error_bo(bo, count_inactive,
1546                                           &vm->active_list, true);
1547         count_active = capture_error_bo(bo + count_inactive, count_active,
1548                                         &vm->inactive_list, true);
1549         error->pinned_bo_count = count_inactive + count_active;
1550         error->pinned_bo = bo;
1551 }
1552
1553 static void i915_gem_capture_guc_log_buffer(struct drm_i915_private *dev_priv,
1554                                             struct i915_gpu_state *error)
1555 {
1556         /* Capturing log buf contents won't be useful if logging was disabled */
1557         if (!dev_priv->guc.log.vma || (i915.guc_log_level < 0))
1558                 return;
1559
1560         error->guc_log = i915_error_object_create(dev_priv,
1561                                                   dev_priv->guc.log.vma);
1562 }
1563
1564 /* Capture all registers which don't fit into another category. */
1565 static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1566                                    struct i915_gpu_state *error)
1567 {
1568         int i;
1569
1570         /* General organization
1571          * 1. Registers specific to a single generation
1572          * 2. Registers which belong to multiple generations
1573          * 3. Feature specific registers.
1574          * 4. Everything else
1575          * Please try to follow the order.
1576          */
1577
1578         /* 1: Registers specific to a single generation */
1579         if (IS_VALLEYVIEW(dev_priv)) {
1580                 error->gtier[0] = I915_READ(GTIER);
1581                 error->ier = I915_READ(VLV_IER);
1582                 error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
1583         }
1584
1585         if (IS_GEN7(dev_priv))
1586                 error->err_int = I915_READ(GEN7_ERR_INT);
1587
1588         if (INTEL_GEN(dev_priv) >= 8) {
1589                 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
1590                 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
1591         }
1592
1593         if (IS_GEN6(dev_priv)) {
1594                 error->forcewake = I915_READ_FW(FORCEWAKE);
1595                 error->gab_ctl = I915_READ(GAB_CTL);
1596                 error->gfx_mode = I915_READ(GFX_MODE);
1597         }
1598
1599         /* 2: Registers which belong to multiple generations */
1600         if (INTEL_GEN(dev_priv) >= 7)
1601                 error->forcewake = I915_READ_FW(FORCEWAKE_MT);
1602
1603         if (INTEL_GEN(dev_priv) >= 6) {
1604                 error->derrmr = I915_READ(DERRMR);
1605                 error->error = I915_READ(ERROR_GEN6);
1606                 error->done_reg = I915_READ(DONE_REG);
1607         }
1608
1609         if (INTEL_GEN(dev_priv) >= 5)
1610                 error->ccid = I915_READ(CCID);
1611
1612         /* 3: Feature specific registers */
1613         if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1614                 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1615                 error->gac_eco = I915_READ(GAC_ECO_BITS);
1616         }
1617
1618         /* 4: Everything else */
1619         if (INTEL_GEN(dev_priv) >= 8) {
1620                 error->ier = I915_READ(GEN8_DE_MISC_IER);
1621                 for (i = 0; i < 4; i++)
1622                         error->gtier[i] = I915_READ(GEN8_GT_IER(i));
1623                 error->ngtier = 4;
1624         } else if (HAS_PCH_SPLIT(dev_priv)) {
1625                 error->ier = I915_READ(DEIER);
1626                 error->gtier[0] = I915_READ(GTIER);
1627                 error->ngtier = 1;
1628         } else if (IS_GEN2(dev_priv)) {
1629                 error->ier = I915_READ16(IER);
1630         } else if (!IS_VALLEYVIEW(dev_priv)) {
1631                 error->ier = I915_READ(IER);
1632         }
1633         error->eir = I915_READ(EIR);
1634         error->pgtbl_er = I915_READ(PGTBL_ER);
1635 }
1636
1637 static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
1638                                    struct i915_gpu_state *error,
1639                                    u32 engine_mask,
1640                                    const char *error_msg)
1641 {
1642         u32 ecode;
1643         int engine_id = -1, len;
1644
1645         ecode = i915_error_generate_code(dev_priv, error, &engine_id);
1646
1647         len = scnprintf(error->error_msg, sizeof(error->error_msg),
1648                         "GPU HANG: ecode %d:%d:0x%08x",
1649                         INTEL_GEN(dev_priv), engine_id, ecode);
1650
1651         if (engine_id != -1 && error->engine[engine_id].context.pid)
1652                 len += scnprintf(error->error_msg + len,
1653                                  sizeof(error->error_msg) - len,
1654                                  ", in %s [%d]",
1655                                  error->engine[engine_id].context.comm,
1656                                  error->engine[engine_id].context.pid);
1657
1658         scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1659                   ", reason: %s, action: %s",
1660                   error_msg,
1661                   engine_mask ? "reset" : "continue");
1662 }
1663
1664 static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
1665                                    struct i915_gpu_state *error)
1666 {
1667         error->awake = dev_priv->gt.awake;
1668         error->wakelock = atomic_read(&dev_priv->pm.wakeref_count);
1669         error->suspended = dev_priv->pm.suspended;
1670
1671         error->iommu = -1;
1672 #ifdef CONFIG_INTEL_IOMMU
1673         error->iommu = intel_iommu_gfx_mapped;
1674 #endif
1675         error->reset_count = i915_reset_count(&dev_priv->gpu_error);
1676         error->suspend_count = dev_priv->suspend_count;
1677
1678         memcpy(&error->device_info,
1679                INTEL_INFO(dev_priv),
1680                sizeof(error->device_info));
1681 }
1682
1683 static __always_inline void dup_param(const char *type, void *x)
1684 {
1685         if (!__builtin_strcmp(type, "char *"))
1686                 *(void **)x = kstrdup(*(void **)x, GFP_ATOMIC);
1687 }
1688
1689 static int capture(void *data)
1690 {
1691         struct i915_gpu_state *error = data;
1692
1693         do_gettimeofday(&error->time);
1694         error->boottime = ktime_to_timeval(ktime_get_boottime());
1695         error->uptime =
1696                 ktime_to_timeval(ktime_sub(ktime_get(),
1697                                            error->i915->gt.last_init_time));
1698
1699         error->params = i915;
1700 #define DUP(T, x) dup_param(#T, &error->params.x);
1701         I915_PARAMS_FOR_EACH(DUP);
1702 #undef DUP
1703
1704         i915_capture_gen_state(error->i915, error);
1705         i915_capture_reg_state(error->i915, error);
1706         i915_gem_record_fences(error->i915, error);
1707         i915_gem_record_rings(error->i915, error);
1708         i915_capture_active_buffers(error->i915, error);
1709         i915_capture_pinned_buffers(error->i915, error);
1710         i915_gem_capture_guc_log_buffer(error->i915, error);
1711
1712         error->overlay = intel_overlay_capture_error_state(error->i915);
1713         error->display = intel_display_capture_error_state(error->i915);
1714
1715         return 0;
1716 }
1717
1718 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
1719
1720 struct i915_gpu_state *
1721 i915_capture_gpu_state(struct drm_i915_private *i915)
1722 {
1723         struct i915_gpu_state *error;
1724
1725         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1726         if (!error)
1727                 return NULL;
1728
1729         kref_init(&error->ref);
1730         error->i915 = i915;
1731
1732         stop_machine(capture, error, NULL);
1733
1734         return error;
1735 }
1736
1737 /**
1738  * i915_capture_error_state - capture an error record for later analysis
1739  * @dev: drm device
1740  *
1741  * Should be called when an error is detected (either a hang or an error
1742  * interrupt) to capture error state from the time of the error.  Fills
1743  * out a structure which becomes available in debugfs for user level tools
1744  * to pick up.
1745  */
1746 void i915_capture_error_state(struct drm_i915_private *dev_priv,
1747                               u32 engine_mask,
1748                               const char *error_msg)
1749 {
1750         static bool warned;
1751         struct i915_gpu_state *error;
1752         unsigned long flags;
1753
1754         if (!i915.error_capture)
1755                 return;
1756
1757         if (READ_ONCE(dev_priv->gpu_error.first_error))
1758                 return;
1759
1760         error = i915_capture_gpu_state(dev_priv);
1761         if (!error) {
1762                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1763                 return;
1764         }
1765
1766         i915_error_capture_msg(dev_priv, error, engine_mask, error_msg);
1767         DRM_INFO("%s\n", error->error_msg);
1768
1769         if (!error->simulated) {
1770                 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1771                 if (!dev_priv->gpu_error.first_error) {
1772                         dev_priv->gpu_error.first_error = error;
1773                         error = NULL;
1774                 }
1775                 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1776         }
1777
1778         if (error) {
1779                 __i915_gpu_state_free(&error->ref);
1780                 return;
1781         }
1782
1783         if (!warned &&
1784             ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
1785                 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1786                 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1787                 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1788                 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1789                 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1790                          dev_priv->drm.primary->index);
1791                 warned = true;
1792         }
1793 }
1794
1795 struct i915_gpu_state *
1796 i915_first_error_state(struct drm_i915_private *i915)
1797 {
1798         struct i915_gpu_state *error;
1799
1800         spin_lock_irq(&i915->gpu_error.lock);
1801         error = i915->gpu_error.first_error;
1802         if (error)
1803                 i915_gpu_state_get(error);
1804         spin_unlock_irq(&i915->gpu_error.lock);
1805
1806         return error;
1807 }
1808
1809 void i915_reset_error_state(struct drm_i915_private *i915)
1810 {
1811         struct i915_gpu_state *error;
1812
1813         spin_lock_irq(&i915->gpu_error.lock);
1814         error = i915->gpu_error.first_error;
1815         i915->gpu_error.first_error = NULL;
1816         spin_unlock_irq(&i915->gpu_error.lock);
1817
1818         i915_gpu_state_put(error);
1819 }