drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34
  35 #include <linux/pm_qos.h>
  36
  37 #include <drm/ttm/ttm_device.h>
  38
  39 #include "display/intel_display.h"
  40 #include "display/intel_display_core.h"
  41
  42 #include "gem/i915_gem_context_types.h"
  43 #include "gem/i915_gem_shrinker.h"
  44 #include "gem/i915_gem_stolen.h"
  45
  46 #include "gt/intel_engine.h"
  47 #include "gt/intel_gt_types.h"
  48 #include "gt/intel_region_lmem.h"
  49 #include "gt/intel_workarounds.h"
  50 #include "gt/uc/intel_uc.h"
  51
  52 #include "i915_drm_client.h"
  53 #include "i915_gem.h"
  54 #include "i915_gpu_error.h"
  55 #include "i915_params.h"
  56 #include "i915_perf_types.h"
  57 #include "i915_scheduler.h"
  58 #include "i915_utils.h"
  59 #include "intel_device_info.h"
  60 #include "intel_memory_region.h"
  61 #include "intel_pch.h"
  62 #include "intel_runtime_pm.h"
  63 #include "intel_step.h"
  64 #include "intel_uncore.h"
  65
  66 struct drm_i915_clock_gating_funcs;
  67 struct drm_i915_gem_object;
  68 struct drm_i915_private;
  69 struct intel_connector;
  70 struct intel_dp;
  71 struct intel_encoder;
  72 struct intel_limit;
  73 struct intel_overlay_error_state;
  74 struct vlv_s0ix_state;
  75
  76 #define I915_GEM_GPU_DOMAINS \
  77         (I915_GEM_DOMAIN_RENDER | \
  78          I915_GEM_DOMAIN_SAMPLER | \
  79          I915_GEM_DOMAIN_COMMAND | \
  80          I915_GEM_DOMAIN_INSTRUCTION | \
  81          I915_GEM_DOMAIN_VERTEX)
  82
  83 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
  84
  85 #define GEM_QUIRK_PIN_SWIZZLED_PAGES    BIT(0)
  86
  87 struct i915_suspend_saved_registers {
  88         u32 saveDSPARB;
  89         u32 saveSWF0[16];
  90         u32 saveSWF1[16];
  91         u32 saveSWF3[3];
  92         u16 saveGCDGMBUS;
  93 };
  94
  95 #define MAX_L3_SLICES 2
  96 struct intel_l3_parity {
  97         u32 *remap_info[MAX_L3_SLICES];
  98         struct work_struct error_work;
  99         int which_slice;
 100 };
 101
 102 struct i915_gem_mm {
 103         /*
 104          * Shortcut for the stolen region. This points to either
 105          * INTEL_REGION_STOLEN_SMEM for integrated platforms, or
 106          * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
 107          * support stolen.
 108          */
 109         struct intel_memory_region *stolen_region;
 110         /** Memory allocator for GTT stolen memory */
 111         struct drm_mm stolen;
 112         /** Protects the usage of the GTT stolen memory allocator. This is
 113          * always the inner lock when overlapping with struct_mutex. */
 114         struct mutex stolen_lock;
 115
 116         /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
 117         spinlock_t obj_lock;
 118
 119         /**
 120          * List of objects which are purgeable.
 121          */
 122         struct list_head purge_list;
 123
 124         /**
 125          * List of objects which have allocated pages and are shrinkable.
 126          */
 127         struct list_head shrink_list;
 128
 129         /**
 130          * List of objects which are pending destruction.
 131          */
 132         struct llist_head free_list;
 133         struct work_struct free_work;
 134         /**
 135          * Count of objects pending destructions. Used to skip needlessly
 136          * waiting on an RCU barrier if no objects are waiting to be freed.
 137          */
 138         atomic_t free_count;
 139
 140         /**
 141          * tmpfs instance used for shmem backed objects
 142          */
 143         struct vfsmount *gemfs;
 144
 145         struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
 146
 147         struct notifier_block oom_notifier;
 148         struct notifier_block vmap_notifier;
 149         struct shrinker shrinker;
 150
 151 #ifdef CONFIG_MMU_NOTIFIER
 152         /**
 153          * notifier_lock for mmu notifiers, memory may not be allocated
 154          * while holding this lock.
 155          */
 156         rwlock_t notifier_lock;
 157 #endif
 158
 159         /* shrinker accounting, also useful for userland debugging */
 160         u64 shrink_memory;
 161         u32 shrink_count;
 162 };
 163
 164 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
 165
 166 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
 167                                          u64 context);
 168
 169 static inline unsigned long
 170 i915_fence_timeout(const struct drm_i915_private *i915)
 171 {
 172         return i915_fence_context_timeout(i915, U64_MAX);
 173 }
 174
 175 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
 176
 177 struct i915_virtual_gpu {
 178         struct mutex lock; /* serialises sending of g2v_notify command pkts */
 179         bool active;
 180         u32 caps;
 181         u32 *initial_mmio;
 182         u8 *initial_cfg_space;
 183         struct list_head entry;
 184 };
 185
 186 struct i915_selftest_stash {
 187         atomic_t counter;
 188         struct ida mock_region_instances;
 189 };
 190
 191 struct drm_i915_private {
 192         struct drm_device drm;
 193
 194         struct intel_display display;
 195
 196         /* FIXME: Device release actions should all be moved to drmm_ */
 197         bool do_release;
 198
 199         /* i915 device parameters */
 200         struct i915_params params;
 201
 202         const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
 203         struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
 204         struct intel_driver_caps caps;
 205
 206         /**
 207          * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
 208          * end of stolen which we can optionally use to create GEM objects
 209          * backed by stolen memory. Note that stolen_usable_size tells us
 210          * exactly how much of this we are actually allowed to use, given that
 211          * some portion of it is in fact reserved for use by hardware functions.
 212          */
 213         struct resource dsm;
 214         /**
 215          * Reseved portion of Data Stolen Memory
 216          */
 217         struct resource dsm_reserved;
 218
 219         /*
 220          * Stolen memory is segmented in hardware with different portions
 221          * offlimits to certain functions.
 222          *
 223          * The drm_mm is initialised to the total accessible range, as found
 224          * from the PCI config. On Broadwell+, this is further restricted to
 225          * avoid the first page! The upper end of stolen memory is reserved for
 226          * hardware functions and similarly removed from the accessible range.
 227          */
 228         resource_size_t stolen_usable_size;     /* Total size minus reserved ranges */
 229
 230         struct intel_uncore uncore;
 231         struct intel_uncore_mmio_debug mmio_debug;
 232
 233         struct i915_virtual_gpu vgpu;
 234
 235         struct intel_gvt *gvt;
 236
 237         struct pci_dev *bridge_dev;
 238
 239         struct rb_root uabi_engines;
 240         unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];
 241
 242         struct resource mch_res;
 243
 244         /* protects the irq masks */
 245         spinlock_t irq_lock;
 246
 247         bool display_irqs_enabled;
 248
 249         /* Sideband mailbox protection */
 250         struct mutex sb_lock;
 251         struct pm_qos_request sb_qos;
 252
 253         /** Cached value of IMR to avoid reads in updating the bitfield */
 254         union {
 255                 u32 irq_mask;
 256                 u32 de_irq_mask[I915_MAX_PIPES];
 257         };
 258         u32 pipestat_irq_mask[I915_MAX_PIPES];
 259
 260         bool preserve_bios_swizzle;
 261
 262         unsigned int fsb_freq, mem_freq, is_ddr3;
 263         unsigned int skl_preferred_vco_freq;
 264
 265         unsigned int max_dotclk_freq;
 266         unsigned int hpll_freq;
 267         unsigned int czclk_freq;
 268
 269         /**
 270          * wq - Driver workqueue for GEM.
 271          *
 272          * NOTE: Work items scheduled here are not allowed to grab any modeset
 273          * locks, for otherwise the flushing done in the pageflip code will
 274          * result in deadlocks.
 275          */
 276         struct workqueue_struct *wq;
 277
 278         /* pm private clock gating functions */
 279         const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
 280
 281         /* PCH chipset type */
 282         enum intel_pch pch_type;
 283         unsigned short pch_id;
 284
 285         unsigned long gem_quirks;
 286
 287         struct i915_gem_mm mm;
 288
 289         bool mchbar_need_disable;
 290
 291         struct intel_l3_parity l3_parity;
 292
 293         /*
 294          * edram size in MB.
 295          * Cannot be determined by PCIID. You must always read a register.
 296          */
 297         u32 edram_size_mb;
 298
 299         struct i915_gpu_error gpu_error;
 300
 301         /*
 302          * Shadows for CHV DPLL_MD regs to keep the state
 303          * checker somewhat working in the presence hardware
 304          * crappiness (can't read out DPLL_MD for pipes B & C).
 305          */
 306         u32 chv_dpll_md[I915_MAX_PIPES];
 307         u32 bxt_phy_grc;
 308
 309         u32 suspend_count;
 310         struct i915_suspend_saved_registers regfile;
 311         struct vlv_s0ix_state *vlv_s0ix_state;
 312
 313         struct dram_info {
 314                 bool wm_lv_0_adjust_needed;
 315                 u8 num_channels;
 316                 bool symmetric_memory;
 317                 enum intel_dram_type {
 318                         INTEL_DRAM_UNKNOWN,
 319                         INTEL_DRAM_DDR3,
 320                         INTEL_DRAM_DDR4,
 321                         INTEL_DRAM_LPDDR3,
 322                         INTEL_DRAM_LPDDR4,
 323                         INTEL_DRAM_DDR5,
 324                         INTEL_DRAM_LPDDR5,
 325                 } type;
 326                 u8 num_qgv_points;
 327                 u8 num_psf_gv_points;
 328         } dram_info;
 329
 330         struct intel_runtime_pm runtime_pm;
 331
 332         struct i915_perf perf;
 333
 334         struct i915_hwmon *hwmon;
 335
 336         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
 337         struct intel_gt gt0;
 338
 339         /*
 340          * i915->gt[0] == &i915->gt0
 341          */
 342 #define I915_MAX_GT 4
 343         struct intel_gt *gt[I915_MAX_GT];
 344
 345         struct kobject *sysfs_gt;
 346
 347         /* Quick lookup of media GT (current platforms only have one) */
 348         struct intel_gt *media_gt;
 349
 350         struct {
 351                 struct i915_gem_contexts {
 352                         spinlock_t lock; /* locks list */
 353                         struct list_head list;
 354                 } contexts;
 355
 356                 /*
 357                  * We replace the local file with a global mappings as the
 358                  * backing storage for the mmap is on the device and not
 359                  * on the struct file, and we do not want to prolong the
 360                  * lifetime of the local fd. To minimise the number of
 361                  * anonymous inodes we create, we use a global singleton to
 362                  * share the global mapping.
 363                  */
 364                 struct file *mmap_singleton;
 365         } gem;
 366
 367         u8 pch_ssc_use;
 368
 369         /* For i915gm/i945gm vblank irq workaround */
 370         u8 vblank_enabled;
 371
 372         bool irq_enabled;
 373
 374         /*
 375          * DG2: Mask of PHYs that were not calibrated by the firmware
 376          * and should not be used.
 377          */
 378         u8 snps_phy_failed_calibration;
 379
 380         struct i915_pmu pmu;
 381
 382         struct i915_drm_clients clients;
 383
 384         /* The TTM device structure. */
 385         struct ttm_device bdev;
 386
 387         I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
 388
 389         /*
 390          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
 391          * will be rejected. Instead look for a better place.
 392          */
 393 };
 394
 395 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
 396 {
 397         return container_of(dev, struct drm_i915_private, drm);
 398 }
 399
 400 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
 401 {
 402         return dev_get_drvdata(kdev);
 403 }
 404
 405 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
 406 {
 407         return pci_get_drvdata(pdev);
 408 }
 409
 410 static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
 411 {
 412         return &i915->gt0;
 413 }
 414
 415 /* Simple iterator over all initialised engines */
 416 #define for_each_engine(engine__, dev_priv__, id__) \
 417         for ((id__) = 0; \
 418              (id__) < I915_NUM_ENGINES; \
 419              (id__)++) \
 420                 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
 421
 422 /* Iterator over subset of engines selected by mask */
 423 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
 424         for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
 425              (tmp__) ? \
 426              ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
 427              0;)
 428
 429 #define rb_to_uabi_engine(rb) \
 430         rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
 431
 432 #define for_each_uabi_engine(engine__, i915__) \
 433         for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
 434              (engine__); \
 435              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
 436
 437 #define for_each_uabi_class_engine(engine__, class__, i915__) \
 438         for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
 439              (engine__) && (engine__)->uabi_class == (class__); \
 440              (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
 441
 442 #define INTEL_INFO(dev_priv)    (&(dev_priv)->__info)
 443 #define RUNTIME_INFO(dev_priv)  (&(dev_priv)->__runtime)
 444 #define DRIVER_CAPS(dev_priv)   (&(dev_priv)->caps)
 445
 446 #define INTEL_DEVID(dev_priv)   (RUNTIME_INFO(dev_priv)->device_id)
 447
 448 #define IP_VER(ver, rel)                ((ver) << 8 | (rel))
 449
 450 #define GRAPHICS_VER(i915)              (RUNTIME_INFO(i915)->graphics.ip.ver)
 451 #define GRAPHICS_VER_FULL(i915)         IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
 452                                                RUNTIME_INFO(i915)->graphics.ip.rel)
 453 #define IS_GRAPHICS_VER(i915, from, until) \
 454         (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
 455
 456 #define MEDIA_VER(i915)                 (RUNTIME_INFO(i915)->media.ip.ver)
 457 #define MEDIA_VER_FULL(i915)            IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
 458                                                RUNTIME_INFO(i915)->media.ip.rel)
 459 #define IS_MEDIA_VER(i915, from, until) \
 460         (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
 461
 462 #define DISPLAY_VER(i915)       (RUNTIME_INFO(i915)->display.ip.ver)
 463 #define IS_DISPLAY_VER(i915, from, until) \
 464         (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
 465
 466 #define INTEL_REVID(dev_priv)   (to_pci_dev((dev_priv)->drm.dev)->revision)
 467
 468 #define HAS_DSB(dev_priv)       (INTEL_INFO(dev_priv)->display.has_dsb)
 469
 470 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
 471 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
 472 #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
 473 #define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step)
 474
 475 #define IS_DISPLAY_STEP(__i915, since, until) \
 476         (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
 477          INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
 478
 479 #define IS_GRAPHICS_STEP(__i915, since, until) \
 480         (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \
 481          INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until))
 482
 483 #define IS_MEDIA_STEP(__i915, since, until) \
 484         (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
 485          INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until))
 486
 487 #define IS_BASEDIE_STEP(__i915, since, until) \
 488         (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \
 489          INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until))
 490
 491 static __always_inline unsigned int
 492 __platform_mask_index(const struct intel_runtime_info *info,
 493                       enum intel_platform p)
 494 {
 495         const unsigned int pbits =
 496                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
 497
 498         /* Expand the platform_mask array if this fails. */
 499         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
 500                      pbits * ARRAY_SIZE(info->platform_mask));
 501
 502         return p / pbits;
 503 }
 504
 505 static __always_inline unsigned int
 506 __platform_mask_bit(const struct intel_runtime_info *info,
 507                     enum intel_platform p)
 508 {
 509         const unsigned int pbits =
 510                 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
 511
 512         return p % pbits + INTEL_SUBPLATFORM_BITS;
 513 }
 514
 515 static inline u32
 516 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
 517 {
 518         const unsigned int pi = __platform_mask_index(info, p);
 519
 520         return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
 521 }
 522
 523 static __always_inline bool
 524 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
 525 {
 526         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
 527         const unsigned int pi = __platform_mask_index(info, p);
 528         const unsigned int pb = __platform_mask_bit(info, p);
 529
 530         BUILD_BUG_ON(!__builtin_constant_p(p));
 531
 532         return info->platform_mask[pi] & BIT(pb);
 533 }
 534
 535 static __always_inline bool
 536 IS_SUBPLATFORM(const struct drm_i915_private *i915,
 537                enum intel_platform p, unsigned int s)
 538 {
 539         const struct intel_runtime_info *info = RUNTIME_INFO(i915);
 540         const unsigned int pi = __platform_mask_index(info, p);
 541         const unsigned int pb = __platform_mask_bit(info, p);
 542         const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
 543         const u32 mask = info->platform_mask[pi];
 544
 545         BUILD_BUG_ON(!__builtin_constant_p(p));
 546         BUILD_BUG_ON(!__builtin_constant_p(s));
 547         BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
 548
 549         /* Shift and test on the MSB position so sign flag can be used. */
 550         return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
 551 }
 552
 553 #define IS_MOBILE(dev_priv)     (INTEL_INFO(dev_priv)->is_mobile)
 554 #define IS_DGFX(dev_priv)   (INTEL_INFO(dev_priv)->is_dgfx)
 555
 556 #define IS_I830(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I830)
 557 #define IS_I845G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I845G)
 558 #define IS_I85X(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I85X)
 559 #define IS_I865G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I865G)
 560 #define IS_I915G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I915G)
 561 #define IS_I915GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I915GM)
 562 #define IS_I945G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I945G)
 563 #define IS_I945GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I945GM)
 564 #define IS_I965G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I965G)
 565 #define IS_I965GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I965GM)
 566 #define IS_G45(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G45)
 567 #define IS_GM45(dev_priv)       IS_PLATFORM(dev_priv, INTEL_GM45)
 568 #define IS_G4X(dev_priv)        (IS_G45(dev_priv) || IS_GM45(dev_priv))
 569 #define IS_PINEVIEW(dev_priv)   IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
 570 #define IS_G33(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G33)
 571 #define IS_IRONLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
 572 #define IS_IRONLAKE_M(dev_priv) \
 573         (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
 574 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
 575 #define IS_IVYBRIDGE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
 576 #define IS_IVB_GT1(dev_priv)    (IS_IVYBRIDGE(dev_priv) && \
 577                                  INTEL_INFO(dev_priv)->gt == 1)
 578 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
 579 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
 580 #define IS_HASWELL(dev_priv)    IS_PLATFORM(dev_priv, INTEL_HASWELL)
 581 #define IS_BROADWELL(dev_priv)  IS_PLATFORM(dev_priv, INTEL_BROADWELL)
 582 #define IS_SKYLAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
 583 #define IS_BROXTON(dev_priv)    IS_PLATFORM(dev_priv, INTEL_BROXTON)
 584 #define IS_KABYLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
 585 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
 586 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
 587 #define IS_COMETLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
 588 #define IS_ICELAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_ICELAKE)
 589 #define IS_JSL_EHL(dev_priv)    (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
 590                                 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
 591 #define IS_TIGERLAKE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
 592 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
 593 #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
 594 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
 595 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
 596 #define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
 597 #define IS_DG2(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG2)
 598 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
 599 #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)
 600
 601 #define IS_METEORLAKE_M(dev_priv) \
 602         IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
 603 #define IS_METEORLAKE_P(dev_priv) \
 604         IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
 605 #define IS_DG2_G10(dev_priv) \
 606         IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
 607 #define IS_DG2_G11(dev_priv) \
 608         IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
 609 #define IS_DG2_G12(dev_priv) \
 610         IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
 611 #define IS_ADLS_RPLS(dev_priv) \
 612         IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 613 #define IS_ADLP_N(dev_priv) \
 614         IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
 615 #define IS_ADLP_RPLP(dev_priv) \
 616         IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
 617 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 618                                     (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
 619 #define IS_BDW_ULT(dev_priv) \
 620         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
 621 #define IS_BDW_ULX(dev_priv) \
 622         IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
 623 #define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
 624                                  INTEL_INFO(dev_priv)->gt == 3)
 625 #define IS_HSW_ULT(dev_priv) \
 626         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
 627 #define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
 628                                  INTEL_INFO(dev_priv)->gt == 3)
 629 #define IS_HSW_GT1(dev_priv)    (IS_HASWELL(dev_priv) && \
 630                                  INTEL_INFO(dev_priv)->gt == 1)
 631 /* ULX machines are also considered ULT. */
 632 #define IS_HSW_ULX(dev_priv) \
 633         IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
 634 #define IS_SKL_ULT(dev_priv) \
 635         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
 636 #define IS_SKL_ULX(dev_priv) \
 637         IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
 638 #define IS_KBL_ULT(dev_priv) \
 639         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
 640 #define IS_KBL_ULX(dev_priv) \
 641         IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
 642 #define IS_SKL_GT2(dev_priv)    (IS_SKYLAKE(dev_priv) && \
 643                                  INTEL_INFO(dev_priv)->gt == 2)
 644 #define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
 645                                  INTEL_INFO(dev_priv)->gt == 3)
 646 #define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
 647                                  INTEL_INFO(dev_priv)->gt == 4)
 648 #define IS_KBL_GT2(dev_priv)    (IS_KABYLAKE(dev_priv) && \
 649                                  INTEL_INFO(dev_priv)->gt == 2)
 650 #define IS_KBL_GT3(dev_priv)    (IS_KABYLAKE(dev_priv) && \
 651                                  INTEL_INFO(dev_priv)->gt == 3)
 652 #define IS_CFL_ULT(dev_priv) \
 653         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
 654 #define IS_CFL_ULX(dev_priv) \
 655         IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
 656 #define IS_CFL_GT2(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
 657                                  INTEL_INFO(dev_priv)->gt == 2)
 658 #define IS_CFL_GT3(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
 659                                  INTEL_INFO(dev_priv)->gt == 3)
 660
 661 #define IS_CML_ULT(dev_priv) \
 662         IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
 663 #define IS_CML_ULX(dev_priv) \
 664         IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
 665 #define IS_CML_GT2(dev_priv)    (IS_COMETLAKE(dev_priv) && \
 666                                  INTEL_INFO(dev_priv)->gt == 2)
 667
 668 #define IS_ICL_WITH_PORT_F(dev_priv) \
 669         IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
 670
 671 #define IS_TGL_UY(dev_priv) \
 672         IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
 673
 674 #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
 675
 676 #define IS_KBL_GRAPHICS_STEP(dev_priv, since, until) \
 677         (IS_KABYLAKE(dev_priv) && IS_GRAPHICS_STEP(dev_priv, since, until))
 678 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
 679         (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
 680
 681 #define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \
 682         (IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
 683 #define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
 684         (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
 685
 686 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
 687         (IS_TIGERLAKE(__i915) && \
 688          IS_DISPLAY_STEP(__i915, since, until))
 689
 690 #define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until) \
 691         (IS_TGL_UY(__i915) && \
 692          IS_GRAPHICS_STEP(__i915, since, until))
 693
 694 #define IS_TGL_GRAPHICS_STEP(__i915, since, until) \
 695         (IS_TIGERLAKE(__i915) && !IS_TGL_UY(__i915)) && \
 696          IS_GRAPHICS_STEP(__i915, since, until))
 697
 698 #define IS_RKL_DISPLAY_STEP(p, since, until) \
 699         (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
 700
 701 #define IS_DG1_GRAPHICS_STEP(p, since, until) \
 702         (IS_DG1(p) && IS_GRAPHICS_STEP(p, since, until))
 703 #define IS_DG1_DISPLAY_STEP(p, since, until) \
 704         (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
 705
 706 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
 707         (IS_ALDERLAKE_S(__i915) && \
 708          IS_DISPLAY_STEP(__i915, since, until))
 709
 710 #define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \
 711         (IS_ALDERLAKE_S(__i915) && \
 712          IS_GRAPHICS_STEP(__i915, since, until))
 713
 714 #define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
 715         (IS_ALDERLAKE_P(__i915) && \
 716          IS_DISPLAY_STEP(__i915, since, until))
 717
 718 #define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \
 719         (IS_ALDERLAKE_P(__i915) && \
 720          IS_GRAPHICS_STEP(__i915, since, until))
 721
 722 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
 723         (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
 724
 725 #define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
 726         (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
 727          IS_GRAPHICS_STEP(__i915, since, until))
 728
 729 /*
 730  * DG2 hardware steppings are a bit unusual.  The hardware design was forked to
 731  * create three variants (G10, G11, and G12) which each have distinct
 732  * workaround sets.  The G11 and G12 forks of the DG2 design reset the GT
 733  * stepping back to "A0" for their first iterations, even though they're more
 734  * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of
 735  * functionality and workarounds.  However the display stepping does not reset
 736  * in the same manner --- a specific stepping like "B0" has a consistent
 737  * meaning regardless of whether it belongs to a G10, G11, or G12 DG2.
 738  *
 739  * TLDR:  All GT workarounds and stepping-specific logic must be applied in
 740  * relation to a specific subplatform (G10/G11/G12), whereas display workarounds
 741  * and stepping-specific logic will be applied with a general DG2-wide stepping
 742  * number.
 743  */
 744 #define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \
 745         (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
 746          IS_GRAPHICS_STEP(__i915, since, until))
 747
 748 #define IS_DG2_DISPLAY_STEP(__i915, since, until) \
 749         (IS_DG2(__i915) && \
 750          IS_DISPLAY_STEP(__i915, since, until))
 751
 752 #define IS_PVC_BD_STEP(__i915, since, until) \
 753         (IS_PONTEVECCHIO(__i915) && \
 754          IS_BASEDIE_STEP(__i915, since, until))
 755
 756 #define IS_PVC_CT_STEP(__i915, since, until) \
 757         (IS_PONTEVECCHIO(__i915) && \
 758          IS_GRAPHICS_STEP(__i915, since, until))
 759
 760 #define IS_LP(dev_priv)         (INTEL_INFO(dev_priv)->is_lp)
 761 #define IS_GEN9_LP(dev_priv)    (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
 762 #define IS_GEN9_BC(dev_priv)    (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
 763
 764 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
 765 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
 766
 767 #define __ENGINE_INSTANCES_MASK(mask, first, count) ({                  \
 768         unsigned int first__ = (first);                                 \
 769         unsigned int count__ = (count);                                 \
 770         ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__;  \
 771 })
 772
 773 #define ENGINE_INSTANCES_MASK(gt, first, count) \
 774         __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
 775
 776 #define RCS_MASK(gt) \
 777         ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
 778 #define BCS_MASK(gt) \
 779         ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
 780 #define VDBOX_MASK(gt) \
 781         ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
 782 #define VEBOX_MASK(gt) \
 783         ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
 784 #define CCS_MASK(gt) \
 785         ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
 786
 787 #define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode)
 788
 789 /*
 790  * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
 791  * All later gens can run the final buffer from the ppgtt
 792  */
 793 #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
 794
 795 #define HAS_LLC(dev_priv)       (INTEL_INFO(dev_priv)->has_llc)
 796 #define HAS_4TILE(dev_priv)     (INTEL_INFO(dev_priv)->has_4tile)
 797 #define HAS_SNOOP(dev_priv)     (INTEL_INFO(dev_priv)->has_snoop)
 798 #define HAS_EDRAM(dev_priv)     ((dev_priv)->edram_size_mb)
 799 #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
 800 #define HAS_WT(dev_priv)        HAS_EDRAM(dev_priv)
 801
 802 #define HWS_NEEDS_PHYSICAL(dev_priv)    (INTEL_INFO(dev_priv)->hws_needs_physical)
 803
 804 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
 805                 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
 806 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
 807                 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
 808
 809 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
 810
 811 #define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type)
 812 #define HAS_PPGTT(dev_priv) \
 813         (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
 814 #define HAS_FULL_PPGTT(dev_priv) \
 815         (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
 816
 817 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 818         GEM_BUG_ON((sizes) == 0); \
 819         ((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \
 820 })
 821
 822 #define HAS_OVERLAY(dev_priv)            (INTEL_INFO(dev_priv)->display.has_overlay)
 823 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
 824                 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
 825
 826 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
 827 #define HAS_BROKEN_CS_TLB(dev_priv)     (IS_I830(dev_priv) || IS_I845G(dev_priv))
 828
 829 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)   \
 830         (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
 831
 832 /* WaRsDisableCoarsePowerGating:skl,cnl */
 833 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)                    \
 834         (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
 835
 836 #define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4)
 837 #define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \
 838                                         IS_GEMINILAKE(dev_priv) || \
 839                                         IS_KABYLAKE(dev_priv))
 840
 841 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 842  * rows, which changed the alignment requirements and fence programming.
 843  */
 844 #define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
 845                                          !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
 846 #define SUPPORTS_TV(dev_priv)           (INTEL_INFO(dev_priv)->display.supports_tv)
 847 #define I915_HAS_HOTPLUG(dev_priv)      (INTEL_INFO(dev_priv)->display.has_hotplug)
 848
 849 #define HAS_FW_BLC(dev_priv)    (DISPLAY_VER(dev_priv) > 2)
 850 #define HAS_FBC(dev_priv)       (RUNTIME_INFO(dev_priv)->fbc_mask != 0)
 851 #define HAS_CUR_FBC(dev_priv)   (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7)
 852
 853 #define HAS_IPS(dev_priv)       (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
 854
 855 #define HAS_DP_MST(dev_priv)    (INTEL_INFO(dev_priv)->display.has_dp_mst)
 856 #define HAS_DP20(dev_priv)      (IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
 857
 858 #define HAS_DOUBLE_BUFFERED_M_N(dev_priv)       (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
 859
 860 #define HAS_CDCLK_CRAWL(dev_priv)        (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
 861 #define HAS_CDCLK_SQUASH(dev_priv)       (INTEL_INFO(dev_priv)->display.has_cdclk_squash)
 862 #define HAS_DDI(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ddi)
 863 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
 864 #define HAS_PSR(dev_priv)                (INTEL_INFO(dev_priv)->display.has_psr)
 865 #define HAS_PSR_HW_TRACKING(dev_priv) \
 866         (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
 867 #define HAS_PSR2_SEL_FETCH(dev_priv)     (DISPLAY_VER(dev_priv) >= 12)
 868 #define HAS_TRANSCODER(dev_priv, trans)  ((RUNTIME_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
 869
 870 #define HAS_RC6(dev_priv)                (INTEL_INFO(dev_priv)->has_rc6)
 871 #define HAS_RC6p(dev_priv)               (INTEL_INFO(dev_priv)->has_rc6p)
 872 #define HAS_RC6pp(dev_priv)              (false) /* HW was never validated */
 873
 874 #define HAS_RPS(dev_priv)       (INTEL_INFO(dev_priv)->has_rps)
 875
 876 #define HAS_DMC(dev_priv)       (RUNTIME_INFO(dev_priv)->has_dmc)
 877
 878 #define HAS_HECI_PXP(dev_priv) \
 879         (INTEL_INFO(dev_priv)->has_heci_pxp)
 880
 881 #define HAS_HECI_GSCFI(dev_priv) \
 882         (INTEL_INFO(dev_priv)->has_heci_gscfi)
 883
 884 #define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv))
 885
 886 #define HAS_MSO(i915)           (DISPLAY_VER(i915) >= 12)
 887
 888 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
 889 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
 890
 891 #define HAS_OA_BPC_REPORTING(dev_priv) \
 892         (INTEL_INFO(dev_priv)->has_oa_bpc_reporting)
 893 #define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \
 894         (INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits)
 895
 896 /*
 897  * Set this flag, when platform requires 64K GTT page sizes or larger for
 898  * device local memory access.
 899  */
 900 #define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
 901
 902 #define HAS_IPC(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ipc)
 903
 904 #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
 905 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
 906
 907 #define HAS_EXTRA_GT_LIST(dev_priv)   (INTEL_INFO(dev_priv)->extra_gt_list)
 908
 909 /*
 910  * Platform has the dedicated compression control state for each lmem surfaces
 911  * stored in lmem to support the 3D and media compression formats.
 912  */
 913 #define HAS_FLAT_CCS(dev_priv)   (INTEL_INFO(dev_priv)->has_flat_ccs)
 914
 915 #define HAS_GT_UC(dev_priv)     (INTEL_INFO(dev_priv)->has_gt_uc)
 916
 917 #define HAS_POOLED_EU(dev_priv) (RUNTIME_INFO(dev_priv)->has_pooled_eu)
 918
 919 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)     (INTEL_INFO(dev_priv)->has_global_mocs)
 920
 921 #define HAS_PXP(dev_priv)  ((IS_ENABLED(CONFIG_DRM_I915_PXP) && \
 922                             INTEL_INFO(dev_priv)->has_pxp) && \
 923                             VDBOX_MASK(to_gt(dev_priv)))
 924
 925 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
 926
 927 #define HAS_GMD_ID(i915)        (INTEL_INFO(i915)->has_gmd_id)
 928
 929 #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
 930
 931 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
 932
 933 /* DPF == dynamic parity feature */
 934 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
 935 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
 936                                  2 : HAS_L3_DPF(dev_priv))
 937
 938 #define GT_FREQUENCY_MULTIPLIER 50
 939 #define GEN9_FREQ_SCALER 3
 940
 941 #define INTEL_NUM_PIPES(dev_priv) (hweight8(RUNTIME_INFO(dev_priv)->pipe_mask))
 942
 943 #define HAS_DISPLAY(dev_priv) (RUNTIME_INFO(dev_priv)->pipe_mask != 0)
 944
 945 #define HAS_VRR(i915)   (DISPLAY_VER(i915) >= 11)
 946
 947 #define HAS_ASYNC_FLIPS(i915)           (DISPLAY_VER(i915) >= 5)
 948
 949 /* Only valid when HAS_DISPLAY() is true */
 950 #define INTEL_DISPLAY_ENABLED(dev_priv) \
 951         (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)),         \
 952          !(dev_priv)->params.disable_display &&                         \
 953          !intel_opregion_headless_sku(dev_priv))
 954
 955 #define HAS_GUC_DEPRIVILEGE(dev_priv) \
 956         (INTEL_INFO(dev_priv)->has_guc_deprivilege)
 957
 958 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
 959                                               IS_ALDERLAKE_S(dev_priv))
 960
 961 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
 962
 963 #define HAS_3D_PIPELINE(i915)   (INTEL_INFO(i915)->has_3d_pipeline)
 964
 965 #define HAS_ONE_EU_PER_FUSE_BIT(i915)   (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
 966
 967 #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
 968                                        GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
 969
 970 /* intel_device_info.c */
 971 static inline struct intel_device_info *
 972 mkwrite_device_info(struct drm_i915_private *dev_priv)
 973 {
 974         return (struct intel_device_info *)INTEL_INFO(dev_priv);
 975 }
 976
 977 #endif