drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_atomic_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "i915_drv.h"
  50 #include "i915_trace.h"
  51 #include "i915_pmu.h"
  52 #include "i915_query.h"
  53 #include "i915_vgpu.h"
  54 #include "intel_drv.h"
  55 #include "intel_uc.h"
  56
  57 static struct drm_driver driver;
  58
  59 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
  60 static unsigned int i915_load_fail_count;
  61
  62 bool __i915_inject_load_failure(const char *func, int line)
  63 {
  64         if (i915_load_fail_count >= i915_modparams.inject_load_failure)
  65                 return false;
  66
  67         if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
  68                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  69                          i915_modparams.inject_load_failure, func, line);
  70                 i915_modparams.inject_load_failure = 0;
  71                 return true;
  72         }
  73
  74         return false;
  75 }
  76 #endif
  77
  78 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  79 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  80                     "providing the dmesg log by booting with drm.debug=0xf"
  81
  82 void
  83 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  84               const char *fmt, ...)
  85 {
  86         static bool shown_bug_once;
  87         struct device *kdev = dev_priv->drm.dev;
  88         bool is_error = level[1] <= KERN_ERR[1];
  89         bool is_debug = level[1] == KERN_DEBUG[1];
  90         struct va_format vaf;
  91         va_list args;
  92
  93         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  94                 return;
  95
  96         va_start(args, fmt);
  97
  98         vaf.fmt = fmt;
  99         vaf.va = &args;
 100
 101         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
 102                    __builtin_return_address(0), &vaf);
 103
 104         if (is_error && !shown_bug_once) {
 105                 /*
 106                  * Ask the user to file a bug report for the error, except
 107                  * if they may have caused the bug by fiddling with unsafe
 108                  * module parameters.
 109                  */
 110                 if (!test_taint(TAINT_USER))
 111                         dev_notice(kdev, "%s", FDO_BUG_MSG);
 112                 shown_bug_once = true;
 113         }
 114
 115         va_end(args);
 116 }
 117
 118 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 119 {
 120 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
 121         return i915_load_fail_count && !i915_modparams.inject_load_failure;
 122 #else
 123         return false;
 124 #endif
 125 }
 126
 127 #define i915_load_error(i915, fmt, ...)                                  \
 128         __i915_printk(i915,                                              \
 129                       i915_error_injected(i915) ? KERN_DEBUG : KERN_ERR, \
 130                       fmt, ##__VA_ARGS__)
 131
 132 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
 133 static enum intel_pch
 134 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 135 {
 136         switch (id) {
 137         case INTEL_PCH_IBX_DEVICE_ID_TYPE:
 138                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 139                 WARN_ON(!IS_GEN5(dev_priv));
 140                 return PCH_IBX;
 141         case INTEL_PCH_CPT_DEVICE_ID_TYPE:
 142                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 143                 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
 144                 return PCH_CPT;
 145         case INTEL_PCH_PPT_DEVICE_ID_TYPE:
 146                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 147                 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
 148                 /* PantherPoint is CPT compatible */
 149                 return PCH_CPT;
 150         case INTEL_PCH_LPT_DEVICE_ID_TYPE:
 151                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 152                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 153                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 154                 return PCH_LPT;
 155         case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
 156                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 157                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 158                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 159                 return PCH_LPT;
 160         case INTEL_PCH_WPT_DEVICE_ID_TYPE:
 161                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
 162                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 163                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 164                 /* WildcatPoint is LPT compatible */
 165                 return PCH_LPT;
 166         case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
 167                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
 168                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 169                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 170                 /* WildcatPoint is LPT compatible */
 171                 return PCH_LPT;
 172         case INTEL_PCH_SPT_DEVICE_ID_TYPE:
 173                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 174                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 175                 return PCH_SPT;
 176         case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
 177                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 178                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 179                 return PCH_SPT;
 180         case INTEL_PCH_KBP_DEVICE_ID_TYPE:
 181                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
 182                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
 183                         !IS_COFFEELAKE(dev_priv));
 184                 return PCH_KBP;
 185         case INTEL_PCH_CNP_DEVICE_ID_TYPE:
 186                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
 187                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 188                 return PCH_CNP;
 189         case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
 190                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
 191                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 192                 return PCH_CNP;
 193         case INTEL_PCH_ICP_DEVICE_ID_TYPE:
 194                 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
 195                 WARN_ON(!IS_ICELAKE(dev_priv));
 196                 return PCH_ICP;
 197         default:
 198                 return PCH_NONE;
 199         }
 200 }
 201
 202 static bool intel_is_virt_pch(unsigned short id,
 203                               unsigned short svendor, unsigned short sdevice)
 204 {
 205         return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
 206                 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
 207                 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
 208                  svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 209                  sdevice == PCI_SUBDEVICE_ID_QEMU));
 210 }
 211
 212 static unsigned short
 213 intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
 214 {
 215         unsigned short id = 0;
 216
 217         /*
 218          * In a virtualized passthrough environment we can be in a
 219          * setup where the ISA bridge is not able to be passed through.
 220          * In this case, a south bridge can be emulated and we have to
 221          * make an educated guess as to which PCH is really there.
 222          */
 223
 224         if (IS_GEN5(dev_priv))
 225                 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
 226         else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
 227                 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
 228         else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
 229                 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 230         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 231                 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
 232         else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 233                 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
 234         else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
 235                 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
 236         else if (IS_ICELAKE(dev_priv))
 237                 id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
 238
 239         if (id)
 240                 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
 241         else
 242                 DRM_DEBUG_KMS("Assuming no PCH\n");
 243
 244         return id;
 245 }
 246
 247 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 248 {
 249         struct pci_dev *pch = NULL;
 250
 251         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 252          * (which really amounts to a PCH but no South Display).
 253          */
 254         if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 255                 dev_priv->pch_type = PCH_NOP;
 256                 return;
 257         }
 258
 259         /*
 260          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 261          * make graphics device passthrough work easy for VMM, that only
 262          * need to expose ISA bridge to let driver know the real hardware
 263          * underneath. This is a requirement from virtualization team.
 264          *
 265          * In some virtualized environments (e.g. XEN), there is irrelevant
 266          * ISA bridge in the system. To work reliably, we should scan trhough
 267          * all the ISA bridge devices and check for the first match, instead
 268          * of only checking the first one.
 269          */
 270         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 271                 unsigned short id;
 272                 enum intel_pch pch_type;
 273
 274                 if (pch->vendor != PCI_VENDOR_ID_INTEL)
 275                         continue;
 276
 277                 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 278
 279                 pch_type = intel_pch_type(dev_priv, id);
 280                 if (pch_type != PCH_NONE) {
 281                         dev_priv->pch_type = pch_type;
 282                         dev_priv->pch_id = id;
 283                         break;
 284                 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
 285                                          pch->subsystem_device)) {
 286                         id = intel_virt_detect_pch(dev_priv);
 287                         if (id) {
 288                                 pch_type = intel_pch_type(dev_priv, id);
 289                                 if (WARN_ON(pch_type == PCH_NONE))
 290                                         pch_type = PCH_NOP;
 291                         } else {
 292                                 pch_type = PCH_NONE;
 293                         }
 294                         dev_priv->pch_type = pch_type;
 295                         dev_priv->pch_id = id;
 296                         break;
 297                 }
 298         }
 299         if (!pch)
 300                 DRM_DEBUG_KMS("No PCH found.\n");
 301
 302         pci_dev_put(pch);
 303 }
 304
 305 static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 306                                struct drm_file *file_priv)
 307 {
 308         struct drm_i915_private *dev_priv = to_i915(dev);
 309         struct pci_dev *pdev = dev_priv->drm.pdev;
 310         drm_i915_getparam_t *param = data;
 311         int value;
 312
 313         switch (param->param) {
 314         case I915_PARAM_IRQ_ACTIVE:
 315         case I915_PARAM_ALLOW_BATCHBUFFER:
 316         case I915_PARAM_LAST_DISPATCH:
 317         case I915_PARAM_HAS_EXEC_CONSTANTS:
 318                 /* Reject all old ums/dri params. */
 319                 return -ENODEV;
 320         case I915_PARAM_CHIPSET_ID:
 321                 value = pdev->device;
 322                 break;
 323         case I915_PARAM_REVISION:
 324                 value = pdev->revision;
 325                 break;
 326         case I915_PARAM_NUM_FENCES_AVAIL:
 327                 value = dev_priv->num_fence_regs;
 328                 break;
 329         case I915_PARAM_HAS_OVERLAY:
 330                 value = dev_priv->overlay ? 1 : 0;
 331                 break;
 332         case I915_PARAM_HAS_BSD:
 333                 value = !!dev_priv->engine[VCS];
 334                 break;
 335         case I915_PARAM_HAS_BLT:
 336                 value = !!dev_priv->engine[BCS];
 337                 break;
 338         case I915_PARAM_HAS_VEBOX:
 339                 value = !!dev_priv->engine[VECS];
 340                 break;
 341         case I915_PARAM_HAS_BSD2:
 342                 value = !!dev_priv->engine[VCS2];
 343                 break;
 344         case I915_PARAM_HAS_LLC:
 345                 value = HAS_LLC(dev_priv);
 346                 break;
 347         case I915_PARAM_HAS_WT:
 348                 value = HAS_WT(dev_priv);
 349                 break;
 350         case I915_PARAM_HAS_ALIASING_PPGTT:
 351                 value = USES_PPGTT(dev_priv);
 352                 break;
 353         case I915_PARAM_HAS_SEMAPHORES:
 354                 value = HAS_LEGACY_SEMAPHORES(dev_priv);
 355                 break;
 356         case I915_PARAM_HAS_SECURE_BATCHES:
 357                 value = capable(CAP_SYS_ADMIN);
 358                 break;
 359         case I915_PARAM_CMD_PARSER_VERSION:
 360                 value = i915_cmd_parser_get_version(dev_priv);
 361                 break;
 362         case I915_PARAM_SUBSLICE_TOTAL:
 363                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 364                 if (!value)
 365                         return -ENODEV;
 366                 break;
 367         case I915_PARAM_EU_TOTAL:
 368                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 369                 if (!value)
 370                         return -ENODEV;
 371                 break;
 372         case I915_PARAM_HAS_GPU_RESET:
 373                 value = i915_modparams.enable_hangcheck &&
 374                         intel_has_gpu_reset(dev_priv);
 375                 if (value && intel_has_reset_engine(dev_priv))
 376                         value = 2;
 377                 break;
 378         case I915_PARAM_HAS_RESOURCE_STREAMER:
 379                 value = HAS_RESOURCE_STREAMER(dev_priv);
 380                 break;
 381         case I915_PARAM_HAS_POOLED_EU:
 382                 value = HAS_POOLED_EU(dev_priv);
 383                 break;
 384         case I915_PARAM_MIN_EU_IN_POOL:
 385                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 386                 break;
 387         case I915_PARAM_HUC_STATUS:
 388                 value = intel_huc_check_status(&dev_priv->huc);
 389                 if (value < 0)
 390                         return value;
 391                 break;
 392         case I915_PARAM_MMAP_GTT_VERSION:
 393                 /* Though we've started our numbering from 1, and so class all
 394                  * earlier versions as 0, in effect their value is undefined as
 395                  * the ioctl will report EINVAL for the unknown param!
 396                  */
 397                 value = i915_gem_mmap_gtt_version();
 398                 break;
 399         case I915_PARAM_HAS_SCHEDULER:
 400                 value = dev_priv->caps.scheduler;
 401                 break;
 402
 403         case I915_PARAM_MMAP_VERSION:
 404                 /* Remember to bump this if the version changes! */
 405         case I915_PARAM_HAS_GEM:
 406         case I915_PARAM_HAS_PAGEFLIPPING:
 407         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 408         case I915_PARAM_HAS_RELAXED_FENCING:
 409         case I915_PARAM_HAS_COHERENT_RINGS:
 410         case I915_PARAM_HAS_RELAXED_DELTA:
 411         case I915_PARAM_HAS_GEN7_SOL_RESET:
 412         case I915_PARAM_HAS_WAIT_TIMEOUT:
 413         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 414         case I915_PARAM_HAS_PINNED_BATCHES:
 415         case I915_PARAM_HAS_EXEC_NO_RELOC:
 416         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 417         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 418         case I915_PARAM_HAS_EXEC_SOFTPIN:
 419         case I915_PARAM_HAS_EXEC_ASYNC:
 420         case I915_PARAM_HAS_EXEC_FENCE:
 421         case I915_PARAM_HAS_EXEC_CAPTURE:
 422         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
 423         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
 424                 /* For the time being all of these are always true;
 425                  * if some supported hardware does not have one of these
 426                  * features this value needs to be provided from
 427                  * INTEL_INFO(), a feature macro, or similar.
 428                  */
 429                 value = 1;
 430                 break;
 431         case I915_PARAM_HAS_CONTEXT_ISOLATION:
 432                 value = intel_engines_has_context_isolation(dev_priv);
 433                 break;
 434         case I915_PARAM_SLICE_MASK:
 435                 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
 436                 if (!value)
 437                         return -ENODEV;
 438                 break;
 439         case I915_PARAM_SUBSLICE_MASK:
 440                 value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0];
 441                 if (!value)
 442                         return -ENODEV;
 443                 break;
 444         case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
 445                 value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
 446                 break;
 447         default:
 448                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 449                 return -EINVAL;
 450         }
 451
 452         if (put_user(value, param->value))
 453                 return -EFAULT;
 454
 455         return 0;
 456 }
 457
 458 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 459 {
 460         int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
 461
 462         dev_priv->bridge_dev =
 463                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 464         if (!dev_priv->bridge_dev) {
 465                 DRM_ERROR("bridge device not found\n");
 466                 return -1;
 467         }
 468         return 0;
 469 }
 470
 471 /* Allocate space for the MCH regs if needed, return nonzero on error */
 472 static int
 473 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 474 {
 475         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 476         u32 temp_lo, temp_hi = 0;
 477         u64 mchbar_addr;
 478         int ret;
 479
 480         if (INTEL_GEN(dev_priv) >= 4)
 481                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 482         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 483         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 484
 485         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 486 #ifdef CONFIG_PNP
 487         if (mchbar_addr &&
 488             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 489                 return 0;
 490 #endif
 491
 492         /* Get some space for it */
 493         dev_priv->mch_res.name = "i915 MCHBAR";
 494         dev_priv->mch_res.flags = IORESOURCE_MEM;
 495         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 496                                      &dev_priv->mch_res,
 497                                      MCHBAR_SIZE, MCHBAR_SIZE,
 498                                      PCIBIOS_MIN_MEM,
 499                                      0, pcibios_align_resource,
 500                                      dev_priv->bridge_dev);
 501         if (ret) {
 502                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 503                 dev_priv->mch_res.start = 0;
 504                 return ret;
 505         }
 506
 507         if (INTEL_GEN(dev_priv) >= 4)
 508                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 509                                        upper_32_bits(dev_priv->mch_res.start));
 510
 511         pci_write_config_dword(dev_priv->bridge_dev, reg,
 512                                lower_32_bits(dev_priv->mch_res.start));
 513         return 0;
 514 }
 515
 516 /* Setup MCHBAR if possible, return true if we should disable it again */
 517 static void
 518 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 519 {
 520         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 521         u32 temp;
 522         bool enabled;
 523
 524         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 525                 return;
 526
 527         dev_priv->mchbar_need_disable = false;
 528
 529         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 530                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 531                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 532         } else {
 533                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 534                 enabled = temp & 1;
 535         }
 536
 537         /* If it's already enabled, don't have to do anything */
 538         if (enabled)
 539                 return;
 540
 541         if (intel_alloc_mchbar_resource(dev_priv))
 542                 return;
 543
 544         dev_priv->mchbar_need_disable = true;
 545
 546         /* Space is allocated or reserved, so enable it. */
 547         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 548                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 549                                        temp | DEVEN_MCHBAR_EN);
 550         } else {
 551                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 552                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 553         }
 554 }
 555
 556 static void
 557 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 558 {
 559         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 560
 561         if (dev_priv->mchbar_need_disable) {
 562                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 563                         u32 deven_val;
 564
 565                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 566                                               &deven_val);
 567                         deven_val &= ~DEVEN_MCHBAR_EN;
 568                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 569                                                deven_val);
 570                 } else {
 571                         u32 mchbar_val;
 572
 573                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 574                                               &mchbar_val);
 575                         mchbar_val &= ~1;
 576                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 577                                                mchbar_val);
 578                 }
 579         }
 580
 581         if (dev_priv->mch_res.start)
 582                 release_resource(&dev_priv->mch_res);
 583 }
 584
 585 /* true = enable decode, false = disable decoder */
 586 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 587 {
 588         struct drm_i915_private *dev_priv = cookie;
 589
 590         intel_modeset_vga_set_state(dev_priv, state);
 591         if (state)
 592                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 593                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 594         else
 595                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 596 }
 597
 598 static int i915_resume_switcheroo(struct drm_device *dev);
 599 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 600
 601 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 602 {
 603         struct drm_device *dev = pci_get_drvdata(pdev);
 604         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 605
 606         if (state == VGA_SWITCHEROO_ON) {
 607                 pr_info("switched on\n");
 608                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 609                 /* i915 resume handler doesn't set to D0 */
 610                 pci_set_power_state(pdev, PCI_D0);
 611                 i915_resume_switcheroo(dev);
 612                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 613         } else {
 614                 pr_info("switched off\n");
 615                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 616                 i915_suspend_switcheroo(dev, pmm);
 617                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 618         }
 619 }
 620
 621 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 622 {
 623         struct drm_device *dev = pci_get_drvdata(pdev);
 624
 625         /*
 626          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 627          * locking inversion with the driver load path. And the access here is
 628          * completely racy anyway. So don't bother with locking for now.
 629          */
 630         return dev->open_count == 0;
 631 }
 632
 633 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 634         .set_gpu_state = i915_switcheroo_set_state,
 635         .reprobe = NULL,
 636         .can_switch = i915_switcheroo_can_switch,
 637 };
 638
 639 static int i915_load_modeset_init(struct drm_device *dev)
 640 {
 641         struct drm_i915_private *dev_priv = to_i915(dev);
 642         struct pci_dev *pdev = dev_priv->drm.pdev;
 643         int ret;
 644
 645         if (i915_inject_load_failure())
 646                 return -ENODEV;
 647
 648         intel_bios_init(dev_priv);
 649
 650         /* If we have > 1 VGA cards, then we need to arbitrate access
 651          * to the common VGA resources.
 652          *
 653          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 654          * then we do not take part in VGA arbitration and the
 655          * vga_client_register() fails with -ENODEV.
 656          */
 657         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 658         if (ret && ret != -ENODEV)
 659                 goto out;
 660
 661         intel_register_dsm_handler();
 662
 663         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 664         if (ret)
 665                 goto cleanup_vga_client;
 666
 667         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 668         intel_update_rawclk(dev_priv);
 669
 670         intel_power_domains_init_hw(dev_priv, false);
 671
 672         intel_csr_ucode_init(dev_priv);
 673
 674         ret = intel_irq_install(dev_priv);
 675         if (ret)
 676                 goto cleanup_csr;
 677
 678         intel_setup_gmbus(dev_priv);
 679
 680         /* Important: The output setup functions called by modeset_init need
 681          * working irqs for e.g. gmbus and dp aux transfers. */
 682         ret = intel_modeset_init(dev);
 683         if (ret)
 684                 goto cleanup_irq;
 685
 686         ret = i915_gem_init(dev_priv);
 687         if (ret)
 688                 goto cleanup_irq;
 689
 690         intel_setup_overlay(dev_priv);
 691
 692         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 693                 return 0;
 694
 695         ret = intel_fbdev_init(dev);
 696         if (ret)
 697                 goto cleanup_gem;
 698
 699         /* Only enable hotplug handling once the fbdev is fully set up. */
 700         intel_hpd_init(dev_priv);
 701
 702         return 0;
 703
 704 cleanup_gem:
 705         if (i915_gem_suspend(dev_priv))
 706                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 707         i915_gem_fini(dev_priv);
 708 cleanup_irq:
 709         drm_irq_uninstall(dev);
 710         intel_teardown_gmbus(dev_priv);
 711 cleanup_csr:
 712         intel_csr_ucode_fini(dev_priv);
 713         intel_power_domains_fini(dev_priv);
 714         vga_switcheroo_unregister_client(pdev);
 715 cleanup_vga_client:
 716         vga_client_register(pdev, NULL, NULL, NULL);
 717 out:
 718         return ret;
 719 }
 720
 721 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 722 {
 723         struct apertures_struct *ap;
 724         struct pci_dev *pdev = dev_priv->drm.pdev;
 725         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 726         bool primary;
 727         int ret;
 728
 729         ap = alloc_apertures(1);
 730         if (!ap)
 731                 return -ENOMEM;
 732
 733         ap->ranges[0].base = ggtt->gmadr.start;
 734         ap->ranges[0].size = ggtt->mappable_end;
 735
 736         primary =
 737                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 738
 739         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 740
 741         kfree(ap);
 742
 743         return ret;
 744 }
 745
 746 #if !defined(CONFIG_VGA_CONSOLE)
 747 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 748 {
 749         return 0;
 750 }
 751 #elif !defined(CONFIG_DUMMY_CONSOLE)
 752 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 753 {
 754         return -ENODEV;
 755 }
 756 #else
 757 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 758 {
 759         int ret = 0;
 760
 761         DRM_INFO("Replacing VGA console driver\n");
 762
 763         console_lock();
 764         if (con_is_bound(&vga_con))
 765                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 766         if (ret == 0) {
 767                 ret = do_unregister_con_driver(&vga_con);
 768
 769                 /* Ignore "already unregistered". */
 770                 if (ret == -ENODEV)
 771                         ret = 0;
 772         }
 773         console_unlock();
 774
 775         return ret;
 776 }
 777 #endif
 778
 779 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 780 {
 781         /*
 782          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 783          * CHV x1 PHY (DP/HDMI D)
 784          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 785          */
 786         if (IS_CHERRYVIEW(dev_priv)) {
 787                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 788                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 789         } else if (IS_VALLEYVIEW(dev_priv)) {
 790                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 791         }
 792 }
 793
 794 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 795 {
 796         /*
 797          * The i915 workqueue is primarily used for batched retirement of
 798          * requests (and thus managing bo) once the task has been completed
 799          * by the GPU. i915_retire_requests() is called directly when we
 800          * need high-priority retirement, such as waiting for an explicit
 801          * bo.
 802          *
 803          * It is also used for periodic low-priority events, such as
 804          * idle-timers and recording error state.
 805          *
 806          * All tasks on the workqueue are expected to acquire the dev mutex
 807          * so there is no point in running more than one instance of the
 808          * workqueue at any time.  Use an ordered one.
 809          */
 810         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 811         if (dev_priv->wq == NULL)
 812                 goto out_err;
 813
 814         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 815         if (dev_priv->hotplug.dp_wq == NULL)
 816                 goto out_free_wq;
 817
 818         return 0;
 819
 820 out_free_wq:
 821         destroy_workqueue(dev_priv->wq);
 822 out_err:
 823         DRM_ERROR("Failed to allocate workqueues.\n");
 824
 825         return -ENOMEM;
 826 }
 827
 828 static void i915_engines_cleanup(struct drm_i915_private *i915)
 829 {
 830         struct intel_engine_cs *engine;
 831         enum intel_engine_id id;
 832
 833         for_each_engine(engine, i915, id)
 834                 kfree(engine);
 835 }
 836
 837 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 838 {
 839         destroy_workqueue(dev_priv->hotplug.dp_wq);
 840         destroy_workqueue(dev_priv->wq);
 841 }
 842
 843 /*
 844  * We don't keep the workarounds for pre-production hardware, so we expect our
 845  * driver to fail on these machines in one way or another. A little warning on
 846  * dmesg may help both the user and the bug triagers.
 847  *
 848  * Our policy for removing pre-production workarounds is to keep the
 849  * current gen workarounds as a guide to the bring-up of the next gen
 850  * (workarounds have a habit of persisting!). Anything older than that
 851  * should be removed along with the complications they introduce.
 852  */
 853 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 854 {
 855         bool pre = false;
 856
 857         pre |= IS_HSW_EARLY_SDV(dev_priv);
 858         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 859         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 860
 861         if (pre) {
 862                 DRM_ERROR("This is a pre-production stepping. "
 863                           "It may not be fully functional.\n");
 864                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 865         }
 866 }
 867
 868 /**
 869  * i915_driver_init_early - setup state not requiring device access
 870  * @dev_priv: device private
 871  * @ent: the matching pci_device_id
 872  *
 873  * Initialize everything that is a "SW-only" state, that is state not
 874  * requiring accessing the device or exposing the driver via kernel internal
 875  * or userspace interfaces. Example steps belonging here: lock initialization,
 876  * system memory allocation, setting up device specific attributes and
 877  * function hooks not requiring accessing the device.
 878  */
 879 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 880                                   const struct pci_device_id *ent)
 881 {
 882         const struct intel_device_info *match_info =
 883                 (struct intel_device_info *)ent->driver_data;
 884         struct intel_device_info *device_info;
 885         int ret = 0;
 886
 887         if (i915_inject_load_failure())
 888                 return -ENODEV;
 889
 890         /* Setup the write-once "constant" device info */
 891         device_info = mkwrite_device_info(dev_priv);
 892         memcpy(device_info, match_info, sizeof(*device_info));
 893         device_info->device_id = dev_priv->drm.pdev->device;
 894
 895         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
 896                      sizeof(device_info->platform_mask) * BITS_PER_BYTE);
 897         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 898         spin_lock_init(&dev_priv->irq_lock);
 899         spin_lock_init(&dev_priv->gpu_error.lock);
 900         mutex_init(&dev_priv->backlight_lock);
 901         spin_lock_init(&dev_priv->uncore.lock);
 902
 903         mutex_init(&dev_priv->sb_lock);
 904         mutex_init(&dev_priv->modeset_restore_lock);
 905         mutex_init(&dev_priv->av_mutex);
 906         mutex_init(&dev_priv->wm.wm_mutex);
 907         mutex_init(&dev_priv->pps_mutex);
 908
 909         i915_memcpy_init_early(dev_priv);
 910
 911         ret = i915_workqueues_init(dev_priv);
 912         if (ret < 0)
 913                 goto err_engines;
 914
 915         ret = i915_gem_init_early(dev_priv);
 916         if (ret < 0)
 917                 goto err_workqueues;
 918
 919         /* This must be called before any calls to HAS_PCH_* */
 920         intel_detect_pch(dev_priv);
 921
 922         intel_wopcm_init_early(&dev_priv->wopcm);
 923         intel_uc_init_early(dev_priv);
 924         intel_pm_setup(dev_priv);
 925         intel_init_dpio(dev_priv);
 926         intel_power_domains_init(dev_priv);
 927         intel_irq_init(dev_priv);
 928         intel_hangcheck_init(dev_priv);
 929         intel_init_display_hooks(dev_priv);
 930         intel_init_clock_gating_hooks(dev_priv);
 931         intel_init_audio_hooks(dev_priv);
 932         intel_display_crc_init(dev_priv);
 933
 934         intel_detect_preproduction_hw(dev_priv);
 935
 936         return 0;
 937
 938 err_workqueues:
 939         i915_workqueues_cleanup(dev_priv);
 940 err_engines:
 941         i915_engines_cleanup(dev_priv);
 942         return ret;
 943 }
 944
 945 /**
 946  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 947  * @dev_priv: device private
 948  */
 949 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 950 {
 951         intel_irq_fini(dev_priv);
 952         intel_uc_cleanup_early(dev_priv);
 953         i915_gem_cleanup_early(dev_priv);
 954         i915_workqueues_cleanup(dev_priv);
 955         i915_engines_cleanup(dev_priv);
 956 }
 957
 958 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 959 {
 960         struct pci_dev *pdev = dev_priv->drm.pdev;
 961         int mmio_bar;
 962         int mmio_size;
 963
 964         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 965         /*
 966          * Before gen4, the registers and the GTT are behind different BARs.
 967          * However, from gen4 onwards, the registers and the GTT are shared
 968          * in the same BAR, so we want to restrict this ioremap from
 969          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 970          * the register BAR remains the same size for all the earlier
 971          * generations up to Ironlake.
 972          */
 973         if (INTEL_GEN(dev_priv) < 5)
 974                 mmio_size = 512 * 1024;
 975         else
 976                 mmio_size = 2 * 1024 * 1024;
 977         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 978         if (dev_priv->regs == NULL) {
 979                 DRM_ERROR("failed to map registers\n");
 980
 981                 return -EIO;
 982         }
 983
 984         /* Try to make sure MCHBAR is enabled before poking at it */
 985         intel_setup_mchbar(dev_priv);
 986
 987         return 0;
 988 }
 989
 990 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 991 {
 992         struct pci_dev *pdev = dev_priv->drm.pdev;
 993
 994         intel_teardown_mchbar(dev_priv);
 995         pci_iounmap(pdev, dev_priv->regs);
 996 }
 997
 998 /**
 999  * i915_driver_init_mmio - setup device MMIO
1000  * @dev_priv: device private
1001  *
1002  * Setup minimal device state necessary for MMIO accesses later in the
1003  * initialization sequence. The setup here should avoid any other device-wide
1004  * side effects or exposing the driver via kernel internal or user space
1005  * interfaces.
1006  */
1007 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1008 {
1009         int ret;
1010
1011         if (i915_inject_load_failure())
1012                 return -ENODEV;
1013
1014         if (i915_get_bridge_dev(dev_priv))
1015                 return -EIO;
1016
1017         ret = i915_mmio_setup(dev_priv);
1018         if (ret < 0)
1019                 goto err_bridge;
1020
1021         intel_uncore_init(dev_priv);
1022
1023         intel_device_info_init_mmio(dev_priv);
1024
1025         intel_uncore_prune(dev_priv);
1026
1027         intel_uc_init_mmio(dev_priv);
1028
1029         ret = intel_engines_init_mmio(dev_priv);
1030         if (ret)
1031                 goto err_uncore;
1032
1033         i915_gem_init_mmio(dev_priv);
1034
1035         return 0;
1036
1037 err_uncore:
1038         intel_uncore_fini(dev_priv);
1039 err_bridge:
1040         pci_dev_put(dev_priv->bridge_dev);
1041
1042         return ret;
1043 }
1044
1045 /**
1046  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1047  * @dev_priv: device private
1048  */
1049 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1050 {
1051         intel_uncore_fini(dev_priv);
1052         i915_mmio_cleanup(dev_priv);
1053         pci_dev_put(dev_priv->bridge_dev);
1054 }
1055
1056 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1057 {
1058         /*
1059          * i915.enable_ppgtt is read-only, so do an early pass to validate the
1060          * user's requested state against the hardware/driver capabilities.  We
1061          * do this now so that we can print out any log messages once rather
1062          * than every time we check intel_enable_ppgtt().
1063          */
1064         i915_modparams.enable_ppgtt =
1065                 intel_sanitize_enable_ppgtt(dev_priv,
1066                                             i915_modparams.enable_ppgtt);
1067         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
1068
1069         intel_gvt_sanitize_options(dev_priv);
1070 }
1071
1072 /**
1073  * i915_driver_init_hw - setup state requiring device access
1074  * @dev_priv: device private
1075  *
1076  * Setup state that requires accessing the device, but doesn't require
1077  * exposing the driver via kernel internal or userspace interfaces.
1078  */
1079 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1080 {
1081         struct pci_dev *pdev = dev_priv->drm.pdev;
1082         int ret;
1083
1084         if (i915_inject_load_failure())
1085                 return -ENODEV;
1086
1087         intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
1088
1089         intel_sanitize_options(dev_priv);
1090
1091         i915_perf_init(dev_priv);
1092
1093         ret = i915_ggtt_probe_hw(dev_priv);
1094         if (ret)
1095                 goto err_perf;
1096
1097         /*
1098          * WARNING: Apparently we must kick fbdev drivers before vgacon,
1099          * otherwise the vga fbdev driver falls over.
1100          */
1101         ret = i915_kick_out_firmware_fb(dev_priv);
1102         if (ret) {
1103                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1104                 goto err_ggtt;
1105         }
1106
1107         ret = i915_kick_out_vgacon(dev_priv);
1108         if (ret) {
1109                 DRM_ERROR("failed to remove conflicting VGA console\n");
1110                 goto err_ggtt;
1111         }
1112
1113         ret = i915_ggtt_init_hw(dev_priv);
1114         if (ret)
1115                 goto err_ggtt;
1116
1117         ret = i915_ggtt_enable_hw(dev_priv);
1118         if (ret) {
1119                 DRM_ERROR("failed to enable GGTT\n");
1120                 goto err_ggtt;
1121         }
1122
1123         pci_set_master(pdev);
1124
1125         /* overlay on gen2 is broken and can't address above 1G */
1126         if (IS_GEN2(dev_priv)) {
1127                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1128                 if (ret) {
1129                         DRM_ERROR("failed to set DMA mask\n");
1130
1131                         goto err_ggtt;
1132                 }
1133         }
1134
1135         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1136          * using 32bit addressing, overwriting memory if HWS is located
1137          * above 4GB.
1138          *
1139          * The documentation also mentions an issue with undefined
1140          * behaviour if any general state is accessed within a page above 4GB,
1141          * which also needs to be handled carefully.
1142          */
1143         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1144                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1145
1146                 if (ret) {
1147                         DRM_ERROR("failed to set DMA mask\n");
1148
1149                         goto err_ggtt;
1150                 }
1151         }
1152
1153         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1154                            PM_QOS_DEFAULT_VALUE);
1155
1156         intel_uncore_sanitize(dev_priv);
1157
1158         intel_opregion_setup(dev_priv);
1159
1160         i915_gem_load_init_fences(dev_priv);
1161
1162         /* On the 945G/GM, the chipset reports the MSI capability on the
1163          * integrated graphics even though the support isn't actually there
1164          * according to the published specs.  It doesn't appear to function
1165          * correctly in testing on 945G.
1166          * This may be a side effect of MSI having been made available for PEG
1167          * and the registers being closely associated.
1168          *
1169          * According to chipset errata, on the 965GM, MSI interrupts may
1170          * be lost or delayed, and was defeatured. MSI interrupts seem to
1171          * get lost on g4x as well, and interrupt delivery seems to stay
1172          * properly dead afterwards. So we'll just disable them for all
1173          * pre-gen5 chipsets.
1174          */
1175         if (INTEL_GEN(dev_priv) >= 5) {
1176                 if (pci_enable_msi(pdev) < 0)
1177                         DRM_DEBUG_DRIVER("can't enable MSI");
1178         }
1179
1180         ret = intel_gvt_init(dev_priv);
1181         if (ret)
1182                 goto err_ggtt;
1183
1184         return 0;
1185
1186 err_ggtt:
1187         i915_ggtt_cleanup_hw(dev_priv);
1188 err_perf:
1189         i915_perf_fini(dev_priv);
1190         return ret;
1191 }
1192
1193 /**
1194  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1195  * @dev_priv: device private
1196  */
1197 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1198 {
1199         struct pci_dev *pdev = dev_priv->drm.pdev;
1200
1201         i915_perf_fini(dev_priv);
1202
1203         if (pdev->msi_enabled)
1204                 pci_disable_msi(pdev);
1205
1206         pm_qos_remove_request(&dev_priv->pm_qos);
1207         i915_ggtt_cleanup_hw(dev_priv);
1208 }
1209
1210 /**
1211  * i915_driver_register - register the driver with the rest of the system
1212  * @dev_priv: device private
1213  *
1214  * Perform any steps necessary to make the driver available via kernel
1215  * internal or userspace interfaces.
1216  */
1217 static void i915_driver_register(struct drm_i915_private *dev_priv)
1218 {
1219         struct drm_device *dev = &dev_priv->drm;
1220
1221         i915_gem_shrinker_register(dev_priv);
1222         i915_pmu_register(dev_priv);
1223
1224         /*
1225          * Notify a valid surface after modesetting,
1226          * when running inside a VM.
1227          */
1228         if (intel_vgpu_active(dev_priv))
1229                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1230
1231         /* Reveal our presence to userspace */
1232         if (drm_dev_register(dev, 0) == 0) {
1233                 i915_debugfs_register(dev_priv);
1234                 i915_setup_sysfs(dev_priv);
1235
1236                 /* Depends on sysfs having been initialized */
1237                 i915_perf_register(dev_priv);
1238         } else
1239                 DRM_ERROR("Failed to register driver for userspace access!\n");
1240
1241         if (INTEL_INFO(dev_priv)->num_pipes) {
1242                 /* Must be done after probing outputs */
1243                 intel_opregion_register(dev_priv);
1244                 acpi_video_register();
1245         }
1246
1247         if (IS_GEN5(dev_priv))
1248                 intel_gpu_ips_init(dev_priv);
1249
1250         intel_audio_init(dev_priv);
1251
1252         /*
1253          * Some ports require correctly set-up hpd registers for detection to
1254          * work properly (leading to ghost connected connector status), e.g. VGA
1255          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1256          * irqs are fully enabled. We do it last so that the async config
1257          * cannot run before the connectors are registered.
1258          */
1259         intel_fbdev_initial_config_async(dev);
1260
1261         /*
1262          * We need to coordinate the hotplugs with the asynchronous fbdev
1263          * configuration, for which we use the fbdev->async_cookie.
1264          */
1265         if (INTEL_INFO(dev_priv)->num_pipes)
1266                 drm_kms_helper_poll_init(dev);
1267 }
1268
1269 /**
1270  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1271  * @dev_priv: device private
1272  */
1273 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1274 {
1275         intel_fbdev_unregister(dev_priv);
1276         intel_audio_deinit(dev_priv);
1277
1278         /*
1279          * After flushing the fbdev (incl. a late async config which will
1280          * have delayed queuing of a hotplug event), then flush the hotplug
1281          * events.
1282          */
1283         drm_kms_helper_poll_fini(&dev_priv->drm);
1284
1285         intel_gpu_ips_teardown();
1286         acpi_video_unregister();
1287         intel_opregion_unregister(dev_priv);
1288
1289         i915_perf_unregister(dev_priv);
1290         i915_pmu_unregister(dev_priv);
1291
1292         i915_teardown_sysfs(dev_priv);
1293         drm_dev_unregister(&dev_priv->drm);
1294
1295         i915_gem_shrinker_unregister(dev_priv);
1296 }
1297
1298 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1299 {
1300         if (drm_debug & DRM_UT_DRIVER) {
1301                 struct drm_printer p = drm_debug_printer("i915 device info:");
1302
1303                 intel_device_info_dump(&dev_priv->info, &p);
1304                 intel_device_info_dump_runtime(&dev_priv->info, &p);
1305         }
1306
1307         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1308                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1309         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1310                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1311 }
1312
1313 /**
1314  * i915_driver_load - setup chip and create an initial config
1315  * @pdev: PCI device
1316  * @ent: matching PCI ID entry
1317  *
1318  * The driver load routine has to do several things:
1319  *   - drive output discovery via intel_modeset_init()
1320  *   - initialize the memory manager
1321  *   - allocate initial config memory
1322  *   - setup the DRM framebuffer with the allocated memory
1323  */
1324 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1325 {
1326         const struct intel_device_info *match_info =
1327                 (struct intel_device_info *)ent->driver_data;
1328         struct drm_i915_private *dev_priv;
1329         int ret;
1330
1331         /* Enable nuclear pageflip on ILK+ */
1332         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1333                 driver.driver_features &= ~DRIVER_ATOMIC;
1334
1335         ret = -ENOMEM;
1336         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1337         if (dev_priv)
1338                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1339         if (ret) {
1340                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1341                 goto out_free;
1342         }
1343
1344         dev_priv->drm.pdev = pdev;
1345         dev_priv->drm.dev_private = dev_priv;
1346
1347         ret = pci_enable_device(pdev);
1348         if (ret)
1349                 goto out_fini;
1350
1351         pci_set_drvdata(pdev, &dev_priv->drm);
1352         /*
1353          * Disable the system suspend direct complete optimization, which can
1354          * leave the device suspended skipping the driver's suspend handlers
1355          * if the device was already runtime suspended. This is needed due to
1356          * the difference in our runtime and system suspend sequence and
1357          * becaue the HDA driver may require us to enable the audio power
1358          * domain during system suspend.
1359          */
1360         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
1361
1362         ret = i915_driver_init_early(dev_priv, ent);
1363         if (ret < 0)
1364                 goto out_pci_disable;
1365
1366         intel_runtime_pm_get(dev_priv);
1367
1368         ret = i915_driver_init_mmio(dev_priv);
1369         if (ret < 0)
1370                 goto out_runtime_pm_put;
1371
1372         ret = i915_driver_init_hw(dev_priv);
1373         if (ret < 0)
1374                 goto out_cleanup_mmio;
1375
1376         /*
1377          * TODO: move the vblank init and parts of modeset init steps into one
1378          * of the i915_driver_init_/i915_driver_register functions according
1379          * to the role/effect of the given init step.
1380          */
1381         if (INTEL_INFO(dev_priv)->num_pipes) {
1382                 ret = drm_vblank_init(&dev_priv->drm,
1383                                       INTEL_INFO(dev_priv)->num_pipes);
1384                 if (ret)
1385                         goto out_cleanup_hw;
1386         }
1387
1388         ret = i915_load_modeset_init(&dev_priv->drm);
1389         if (ret < 0)
1390                 goto out_cleanup_hw;
1391
1392         i915_driver_register(dev_priv);
1393
1394         intel_runtime_pm_enable(dev_priv);
1395
1396         intel_init_ipc(dev_priv);
1397
1398         intel_runtime_pm_put(dev_priv);
1399
1400         i915_welcome_messages(dev_priv);
1401
1402         return 0;
1403
1404 out_cleanup_hw:
1405         i915_driver_cleanup_hw(dev_priv);
1406 out_cleanup_mmio:
1407         i915_driver_cleanup_mmio(dev_priv);
1408 out_runtime_pm_put:
1409         intel_runtime_pm_put(dev_priv);
1410         i915_driver_cleanup_early(dev_priv);
1411 out_pci_disable:
1412         pci_disable_device(pdev);
1413 out_fini:
1414         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1415         drm_dev_fini(&dev_priv->drm);
1416 out_free:
1417         kfree(dev_priv);
1418         return ret;
1419 }
1420
1421 void i915_driver_unload(struct drm_device *dev)
1422 {
1423         struct drm_i915_private *dev_priv = to_i915(dev);
1424         struct pci_dev *pdev = dev_priv->drm.pdev;
1425
1426         i915_driver_unregister(dev_priv);
1427
1428         if (i915_gem_suspend(dev_priv))
1429                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1430
1431         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1432
1433         drm_atomic_helper_shutdown(dev);
1434
1435         intel_gvt_cleanup(dev_priv);
1436
1437         intel_modeset_cleanup(dev);
1438
1439         intel_bios_cleanup(dev_priv);
1440
1441         vga_switcheroo_unregister_client(pdev);
1442         vga_client_register(pdev, NULL, NULL, NULL);
1443
1444         intel_csr_ucode_fini(dev_priv);
1445
1446         /* Free error state after interrupts are fully disabled. */
1447         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1448         i915_reset_error_state(dev_priv);
1449
1450         i915_gem_fini(dev_priv);
1451         intel_fbc_cleanup_cfb(dev_priv);
1452
1453         intel_power_domains_fini(dev_priv);
1454
1455         i915_driver_cleanup_hw(dev_priv);
1456         i915_driver_cleanup_mmio(dev_priv);
1457
1458         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1459 }
1460
1461 static void i915_driver_release(struct drm_device *dev)
1462 {
1463         struct drm_i915_private *dev_priv = to_i915(dev);
1464
1465         i915_driver_cleanup_early(dev_priv);
1466         drm_dev_fini(&dev_priv->drm);
1467
1468         kfree(dev_priv);
1469 }
1470
1471 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1472 {
1473         struct drm_i915_private *i915 = to_i915(dev);
1474         int ret;
1475
1476         ret = i915_gem_open(i915, file);
1477         if (ret)
1478                 return ret;
1479
1480         return 0;
1481 }
1482
1483 /**
1484  * i915_driver_lastclose - clean up after all DRM clients have exited
1485  * @dev: DRM device
1486  *
1487  * Take care of cleaning up after all DRM clients have exited.  In the
1488  * mode setting case, we want to restore the kernel's initial mode (just
1489  * in case the last client left us in a bad state).
1490  *
1491  * Additionally, in the non-mode setting case, we'll tear down the GTT
1492  * and DMA structures, since the kernel won't be using them, and clea
1493  * up any GEM state.
1494  */
1495 static void i915_driver_lastclose(struct drm_device *dev)
1496 {
1497         intel_fbdev_restore_mode(dev);
1498         vga_switcheroo_process_delayed_switch();
1499 }
1500
1501 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1502 {
1503         struct drm_i915_file_private *file_priv = file->driver_priv;
1504
1505         mutex_lock(&dev->struct_mutex);
1506         i915_gem_context_close(file);
1507         i915_gem_release(dev, file);
1508         mutex_unlock(&dev->struct_mutex);
1509
1510         kfree(file_priv);
1511 }
1512
1513 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1514 {
1515         struct drm_device *dev = &dev_priv->drm;
1516         struct intel_encoder *encoder;
1517
1518         drm_modeset_lock_all(dev);
1519         for_each_intel_encoder(dev, encoder)
1520                 if (encoder->suspend)
1521                         encoder->suspend(encoder);
1522         drm_modeset_unlock_all(dev);
1523 }
1524
1525 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1526                               bool rpm_resume);
1527 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1528
1529 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1530 {
1531 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1532         if (acpi_target_system_state() < ACPI_STATE_S3)
1533                 return true;
1534 #endif
1535         return false;
1536 }
1537
1538 static int i915_drm_prepare(struct drm_device *dev)
1539 {
1540         struct drm_i915_private *i915 = to_i915(dev);
1541         int err;
1542
1543         /*
1544          * NB intel_display_suspend() may issue new requests after we've
1545          * ostensibly marked the GPU as ready-to-sleep here. We need to
1546          * split out that work and pull it forward so that after point,
1547          * the GPU is not woken again.
1548          */
1549         err = i915_gem_suspend(i915);
1550         if (err)
1551                 dev_err(&i915->drm.pdev->dev,
1552                         "GEM idle failed, suspend/resume might fail\n");
1553
1554         return err;
1555 }
1556
1557 static int i915_drm_suspend(struct drm_device *dev)
1558 {
1559         struct drm_i915_private *dev_priv = to_i915(dev);
1560         struct pci_dev *pdev = dev_priv->drm.pdev;
1561         pci_power_t opregion_target_state;
1562
1563         /* ignore lid events during suspend */
1564         mutex_lock(&dev_priv->modeset_restore_lock);
1565         dev_priv->modeset_restore = MODESET_SUSPENDED;
1566         mutex_unlock(&dev_priv->modeset_restore_lock);
1567
1568         disable_rpm_wakeref_asserts(dev_priv);
1569
1570         /* We do a lot of poking in a lot of registers, make sure they work
1571          * properly. */
1572         intel_display_set_init_power(dev_priv, true);
1573
1574         drm_kms_helper_poll_disable(dev);
1575
1576         pci_save_state(pdev);
1577
1578         intel_display_suspend(dev);
1579
1580         intel_dp_mst_suspend(dev);
1581
1582         intel_runtime_pm_disable_interrupts(dev_priv);
1583         intel_hpd_cancel_work(dev_priv);
1584
1585         intel_suspend_encoders(dev_priv);
1586
1587         intel_suspend_hw(dev_priv);
1588
1589         i915_gem_suspend_gtt_mappings(dev_priv);
1590
1591         i915_save_state(dev_priv);
1592
1593         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1594         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1595
1596         intel_opregion_unregister(dev_priv);
1597
1598         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1599
1600         dev_priv->suspend_count++;
1601
1602         intel_csr_ucode_suspend(dev_priv);
1603
1604         enable_rpm_wakeref_asserts(dev_priv);
1605
1606         return 0;
1607 }
1608
1609 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1610 {
1611         struct drm_i915_private *dev_priv = to_i915(dev);
1612         struct pci_dev *pdev = dev_priv->drm.pdev;
1613         int ret;
1614
1615         disable_rpm_wakeref_asserts(dev_priv);
1616
1617         i915_gem_suspend_late(dev_priv);
1618
1619         intel_display_set_init_power(dev_priv, false);
1620         intel_uncore_suspend(dev_priv);
1621
1622         /*
1623          * In case of firmware assisted context save/restore don't manually
1624          * deinit the power domains. This also means the CSR/DMC firmware will
1625          * stay active, it will power down any HW resources as required and
1626          * also enable deeper system power states that would be blocked if the
1627          * firmware was inactive.
1628          */
1629         if (IS_GEN9_LP(dev_priv) || hibernation || !suspend_to_idle(dev_priv) ||
1630             dev_priv->csr.dmc_payload == NULL) {
1631                 intel_power_domains_suspend(dev_priv);
1632                 dev_priv->power_domains_suspended = true;
1633         }
1634
1635         ret = 0;
1636         if (IS_GEN9_LP(dev_priv))
1637                 bxt_enable_dc9(dev_priv);
1638         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1639                 hsw_enable_pc8(dev_priv);
1640         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1641                 ret = vlv_suspend_complete(dev_priv);
1642
1643         if (ret) {
1644                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1645                 if (dev_priv->power_domains_suspended) {
1646                         intel_power_domains_init_hw(dev_priv, true);
1647                         dev_priv->power_domains_suspended = false;
1648                 }
1649
1650                 goto out;
1651         }
1652
1653         pci_disable_device(pdev);
1654         /*
1655          * During hibernation on some platforms the BIOS may try to access
1656          * the device even though it's already in D3 and hang the machine. So
1657          * leave the device in D0 on those platforms and hope the BIOS will
1658          * power down the device properly. The issue was seen on multiple old
1659          * GENs with different BIOS vendors, so having an explicit blacklist
1660          * is inpractical; apply the workaround on everything pre GEN6. The
1661          * platforms where the issue was seen:
1662          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1663          * Fujitsu FSC S7110
1664          * Acer Aspire 1830T
1665          */
1666         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1667                 pci_set_power_state(pdev, PCI_D3hot);
1668
1669 out:
1670         enable_rpm_wakeref_asserts(dev_priv);
1671
1672         return ret;
1673 }
1674
1675 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1676 {
1677         int error;
1678
1679         if (!dev) {
1680                 DRM_ERROR("dev: %p\n", dev);
1681                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1682                 return -ENODEV;
1683         }
1684
1685         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1686                          state.event != PM_EVENT_FREEZE))
1687                 return -EINVAL;
1688
1689         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1690                 return 0;
1691
1692         error = i915_drm_suspend(dev);
1693         if (error)
1694                 return error;
1695
1696         return i915_drm_suspend_late(dev, false);
1697 }
1698
1699 static int i915_drm_resume(struct drm_device *dev)
1700 {
1701         struct drm_i915_private *dev_priv = to_i915(dev);
1702         int ret;
1703
1704         disable_rpm_wakeref_asserts(dev_priv);
1705         intel_sanitize_gt_powersave(dev_priv);
1706
1707         ret = i915_ggtt_enable_hw(dev_priv);
1708         if (ret)
1709                 DRM_ERROR("failed to re-enable GGTT\n");
1710
1711         intel_csr_ucode_resume(dev_priv);
1712
1713         i915_restore_state(dev_priv);
1714         intel_pps_unlock_regs_wa(dev_priv);
1715         intel_opregion_setup(dev_priv);
1716
1717         intel_init_pch_refclk(dev_priv);
1718
1719         /*
1720          * Interrupts have to be enabled before any batches are run. If not the
1721          * GPU will hang. i915_gem_init_hw() will initiate batches to
1722          * update/restore the context.
1723          *
1724          * drm_mode_config_reset() needs AUX interrupts.
1725          *
1726          * Modeset enabling in intel_modeset_init_hw() also needs working
1727          * interrupts.
1728          */
1729         intel_runtime_pm_enable_interrupts(dev_priv);
1730
1731         drm_mode_config_reset(dev);
1732
1733         i915_gem_resume(dev_priv);
1734
1735         intel_modeset_init_hw(dev);
1736         intel_init_clock_gating(dev_priv);
1737
1738         spin_lock_irq(&dev_priv->irq_lock);
1739         if (dev_priv->display.hpd_irq_setup)
1740                 dev_priv->display.hpd_irq_setup(dev_priv);
1741         spin_unlock_irq(&dev_priv->irq_lock);
1742
1743         intel_dp_mst_resume(dev);
1744
1745         intel_display_resume(dev);
1746
1747         drm_kms_helper_poll_enable(dev);
1748
1749         /*
1750          * ... but also need to make sure that hotplug processing
1751          * doesn't cause havoc. Like in the driver load code we don't
1752          * bother with the tiny race here where we might loose hotplug
1753          * notifications.
1754          * */
1755         intel_hpd_init(dev_priv);
1756
1757         intel_opregion_register(dev_priv);
1758
1759         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1760
1761         mutex_lock(&dev_priv->modeset_restore_lock);
1762         dev_priv->modeset_restore = MODESET_DONE;
1763         mutex_unlock(&dev_priv->modeset_restore_lock);
1764
1765         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1766
1767         enable_rpm_wakeref_asserts(dev_priv);
1768
1769         return 0;
1770 }
1771
1772 static int i915_drm_resume_early(struct drm_device *dev)
1773 {
1774         struct drm_i915_private *dev_priv = to_i915(dev);
1775         struct pci_dev *pdev = dev_priv->drm.pdev;
1776         int ret;
1777
1778         /*
1779          * We have a resume ordering issue with the snd-hda driver also
1780          * requiring our device to be power up. Due to the lack of a
1781          * parent/child relationship we currently solve this with an early
1782          * resume hook.
1783          *
1784          * FIXME: This should be solved with a special hdmi sink device or
1785          * similar so that power domains can be employed.
1786          */
1787
1788         /*
1789          * Note that we need to set the power state explicitly, since we
1790          * powered off the device during freeze and the PCI core won't power
1791          * it back up for us during thaw. Powering off the device during
1792          * freeze is not a hard requirement though, and during the
1793          * suspend/resume phases the PCI core makes sure we get here with the
1794          * device powered on. So in case we change our freeze logic and keep
1795          * the device powered we can also remove the following set power state
1796          * call.
1797          */
1798         ret = pci_set_power_state(pdev, PCI_D0);
1799         if (ret) {
1800                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1801                 goto out;
1802         }
1803
1804         /*
1805          * Note that pci_enable_device() first enables any parent bridge
1806          * device and only then sets the power state for this device. The
1807          * bridge enabling is a nop though, since bridge devices are resumed
1808          * first. The order of enabling power and enabling the device is
1809          * imposed by the PCI core as described above, so here we preserve the
1810          * same order for the freeze/thaw phases.
1811          *
1812          * TODO: eventually we should remove pci_disable_device() /
1813          * pci_enable_enable_device() from suspend/resume. Due to how they
1814          * depend on the device enable refcount we can't anyway depend on them
1815          * disabling/enabling the device.
1816          */
1817         if (pci_enable_device(pdev)) {
1818                 ret = -EIO;
1819                 goto out;
1820         }
1821
1822         pci_set_master(pdev);
1823
1824         disable_rpm_wakeref_asserts(dev_priv);
1825
1826         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1827                 ret = vlv_resume_prepare(dev_priv, false);
1828         if (ret)
1829                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1830                           ret);
1831
1832         intel_uncore_resume_early(dev_priv);
1833
1834         if (IS_GEN9_LP(dev_priv)) {
1835                 gen9_sanitize_dc_state(dev_priv);
1836                 bxt_disable_dc9(dev_priv);
1837         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1838                 hsw_disable_pc8(dev_priv);
1839         }
1840
1841         intel_uncore_sanitize(dev_priv);
1842
1843         if (dev_priv->power_domains_suspended)
1844                 intel_power_domains_init_hw(dev_priv, true);
1845         else
1846                 intel_display_set_init_power(dev_priv, true);
1847
1848         i915_gem_sanitize(dev_priv);
1849
1850         enable_rpm_wakeref_asserts(dev_priv);
1851
1852 out:
1853         dev_priv->power_domains_suspended = false;
1854
1855         return ret;
1856 }
1857
1858 static int i915_resume_switcheroo(struct drm_device *dev)
1859 {
1860         int ret;
1861
1862         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1863                 return 0;
1864
1865         ret = i915_drm_resume_early(dev);
1866         if (ret)
1867                 return ret;
1868
1869         return i915_drm_resume(dev);
1870 }
1871
1872 /**
1873  * i915_reset - reset chip after a hang
1874  * @i915: #drm_i915_private to reset
1875  * @stalled_mask: mask of the stalled engines with the guilty requests
1876  * @reason: user error message for why we are resetting
1877  *
1878  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1879  * on failure.
1880  *
1881  * Caller must hold the struct_mutex.
1882  *
1883  * Procedure is fairly simple:
1884  *   - reset the chip using the reset reg
1885  *   - re-init context state
1886  *   - re-init hardware status page
1887  *   - re-init ring buffer
1888  *   - re-init interrupt state
1889  *   - re-init display
1890  */
1891 void i915_reset(struct drm_i915_private *i915,
1892                 unsigned int stalled_mask,
1893                 const char *reason)
1894 {
1895         struct i915_gpu_error *error = &i915->gpu_error;
1896         int ret;
1897         int i;
1898
1899         GEM_TRACE("flags=%lx\n", error->flags);
1900
1901         might_sleep();
1902         lockdep_assert_held(&i915->drm.struct_mutex);
1903         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1904
1905         if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1906                 return;
1907
1908         /* Clear any previous failed attempts at recovery. Time to try again. */
1909         if (!i915_gem_unset_wedged(i915))
1910                 goto wakeup;
1911
1912         if (reason)
1913                 dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason);
1914         error->reset_count++;
1915
1916         disable_irq(i915->drm.irq);
1917         ret = i915_gem_reset_prepare(i915);
1918         if (ret) {
1919                 dev_err(i915->drm.dev, "GPU recovery failed\n");
1920                 goto taint;
1921         }
1922
1923         if (!intel_has_gpu_reset(i915)) {
1924                 if (i915_modparams.reset)
1925                         dev_err(i915->drm.dev, "GPU reset not supported\n");
1926                 else
1927                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1928                 goto error;
1929         }
1930
1931         for (i = 0; i < 3; i++) {
1932                 ret = intel_gpu_reset(i915, ALL_ENGINES);
1933                 if (ret == 0)
1934                         break;
1935
1936                 msleep(100);
1937         }
1938         if (ret) {
1939                 dev_err(i915->drm.dev, "Failed to reset chip\n");
1940                 goto taint;
1941         }
1942
1943         /* Ok, now get things going again... */
1944
1945         /*
1946          * Everything depends on having the GTT running, so we need to start
1947          * there.
1948          */
1949         ret = i915_ggtt_enable_hw(i915);
1950         if (ret) {
1951                 DRM_ERROR("Failed to re-enable GGTT following reset (%d)\n",
1952                           ret);
1953                 goto error;
1954         }
1955
1956         i915_gem_reset(i915, stalled_mask);
1957         intel_overlay_reset(i915);
1958
1959         /*
1960          * Next we need to restore the context, but we don't use those
1961          * yet either...
1962          *
1963          * Ring buffer needs to be re-initialized in the KMS case, or if X
1964          * was running at the time of the reset (i.e. we weren't VT
1965          * switched away).
1966          */
1967         ret = i915_gem_init_hw(i915);
1968         if (ret) {
1969                 DRM_ERROR("Failed to initialise HW following reset (%d)\n",
1970                           ret);
1971                 goto error;
1972         }
1973
1974         i915_queue_hangcheck(i915);
1975
1976 finish:
1977         i915_gem_reset_finish(i915);
1978         enable_irq(i915->drm.irq);
1979
1980 wakeup:
1981         clear_bit(I915_RESET_HANDOFF, &error->flags);
1982         wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1983         return;
1984
1985 taint:
1986         /*
1987          * History tells us that if we cannot reset the GPU now, we
1988          * never will. This then impacts everything that is run
1989          * subsequently. On failing the reset, we mark the driver
1990          * as wedged, preventing further execution on the GPU.
1991          * We also want to go one step further and add a taint to the
1992          * kernel so that any subsequent faults can be traced back to
1993          * this failure. This is important for CI, where if the
1994          * GPU/driver fails we would like to reboot and restart testing
1995          * rather than continue on into oblivion. For everyone else,
1996          * the system should still plod along, but they have been warned!
1997          */
1998         add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
1999 error:
2000         i915_gem_set_wedged(i915);
2001         i915_retire_requests(i915);
2002         goto finish;
2003 }
2004
2005 static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv,
2006                                         struct intel_engine_cs *engine)
2007 {
2008         return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
2009 }
2010
2011 /**
2012  * i915_reset_engine - reset GPU engine to recover from a hang
2013  * @engine: engine to reset
2014  * @msg: reason for GPU reset; or NULL for no dev_notice()
2015  *
2016  * Reset a specific GPU engine. Useful if a hang is detected.
2017  * Returns zero on successful reset or otherwise an error code.
2018  *
2019  * Procedure is:
2020  *  - identifies the request that caused the hang and it is dropped
2021  *  - reset engine (which will force the engine to idle)
2022  *  - re-init/configure engine
2023  */
2024 int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
2025 {
2026         struct i915_gpu_error *error = &engine->i915->gpu_error;
2027         struct i915_request *active_request;
2028         int ret;
2029
2030         GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);
2031         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
2032
2033         active_request = i915_gem_reset_prepare_engine(engine);
2034         if (IS_ERR_OR_NULL(active_request)) {
2035                 /* Either the previous reset failed, or we pardon the reset. */
2036                 ret = PTR_ERR(active_request);
2037                 goto out;
2038         }
2039
2040         if (msg)
2041                 dev_notice(engine->i915->drm.dev,
2042                            "Resetting %s for %s\n", engine->name, msg);
2043         error->reset_engine_count[engine->id]++;
2044
2045         if (!engine->i915->guc.execbuf_client)
2046                 ret = intel_gt_reset_engine(engine->i915, engine);
2047         else
2048                 ret = intel_guc_reset_engine(&engine->i915->guc, engine);
2049         if (ret) {
2050                 /* If we fail here, we expect to fallback to a global reset */
2051                 DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
2052                                  engine->i915->guc.execbuf_client ? "GuC " : "",
2053                                  engine->name, ret);
2054                 goto out;
2055         }
2056
2057         /*
2058          * The request that caused the hang is stuck on elsp, we know the
2059          * active request and can drop it, adjust head to skip the offending
2060          * request to resume executing remaining requests in the queue.
2061          */
2062         i915_gem_reset_engine(engine, active_request, true);
2063
2064         /*
2065          * The engine and its registers (and workarounds in case of render)
2066          * have been reset to their default values. Follow the init_ring
2067          * process to program RING_MODE, HWSP and re-enable submission.
2068          */
2069         ret = engine->init_hw(engine);
2070         if (ret)
2071                 goto out;
2072
2073 out:
2074         i915_gem_reset_finish_engine(engine);
2075         return ret;
2076 }
2077
2078 static int i915_pm_prepare(struct device *kdev)
2079 {
2080         struct pci_dev *pdev = to_pci_dev(kdev);
2081         struct drm_device *dev = pci_get_drvdata(pdev);
2082
2083         if (!dev) {
2084                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2085                 return -ENODEV;
2086         }
2087
2088         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2089                 return 0;
2090
2091         return i915_drm_prepare(dev);
2092 }
2093
2094 static int i915_pm_suspend(struct device *kdev)
2095 {
2096         struct pci_dev *pdev = to_pci_dev(kdev);
2097         struct drm_device *dev = pci_get_drvdata(pdev);
2098
2099         if (!dev) {
2100                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2101                 return -ENODEV;
2102         }
2103
2104         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2105                 return 0;
2106
2107         return i915_drm_suspend(dev);
2108 }
2109
2110 static int i915_pm_suspend_late(struct device *kdev)
2111 {
2112         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2113
2114         /*
2115          * We have a suspend ordering issue with the snd-hda driver also
2116          * requiring our device to be power up. Due to the lack of a
2117          * parent/child relationship we currently solve this with an late
2118          * suspend hook.
2119          *
2120          * FIXME: This should be solved with a special hdmi sink device or
2121          * similar so that power domains can be employed.
2122          */
2123         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2124                 return 0;
2125
2126         return i915_drm_suspend_late(dev, false);
2127 }
2128
2129 static int i915_pm_poweroff_late(struct device *kdev)
2130 {
2131         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2132
2133         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2134                 return 0;
2135
2136         return i915_drm_suspend_late(dev, true);
2137 }
2138
2139 static int i915_pm_resume_early(struct device *kdev)
2140 {
2141         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2142
2143         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2144                 return 0;
2145
2146         return i915_drm_resume_early(dev);
2147 }
2148
2149 static int i915_pm_resume(struct device *kdev)
2150 {
2151         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2152
2153         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2154                 return 0;
2155
2156         return i915_drm_resume(dev);
2157 }
2158
2159 /* freeze: before creating the hibernation_image */
2160 static int i915_pm_freeze(struct device *kdev)
2161 {
2162         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2163         int ret;
2164
2165         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2166                 ret = i915_drm_suspend(dev);
2167                 if (ret)
2168                         return ret;
2169         }
2170
2171         ret = i915_gem_freeze(kdev_to_i915(kdev));
2172         if (ret)
2173                 return ret;
2174
2175         return 0;
2176 }
2177
2178 static int i915_pm_freeze_late(struct device *kdev)
2179 {
2180         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2181         int ret;
2182
2183         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2184                 ret = i915_drm_suspend_late(dev, true);
2185                 if (ret)
2186                         return ret;
2187         }
2188
2189         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2190         if (ret)
2191                 return ret;
2192
2193         return 0;
2194 }
2195
2196 /* thaw: called after creating the hibernation image, but before turning off. */
2197 static int i915_pm_thaw_early(struct device *kdev)
2198 {
2199         return i915_pm_resume_early(kdev);
2200 }
2201
2202 static int i915_pm_thaw(struct device *kdev)
2203 {
2204         return i915_pm_resume(kdev);
2205 }
2206
2207 /* restore: called after loading the hibernation image. */
2208 static int i915_pm_restore_early(struct device *kdev)
2209 {
2210         return i915_pm_resume_early(kdev);
2211 }
2212
2213 static int i915_pm_restore(struct device *kdev)
2214 {
2215         return i915_pm_resume(kdev);
2216 }
2217
2218 /*
2219  * Save all Gunit registers that may be lost after a D3 and a subsequent
2220  * S0i[R123] transition. The list of registers needing a save/restore is
2221  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2222  * registers in the following way:
2223  * - Driver: saved/restored by the driver
2224  * - Punit : saved/restored by the Punit firmware
2225  * - No, w/o marking: no need to save/restore, since the register is R/O or
2226  *                    used internally by the HW in a way that doesn't depend
2227  *                    keeping the content across a suspend/resume.
2228  * - Debug : used for debugging
2229  *
2230  * We save/restore all registers marked with 'Driver', with the following
2231  * exceptions:
2232  * - Registers out of use, including also registers marked with 'Debug'.
2233  *   These have no effect on the driver's operation, so we don't save/restore
2234  *   them to reduce the overhead.
2235  * - Registers that are fully setup by an initialization function called from
2236  *   the resume path. For example many clock gating and RPS/RC6 registers.
2237  * - Registers that provide the right functionality with their reset defaults.
2238  *
2239  * TODO: Except for registers that based on the above 3 criteria can be safely
2240  * ignored, we save/restore all others, practically treating the HW context as
2241  * a black-box for the driver. Further investigation is needed to reduce the
2242  * saved/restored registers even further, by following the same 3 criteria.
2243  */
2244 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2245 {
2246         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2247         int i;
2248
2249         /* GAM 0x4000-0x4770 */
2250         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2251         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2252         s->arb_mode             = I915_READ(ARB_MODE);
2253         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2254         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2255
2256         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2257                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2258
2259         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2260         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2261
2262         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2263         s->ecochk               = I915_READ(GAM_ECOCHK);
2264         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2265         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2266
2267         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2268
2269         /* MBC 0x9024-0x91D0, 0x8500 */
2270         s->g3dctl               = I915_READ(VLV_G3DCTL);
2271         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2272         s->mbctl                = I915_READ(GEN6_MBCTL);
2273
2274         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2275         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2276         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2277         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2278         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2279         s->rstctl               = I915_READ(GEN6_RSTCTL);
2280         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2281
2282         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2283         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2284         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2285         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2286         s->ecobus               = I915_READ(ECOBUS);
2287         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2288         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2289         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2290         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2291         s->rcedata              = I915_READ(VLV_RCEDATA);
2292         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2293
2294         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2295         s->gt_imr               = I915_READ(GTIMR);
2296         s->gt_ier               = I915_READ(GTIER);
2297         s->pm_imr               = I915_READ(GEN6_PMIMR);
2298         s->pm_ier               = I915_READ(GEN6_PMIER);
2299
2300         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2301                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2302
2303         /* GT SA CZ domain, 0x100000-0x138124 */
2304         s->tilectl              = I915_READ(TILECTL);
2305         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2306         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2307         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2308         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2309
2310         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2311         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2312         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2313         s->pcbr                 = I915_READ(VLV_PCBR);
2314         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2315
2316         /*
2317          * Not saving any of:
2318          * DFT,         0x9800-0x9EC0
2319          * SARB,        0xB000-0xB1FC
2320          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2321          * PCI CFG
2322          */
2323 }
2324
2325 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2326 {
2327         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2328         u32 val;
2329         int i;
2330
2331         /* GAM 0x4000-0x4770 */
2332         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2333         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2334         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2335         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2336         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2337
2338         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2339                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2340
2341         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2342         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2343
2344         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2345         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2346         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2347         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2348
2349         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2350
2351         /* MBC 0x9024-0x91D0, 0x8500 */
2352         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2353         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2354         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2355
2356         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2357         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2358         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2359         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2360         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2361         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2362         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2363
2364         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2365         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2366         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2367         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2368         I915_WRITE(ECOBUS,              s->ecobus);
2369         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2370         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2371         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2372         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2373         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2374         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2375
2376         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2377         I915_WRITE(GTIMR,               s->gt_imr);
2378         I915_WRITE(GTIER,               s->gt_ier);
2379         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2380         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2381
2382         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2383                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2384
2385         /* GT SA CZ domain, 0x100000-0x138124 */
2386         I915_WRITE(TILECTL,                     s->tilectl);
2387         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2388         /*
2389          * Preserve the GT allow wake and GFX force clock bit, they are not
2390          * be restored, as they are used to control the s0ix suspend/resume
2391          * sequence by the caller.
2392          */
2393         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2394         val &= VLV_GTLC_ALLOWWAKEREQ;
2395         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2396         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2397
2398         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2399         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2400         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2401         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2402
2403         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2404
2405         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2406         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2407         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2408         I915_WRITE(VLV_PCBR,                    s->pcbr);
2409         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2410 }
2411
2412 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2413                                   u32 mask, u32 val)
2414 {
2415         /* The HW does not like us polling for PW_STATUS frequently, so
2416          * use the sleeping loop rather than risk the busy spin within
2417          * intel_wait_for_register().
2418          *
2419          * Transitioning between RC6 states should be at most 2ms (see
2420          * valleyview_enable_rps) so use a 3ms timeout.
2421          */
2422         return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2423                         3);
2424 }
2425
2426 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2427 {
2428         u32 val;
2429         int err;
2430
2431         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2432         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2433         if (force_on)
2434                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2435         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2436
2437         if (!force_on)
2438                 return 0;
2439
2440         err = intel_wait_for_register(dev_priv,
2441                                       VLV_GTLC_SURVIVABILITY_REG,
2442                                       VLV_GFX_CLK_STATUS_BIT,
2443                                       VLV_GFX_CLK_STATUS_BIT,
2444                                       20);
2445         if (err)
2446                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2447                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2448
2449         return err;
2450 }
2451
2452 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2453 {
2454         u32 mask;
2455         u32 val;
2456         int err;
2457
2458         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2459         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2460         if (allow)
2461                 val |= VLV_GTLC_ALLOWWAKEREQ;
2462         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2463         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2464
2465         mask = VLV_GTLC_ALLOWWAKEACK;
2466         val = allow ? mask : 0;
2467
2468         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2469         if (err)
2470                 DRM_ERROR("timeout disabling GT waking\n");
2471
2472         return err;
2473 }
2474
2475 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2476                                   bool wait_for_on)
2477 {
2478         u32 mask;
2479         u32 val;
2480
2481         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2482         val = wait_for_on ? mask : 0;
2483
2484         /*
2485          * RC6 transitioning can be delayed up to 2 msec (see
2486          * valleyview_enable_rps), use 3 msec for safety.
2487          *
2488          * This can fail to turn off the rc6 if the GPU is stuck after a failed
2489          * reset and we are trying to force the machine to sleep.
2490          */
2491         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2492                 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2493                                  onoff(wait_for_on));
2494 }
2495
2496 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2497 {
2498         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2499                 return;
2500
2501         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2502         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2503 }
2504
2505 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2506 {
2507         u32 mask;
2508         int err;
2509
2510         /*
2511          * Bspec defines the following GT well on flags as debug only, so
2512          * don't treat them as hard failures.
2513          */
2514         vlv_wait_for_gt_wells(dev_priv, false);
2515
2516         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2517         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2518
2519         vlv_check_no_gt_access(dev_priv);
2520
2521         err = vlv_force_gfx_clock(dev_priv, true);
2522         if (err)
2523                 goto err1;
2524
2525         err = vlv_allow_gt_wake(dev_priv, false);
2526         if (err)
2527                 goto err2;
2528
2529         if (!IS_CHERRYVIEW(dev_priv))
2530                 vlv_save_gunit_s0ix_state(dev_priv);
2531
2532         err = vlv_force_gfx_clock(dev_priv, false);
2533         if (err)
2534                 goto err2;
2535
2536         return 0;
2537
2538 err2:
2539         /* For safety always re-enable waking and disable gfx clock forcing */
2540         vlv_allow_gt_wake(dev_priv, true);
2541 err1:
2542         vlv_force_gfx_clock(dev_priv, false);
2543
2544         return err;
2545 }
2546
2547 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2548                                 bool rpm_resume)
2549 {
2550         int err;
2551         int ret;
2552
2553         /*
2554          * If any of the steps fail just try to continue, that's the best we
2555          * can do at this point. Return the first error code (which will also
2556          * leave RPM permanently disabled).
2557          */
2558         ret = vlv_force_gfx_clock(dev_priv, true);
2559
2560         if (!IS_CHERRYVIEW(dev_priv))
2561                 vlv_restore_gunit_s0ix_state(dev_priv);
2562
2563         err = vlv_allow_gt_wake(dev_priv, true);
2564         if (!ret)
2565                 ret = err;
2566
2567         err = vlv_force_gfx_clock(dev_priv, false);
2568         if (!ret)
2569                 ret = err;
2570
2571         vlv_check_no_gt_access(dev_priv);
2572
2573         if (rpm_resume)
2574                 intel_init_clock_gating(dev_priv);
2575
2576         return ret;
2577 }
2578
2579 static int intel_runtime_suspend(struct device *kdev)
2580 {
2581         struct pci_dev *pdev = to_pci_dev(kdev);
2582         struct drm_device *dev = pci_get_drvdata(pdev);
2583         struct drm_i915_private *dev_priv = to_i915(dev);
2584         int ret;
2585
2586         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2587                 return -ENODEV;
2588
2589         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2590                 return -ENODEV;
2591
2592         DRM_DEBUG_KMS("Suspending device\n");
2593
2594         disable_rpm_wakeref_asserts(dev_priv);
2595
2596         /*
2597          * We are safe here against re-faults, since the fault handler takes
2598          * an RPM reference.
2599          */
2600         i915_gem_runtime_suspend(dev_priv);
2601
2602         intel_uc_suspend(dev_priv);
2603
2604         intel_runtime_pm_disable_interrupts(dev_priv);
2605
2606         intel_uncore_suspend(dev_priv);
2607
2608         ret = 0;
2609         if (IS_GEN9_LP(dev_priv)) {
2610                 bxt_display_core_uninit(dev_priv);
2611                 bxt_enable_dc9(dev_priv);
2612         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2613                 hsw_enable_pc8(dev_priv);
2614         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2615                 ret = vlv_suspend_complete(dev_priv);
2616         }
2617
2618         if (ret) {
2619                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2620                 intel_uncore_runtime_resume(dev_priv);
2621
2622                 intel_runtime_pm_enable_interrupts(dev_priv);
2623
2624                 intel_uc_resume(dev_priv);
2625
2626                 i915_gem_init_swizzling(dev_priv);
2627                 i915_gem_restore_fences(dev_priv);
2628
2629                 enable_rpm_wakeref_asserts(dev_priv);
2630
2631                 return ret;
2632         }
2633
2634         enable_rpm_wakeref_asserts(dev_priv);
2635         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2636
2637         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2638                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2639
2640         dev_priv->runtime_pm.suspended = true;
2641
2642         /*
2643          * FIXME: We really should find a document that references the arguments
2644          * used below!
2645          */
2646         if (IS_BROADWELL(dev_priv)) {
2647                 /*
2648                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2649                  * being detected, and the call we do at intel_runtime_resume()
2650                  * won't be able to restore them. Since PCI_D3hot matches the
2651                  * actual specification and appears to be working, use it.
2652                  */
2653                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2654         } else {
2655                 /*
2656                  * current versions of firmware which depend on this opregion
2657                  * notification have repurposed the D1 definition to mean
2658                  * "runtime suspended" vs. what you would normally expect (D3)
2659                  * to distinguish it from notifications that might be sent via
2660                  * the suspend path.
2661                  */
2662                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2663         }
2664
2665         assert_forcewakes_inactive(dev_priv);
2666
2667         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2668                 intel_hpd_poll_init(dev_priv);
2669
2670         DRM_DEBUG_KMS("Device suspended\n");
2671         return 0;
2672 }
2673
2674 static int intel_runtime_resume(struct device *kdev)
2675 {
2676         struct pci_dev *pdev = to_pci_dev(kdev);
2677         struct drm_device *dev = pci_get_drvdata(pdev);
2678         struct drm_i915_private *dev_priv = to_i915(dev);
2679         int ret = 0;
2680
2681         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2682                 return -ENODEV;
2683
2684         DRM_DEBUG_KMS("Resuming device\n");
2685
2686         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2687         disable_rpm_wakeref_asserts(dev_priv);
2688
2689         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2690         dev_priv->runtime_pm.suspended = false;
2691         if (intel_uncore_unclaimed_mmio(dev_priv))
2692                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2693
2694         if (IS_GEN9_LP(dev_priv)) {
2695                 bxt_disable_dc9(dev_priv);
2696                 bxt_display_core_init(dev_priv, true);
2697                 if (dev_priv->csr.dmc_payload &&
2698                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2699                         gen9_enable_dc5(dev_priv);
2700         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2701                 hsw_disable_pc8(dev_priv);
2702         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2703                 ret = vlv_resume_prepare(dev_priv, true);
2704         }
2705
2706         intel_uncore_runtime_resume(dev_priv);
2707
2708         intel_runtime_pm_enable_interrupts(dev_priv);
2709
2710         intel_uc_resume(dev_priv);
2711
2712         /*
2713          * No point of rolling back things in case of an error, as the best
2714          * we can do is to hope that things will still work (and disable RPM).
2715          */
2716         i915_gem_init_swizzling(dev_priv);
2717         i915_gem_restore_fences(dev_priv);
2718
2719         /*
2720          * On VLV/CHV display interrupts are part of the display
2721          * power well, so hpd is reinitialized from there. For
2722          * everyone else do it here.
2723          */
2724         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2725                 intel_hpd_init(dev_priv);
2726
2727         intel_enable_ipc(dev_priv);
2728
2729         enable_rpm_wakeref_asserts(dev_priv);
2730
2731         if (ret)
2732                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2733         else
2734                 DRM_DEBUG_KMS("Device resumed\n");
2735
2736         return ret;
2737 }
2738
2739 const struct dev_pm_ops i915_pm_ops = {
2740         /*
2741          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2742          * PMSG_RESUME]
2743          */
2744         .prepare = i915_pm_prepare,
2745         .suspend = i915_pm_suspend,
2746         .suspend_late = i915_pm_suspend_late,
2747         .resume_early = i915_pm_resume_early,
2748         .resume = i915_pm_resume,
2749
2750         /*
2751          * S4 event handlers
2752          * @freeze, @freeze_late    : called (1) before creating the
2753          *                            hibernation image [PMSG_FREEZE] and
2754          *                            (2) after rebooting, before restoring
2755          *                            the image [PMSG_QUIESCE]
2756          * @thaw, @thaw_early       : called (1) after creating the hibernation
2757          *                            image, before writing it [PMSG_THAW]
2758          *                            and (2) after failing to create or
2759          *                            restore the image [PMSG_RECOVER]
2760          * @poweroff, @poweroff_late: called after writing the hibernation
2761          *                            image, before rebooting [PMSG_HIBERNATE]
2762          * @restore, @restore_early : called after rebooting and restoring the
2763          *                            hibernation image [PMSG_RESTORE]
2764          */
2765         .freeze = i915_pm_freeze,
2766         .freeze_late = i915_pm_freeze_late,
2767         .thaw_early = i915_pm_thaw_early,
2768         .thaw = i915_pm_thaw,
2769         .poweroff = i915_pm_suspend,
2770         .poweroff_late = i915_pm_poweroff_late,
2771         .restore_early = i915_pm_restore_early,
2772         .restore = i915_pm_restore,
2773
2774         /* S0ix (via runtime suspend) event handlers */
2775         .runtime_suspend = intel_runtime_suspend,
2776         .runtime_resume = intel_runtime_resume,
2777 };
2778
2779 static const struct vm_operations_struct i915_gem_vm_ops = {
2780         .fault = i915_gem_fault,
2781         .open = drm_gem_vm_open,
2782         .close = drm_gem_vm_close,
2783 };
2784
2785 static const struct file_operations i915_driver_fops = {
2786         .owner = THIS_MODULE,
2787         .open = drm_open,
2788         .release = drm_release,
2789         .unlocked_ioctl = drm_ioctl,
2790         .mmap = drm_gem_mmap,
2791         .poll = drm_poll,
2792         .read = drm_read,
2793         .compat_ioctl = i915_compat_ioctl,
2794         .llseek = noop_llseek,
2795 };
2796
2797 static int
2798 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2799                           struct drm_file *file)
2800 {
2801         return -ENODEV;
2802 }
2803
2804 static const struct drm_ioctl_desc i915_ioctls[] = {
2805         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2806         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2807         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2808         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2809         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2810         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2811         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2812         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2813         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2814         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2815         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2816         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2817         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2818         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2819         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2820         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2821         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2822         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2823         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
2824         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2825         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2826         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2827         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2828         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2829         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2830         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2831         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2832         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2833         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2834         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2835         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2836         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2837         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2838         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2839         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2840         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2841         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2842         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2843         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2844         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2845         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2846         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2847         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2848         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2849         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2850         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2851         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2852         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2853         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2854         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2855         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2856         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2857         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2858         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2859         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2860         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2861 };
2862
2863 static struct drm_driver driver = {
2864         /* Don't use MTRRs here; the Xserver or userspace app should
2865          * deal with them for Intel hardware.
2866          */
2867         .driver_features =
2868             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2869             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2870         .release = i915_driver_release,
2871         .open = i915_driver_open,
2872         .lastclose = i915_driver_lastclose,
2873         .postclose = i915_driver_postclose,
2874
2875         .gem_close_object = i915_gem_close_object,
2876         .gem_free_object_unlocked = i915_gem_free_object,
2877         .gem_vm_ops = &i915_gem_vm_ops,
2878
2879         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2880         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2881         .gem_prime_export = i915_gem_prime_export,
2882         .gem_prime_import = i915_gem_prime_import,
2883
2884         .dumb_create = i915_gem_dumb_create,
2885         .dumb_map_offset = i915_gem_mmap_gtt,
2886         .ioctls = i915_ioctls,
2887         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2888         .fops = &i915_driver_fops,
2889         .name = DRIVER_NAME,
2890         .desc = DRIVER_DESC,
2891         .date = DRIVER_DATE,
2892         .major = DRIVER_MAJOR,
2893         .minor = DRIVER_MINOR,
2894         .patchlevel = DRIVER_PATCHLEVEL,
2895 };
2896
2897 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2898 #include "selftests/mock_drm.c"
2899 #endif