drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_atomic_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "i915_drv.h"
  50 #include "i915_trace.h"
  51 #include "i915_vgpu.h"
  52 #include "intel_drv.h"
  53 #include "intel_uc.h"
  54
  55 static struct drm_driver driver;
  56
  57 static unsigned int i915_load_fail_count;
  58
  59 bool __i915_inject_load_failure(const char *func, int line)
  60 {
  61         if (i915_load_fail_count >= i915.inject_load_failure)
  62                 return false;
  63
  64         if (++i915_load_fail_count == i915.inject_load_failure) {
  65                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  66                          i915.inject_load_failure, func, line);
  67                 return true;
  68         }
  69
  70         return false;
  71 }
  72
  73 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  74 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  75                     "providing the dmesg log by booting with drm.debug=0xf"
  76
  77 void
  78 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  79               const char *fmt, ...)
  80 {
  81         static bool shown_bug_once;
  82         struct device *kdev = dev_priv->drm.dev;
  83         bool is_error = level[1] <= KERN_ERR[1];
  84         bool is_debug = level[1] == KERN_DEBUG[1];
  85         struct va_format vaf;
  86         va_list args;
  87
  88         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  89                 return;
  90
  91         va_start(args, fmt);
  92
  93         vaf.fmt = fmt;
  94         vaf.va = &args;
  95
  96         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
  97                    __builtin_return_address(0), &vaf);
  98
  99         if (is_error && !shown_bug_once) {
 100                 dev_notice(kdev, "%s", FDO_BUG_MSG);
 101                 shown_bug_once = true;
 102         }
 103
 104         va_end(args);
 105 }
 106
 107 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 108 {
 109         return i915.inject_load_failure &&
 110                i915_load_fail_count == i915.inject_load_failure;
 111 }
 112
 113 #define i915_load_error(dev_priv, fmt, ...)                                  \
 114         __i915_printk(dev_priv,                                              \
 115                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 116                       fmt, ##__VA_ARGS__)
 117
 118
 119 static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 120 {
 121         enum intel_pch ret = PCH_NOP;
 122
 123         /*
 124          * In a virtualized passthrough environment we can be in a
 125          * setup where the ISA bridge is not able to be passed through.
 126          * In this case, a south bridge can be emulated and we have to
 127          * make an educated guess as to which PCH is really there.
 128          */
 129
 130         if (IS_GEN5(dev_priv)) {
 131                 ret = PCH_IBX;
 132                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 133         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
 134                 ret = PCH_CPT;
 135                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 136         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 137                 ret = PCH_LPT;
 138                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 139         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 140                 ret = PCH_SPT;
 141                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 142         }
 143
 144         return ret;
 145 }
 146
 147 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 148 {
 149         struct pci_dev *pch = NULL;
 150
 151         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 152          * (which really amounts to a PCH but no South Display).
 153          */
 154         if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 155                 dev_priv->pch_type = PCH_NOP;
 156                 return;
 157         }
 158
 159         /*
 160          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 161          * make graphics device passthrough work easy for VMM, that only
 162          * need to expose ISA bridge to let driver know the real hardware
 163          * underneath. This is a requirement from virtualization team.
 164          *
 165          * In some virtualized environments (e.g. XEN), there is irrelevant
 166          * ISA bridge in the system. To work reliably, we should scan trhough
 167          * all the ISA bridge devices and check for the first match, instead
 168          * of only checking the first one.
 169          */
 170         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 171                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 172                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 173                         dev_priv->pch_id = id;
 174
 175                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 176                                 dev_priv->pch_type = PCH_IBX;
 177                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 178                                 WARN_ON(!IS_GEN5(dev_priv));
 179                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 180                                 dev_priv->pch_type = PCH_CPT;
 181                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 182                                 WARN_ON(!(IS_GEN6(dev_priv) ||
 183                                         IS_IVYBRIDGE(dev_priv)));
 184                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 185                                 /* PantherPoint is CPT compatible */
 186                                 dev_priv->pch_type = PCH_CPT;
 187                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 188                                 WARN_ON(!(IS_GEN6(dev_priv) ||
 189                                         IS_IVYBRIDGE(dev_priv)));
 190                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 191                                 dev_priv->pch_type = PCH_LPT;
 192                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 193                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 194                                         !IS_BROADWELL(dev_priv));
 195                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 196                                         IS_BDW_ULT(dev_priv));
 197                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 198                                 dev_priv->pch_type = PCH_LPT;
 199                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 200                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 201                                         !IS_BROADWELL(dev_priv));
 202                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 203                                         !IS_BDW_ULT(dev_priv));
 204                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 205                                 dev_priv->pch_type = PCH_SPT;
 206                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 207                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 208                                         !IS_KABYLAKE(dev_priv));
 209                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 210                                 dev_priv->pch_type = PCH_SPT;
 211                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 212                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 213                                         !IS_KABYLAKE(dev_priv));
 214                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
 215                                 dev_priv->pch_type = PCH_KBP;
 216                                 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
 217                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 218                                         !IS_KABYLAKE(dev_priv));
 219                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 220                                    (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 221                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 222                                     pch->subsystem_vendor ==
 223                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 224                                     pch->subsystem_device ==
 225                                             PCI_SUBDEVICE_ID_QEMU)) {
 226                                 dev_priv->pch_type =
 227                                         intel_virt_detect_pch(dev_priv);
 228                         } else
 229                                 continue;
 230
 231                         break;
 232                 }
 233         }
 234         if (!pch)
 235                 DRM_DEBUG_KMS("No PCH found.\n");
 236
 237         pci_dev_put(pch);
 238 }
 239
 240 static int i915_getparam(struct drm_device *dev, void *data,
 241                          struct drm_file *file_priv)
 242 {
 243         struct drm_i915_private *dev_priv = to_i915(dev);
 244         struct pci_dev *pdev = dev_priv->drm.pdev;
 245         drm_i915_getparam_t *param = data;
 246         int value;
 247
 248         switch (param->param) {
 249         case I915_PARAM_IRQ_ACTIVE:
 250         case I915_PARAM_ALLOW_BATCHBUFFER:
 251         case I915_PARAM_LAST_DISPATCH:
 252                 /* Reject all old ums/dri params. */
 253                 return -ENODEV;
 254         case I915_PARAM_CHIPSET_ID:
 255                 value = pdev->device;
 256                 break;
 257         case I915_PARAM_REVISION:
 258                 value = pdev->revision;
 259                 break;
 260         case I915_PARAM_NUM_FENCES_AVAIL:
 261                 value = dev_priv->num_fence_regs;
 262                 break;
 263         case I915_PARAM_HAS_OVERLAY:
 264                 value = dev_priv->overlay ? 1 : 0;
 265                 break;
 266         case I915_PARAM_HAS_BSD:
 267                 value = !!dev_priv->engine[VCS];
 268                 break;
 269         case I915_PARAM_HAS_BLT:
 270                 value = !!dev_priv->engine[BCS];
 271                 break;
 272         case I915_PARAM_HAS_VEBOX:
 273                 value = !!dev_priv->engine[VECS];
 274                 break;
 275         case I915_PARAM_HAS_BSD2:
 276                 value = !!dev_priv->engine[VCS2];
 277                 break;
 278         case I915_PARAM_HAS_EXEC_CONSTANTS:
 279                 value = INTEL_GEN(dev_priv) >= 4;
 280                 break;
 281         case I915_PARAM_HAS_LLC:
 282                 value = HAS_LLC(dev_priv);
 283                 break;
 284         case I915_PARAM_HAS_WT:
 285                 value = HAS_WT(dev_priv);
 286                 break;
 287         case I915_PARAM_HAS_ALIASING_PPGTT:
 288                 value = USES_PPGTT(dev_priv);
 289                 break;
 290         case I915_PARAM_HAS_SEMAPHORES:
 291                 value = i915.semaphores;
 292                 break;
 293         case I915_PARAM_HAS_SECURE_BATCHES:
 294                 value = capable(CAP_SYS_ADMIN);
 295                 break;
 296         case I915_PARAM_CMD_PARSER_VERSION:
 297                 value = i915_cmd_parser_get_version(dev_priv);
 298                 break;
 299         case I915_PARAM_SUBSLICE_TOTAL:
 300                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 301                 if (!value)
 302                         return -ENODEV;
 303                 break;
 304         case I915_PARAM_EU_TOTAL:
 305                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 306                 if (!value)
 307                         return -ENODEV;
 308                 break;
 309         case I915_PARAM_HAS_GPU_RESET:
 310                 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
 311                 break;
 312         case I915_PARAM_HAS_RESOURCE_STREAMER:
 313                 value = HAS_RESOURCE_STREAMER(dev_priv);
 314                 break;
 315         case I915_PARAM_HAS_POOLED_EU:
 316                 value = HAS_POOLED_EU(dev_priv);
 317                 break;
 318         case I915_PARAM_MIN_EU_IN_POOL:
 319                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 320                 break;
 321         case I915_PARAM_HUC_STATUS:
 322                 intel_runtime_pm_get(dev_priv);
 323                 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
 324                 intel_runtime_pm_put(dev_priv);
 325                 break;
 326         case I915_PARAM_MMAP_GTT_VERSION:
 327                 /* Though we've started our numbering from 1, and so class all
 328                  * earlier versions as 0, in effect their value is undefined as
 329                  * the ioctl will report EINVAL for the unknown param!
 330                  */
 331                 value = i915_gem_mmap_gtt_version();
 332                 break;
 333         case I915_PARAM_HAS_SCHEDULER:
 334                 value = dev_priv->engine[RCS] &&
 335                         dev_priv->engine[RCS]->schedule;
 336                 break;
 337         case I915_PARAM_MMAP_VERSION:
 338                 /* Remember to bump this if the version changes! */
 339         case I915_PARAM_HAS_GEM:
 340         case I915_PARAM_HAS_PAGEFLIPPING:
 341         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 342         case I915_PARAM_HAS_RELAXED_FENCING:
 343         case I915_PARAM_HAS_COHERENT_RINGS:
 344         case I915_PARAM_HAS_RELAXED_DELTA:
 345         case I915_PARAM_HAS_GEN7_SOL_RESET:
 346         case I915_PARAM_HAS_WAIT_TIMEOUT:
 347         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 348         case I915_PARAM_HAS_PINNED_BATCHES:
 349         case I915_PARAM_HAS_EXEC_NO_RELOC:
 350         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 351         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 352         case I915_PARAM_HAS_EXEC_SOFTPIN:
 353         case I915_PARAM_HAS_EXEC_ASYNC:
 354         case I915_PARAM_HAS_EXEC_FENCE:
 355                 /* For the time being all of these are always true;
 356                  * if some supported hardware does not have one of these
 357                  * features this value needs to be provided from
 358                  * INTEL_INFO(), a feature macro, or similar.
 359                  */
 360                 value = 1;
 361                 break;
 362         default:
 363                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 364                 return -EINVAL;
 365         }
 366
 367         if (put_user(value, param->value))
 368                 return -EFAULT;
 369
 370         return 0;
 371 }
 372
 373 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 374 {
 375         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 376         if (!dev_priv->bridge_dev) {
 377                 DRM_ERROR("bridge device not found\n");
 378                 return -1;
 379         }
 380         return 0;
 381 }
 382
 383 /* Allocate space for the MCH regs if needed, return nonzero on error */
 384 static int
 385 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 386 {
 387         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 388         u32 temp_lo, temp_hi = 0;
 389         u64 mchbar_addr;
 390         int ret;
 391
 392         if (INTEL_GEN(dev_priv) >= 4)
 393                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 394         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 395         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 396
 397         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 398 #ifdef CONFIG_PNP
 399         if (mchbar_addr &&
 400             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 401                 return 0;
 402 #endif
 403
 404         /* Get some space for it */
 405         dev_priv->mch_res.name = "i915 MCHBAR";
 406         dev_priv->mch_res.flags = IORESOURCE_MEM;
 407         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 408                                      &dev_priv->mch_res,
 409                                      MCHBAR_SIZE, MCHBAR_SIZE,
 410                                      PCIBIOS_MIN_MEM,
 411                                      0, pcibios_align_resource,
 412                                      dev_priv->bridge_dev);
 413         if (ret) {
 414                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 415                 dev_priv->mch_res.start = 0;
 416                 return ret;
 417         }
 418
 419         if (INTEL_GEN(dev_priv) >= 4)
 420                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 421                                        upper_32_bits(dev_priv->mch_res.start));
 422
 423         pci_write_config_dword(dev_priv->bridge_dev, reg,
 424                                lower_32_bits(dev_priv->mch_res.start));
 425         return 0;
 426 }
 427
 428 /* Setup MCHBAR if possible, return true if we should disable it again */
 429 static void
 430 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 431 {
 432         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 433         u32 temp;
 434         bool enabled;
 435
 436         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 437                 return;
 438
 439         dev_priv->mchbar_need_disable = false;
 440
 441         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 442                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 443                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 444         } else {
 445                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 446                 enabled = temp & 1;
 447         }
 448
 449         /* If it's already enabled, don't have to do anything */
 450         if (enabled)
 451                 return;
 452
 453         if (intel_alloc_mchbar_resource(dev_priv))
 454                 return;
 455
 456         dev_priv->mchbar_need_disable = true;
 457
 458         /* Space is allocated or reserved, so enable it. */
 459         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 460                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 461                                        temp | DEVEN_MCHBAR_EN);
 462         } else {
 463                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 464                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 465         }
 466 }
 467
 468 static void
 469 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 470 {
 471         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 472
 473         if (dev_priv->mchbar_need_disable) {
 474                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 475                         u32 deven_val;
 476
 477                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 478                                               &deven_val);
 479                         deven_val &= ~DEVEN_MCHBAR_EN;
 480                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 481                                                deven_val);
 482                 } else {
 483                         u32 mchbar_val;
 484
 485                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 486                                               &mchbar_val);
 487                         mchbar_val &= ~1;
 488                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 489                                                mchbar_val);
 490                 }
 491         }
 492
 493         if (dev_priv->mch_res.start)
 494                 release_resource(&dev_priv->mch_res);
 495 }
 496
 497 /* true = enable decode, false = disable decoder */
 498 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 499 {
 500         struct drm_i915_private *dev_priv = cookie;
 501
 502         intel_modeset_vga_set_state(dev_priv, state);
 503         if (state)
 504                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 505                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 506         else
 507                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 508 }
 509
 510 static int i915_resume_switcheroo(struct drm_device *dev);
 511 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 512
 513 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 514 {
 515         struct drm_device *dev = pci_get_drvdata(pdev);
 516         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 517
 518         if (state == VGA_SWITCHEROO_ON) {
 519                 pr_info("switched on\n");
 520                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 521                 /* i915 resume handler doesn't set to D0 */
 522                 pci_set_power_state(pdev, PCI_D0);
 523                 i915_resume_switcheroo(dev);
 524                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 525         } else {
 526                 pr_info("switched off\n");
 527                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 528                 i915_suspend_switcheroo(dev, pmm);
 529                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 530         }
 531 }
 532
 533 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 534 {
 535         struct drm_device *dev = pci_get_drvdata(pdev);
 536
 537         /*
 538          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 539          * locking inversion with the driver load path. And the access here is
 540          * completely racy anyway. So don't bother with locking for now.
 541          */
 542         return dev->open_count == 0;
 543 }
 544
 545 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 546         .set_gpu_state = i915_switcheroo_set_state,
 547         .reprobe = NULL,
 548         .can_switch = i915_switcheroo_can_switch,
 549 };
 550
 551 static void i915_gem_fini(struct drm_i915_private *dev_priv)
 552 {
 553         mutex_lock(&dev_priv->drm.struct_mutex);
 554         i915_gem_cleanup_engines(dev_priv);
 555         i915_gem_context_fini(dev_priv);
 556         mutex_unlock(&dev_priv->drm.struct_mutex);
 557
 558         i915_gem_drain_freed_objects(dev_priv);
 559
 560         WARN_ON(!list_empty(&dev_priv->context_list));
 561 }
 562
 563 static int i915_load_modeset_init(struct drm_device *dev)
 564 {
 565         struct drm_i915_private *dev_priv = to_i915(dev);
 566         struct pci_dev *pdev = dev_priv->drm.pdev;
 567         int ret;
 568
 569         if (i915_inject_load_failure())
 570                 return -ENODEV;
 571
 572         ret = intel_bios_init(dev_priv);
 573         if (ret)
 574                 DRM_INFO("failed to find VBIOS tables\n");
 575
 576         /* If we have > 1 VGA cards, then we need to arbitrate access
 577          * to the common VGA resources.
 578          *
 579          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 580          * then we do not take part in VGA arbitration and the
 581          * vga_client_register() fails with -ENODEV.
 582          */
 583         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 584         if (ret && ret != -ENODEV)
 585                 goto out;
 586
 587         intel_register_dsm_handler();
 588
 589         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 590         if (ret)
 591                 goto cleanup_vga_client;
 592
 593         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 594         intel_update_rawclk(dev_priv);
 595
 596         intel_power_domains_init_hw(dev_priv, false);
 597
 598         intel_csr_ucode_init(dev_priv);
 599
 600         ret = intel_irq_install(dev_priv);
 601         if (ret)
 602                 goto cleanup_csr;
 603
 604         intel_setup_gmbus(dev_priv);
 605
 606         /* Important: The output setup functions called by modeset_init need
 607          * working irqs for e.g. gmbus and dp aux transfers. */
 608         ret = intel_modeset_init(dev);
 609         if (ret)
 610                 goto cleanup_irq;
 611
 612         intel_huc_init(dev_priv);
 613         intel_guc_init(dev_priv);
 614
 615         ret = i915_gem_init(dev_priv);
 616         if (ret)
 617                 goto cleanup_irq;
 618
 619         intel_modeset_gem_init(dev);
 620
 621         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 622                 return 0;
 623
 624         ret = intel_fbdev_init(dev);
 625         if (ret)
 626                 goto cleanup_gem;
 627
 628         /* Only enable hotplug handling once the fbdev is fully set up. */
 629         intel_hpd_init(dev_priv);
 630
 631         drm_kms_helper_poll_init(dev);
 632
 633         return 0;
 634
 635 cleanup_gem:
 636         if (i915_gem_suspend(dev_priv))
 637                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 638         i915_gem_fini(dev_priv);
 639 cleanup_irq:
 640         intel_guc_fini(dev_priv);
 641         intel_huc_fini(dev_priv);
 642         drm_irq_uninstall(dev);
 643         intel_teardown_gmbus(dev_priv);
 644 cleanup_csr:
 645         intel_csr_ucode_fini(dev_priv);
 646         intel_power_domains_fini(dev_priv);
 647         vga_switcheroo_unregister_client(pdev);
 648 cleanup_vga_client:
 649         vga_client_register(pdev, NULL, NULL, NULL);
 650 out:
 651         return ret;
 652 }
 653
 654 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 655 {
 656         struct apertures_struct *ap;
 657         struct pci_dev *pdev = dev_priv->drm.pdev;
 658         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 659         bool primary;
 660         int ret;
 661
 662         ap = alloc_apertures(1);
 663         if (!ap)
 664                 return -ENOMEM;
 665
 666         ap->ranges[0].base = ggtt->mappable_base;
 667         ap->ranges[0].size = ggtt->mappable_end;
 668
 669         primary =
 670                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 671
 672         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 673
 674         kfree(ap);
 675
 676         return ret;
 677 }
 678
 679 #if !defined(CONFIG_VGA_CONSOLE)
 680 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 681 {
 682         return 0;
 683 }
 684 #elif !defined(CONFIG_DUMMY_CONSOLE)
 685 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 686 {
 687         return -ENODEV;
 688 }
 689 #else
 690 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 691 {
 692         int ret = 0;
 693
 694         DRM_INFO("Replacing VGA console driver\n");
 695
 696         console_lock();
 697         if (con_is_bound(&vga_con))
 698                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 699         if (ret == 0) {
 700                 ret = do_unregister_con_driver(&vga_con);
 701
 702                 /* Ignore "already unregistered". */
 703                 if (ret == -ENODEV)
 704                         ret = 0;
 705         }
 706         console_unlock();
 707
 708         return ret;
 709 }
 710 #endif
 711
 712 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 713 {
 714         /*
 715          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 716          * CHV x1 PHY (DP/HDMI D)
 717          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 718          */
 719         if (IS_CHERRYVIEW(dev_priv)) {
 720                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 721                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 722         } else if (IS_VALLEYVIEW(dev_priv)) {
 723                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 724         }
 725 }
 726
 727 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 728 {
 729         /*
 730          * The i915 workqueue is primarily used for batched retirement of
 731          * requests (and thus managing bo) once the task has been completed
 732          * by the GPU. i915_gem_retire_requests() is called directly when we
 733          * need high-priority retirement, such as waiting for an explicit
 734          * bo.
 735          *
 736          * It is also used for periodic low-priority events, such as
 737          * idle-timers and recording error state.
 738          *
 739          * All tasks on the workqueue are expected to acquire the dev mutex
 740          * so there is no point in running more than one instance of the
 741          * workqueue at any time.  Use an ordered one.
 742          */
 743         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 744         if (dev_priv->wq == NULL)
 745                 goto out_err;
 746
 747         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 748         if (dev_priv->hotplug.dp_wq == NULL)
 749                 goto out_free_wq;
 750
 751         return 0;
 752
 753 out_free_wq:
 754         destroy_workqueue(dev_priv->wq);
 755 out_err:
 756         DRM_ERROR("Failed to allocate workqueues.\n");
 757
 758         return -ENOMEM;
 759 }
 760
 761 static void i915_engines_cleanup(struct drm_i915_private *i915)
 762 {
 763         struct intel_engine_cs *engine;
 764         enum intel_engine_id id;
 765
 766         for_each_engine(engine, i915, id)
 767                 kfree(engine);
 768 }
 769
 770 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 771 {
 772         destroy_workqueue(dev_priv->hotplug.dp_wq);
 773         destroy_workqueue(dev_priv->wq);
 774 }
 775
 776 /*
 777  * We don't keep the workarounds for pre-production hardware, so we expect our
 778  * driver to fail on these machines in one way or another. A little warning on
 779  * dmesg may help both the user and the bug triagers.
 780  */
 781 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 782 {
 783         bool pre = false;
 784
 785         pre |= IS_HSW_EARLY_SDV(dev_priv);
 786         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 787         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 788
 789         if (pre) {
 790                 DRM_ERROR("This is a pre-production stepping. "
 791                           "It may not be fully functional.\n");
 792                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 793         }
 794 }
 795
 796 /**
 797  * i915_driver_init_early - setup state not requiring device access
 798  * @dev_priv: device private
 799  *
 800  * Initialize everything that is a "SW-only" state, that is state not
 801  * requiring accessing the device or exposing the driver via kernel internal
 802  * or userspace interfaces. Example steps belonging here: lock initialization,
 803  * system memory allocation, setting up device specific attributes and
 804  * function hooks not requiring accessing the device.
 805  */
 806 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 807                                   const struct pci_device_id *ent)
 808 {
 809         const struct intel_device_info *match_info =
 810                 (struct intel_device_info *)ent->driver_data;
 811         struct intel_device_info *device_info;
 812         int ret = 0;
 813
 814         if (i915_inject_load_failure())
 815                 return -ENODEV;
 816
 817         /* Setup the write-once "constant" device info */
 818         device_info = mkwrite_device_info(dev_priv);
 819         memcpy(device_info, match_info, sizeof(*device_info));
 820         device_info->device_id = dev_priv->drm.pdev->device;
 821
 822         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 823         device_info->gen_mask = BIT(device_info->gen - 1);
 824
 825         spin_lock_init(&dev_priv->irq_lock);
 826         spin_lock_init(&dev_priv->gpu_error.lock);
 827         mutex_init(&dev_priv->backlight_lock);
 828         spin_lock_init(&dev_priv->uncore.lock);
 829
 830         spin_lock_init(&dev_priv->mm.object_stat_lock);
 831         spin_lock_init(&dev_priv->mmio_flip_lock);
 832         spin_lock_init(&dev_priv->wm.dsparb_lock);
 833         mutex_init(&dev_priv->sb_lock);
 834         mutex_init(&dev_priv->modeset_restore_lock);
 835         mutex_init(&dev_priv->av_mutex);
 836         mutex_init(&dev_priv->wm.wm_mutex);
 837         mutex_init(&dev_priv->pps_mutex);
 838
 839         intel_uc_init_early(dev_priv);
 840         i915_memcpy_init_early(dev_priv);
 841
 842         ret = intel_engines_init_early(dev_priv);
 843         if (ret)
 844                 return ret;
 845
 846         ret = i915_workqueues_init(dev_priv);
 847         if (ret < 0)
 848                 goto err_engines;
 849
 850         ret = intel_gvt_init(dev_priv);
 851         if (ret < 0)
 852                 goto err_workqueues;
 853
 854         /* This must be called before any calls to HAS_PCH_* */
 855         intel_detect_pch(dev_priv);
 856
 857         intel_pm_setup(dev_priv);
 858         intel_init_dpio(dev_priv);
 859         intel_power_domains_init(dev_priv);
 860         intel_irq_init(dev_priv);
 861         intel_hangcheck_init(dev_priv);
 862         intel_init_display_hooks(dev_priv);
 863         intel_init_clock_gating_hooks(dev_priv);
 864         intel_init_audio_hooks(dev_priv);
 865         ret = i915_gem_load_init(dev_priv);
 866         if (ret < 0)
 867                 goto err_gvt;
 868
 869         intel_display_crc_init(dev_priv);
 870
 871         intel_device_info_dump(dev_priv);
 872
 873         intel_detect_preproduction_hw(dev_priv);
 874
 875         i915_perf_init(dev_priv);
 876
 877         return 0;
 878
 879 err_gvt:
 880         intel_gvt_cleanup(dev_priv);
 881 err_workqueues:
 882         i915_workqueues_cleanup(dev_priv);
 883 err_engines:
 884         i915_engines_cleanup(dev_priv);
 885         return ret;
 886 }
 887
 888 /**
 889  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 890  * @dev_priv: device private
 891  */
 892 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 893 {
 894         i915_perf_fini(dev_priv);
 895         i915_gem_load_cleanup(dev_priv);
 896         i915_workqueues_cleanup(dev_priv);
 897         i915_engines_cleanup(dev_priv);
 898 }
 899
 900 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 901 {
 902         struct pci_dev *pdev = dev_priv->drm.pdev;
 903         int mmio_bar;
 904         int mmio_size;
 905
 906         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 907         /*
 908          * Before gen4, the registers and the GTT are behind different BARs.
 909          * However, from gen4 onwards, the registers and the GTT are shared
 910          * in the same BAR, so we want to restrict this ioremap from
 911          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 912          * the register BAR remains the same size for all the earlier
 913          * generations up to Ironlake.
 914          */
 915         if (INTEL_GEN(dev_priv) < 5)
 916                 mmio_size = 512 * 1024;
 917         else
 918                 mmio_size = 2 * 1024 * 1024;
 919         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 920         if (dev_priv->regs == NULL) {
 921                 DRM_ERROR("failed to map registers\n");
 922
 923                 return -EIO;
 924         }
 925
 926         /* Try to make sure MCHBAR is enabled before poking at it */
 927         intel_setup_mchbar(dev_priv);
 928
 929         return 0;
 930 }
 931
 932 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 933 {
 934         struct pci_dev *pdev = dev_priv->drm.pdev;
 935
 936         intel_teardown_mchbar(dev_priv);
 937         pci_iounmap(pdev, dev_priv->regs);
 938 }
 939
 940 /**
 941  * i915_driver_init_mmio - setup device MMIO
 942  * @dev_priv: device private
 943  *
 944  * Setup minimal device state necessary for MMIO accesses later in the
 945  * initialization sequence. The setup here should avoid any other device-wide
 946  * side effects or exposing the driver via kernel internal or user space
 947  * interfaces.
 948  */
 949 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 950 {
 951         int ret;
 952
 953         if (i915_inject_load_failure())
 954                 return -ENODEV;
 955
 956         if (i915_get_bridge_dev(dev_priv))
 957                 return -EIO;
 958
 959         ret = i915_mmio_setup(dev_priv);
 960         if (ret < 0)
 961                 goto put_bridge;
 962
 963         intel_uncore_init(dev_priv);
 964         i915_gem_init_mmio(dev_priv);
 965
 966         return 0;
 967
 968 put_bridge:
 969         pci_dev_put(dev_priv->bridge_dev);
 970
 971         return ret;
 972 }
 973
 974 /**
 975  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
 976  * @dev_priv: device private
 977  */
 978 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
 979 {
 980         intel_uncore_fini(dev_priv);
 981         i915_mmio_cleanup(dev_priv);
 982         pci_dev_put(dev_priv->bridge_dev);
 983 }
 984
 985 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 986 {
 987         i915.enable_execlists =
 988                 intel_sanitize_enable_execlists(dev_priv,
 989                                                 i915.enable_execlists);
 990
 991         /*
 992          * i915.enable_ppgtt is read-only, so do an early pass to validate the
 993          * user's requested state against the hardware/driver capabilities.  We
 994          * do this now so that we can print out any log messages once rather
 995          * than every time we check intel_enable_ppgtt().
 996          */
 997         i915.enable_ppgtt =
 998                 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
 999         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
1000
1001         i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
1002         DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915.semaphores));
1003 }
1004
1005 /**
1006  * i915_driver_init_hw - setup state requiring device access
1007  * @dev_priv: device private
1008  *
1009  * Setup state that requires accessing the device, but doesn't require
1010  * exposing the driver via kernel internal or userspace interfaces.
1011  */
1012 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1013 {
1014         struct pci_dev *pdev = dev_priv->drm.pdev;
1015         int ret;
1016
1017         if (i915_inject_load_failure())
1018                 return -ENODEV;
1019
1020         intel_device_info_runtime_init(dev_priv);
1021
1022         intel_sanitize_options(dev_priv);
1023
1024         ret = i915_ggtt_probe_hw(dev_priv);
1025         if (ret)
1026                 return ret;
1027
1028         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1029          * otherwise the vga fbdev driver falls over. */
1030         ret = i915_kick_out_firmware_fb(dev_priv);
1031         if (ret) {
1032                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1033                 goto out_ggtt;
1034         }
1035
1036         ret = i915_kick_out_vgacon(dev_priv);
1037         if (ret) {
1038                 DRM_ERROR("failed to remove conflicting VGA console\n");
1039                 goto out_ggtt;
1040         }
1041
1042         ret = i915_ggtt_init_hw(dev_priv);
1043         if (ret)
1044                 return ret;
1045
1046         ret = i915_ggtt_enable_hw(dev_priv);
1047         if (ret) {
1048                 DRM_ERROR("failed to enable GGTT\n");
1049                 goto out_ggtt;
1050         }
1051
1052         pci_set_master(pdev);
1053
1054         /* overlay on gen2 is broken and can't address above 1G */
1055         if (IS_GEN2(dev_priv)) {
1056                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1057                 if (ret) {
1058                         DRM_ERROR("failed to set DMA mask\n");
1059
1060                         goto out_ggtt;
1061                 }
1062         }
1063
1064         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1065          * using 32bit addressing, overwriting memory if HWS is located
1066          * above 4GB.
1067          *
1068          * The documentation also mentions an issue with undefined
1069          * behaviour if any general state is accessed within a page above 4GB,
1070          * which also needs to be handled carefully.
1071          */
1072         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1073                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1074
1075                 if (ret) {
1076                         DRM_ERROR("failed to set DMA mask\n");
1077
1078                         goto out_ggtt;
1079                 }
1080         }
1081
1082         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1083                            PM_QOS_DEFAULT_VALUE);
1084
1085         intel_uncore_sanitize(dev_priv);
1086
1087         intel_opregion_setup(dev_priv);
1088
1089         i915_gem_load_init_fences(dev_priv);
1090
1091         /* On the 945G/GM, the chipset reports the MSI capability on the
1092          * integrated graphics even though the support isn't actually there
1093          * according to the published specs.  It doesn't appear to function
1094          * correctly in testing on 945G.
1095          * This may be a side effect of MSI having been made available for PEG
1096          * and the registers being closely associated.
1097          *
1098          * According to chipset errata, on the 965GM, MSI interrupts may
1099          * be lost or delayed, but we use them anyways to avoid
1100          * stuck interrupts on some machines.
1101          */
1102         if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
1103                 if (pci_enable_msi(pdev) < 0)
1104                         DRM_DEBUG_DRIVER("can't enable MSI");
1105         }
1106
1107         return 0;
1108
1109 out_ggtt:
1110         i915_ggtt_cleanup_hw(dev_priv);
1111
1112         return ret;
1113 }
1114
1115 /**
1116  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1117  * @dev_priv: device private
1118  */
1119 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1120 {
1121         struct pci_dev *pdev = dev_priv->drm.pdev;
1122
1123         if (pdev->msi_enabled)
1124                 pci_disable_msi(pdev);
1125
1126         pm_qos_remove_request(&dev_priv->pm_qos);
1127         i915_ggtt_cleanup_hw(dev_priv);
1128 }
1129
1130 /**
1131  * i915_driver_register - register the driver with the rest of the system
1132  * @dev_priv: device private
1133  *
1134  * Perform any steps necessary to make the driver available via kernel
1135  * internal or userspace interfaces.
1136  */
1137 static void i915_driver_register(struct drm_i915_private *dev_priv)
1138 {
1139         struct drm_device *dev = &dev_priv->drm;
1140
1141         i915_gem_shrinker_init(dev_priv);
1142
1143         /*
1144          * Notify a valid surface after modesetting,
1145          * when running inside a VM.
1146          */
1147         if (intel_vgpu_active(dev_priv))
1148                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1149
1150         /* Reveal our presence to userspace */
1151         if (drm_dev_register(dev, 0) == 0) {
1152                 i915_debugfs_register(dev_priv);
1153                 i915_guc_log_register(dev_priv);
1154                 i915_setup_sysfs(dev_priv);
1155
1156                 /* Depends on sysfs having been initialized */
1157                 i915_perf_register(dev_priv);
1158         } else
1159                 DRM_ERROR("Failed to register driver for userspace access!\n");
1160
1161         if (INTEL_INFO(dev_priv)->num_pipes) {
1162                 /* Must be done after probing outputs */
1163                 intel_opregion_register(dev_priv);
1164                 acpi_video_register();
1165         }
1166
1167         if (IS_GEN5(dev_priv))
1168                 intel_gpu_ips_init(dev_priv);
1169
1170         i915_audio_component_init(dev_priv);
1171
1172         /*
1173          * Some ports require correctly set-up hpd registers for detection to
1174          * work properly (leading to ghost connected connector status), e.g. VGA
1175          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1176          * irqs are fully enabled. We do it last so that the async config
1177          * cannot run before the connectors are registered.
1178          */
1179         intel_fbdev_initial_config_async(dev);
1180 }
1181
1182 /**
1183  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1184  * @dev_priv: device private
1185  */
1186 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1187 {
1188         i915_audio_component_cleanup(dev_priv);
1189
1190         intel_gpu_ips_teardown();
1191         acpi_video_unregister();
1192         intel_opregion_unregister(dev_priv);
1193
1194         i915_perf_unregister(dev_priv);
1195
1196         i915_teardown_sysfs(dev_priv);
1197         i915_guc_log_unregister(dev_priv);
1198         i915_debugfs_unregister(dev_priv);
1199         drm_dev_unregister(&dev_priv->drm);
1200
1201         i915_gem_shrinker_cleanup(dev_priv);
1202 }
1203
1204 /**
1205  * i915_driver_load - setup chip and create an initial config
1206  * @pdev: PCI device
1207  * @ent: matching PCI ID entry
1208  *
1209  * The driver load routine has to do several things:
1210  *   - drive output discovery via intel_modeset_init()
1211  *   - initialize the memory manager
1212  *   - allocate initial config memory
1213  *   - setup the DRM framebuffer with the allocated memory
1214  */
1215 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1216 {
1217         const struct intel_device_info *match_info =
1218                 (struct intel_device_info *)ent->driver_data;
1219         struct drm_i915_private *dev_priv;
1220         int ret;
1221
1222         /* Enable nuclear pageflip on ILK+, except vlv/chv */
1223         if (!i915.nuclear_pageflip &&
1224             (match_info->gen < 5 || match_info->has_gmch_display))
1225                 driver.driver_features &= ~DRIVER_ATOMIC;
1226
1227         ret = -ENOMEM;
1228         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1229         if (dev_priv)
1230                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1231         if (ret) {
1232                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1233                 goto out_free;
1234         }
1235
1236         dev_priv->drm.pdev = pdev;
1237         dev_priv->drm.dev_private = dev_priv;
1238
1239         ret = pci_enable_device(pdev);
1240         if (ret)
1241                 goto out_fini;
1242
1243         pci_set_drvdata(pdev, &dev_priv->drm);
1244
1245         ret = i915_driver_init_early(dev_priv, ent);
1246         if (ret < 0)
1247                 goto out_pci_disable;
1248
1249         intel_runtime_pm_get(dev_priv);
1250
1251         ret = i915_driver_init_mmio(dev_priv);
1252         if (ret < 0)
1253                 goto out_runtime_pm_put;
1254
1255         ret = i915_driver_init_hw(dev_priv);
1256         if (ret < 0)
1257                 goto out_cleanup_mmio;
1258
1259         /*
1260          * TODO: move the vblank init and parts of modeset init steps into one
1261          * of the i915_driver_init_/i915_driver_register functions according
1262          * to the role/effect of the given init step.
1263          */
1264         if (INTEL_INFO(dev_priv)->num_pipes) {
1265                 ret = drm_vblank_init(&dev_priv->drm,
1266                                       INTEL_INFO(dev_priv)->num_pipes);
1267                 if (ret)
1268                         goto out_cleanup_hw;
1269         }
1270
1271         ret = i915_load_modeset_init(&dev_priv->drm);
1272         if (ret < 0)
1273                 goto out_cleanup_vblank;
1274
1275         i915_driver_register(dev_priv);
1276
1277         intel_runtime_pm_enable(dev_priv);
1278
1279         dev_priv->ipc_enabled = false;
1280
1281         /* Everything is in place, we can now relax! */
1282         DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
1283                  driver.name, driver.major, driver.minor, driver.patchlevel,
1284                  driver.date, pci_name(pdev), dev_priv->drm.primary->index);
1285         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1286                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1287         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1288                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1289
1290         intel_runtime_pm_put(dev_priv);
1291
1292         return 0;
1293
1294 out_cleanup_vblank:
1295         drm_vblank_cleanup(&dev_priv->drm);
1296 out_cleanup_hw:
1297         i915_driver_cleanup_hw(dev_priv);
1298 out_cleanup_mmio:
1299         i915_driver_cleanup_mmio(dev_priv);
1300 out_runtime_pm_put:
1301         intel_runtime_pm_put(dev_priv);
1302         i915_driver_cleanup_early(dev_priv);
1303 out_pci_disable:
1304         pci_disable_device(pdev);
1305 out_fini:
1306         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1307         drm_dev_fini(&dev_priv->drm);
1308 out_free:
1309         kfree(dev_priv);
1310         return ret;
1311 }
1312
1313 void i915_driver_unload(struct drm_device *dev)
1314 {
1315         struct drm_i915_private *dev_priv = to_i915(dev);
1316         struct pci_dev *pdev = dev_priv->drm.pdev;
1317         struct drm_modeset_acquire_ctx ctx;
1318         int ret;
1319
1320         intel_fbdev_fini(dev);
1321
1322         if (i915_gem_suspend(dev_priv))
1323                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1324
1325         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1326
1327         drm_modeset_acquire_init(&ctx, 0);
1328         while (1) {
1329                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
1330                 if (!ret)
1331                         ret = drm_atomic_helper_disable_all(dev, &ctx);
1332
1333                 if (ret != -EDEADLK)
1334                         break;
1335
1336                 drm_modeset_backoff(&ctx);
1337         }
1338
1339         if (ret)
1340                 DRM_ERROR("Disabling all crtc's during unload failed with %i\n", ret);
1341
1342         drm_modeset_drop_locks(&ctx);
1343         drm_modeset_acquire_fini(&ctx);
1344
1345         i915_driver_unregister(dev_priv);
1346
1347         drm_vblank_cleanup(dev);
1348
1349         intel_modeset_cleanup(dev);
1350
1351         /*
1352          * free the memory space allocated for the child device
1353          * config parsed from VBT
1354          */
1355         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1356                 kfree(dev_priv->vbt.child_dev);
1357                 dev_priv->vbt.child_dev = NULL;
1358                 dev_priv->vbt.child_dev_num = 0;
1359         }
1360         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1361         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1362         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1363         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1364
1365         vga_switcheroo_unregister_client(pdev);
1366         vga_client_register(pdev, NULL, NULL, NULL);
1367
1368         intel_csr_ucode_fini(dev_priv);
1369
1370         /* Free error state after interrupts are fully disabled. */
1371         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1372         i915_reset_error_state(dev_priv);
1373
1374         /* Flush any outstanding unpin_work. */
1375         drain_workqueue(dev_priv->wq);
1376
1377         intel_guc_fini(dev_priv);
1378         intel_huc_fini(dev_priv);
1379         i915_gem_fini(dev_priv);
1380         intel_fbc_cleanup_cfb(dev_priv);
1381
1382         intel_power_domains_fini(dev_priv);
1383
1384         i915_driver_cleanup_hw(dev_priv);
1385         i915_driver_cleanup_mmio(dev_priv);
1386
1387         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1388 }
1389
1390 static void i915_driver_release(struct drm_device *dev)
1391 {
1392         struct drm_i915_private *dev_priv = to_i915(dev);
1393
1394         i915_driver_cleanup_early(dev_priv);
1395         drm_dev_fini(&dev_priv->drm);
1396
1397         kfree(dev_priv);
1398 }
1399
1400 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1401 {
1402         int ret;
1403
1404         ret = i915_gem_open(dev, file);
1405         if (ret)
1406                 return ret;
1407
1408         return 0;
1409 }
1410
1411 /**
1412  * i915_driver_lastclose - clean up after all DRM clients have exited
1413  * @dev: DRM device
1414  *
1415  * Take care of cleaning up after all DRM clients have exited.  In the
1416  * mode setting case, we want to restore the kernel's initial mode (just
1417  * in case the last client left us in a bad state).
1418  *
1419  * Additionally, in the non-mode setting case, we'll tear down the GTT
1420  * and DMA structures, since the kernel won't be using them, and clea
1421  * up any GEM state.
1422  */
1423 static void i915_driver_lastclose(struct drm_device *dev)
1424 {
1425         intel_fbdev_restore_mode(dev);
1426         vga_switcheroo_process_delayed_switch();
1427 }
1428
1429 static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1430 {
1431         mutex_lock(&dev->struct_mutex);
1432         i915_gem_context_close(dev, file);
1433         i915_gem_release(dev, file);
1434         mutex_unlock(&dev->struct_mutex);
1435 }
1436
1437 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1438 {
1439         struct drm_i915_file_private *file_priv = file->driver_priv;
1440
1441         kfree(file_priv);
1442 }
1443
1444 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1445 {
1446         struct drm_device *dev = &dev_priv->drm;
1447         struct intel_encoder *encoder;
1448
1449         drm_modeset_lock_all(dev);
1450         for_each_intel_encoder(dev, encoder)
1451                 if (encoder->suspend)
1452                         encoder->suspend(encoder);
1453         drm_modeset_unlock_all(dev);
1454 }
1455
1456 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1457                               bool rpm_resume);
1458 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1459
1460 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1461 {
1462 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1463         if (acpi_target_system_state() < ACPI_STATE_S3)
1464                 return true;
1465 #endif
1466         return false;
1467 }
1468
1469 static int i915_drm_suspend(struct drm_device *dev)
1470 {
1471         struct drm_i915_private *dev_priv = to_i915(dev);
1472         struct pci_dev *pdev = dev_priv->drm.pdev;
1473         pci_power_t opregion_target_state;
1474         int error;
1475
1476         /* ignore lid events during suspend */
1477         mutex_lock(&dev_priv->modeset_restore_lock);
1478         dev_priv->modeset_restore = MODESET_SUSPENDED;
1479         mutex_unlock(&dev_priv->modeset_restore_lock);
1480
1481         disable_rpm_wakeref_asserts(dev_priv);
1482
1483         /* We do a lot of poking in a lot of registers, make sure they work
1484          * properly. */
1485         intel_display_set_init_power(dev_priv, true);
1486
1487         drm_kms_helper_poll_disable(dev);
1488
1489         pci_save_state(pdev);
1490
1491         error = i915_gem_suspend(dev_priv);
1492         if (error) {
1493                 dev_err(&pdev->dev,
1494                         "GEM idle failed, resume might fail\n");
1495                 goto out;
1496         }
1497
1498         intel_guc_suspend(dev_priv);
1499
1500         intel_display_suspend(dev);
1501
1502         intel_dp_mst_suspend(dev);
1503
1504         intel_runtime_pm_disable_interrupts(dev_priv);
1505         intel_hpd_cancel_work(dev_priv);
1506
1507         intel_suspend_encoders(dev_priv);
1508
1509         intel_suspend_hw(dev_priv);
1510
1511         i915_gem_suspend_gtt_mappings(dev_priv);
1512
1513         i915_save_state(dev_priv);
1514
1515         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1516         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1517
1518         intel_uncore_forcewake_reset(dev_priv, false);
1519         intel_opregion_unregister(dev_priv);
1520
1521         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1522
1523         dev_priv->suspend_count++;
1524
1525         intel_csr_ucode_suspend(dev_priv);
1526
1527 out:
1528         enable_rpm_wakeref_asserts(dev_priv);
1529
1530         return error;
1531 }
1532
1533 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1534 {
1535         struct drm_i915_private *dev_priv = to_i915(dev);
1536         struct pci_dev *pdev = dev_priv->drm.pdev;
1537         bool fw_csr;
1538         int ret;
1539
1540         disable_rpm_wakeref_asserts(dev_priv);
1541
1542         intel_display_set_init_power(dev_priv, false);
1543
1544         fw_csr = !IS_GEN9_LP(dev_priv) &&
1545                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1546         /*
1547          * In case of firmware assisted context save/restore don't manually
1548          * deinit the power domains. This also means the CSR/DMC firmware will
1549          * stay active, it will power down any HW resources as required and
1550          * also enable deeper system power states that would be blocked if the
1551          * firmware was inactive.
1552          */
1553         if (!fw_csr)
1554                 intel_power_domains_suspend(dev_priv);
1555
1556         ret = 0;
1557         if (IS_GEN9_LP(dev_priv))
1558                 bxt_enable_dc9(dev_priv);
1559         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1560                 hsw_enable_pc8(dev_priv);
1561         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1562                 ret = vlv_suspend_complete(dev_priv);
1563
1564         if (ret) {
1565                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1566                 if (!fw_csr)
1567                         intel_power_domains_init_hw(dev_priv, true);
1568
1569                 goto out;
1570         }
1571
1572         pci_disable_device(pdev);
1573         /*
1574          * During hibernation on some platforms the BIOS may try to access
1575          * the device even though it's already in D3 and hang the machine. So
1576          * leave the device in D0 on those platforms and hope the BIOS will
1577          * power down the device properly. The issue was seen on multiple old
1578          * GENs with different BIOS vendors, so having an explicit blacklist
1579          * is inpractical; apply the workaround on everything pre GEN6. The
1580          * platforms where the issue was seen:
1581          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1582          * Fujitsu FSC S7110
1583          * Acer Aspire 1830T
1584          */
1585         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1586                 pci_set_power_state(pdev, PCI_D3hot);
1587
1588         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1589
1590 out:
1591         enable_rpm_wakeref_asserts(dev_priv);
1592
1593         return ret;
1594 }
1595
1596 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1597 {
1598         int error;
1599
1600         if (!dev) {
1601                 DRM_ERROR("dev: %p\n", dev);
1602                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1603                 return -ENODEV;
1604         }
1605
1606         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1607                          state.event != PM_EVENT_FREEZE))
1608                 return -EINVAL;
1609
1610         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1611                 return 0;
1612
1613         error = i915_drm_suspend(dev);
1614         if (error)
1615                 return error;
1616
1617         return i915_drm_suspend_late(dev, false);
1618 }
1619
1620 static int i915_drm_resume(struct drm_device *dev)
1621 {
1622         struct drm_i915_private *dev_priv = to_i915(dev);
1623         int ret;
1624
1625         disable_rpm_wakeref_asserts(dev_priv);
1626         intel_sanitize_gt_powersave(dev_priv);
1627
1628         ret = i915_ggtt_enable_hw(dev_priv);
1629         if (ret)
1630                 DRM_ERROR("failed to re-enable GGTT\n");
1631
1632         intel_csr_ucode_resume(dev_priv);
1633
1634         i915_gem_resume(dev_priv);
1635
1636         i915_restore_state(dev_priv);
1637         intel_pps_unlock_regs_wa(dev_priv);
1638         intel_opregion_setup(dev_priv);
1639
1640         intel_init_pch_refclk(dev_priv);
1641
1642         /*
1643          * Interrupts have to be enabled before any batches are run. If not the
1644          * GPU will hang. i915_gem_init_hw() will initiate batches to
1645          * update/restore the context.
1646          *
1647          * drm_mode_config_reset() needs AUX interrupts.
1648          *
1649          * Modeset enabling in intel_modeset_init_hw() also needs working
1650          * interrupts.
1651          */
1652         intel_runtime_pm_enable_interrupts(dev_priv);
1653
1654         drm_mode_config_reset(dev);
1655
1656         mutex_lock(&dev->struct_mutex);
1657         if (i915_gem_init_hw(dev_priv)) {
1658                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1659                 i915_gem_set_wedged(dev_priv);
1660         }
1661         mutex_unlock(&dev->struct_mutex);
1662
1663         intel_guc_resume(dev_priv);
1664
1665         intel_modeset_init_hw(dev);
1666
1667         spin_lock_irq(&dev_priv->irq_lock);
1668         if (dev_priv->display.hpd_irq_setup)
1669                 dev_priv->display.hpd_irq_setup(dev_priv);
1670         spin_unlock_irq(&dev_priv->irq_lock);
1671
1672         intel_dp_mst_resume(dev);
1673
1674         intel_display_resume(dev);
1675
1676         drm_kms_helper_poll_enable(dev);
1677
1678         /*
1679          * ... but also need to make sure that hotplug processing
1680          * doesn't cause havoc. Like in the driver load code we don't
1681          * bother with the tiny race here where we might loose hotplug
1682          * notifications.
1683          * */
1684         intel_hpd_init(dev_priv);
1685
1686         intel_opregion_register(dev_priv);
1687
1688         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1689
1690         mutex_lock(&dev_priv->modeset_restore_lock);
1691         dev_priv->modeset_restore = MODESET_DONE;
1692         mutex_unlock(&dev_priv->modeset_restore_lock);
1693
1694         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1695
1696         intel_autoenable_gt_powersave(dev_priv);
1697
1698         enable_rpm_wakeref_asserts(dev_priv);
1699
1700         return 0;
1701 }
1702
1703 static int i915_drm_resume_early(struct drm_device *dev)
1704 {
1705         struct drm_i915_private *dev_priv = to_i915(dev);
1706         struct pci_dev *pdev = dev_priv->drm.pdev;
1707         int ret;
1708
1709         /*
1710          * We have a resume ordering issue with the snd-hda driver also
1711          * requiring our device to be power up. Due to the lack of a
1712          * parent/child relationship we currently solve this with an early
1713          * resume hook.
1714          *
1715          * FIXME: This should be solved with a special hdmi sink device or
1716          * similar so that power domains can be employed.
1717          */
1718
1719         /*
1720          * Note that we need to set the power state explicitly, since we
1721          * powered off the device during freeze and the PCI core won't power
1722          * it back up for us during thaw. Powering off the device during
1723          * freeze is not a hard requirement though, and during the
1724          * suspend/resume phases the PCI core makes sure we get here with the
1725          * device powered on. So in case we change our freeze logic and keep
1726          * the device powered we can also remove the following set power state
1727          * call.
1728          */
1729         ret = pci_set_power_state(pdev, PCI_D0);
1730         if (ret) {
1731                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1732                 goto out;
1733         }
1734
1735         /*
1736          * Note that pci_enable_device() first enables any parent bridge
1737          * device and only then sets the power state for this device. The
1738          * bridge enabling is a nop though, since bridge devices are resumed
1739          * first. The order of enabling power and enabling the device is
1740          * imposed by the PCI core as described above, so here we preserve the
1741          * same order for the freeze/thaw phases.
1742          *
1743          * TODO: eventually we should remove pci_disable_device() /
1744          * pci_enable_enable_device() from suspend/resume. Due to how they
1745          * depend on the device enable refcount we can't anyway depend on them
1746          * disabling/enabling the device.
1747          */
1748         if (pci_enable_device(pdev)) {
1749                 ret = -EIO;
1750                 goto out;
1751         }
1752
1753         pci_set_master(pdev);
1754
1755         disable_rpm_wakeref_asserts(dev_priv);
1756
1757         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1758                 ret = vlv_resume_prepare(dev_priv, false);
1759         if (ret)
1760                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1761                           ret);
1762
1763         intel_uncore_early_sanitize(dev_priv, true);
1764
1765         if (IS_GEN9_LP(dev_priv)) {
1766                 if (!dev_priv->suspended_to_idle)
1767                         gen9_sanitize_dc_state(dev_priv);
1768                 bxt_disable_dc9(dev_priv);
1769         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1770                 hsw_disable_pc8(dev_priv);
1771         }
1772
1773         intel_uncore_sanitize(dev_priv);
1774
1775         if (IS_GEN9_LP(dev_priv) ||
1776             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1777                 intel_power_domains_init_hw(dev_priv, true);
1778
1779         i915_gem_sanitize(dev_priv);
1780
1781         enable_rpm_wakeref_asserts(dev_priv);
1782
1783 out:
1784         dev_priv->suspended_to_idle = false;
1785
1786         return ret;
1787 }
1788
1789 static int i915_resume_switcheroo(struct drm_device *dev)
1790 {
1791         int ret;
1792
1793         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1794                 return 0;
1795
1796         ret = i915_drm_resume_early(dev);
1797         if (ret)
1798                 return ret;
1799
1800         return i915_drm_resume(dev);
1801 }
1802
1803 /**
1804  * i915_reset - reset chip after a hang
1805  * @dev_priv: device private to reset
1806  *
1807  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1808  * on failure.
1809  *
1810  * Caller must hold the struct_mutex.
1811  *
1812  * Procedure is fairly simple:
1813  *   - reset the chip using the reset reg
1814  *   - re-init context state
1815  *   - re-init hardware status page
1816  *   - re-init ring buffer
1817  *   - re-init interrupt state
1818  *   - re-init display
1819  */
1820 void i915_reset(struct drm_i915_private *dev_priv)
1821 {
1822         struct i915_gpu_error *error = &dev_priv->gpu_error;
1823         int ret;
1824
1825         lockdep_assert_held(&dev_priv->drm.struct_mutex);
1826
1827         if (!test_and_clear_bit(I915_RESET_IN_PROGRESS, &error->flags))
1828                 return;
1829
1830         /* Clear any previous failed attempts at recovery. Time to try again. */
1831         __clear_bit(I915_WEDGED, &error->flags);
1832         error->reset_count++;
1833
1834         pr_notice("drm/i915: Resetting chip after gpu hang\n");
1835         disable_irq(dev_priv->drm.irq);
1836         ret = i915_gem_reset_prepare(dev_priv);
1837         if (ret) {
1838                 DRM_ERROR("GPU recovery failed\n");
1839                 intel_gpu_reset(dev_priv, ALL_ENGINES);
1840                 goto error;
1841         }
1842
1843         ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
1844         if (ret) {
1845                 if (ret != -ENODEV)
1846                         DRM_ERROR("Failed to reset chip: %i\n", ret);
1847                 else
1848                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1849                 goto error;
1850         }
1851
1852         i915_gem_reset(dev_priv);
1853         intel_overlay_reset(dev_priv);
1854
1855         /* Ok, now get things going again... */
1856
1857         /*
1858          * Everything depends on having the GTT running, so we need to start
1859          * there.  Fortunately we don't need to do this unless we reset the
1860          * chip at a PCI level.
1861          *
1862          * Next we need to restore the context, but we don't use those
1863          * yet either...
1864          *
1865          * Ring buffer needs to be re-initialized in the KMS case, or if X
1866          * was running at the time of the reset (i.e. we weren't VT
1867          * switched away).
1868          */
1869         ret = i915_gem_init_hw(dev_priv);
1870         if (ret) {
1871                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1872                 goto error;
1873         }
1874
1875         i915_queue_hangcheck(dev_priv);
1876
1877 wakeup:
1878         i915_gem_reset_finish(dev_priv);
1879         enable_irq(dev_priv->drm.irq);
1880         wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS);
1881         return;
1882
1883 error:
1884         i915_gem_set_wedged(dev_priv);
1885         goto wakeup;
1886 }
1887
1888 static int i915_pm_suspend(struct device *kdev)
1889 {
1890         struct pci_dev *pdev = to_pci_dev(kdev);
1891         struct drm_device *dev = pci_get_drvdata(pdev);
1892
1893         if (!dev) {
1894                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1895                 return -ENODEV;
1896         }
1897
1898         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1899                 return 0;
1900
1901         return i915_drm_suspend(dev);
1902 }
1903
1904 static int i915_pm_suspend_late(struct device *kdev)
1905 {
1906         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1907
1908         /*
1909          * We have a suspend ordering issue with the snd-hda driver also
1910          * requiring our device to be power up. Due to the lack of a
1911          * parent/child relationship we currently solve this with an late
1912          * suspend hook.
1913          *
1914          * FIXME: This should be solved with a special hdmi sink device or
1915          * similar so that power domains can be employed.
1916          */
1917         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1918                 return 0;
1919
1920         return i915_drm_suspend_late(dev, false);
1921 }
1922
1923 static int i915_pm_poweroff_late(struct device *kdev)
1924 {
1925         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1926
1927         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1928                 return 0;
1929
1930         return i915_drm_suspend_late(dev, true);
1931 }
1932
1933 static int i915_pm_resume_early(struct device *kdev)
1934 {
1935         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1936
1937         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1938                 return 0;
1939
1940         return i915_drm_resume_early(dev);
1941 }
1942
1943 static int i915_pm_resume(struct device *kdev)
1944 {
1945         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1946
1947         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1948                 return 0;
1949
1950         return i915_drm_resume(dev);
1951 }
1952
1953 /* freeze: before creating the hibernation_image */
1954 static int i915_pm_freeze(struct device *kdev)
1955 {
1956         int ret;
1957
1958         ret = i915_pm_suspend(kdev);
1959         if (ret)
1960                 return ret;
1961
1962         ret = i915_gem_freeze(kdev_to_i915(kdev));
1963         if (ret)
1964                 return ret;
1965
1966         return 0;
1967 }
1968
1969 static int i915_pm_freeze_late(struct device *kdev)
1970 {
1971         int ret;
1972
1973         ret = i915_pm_suspend_late(kdev);
1974         if (ret)
1975                 return ret;
1976
1977         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
1978         if (ret)
1979                 return ret;
1980
1981         return 0;
1982 }
1983
1984 /* thaw: called after creating the hibernation image, but before turning off. */
1985 static int i915_pm_thaw_early(struct device *kdev)
1986 {
1987         return i915_pm_resume_early(kdev);
1988 }
1989
1990 static int i915_pm_thaw(struct device *kdev)
1991 {
1992         return i915_pm_resume(kdev);
1993 }
1994
1995 /* restore: called after loading the hibernation image. */
1996 static int i915_pm_restore_early(struct device *kdev)
1997 {
1998         return i915_pm_resume_early(kdev);
1999 }
2000
2001 static int i915_pm_restore(struct device *kdev)
2002 {
2003         return i915_pm_resume(kdev);
2004 }
2005
2006 /*
2007  * Save all Gunit registers that may be lost after a D3 and a subsequent
2008  * S0i[R123] transition. The list of registers needing a save/restore is
2009  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2010  * registers in the following way:
2011  * - Driver: saved/restored by the driver
2012  * - Punit : saved/restored by the Punit firmware
2013  * - No, w/o marking: no need to save/restore, since the register is R/O or
2014  *                    used internally by the HW in a way that doesn't depend
2015  *                    keeping the content across a suspend/resume.
2016  * - Debug : used for debugging
2017  *
2018  * We save/restore all registers marked with 'Driver', with the following
2019  * exceptions:
2020  * - Registers out of use, including also registers marked with 'Debug'.
2021  *   These have no effect on the driver's operation, so we don't save/restore
2022  *   them to reduce the overhead.
2023  * - Registers that are fully setup by an initialization function called from
2024  *   the resume path. For example many clock gating and RPS/RC6 registers.
2025  * - Registers that provide the right functionality with their reset defaults.
2026  *
2027  * TODO: Except for registers that based on the above 3 criteria can be safely
2028  * ignored, we save/restore all others, practically treating the HW context as
2029  * a black-box for the driver. Further investigation is needed to reduce the
2030  * saved/restored registers even further, by following the same 3 criteria.
2031  */
2032 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2033 {
2034         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2035         int i;
2036
2037         /* GAM 0x4000-0x4770 */
2038         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2039         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2040         s->arb_mode             = I915_READ(ARB_MODE);
2041         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2042         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2043
2044         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2045                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2046
2047         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2048         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2049
2050         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2051         s->ecochk               = I915_READ(GAM_ECOCHK);
2052         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2053         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2054
2055         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2056
2057         /* MBC 0x9024-0x91D0, 0x8500 */
2058         s->g3dctl               = I915_READ(VLV_G3DCTL);
2059         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2060         s->mbctl                = I915_READ(GEN6_MBCTL);
2061
2062         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2063         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2064         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2065         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2066         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2067         s->rstctl               = I915_READ(GEN6_RSTCTL);
2068         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2069
2070         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2071         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2072         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2073         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2074         s->ecobus               = I915_READ(ECOBUS);
2075         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2076         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2077         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2078         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2079         s->rcedata              = I915_READ(VLV_RCEDATA);
2080         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2081
2082         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2083         s->gt_imr               = I915_READ(GTIMR);
2084         s->gt_ier               = I915_READ(GTIER);
2085         s->pm_imr               = I915_READ(GEN6_PMIMR);
2086         s->pm_ier               = I915_READ(GEN6_PMIER);
2087
2088         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2089                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2090
2091         /* GT SA CZ domain, 0x100000-0x138124 */
2092         s->tilectl              = I915_READ(TILECTL);
2093         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2094         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2095         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2096         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2097
2098         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2099         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2100         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2101         s->pcbr                 = I915_READ(VLV_PCBR);
2102         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2103
2104         /*
2105          * Not saving any of:
2106          * DFT,         0x9800-0x9EC0
2107          * SARB,        0xB000-0xB1FC
2108          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2109          * PCI CFG
2110          */
2111 }
2112
2113 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2114 {
2115         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2116         u32 val;
2117         int i;
2118
2119         /* GAM 0x4000-0x4770 */
2120         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2121         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2122         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2123         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2124         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2125
2126         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2127                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2128
2129         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2130         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2131
2132         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2133         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2134         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2135         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2136
2137         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2138
2139         /* MBC 0x9024-0x91D0, 0x8500 */
2140         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2141         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2142         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2143
2144         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2145         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2146         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2147         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2148         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2149         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2150         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2151
2152         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2153         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2154         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2155         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2156         I915_WRITE(ECOBUS,              s->ecobus);
2157         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2158         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2159         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2160         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2161         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2162         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2163
2164         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2165         I915_WRITE(GTIMR,               s->gt_imr);
2166         I915_WRITE(GTIER,               s->gt_ier);
2167         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2168         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2169
2170         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2171                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2172
2173         /* GT SA CZ domain, 0x100000-0x138124 */
2174         I915_WRITE(TILECTL,                     s->tilectl);
2175         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2176         /*
2177          * Preserve the GT allow wake and GFX force clock bit, they are not
2178          * be restored, as they are used to control the s0ix suspend/resume
2179          * sequence by the caller.
2180          */
2181         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2182         val &= VLV_GTLC_ALLOWWAKEREQ;
2183         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2184         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2185
2186         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2187         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2188         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2189         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2190
2191         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2192
2193         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2194         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2195         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2196         I915_WRITE(VLV_PCBR,                    s->pcbr);
2197         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2198 }
2199
2200 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2201 {
2202         u32 val;
2203         int err;
2204
2205         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2206         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2207         if (force_on)
2208                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2209         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2210
2211         if (!force_on)
2212                 return 0;
2213
2214         err = intel_wait_for_register(dev_priv,
2215                                       VLV_GTLC_SURVIVABILITY_REG,
2216                                       VLV_GFX_CLK_STATUS_BIT,
2217                                       VLV_GFX_CLK_STATUS_BIT,
2218                                       20);
2219         if (err)
2220                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2221                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2222
2223         return err;
2224 }
2225
2226 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2227 {
2228         u32 val;
2229         int err = 0;
2230
2231         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2232         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2233         if (allow)
2234                 val |= VLV_GTLC_ALLOWWAKEREQ;
2235         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2236         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2237
2238         err = intel_wait_for_register(dev_priv,
2239                                       VLV_GTLC_PW_STATUS,
2240                                       VLV_GTLC_ALLOWWAKEACK,
2241                                       allow,
2242                                       1);
2243         if (err)
2244                 DRM_ERROR("timeout disabling GT waking\n");
2245
2246         return err;
2247 }
2248
2249 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2250                                  bool wait_for_on)
2251 {
2252         u32 mask;
2253         u32 val;
2254         int err;
2255
2256         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2257         val = wait_for_on ? mask : 0;
2258         if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
2259                 return 0;
2260
2261         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
2262                       onoff(wait_for_on),
2263                       I915_READ(VLV_GTLC_PW_STATUS));
2264
2265         /*
2266          * RC6 transitioning can be delayed up to 2 msec (see
2267          * valleyview_enable_rps), use 3 msec for safety.
2268          */
2269         err = intel_wait_for_register(dev_priv,
2270                                       VLV_GTLC_PW_STATUS, mask, val,
2271                                       3);
2272         if (err)
2273                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2274                           onoff(wait_for_on));
2275
2276         return err;
2277 }
2278
2279 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2280 {
2281         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2282                 return;
2283
2284         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2285         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2286 }
2287
2288 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2289 {
2290         u32 mask;
2291         int err;
2292
2293         /*
2294          * Bspec defines the following GT well on flags as debug only, so
2295          * don't treat them as hard failures.
2296          */
2297         (void)vlv_wait_for_gt_wells(dev_priv, false);
2298
2299         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2300         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2301
2302         vlv_check_no_gt_access(dev_priv);
2303
2304         err = vlv_force_gfx_clock(dev_priv, true);
2305         if (err)
2306                 goto err1;
2307
2308         err = vlv_allow_gt_wake(dev_priv, false);
2309         if (err)
2310                 goto err2;
2311
2312         if (!IS_CHERRYVIEW(dev_priv))
2313                 vlv_save_gunit_s0ix_state(dev_priv);
2314
2315         err = vlv_force_gfx_clock(dev_priv, false);
2316         if (err)
2317                 goto err2;
2318
2319         return 0;
2320
2321 err2:
2322         /* For safety always re-enable waking and disable gfx clock forcing */
2323         vlv_allow_gt_wake(dev_priv, true);
2324 err1:
2325         vlv_force_gfx_clock(dev_priv, false);
2326
2327         return err;
2328 }
2329
2330 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2331                                 bool rpm_resume)
2332 {
2333         int err;
2334         int ret;
2335
2336         /*
2337          * If any of the steps fail just try to continue, that's the best we
2338          * can do at this point. Return the first error code (which will also
2339          * leave RPM permanently disabled).
2340          */
2341         ret = vlv_force_gfx_clock(dev_priv, true);
2342
2343         if (!IS_CHERRYVIEW(dev_priv))
2344                 vlv_restore_gunit_s0ix_state(dev_priv);
2345
2346         err = vlv_allow_gt_wake(dev_priv, true);
2347         if (!ret)
2348                 ret = err;
2349
2350         err = vlv_force_gfx_clock(dev_priv, false);
2351         if (!ret)
2352                 ret = err;
2353
2354         vlv_check_no_gt_access(dev_priv);
2355
2356         if (rpm_resume)
2357                 intel_init_clock_gating(dev_priv);
2358
2359         return ret;
2360 }
2361
2362 static int intel_runtime_suspend(struct device *kdev)
2363 {
2364         struct pci_dev *pdev = to_pci_dev(kdev);
2365         struct drm_device *dev = pci_get_drvdata(pdev);
2366         struct drm_i915_private *dev_priv = to_i915(dev);
2367         int ret;
2368
2369         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2370                 return -ENODEV;
2371
2372         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2373                 return -ENODEV;
2374
2375         DRM_DEBUG_KMS("Suspending device\n");
2376
2377         disable_rpm_wakeref_asserts(dev_priv);
2378
2379         /*
2380          * We are safe here against re-faults, since the fault handler takes
2381          * an RPM reference.
2382          */
2383         i915_gem_runtime_suspend(dev_priv);
2384
2385         intel_guc_suspend(dev_priv);
2386
2387         intel_runtime_pm_disable_interrupts(dev_priv);
2388
2389         ret = 0;
2390         if (IS_GEN9_LP(dev_priv)) {
2391                 bxt_display_core_uninit(dev_priv);
2392                 bxt_enable_dc9(dev_priv);
2393         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2394                 hsw_enable_pc8(dev_priv);
2395         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2396                 ret = vlv_suspend_complete(dev_priv);
2397         }
2398
2399         if (ret) {
2400                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2401                 intel_runtime_pm_enable_interrupts(dev_priv);
2402
2403                 enable_rpm_wakeref_asserts(dev_priv);
2404
2405                 return ret;
2406         }
2407
2408         intel_uncore_forcewake_reset(dev_priv, false);
2409
2410         enable_rpm_wakeref_asserts(dev_priv);
2411         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2412
2413         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2414                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2415
2416         dev_priv->pm.suspended = true;
2417
2418         /*
2419          * FIXME: We really should find a document that references the arguments
2420          * used below!
2421          */
2422         if (IS_BROADWELL(dev_priv)) {
2423                 /*
2424                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2425                  * being detected, and the call we do at intel_runtime_resume()
2426                  * won't be able to restore them. Since PCI_D3hot matches the
2427                  * actual specification and appears to be working, use it.
2428                  */
2429                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2430         } else {
2431                 /*
2432                  * current versions of firmware which depend on this opregion
2433                  * notification have repurposed the D1 definition to mean
2434                  * "runtime suspended" vs. what you would normally expect (D3)
2435                  * to distinguish it from notifications that might be sent via
2436                  * the suspend path.
2437                  */
2438                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2439         }
2440
2441         assert_forcewakes_inactive(dev_priv);
2442
2443         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2444                 intel_hpd_poll_init(dev_priv);
2445
2446         DRM_DEBUG_KMS("Device suspended\n");
2447         return 0;
2448 }
2449
2450 static int intel_runtime_resume(struct device *kdev)
2451 {
2452         struct pci_dev *pdev = to_pci_dev(kdev);
2453         struct drm_device *dev = pci_get_drvdata(pdev);
2454         struct drm_i915_private *dev_priv = to_i915(dev);
2455         int ret = 0;
2456
2457         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2458                 return -ENODEV;
2459
2460         DRM_DEBUG_KMS("Resuming device\n");
2461
2462         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2463         disable_rpm_wakeref_asserts(dev_priv);
2464
2465         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2466         dev_priv->pm.suspended = false;
2467         if (intel_uncore_unclaimed_mmio(dev_priv))
2468                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2469
2470         intel_guc_resume(dev_priv);
2471
2472         if (IS_GEN6(dev_priv))
2473                 intel_init_pch_refclk(dev_priv);
2474
2475         if (IS_GEN9_LP(dev_priv)) {
2476                 bxt_disable_dc9(dev_priv);
2477                 bxt_display_core_init(dev_priv, true);
2478                 if (dev_priv->csr.dmc_payload &&
2479                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2480                         gen9_enable_dc5(dev_priv);
2481         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2482                 hsw_disable_pc8(dev_priv);
2483         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2484                 ret = vlv_resume_prepare(dev_priv, true);
2485         }
2486
2487         /*
2488          * No point of rolling back things in case of an error, as the best
2489          * we can do is to hope that things will still work (and disable RPM).
2490          */
2491         i915_gem_init_swizzling(dev_priv);
2492         i915_gem_restore_fences(dev_priv);
2493
2494         intel_runtime_pm_enable_interrupts(dev_priv);
2495
2496         /*
2497          * On VLV/CHV display interrupts are part of the display
2498          * power well, so hpd is reinitialized from there. For
2499          * everyone else do it here.
2500          */
2501         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2502                 intel_hpd_init(dev_priv);
2503
2504         enable_rpm_wakeref_asserts(dev_priv);
2505
2506         if (ret)
2507                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2508         else
2509                 DRM_DEBUG_KMS("Device resumed\n");
2510
2511         return ret;
2512 }
2513
2514 const struct dev_pm_ops i915_pm_ops = {
2515         /*
2516          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2517          * PMSG_RESUME]
2518          */
2519         .suspend = i915_pm_suspend,
2520         .suspend_late = i915_pm_suspend_late,
2521         .resume_early = i915_pm_resume_early,
2522         .resume = i915_pm_resume,
2523
2524         /*
2525          * S4 event handlers
2526          * @freeze, @freeze_late    : called (1) before creating the
2527          *                            hibernation image [PMSG_FREEZE] and
2528          *                            (2) after rebooting, before restoring
2529          *                            the image [PMSG_QUIESCE]
2530          * @thaw, @thaw_early       : called (1) after creating the hibernation
2531          *                            image, before writing it [PMSG_THAW]
2532          *                            and (2) after failing to create or
2533          *                            restore the image [PMSG_RECOVER]
2534          * @poweroff, @poweroff_late: called after writing the hibernation
2535          *                            image, before rebooting [PMSG_HIBERNATE]
2536          * @restore, @restore_early : called after rebooting and restoring the
2537          *                            hibernation image [PMSG_RESTORE]
2538          */
2539         .freeze = i915_pm_freeze,
2540         .freeze_late = i915_pm_freeze_late,
2541         .thaw_early = i915_pm_thaw_early,
2542         .thaw = i915_pm_thaw,
2543         .poweroff = i915_pm_suspend,
2544         .poweroff_late = i915_pm_poweroff_late,
2545         .restore_early = i915_pm_restore_early,
2546         .restore = i915_pm_restore,
2547
2548         /* S0ix (via runtime suspend) event handlers */
2549         .runtime_suspend = intel_runtime_suspend,
2550         .runtime_resume = intel_runtime_resume,
2551 };
2552
2553 static const struct vm_operations_struct i915_gem_vm_ops = {
2554         .fault = i915_gem_fault,
2555         .open = drm_gem_vm_open,
2556         .close = drm_gem_vm_close,
2557 };
2558
2559 static const struct file_operations i915_driver_fops = {
2560         .owner = THIS_MODULE,
2561         .open = drm_open,
2562         .release = drm_release,
2563         .unlocked_ioctl = drm_ioctl,
2564         .mmap = drm_gem_mmap,
2565         .poll = drm_poll,
2566         .read = drm_read,
2567         .compat_ioctl = i915_compat_ioctl,
2568         .llseek = noop_llseek,
2569 };
2570
2571 static int
2572 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2573                           struct drm_file *file)
2574 {
2575         return -ENODEV;
2576 }
2577
2578 static const struct drm_ioctl_desc i915_ioctls[] = {
2579         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2580         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2581         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2582         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2583         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2584         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2585         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2586         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2587         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2588         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2589         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2590         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2591         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2592         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2593         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2594         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2595         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2596         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2597         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2598         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2599         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2600         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2601         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2602         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2603         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2604         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2605         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2606         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2607         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2608         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2609         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2610         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2611         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2612         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2613         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2614         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2615         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2616         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2617         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2618         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2619         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2620         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2621         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2622         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2623         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2624         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2625         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2626         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2627         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2628         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2629         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2630         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2631         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2632 };
2633
2634 static struct drm_driver driver = {
2635         /* Don't use MTRRs here; the Xserver or userspace app should
2636          * deal with them for Intel hardware.
2637          */
2638         .driver_features =
2639             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2640             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC,
2641         .release = i915_driver_release,
2642         .open = i915_driver_open,
2643         .lastclose = i915_driver_lastclose,
2644         .preclose = i915_driver_preclose,
2645         .postclose = i915_driver_postclose,
2646         .set_busid = drm_pci_set_busid,
2647
2648         .gem_close_object = i915_gem_close_object,
2649         .gem_free_object_unlocked = i915_gem_free_object,
2650         .gem_vm_ops = &i915_gem_vm_ops,
2651
2652         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2653         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2654         .gem_prime_export = i915_gem_prime_export,
2655         .gem_prime_import = i915_gem_prime_import,
2656
2657         .dumb_create = i915_gem_dumb_create,
2658         .dumb_map_offset = i915_gem_mmap_gtt,
2659         .dumb_destroy = drm_gem_dumb_destroy,
2660         .ioctls = i915_ioctls,
2661         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2662         .fops = &i915_driver_fops,
2663         .name = DRIVER_NAME,
2664         .desc = DRIVER_DESC,
2665         .date = DRIVER_DATE,
2666         .major = DRIVER_MAJOR,
2667         .minor = DRIVER_MINOR,
2668         .patchlevel = DRIVER_PATCHLEVEL,
2669 };
2670
2671 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2672 #include "selftests/mock_drm.c"
2673 #endif