drivers/gpu/drm/i915/i915_driver.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/module.h>
  33 #include <linux/oom.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/slab.h>
  38 #include <linux/string_helpers.h>
  39 #include <linux/vga_switcheroo.h>
  40 #include <linux/vt.h>
  41
  42 #include <drm/drm_aperture.h>
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_ioctl.h>
  45 #include <drm/drm_managed.h>
  46 #include <drm/drm_probe_helper.h>
  47
  48 #include "display/intel_acpi.h"
  49 #include "display/intel_bw.h"
  50 #include "display/intel_cdclk.h"
  51 #include "display/intel_display_driver.h"
  52 #include "display/intel_display_types.h"
  53 #include "display/intel_dmc.h"
  54 #include "display/intel_dp.h"
  55 #include "display/intel_dpt.h"
  56 #include "display/intel_fbdev.h"
  57 #include "display/intel_hotplug.h"
  58 #include "display/intel_overlay.h"
  59 #include "display/intel_pch_refclk.h"
  60 #include "display/intel_pipe_crc.h"
  61 #include "display/intel_pps.h"
  62 #include "display/intel_sprite.h"
  63 #include "display/intel_vga.h"
  64 #include "display/skl_watermark.h"
  65
  66 #include "gem/i915_gem_context.h"
  67 #include "gem/i915_gem_create.h"
  68 #include "gem/i915_gem_dmabuf.h"
  69 #include "gem/i915_gem_ioctls.h"
  70 #include "gem/i915_gem_mman.h"
  71 #include "gem/i915_gem_pm.h"
  72 #include "gt/intel_gt.h"
  73 #include "gt/intel_gt_pm.h"
  74 #include "gt/intel_gt_print.h"
  75 #include "gt/intel_rc6.h"
  76
  77 #include "pxp/intel_pxp.h"
  78 #include "pxp/intel_pxp_debugfs.h"
  79 #include "pxp/intel_pxp_pm.h"
  80
  81 #include "soc/intel_dram.h"
  82 #include "soc/intel_gmch.h"
  83
  84 #include "i915_debugfs.h"
  85 #include "i915_driver.h"
  86 #include "i915_drm_client.h"
  87 #include "i915_drv.h"
  88 #include "i915_file_private.h"
  89 #include "i915_getparam.h"
  90 #include "i915_hwmon.h"
  91 #include "i915_ioc32.h"
  92 #include "i915_ioctl.h"
  93 #include "i915_irq.h"
  94 #include "i915_memcpy.h"
  95 #include "i915_perf.h"
  96 #include "i915_query.h"
  97 #include "i915_suspend.h"
  98 #include "i915_switcheroo.h"
  99 #include "i915_sysfs.h"
 100 #include "i915_utils.h"
 101 #include "i915_vgpu.h"
 102 #include "intel_clock_gating.h"
 103 #include "intel_gvt.h"
 104 #include "intel_memory_region.h"
 105 #include "intel_pci_config.h"
 106 #include "intel_pcode.h"
 107 #include "intel_region_ttm.h"
 108 #include "vlv_suspend.h"
 109
 110 static const struct drm_driver i915_drm_driver;
 111
 112 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 113 {
 114         /*
 115          * The i915 workqueue is primarily used for batched retirement of
 116          * requests (and thus managing bo) once the task has been completed
 117          * by the GPU. i915_retire_requests() is called directly when we
 118          * need high-priority retirement, such as waiting for an explicit
 119          * bo.
 120          *
 121          * It is also used for periodic low-priority events, such as
 122          * idle-timers and recording error state.
 123          *
 124          * All tasks on the workqueue are expected to acquire the dev mutex
 125          * so there is no point in running more than one instance of the
 126          * workqueue at any time.  Use an ordered one.
 127          */
 128         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 129         if (dev_priv->wq == NULL)
 130                 goto out_err;
 131
 132         dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 133         if (dev_priv->display.hotplug.dp_wq == NULL)
 134                 goto out_free_wq;
 135
 136         /*
 137          * The unordered i915 workqueue should be used for all work
 138          * scheduling that do not require running in order, which used
 139          * to be scheduled on the system_wq before moving to a driver
 140          * instance due deprecation of flush_scheduled_work().
 141          */
 142         dev_priv->unordered_wq = alloc_workqueue("i915-unordered", 0, 0);
 143         if (dev_priv->unordered_wq == NULL)
 144                 goto out_free_dp_wq;
 145
 146         return 0;
 147
 148 out_free_dp_wq:
 149         destroy_workqueue(dev_priv->display.hotplug.dp_wq);
 150 out_free_wq:
 151         destroy_workqueue(dev_priv->wq);
 152 out_err:
 153         drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
 154
 155         return -ENOMEM;
 156 }
 157
 158 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 159 {
 160         destroy_workqueue(dev_priv->unordered_wq);
 161         destroy_workqueue(dev_priv->display.hotplug.dp_wq);
 162         destroy_workqueue(dev_priv->wq);
 163 }
 164
 165 /*
 166  * We don't keep the workarounds for pre-production hardware, so we expect our
 167  * driver to fail on these machines in one way or another. A little warning on
 168  * dmesg may help both the user and the bug triagers.
 169  *
 170  * Our policy for removing pre-production workarounds is to keep the
 171  * current gen workarounds as a guide to the bring-up of the next gen
 172  * (workarounds have a habit of persisting!). Anything older than that
 173  * should be removed along with the complications they introduce.
 174  */
 175 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 176 {
 177         bool pre = false;
 178
 179         pre |= IS_HASWELL_EARLY_SDV(dev_priv);
 180         pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
 181         pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
 182         pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 183         pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
 184         pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
 185         pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 186         pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 187         pre |= IS_DG2_G10(dev_priv) && INTEL_REVID(dev_priv) < 0x8;
 188         pre |= IS_DG2_G11(dev_priv) && INTEL_REVID(dev_priv) < 0x5;
 189         pre |= IS_DG2_G12(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 190
 191         if (pre) {
 192                 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
 193                           "It may not be fully functional.\n");
 194                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 195         }
 196 }
 197
 198 static void sanitize_gpu(struct drm_i915_private *i915)
 199 {
 200         if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) {
 201                 struct intel_gt *gt;
 202                 unsigned int i;
 203
 204                 for_each_gt(gt, i915, i)
 205                         __intel_gt_reset(gt, ALL_ENGINES);
 206         }
 207 }
 208
 209 /**
 210  * i915_driver_early_probe - setup state not requiring device access
 211  * @dev_priv: device private
 212  *
 213  * Initialize everything that is a "SW-only" state, that is state not
 214  * requiring accessing the device or exposing the driver via kernel internal
 215  * or userspace interfaces. Example steps belonging here: lock initialization,
 216  * system memory allocation, setting up device specific attributes and
 217  * function hooks not requiring accessing the device.
 218  */
 219 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 220 {
 221         int ret = 0;
 222
 223         if (i915_inject_probe_failure(dev_priv))
 224                 return -ENODEV;
 225
 226         intel_device_info_runtime_init_early(dev_priv);
 227
 228         intel_step_init(dev_priv);
 229
 230         intel_uncore_mmio_debug_init_early(dev_priv);
 231
 232         spin_lock_init(&dev_priv->irq_lock);
 233         spin_lock_init(&dev_priv->gpu_error.lock);
 234
 235         mutex_init(&dev_priv->sb_lock);
 236         cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
 237
 238         i915_memcpy_init_early(dev_priv);
 239         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 240
 241         ret = i915_workqueues_init(dev_priv);
 242         if (ret < 0)
 243                 return ret;
 244
 245         ret = vlv_suspend_init(dev_priv);
 246         if (ret < 0)
 247                 goto err_workqueues;
 248
 249         ret = intel_region_ttm_device_init(dev_priv);
 250         if (ret)
 251                 goto err_ttm;
 252
 253         ret = intel_root_gt_init_early(dev_priv);
 254         if (ret < 0)
 255                 goto err_rootgt;
 256
 257         i915_gem_init_early(dev_priv);
 258
 259         /* This must be called before any calls to HAS_PCH_* */
 260         intel_detect_pch(dev_priv);
 261
 262         intel_irq_init(dev_priv);
 263         intel_display_driver_early_probe(dev_priv);
 264         intel_clock_gating_hooks_init(dev_priv);
 265
 266         intel_detect_preproduction_hw(dev_priv);
 267
 268         return 0;
 269
 270 err_rootgt:
 271         intel_region_ttm_device_fini(dev_priv);
 272 err_ttm:
 273         vlv_suspend_cleanup(dev_priv);
 274 err_workqueues:
 275         i915_workqueues_cleanup(dev_priv);
 276         return ret;
 277 }
 278
 279 /**
 280  * i915_driver_late_release - cleanup the setup done in
 281  *                             i915_driver_early_probe()
 282  * @dev_priv: device private
 283  */
 284 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
 285 {
 286         intel_irq_fini(dev_priv);
 287         intel_power_domains_cleanup(dev_priv);
 288         i915_gem_cleanup_early(dev_priv);
 289         intel_gt_driver_late_release_all(dev_priv);
 290         intel_region_ttm_device_fini(dev_priv);
 291         vlv_suspend_cleanup(dev_priv);
 292         i915_workqueues_cleanup(dev_priv);
 293
 294         cpu_latency_qos_remove_request(&dev_priv->sb_qos);
 295         mutex_destroy(&dev_priv->sb_lock);
 296
 297         i915_params_free(&dev_priv->params);
 298 }
 299
 300 /**
 301  * i915_driver_mmio_probe - setup device MMIO
 302  * @dev_priv: device private
 303  *
 304  * Setup minimal device state necessary for MMIO accesses later in the
 305  * initialization sequence. The setup here should avoid any other device-wide
 306  * side effects or exposing the driver via kernel internal or user space
 307  * interfaces.
 308  */
 309 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 310 {
 311         struct intel_gt *gt;
 312         int ret, i;
 313
 314         if (i915_inject_probe_failure(dev_priv))
 315                 return -ENODEV;
 316
 317         ret = intel_gmch_bridge_setup(dev_priv);
 318         if (ret < 0)
 319                 return ret;
 320
 321         for_each_gt(gt, dev_priv, i) {
 322                 ret = intel_uncore_init_mmio(gt->uncore);
 323                 if (ret)
 324                         return ret;
 325
 326                 ret = drmm_add_action_or_reset(&dev_priv->drm,
 327                                                intel_uncore_fini_mmio,
 328                                                gt->uncore);
 329                 if (ret)
 330                         return ret;
 331         }
 332
 333         /* Try to make sure MCHBAR is enabled before poking at it */
 334         intel_gmch_bar_setup(dev_priv);
 335         intel_device_info_runtime_init(dev_priv);
 336         intel_display_device_info_runtime_init(dev_priv);
 337
 338         for_each_gt(gt, dev_priv, i) {
 339                 ret = intel_gt_init_mmio(gt);
 340                 if (ret)
 341                         goto err_uncore;
 342         }
 343
 344         /* As early as possible, scrub existing GPU state before clobbering */
 345         sanitize_gpu(dev_priv);
 346
 347         return 0;
 348
 349 err_uncore:
 350         intel_gmch_bar_teardown(dev_priv);
 351
 352         return ret;
 353 }
 354
 355 /**
 356  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
 357  * @dev_priv: device private
 358  */
 359 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 360 {
 361         intel_gmch_bar_teardown(dev_priv);
 362 }
 363
 364 /**
 365  * i915_set_dma_info - set all relevant PCI dma info as configured for the
 366  * platform
 367  * @i915: valid i915 instance
 368  *
 369  * Set the dma max segment size, device and coherent masks.  The dma mask set
 370  * needs to occur before i915_ggtt_probe_hw.
 371  *
 372  * A couple of platforms have special needs.  Address them as well.
 373  *
 374  */
 375 static int i915_set_dma_info(struct drm_i915_private *i915)
 376 {
 377         unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
 378         int ret;
 379
 380         GEM_BUG_ON(!mask_size);
 381
 382         /*
 383          * We don't have a max segment size, so set it to the max so sg's
 384          * debugging layer doesn't complain
 385          */
 386         dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
 387
 388         ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 389         if (ret)
 390                 goto mask_err;
 391
 392         /* overlay on gen2 is broken and can't address above 1G */
 393         if (GRAPHICS_VER(i915) == 2)
 394                 mask_size = 30;
 395
 396         /*
 397          * 965GM sometimes incorrectly writes to hardware status page (HWS)
 398          * using 32bit addressing, overwriting memory if HWS is located
 399          * above 4GB.
 400          *
 401          * The documentation also mentions an issue with undefined
 402          * behaviour if any general state is accessed within a page above 4GB,
 403          * which also needs to be handled carefully.
 404          */
 405         if (IS_I965G(i915) || IS_I965GM(i915))
 406                 mask_size = 32;
 407
 408         ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 409         if (ret)
 410                 goto mask_err;
 411
 412         return 0;
 413
 414 mask_err:
 415         drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
 416         return ret;
 417 }
 418
 419 static int i915_pcode_init(struct drm_i915_private *i915)
 420 {
 421         struct intel_gt *gt;
 422         int id, ret;
 423
 424         for_each_gt(gt, i915, id) {
 425                 ret = intel_pcode_init(gt->uncore);
 426                 if (ret) {
 427                         gt_err(gt, "intel_pcode_init failed %d\n", ret);
 428                         return ret;
 429                 }
 430         }
 431
 432         return 0;
 433 }
 434
 435 /**
 436  * i915_driver_hw_probe - setup state requiring device access
 437  * @dev_priv: device private
 438  *
 439  * Setup state that requires accessing the device, but doesn't require
 440  * exposing the driver via kernel internal or userspace interfaces.
 441  */
 442 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 443 {
 444         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 445         int ret;
 446
 447         if (i915_inject_probe_failure(dev_priv))
 448                 return -ENODEV;
 449
 450         if (HAS_PPGTT(dev_priv)) {
 451                 if (intel_vgpu_active(dev_priv) &&
 452                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
 453                         i915_report_error(dev_priv,
 454                                           "incompatible vGPU found, support for isolated ppGTT required\n");
 455                         return -ENXIO;
 456                 }
 457         }
 458
 459         if (HAS_EXECLISTS(dev_priv)) {
 460                 /*
 461                  * Older GVT emulation depends upon intercepting CSB mmio,
 462                  * which we no longer use, preferring to use the HWSP cache
 463                  * instead.
 464                  */
 465                 if (intel_vgpu_active(dev_priv) &&
 466                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
 467                         i915_report_error(dev_priv,
 468                                           "old vGPU host found, support for HWSP emulation required\n");
 469                         return -ENXIO;
 470                 }
 471         }
 472
 473         /* needs to be done before ggtt probe */
 474         intel_dram_edram_detect(dev_priv);
 475
 476         ret = i915_set_dma_info(dev_priv);
 477         if (ret)
 478                 return ret;
 479
 480         ret = i915_perf_init(dev_priv);
 481         if (ret)
 482                 return ret;
 483
 484         ret = i915_ggtt_probe_hw(dev_priv);
 485         if (ret)
 486                 goto err_perf;
 487
 488         ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver);
 489         if (ret)
 490                 goto err_ggtt;
 491
 492         ret = i915_ggtt_init_hw(dev_priv);
 493         if (ret)
 494                 goto err_ggtt;
 495
 496         /*
 497          * Make sure we probe lmem before we probe stolen-lmem. The BAR size
 498          * might be different due to bar resizing.
 499          */
 500         ret = intel_gt_tiles_init(dev_priv);
 501         if (ret)
 502                 goto err_ggtt;
 503
 504         ret = intel_memory_regions_hw_probe(dev_priv);
 505         if (ret)
 506                 goto err_ggtt;
 507
 508         ret = i915_ggtt_enable_hw(dev_priv);
 509         if (ret) {
 510                 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
 511                 goto err_mem_regions;
 512         }
 513
 514         pci_set_master(pdev);
 515
 516         /* On the 945G/GM, the chipset reports the MSI capability on the
 517          * integrated graphics even though the support isn't actually there
 518          * according to the published specs.  It doesn't appear to function
 519          * correctly in testing on 945G.
 520          * This may be a side effect of MSI having been made available for PEG
 521          * and the registers being closely associated.
 522          *
 523          * According to chipset errata, on the 965GM, MSI interrupts may
 524          * be lost or delayed, and was defeatured. MSI interrupts seem to
 525          * get lost on g4x as well, and interrupt delivery seems to stay
 526          * properly dead afterwards. So we'll just disable them for all
 527          * pre-gen5 chipsets.
 528          *
 529          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
 530          * interrupts even when in MSI mode. This results in spurious
 531          * interrupt warnings if the legacy irq no. is shared with another
 532          * device. The kernel then disables that interrupt source and so
 533          * prevents the other device from working properly.
 534          */
 535         if (GRAPHICS_VER(dev_priv) >= 5) {
 536                 if (pci_enable_msi(pdev) < 0)
 537                         drm_dbg(&dev_priv->drm, "can't enable MSI");
 538         }
 539
 540         ret = intel_gvt_init(dev_priv);
 541         if (ret)
 542                 goto err_msi;
 543
 544         intel_opregion_setup(dev_priv);
 545
 546         ret = i915_pcode_init(dev_priv);
 547         if (ret)
 548                 goto err_opregion;
 549
 550         /*
 551          * Fill the dram structure to get the system dram info. This will be
 552          * used for memory latency calculation.
 553          */
 554         intel_dram_detect(dev_priv);
 555
 556         intel_bw_init_hw(dev_priv);
 557
 558         return 0;
 559
 560 err_opregion:
 561         intel_opregion_cleanup(dev_priv);
 562 err_msi:
 563         if (pdev->msi_enabled)
 564                 pci_disable_msi(pdev);
 565 err_mem_regions:
 566         intel_memory_regions_driver_release(dev_priv);
 567 err_ggtt:
 568         i915_ggtt_driver_release(dev_priv);
 569         i915_gem_drain_freed_objects(dev_priv);
 570         i915_ggtt_driver_late_release(dev_priv);
 571 err_perf:
 572         i915_perf_fini(dev_priv);
 573         return ret;
 574 }
 575
 576 /**
 577  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
 578  * @dev_priv: device private
 579  */
 580 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
 581 {
 582         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 583
 584         i915_perf_fini(dev_priv);
 585
 586         intel_opregion_cleanup(dev_priv);
 587
 588         if (pdev->msi_enabled)
 589                 pci_disable_msi(pdev);
 590 }
 591
 592 /**
 593  * i915_driver_register - register the driver with the rest of the system
 594  * @dev_priv: device private
 595  *
 596  * Perform any steps necessary to make the driver available via kernel
 597  * internal or userspace interfaces.
 598  */
 599 static void i915_driver_register(struct drm_i915_private *dev_priv)
 600 {
 601         struct intel_gt *gt;
 602         unsigned int i;
 603
 604         i915_gem_driver_register(dev_priv);
 605         i915_pmu_register(dev_priv);
 606
 607         intel_vgpu_register(dev_priv);
 608
 609         /* Reveal our presence to userspace */
 610         if (drm_dev_register(&dev_priv->drm, 0)) {
 611                 drm_err(&dev_priv->drm,
 612                         "Failed to register driver for userspace access!\n");
 613                 return;
 614         }
 615
 616         i915_debugfs_register(dev_priv);
 617         i915_setup_sysfs(dev_priv);
 618
 619         /* Depends on sysfs having been initialized */
 620         i915_perf_register(dev_priv);
 621
 622         for_each_gt(gt, dev_priv, i)
 623                 intel_gt_driver_register(gt);
 624
 625         intel_pxp_debugfs_register(dev_priv->pxp);
 626
 627         i915_hwmon_register(dev_priv);
 628
 629         intel_display_driver_register(dev_priv);
 630
 631         intel_power_domains_enable(dev_priv);
 632         intel_runtime_pm_enable(&dev_priv->runtime_pm);
 633
 634         intel_register_dsm_handler();
 635
 636         if (i915_switcheroo_register(dev_priv))
 637                 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
 638 }
 639
 640 /**
 641  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
 642  * @dev_priv: device private
 643  */
 644 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
 645 {
 646         struct intel_gt *gt;
 647         unsigned int i;
 648
 649         i915_switcheroo_unregister(dev_priv);
 650
 651         intel_unregister_dsm_handler();
 652
 653         intel_runtime_pm_disable(&dev_priv->runtime_pm);
 654         intel_power_domains_disable(dev_priv);
 655
 656         intel_display_driver_unregister(dev_priv);
 657
 658         intel_pxp_fini(dev_priv);
 659
 660         for_each_gt(gt, dev_priv, i)
 661                 intel_gt_driver_unregister(gt);
 662
 663         i915_hwmon_unregister(dev_priv);
 664
 665         i915_perf_unregister(dev_priv);
 666         i915_pmu_unregister(dev_priv);
 667
 668         i915_teardown_sysfs(dev_priv);
 669         drm_dev_unplug(&dev_priv->drm);
 670
 671         i915_gem_driver_unregister(dev_priv);
 672 }
 673
 674 void
 675 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p)
 676 {
 677         drm_printf(p, "iommu: %s\n",
 678                    str_enabled_disabled(i915_vtd_active(i915)));
 679 }
 680
 681 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 682 {
 683         if (drm_debug_enabled(DRM_UT_DRIVER)) {
 684                 struct drm_printer p = drm_debug_printer("i915 device info:");
 685                 struct intel_gt *gt;
 686                 unsigned int i;
 687
 688                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
 689                            INTEL_DEVID(dev_priv),
 690                            INTEL_REVID(dev_priv),
 691                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
 692                            intel_subplatform(RUNTIME_INFO(dev_priv),
 693                                              INTEL_INFO(dev_priv)->platform),
 694                            GRAPHICS_VER(dev_priv));
 695
 696                 intel_device_info_print(INTEL_INFO(dev_priv),
 697                                         RUNTIME_INFO(dev_priv), &p);
 698                 i915_print_iommu_status(dev_priv, &p);
 699                 for_each_gt(gt, dev_priv, i)
 700                         intel_gt_info_print(&gt->info, &p);
 701         }
 702
 703         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 704                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
 705         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 706                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
 707         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
 708                 drm_info(&dev_priv->drm,
 709                          "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
 710 }
 711
 712 static struct drm_i915_private *
 713 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 714 {
 715         const struct intel_device_info *match_info =
 716                 (struct intel_device_info *)ent->driver_data;
 717         struct drm_i915_private *i915;
 718
 719         i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver,
 720                                   struct drm_i915_private, drm);
 721         if (IS_ERR(i915))
 722                 return i915;
 723
 724         pci_set_drvdata(pdev, i915);
 725
 726         /* Device parameters start as a copy of module parameters. */
 727         i915_params_copy(&i915->params, &i915_modparams);
 728
 729         /* Set up device info and initial runtime info. */
 730         intel_device_info_driver_create(i915, pdev->device, match_info);
 731
 732         intel_display_device_probe(i915);
 733
 734         return i915;
 735 }
 736
 737 /**
 738  * i915_driver_probe - setup chip and create an initial config
 739  * @pdev: PCI device
 740  * @ent: matching PCI ID entry
 741  *
 742  * The driver probe routine has to do several things:
 743  *   - drive output discovery via intel_display_driver_probe()
 744  *   - initialize the memory manager
 745  *   - allocate initial config memory
 746  *   - setup the DRM framebuffer with the allocated memory
 747  */
 748 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 749 {
 750         struct drm_i915_private *i915;
 751         int ret;
 752
 753         ret = pci_enable_device(pdev);
 754         if (ret) {
 755                 pr_err("Failed to enable graphics device: %pe\n", ERR_PTR(ret));
 756                 return ret;
 757         }
 758
 759         i915 = i915_driver_create(pdev, ent);
 760         if (IS_ERR(i915)) {
 761                 pci_disable_device(pdev);
 762                 return PTR_ERR(i915);
 763         }
 764
 765         ret = i915_driver_early_probe(i915);
 766         if (ret < 0)
 767                 goto out_pci_disable;
 768
 769         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 770
 771         intel_vgpu_detect(i915);
 772
 773         ret = intel_gt_probe_all(i915);
 774         if (ret < 0)
 775                 goto out_runtime_pm_put;
 776
 777         ret = i915_driver_mmio_probe(i915);
 778         if (ret < 0)
 779                 goto out_runtime_pm_put;
 780
 781         ret = i915_driver_hw_probe(i915);
 782         if (ret < 0)
 783                 goto out_cleanup_mmio;
 784
 785         ret = intel_display_driver_probe_noirq(i915);
 786         if (ret < 0)
 787                 goto out_cleanup_hw;
 788
 789         ret = intel_irq_install(i915);
 790         if (ret)
 791                 goto out_cleanup_modeset;
 792
 793         ret = intel_display_driver_probe_nogem(i915);
 794         if (ret)
 795                 goto out_cleanup_irq;
 796
 797         ret = i915_gem_init(i915);
 798         if (ret)
 799                 goto out_cleanup_modeset2;
 800
 801         ret = intel_pxp_init(i915);
 802         if (ret != -ENODEV)
 803                 drm_dbg(&i915->drm, "pxp init failed with %d\n", ret);
 804
 805         ret = intel_display_driver_probe(i915);
 806         if (ret)
 807                 goto out_cleanup_gem;
 808
 809         i915_driver_register(i915);
 810
 811         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 812
 813         i915_welcome_messages(i915);
 814
 815         i915->do_release = true;
 816
 817         return 0;
 818
 819 out_cleanup_gem:
 820         i915_gem_suspend(i915);
 821         i915_gem_driver_remove(i915);
 822         i915_gem_driver_release(i915);
 823 out_cleanup_modeset2:
 824         /* FIXME clean up the error path */
 825         intel_display_driver_remove(i915);
 826         intel_irq_uninstall(i915);
 827         intel_display_driver_remove_noirq(i915);
 828         goto out_cleanup_modeset;
 829 out_cleanup_irq:
 830         intel_irq_uninstall(i915);
 831 out_cleanup_modeset:
 832         intel_display_driver_remove_nogem(i915);
 833 out_cleanup_hw:
 834         i915_driver_hw_remove(i915);
 835         intel_memory_regions_driver_release(i915);
 836         i915_ggtt_driver_release(i915);
 837         i915_gem_drain_freed_objects(i915);
 838         i915_ggtt_driver_late_release(i915);
 839 out_cleanup_mmio:
 840         i915_driver_mmio_release(i915);
 841 out_runtime_pm_put:
 842         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 843         i915_driver_late_release(i915);
 844 out_pci_disable:
 845         pci_disable_device(pdev);
 846         i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
 847         return ret;
 848 }
 849
 850 void i915_driver_remove(struct drm_i915_private *i915)
 851 {
 852         intel_wakeref_t wakeref;
 853
 854         wakeref = intel_runtime_pm_get(&i915->runtime_pm);
 855
 856         i915_driver_unregister(i915);
 857
 858         /* Flush any external code that still may be under the RCU lock */
 859         synchronize_rcu();
 860
 861         i915_gem_suspend(i915);
 862
 863         intel_gvt_driver_remove(i915);
 864
 865         intel_display_driver_remove(i915);
 866
 867         intel_irq_uninstall(i915);
 868
 869         intel_display_driver_remove_noirq(i915);
 870
 871         i915_reset_error_state(i915);
 872         i915_gem_driver_remove(i915);
 873
 874         intel_display_driver_remove_nogem(i915);
 875
 876         i915_driver_hw_remove(i915);
 877
 878         intel_runtime_pm_put(&i915->runtime_pm, wakeref);
 879 }
 880
 881 static void i915_driver_release(struct drm_device *dev)
 882 {
 883         struct drm_i915_private *dev_priv = to_i915(dev);
 884         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
 885         intel_wakeref_t wakeref;
 886
 887         if (!dev_priv->do_release)
 888                 return;
 889
 890         wakeref = intel_runtime_pm_get(rpm);
 891
 892         i915_gem_driver_release(dev_priv);
 893
 894         intel_memory_regions_driver_release(dev_priv);
 895         i915_ggtt_driver_release(dev_priv);
 896         i915_gem_drain_freed_objects(dev_priv);
 897         i915_ggtt_driver_late_release(dev_priv);
 898
 899         i915_driver_mmio_release(dev_priv);
 900
 901         intel_runtime_pm_put(rpm, wakeref);
 902
 903         intel_runtime_pm_driver_release(rpm);
 904
 905         i915_driver_late_release(dev_priv);
 906
 907         intel_display_device_remove(dev_priv);
 908 }
 909
 910 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
 911 {
 912         struct drm_i915_private *i915 = to_i915(dev);
 913         int ret;
 914
 915         ret = i915_gem_open(i915, file);
 916         if (ret)
 917                 return ret;
 918
 919         return 0;
 920 }
 921
 922 /**
 923  * i915_driver_lastclose - clean up after all DRM clients have exited
 924  * @dev: DRM device
 925  *
 926  * Take care of cleaning up after all DRM clients have exited.  In the
 927  * mode setting case, we want to restore the kernel's initial mode (just
 928  * in case the last client left us in a bad state).
 929  *
 930  * Additionally, in the non-mode setting case, we'll tear down the GTT
 931  * and DMA structures, since the kernel won't be using them, and clea
 932  * up any GEM state.
 933  */
 934 static void i915_driver_lastclose(struct drm_device *dev)
 935 {
 936         struct drm_i915_private *i915 = to_i915(dev);
 937
 938         intel_fbdev_restore_mode(i915);
 939
 940         vga_switcheroo_process_delayed_switch();
 941 }
 942
 943 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
 944 {
 945         struct drm_i915_file_private *file_priv = file->driver_priv;
 946
 947         i915_gem_context_close(file);
 948         i915_drm_client_put(file_priv->client);
 949
 950         kfree_rcu(file_priv, rcu);
 951
 952         /* Catch up with all the deferred frees from "this" client */
 953         i915_gem_flush_free_objects(to_i915(dev));
 954 }
 955
 956 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
 957 {
 958         struct intel_encoder *encoder;
 959
 960         if (!HAS_DISPLAY(dev_priv))
 961                 return;
 962
 963         /*
 964          * TODO: check and remove holding the modeset locks if none of
 965          * the encoders depends on this.
 966          */
 967         drm_modeset_lock_all(&dev_priv->drm);
 968         for_each_intel_encoder(&dev_priv->drm, encoder)
 969                 if (encoder->suspend)
 970                         encoder->suspend(encoder);
 971         drm_modeset_unlock_all(&dev_priv->drm);
 972
 973         for_each_intel_encoder(&dev_priv->drm, encoder)
 974                 if (encoder->suspend_complete)
 975                         encoder->suspend_complete(encoder);
 976 }
 977
 978 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
 979 {
 980         struct intel_encoder *encoder;
 981
 982         if (!HAS_DISPLAY(dev_priv))
 983                 return;
 984
 985         /*
 986          * TODO: check and remove holding the modeset locks if none of
 987          * the encoders depends on this.
 988          */
 989         drm_modeset_lock_all(&dev_priv->drm);
 990         for_each_intel_encoder(&dev_priv->drm, encoder)
 991                 if (encoder->shutdown)
 992                         encoder->shutdown(encoder);
 993         drm_modeset_unlock_all(&dev_priv->drm);
 994
 995         for_each_intel_encoder(&dev_priv->drm, encoder)
 996                 if (encoder->shutdown_complete)
 997                         encoder->shutdown_complete(encoder);
 998 }
 999
1000 void i915_driver_shutdown(struct drm_i915_private *i915)
1001 {
1002         disable_rpm_wakeref_asserts(&i915->runtime_pm);
1003         intel_runtime_pm_disable(&i915->runtime_pm);
1004         intel_power_domains_disable(i915);
1005
1006         intel_fbdev_set_suspend(&i915->drm, FBINFO_STATE_SUSPENDED, true);
1007         if (HAS_DISPLAY(i915)) {
1008                 drm_kms_helper_poll_disable(&i915->drm);
1009                 intel_display_driver_disable_user_access(i915);
1010
1011                 drm_atomic_helper_shutdown(&i915->drm);
1012         }
1013
1014         intel_dp_mst_suspend(i915);
1015
1016         intel_runtime_pm_disable_interrupts(i915);
1017         intel_hpd_cancel_work(i915);
1018
1019         if (HAS_DISPLAY(i915))
1020                 intel_display_driver_suspend_access(i915);
1021
1022         intel_suspend_encoders(i915);
1023         intel_shutdown_encoders(i915);
1024
1025         intel_dmc_suspend(i915);
1026
1027         i915_gem_suspend(i915);
1028
1029         /*
1030          * The only requirement is to reboot with display DC states disabled,
1031          * for now leaving all display power wells in the INIT power domain
1032          * enabled.
1033          *
1034          * TODO:
1035          * - unify the pci_driver::shutdown sequence here with the
1036          *   pci_driver.driver.pm.poweroff,poweroff_late sequence.
1037          * - unify the driver remove and system/runtime suspend sequences with
1038          *   the above unified shutdown/poweroff sequence.
1039          */
1040         intel_power_domains_driver_remove(i915);
1041         enable_rpm_wakeref_asserts(&i915->runtime_pm);
1042
1043         intel_runtime_pm_driver_last_release(&i915->runtime_pm);
1044 }
1045
1046 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1047 {
1048 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1049         if (acpi_target_system_state() < ACPI_STATE_S3)
1050                 return true;
1051 #endif
1052         return false;
1053 }
1054
1055 static void i915_drm_complete(struct drm_device *dev)
1056 {
1057         struct drm_i915_private *i915 = to_i915(dev);
1058
1059         intel_pxp_resume_complete(i915->pxp);
1060 }
1061
1062 static int i915_drm_prepare(struct drm_device *dev)
1063 {
1064         struct drm_i915_private *i915 = to_i915(dev);
1065
1066         intel_pxp_suspend_prepare(i915->pxp);
1067
1068         /*
1069          * NB intel_display_driver_suspend() may issue new requests after we've
1070          * ostensibly marked the GPU as ready-to-sleep here. We need to
1071          * split out that work and pull it forward so that after point,
1072          * the GPU is not woken again.
1073          */
1074         return i915_gem_backup_suspend(i915);
1075 }
1076
1077 static int i915_drm_suspend(struct drm_device *dev)
1078 {
1079         struct drm_i915_private *dev_priv = to_i915(dev);
1080         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1081         pci_power_t opregion_target_state;
1082
1083         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1084
1085         /* We do a lot of poking in a lot of registers, make sure they work
1086          * properly. */
1087         intel_power_domains_disable(dev_priv);
1088         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1089         if (HAS_DISPLAY(dev_priv)) {
1090                 drm_kms_helper_poll_disable(dev);
1091                 intel_display_driver_disable_user_access(dev_priv);
1092         }
1093
1094         pci_save_state(pdev);
1095
1096         intel_display_driver_suspend(dev_priv);
1097
1098         intel_dp_mst_suspend(dev_priv);
1099
1100         intel_runtime_pm_disable_interrupts(dev_priv);
1101         intel_hpd_cancel_work(dev_priv);
1102
1103         if (HAS_DISPLAY(dev_priv))
1104                 intel_display_driver_suspend_access(dev_priv);
1105
1106         intel_suspend_encoders(dev_priv);
1107
1108         /* Must be called before GGTT is suspended. */
1109         intel_dpt_suspend(dev_priv);
1110         i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
1111
1112         i915_save_display(dev_priv);
1113
1114         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1115         intel_opregion_suspend(dev_priv, opregion_target_state);
1116
1117         dev_priv->suspend_count++;
1118
1119         intel_dmc_suspend(dev_priv);
1120
1121         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1122
1123         i915_gem_drain_freed_objects(dev_priv);
1124
1125         return 0;
1126 }
1127
1128 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1129 {
1130         struct drm_i915_private *dev_priv = to_i915(dev);
1131         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1132         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1133         struct intel_gt *gt;
1134         int ret, i;
1135         bool s2idle = !hibernation && suspend_to_idle(dev_priv);
1136
1137         disable_rpm_wakeref_asserts(rpm);
1138
1139         intel_pxp_suspend(dev_priv->pxp);
1140
1141         i915_gem_suspend_late(dev_priv);
1142
1143         for_each_gt(gt, dev_priv, i)
1144                 intel_uncore_suspend(gt->uncore);
1145
1146         intel_power_domains_suspend(dev_priv, s2idle);
1147
1148         intel_display_power_suspend_late(dev_priv);
1149
1150         ret = vlv_suspend_complete(dev_priv);
1151         if (ret) {
1152                 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1153                 intel_power_domains_resume(dev_priv);
1154
1155                 goto out;
1156         }
1157
1158         pci_disable_device(pdev);
1159         /*
1160          * During hibernation on some platforms the BIOS may try to access
1161          * the device even though it's already in D3 and hang the machine. So
1162          * leave the device in D0 on those platforms and hope the BIOS will
1163          * power down the device properly. The issue was seen on multiple old
1164          * GENs with different BIOS vendors, so having an explicit blacklist
1165          * is inpractical; apply the workaround on everything pre GEN6. The
1166          * platforms where the issue was seen:
1167          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1168          * Fujitsu FSC S7110
1169          * Acer Aspire 1830T
1170          */
1171         if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))
1172                 pci_set_power_state(pdev, PCI_D3hot);
1173
1174 out:
1175         enable_rpm_wakeref_asserts(rpm);
1176         if (!dev_priv->uncore.user_forcewake_count)
1177                 intel_runtime_pm_driver_release(rpm);
1178
1179         return ret;
1180 }
1181
1182 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915,
1183                                    pm_message_t state)
1184 {
1185         int error;
1186
1187         if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1188                              state.event != PM_EVENT_FREEZE))
1189                 return -EINVAL;
1190
1191         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1192                 return 0;
1193
1194         error = i915_drm_suspend(&i915->drm);
1195         if (error)
1196                 return error;
1197
1198         return i915_drm_suspend_late(&i915->drm, false);
1199 }
1200
1201 static int i915_drm_resume(struct drm_device *dev)
1202 {
1203         struct drm_i915_private *dev_priv = to_i915(dev);
1204         struct intel_gt *gt;
1205         int ret, i;
1206
1207         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1208
1209         ret = i915_pcode_init(dev_priv);
1210         if (ret)
1211                 return ret;
1212
1213         sanitize_gpu(dev_priv);
1214
1215         ret = i915_ggtt_enable_hw(dev_priv);
1216         if (ret)
1217                 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1218
1219         i915_ggtt_resume(to_gt(dev_priv)->ggtt);
1220
1221         for_each_gt(gt, dev_priv, i)
1222                 if (GRAPHICS_VER(gt->i915) >= 8)
1223                         setup_private_pat(gt);
1224
1225         /* Must be called after GGTT is resumed. */
1226         intel_dpt_resume(dev_priv);
1227
1228         intel_dmc_resume(dev_priv);
1229
1230         i915_restore_display(dev_priv);
1231         intel_pps_unlock_regs_wa(dev_priv);
1232
1233         intel_init_pch_refclk(dev_priv);
1234
1235         /*
1236          * Interrupts have to be enabled before any batches are run. If not the
1237          * GPU will hang. i915_gem_init_hw() will initiate batches to
1238          * update/restore the context.
1239          *
1240          * drm_mode_config_reset() needs AUX interrupts.
1241          *
1242          * Modeset enabling in intel_display_driver_init_hw() also needs working
1243          * interrupts.
1244          */
1245         intel_runtime_pm_enable_interrupts(dev_priv);
1246
1247         if (HAS_DISPLAY(dev_priv))
1248                 drm_mode_config_reset(dev);
1249
1250         i915_gem_resume(dev_priv);
1251
1252         intel_display_driver_init_hw(dev_priv);
1253
1254         intel_clock_gating_init(dev_priv);
1255
1256         if (HAS_DISPLAY(dev_priv))
1257                 intel_display_driver_resume_access(dev_priv);
1258
1259         intel_hpd_init(dev_priv);
1260
1261         /* MST sideband requires HPD interrupts enabled */
1262         intel_dp_mst_resume(dev_priv);
1263         intel_display_driver_resume(dev_priv);
1264
1265         if (HAS_DISPLAY(dev_priv)) {
1266                 intel_display_driver_enable_user_access(dev_priv);
1267                 drm_kms_helper_poll_enable(dev);
1268         }
1269         intel_hpd_poll_disable(dev_priv);
1270
1271         intel_opregion_resume(dev_priv);
1272
1273         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1274
1275         intel_power_domains_enable(dev_priv);
1276
1277         intel_gvt_resume(dev_priv);
1278
1279         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1280
1281         return 0;
1282 }
1283
1284 static int i915_drm_resume_early(struct drm_device *dev)
1285 {
1286         struct drm_i915_private *dev_priv = to_i915(dev);
1287         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1288         struct intel_gt *gt;
1289         int ret, i;
1290
1291         /*
1292          * We have a resume ordering issue with the snd-hda driver also
1293          * requiring our device to be power up. Due to the lack of a
1294          * parent/child relationship we currently solve this with an early
1295          * resume hook.
1296          *
1297          * FIXME: This should be solved with a special hdmi sink device or
1298          * similar so that power domains can be employed.
1299          */
1300
1301         /*
1302          * Note that we need to set the power state explicitly, since we
1303          * powered off the device during freeze and the PCI core won't power
1304          * it back up for us during thaw. Powering off the device during
1305          * freeze is not a hard requirement though, and during the
1306          * suspend/resume phases the PCI core makes sure we get here with the
1307          * device powered on. So in case we change our freeze logic and keep
1308          * the device powered we can also remove the following set power state
1309          * call.
1310          */
1311         ret = pci_set_power_state(pdev, PCI_D0);
1312         if (ret) {
1313                 drm_err(&dev_priv->drm,
1314                         "failed to set PCI D0 power state (%d)\n", ret);
1315                 return ret;
1316         }
1317
1318         /*
1319          * Note that pci_enable_device() first enables any parent bridge
1320          * device and only then sets the power state for this device. The
1321          * bridge enabling is a nop though, since bridge devices are resumed
1322          * first. The order of enabling power and enabling the device is
1323          * imposed by the PCI core as described above, so here we preserve the
1324          * same order for the freeze/thaw phases.
1325          *
1326          * TODO: eventually we should remove pci_disable_device() /
1327          * pci_enable_enable_device() from suspend/resume. Due to how they
1328          * depend on the device enable refcount we can't anyway depend on them
1329          * disabling/enabling the device.
1330          */
1331         if (pci_enable_device(pdev))
1332                 return -EIO;
1333
1334         pci_set_master(pdev);
1335
1336         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1337
1338         ret = vlv_resume_prepare(dev_priv, false);
1339         if (ret)
1340                 drm_err(&dev_priv->drm,
1341                         "Resume prepare failed: %d, continuing anyway\n", ret);
1342
1343         for_each_gt(gt, dev_priv, i)
1344                 intel_gt_resume_early(gt);
1345
1346         intel_display_power_resume_early(dev_priv);
1347
1348         intel_power_domains_resume(dev_priv);
1349
1350         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1351
1352         return ret;
1353 }
1354
1355 int i915_driver_resume_switcheroo(struct drm_i915_private *i915)
1356 {
1357         int ret;
1358
1359         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1360                 return 0;
1361
1362         ret = i915_drm_resume_early(&i915->drm);
1363         if (ret)
1364                 return ret;
1365
1366         return i915_drm_resume(&i915->drm);
1367 }
1368
1369 static int i915_pm_prepare(struct device *kdev)
1370 {
1371         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1372
1373         if (!i915) {
1374                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1375                 return -ENODEV;
1376         }
1377
1378         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1379                 return 0;
1380
1381         return i915_drm_prepare(&i915->drm);
1382 }
1383
1384 static int i915_pm_suspend(struct device *kdev)
1385 {
1386         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1387
1388         if (!i915) {
1389                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1390                 return -ENODEV;
1391         }
1392
1393         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1394                 return 0;
1395
1396         return i915_drm_suspend(&i915->drm);
1397 }
1398
1399 static int i915_pm_suspend_late(struct device *kdev)
1400 {
1401         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1402
1403         /*
1404          * We have a suspend ordering issue with the snd-hda driver also
1405          * requiring our device to be power up. Due to the lack of a
1406          * parent/child relationship we currently solve this with an late
1407          * suspend hook.
1408          *
1409          * FIXME: This should be solved with a special hdmi sink device or
1410          * similar so that power domains can be employed.
1411          */
1412         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1413                 return 0;
1414
1415         return i915_drm_suspend_late(&i915->drm, false);
1416 }
1417
1418 static int i915_pm_poweroff_late(struct device *kdev)
1419 {
1420         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1421
1422         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1423                 return 0;
1424
1425         return i915_drm_suspend_late(&i915->drm, true);
1426 }
1427
1428 static int i915_pm_resume_early(struct device *kdev)
1429 {
1430         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1431
1432         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1433                 return 0;
1434
1435         return i915_drm_resume_early(&i915->drm);
1436 }
1437
1438 static int i915_pm_resume(struct device *kdev)
1439 {
1440         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1441
1442         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1443                 return 0;
1444
1445         return i915_drm_resume(&i915->drm);
1446 }
1447
1448 static void i915_pm_complete(struct device *kdev)
1449 {
1450         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1451
1452         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1453                 return;
1454
1455         i915_drm_complete(&i915->drm);
1456 }
1457
1458 /* freeze: before creating the hibernation_image */
1459 static int i915_pm_freeze(struct device *kdev)
1460 {
1461         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1462         int ret;
1463
1464         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1465                 ret = i915_drm_suspend(&i915->drm);
1466                 if (ret)
1467                         return ret;
1468         }
1469
1470         ret = i915_gem_freeze(i915);
1471         if (ret)
1472                 return ret;
1473
1474         return 0;
1475 }
1476
1477 static int i915_pm_freeze_late(struct device *kdev)
1478 {
1479         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1480         int ret;
1481
1482         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1483                 ret = i915_drm_suspend_late(&i915->drm, true);
1484                 if (ret)
1485                         return ret;
1486         }
1487
1488         ret = i915_gem_freeze_late(i915);
1489         if (ret)
1490                 return ret;
1491
1492         return 0;
1493 }
1494
1495 /* thaw: called after creating the hibernation image, but before turning off. */
1496 static int i915_pm_thaw_early(struct device *kdev)
1497 {
1498         return i915_pm_resume_early(kdev);
1499 }
1500
1501 static int i915_pm_thaw(struct device *kdev)
1502 {
1503         return i915_pm_resume(kdev);
1504 }
1505
1506 /* restore: called after loading the hibernation image. */
1507 static int i915_pm_restore_early(struct device *kdev)
1508 {
1509         return i915_pm_resume_early(kdev);
1510 }
1511
1512 static int i915_pm_restore(struct device *kdev)
1513 {
1514         return i915_pm_resume(kdev);
1515 }
1516
1517 static int intel_runtime_suspend(struct device *kdev)
1518 {
1519         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1520         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1521         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1522         struct pci_dev *root_pdev;
1523         struct intel_gt *gt;
1524         int ret, i;
1525
1526         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1527                 return -ENODEV;
1528
1529         drm_dbg(&dev_priv->drm, "Suspending device\n");
1530
1531         disable_rpm_wakeref_asserts(rpm);
1532
1533         /*
1534          * We are safe here against re-faults, since the fault handler takes
1535          * an RPM reference.
1536          */
1537         i915_gem_runtime_suspend(dev_priv);
1538
1539         intel_pxp_runtime_suspend(dev_priv->pxp);
1540
1541         for_each_gt(gt, dev_priv, i)
1542                 intel_gt_runtime_suspend(gt);
1543
1544         intel_runtime_pm_disable_interrupts(dev_priv);
1545
1546         for_each_gt(gt, dev_priv, i)
1547                 intel_uncore_suspend(gt->uncore);
1548
1549         intel_display_power_suspend(dev_priv);
1550
1551         ret = vlv_suspend_complete(dev_priv);
1552         if (ret) {
1553                 drm_err(&dev_priv->drm,
1554                         "Runtime suspend failed, disabling it (%d)\n", ret);
1555                 intel_uncore_runtime_resume(&dev_priv->uncore);
1556
1557                 intel_runtime_pm_enable_interrupts(dev_priv);
1558
1559                 for_each_gt(gt, dev_priv, i)
1560                         intel_gt_runtime_resume(gt);
1561
1562                 enable_rpm_wakeref_asserts(rpm);
1563
1564                 return ret;
1565         }
1566
1567         enable_rpm_wakeref_asserts(rpm);
1568         intel_runtime_pm_driver_release(rpm);
1569
1570         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1571                 drm_err(&dev_priv->drm,
1572                         "Unclaimed access detected prior to suspending\n");
1573
1574         /*
1575          * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
1576          * This should be totally removed when we handle the pci states properly
1577          * on runtime PM.
1578          */
1579         root_pdev = pcie_find_root_port(pdev);
1580         if (root_pdev)
1581                 pci_d3cold_disable(root_pdev);
1582
1583         /*
1584          * FIXME: We really should find a document that references the arguments
1585          * used below!
1586          */
1587         if (IS_BROADWELL(dev_priv)) {
1588                 /*
1589                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1590                  * being detected, and the call we do at intel_runtime_resume()
1591                  * won't be able to restore them. Since PCI_D3hot matches the
1592                  * actual specification and appears to be working, use it.
1593                  */
1594                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1595         } else {
1596                 /*
1597                  * current versions of firmware which depend on this opregion
1598                  * notification have repurposed the D1 definition to mean
1599                  * "runtime suspended" vs. what you would normally expect (D3)
1600                  * to distinguish it from notifications that might be sent via
1601                  * the suspend path.
1602                  */
1603                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1604         }
1605
1606         assert_forcewakes_inactive(&dev_priv->uncore);
1607
1608         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1609                 intel_hpd_poll_enable(dev_priv);
1610
1611         drm_dbg(&dev_priv->drm, "Device suspended\n");
1612         return 0;
1613 }
1614
1615 static int intel_runtime_resume(struct device *kdev)
1616 {
1617         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1618         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1619         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1620         struct pci_dev *root_pdev;
1621         struct intel_gt *gt;
1622         int ret, i;
1623
1624         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1625                 return -ENODEV;
1626
1627         drm_dbg(&dev_priv->drm, "Resuming device\n");
1628
1629         drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1630         disable_rpm_wakeref_asserts(rpm);
1631
1632         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1633
1634         root_pdev = pcie_find_root_port(pdev);
1635         if (root_pdev)
1636                 pci_d3cold_enable(root_pdev);
1637
1638         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1639                 drm_dbg(&dev_priv->drm,
1640                         "Unclaimed access during suspend, bios?\n");
1641
1642         intel_display_power_resume(dev_priv);
1643
1644         ret = vlv_resume_prepare(dev_priv, true);
1645
1646         for_each_gt(gt, dev_priv, i)
1647                 intel_uncore_runtime_resume(gt->uncore);
1648
1649         intel_runtime_pm_enable_interrupts(dev_priv);
1650
1651         /*
1652          * No point of rolling back things in case of an error, as the best
1653          * we can do is to hope that things will still work (and disable RPM).
1654          */
1655         for_each_gt(gt, dev_priv, i)
1656                 intel_gt_runtime_resume(gt);
1657
1658         intel_pxp_runtime_resume(dev_priv->pxp);
1659
1660         /*
1661          * On VLV/CHV display interrupts are part of the display
1662          * power well, so hpd is reinitialized from there. For
1663          * everyone else do it here.
1664          */
1665         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1666                 intel_hpd_init(dev_priv);
1667                 intel_hpd_poll_disable(dev_priv);
1668         }
1669
1670         skl_watermark_ipc_update(dev_priv);
1671
1672         enable_rpm_wakeref_asserts(rpm);
1673
1674         if (ret)
1675                 drm_err(&dev_priv->drm,
1676                         "Runtime resume failed, disabling it (%d)\n", ret);
1677         else
1678                 drm_dbg(&dev_priv->drm, "Device resumed\n");
1679
1680         return ret;
1681 }
1682
1683 const struct dev_pm_ops i915_pm_ops = {
1684         /*
1685          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1686          * PMSG_RESUME]
1687          */
1688         .prepare = i915_pm_prepare,
1689         .suspend = i915_pm_suspend,
1690         .suspend_late = i915_pm_suspend_late,
1691         .resume_early = i915_pm_resume_early,
1692         .resume = i915_pm_resume,
1693         .complete = i915_pm_complete,
1694
1695         /*
1696          * S4 event handlers
1697          * @freeze, @freeze_late    : called (1) before creating the
1698          *                            hibernation image [PMSG_FREEZE] and
1699          *                            (2) after rebooting, before restoring
1700          *                            the image [PMSG_QUIESCE]
1701          * @thaw, @thaw_early       : called (1) after creating the hibernation
1702          *                            image, before writing it [PMSG_THAW]
1703          *                            and (2) after failing to create or
1704          *                            restore the image [PMSG_RECOVER]
1705          * @poweroff, @poweroff_late: called after writing the hibernation
1706          *                            image, before rebooting [PMSG_HIBERNATE]
1707          * @restore, @restore_early : called after rebooting and restoring the
1708          *                            hibernation image [PMSG_RESTORE]
1709          */
1710         .freeze = i915_pm_freeze,
1711         .freeze_late = i915_pm_freeze_late,
1712         .thaw_early = i915_pm_thaw_early,
1713         .thaw = i915_pm_thaw,
1714         .poweroff = i915_pm_suspend,
1715         .poweroff_late = i915_pm_poweroff_late,
1716         .restore_early = i915_pm_restore_early,
1717         .restore = i915_pm_restore,
1718
1719         /* S0ix (via runtime suspend) event handlers */
1720         .runtime_suspend = intel_runtime_suspend,
1721         .runtime_resume = intel_runtime_resume,
1722 };
1723
1724 static const struct file_operations i915_driver_fops = {
1725         .owner = THIS_MODULE,
1726         .open = drm_open,
1727         .release = drm_release_noglobal,
1728         .unlocked_ioctl = drm_ioctl,
1729         .mmap = i915_gem_mmap,
1730         .poll = drm_poll,
1731         .read = drm_read,
1732         .compat_ioctl = i915_ioc32_compat_ioctl,
1733         .llseek = noop_llseek,
1734 #ifdef CONFIG_PROC_FS
1735         .show_fdinfo = drm_show_fdinfo,
1736 #endif
1737 };
1738
1739 static int
1740 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1741                           struct drm_file *file)
1742 {
1743         return -ENODEV;
1744 }
1745
1746 static const struct drm_ioctl_desc i915_ioctls[] = {
1747         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1748         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1749         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1750         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1751         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1752         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1753         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1754         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1755         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1756         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1757         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1758         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1759         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1760         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1761         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1762         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1763         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1764         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1765         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1766         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1767         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1768         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1769         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1770         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1771         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1772         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1773         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1774         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1775         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1776         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW),
1777         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1778         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1779         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1780         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1781         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1782         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1783         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1784         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1785         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1786         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1787         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1788         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1789         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1790         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1791         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1792         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1793         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1794         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1795         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1796         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1797         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1798         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1799         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1800         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1801         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1802         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1803         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1804         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1805         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1806 };
1807
1808 /*
1809  * Interface history:
1810  *
1811  * 1.1: Original.
1812  * 1.2: Add Power Management
1813  * 1.3: Add vblank support
1814  * 1.4: Fix cmdbuffer path, add heap destroy
1815  * 1.5: Add vblank pipe configuration
1816  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
1817  *      - Support vertical blank on secondary display pipe
1818  */
1819 #define DRIVER_MAJOR            1
1820 #define DRIVER_MINOR            6
1821 #define DRIVER_PATCHLEVEL       0
1822
1823 static const struct drm_driver i915_drm_driver = {
1824         /* Don't use MTRRs here; the Xserver or userspace app should
1825          * deal with them for Intel hardware.
1826          */
1827         .driver_features =
1828             DRIVER_GEM |
1829             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1830             DRIVER_SYNCOBJ_TIMELINE,
1831         .release = i915_driver_release,
1832         .open = i915_driver_open,
1833         .lastclose = i915_driver_lastclose,
1834         .postclose = i915_driver_postclose,
1835         .show_fdinfo = PTR_IF(IS_ENABLED(CONFIG_PROC_FS), i915_drm_client_fdinfo),
1836
1837         .gem_prime_import = i915_gem_prime_import,
1838
1839         .dumb_create = i915_gem_dumb_create,
1840         .dumb_map_offset = i915_gem_dumb_mmap_offset,
1841
1842         .ioctls = i915_ioctls,
1843         .num_ioctls = ARRAY_SIZE(i915_ioctls),
1844         .fops = &i915_driver_fops,
1845         .name = DRIVER_NAME,
1846         .desc = DRIVER_DESC,
1847         .date = DRIVER_DATE,
1848         .major = DRIVER_MAJOR,
1849         .minor = DRIVER_MINOR,
1850         .patchlevel = DRIVER_PATCHLEVEL,
1851 };