drivers/gpu/drm/i915/gvt/cmd_parser.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ke Yu
  25  *    Kevin Tian <kevin.tian@intel.com>
  26  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
  27  *
  28  * Contributors:
  29  *    Min He <min.he@intel.com>
  30  *    Ping Gao <ping.a.gao@intel.com>
  31  *    Tina Zhang <tina.zhang@intel.com>
  32  *    Yulei Zhang <yulei.zhang@intel.com>
  33  *    Zhi Wang <zhi.a.wang@intel.com>
  34  *
  35  */
  36
  37 #include <linux/slab.h>
  38 #include "i915_drv.h"
  39 #include "gvt.h"
  40 #include "i915_pvinfo.h"
  41 #include "trace.h"
  42
  43 #define INVALID_OP    (~0U)
  44
  45 #define OP_LEN_MI           9
  46 #define OP_LEN_2D           10
  47 #define OP_LEN_3D_MEDIA     16
  48 #define OP_LEN_MFX_VC       16
  49 #define OP_LEN_VEBOX        16
  50
  51 #define CMD_TYPE(cmd)   (((cmd) >> 29) & 7)
  52
  53 struct sub_op_bits {
  54         int hi;
  55         int low;
  56 };
  57 struct decode_info {
  58         const char *name;
  59         int op_len;
  60         int nr_sub_op;
  61         const struct sub_op_bits *sub_op;
  62 };
  63
  64 #define   MAX_CMD_BUDGET                        0x7fffffff
  65 #define   MI_WAIT_FOR_PLANE_C_FLIP_PENDING      (1<<15)
  66 #define   MI_WAIT_FOR_PLANE_B_FLIP_PENDING      (1<<9)
  67 #define   MI_WAIT_FOR_PLANE_A_FLIP_PENDING      (1<<1)
  68
  69 #define   MI_WAIT_FOR_SPRITE_C_FLIP_PENDING      (1<<20)
  70 #define   MI_WAIT_FOR_SPRITE_B_FLIP_PENDING      (1<<10)
  71 #define   MI_WAIT_FOR_SPRITE_A_FLIP_PENDING      (1<<2)
  72
  73 /* Render Command Map */
  74
  75 /* MI_* command Opcode (28:23) */
  76 #define OP_MI_NOOP                          0x0
  77 #define OP_MI_SET_PREDICATE                 0x1  /* HSW+ */
  78 #define OP_MI_USER_INTERRUPT                0x2
  79 #define OP_MI_WAIT_FOR_EVENT                0x3
  80 #define OP_MI_FLUSH                         0x4
  81 #define OP_MI_ARB_CHECK                     0x5
  82 #define OP_MI_RS_CONTROL                    0x6  /* HSW+ */
  83 #define OP_MI_REPORT_HEAD                   0x7
  84 #define OP_MI_ARB_ON_OFF                    0x8
  85 #define OP_MI_URB_ATOMIC_ALLOC              0x9  /* HSW+ */
  86 #define OP_MI_BATCH_BUFFER_END              0xA
  87 #define OP_MI_SUSPEND_FLUSH                 0xB
  88 #define OP_MI_PREDICATE                     0xC  /* IVB+ */
  89 #define OP_MI_TOPOLOGY_FILTER               0xD  /* IVB+ */
  90 #define OP_MI_SET_APPID                     0xE  /* IVB+ */
  91 #define OP_MI_RS_CONTEXT                    0xF  /* HSW+ */
  92 #define OP_MI_LOAD_SCAN_LINES_INCL          0x12 /* HSW+ */
  93 #define OP_MI_DISPLAY_FLIP                  0x14
  94 #define OP_MI_SEMAPHORE_MBOX                0x16
  95 #define OP_MI_SET_CONTEXT                   0x18
  96 #define OP_MI_MATH                          0x1A
  97 #define OP_MI_URB_CLEAR                     0x19
  98 #define OP_MI_SEMAPHORE_SIGNAL              0x1B  /* BDW+ */
  99 #define OP_MI_SEMAPHORE_WAIT                0x1C  /* BDW+ */
 100
 101 #define OP_MI_STORE_DATA_IMM                0x20
 102 #define OP_MI_STORE_DATA_INDEX              0x21
 103 #define OP_MI_LOAD_REGISTER_IMM             0x22
 104 #define OP_MI_UPDATE_GTT                    0x23
 105 #define OP_MI_STORE_REGISTER_MEM            0x24
 106 #define OP_MI_FLUSH_DW                      0x26
 107 #define OP_MI_CLFLUSH                       0x27
 108 #define OP_MI_REPORT_PERF_COUNT             0x28
 109 #define OP_MI_LOAD_REGISTER_MEM             0x29  /* HSW+ */
 110 #define OP_MI_LOAD_REGISTER_REG             0x2A  /* HSW+ */
 111 #define OP_MI_RS_STORE_DATA_IMM             0x2B  /* HSW+ */
 112 #define OP_MI_LOAD_URB_MEM                  0x2C  /* HSW+ */
 113 #define OP_MI_STORE_URM_MEM                 0x2D  /* HSW+ */
 114 #define OP_MI_2E                            0x2E  /* BDW+ */
 115 #define OP_MI_2F                            0x2F  /* BDW+ */
 116 #define OP_MI_BATCH_BUFFER_START            0x31
 117
 118 /* Bit definition for dword 0 */
 119 #define _CMDBIT_BB_START_IN_PPGTT       (1UL << 8)
 120
 121 #define OP_MI_CONDITIONAL_BATCH_BUFFER_END  0x36
 122
 123 #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
 124 #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
 125 #define BATCH_BUFFER_ADR_SPACE_BIT(x)   (((x) >> 8) & 1U)
 126 #define BATCH_BUFFER_2ND_LEVEL_BIT(x)   ((x) >> 22 & 1U)
 127
 128 /* 2D command: Opcode (28:22) */
 129 #define OP_2D(x)    ((2<<7) | x)
 130
 131 #define OP_XY_SETUP_BLT                             OP_2D(0x1)
 132 #define OP_XY_SETUP_CLIP_BLT                        OP_2D(0x3)
 133 #define OP_XY_SETUP_MONO_PATTERN_SL_BLT             OP_2D(0x11)
 134 #define OP_XY_PIXEL_BLT                             OP_2D(0x24)
 135 #define OP_XY_SCANLINES_BLT                         OP_2D(0x25)
 136 #define OP_XY_TEXT_BLT                              OP_2D(0x26)
 137 #define OP_XY_TEXT_IMMEDIATE_BLT                    OP_2D(0x31)
 138 #define OP_XY_COLOR_BLT                             OP_2D(0x50)
 139 #define OP_XY_PAT_BLT                               OP_2D(0x51)
 140 #define OP_XY_MONO_PAT_BLT                          OP_2D(0x52)
 141 #define OP_XY_SRC_COPY_BLT                          OP_2D(0x53)
 142 #define OP_XY_MONO_SRC_COPY_BLT                     OP_2D(0x54)
 143 #define OP_XY_FULL_BLT                              OP_2D(0x55)
 144 #define OP_XY_FULL_MONO_SRC_BLT                     OP_2D(0x56)
 145 #define OP_XY_FULL_MONO_PATTERN_BLT                 OP_2D(0x57)
 146 #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT        OP_2D(0x58)
 147 #define OP_XY_MONO_PAT_FIXED_BLT                    OP_2D(0x59)
 148 #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT           OP_2D(0x71)
 149 #define OP_XY_PAT_BLT_IMMEDIATE                     OP_2D(0x72)
 150 #define OP_XY_SRC_COPY_CHROMA_BLT                   OP_2D(0x73)
 151 #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT            OP_2D(0x74)
 152 #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT   OP_2D(0x75)
 153 #define OP_XY_PAT_CHROMA_BLT                        OP_2D(0x76)
 154 #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE              OP_2D(0x77)
 155
 156 /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
 157 #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
 158         ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
 159
 160 #define OP_STATE_PREFETCH                       OP_3D_MEDIA(0x0, 0x0, 0x03)
 161
 162 #define OP_STATE_BASE_ADDRESS                   OP_3D_MEDIA(0x0, 0x1, 0x01)
 163 #define OP_STATE_SIP                            OP_3D_MEDIA(0x0, 0x1, 0x02)
 164 #define OP_3D_MEDIA_0_1_4                       OP_3D_MEDIA(0x0, 0x1, 0x04)
 165
 166 #define OP_3DSTATE_VF_STATISTICS_GM45           OP_3D_MEDIA(0x1, 0x0, 0x0B)
 167
 168 #define OP_PIPELINE_SELECT                      OP_3D_MEDIA(0x1, 0x1, 0x04)
 169
 170 #define OP_MEDIA_VFE_STATE                      OP_3D_MEDIA(0x2, 0x0, 0x0)
 171 #define OP_MEDIA_CURBE_LOAD                     OP_3D_MEDIA(0x2, 0x0, 0x1)
 172 #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD      OP_3D_MEDIA(0x2, 0x0, 0x2)
 173 #define OP_MEDIA_GATEWAY_STATE                  OP_3D_MEDIA(0x2, 0x0, 0x3)
 174 #define OP_MEDIA_STATE_FLUSH                    OP_3D_MEDIA(0x2, 0x0, 0x4)
 175 #define OP_MEDIA_POOL_STATE                     OP_3D_MEDIA(0x2, 0x0, 0x5)
 176
 177 #define OP_MEDIA_OBJECT                         OP_3D_MEDIA(0x2, 0x1, 0x0)
 178 #define OP_MEDIA_OBJECT_PRT                     OP_3D_MEDIA(0x2, 0x1, 0x2)
 179 #define OP_MEDIA_OBJECT_WALKER                  OP_3D_MEDIA(0x2, 0x1, 0x3)
 180 #define OP_GPGPU_WALKER                         OP_3D_MEDIA(0x2, 0x1, 0x5)
 181
 182 #define OP_3DSTATE_CLEAR_PARAMS                 OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
 183 #define OP_3DSTATE_DEPTH_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
 184 #define OP_3DSTATE_STENCIL_BUFFER               OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
 185 #define OP_3DSTATE_HIER_DEPTH_BUFFER            OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
 186 #define OP_3DSTATE_VERTEX_BUFFERS               OP_3D_MEDIA(0x3, 0x0, 0x08)
 187 #define OP_3DSTATE_VERTEX_ELEMENTS              OP_3D_MEDIA(0x3, 0x0, 0x09)
 188 #define OP_3DSTATE_INDEX_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x0A)
 189 #define OP_3DSTATE_VF_STATISTICS                OP_3D_MEDIA(0x3, 0x0, 0x0B)
 190 #define OP_3DSTATE_VF                           OP_3D_MEDIA(0x3, 0x0, 0x0C)  /* HSW+ */
 191 #define OP_3DSTATE_CC_STATE_POINTERS            OP_3D_MEDIA(0x3, 0x0, 0x0E)
 192 #define OP_3DSTATE_SCISSOR_STATE_POINTERS       OP_3D_MEDIA(0x3, 0x0, 0x0F)
 193 #define OP_3DSTATE_VS                           OP_3D_MEDIA(0x3, 0x0, 0x10)
 194 #define OP_3DSTATE_GS                           OP_3D_MEDIA(0x3, 0x0, 0x11)
 195 #define OP_3DSTATE_CLIP                         OP_3D_MEDIA(0x3, 0x0, 0x12)
 196 #define OP_3DSTATE_SF                           OP_3D_MEDIA(0x3, 0x0, 0x13)
 197 #define OP_3DSTATE_WM                           OP_3D_MEDIA(0x3, 0x0, 0x14)
 198 #define OP_3DSTATE_CONSTANT_VS                  OP_3D_MEDIA(0x3, 0x0, 0x15)
 199 #define OP_3DSTATE_CONSTANT_GS                  OP_3D_MEDIA(0x3, 0x0, 0x16)
 200 #define OP_3DSTATE_CONSTANT_PS                  OP_3D_MEDIA(0x3, 0x0, 0x17)
 201 #define OP_3DSTATE_SAMPLE_MASK                  OP_3D_MEDIA(0x3, 0x0, 0x18)
 202 #define OP_3DSTATE_CONSTANT_HS                  OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
 203 #define OP_3DSTATE_CONSTANT_DS                  OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
 204 #define OP_3DSTATE_HS                           OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
 205 #define OP_3DSTATE_TE                           OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
 206 #define OP_3DSTATE_DS                           OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
 207 #define OP_3DSTATE_STREAMOUT                    OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
 208 #define OP_3DSTATE_SBE                          OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
 209 #define OP_3DSTATE_PS                           OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
 210 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
 211 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC   OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
 212 #define OP_3DSTATE_BLEND_STATE_POINTERS         OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
 213 #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
 214 #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
 215 #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
 216 #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
 217 #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
 218 #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
 219 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
 220 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
 221 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
 222 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
 223 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
 224 #define OP_3DSTATE_URB_VS                       OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
 225 #define OP_3DSTATE_URB_HS                       OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
 226 #define OP_3DSTATE_URB_DS                       OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
 227 #define OP_3DSTATE_URB_GS                       OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
 228 #define OP_3DSTATE_GATHER_CONSTANT_VS           OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
 229 #define OP_3DSTATE_GATHER_CONSTANT_GS           OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
 230 #define OP_3DSTATE_GATHER_CONSTANT_HS           OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
 231 #define OP_3DSTATE_GATHER_CONSTANT_DS           OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
 232 #define OP_3DSTATE_GATHER_CONSTANT_PS           OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
 233 #define OP_3DSTATE_DX9_CONSTANTF_VS             OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
 234 #define OP_3DSTATE_DX9_CONSTANTF_PS             OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
 235 #define OP_3DSTATE_DX9_CONSTANTI_VS             OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
 236 #define OP_3DSTATE_DX9_CONSTANTI_PS             OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
 237 #define OP_3DSTATE_DX9_CONSTANTB_VS             OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
 238 #define OP_3DSTATE_DX9_CONSTANTB_PS             OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
 239 #define OP_3DSTATE_DX9_LOCAL_VALID_VS           OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
 240 #define OP_3DSTATE_DX9_LOCAL_VALID_PS           OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
 241 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS       OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
 242 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS       OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
 243 #define OP_3DSTATE_BINDING_TABLE_EDIT_VS        OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
 244 #define OP_3DSTATE_BINDING_TABLE_EDIT_GS        OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
 245 #define OP_3DSTATE_BINDING_TABLE_EDIT_HS        OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
 246 #define OP_3DSTATE_BINDING_TABLE_EDIT_DS        OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
 247 #define OP_3DSTATE_BINDING_TABLE_EDIT_PS        OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
 248
 249 #define OP_3DSTATE_VF_INSTANCING                OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
 250 #define OP_3DSTATE_VF_SGVS                      OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
 251 #define OP_3DSTATE_VF_TOPOLOGY                  OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
 252 #define OP_3DSTATE_WM_CHROMAKEY                 OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
 253 #define OP_3DSTATE_PS_BLEND                     OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
 254 #define OP_3DSTATE_WM_DEPTH_STENCIL             OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
 255 #define OP_3DSTATE_PS_EXTRA                     OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
 256 #define OP_3DSTATE_RASTER                       OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
 257 #define OP_3DSTATE_SBE_SWIZ                     OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
 258 #define OP_3DSTATE_WM_HZ_OP                     OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
 259 #define OP_3DSTATE_COMPONENT_PACKING            OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
 260
 261 #define OP_3DSTATE_DRAWING_RECTANGLE            OP_3D_MEDIA(0x3, 0x1, 0x00)
 262 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0        OP_3D_MEDIA(0x3, 0x1, 0x02)
 263 #define OP_3DSTATE_CHROMA_KEY                   OP_3D_MEDIA(0x3, 0x1, 0x04)
 264 #define OP_SNB_3DSTATE_DEPTH_BUFFER             OP_3D_MEDIA(0x3, 0x1, 0x05)
 265 #define OP_3DSTATE_POLY_STIPPLE_OFFSET          OP_3D_MEDIA(0x3, 0x1, 0x06)
 266 #define OP_3DSTATE_POLY_STIPPLE_PATTERN         OP_3D_MEDIA(0x3, 0x1, 0x07)
 267 #define OP_3DSTATE_LINE_STIPPLE                 OP_3D_MEDIA(0x3, 0x1, 0x08)
 268 #define OP_3DSTATE_AA_LINE_PARAMS               OP_3D_MEDIA(0x3, 0x1, 0x0A)
 269 #define OP_3DSTATE_GS_SVB_INDEX                 OP_3D_MEDIA(0x3, 0x1, 0x0B)
 270 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1        OP_3D_MEDIA(0x3, 0x1, 0x0C)
 271 #define OP_3DSTATE_MULTISAMPLE_BDW              OP_3D_MEDIA(0x3, 0x0, 0x0D)
 272 #define OP_SNB_3DSTATE_STENCIL_BUFFER           OP_3D_MEDIA(0x3, 0x1, 0x0E)
 273 #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER        OP_3D_MEDIA(0x3, 0x1, 0x0F)
 274 #define OP_SNB_3DSTATE_CLEAR_PARAMS             OP_3D_MEDIA(0x3, 0x1, 0x10)
 275 #define OP_3DSTATE_MONOFILTER_SIZE              OP_3D_MEDIA(0x3, 0x1, 0x11)
 276 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS       OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
 277 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS       OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
 278 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS       OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
 279 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS       OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
 280 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS       OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
 281 #define OP_3DSTATE_SO_DECL_LIST                 OP_3D_MEDIA(0x3, 0x1, 0x17)
 282 #define OP_3DSTATE_SO_BUFFER                    OP_3D_MEDIA(0x3, 0x1, 0x18)
 283 #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC     OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
 284 #define OP_3DSTATE_GATHER_POOL_ALLOC            OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
 285 #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
 286 #define OP_3DSTATE_SAMPLE_PATTERN               OP_3D_MEDIA(0x3, 0x1, 0x1C)
 287 #define OP_PIPE_CONTROL                         OP_3D_MEDIA(0x3, 0x2, 0x00)
 288 #define OP_3DPRIMITIVE                          OP_3D_MEDIA(0x3, 0x3, 0x00)
 289
 290 /* VCCP Command Parser */
 291
 292 /*
 293  * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
 294  * git://anongit.freedesktop.org/vaapi/intel-driver
 295  * src/i965_defines.h
 296  *
 297  */
 298
 299 #define OP_MFX(pipeline, op, sub_opa, sub_opb)     \
 300         (3 << 13 | \
 301          (pipeline) << 11 | \
 302          (op) << 8 | \
 303          (sub_opa) << 5 | \
 304          (sub_opb))
 305
 306 #define OP_MFX_PIPE_MODE_SELECT                    OP_MFX(2, 0, 0, 0)  /* ALL */
 307 #define OP_MFX_SURFACE_STATE                       OP_MFX(2, 0, 0, 1)  /* ALL */
 308 #define OP_MFX_PIPE_BUF_ADDR_STATE                 OP_MFX(2, 0, 0, 2)  /* ALL */
 309 #define OP_MFX_IND_OBJ_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 3)  /* ALL */
 310 #define OP_MFX_BSP_BUF_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 4)  /* ALL */
 311 #define OP_2_0_0_5                                 OP_MFX(2, 0, 0, 5)  /* ALL */
 312 #define OP_MFX_STATE_POINTER                       OP_MFX(2, 0, 0, 6)  /* ALL */
 313 #define OP_MFX_QM_STATE                            OP_MFX(2, 0, 0, 7)  /* IVB+ */
 314 #define OP_MFX_FQM_STATE                           OP_MFX(2, 0, 0, 8)  /* IVB+ */
 315 #define OP_MFX_PAK_INSERT_OBJECT                   OP_MFX(2, 0, 2, 8)  /* IVB+ */
 316 #define OP_MFX_STITCH_OBJECT                       OP_MFX(2, 0, 2, 0xA)  /* IVB+ */
 317
 318 #define OP_MFD_IT_OBJECT                           OP_MFX(2, 0, 1, 9) /* ALL */
 319
 320 #define OP_MFX_WAIT                                OP_MFX(1, 0, 0, 0) /* IVB+ */
 321 #define OP_MFX_AVC_IMG_STATE                       OP_MFX(2, 1, 0, 0) /* ALL */
 322 #define OP_MFX_AVC_QM_STATE                        OP_MFX(2, 1, 0, 1) /* ALL */
 323 #define OP_MFX_AVC_DIRECTMODE_STATE                OP_MFX(2, 1, 0, 2) /* ALL */
 324 #define OP_MFX_AVC_SLICE_STATE                     OP_MFX(2, 1, 0, 3) /* ALL */
 325 #define OP_MFX_AVC_REF_IDX_STATE                   OP_MFX(2, 1, 0, 4) /* ALL */
 326 #define OP_MFX_AVC_WEIGHTOFFSET_STATE              OP_MFX(2, 1, 0, 5) /* ALL */
 327 #define OP_MFD_AVC_PICID_STATE                     OP_MFX(2, 1, 1, 5) /* HSW+ */
 328 #define OP_MFD_AVC_DPB_STATE                       OP_MFX(2, 1, 1, 6) /* IVB+ */
 329 #define OP_MFD_AVC_SLICEADDR                       OP_MFX(2, 1, 1, 7) /* IVB+ */
 330 #define OP_MFD_AVC_BSD_OBJECT                      OP_MFX(2, 1, 1, 8) /* ALL */
 331 #define OP_MFC_AVC_PAK_OBJECT                      OP_MFX(2, 1, 2, 9) /* ALL */
 332
 333 #define OP_MFX_VC1_PRED_PIPE_STATE                 OP_MFX(2, 2, 0, 1) /* ALL */
 334 #define OP_MFX_VC1_DIRECTMODE_STATE                OP_MFX(2, 2, 0, 2) /* ALL */
 335 #define OP_MFD_VC1_SHORT_PIC_STATE                 OP_MFX(2, 2, 1, 0) /* IVB+ */
 336 #define OP_MFD_VC1_LONG_PIC_STATE                  OP_MFX(2, 2, 1, 1) /* IVB+ */
 337 #define OP_MFD_VC1_BSD_OBJECT                      OP_MFX(2, 2, 1, 8) /* ALL */
 338
 339 #define OP_MFX_MPEG2_PIC_STATE                     OP_MFX(2, 3, 0, 0) /* ALL */
 340 #define OP_MFX_MPEG2_QM_STATE                      OP_MFX(2, 3, 0, 1) /* ALL */
 341 #define OP_MFD_MPEG2_BSD_OBJECT                    OP_MFX(2, 3, 1, 8) /* ALL */
 342 #define OP_MFC_MPEG2_SLICEGROUP_STATE              OP_MFX(2, 3, 2, 3) /* ALL */
 343 #define OP_MFC_MPEG2_PAK_OBJECT                    OP_MFX(2, 3, 2, 9) /* ALL */
 344
 345 #define OP_MFX_2_6_0_0                             OP_MFX(2, 6, 0, 0) /* IVB+ */
 346 #define OP_MFX_2_6_0_8                             OP_MFX(2, 6, 0, 8) /* IVB+ */
 347 #define OP_MFX_2_6_0_9                             OP_MFX(2, 6, 0, 9) /* IVB+ */
 348
 349 #define OP_MFX_JPEG_PIC_STATE                      OP_MFX(2, 7, 0, 0)
 350 #define OP_MFX_JPEG_HUFF_TABLE_STATE               OP_MFX(2, 7, 0, 2)
 351 #define OP_MFD_JPEG_BSD_OBJECT                     OP_MFX(2, 7, 1, 8)
 352
 353 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
 354         (3 << 13 | \
 355          (pipeline) << 11 | \
 356          (op) << 8 | \
 357          (sub_opa) << 5 | \
 358          (sub_opb))
 359
 360 #define OP_VEB_SURFACE_STATE                       OP_VEB(2, 4, 0, 0)
 361 #define OP_VEB_STATE                               OP_VEB(2, 4, 0, 2)
 362 #define OP_VEB_DNDI_IECP_STATE                     OP_VEB(2, 4, 0, 3)
 363
 364 struct parser_exec_state;
 365
 366 typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
 367
 368 #define GVT_CMD_HASH_BITS   7
 369
 370 /* which DWords need address fix */
 371 #define ADDR_FIX_1(x1)                  (1 << (x1))
 372 #define ADDR_FIX_2(x1, x2)              (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
 373 #define ADDR_FIX_3(x1, x2, x3)          (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
 374 #define ADDR_FIX_4(x1, x2, x3, x4)      (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
 375 #define ADDR_FIX_5(x1, x2, x3, x4, x5)  (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
 376
 377 struct cmd_info {
 378         const char *name;
 379         u32 opcode;
 380
 381 #define F_LEN_MASK      (1U<<0)
 382 #define F_LEN_CONST  1U
 383 #define F_LEN_VAR    0U
 384
 385 /*
 386  * command has its own ip advance logic
 387  * e.g. MI_BATCH_START, MI_BATCH_END
 388  */
 389 #define F_IP_ADVANCE_CUSTOM (1<<1)
 390
 391 #define F_POST_HANDLE   (1<<2)
 392         u32 flag;
 393
 394 #define R_RCS   BIT(RCS0)
 395 #define R_VCS1  BIT(VCS0)
 396 #define R_VCS2  BIT(VCS1)
 397 #define R_VCS   (R_VCS1 | R_VCS2)
 398 #define R_BCS   BIT(BCS0)
 399 #define R_VECS  BIT(VECS0)
 400 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
 401         /* rings that support this cmd: BLT/RCS/VCS/VECS */
 402         u16 rings;
 403
 404         /* devices that support this cmd: SNB/IVB/HSW/... */
 405         u16 devices;
 406
 407         /* which DWords are address that need fix up.
 408          * bit 0 means a 32-bit non address operand in command
 409          * bit 1 means address operand, which could be 32-bit
 410          * or 64-bit depending on different architectures.(
 411          * defined by "gmadr_bytes_in_cmd" in intel_gvt.
 412          * No matter the address length, each address only takes
 413          * one bit in the bitmap.
 414          */
 415         u16 addr_bitmap;
 416
 417         /* flag == F_LEN_CONST : command length
 418          * flag == F_LEN_VAR : length bias bits
 419          * Note: length is in DWord
 420          */
 421         u8 len;
 422
 423         parser_cmd_handler handler;
 424 };
 425
 426 struct cmd_entry {
 427         struct hlist_node hlist;
 428         const struct cmd_info *info;
 429 };
 430
 431 enum {
 432         RING_BUFFER_INSTRUCTION,
 433         BATCH_BUFFER_INSTRUCTION,
 434         BATCH_BUFFER_2ND_LEVEL,
 435 };
 436
 437 enum {
 438         GTT_BUFFER,
 439         PPGTT_BUFFER
 440 };
 441
 442 struct parser_exec_state {
 443         struct intel_vgpu *vgpu;
 444         int ring_id;
 445
 446         int buf_type;
 447
 448         /* batch buffer address type */
 449         int buf_addr_type;
 450
 451         /* graphics memory address of ring buffer start */
 452         unsigned long ring_start;
 453         unsigned long ring_size;
 454         unsigned long ring_head;
 455         unsigned long ring_tail;
 456
 457         /* instruction graphics memory address */
 458         unsigned long ip_gma;
 459
 460         /* mapped va of the instr_gma */
 461         void *ip_va;
 462         void *rb_va;
 463
 464         void *ret_bb_va;
 465         /* next instruction when return from  batch buffer to ring buffer */
 466         unsigned long ret_ip_gma_ring;
 467
 468         /* next instruction when return from 2nd batch buffer to batch buffer */
 469         unsigned long ret_ip_gma_bb;
 470
 471         /* batch buffer address type (GTT or PPGTT)
 472          * used when ret from 2nd level batch buffer
 473          */
 474         int saved_buf_addr_type;
 475         bool is_ctx_wa;
 476
 477         const struct cmd_info *info;
 478
 479         struct intel_vgpu_workload *workload;
 480 };
 481
 482 #define gmadr_dw_number(s)      \
 483         (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
 484
 485 static unsigned long bypass_scan_mask = 0;
 486
 487 /* ring ALL, type = 0 */
 488 static const struct sub_op_bits sub_op_mi[] = {
 489         {31, 29},
 490         {28, 23},
 491 };
 492
 493 static const struct decode_info decode_info_mi = {
 494         "MI",
 495         OP_LEN_MI,
 496         ARRAY_SIZE(sub_op_mi),
 497         sub_op_mi,
 498 };
 499
 500 /* ring RCS, command type 2 */
 501 static const struct sub_op_bits sub_op_2d[] = {
 502         {31, 29},
 503         {28, 22},
 504 };
 505
 506 static const struct decode_info decode_info_2d = {
 507         "2D",
 508         OP_LEN_2D,
 509         ARRAY_SIZE(sub_op_2d),
 510         sub_op_2d,
 511 };
 512
 513 /* ring RCS, command type 3 */
 514 static const struct sub_op_bits sub_op_3d_media[] = {
 515         {31, 29},
 516         {28, 27},
 517         {26, 24},
 518         {23, 16},
 519 };
 520
 521 static const struct decode_info decode_info_3d_media = {
 522         "3D_Media",
 523         OP_LEN_3D_MEDIA,
 524         ARRAY_SIZE(sub_op_3d_media),
 525         sub_op_3d_media,
 526 };
 527
 528 /* ring VCS, command type 3 */
 529 static const struct sub_op_bits sub_op_mfx_vc[] = {
 530         {31, 29},
 531         {28, 27},
 532         {26, 24},
 533         {23, 21},
 534         {20, 16},
 535 };
 536
 537 static const struct decode_info decode_info_mfx_vc = {
 538         "MFX_VC",
 539         OP_LEN_MFX_VC,
 540         ARRAY_SIZE(sub_op_mfx_vc),
 541         sub_op_mfx_vc,
 542 };
 543
 544 /* ring VECS, command type 3 */
 545 static const struct sub_op_bits sub_op_vebox[] = {
 546         {31, 29},
 547         {28, 27},
 548         {26, 24},
 549         {23, 21},
 550         {20, 16},
 551 };
 552
 553 static const struct decode_info decode_info_vebox = {
 554         "VEBOX",
 555         OP_LEN_VEBOX,
 556         ARRAY_SIZE(sub_op_vebox),
 557         sub_op_vebox,
 558 };
 559
 560 static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
 561         [RCS0] = {
 562                 &decode_info_mi,
 563                 NULL,
 564                 NULL,
 565                 &decode_info_3d_media,
 566                 NULL,
 567                 NULL,
 568                 NULL,
 569                 NULL,
 570         },
 571
 572         [VCS0] = {
 573                 &decode_info_mi,
 574                 NULL,
 575                 NULL,
 576                 &decode_info_mfx_vc,
 577                 NULL,
 578                 NULL,
 579                 NULL,
 580                 NULL,
 581         },
 582
 583         [BCS0] = {
 584                 &decode_info_mi,
 585                 NULL,
 586                 &decode_info_2d,
 587                 NULL,
 588                 NULL,
 589                 NULL,
 590                 NULL,
 591                 NULL,
 592         },
 593
 594         [VECS0] = {
 595                 &decode_info_mi,
 596                 NULL,
 597                 NULL,
 598                 &decode_info_vebox,
 599                 NULL,
 600                 NULL,
 601                 NULL,
 602                 NULL,
 603         },
 604
 605         [VCS1] = {
 606                 &decode_info_mi,
 607                 NULL,
 608                 NULL,
 609                 &decode_info_mfx_vc,
 610                 NULL,
 611                 NULL,
 612                 NULL,
 613                 NULL,
 614         },
 615 };
 616
 617 static inline u32 get_opcode(u32 cmd, int ring_id)
 618 {
 619         const struct decode_info *d_info;
 620
 621         d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
 622         if (d_info == NULL)
 623                 return INVALID_OP;
 624
 625         return cmd >> (32 - d_info->op_len);
 626 }
 627
 628 static inline const struct cmd_info *find_cmd_entry(struct intel_gvt *gvt,
 629                 unsigned int opcode, int ring_id)
 630 {
 631         struct cmd_entry *e;
 632
 633         hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
 634                 if (opcode == e->info->opcode && e->info->rings & BIT(ring_id))
 635                         return e->info;
 636         }
 637         return NULL;
 638 }
 639
 640 static inline const struct cmd_info *get_cmd_info(struct intel_gvt *gvt,
 641                 u32 cmd, int ring_id)
 642 {
 643         u32 opcode;
 644
 645         opcode = get_opcode(cmd, ring_id);
 646         if (opcode == INVALID_OP)
 647                 return NULL;
 648
 649         return find_cmd_entry(gvt, opcode, ring_id);
 650 }
 651
 652 static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
 653 {
 654         return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
 655 }
 656
 657 static inline void print_opcode(u32 cmd, int ring_id)
 658 {
 659         const struct decode_info *d_info;
 660         int i;
 661
 662         d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
 663         if (d_info == NULL)
 664                 return;
 665
 666         gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
 667                         cmd >> (32 - d_info->op_len), d_info->name);
 668
 669         for (i = 0; i < d_info->nr_sub_op; i++)
 670                 pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
 671                                         d_info->sub_op[i].low));
 672
 673         pr_err("\n");
 674 }
 675
 676 static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
 677 {
 678         return s->ip_va + (index << 2);
 679 }
 680
 681 static inline u32 cmd_val(struct parser_exec_state *s, int index)
 682 {
 683         return *cmd_ptr(s, index);
 684 }
 685
 686 static void parser_exec_state_dump(struct parser_exec_state *s)
 687 {
 688         int cnt = 0;
 689         int i;
 690
 691         gvt_dbg_cmd("  vgpu%d RING%d: ring_start(%08lx) ring_end(%08lx)"
 692                         " ring_head(%08lx) ring_tail(%08lx)\n", s->vgpu->id,
 693                         s->ring_id, s->ring_start, s->ring_start + s->ring_size,
 694                         s->ring_head, s->ring_tail);
 695
 696         gvt_dbg_cmd("  %s %s ip_gma(%08lx) ",
 697                         s->buf_type == RING_BUFFER_INSTRUCTION ?
 698                         "RING_BUFFER" : "BATCH_BUFFER",
 699                         s->buf_addr_type == GTT_BUFFER ?
 700                         "GTT" : "PPGTT", s->ip_gma);
 701
 702         if (s->ip_va == NULL) {
 703                 gvt_dbg_cmd(" ip_va(NULL)");
 704                 return;
 705         }
 706
 707         gvt_dbg_cmd("  ip_va=%p: %08x %08x %08x %08x\n",
 708                         s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
 709                         cmd_val(s, 2), cmd_val(s, 3));
 710
 711         print_opcode(cmd_val(s, 0), s->ring_id);
 712
 713         s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
 714
 715         while (cnt < 1024) {
 716                 gvt_dbg_cmd("ip_va=%p: ", s->ip_va);
 717                 for (i = 0; i < 8; i++)
 718                         gvt_dbg_cmd("%08x ", cmd_val(s, i));
 719                 gvt_dbg_cmd("\n");
 720
 721                 s->ip_va += 8 * sizeof(u32);
 722                 cnt += 8;
 723         }
 724 }
 725
 726 static inline void update_ip_va(struct parser_exec_state *s)
 727 {
 728         unsigned long len = 0;
 729
 730         if (WARN_ON(s->ring_head == s->ring_tail))
 731                 return;
 732
 733         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
 734                 unsigned long ring_top = s->ring_start + s->ring_size;
 735
 736                 if (s->ring_head > s->ring_tail) {
 737                         if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
 738                                 len = (s->ip_gma - s->ring_head);
 739                         else if (s->ip_gma >= s->ring_start &&
 740                                         s->ip_gma <= s->ring_tail)
 741                                 len = (ring_top - s->ring_head) +
 742                                         (s->ip_gma - s->ring_start);
 743                 } else
 744                         len = (s->ip_gma - s->ring_head);
 745
 746                 s->ip_va = s->rb_va + len;
 747         } else {/* shadow batch buffer */
 748                 s->ip_va = s->ret_bb_va;
 749         }
 750 }
 751
 752 static inline int ip_gma_set(struct parser_exec_state *s,
 753                 unsigned long ip_gma)
 754 {
 755         WARN_ON(!IS_ALIGNED(ip_gma, 4));
 756
 757         s->ip_gma = ip_gma;
 758         update_ip_va(s);
 759         return 0;
 760 }
 761
 762 static inline int ip_gma_advance(struct parser_exec_state *s,
 763                 unsigned int dw_len)
 764 {
 765         s->ip_gma += (dw_len << 2);
 766
 767         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
 768                 if (s->ip_gma >= s->ring_start + s->ring_size)
 769                         s->ip_gma -= s->ring_size;
 770                 update_ip_va(s);
 771         } else {
 772                 s->ip_va += (dw_len << 2);
 773         }
 774
 775         return 0;
 776 }
 777
 778 static inline int get_cmd_length(const struct cmd_info *info, u32 cmd)
 779 {
 780         if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
 781                 return info->len;
 782         else
 783                 return (cmd & ((1U << info->len) - 1)) + 2;
 784         return 0;
 785 }
 786
 787 static inline int cmd_length(struct parser_exec_state *s)
 788 {
 789         return get_cmd_length(s->info, cmd_val(s, 0));
 790 }
 791
 792 /* do not remove this, some platform may need clflush here */
 793 #define patch_value(s, addr, val) do { \
 794         *addr = val; \
 795 } while (0)
 796
 797 static bool is_shadowed_mmio(unsigned int offset)
 798 {
 799         bool ret = false;
 800
 801         if ((offset == 0x2168) || /*BB current head register UDW */
 802             (offset == 0x2140) || /*BB current header register */
 803             (offset == 0x211c) || /*second BB header register UDW */
 804             (offset == 0x2114)) { /*second BB header register UDW */
 805                 ret = true;
 806         }
 807         return ret;
 808 }
 809
 810 static inline bool is_force_nonpriv_mmio(unsigned int offset)
 811 {
 812         return (offset >= 0x24d0 && offset < 0x2500);
 813 }
 814
 815 static int force_nonpriv_reg_handler(struct parser_exec_state *s,
 816                 unsigned int offset, unsigned int index, char *cmd)
 817 {
 818         struct intel_gvt *gvt = s->vgpu->gvt;
 819         unsigned int data;
 820         u32 ring_base;
 821         u32 nopid;
 822         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
 823
 824         if (!strcmp(cmd, "lri"))
 825                 data = cmd_val(s, index + 1);
 826         else {
 827                 gvt_err("Unexpected forcenonpriv 0x%x write from cmd %s\n",
 828                         offset, cmd);
 829                 return -EINVAL;
 830         }
 831
 832         ring_base = dev_priv->engine[s->ring_id]->mmio_base;
 833         nopid = i915_mmio_reg_offset(RING_NOPID(ring_base));
 834
 835         if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) &&
 836                         data != nopid) {
 837                 gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
 838                         offset, data);
 839                 patch_value(s, cmd_ptr(s, index), nopid);
 840                 return 0;
 841         }
 842         return 0;
 843 }
 844
 845 static inline bool is_mocs_mmio(unsigned int offset)
 846 {
 847         return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
 848                 ((offset >= 0xb020) && (offset <= 0xb0a0));
 849 }
 850
 851 static int mocs_cmd_reg_handler(struct parser_exec_state *s,
 852                                 unsigned int offset, unsigned int index)
 853 {
 854         if (!is_mocs_mmio(offset))
 855                 return -EINVAL;
 856         vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1);
 857         return 0;
 858 }
 859
 860 static int cmd_reg_handler(struct parser_exec_state *s,
 861         unsigned int offset, unsigned int index, char *cmd)
 862 {
 863         struct intel_vgpu *vgpu = s->vgpu;
 864         struct intel_gvt *gvt = vgpu->gvt;
 865         u32 ctx_sr_ctl;
 866
 867         if (offset + 4 > gvt->device_info.mmio_size) {
 868                 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
 869                                 cmd, offset);
 870                 return -EFAULT;
 871         }
 872
 873         if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) {
 874                 gvt_vgpu_err("%s access to non-render register (%x)\n",
 875                                 cmd, offset);
 876                 return -EBADRQC;
 877         }
 878
 879         if (is_shadowed_mmio(offset)) {
 880                 gvt_vgpu_err("found access of shadowed MMIO %x\n", offset);
 881                 return 0;
 882         }
 883
 884         if (is_mocs_mmio(offset) &&
 885             mocs_cmd_reg_handler(s, offset, index))
 886                 return -EINVAL;
 887
 888         if (is_force_nonpriv_mmio(offset) &&
 889                 force_nonpriv_reg_handler(s, offset, index, cmd))
 890                 return -EPERM;
 891
 892         if (offset == i915_mmio_reg_offset(DERRMR) ||
 893                 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
 894                 /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
 895                 patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
 896         }
 897
 898         /* TODO
 899          * Right now only scan LRI command on KBL and in inhibit context.
 900          * It's good enough to support initializing mmio by lri command in
 901          * vgpu inhibit context on KBL.
 902          */
 903         if ((IS_KABYLAKE(s->vgpu->gvt->dev_priv)
 904                 || IS_COFFEELAKE(s->vgpu->gvt->dev_priv)) &&
 905                         intel_gvt_mmio_is_in_ctx(gvt, offset) &&
 906                         !strncmp(cmd, "lri", 3)) {
 907                 intel_gvt_hypervisor_read_gpa(s->vgpu,
 908                         s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4);
 909                 /* check inhibit context */
 910                 if (ctx_sr_ctl & 1) {
 911                         u32 data = cmd_val(s, index + 1);
 912
 913                         if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset))
 914                                 intel_vgpu_mask_mmio_write(vgpu,
 915                                                         offset, &data, 4);
 916                         else
 917                                 vgpu_vreg(vgpu, offset) = data;
 918                 }
 919         }
 920
 921         /* TODO: Update the global mask if this MMIO is a masked-MMIO */
 922         intel_gvt_mmio_set_cmd_accessed(gvt, offset);
 923         return 0;
 924 }
 925
 926 #define cmd_reg(s, i) \
 927         (cmd_val(s, i) & GENMASK(22, 2))
 928
 929 #define cmd_reg_inhibit(s, i) \
 930         (cmd_val(s, i) & GENMASK(22, 18))
 931
 932 #define cmd_gma(s, i) \
 933         (cmd_val(s, i) & GENMASK(31, 2))
 934
 935 #define cmd_gma_hi(s, i) \
 936         (cmd_val(s, i) & GENMASK(15, 0))
 937
 938 static int cmd_handler_lri(struct parser_exec_state *s)
 939 {
 940         int i, ret = 0;
 941         int cmd_len = cmd_length(s);
 942         struct intel_gvt *gvt = s->vgpu->gvt;
 943
 944         for (i = 1; i < cmd_len; i += 2) {
 945                 if (IS_BROADWELL(gvt->dev_priv) && s->ring_id != RCS0) {
 946                         if (s->ring_id == BCS0 &&
 947                             cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR))
 948                                 ret |= 0;
 949                         else
 950                                 ret |= cmd_reg_inhibit(s, i) ? -EBADRQC : 0;
 951                 }
 952                 if (ret)
 953                         break;
 954                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
 955                 if (ret)
 956                         break;
 957         }
 958         return ret;
 959 }
 960
 961 static int cmd_handler_lrr(struct parser_exec_state *s)
 962 {
 963         int i, ret = 0;
 964         int cmd_len = cmd_length(s);
 965
 966         for (i = 1; i < cmd_len; i += 2) {
 967                 if (IS_BROADWELL(s->vgpu->gvt->dev_priv))
 968                         ret |= ((cmd_reg_inhibit(s, i) ||
 969                                         (cmd_reg_inhibit(s, i + 1)))) ?
 970                                 -EBADRQC : 0;
 971                 if (ret)
 972                         break;
 973                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
 974                 if (ret)
 975                         break;
 976                 ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
 977                 if (ret)
 978                         break;
 979         }
 980         return ret;
 981 }
 982
 983 static inline int cmd_address_audit(struct parser_exec_state *s,
 984                 unsigned long guest_gma, int op_size, bool index_mode);
 985
 986 static int cmd_handler_lrm(struct parser_exec_state *s)
 987 {
 988         struct intel_gvt *gvt = s->vgpu->gvt;
 989         int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
 990         unsigned long gma;
 991         int i, ret = 0;
 992         int cmd_len = cmd_length(s);
 993
 994         for (i = 1; i < cmd_len;) {
 995                 if (IS_BROADWELL(gvt->dev_priv))
 996                         ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;
 997                 if (ret)
 998                         break;
 999                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
1000                 if (ret)
1001                         break;
1002                 if (cmd_val(s, 0) & (1 << 22)) {
1003                         gma = cmd_gma(s, i + 1);
1004                         if (gmadr_bytes == 8)
1005                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1006                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1007                         if (ret)
1008                                 break;
1009                 }
1010                 i += gmadr_dw_number(s) + 1;
1011         }
1012         return ret;
1013 }
1014
1015 static int cmd_handler_srm(struct parser_exec_state *s)
1016 {
1017         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1018         unsigned long gma;
1019         int i, ret = 0;
1020         int cmd_len = cmd_length(s);
1021
1022         for (i = 1; i < cmd_len;) {
1023                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
1024                 if (ret)
1025                         break;
1026                 if (cmd_val(s, 0) & (1 << 22)) {
1027                         gma = cmd_gma(s, i + 1);
1028                         if (gmadr_bytes == 8)
1029                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1030                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1031                         if (ret)
1032                                 break;
1033                 }
1034                 i += gmadr_dw_number(s) + 1;
1035         }
1036         return ret;
1037 }
1038
1039 struct cmd_interrupt_event {
1040         int pipe_control_notify;
1041         int mi_flush_dw;
1042         int mi_user_interrupt;
1043 };
1044
1045 static struct cmd_interrupt_event cmd_interrupt_events[] = {
1046         [RCS0] = {
1047                 .pipe_control_notify = RCS_PIPE_CONTROL,
1048                 .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
1049                 .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
1050         },
1051         [BCS0] = {
1052                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1053                 .mi_flush_dw = BCS_MI_FLUSH_DW,
1054                 .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
1055         },
1056         [VCS0] = {
1057                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1058                 .mi_flush_dw = VCS_MI_FLUSH_DW,
1059                 .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
1060         },
1061         [VCS1] = {
1062                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1063                 .mi_flush_dw = VCS2_MI_FLUSH_DW,
1064                 .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1065         },
1066         [VECS0] = {
1067                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1068                 .mi_flush_dw = VECS_MI_FLUSH_DW,
1069                 .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1070         },
1071 };
1072
1073 static int cmd_handler_pipe_control(struct parser_exec_state *s)
1074 {
1075         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1076         unsigned long gma;
1077         bool index_mode = false;
1078         unsigned int post_sync;
1079         int ret = 0;
1080
1081         post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1082
1083         /* LRI post sync */
1084         if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1085                 ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1086         /* post sync */
1087         else if (post_sync) {
1088                 if (post_sync == 2)
1089                         ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1090                 else if (post_sync == 3)
1091                         ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1092                 else if (post_sync == 1) {
1093                         /* check ggtt*/
1094                         if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1095                                 gma = cmd_val(s, 2) & GENMASK(31, 3);
1096                                 if (gmadr_bytes == 8)
1097                                         gma |= (cmd_gma_hi(s, 3)) << 32;
1098                                 /* Store Data Index */
1099                                 if (cmd_val(s, 1) & (1 << 21))
1100                                         index_mode = true;
1101                                 ret |= cmd_address_audit(s, gma, sizeof(u64),
1102                                                 index_mode);
1103                         }
1104                 }
1105         }
1106
1107         if (ret)
1108                 return ret;
1109
1110         if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1111                 set_bit(cmd_interrupt_events[s->ring_id].pipe_control_notify,
1112                                 s->workload->pending_events);
1113         return 0;
1114 }
1115
1116 static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1117 {
1118         set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt,
1119                         s->workload->pending_events);
1120         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1121         return 0;
1122 }
1123
1124 static int cmd_advance_default(struct parser_exec_state *s)
1125 {
1126         return ip_gma_advance(s, cmd_length(s));
1127 }
1128
1129 static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1130 {
1131         int ret;
1132
1133         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1134                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1135                 ret = ip_gma_set(s, s->ret_ip_gma_bb);
1136                 s->buf_addr_type = s->saved_buf_addr_type;
1137         } else {
1138                 s->buf_type = RING_BUFFER_INSTRUCTION;
1139                 s->buf_addr_type = GTT_BUFFER;
1140                 if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1141                         s->ret_ip_gma_ring -= s->ring_size;
1142                 ret = ip_gma_set(s, s->ret_ip_gma_ring);
1143         }
1144         return ret;
1145 }
1146
1147 struct mi_display_flip_command_info {
1148         int pipe;
1149         int plane;
1150         int event;
1151         i915_reg_t stride_reg;
1152         i915_reg_t ctrl_reg;
1153         i915_reg_t surf_reg;
1154         u64 stride_val;
1155         u64 tile_val;
1156         u64 surf_val;
1157         bool async_flip;
1158 };
1159
1160 struct plane_code_mapping {
1161         int pipe;
1162         int plane;
1163         int event;
1164 };
1165
1166 static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1167                 struct mi_display_flip_command_info *info)
1168 {
1169         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1170         struct plane_code_mapping gen8_plane_code[] = {
1171                 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1172                 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1173                 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1174                 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1175                 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1176                 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1177         };
1178         u32 dword0, dword1, dword2;
1179         u32 v;
1180
1181         dword0 = cmd_val(s, 0);
1182         dword1 = cmd_val(s, 1);
1183         dword2 = cmd_val(s, 2);
1184
1185         v = (dword0 & GENMASK(21, 19)) >> 19;
1186         if (WARN_ON(v >= ARRAY_SIZE(gen8_plane_code)))
1187                 return -EBADRQC;
1188
1189         info->pipe = gen8_plane_code[v].pipe;
1190         info->plane = gen8_plane_code[v].plane;
1191         info->event = gen8_plane_code[v].event;
1192         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1193         info->tile_val = (dword1 & 0x1);
1194         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1195         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1196
1197         if (info->plane == PLANE_A) {
1198                 info->ctrl_reg = DSPCNTR(info->pipe);
1199                 info->stride_reg = DSPSTRIDE(info->pipe);
1200                 info->surf_reg = DSPSURF(info->pipe);
1201         } else if (info->plane == PLANE_B) {
1202                 info->ctrl_reg = SPRCTL(info->pipe);
1203                 info->stride_reg = SPRSTRIDE(info->pipe);
1204                 info->surf_reg = SPRSURF(info->pipe);
1205         } else {
1206                 WARN_ON(1);
1207                 return -EBADRQC;
1208         }
1209         return 0;
1210 }
1211
1212 static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1213                 struct mi_display_flip_command_info *info)
1214 {
1215         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1216         struct intel_vgpu *vgpu = s->vgpu;
1217         u32 dword0 = cmd_val(s, 0);
1218         u32 dword1 = cmd_val(s, 1);
1219         u32 dword2 = cmd_val(s, 2);
1220         u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1221
1222         info->plane = PRIMARY_PLANE;
1223
1224         switch (plane) {
1225         case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1226                 info->pipe = PIPE_A;
1227                 info->event = PRIMARY_A_FLIP_DONE;
1228                 break;
1229         case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1230                 info->pipe = PIPE_B;
1231                 info->event = PRIMARY_B_FLIP_DONE;
1232                 break;
1233         case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1234                 info->pipe = PIPE_C;
1235                 info->event = PRIMARY_C_FLIP_DONE;
1236                 break;
1237
1238         case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1239                 info->pipe = PIPE_A;
1240                 info->event = SPRITE_A_FLIP_DONE;
1241                 info->plane = SPRITE_PLANE;
1242                 break;
1243         case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1244                 info->pipe = PIPE_B;
1245                 info->event = SPRITE_B_FLIP_DONE;
1246                 info->plane = SPRITE_PLANE;
1247                 break;
1248         case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1249                 info->pipe = PIPE_C;
1250                 info->event = SPRITE_C_FLIP_DONE;
1251                 info->plane = SPRITE_PLANE;
1252                 break;
1253
1254         default:
1255                 gvt_vgpu_err("unknown plane code %d\n", plane);
1256                 return -EBADRQC;
1257         }
1258
1259         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1260         info->tile_val = (dword1 & GENMASK(2, 0));
1261         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1262         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1263
1264         info->ctrl_reg = DSPCNTR(info->pipe);
1265         info->stride_reg = DSPSTRIDE(info->pipe);
1266         info->surf_reg = DSPSURF(info->pipe);
1267
1268         return 0;
1269 }
1270
1271 static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1272                 struct mi_display_flip_command_info *info)
1273 {
1274         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1275         u32 stride, tile;
1276
1277         if (!info->async_flip)
1278                 return 0;
1279
1280         if (INTEL_GEN(dev_priv) >= 9) {
1281                 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1282                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1283                                 GENMASK(12, 10)) >> 10;
1284         } else {
1285                 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1286                                 GENMASK(15, 6)) >> 6;
1287                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1288         }
1289
1290         if (stride != info->stride_val)
1291                 gvt_dbg_cmd("cannot change stride during async flip\n");
1292
1293         if (tile != info->tile_val)
1294                 gvt_dbg_cmd("cannot change tile during async flip\n");
1295
1296         return 0;
1297 }
1298
1299 static int gen8_update_plane_mmio_from_mi_display_flip(
1300                 struct parser_exec_state *s,
1301                 struct mi_display_flip_command_info *info)
1302 {
1303         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1304         struct intel_vgpu *vgpu = s->vgpu;
1305
1306         set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1307                       info->surf_val << 12);
1308         if (INTEL_GEN(dev_priv) >= 9) {
1309                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1310                               info->stride_val);
1311                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1312                               info->tile_val << 10);
1313         } else {
1314                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1315                               info->stride_val << 6);
1316                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1317                               info->tile_val << 10);
1318         }
1319
1320         vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;
1321         intel_vgpu_trigger_virtual_event(vgpu, info->event);
1322         return 0;
1323 }
1324
1325 static int decode_mi_display_flip(struct parser_exec_state *s,
1326                 struct mi_display_flip_command_info *info)
1327 {
1328         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1329
1330         if (IS_BROADWELL(dev_priv))
1331                 return gen8_decode_mi_display_flip(s, info);
1332         if (INTEL_GEN(dev_priv) >= 9)
1333                 return skl_decode_mi_display_flip(s, info);
1334
1335         return -ENODEV;
1336 }
1337
1338 static int check_mi_display_flip(struct parser_exec_state *s,
1339                 struct mi_display_flip_command_info *info)
1340 {
1341         return gen8_check_mi_display_flip(s, info);
1342 }
1343
1344 static int update_plane_mmio_from_mi_display_flip(
1345                 struct parser_exec_state *s,
1346                 struct mi_display_flip_command_info *info)
1347 {
1348         return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1349 }
1350
1351 static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1352 {
1353         struct mi_display_flip_command_info info;
1354         struct intel_vgpu *vgpu = s->vgpu;
1355         int ret;
1356         int i;
1357         int len = cmd_length(s);
1358
1359         ret = decode_mi_display_flip(s, &info);
1360         if (ret) {
1361                 gvt_vgpu_err("fail to decode MI display flip command\n");
1362                 return ret;
1363         }
1364
1365         ret = check_mi_display_flip(s, &info);
1366         if (ret) {
1367                 gvt_vgpu_err("invalid MI display flip command\n");
1368                 return ret;
1369         }
1370
1371         ret = update_plane_mmio_from_mi_display_flip(s, &info);
1372         if (ret) {
1373                 gvt_vgpu_err("fail to update plane mmio\n");
1374                 return ret;
1375         }
1376
1377         for (i = 0; i < len; i++)
1378                 patch_value(s, cmd_ptr(s, i), MI_NOOP);
1379         return 0;
1380 }
1381
1382 static bool is_wait_for_flip_pending(u32 cmd)
1383 {
1384         return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1385                         MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1386                         MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1387                         MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1388                         MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1389                         MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1390 }
1391
1392 static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1393 {
1394         u32 cmd = cmd_val(s, 0);
1395
1396         if (!is_wait_for_flip_pending(cmd))
1397                 return 0;
1398
1399         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1400         return 0;
1401 }
1402
1403 static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1404 {
1405         unsigned long addr;
1406         unsigned long gma_high, gma_low;
1407         struct intel_vgpu *vgpu = s->vgpu;
1408         int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1409
1410         if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) {
1411                 gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
1412                 return INTEL_GVT_INVALID_ADDR;
1413         }
1414
1415         gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1416         if (gmadr_bytes == 4) {
1417                 addr = gma_low;
1418         } else {
1419                 gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1420                 addr = (((unsigned long)gma_high) << 32) | gma_low;
1421         }
1422         return addr;
1423 }
1424
1425 static inline int cmd_address_audit(struct parser_exec_state *s,
1426                 unsigned long guest_gma, int op_size, bool index_mode)
1427 {
1428         struct intel_vgpu *vgpu = s->vgpu;
1429         u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1430         int i;
1431         int ret;
1432
1433         if (op_size > max_surface_size) {
1434                 gvt_vgpu_err("command address audit fail name %s\n",
1435                         s->info->name);
1436                 return -EFAULT;
1437         }
1438
1439         if (index_mode) {
1440                 if (guest_gma >= I915_GTT_PAGE_SIZE / sizeof(u64)) {
1441                         ret = -EFAULT;
1442                         goto err;
1443                 }
1444         } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1445                 ret = -EFAULT;
1446                 goto err;
1447         }
1448
1449         return 0;
1450
1451 err:
1452         gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1453                         s->info->name, guest_gma, op_size);
1454
1455         pr_err("cmd dump: ");
1456         for (i = 0; i < cmd_length(s); i++) {
1457                 if (!(i % 4))
1458                         pr_err("\n%08x ", cmd_val(s, i));
1459                 else
1460                         pr_err("%08x ", cmd_val(s, i));
1461         }
1462         pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1463                         vgpu->id,
1464                         vgpu_aperture_gmadr_base(vgpu),
1465                         vgpu_aperture_gmadr_end(vgpu),
1466                         vgpu_hidden_gmadr_base(vgpu),
1467                         vgpu_hidden_gmadr_end(vgpu));
1468         return ret;
1469 }
1470
1471 static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1472 {
1473         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1474         int op_size = (cmd_length(s) - 3) * sizeof(u32);
1475         int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1476         unsigned long gma, gma_low, gma_high;
1477         int ret = 0;
1478
1479         /* check ppggt */
1480         if (!(cmd_val(s, 0) & (1 << 22)))
1481                 return 0;
1482
1483         gma = cmd_val(s, 2) & GENMASK(31, 2);
1484
1485         if (gmadr_bytes == 8) {
1486                 gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1487                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1488                 gma = (gma_high << 32) | gma_low;
1489                 core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1490         }
1491         ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1492         return ret;
1493 }
1494
1495 static inline int unexpected_cmd(struct parser_exec_state *s)
1496 {
1497         struct intel_vgpu *vgpu = s->vgpu;
1498
1499         gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1500
1501         return -EBADRQC;
1502 }
1503
1504 static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1505 {
1506         return unexpected_cmd(s);
1507 }
1508
1509 static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1510 {
1511         return unexpected_cmd(s);
1512 }
1513
1514 static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1515 {
1516         return unexpected_cmd(s);
1517 }
1518
1519 static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1520 {
1521         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1522         int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1523                         sizeof(u32);
1524         unsigned long gma, gma_high;
1525         int ret = 0;
1526
1527         if (!(cmd_val(s, 0) & (1 << 22)))
1528                 return ret;
1529
1530         gma = cmd_val(s, 1) & GENMASK(31, 2);
1531         if (gmadr_bytes == 8) {
1532                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1533                 gma = (gma_high << 32) | gma;
1534         }
1535         ret = cmd_address_audit(s, gma, op_size, false);
1536         return ret;
1537 }
1538
1539 static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1540 {
1541         return unexpected_cmd(s);
1542 }
1543
1544 static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1545 {
1546         return unexpected_cmd(s);
1547 }
1548
1549 static int cmd_handler_mi_conditional_batch_buffer_end(
1550                 struct parser_exec_state *s)
1551 {
1552         return unexpected_cmd(s);
1553 }
1554
1555 static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1556 {
1557         return unexpected_cmd(s);
1558 }
1559
1560 static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1561 {
1562         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1563         unsigned long gma;
1564         bool index_mode = false;
1565         int ret = 0;
1566
1567         /* Check post-sync and ppgtt bit */
1568         if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1569                 gma = cmd_val(s, 1) & GENMASK(31, 3);
1570                 if (gmadr_bytes == 8)
1571                         gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1572                 /* Store Data Index */
1573                 if (cmd_val(s, 0) & (1 << 21))
1574                         index_mode = true;
1575                 ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1576         }
1577         /* Check notify bit */
1578         if ((cmd_val(s, 0) & (1 << 8)))
1579                 set_bit(cmd_interrupt_events[s->ring_id].mi_flush_dw,
1580                                 s->workload->pending_events);
1581         return ret;
1582 }
1583
1584 static void addr_type_update_snb(struct parser_exec_state *s)
1585 {
1586         if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1587                         (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1588                 s->buf_addr_type = PPGTT_BUFFER;
1589         }
1590 }
1591
1592
1593 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1594                 unsigned long gma, unsigned long end_gma, void *va)
1595 {
1596         unsigned long copy_len, offset;
1597         unsigned long len = 0;
1598         unsigned long gpa;
1599
1600         while (gma != end_gma) {
1601                 gpa = intel_vgpu_gma_to_gpa(mm, gma);
1602                 if (gpa == INTEL_GVT_INVALID_ADDR) {
1603                         gvt_vgpu_err("invalid gma address: %lx\n", gma);
1604                         return -EFAULT;
1605                 }
1606
1607                 offset = gma & (I915_GTT_PAGE_SIZE - 1);
1608
1609                 copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
1610                         I915_GTT_PAGE_SIZE - offset : end_gma - gma;
1611
1612                 intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len);
1613
1614                 len += copy_len;
1615                 gma += copy_len;
1616         }
1617         return len;
1618 }
1619
1620
1621 /*
1622  * Check whether a batch buffer needs to be scanned. Currently
1623  * the only criteria is based on privilege.
1624  */
1625 static int batch_buffer_needs_scan(struct parser_exec_state *s)
1626 {
1627         /* Decide privilege based on address space */
1628         if (cmd_val(s, 0) & (1 << 8) &&
1629                         !(s->vgpu->scan_nonprivbb & (1 << s->ring_id)))
1630                 return 0;
1631         return 1;
1632 }
1633
1634 static int find_bb_size(struct parser_exec_state *s, unsigned long *bb_size)
1635 {
1636         unsigned long gma = 0;
1637         const struct cmd_info *info;
1638         u32 cmd_len = 0;
1639         bool bb_end = false;
1640         struct intel_vgpu *vgpu = s->vgpu;
1641         u32 cmd;
1642         struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1643                 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1644
1645         *bb_size = 0;
1646
1647         /* get the start gm address of the batch buffer */
1648         gma = get_gma_bb_from_cmd(s, 1);
1649         if (gma == INTEL_GVT_INVALID_ADDR)
1650                 return -EFAULT;
1651
1652         cmd = cmd_val(s, 0);
1653         info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1654         if (info == NULL) {
1655                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
1656                                 cmd, get_opcode(cmd, s->ring_id),
1657                                 (s->buf_addr_type == PPGTT_BUFFER) ?
1658                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
1659                 return -EBADRQC;
1660         }
1661         do {
1662                 if (copy_gma_to_hva(s->vgpu, mm,
1663                                 gma, gma + 4, &cmd) < 0)
1664                         return -EFAULT;
1665                 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1666                 if (info == NULL) {
1667                         gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
1668                                 cmd, get_opcode(cmd, s->ring_id),
1669                                 (s->buf_addr_type == PPGTT_BUFFER) ?
1670                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
1671                         return -EBADRQC;
1672                 }
1673
1674                 if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1675                         bb_end = true;
1676                 } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1677                         if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)
1678                                 /* chained batch buffer */
1679                                 bb_end = true;
1680                 }
1681                 cmd_len = get_cmd_length(info, cmd) << 2;
1682                 *bb_size += cmd_len;
1683                 gma += cmd_len;
1684         } while (!bb_end);
1685
1686         return 0;
1687 }
1688
1689 static int perform_bb_shadow(struct parser_exec_state *s)
1690 {
1691         struct intel_vgpu *vgpu = s->vgpu;
1692         struct intel_vgpu_shadow_bb *bb;
1693         unsigned long gma = 0;
1694         unsigned long bb_size;
1695         int ret = 0;
1696         struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1697                 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1698         unsigned long gma_start_offset = 0;
1699
1700         /* get the start gm address of the batch buffer */
1701         gma = get_gma_bb_from_cmd(s, 1);
1702         if (gma == INTEL_GVT_INVALID_ADDR)
1703                 return -EFAULT;
1704
1705         ret = find_bb_size(s, &bb_size);
1706         if (ret)
1707                 return ret;
1708
1709         bb = kzalloc(sizeof(*bb), GFP_KERNEL);
1710         if (!bb)
1711                 return -ENOMEM;
1712
1713         bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true;
1714
1715         /* the gma_start_offset stores the batch buffer's start gma's
1716          * offset relative to page boundary. so for non-privileged batch
1717          * buffer, the shadowed gem object holds exactly the same page
1718          * layout as original gem object. This is for the convience of
1719          * replacing the whole non-privilged batch buffer page to this
1720          * shadowed one in PPGTT at the same gma address. (this replacing
1721          * action is not implemented yet now, but may be necessary in
1722          * future).
1723          * for prileged batch buffer, we just change start gma address to
1724          * that of shadowed page.
1725          */
1726         if (bb->ppgtt)
1727                 gma_start_offset = gma & ~I915_GTT_PAGE_MASK;
1728
1729         bb->obj = i915_gem_object_create(s->vgpu->gvt->dev_priv,
1730                          roundup(bb_size + gma_start_offset, PAGE_SIZE));
1731         if (IS_ERR(bb->obj)) {
1732                 ret = PTR_ERR(bb->obj);
1733                 goto err_free_bb;
1734         }
1735
1736         ret = i915_gem_obj_prepare_shmem_write(bb->obj, &bb->clflush);
1737         if (ret)
1738                 goto err_free_obj;
1739
1740         bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
1741         if (IS_ERR(bb->va)) {
1742                 ret = PTR_ERR(bb->va);
1743                 goto err_finish_shmem_access;
1744         }
1745
1746         if (bb->clflush & CLFLUSH_BEFORE) {
1747                 drm_clflush_virt_range(bb->va, bb->obj->base.size);
1748                 bb->clflush &= ~CLFLUSH_BEFORE;
1749         }
1750
1751         ret = copy_gma_to_hva(s->vgpu, mm,
1752                               gma, gma + bb_size,
1753                               bb->va + gma_start_offset);
1754         if (ret < 0) {
1755                 gvt_vgpu_err("fail to copy guest ring buffer\n");
1756                 ret = -EFAULT;
1757                 goto err_unmap;
1758         }
1759
1760         INIT_LIST_HEAD(&bb->list);
1761         list_add(&bb->list, &s->workload->shadow_bb);
1762
1763         bb->accessing = true;
1764         bb->bb_start_cmd_va = s->ip_va;
1765
1766         if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1767                 bb->bb_offset = s->ip_va - s->rb_va;
1768         else
1769                 bb->bb_offset = 0;
1770
1771         /*
1772          * ip_va saves the virtual address of the shadow batch buffer, while
1773          * ip_gma saves the graphics address of the original batch buffer.
1774          * As the shadow batch buffer is just a copy from the originial one,
1775          * it should be right to use shadow batch buffer'va and original batch
1776          * buffer's gma in pair. After all, we don't want to pin the shadow
1777          * buffer here (too early).
1778          */
1779         s->ip_va = bb->va + gma_start_offset;
1780         s->ip_gma = gma;
1781         return 0;
1782 err_unmap:
1783         i915_gem_object_unpin_map(bb->obj);
1784 err_finish_shmem_access:
1785         i915_gem_obj_finish_shmem_access(bb->obj);
1786 err_free_obj:
1787         i915_gem_object_put(bb->obj);
1788 err_free_bb:
1789         kfree(bb);
1790         return ret;
1791 }
1792
1793 static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1794 {
1795         bool second_level;
1796         int ret = 0;
1797         struct intel_vgpu *vgpu = s->vgpu;
1798
1799         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1800                 gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
1801                 return -EFAULT;
1802         }
1803
1804         second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
1805         if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
1806                 gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
1807                 return -EFAULT;
1808         }
1809
1810         s->saved_buf_addr_type = s->buf_addr_type;
1811         addr_type_update_snb(s);
1812         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
1813                 s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
1814                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1815         } else if (second_level) {
1816                 s->buf_type = BATCH_BUFFER_2ND_LEVEL;
1817                 s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
1818                 s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
1819         }
1820
1821         if (batch_buffer_needs_scan(s)) {
1822                 ret = perform_bb_shadow(s);
1823                 if (ret < 0)
1824                         gvt_vgpu_err("invalid shadow batch buffer\n");
1825         } else {
1826                 /* emulate a batch buffer end to do return right */
1827                 ret = cmd_handler_mi_batch_buffer_end(s);
1828                 if (ret < 0)
1829                         return ret;
1830         }
1831         return ret;
1832 }
1833
1834 static int mi_noop_index;
1835
1836 static const struct cmd_info cmd_info[] = {
1837         {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1838
1839         {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
1840                 0, 1, NULL},
1841
1842         {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
1843                 0, 1, cmd_handler_mi_user_interrupt},
1844
1845         {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
1846                 D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
1847
1848         {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1849
1850         {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1851                 NULL},
1852
1853         {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1854                 NULL},
1855
1856         {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1857                 NULL},
1858
1859         {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1860                 NULL},
1861
1862         {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
1863                 D_ALL, 0, 1, NULL},
1864
1865         {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
1866                 F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1867                 cmd_handler_mi_batch_buffer_end},
1868
1869         {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
1870                 0, 1, NULL},
1871
1872         {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1873                 NULL},
1874
1875         {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
1876                 D_ALL, 0, 1, NULL},
1877
1878         {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1879                 NULL},
1880
1881         {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1882                 NULL},
1883
1884         {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR | F_POST_HANDLE,
1885                 R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
1886
1887         {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR, R_ALL, D_ALL,
1888                 0, 8, NULL},
1889
1890         {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
1891
1892         {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1893
1894         {"MI_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL, F_LEN_VAR, R_ALL,
1895                 D_BDW_PLUS, 0, 8, NULL},
1896
1897         {"MI_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT, F_LEN_VAR, R_ALL,
1898                 D_BDW_PLUS, ADDR_FIX_1(2), 8, cmd_handler_mi_semaphore_wait},
1899
1900         {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1901                 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
1902
1903         {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
1904                 0, 8, cmd_handler_mi_store_data_index},
1905
1906         {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
1907                 D_ALL, 0, 8, cmd_handler_lri},
1908
1909         {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
1910                 cmd_handler_mi_update_gtt},
1911
1912         {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM, F_LEN_VAR, R_ALL,
1913                 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_srm},
1914
1915         {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
1916                 cmd_handler_mi_flush_dw},
1917
1918         {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
1919                 10, cmd_handler_mi_clflush},
1920
1921         {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT, F_LEN_VAR, R_ALL,
1922                 D_ALL, ADDR_FIX_1(1), 6, cmd_handler_mi_report_perf_count},
1923
1924         {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM, F_LEN_VAR, R_ALL,
1925                 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_lrm},
1926
1927         {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG, F_LEN_VAR, R_ALL,
1928                 D_ALL, 0, 8, cmd_handler_lrr},
1929
1930         {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM, F_LEN_VAR, R_RCS,
1931                 D_ALL, 0, 8, NULL},
1932
1933         {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR, R_RCS, D_ALL,
1934                 ADDR_FIX_1(2), 8, NULL},
1935
1936         {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
1937                 ADDR_FIX_1(2), 8, NULL},
1938
1939         {"MI_OP_2E", OP_MI_2E, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_2(1, 2),
1940                 8, cmd_handler_mi_op_2e},
1941
1942         {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
1943                 8, cmd_handler_mi_op_2f},
1944
1945         {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
1946                 F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
1947                 cmd_handler_mi_batch_buffer_start},
1948
1949         {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
1950                 F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
1951                 cmd_handler_mi_conditional_batch_buffer_end},
1952
1953         {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
1954                 R_RCS | R_BCS, D_ALL, 0, 2, NULL},
1955
1956         {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1957                 ADDR_FIX_2(4, 7), 8, NULL},
1958
1959         {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1960                 0, 8, NULL},
1961
1962         {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
1963                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1964
1965         {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1966
1967         {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
1968                 0, 8, NULL},
1969
1970         {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1971                 ADDR_FIX_1(3), 8, NULL},
1972
1973         {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
1974                 D_ALL, 0, 8, NULL},
1975
1976         {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
1977                 ADDR_FIX_1(4), 8, NULL},
1978
1979         {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1980                 ADDR_FIX_2(4, 5), 8, NULL},
1981
1982         {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1983                 ADDR_FIX_1(4), 8, NULL},
1984
1985         {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
1986                 ADDR_FIX_2(4, 7), 8, NULL},
1987
1988         {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
1989                 D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1990
1991         {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1992
1993         {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
1994                 D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
1995
1996         {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
1997                 R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1998
1999         {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
2000                 OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
2001                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2002
2003         {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
2004                 D_ALL, ADDR_FIX_1(4), 8, NULL},
2005
2006         {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
2007                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2008
2009         {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
2010                 D_ALL, ADDR_FIX_1(4), 8, NULL},
2011
2012         {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
2013                 D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2014
2015         {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
2016                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2017
2018         {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
2019                 OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
2020                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2021
2022         {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
2023                 ADDR_FIX_2(4, 5), 8, NULL},
2024
2025         {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
2026                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2027
2028         {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
2029                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
2030                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2031
2032         {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
2033                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
2034                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2035
2036         {"3DSTATE_BLEND_STATE_POINTERS",
2037                 OP_3DSTATE_BLEND_STATE_POINTERS,
2038                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2039
2040         {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
2041                 OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
2042                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2043
2044         {"3DSTATE_BINDING_TABLE_POINTERS_VS",
2045                 OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
2046                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2047
2048         {"3DSTATE_BINDING_TABLE_POINTERS_HS",
2049                 OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
2050                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2051
2052         {"3DSTATE_BINDING_TABLE_POINTERS_DS",
2053                 OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
2054                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2055
2056         {"3DSTATE_BINDING_TABLE_POINTERS_GS",
2057                 OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
2058                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2059
2060         {"3DSTATE_BINDING_TABLE_POINTERS_PS",
2061                 OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
2062                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2063
2064         {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
2065                 OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
2066                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2067
2068         {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
2069                 OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
2070                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2071
2072         {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
2073                 OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
2074                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2075
2076         {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
2077                 OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
2078                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2079
2080         {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
2081                 OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
2082                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2083
2084         {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
2085                 0, 8, NULL},
2086
2087         {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2088                 0, 8, NULL},
2089
2090         {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2091                 0, 8, NULL},
2092
2093         {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2094                 0, 8, NULL},
2095
2096         {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2097                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2098
2099         {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2100                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2101
2102         {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2103                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2104
2105         {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2106                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2107
2108         {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2109                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2110
2111         {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2112                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2113
2114         {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2115                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2116
2117         {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2118                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2119
2120         {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2121                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2122
2123         {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2124                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2125
2126         {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2127                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2128
2129         {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2130                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2131
2132         {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2133                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2134
2135         {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2136                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2137
2138         {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2139                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2140
2141         {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2142                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2143
2144         {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2145                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2146
2147         {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2148                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2149
2150         {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2151                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2152
2153         {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2154                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2155
2156         {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2157                 D_BDW_PLUS, 0, 8, NULL},
2158
2159         {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2160                 NULL},
2161
2162         {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2163                 D_BDW_PLUS, 0, 8, NULL},
2164
2165         {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2166                 D_BDW_PLUS, 0, 8, NULL},
2167
2168         {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2169                 8, NULL},
2170
2171         {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2172                 R_RCS, D_BDW_PLUS, 0, 8, NULL},
2173
2174         {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2175                 8, NULL},
2176
2177         {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2178                 NULL},
2179
2180         {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2181                 NULL},
2182
2183         {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2184                 NULL},
2185
2186         {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2187                 D_BDW_PLUS, 0, 8, NULL},
2188
2189         {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2190                 R_RCS, D_ALL, 0, 8, NULL},
2191
2192         {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2193                 D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2194
2195         {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2196                 R_RCS, D_ALL, 0, 1, NULL},
2197
2198         {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2199
2200         {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2201                 R_RCS, D_ALL, 0, 8, NULL},
2202
2203         {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2204                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2205
2206         {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2207
2208         {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2209
2210         {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2211
2212         {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2213                 D_BDW_PLUS, 0, 8, NULL},
2214
2215         {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2216                 D_BDW_PLUS, 0, 8, NULL},
2217
2218         {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2219                 D_ALL, 0, 8, NULL},
2220
2221         {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2222                 D_BDW_PLUS, 0, 8, NULL},
2223
2224         {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2225                 D_BDW_PLUS, 0, 8, NULL},
2226
2227         {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2228
2229         {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2230
2231         {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2232
2233         {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2234                 D_ALL, 0, 8, NULL},
2235
2236         {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2237
2238         {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2239
2240         {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2241                 R_RCS, D_ALL, 0, 8, NULL},
2242
2243         {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2244                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2245
2246         {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2247                 0, 8, NULL},
2248
2249         {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2250                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2251
2252         {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2253                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2254
2255         {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2256                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2257
2258         {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2259                 D_ALL, 0, 8, NULL},
2260
2261         {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2262                 D_ALL, 0, 8, NULL},
2263
2264         {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2265                 D_ALL, 0, 8, NULL},
2266
2267         {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2268                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2269
2270         {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2271                 D_BDW_PLUS, 0, 8, NULL},
2272
2273         {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2274                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2275
2276         {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2277                 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2278
2279         {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2280                 R_RCS, D_ALL, 0, 8, NULL},
2281
2282         {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2283                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2284
2285         {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2286                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2287
2288         {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2289                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2290
2291         {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2292                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2293
2294         {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2295                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2296
2297         {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2298                 R_RCS, D_ALL, 0, 8, NULL},
2299
2300         {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2301                 D_ALL, 0, 9, NULL},
2302
2303         {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2304                 ADDR_FIX_2(2, 4), 8, NULL},
2305
2306         {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2307                 OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2308                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2309
2310         {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2311                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2312
2313         {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2314                 OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2315                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2316
2317         {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2318                 D_BDW_PLUS, 0, 8, NULL},
2319
2320         {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2321                 ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2322
2323         {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2324
2325         {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2326                 1, NULL},
2327
2328         {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2329                 ADDR_FIX_1(1), 8, NULL},
2330
2331         {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2332
2333         {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2334                 ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2335
2336         {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2337                 ADDR_FIX_1(1), 8, NULL},
2338
2339         {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2340
2341         {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2342
2343         {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2344                 0, 8, NULL},
2345
2346         {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2347                 D_SKL_PLUS, 0, 8, NULL},
2348
2349         {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2350                 F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2351
2352         {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2353                 0, 16, NULL},
2354
2355         {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2356                 0, 16, NULL},
2357
2358         {"MEDIA_POOL_STATE", OP_MEDIA_POOL_STATE, F_LEN_VAR, R_RCS, D_ALL,
2359                 0, 16, NULL},
2360
2361         {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2362
2363         {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2364                 0, 16, NULL},
2365
2366         {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2367                 0, 16, NULL},
2368
2369         {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2370                 0, 16, NULL},
2371
2372         {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2373                 0, 8, NULL},
2374
2375         {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2376                 NULL},
2377
2378         {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2379                 F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2380
2381         {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2382                 R_VCS, D_ALL, 0, 12, NULL},
2383
2384         {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2385                 R_VCS, D_ALL, 0, 12, NULL},
2386
2387         {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2388                 R_VCS, D_BDW_PLUS, 0, 12, NULL},
2389
2390         {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2391                 F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2392
2393         {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2394                 F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2395
2396         {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2397
2398         {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2399                 R_VCS, D_ALL, 0, 12, NULL},
2400
2401         {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2402                 R_VCS, D_ALL, 0, 12, NULL},
2403
2404         {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2405                 R_VCS, D_ALL, 0, 12, NULL},
2406
2407         {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2408                 R_VCS, D_ALL, 0, 12, NULL},
2409
2410         {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2411                 R_VCS, D_ALL, 0, 12, NULL},
2412
2413         {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2414                 R_VCS, D_ALL, 0, 12, NULL},
2415
2416         {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2417                 R_VCS, D_ALL, 0, 6, NULL},
2418
2419         {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2420                 R_VCS, D_ALL, 0, 12, NULL},
2421
2422         {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2423                 R_VCS, D_ALL, 0, 12, NULL},
2424
2425         {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2426                 R_VCS, D_ALL, 0, 12, NULL},
2427
2428         {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2429                 R_VCS, D_ALL, 0, 12, NULL},
2430
2431         {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2432                 R_VCS, D_ALL, 0, 12, NULL},
2433
2434         {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2435                 R_VCS, D_ALL, 0, 12, NULL},
2436
2437         {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2438                 R_VCS, D_ALL, 0, 12, NULL},
2439         {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2440                 R_VCS, D_ALL, 0, 12, NULL},
2441
2442         {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2443                 R_VCS, D_ALL, 0, 12, NULL},
2444
2445         {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2446                 R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2447
2448         {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2449                 R_VCS, D_ALL, 0, 12, NULL},
2450
2451         {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2452                 R_VCS, D_ALL, 0, 12, NULL},
2453
2454         {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2455                 R_VCS, D_ALL, 0, 12, NULL},
2456
2457         {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2458                 R_VCS, D_ALL, 0, 12, NULL},
2459
2460         {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2461                 R_VCS, D_ALL, 0, 12, NULL},
2462
2463         {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2464                 R_VCS, D_ALL, 0, 12, NULL},
2465
2466         {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2467                 R_VCS, D_ALL, 0, 12, NULL},
2468
2469         {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2470                 R_VCS, D_ALL, 0, 12, NULL},
2471
2472         {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2473                 R_VCS, D_ALL, 0, 12, NULL},
2474
2475         {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2476                 R_VCS, D_ALL, 0, 12, NULL},
2477
2478         {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2479                 R_VCS, D_ALL, 0, 12, NULL},
2480
2481         {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2482                 0, 16, NULL},
2483
2484         {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2485
2486         {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2487
2488         {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2489                 R_VCS, D_ALL, 0, 12, NULL},
2490
2491         {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2492                 R_VCS, D_ALL, 0, 12, NULL},
2493
2494         {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2495                 R_VCS, D_ALL, 0, 12, NULL},
2496
2497         {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2498
2499         {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2500                 0, 12, NULL},
2501
2502         {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2503                 0, 20, NULL},
2504 };
2505
2506 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2507 {
2508         hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2509 }
2510
2511 /* call the cmd handler, and advance ip */
2512 static int cmd_parser_exec(struct parser_exec_state *s)
2513 {
2514         struct intel_vgpu *vgpu = s->vgpu;
2515         const struct cmd_info *info;
2516         u32 cmd;
2517         int ret = 0;
2518
2519         cmd = cmd_val(s, 0);
2520
2521         /* fastpath for MI_NOOP */
2522         if (cmd == MI_NOOP)
2523                 info = &cmd_info[mi_noop_index];
2524         else
2525                 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
2526
2527         if (info == NULL) {
2528                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
2529                                 cmd, get_opcode(cmd, s->ring_id),
2530                                 (s->buf_addr_type == PPGTT_BUFFER) ?
2531                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
2532                 return -EBADRQC;
2533         }
2534
2535         s->info = info;
2536
2537         trace_gvt_command(vgpu->id, s->ring_id, s->ip_gma, s->ip_va,
2538                           cmd_length(s), s->buf_type, s->buf_addr_type,
2539                           s->workload, info->name);
2540
2541         if (info->handler) {
2542                 ret = info->handler(s);
2543                 if (ret < 0) {
2544                         gvt_vgpu_err("%s handler error\n", info->name);
2545                         return ret;
2546                 }
2547         }
2548
2549         if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2550                 ret = cmd_advance_default(s);
2551                 if (ret) {
2552                         gvt_vgpu_err("%s IP advance error\n", info->name);
2553                         return ret;
2554                 }
2555         }
2556         return 0;
2557 }
2558
2559 static inline bool gma_out_of_range(unsigned long gma,
2560                 unsigned long gma_head, unsigned int gma_tail)
2561 {
2562         if (gma_tail >= gma_head)
2563                 return (gma < gma_head) || (gma > gma_tail);
2564         else
2565                 return (gma > gma_tail) && (gma < gma_head);
2566 }
2567
2568 /* Keep the consistent return type, e.g EBADRQC for unknown
2569  * cmd, EFAULT for invalid address, EPERM for nonpriv. later
2570  * works as the input of VM healthy status.
2571  */
2572 static int command_scan(struct parser_exec_state *s,
2573                 unsigned long rb_head, unsigned long rb_tail,
2574                 unsigned long rb_start, unsigned long rb_len)
2575 {
2576
2577         unsigned long gma_head, gma_tail, gma_bottom;
2578         int ret = 0;
2579         struct intel_vgpu *vgpu = s->vgpu;
2580
2581         gma_head = rb_start + rb_head;
2582         gma_tail = rb_start + rb_tail;
2583         gma_bottom = rb_start +  rb_len;
2584
2585         while (s->ip_gma != gma_tail) {
2586                 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2587                         if (!(s->ip_gma >= rb_start) ||
2588                                 !(s->ip_gma < gma_bottom)) {
2589                                 gvt_vgpu_err("ip_gma %lx out of ring scope."
2590                                         "(base:0x%lx, bottom: 0x%lx)\n",
2591                                         s->ip_gma, rb_start,
2592                                         gma_bottom);
2593                                 parser_exec_state_dump(s);
2594                                 return -EFAULT;
2595                         }
2596                         if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2597                                 gvt_vgpu_err("ip_gma %lx out of range."
2598                                         "base 0x%lx head 0x%lx tail 0x%lx\n",
2599                                         s->ip_gma, rb_start,
2600                                         rb_head, rb_tail);
2601                                 parser_exec_state_dump(s);
2602                                 break;
2603                         }
2604                 }
2605                 ret = cmd_parser_exec(s);
2606                 if (ret) {
2607                         gvt_vgpu_err("cmd parser error\n");
2608                         parser_exec_state_dump(s);
2609                         break;
2610                 }
2611         }
2612
2613         return ret;
2614 }
2615
2616 static int scan_workload(struct intel_vgpu_workload *workload)
2617 {
2618         unsigned long gma_head, gma_tail, gma_bottom;
2619         struct parser_exec_state s;
2620         int ret = 0;
2621
2622         /* ring base is page aligned */
2623         if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
2624                 return -EINVAL;
2625
2626         gma_head = workload->rb_start + workload->rb_head;
2627         gma_tail = workload->rb_start + workload->rb_tail;
2628         gma_bottom = workload->rb_start +  _RING_CTL_BUF_SIZE(workload->rb_ctl);
2629
2630         s.buf_type = RING_BUFFER_INSTRUCTION;
2631         s.buf_addr_type = GTT_BUFFER;
2632         s.vgpu = workload->vgpu;
2633         s.ring_id = workload->ring_id;
2634         s.ring_start = workload->rb_start;
2635         s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2636         s.ring_head = gma_head;
2637         s.ring_tail = gma_tail;
2638         s.rb_va = workload->shadow_ring_buffer_va;
2639         s.workload = workload;
2640         s.is_ctx_wa = false;
2641
2642         if ((bypass_scan_mask & (1 << workload->ring_id)) ||
2643                 gma_head == gma_tail)
2644                 return 0;
2645
2646         if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2647                 ret = -EINVAL;
2648                 goto out;
2649         }
2650
2651         ret = ip_gma_set(&s, gma_head);
2652         if (ret)
2653                 goto out;
2654
2655         ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2656                 workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2657
2658 out:
2659         return ret;
2660 }
2661
2662 static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2663 {
2664
2665         unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;
2666         struct parser_exec_state s;
2667         int ret = 0;
2668         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2669                                 struct intel_vgpu_workload,
2670                                 wa_ctx);
2671
2672         /* ring base is page aligned */
2673         if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
2674                                         I915_GTT_PAGE_SIZE)))
2675                 return -EINVAL;
2676
2677         ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(u32);
2678         ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2679                         PAGE_SIZE);
2680         gma_head = wa_ctx->indirect_ctx.guest_gma;
2681         gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2682         gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size;
2683
2684         s.buf_type = RING_BUFFER_INSTRUCTION;
2685         s.buf_addr_type = GTT_BUFFER;
2686         s.vgpu = workload->vgpu;
2687         s.ring_id = workload->ring_id;
2688         s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2689         s.ring_size = ring_size;
2690         s.ring_head = gma_head;
2691         s.ring_tail = gma_tail;
2692         s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2693         s.workload = workload;
2694         s.is_ctx_wa = true;
2695
2696         if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2697                 ret = -EINVAL;
2698                 goto out;
2699         }
2700
2701         ret = ip_gma_set(&s, gma_head);
2702         if (ret)
2703                 goto out;
2704
2705         ret = command_scan(&s, 0, ring_tail,
2706                 wa_ctx->indirect_ctx.guest_gma, ring_size);
2707 out:
2708         return ret;
2709 }
2710
2711 static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2712 {
2713         struct intel_vgpu *vgpu = workload->vgpu;
2714         struct intel_vgpu_submission *s = &vgpu->submission;
2715         unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2716         void *shadow_ring_buffer_va;
2717         int ring_id = workload->ring_id;
2718         int ret;
2719
2720         guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2721
2722         /* calculate workload ring buffer size */
2723         workload->rb_len = (workload->rb_tail + guest_rb_size -
2724                         workload->rb_head) % guest_rb_size;
2725
2726         gma_head = workload->rb_start + workload->rb_head;
2727         gma_tail = workload->rb_start + workload->rb_tail;
2728         gma_top = workload->rb_start + guest_rb_size;
2729
2730         if (workload->rb_len > s->ring_scan_buffer_size[ring_id]) {
2731                 void *p;
2732
2733                 /* realloc the new ring buffer if needed */
2734                 p = krealloc(s->ring_scan_buffer[ring_id], workload->rb_len,
2735                                 GFP_KERNEL);
2736                 if (!p) {
2737                         gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
2738                         return -ENOMEM;
2739                 }
2740                 s->ring_scan_buffer[ring_id] = p;
2741                 s->ring_scan_buffer_size[ring_id] = workload->rb_len;
2742         }
2743
2744         shadow_ring_buffer_va = s->ring_scan_buffer[ring_id];
2745
2746         /* get shadow ring buffer va */
2747         workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2748
2749         /* head > tail --> copy head <-> top */
2750         if (gma_head > gma_tail) {
2751                 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2752                                       gma_head, gma_top, shadow_ring_buffer_va);
2753                 if (ret < 0) {
2754                         gvt_vgpu_err("fail to copy guest ring buffer\n");
2755                         return ret;
2756                 }
2757                 shadow_ring_buffer_va += ret;
2758                 gma_head = workload->rb_start;
2759         }
2760
2761         /* copy head or start <-> tail */
2762         ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2763                                 shadow_ring_buffer_va);
2764         if (ret < 0) {
2765                 gvt_vgpu_err("fail to copy guest ring buffer\n");
2766                 return ret;
2767         }
2768         return 0;
2769 }
2770
2771 int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2772 {
2773         int ret;
2774         struct intel_vgpu *vgpu = workload->vgpu;
2775
2776         ret = shadow_workload_ring_buffer(workload);
2777         if (ret) {
2778                 gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2779                 return ret;
2780         }
2781
2782         ret = scan_workload(workload);
2783         if (ret) {
2784                 gvt_vgpu_err("scan workload error\n");
2785                 return ret;
2786         }
2787         return 0;
2788 }
2789
2790 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2791 {
2792         int ctx_size = wa_ctx->indirect_ctx.size;
2793         unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
2794         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2795                                         struct intel_vgpu_workload,
2796                                         wa_ctx);
2797         struct intel_vgpu *vgpu = workload->vgpu;
2798         struct drm_i915_gem_object *obj;
2799         int ret = 0;
2800         void *map;
2801
2802         obj = i915_gem_object_create(workload->vgpu->gvt->dev_priv,
2803                                      roundup(ctx_size + CACHELINE_BYTES,
2804                                              PAGE_SIZE));
2805         if (IS_ERR(obj))
2806                 return PTR_ERR(obj);
2807
2808         /* get the va of the shadow batch buffer */
2809         map = i915_gem_object_pin_map(obj, I915_MAP_WB);
2810         if (IS_ERR(map)) {
2811                 gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
2812                 ret = PTR_ERR(map);
2813                 goto put_obj;
2814         }
2815
2816         ret = i915_gem_object_set_to_cpu_domain(obj, false);
2817         if (ret) {
2818                 gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
2819                 goto unmap_src;
2820         }
2821
2822         ret = copy_gma_to_hva(workload->vgpu,
2823                                 workload->vgpu->gtt.ggtt_mm,
2824                                 guest_gma, guest_gma + ctx_size,
2825                                 map);
2826         if (ret < 0) {
2827                 gvt_vgpu_err("fail to copy guest indirect ctx\n");
2828                 goto unmap_src;
2829         }
2830
2831         wa_ctx->indirect_ctx.obj = obj;
2832         wa_ctx->indirect_ctx.shadow_va = map;
2833         return 0;
2834
2835 unmap_src:
2836         i915_gem_object_unpin_map(obj);
2837 put_obj:
2838         i915_gem_object_put(obj);
2839         return ret;
2840 }
2841
2842 static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2843 {
2844         u32 per_ctx_start[CACHELINE_DWORDS] = {0};
2845         unsigned char *bb_start_sva;
2846
2847         if (!wa_ctx->per_ctx.valid)
2848                 return 0;
2849
2850         per_ctx_start[0] = 0x18800001;
2851         per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
2852
2853         bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
2854                                 wa_ctx->indirect_ctx.size;
2855
2856         memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
2857
2858         return 0;
2859 }
2860
2861 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2862 {
2863         int ret;
2864         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2865                                         struct intel_vgpu_workload,
2866                                         wa_ctx);
2867         struct intel_vgpu *vgpu = workload->vgpu;
2868
2869         if (wa_ctx->indirect_ctx.size == 0)
2870                 return 0;
2871
2872         ret = shadow_indirect_ctx(wa_ctx);
2873         if (ret) {
2874                 gvt_vgpu_err("fail to shadow indirect ctx\n");
2875                 return ret;
2876         }
2877
2878         combine_wa_ctx(wa_ctx);
2879
2880         ret = scan_wa_ctx(wa_ctx);
2881         if (ret) {
2882                 gvt_vgpu_err("scan wa ctx error\n");
2883                 return ret;
2884         }
2885
2886         return 0;
2887 }
2888
2889 static const struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt,
2890                 unsigned int opcode, unsigned long rings)
2891 {
2892         const struct cmd_info *info = NULL;
2893         unsigned int ring;
2894
2895         for_each_set_bit(ring, &rings, I915_NUM_ENGINES) {
2896                 info = find_cmd_entry(gvt, opcode, ring);
2897                 if (info)
2898                         break;
2899         }
2900         return info;
2901 }
2902
2903 static int init_cmd_table(struct intel_gvt *gvt)
2904 {
2905         int i;
2906         struct cmd_entry *e;
2907         const struct cmd_info *info;
2908         unsigned int gen_type;
2909
2910         gen_type = intel_gvt_get_device_type(gvt);
2911
2912         for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
2913                 if (!(cmd_info[i].devices & gen_type))
2914                         continue;
2915
2916                 e = kzalloc(sizeof(*e), GFP_KERNEL);
2917                 if (!e)
2918                         return -ENOMEM;
2919
2920                 e->info = &cmd_info[i];
2921                 info = find_cmd_entry_any_ring(gvt,
2922                                 e->info->opcode, e->info->rings);
2923                 if (info) {
2924                         gvt_err("%s %s duplicated\n", e->info->name,
2925                                         info->name);
2926                         kfree(e);
2927                         return -EEXIST;
2928                 }
2929                 if (cmd_info[i].opcode == OP_MI_NOOP)
2930                         mi_noop_index = i;
2931
2932                 INIT_HLIST_NODE(&e->hlist);
2933                 add_cmd_entry(gvt, e);
2934                 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
2935                                 e->info->name, e->info->opcode, e->info->flag,
2936                                 e->info->devices, e->info->rings);
2937         }
2938         return 0;
2939 }
2940
2941 static void clean_cmd_table(struct intel_gvt *gvt)
2942 {
2943         struct hlist_node *tmp;
2944         struct cmd_entry *e;
2945         int i;
2946
2947         hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
2948                 kfree(e);
2949
2950         hash_init(gvt->cmd_table);
2951 }
2952
2953 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
2954 {
2955         clean_cmd_table(gvt);
2956 }
2957
2958 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
2959 {
2960         int ret;
2961
2962         ret = init_cmd_table(gvt);
2963         if (ret) {
2964                 intel_gvt_clean_cmd_parser(gvt);
2965                 return ret;
2966         }
2967         return 0;
2968 }