drivers/gpu/drm/i915/gt/uc/intel_uc.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2016-2019 Intel Corporation
   4  */
   5
   6 #include "gt/intel_gt.h"
   7 #include "gt/intel_reset.h"
   8 #include "intel_guc.h"
   9 #include "intel_guc_ads.h"
  10 #include "intel_guc_submission.h"
  11 #include "gt/intel_rps.h"
  12 #include "intel_uc.h"
  13
  14 #include "i915_drv.h"
  15
  16 static const struct intel_uc_ops uc_ops_off;
  17 static const struct intel_uc_ops uc_ops_on;
  18
  19 static void uc_expand_default_options(struct intel_uc *uc)
  20 {
  21         struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
  22
  23         if (i915->params.enable_guc != -1)
  24                 return;
  25
  26         /* Don't enable GuC/HuC on pre-Gen12 */
  27         if (GRAPHICS_VER(i915) < 12) {
  28                 i915->params.enable_guc = 0;
  29                 return;
  30         }
  31
  32         /* Don't enable GuC/HuC on older Gen12 platforms */
  33         if (IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) {
  34                 i915->params.enable_guc = 0;
  35                 return;
  36         }
  37
  38         /* Intermediate platforms are HuC authentication only */
  39         if (IS_ALDERLAKE_S(i915) && !IS_ADLS_RPLS(i915)) {
  40                 i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
  41                 return;
  42         }
  43
  44         /* Default: enable HuC authentication and GuC submission */
  45         i915->params.enable_guc = ENABLE_GUC_LOAD_HUC | ENABLE_GUC_SUBMISSION;
  46 }
  47
  48 /* Reset GuC providing us with fresh state for both GuC and HuC.
  49  */
  50 static int __intel_uc_reset_hw(struct intel_uc *uc)
  51 {
  52         struct intel_gt *gt = uc_to_gt(uc);
  53         int ret;
  54         u32 guc_status;
  55
  56         ret = i915_inject_probe_error(gt->i915, -ENXIO);
  57         if (ret)
  58                 return ret;
  59
  60         ret = intel_reset_guc(gt);
  61         if (ret) {
  62                 DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
  63                 return ret;
  64         }
  65
  66         guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
  67         WARN(!(guc_status & GS_MIA_IN_RESET),
  68              "GuC status: 0x%x, MIA core expected to be in reset\n",
  69              guc_status);
  70
  71         return ret;
  72 }
  73
  74 static void __confirm_options(struct intel_uc *uc)
  75 {
  76         struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
  77
  78         drm_dbg(&i915->drm,
  79                 "enable_guc=%d (guc:%s submission:%s huc:%s slpc:%s)\n",
  80                 i915->params.enable_guc,
  81                 yesno(intel_uc_wants_guc(uc)),
  82                 yesno(intel_uc_wants_guc_submission(uc)),
  83                 yesno(intel_uc_wants_huc(uc)),
  84                 yesno(intel_uc_wants_guc_slpc(uc)));
  85
  86         if (i915->params.enable_guc == 0) {
  87                 GEM_BUG_ON(intel_uc_wants_guc(uc));
  88                 GEM_BUG_ON(intel_uc_wants_guc_submission(uc));
  89                 GEM_BUG_ON(intel_uc_wants_huc(uc));
  90                 GEM_BUG_ON(intel_uc_wants_guc_slpc(uc));
  91                 return;
  92         }
  93
  94         if (!intel_uc_supports_guc(uc))
  95                 drm_info(&i915->drm,
  96                          "Incompatible option enable_guc=%d - %s\n",
  97                          i915->params.enable_guc, "GuC is not supported!");
  98
  99         if (i915->params.enable_guc & ENABLE_GUC_LOAD_HUC &&
 100             !intel_uc_supports_huc(uc))
 101                 drm_info(&i915->drm,
 102                          "Incompatible option enable_guc=%d - %s\n",
 103                          i915->params.enable_guc, "HuC is not supported!");
 104
 105         if (i915->params.enable_guc & ENABLE_GUC_SUBMISSION &&
 106             !intel_uc_supports_guc_submission(uc))
 107                 drm_info(&i915->drm,
 108                          "Incompatible option enable_guc=%d - %s\n",
 109                          i915->params.enable_guc, "GuC submission is N/A");
 110
 111         if (i915->params.enable_guc & ~ENABLE_GUC_MASK)
 112                 drm_info(&i915->drm,
 113                          "Incompatible option enable_guc=%d - %s\n",
 114                          i915->params.enable_guc, "undocumented flag");
 115 }
 116
 117 void intel_uc_init_early(struct intel_uc *uc)
 118 {
 119         uc_expand_default_options(uc);
 120
 121         intel_guc_init_early(&uc->guc);
 122         intel_huc_init_early(&uc->huc);
 123
 124         __confirm_options(uc);
 125
 126         if (intel_uc_wants_guc(uc))
 127                 uc->ops = &uc_ops_on;
 128         else
 129                 uc->ops = &uc_ops_off;
 130 }
 131
 132 void intel_uc_init_late(struct intel_uc *uc)
 133 {
 134         intel_guc_init_late(&uc->guc);
 135 }
 136
 137 void intel_uc_driver_late_release(struct intel_uc *uc)
 138 {
 139 }
 140
 141 /**
 142  * intel_uc_init_mmio - setup uC MMIO access
 143  * @uc: the intel_uc structure
 144  *
 145  * Setup minimal state necessary for MMIO accesses later in the
 146  * initialization sequence.
 147  */
 148 void intel_uc_init_mmio(struct intel_uc *uc)
 149 {
 150         intel_guc_init_send_regs(&uc->guc);
 151 }
 152
 153 static void __uc_capture_load_err_log(struct intel_uc *uc)
 154 {
 155         struct intel_guc *guc = &uc->guc;
 156
 157         if (guc->log.vma && !uc->load_err_log)
 158                 uc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
 159 }
 160
 161 static void __uc_free_load_err_log(struct intel_uc *uc)
 162 {
 163         struct drm_i915_gem_object *log = fetch_and_zero(&uc->load_err_log);
 164
 165         if (log)
 166                 i915_gem_object_put(log);
 167 }
 168
 169 void intel_uc_driver_remove(struct intel_uc *uc)
 170 {
 171         intel_uc_fini_hw(uc);
 172         intel_uc_fini(uc);
 173         __uc_free_load_err_log(uc);
 174 }
 175
 176 /*
 177  * Events triggered while CT buffers are disabled are logged in the SCRATCH_15
 178  * register using the same bits used in the CT message payload. Since our
 179  * communication channel with guc is turned off at this point, we can save the
 180  * message and handle it after we turn it back on.
 181  */
 182 static void guc_clear_mmio_msg(struct intel_guc *guc)
 183 {
 184         intel_uncore_write(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15), 0);
 185 }
 186
 187 static void guc_get_mmio_msg(struct intel_guc *guc)
 188 {
 189         u32 val;
 190
 191         spin_lock_irq(&guc->irq_lock);
 192
 193         val = intel_uncore_read(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15));
 194         guc->mmio_msg |= val & guc->msg_enabled_mask;
 195
 196         /*
 197          * clear all events, including the ones we're not currently servicing,
 198          * to make sure we don't try to process a stale message if we enable
 199          * handling of more events later.
 200          */
 201         guc_clear_mmio_msg(guc);
 202
 203         spin_unlock_irq(&guc->irq_lock);
 204 }
 205
 206 static void guc_handle_mmio_msg(struct intel_guc *guc)
 207 {
 208         /* we need communication to be enabled to reply to GuC */
 209         GEM_BUG_ON(!intel_guc_ct_enabled(&guc->ct));
 210
 211         spin_lock_irq(&guc->irq_lock);
 212         if (guc->mmio_msg) {
 213                 intel_guc_to_host_process_recv_msg(guc, &guc->mmio_msg, 1);
 214                 guc->mmio_msg = 0;
 215         }
 216         spin_unlock_irq(&guc->irq_lock);
 217 }
 218
 219 static int guc_enable_communication(struct intel_guc *guc)
 220 {
 221         struct intel_gt *gt = guc_to_gt(guc);
 222         struct drm_i915_private *i915 = gt->i915;
 223         int ret;
 224
 225         GEM_BUG_ON(intel_guc_ct_enabled(&guc->ct));
 226
 227         ret = i915_inject_probe_error(i915, -ENXIO);
 228         if (ret)
 229                 return ret;
 230
 231         ret = intel_guc_ct_enable(&guc->ct);
 232         if (ret)
 233                 return ret;
 234
 235         /* check for mmio messages received before/during the CT enable */
 236         guc_get_mmio_msg(guc);
 237         guc_handle_mmio_msg(guc);
 238
 239         intel_guc_enable_interrupts(guc);
 240
 241         /* check for CT messages received before we enabled interrupts */
 242         spin_lock_irq(&gt->irq_lock);
 243         intel_guc_ct_event_handler(&guc->ct);
 244         spin_unlock_irq(&gt->irq_lock);
 245
 246         drm_dbg(&i915->drm, "GuC communication enabled\n");
 247
 248         return 0;
 249 }
 250
 251 static void guc_disable_communication(struct intel_guc *guc)
 252 {
 253         struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
 254
 255         /*
 256          * Events generated during or after CT disable are logged by guc in
 257          * via mmio. Make sure the register is clear before disabling CT since
 258          * all events we cared about have already been processed via CT.
 259          */
 260         guc_clear_mmio_msg(guc);
 261
 262         intel_guc_disable_interrupts(guc);
 263
 264         intel_guc_ct_disable(&guc->ct);
 265
 266         /*
 267          * Check for messages received during/after the CT disable. We do not
 268          * expect any messages to have arrived via CT between the interrupt
 269          * disable and the CT disable because GuC should've been idle until we
 270          * triggered the CT disable protocol.
 271          */
 272         guc_get_mmio_msg(guc);
 273
 274         drm_dbg(&i915->drm, "GuC communication disabled\n");
 275 }
 276
 277 static void __uc_fetch_firmwares(struct intel_uc *uc)
 278 {
 279         int err;
 280
 281         GEM_BUG_ON(!intel_uc_wants_guc(uc));
 282
 283         err = intel_uc_fw_fetch(&uc->guc.fw);
 284         if (err) {
 285                 /* Make sure we transition out of transient "SELECTED" state */
 286                 if (intel_uc_wants_huc(uc)) {
 287                         drm_dbg(&uc_to_gt(uc)->i915->drm,
 288                                 "Failed to fetch GuC: %d disabling HuC\n", err);
 289                         intel_uc_fw_change_status(&uc->huc.fw,
 290                                                   INTEL_UC_FIRMWARE_ERROR);
 291                 }
 292
 293                 return;
 294         }
 295
 296         if (intel_uc_wants_huc(uc))
 297                 intel_uc_fw_fetch(&uc->huc.fw);
 298 }
 299
 300 static void __uc_cleanup_firmwares(struct intel_uc *uc)
 301 {
 302         intel_uc_fw_cleanup_fetch(&uc->huc.fw);
 303         intel_uc_fw_cleanup_fetch(&uc->guc.fw);
 304 }
 305
 306 static int __uc_init(struct intel_uc *uc)
 307 {
 308         struct intel_guc *guc = &uc->guc;
 309         struct intel_huc *huc = &uc->huc;
 310         int ret;
 311
 312         GEM_BUG_ON(!intel_uc_wants_guc(uc));
 313
 314         if (!intel_uc_uses_guc(uc))
 315                 return 0;
 316
 317         if (i915_inject_probe_failure(uc_to_gt(uc)->i915))
 318                 return -ENOMEM;
 319
 320         ret = intel_guc_init(guc);
 321         if (ret)
 322                 return ret;
 323
 324         if (intel_uc_uses_huc(uc)) {
 325                 ret = intel_huc_init(huc);
 326                 if (ret)
 327                         goto out_guc;
 328         }
 329
 330         return 0;
 331
 332 out_guc:
 333         intel_guc_fini(guc);
 334         return ret;
 335 }
 336
 337 static void __uc_fini(struct intel_uc *uc)
 338 {
 339         intel_huc_fini(&uc->huc);
 340         intel_guc_fini(&uc->guc);
 341 }
 342
 343 static int __uc_sanitize(struct intel_uc *uc)
 344 {
 345         struct intel_guc *guc = &uc->guc;
 346         struct intel_huc *huc = &uc->huc;
 347
 348         GEM_BUG_ON(!intel_uc_supports_guc(uc));
 349
 350         intel_huc_sanitize(huc);
 351         intel_guc_sanitize(guc);
 352
 353         return __intel_uc_reset_hw(uc);
 354 }
 355
 356 /* Initialize and verify the uC regs related to uC positioning in WOPCM */
 357 static int uc_init_wopcm(struct intel_uc *uc)
 358 {
 359         struct intel_gt *gt = uc_to_gt(uc);
 360         struct intel_uncore *uncore = gt->uncore;
 361         u32 base = intel_wopcm_guc_base(&gt->i915->wopcm);
 362         u32 size = intel_wopcm_guc_size(&gt->i915->wopcm);
 363         u32 huc_agent = intel_uc_uses_huc(uc) ? HUC_LOADING_AGENT_GUC : 0;
 364         u32 mask;
 365         int err;
 366
 367         if (unlikely(!base || !size)) {
 368                 i915_probe_error(gt->i915, "Unsuccessful WOPCM partitioning\n");
 369                 return -E2BIG;
 370         }
 371
 372         GEM_BUG_ON(!intel_uc_supports_guc(uc));
 373         GEM_BUG_ON(!(base & GUC_WOPCM_OFFSET_MASK));
 374         GEM_BUG_ON(base & ~GUC_WOPCM_OFFSET_MASK);
 375         GEM_BUG_ON(!(size & GUC_WOPCM_SIZE_MASK));
 376         GEM_BUG_ON(size & ~GUC_WOPCM_SIZE_MASK);
 377
 378         err = i915_inject_probe_error(gt->i915, -ENXIO);
 379         if (err)
 380                 return err;
 381
 382         mask = GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED;
 383         err = intel_uncore_write_and_verify(uncore, GUC_WOPCM_SIZE, size, mask,
 384                                             size | GUC_WOPCM_SIZE_LOCKED);
 385         if (err)
 386                 goto err_out;
 387
 388         mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
 389         err = intel_uncore_write_and_verify(uncore, DMA_GUC_WOPCM_OFFSET,
 390                                             base | huc_agent, mask,
 391                                             base | huc_agent |
 392                                             GUC_WOPCM_OFFSET_VALID);
 393         if (err)
 394                 goto err_out;
 395
 396         return 0;
 397
 398 err_out:
 399         i915_probe_error(gt->i915, "Failed to init uC WOPCM registers!\n");
 400         i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
 401                          i915_mmio_reg_offset(DMA_GUC_WOPCM_OFFSET),
 402                          intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
 403         i915_probe_error(gt->i915, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
 404                          i915_mmio_reg_offset(GUC_WOPCM_SIZE),
 405                          intel_uncore_read(uncore, GUC_WOPCM_SIZE));
 406
 407         return err;
 408 }
 409
 410 static bool uc_is_wopcm_locked(struct intel_uc *uc)
 411 {
 412         struct intel_gt *gt = uc_to_gt(uc);
 413         struct intel_uncore *uncore = gt->uncore;
 414
 415         return (intel_uncore_read(uncore, GUC_WOPCM_SIZE) & GUC_WOPCM_SIZE_LOCKED) ||
 416                (intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET) & GUC_WOPCM_OFFSET_VALID);
 417 }
 418
 419 static int __uc_check_hw(struct intel_uc *uc)
 420 {
 421         if (!intel_uc_supports_guc(uc))
 422                 return 0;
 423
 424         /*
 425          * We can silently continue without GuC only if it was never enabled
 426          * before on this system after reboot, otherwise we risk GPU hangs.
 427          * To check if GuC was loaded before we look at WOPCM registers.
 428          */
 429         if (uc_is_wopcm_locked(uc))
 430                 return -EIO;
 431
 432         return 0;
 433 }
 434
 435 static void print_fw_ver(struct intel_uc *uc, struct intel_uc_fw *fw)
 436 {
 437         struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
 438
 439         drm_info(&i915->drm, "%s firmware %s version %u.%u\n",
 440                  intel_uc_fw_type_repr(fw->type), fw->path,
 441                  fw->major_ver_found, fw->minor_ver_found);
 442 }
 443
 444 static int __uc_init_hw(struct intel_uc *uc)
 445 {
 446         struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
 447         struct intel_guc *guc = &uc->guc;
 448         struct intel_huc *huc = &uc->huc;
 449         int ret, attempts;
 450
 451         GEM_BUG_ON(!intel_uc_supports_guc(uc));
 452         GEM_BUG_ON(!intel_uc_wants_guc(uc));
 453
 454         print_fw_ver(uc, &guc->fw);
 455
 456         if (intel_uc_uses_huc(uc))
 457                 print_fw_ver(uc, &huc->fw);
 458
 459         if (!intel_uc_fw_is_loadable(&guc->fw)) {
 460                 ret = __uc_check_hw(uc) ||
 461                       intel_uc_fw_is_overridden(&guc->fw) ||
 462                       intel_uc_wants_guc_submission(uc) ?
 463                       intel_uc_fw_status_to_error(guc->fw.status) : 0;
 464                 goto err_out;
 465         }
 466
 467         ret = uc_init_wopcm(uc);
 468         if (ret)
 469                 goto err_out;
 470
 471         intel_guc_reset_interrupts(guc);
 472
 473         /* WaEnableuKernelHeaderValidFix:skl */
 474         /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
 475         if (GRAPHICS_VER(i915) == 9)
 476                 attempts = 3;
 477         else
 478                 attempts = 1;
 479
 480         intel_rps_raise_unslice(&uc_to_gt(uc)->rps);
 481
 482         while (attempts--) {
 483                 /*
 484                  * Always reset the GuC just before (re)loading, so
 485                  * that the state and timing are fairly predictable
 486                  */
 487                 ret = __uc_sanitize(uc);
 488                 if (ret)
 489                         goto err_out;
 490
 491                 intel_huc_fw_upload(huc);
 492                 intel_guc_ads_reset(guc);
 493                 intel_guc_write_params(guc);
 494                 ret = intel_guc_fw_upload(guc);
 495                 if (ret == 0)
 496                         break;
 497
 498                 DRM_DEBUG_DRIVER("GuC fw load failed: %d; will reset and "
 499                                  "retry %d more time(s)\n", ret, attempts);
 500         }
 501
 502         /* Did we succeded or run out of retries? */
 503         if (ret)
 504                 goto err_log_capture;
 505
 506         ret = guc_enable_communication(guc);
 507         if (ret)
 508                 goto err_log_capture;
 509
 510         intel_huc_auth(huc);
 511
 512         if (intel_uc_uses_guc_submission(uc))
 513                 intel_guc_submission_enable(guc);
 514
 515         if (intel_uc_uses_guc_slpc(uc)) {
 516                 ret = intel_guc_slpc_enable(&guc->slpc);
 517                 if (ret)
 518                         goto err_submission;
 519         } else {
 520                 /* Restore GT back to RPn for non-SLPC path */
 521                 intel_rps_lower_unslice(&uc_to_gt(uc)->rps);
 522         }
 523
 524         drm_info(&i915->drm, "GuC submission %s\n",
 525                  enableddisabled(intel_uc_uses_guc_submission(uc)));
 526         drm_info(&i915->drm, "GuC SLPC %s\n",
 527                  enableddisabled(intel_uc_uses_guc_slpc(uc)));
 528
 529         return 0;
 530
 531         /*
 532          * We've failed to load the firmware :(
 533          */
 534 err_submission:
 535         intel_guc_submission_disable(guc);
 536 err_log_capture:
 537         __uc_capture_load_err_log(uc);
 538 err_out:
 539         /* Return GT back to RPn */
 540         intel_rps_lower_unslice(&uc_to_gt(uc)->rps);
 541
 542         __uc_sanitize(uc);
 543
 544         if (!ret) {
 545                 drm_notice(&i915->drm, "GuC is uninitialized\n");
 546                 /* We want to run without GuC submission */
 547                 return 0;
 548         }
 549
 550         i915_probe_error(i915, "GuC initialization failed %d\n", ret);
 551
 552         /* We want to keep KMS alive */
 553         return -EIO;
 554 }
 555
 556 static void __uc_fini_hw(struct intel_uc *uc)
 557 {
 558         struct intel_guc *guc = &uc->guc;
 559
 560         if (!intel_guc_is_fw_running(guc))
 561                 return;
 562
 563         if (intel_uc_uses_guc_submission(uc))
 564                 intel_guc_submission_disable(guc);
 565
 566         __uc_sanitize(uc);
 567 }
 568
 569 /**
 570  * intel_uc_reset_prepare - Prepare for reset
 571  * @uc: the intel_uc structure
 572  *
 573  * Preparing for full gpu reset.
 574  */
 575 void intel_uc_reset_prepare(struct intel_uc *uc)
 576 {
 577         struct intel_guc *guc = &uc->guc;
 578
 579         uc->reset_in_progress = true;
 580
 581         /* Nothing to do if GuC isn't supported */
 582         if (!intel_uc_supports_guc(uc))
 583                 return;
 584
 585         /* Firmware expected to be running when this function is called */
 586         if (!intel_guc_is_ready(guc))
 587                 goto sanitize;
 588
 589         if (intel_uc_uses_guc_submission(uc))
 590                 intel_guc_submission_reset_prepare(guc);
 591
 592 sanitize:
 593         __uc_sanitize(uc);
 594 }
 595
 596 void intel_uc_reset(struct intel_uc *uc, bool stalled)
 597 {
 598         struct intel_guc *guc = &uc->guc;
 599
 600         /* Firmware can not be running when this function is called  */
 601         if (intel_uc_uses_guc_submission(uc))
 602                 intel_guc_submission_reset(guc, stalled);
 603 }
 604
 605 void intel_uc_reset_finish(struct intel_uc *uc)
 606 {
 607         struct intel_guc *guc = &uc->guc;
 608
 609         uc->reset_in_progress = false;
 610
 611         /* Firmware expected to be running when this function is called */
 612         if (intel_guc_is_fw_running(guc) && intel_uc_uses_guc_submission(uc))
 613                 intel_guc_submission_reset_finish(guc);
 614 }
 615
 616 void intel_uc_cancel_requests(struct intel_uc *uc)
 617 {
 618         struct intel_guc *guc = &uc->guc;
 619
 620         /* Firmware can not be running when this function is called  */
 621         if (intel_uc_uses_guc_submission(uc))
 622                 intel_guc_submission_cancel_requests(guc);
 623 }
 624
 625 void intel_uc_runtime_suspend(struct intel_uc *uc)
 626 {
 627         struct intel_guc *guc = &uc->guc;
 628
 629         if (!intel_guc_is_ready(guc))
 630                 return;
 631
 632         /*
 633          * Wait for any outstanding CTB before tearing down communication /w the
 634          * GuC.
 635          */
 636 #define OUTSTANDING_CTB_TIMEOUT_PERIOD  (HZ / 5)
 637         intel_guc_wait_for_pending_msg(guc, &guc->outstanding_submission_g2h,
 638                                        false, OUTSTANDING_CTB_TIMEOUT_PERIOD);
 639         GEM_WARN_ON(atomic_read(&guc->outstanding_submission_g2h));
 640
 641         guc_disable_communication(guc);
 642 }
 643
 644 void intel_uc_suspend(struct intel_uc *uc)
 645 {
 646         struct intel_guc *guc = &uc->guc;
 647         intel_wakeref_t wakeref;
 648         int err;
 649
 650         if (!intel_guc_is_ready(guc))
 651                 return;
 652
 653         with_intel_runtime_pm(&uc_to_gt(uc)->i915->runtime_pm, wakeref) {
 654                 err = intel_guc_suspend(guc);
 655                 if (err)
 656                         DRM_DEBUG_DRIVER("Failed to suspend GuC, err=%d", err);
 657         }
 658 }
 659
 660 static int __uc_resume(struct intel_uc *uc, bool enable_communication)
 661 {
 662         struct intel_guc *guc = &uc->guc;
 663         struct intel_gt *gt = guc_to_gt(guc);
 664         int err;
 665
 666         if (!intel_guc_is_fw_running(guc))
 667                 return 0;
 668
 669         /* Make sure we enable communication if and only if it's disabled */
 670         GEM_BUG_ON(enable_communication == intel_guc_ct_enabled(&guc->ct));
 671
 672         if (enable_communication)
 673                 guc_enable_communication(guc);
 674
 675         /* If we are only resuming GuC communication but not reloading
 676          * GuC, we need to ensure the ARAT timer interrupt is enabled
 677          * again. In case of GuC reload, it is enabled during SLPC enable.
 678          */
 679         if (enable_communication && intel_uc_uses_guc_slpc(uc))
 680                 intel_guc_pm_intrmsk_enable(gt);
 681
 682         err = intel_guc_resume(guc);
 683         if (err) {
 684                 DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
 685                 return err;
 686         }
 687
 688         return 0;
 689 }
 690
 691 int intel_uc_resume(struct intel_uc *uc)
 692 {
 693         /*
 694          * When coming out of S3/S4 we sanitize and re-init the HW, so
 695          * communication is already re-enabled at this point.
 696          */
 697         return __uc_resume(uc, false);
 698 }
 699
 700 int intel_uc_runtime_resume(struct intel_uc *uc)
 701 {
 702         /*
 703          * During runtime resume we don't sanitize, so we need to re-init
 704          * communication as well.
 705          */
 706         return __uc_resume(uc, true);
 707 }
 708
 709 static const struct intel_uc_ops uc_ops_off = {
 710         .init_hw = __uc_check_hw,
 711 };
 712
 713 static const struct intel_uc_ops uc_ops_on = {
 714         .sanitize = __uc_sanitize,
 715
 716         .init_fw = __uc_fetch_firmwares,
 717         .fini_fw = __uc_cleanup_firmwares,
 718
 719         .init = __uc_init,
 720         .fini = __uc_fini,
 721
 722         .init_hw = __uc_init_hw,
 723         .fini_hw = __uc_fini_hw,
 724 };