drivers/gpu/drm/i915/gt/intel_gt.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5
   6 #include <drm/drm_managed.h>
   7 #include <drm/intel-gtt.h>
   8
   9 #include "gem/i915_gem_internal.h"
  10 #include "gem/i915_gem_lmem.h"
  11
  12 #include "i915_drv.h"
  13 #include "i915_perf_oa_regs.h"
  14 #include "i915_reg.h"
  15 #include "intel_context.h"
  16 #include "intel_engine_pm.h"
  17 #include "intel_engine_regs.h"
  18 #include "intel_ggtt_gmch.h"
  19 #include "intel_gt.h"
  20 #include "intel_gt_buffer_pool.h"
  21 #include "intel_gt_clock_utils.h"
  22 #include "intel_gt_debugfs.h"
  23 #include "intel_gt_mcr.h"
  24 #include "intel_gt_pm.h"
  25 #include "intel_gt_regs.h"
  26 #include "intel_gt_requests.h"
  27 #include "intel_migrate.h"
  28 #include "intel_mocs.h"
  29 #include "intel_pci_config.h"
  30 #include "intel_pm.h"
  31 #include "intel_rc6.h"
  32 #include "intel_renderstate.h"
  33 #include "intel_rps.h"
  34 #include "intel_sa_media.h"
  35 #include "intel_gt_sysfs.h"
  36 #include "intel_uncore.h"
  37 #include "shmem_utils.h"
  38
  39 void intel_gt_common_init_early(struct intel_gt *gt)
  40 {
  41         spin_lock_init(gt->irq_lock);
  42
  43         INIT_LIST_HEAD(&gt->closed_vma);
  44         spin_lock_init(&gt->closed_lock);
  45
  46         init_llist_head(&gt->watchdog.list);
  47         INIT_WORK(&gt->watchdog.work, intel_gt_watchdog_work);
  48
  49         intel_gt_init_buffer_pool(gt);
  50         intel_gt_init_reset(gt);
  51         intel_gt_init_requests(gt);
  52         intel_gt_init_timelines(gt);
  53         mutex_init(&gt->tlb.invalidate_lock);
  54         seqcount_mutex_init(&gt->tlb.seqno, &gt->tlb.invalidate_lock);
  55         intel_gt_pm_init_early(gt);
  56
  57         intel_wopcm_init_early(&gt->wopcm);
  58         intel_uc_init_early(&gt->uc);
  59         intel_rps_init_early(&gt->rps);
  60 }
  61
  62 /* Preliminary initialization of Tile 0 */
  63 int intel_root_gt_init_early(struct drm_i915_private *i915)
  64 {
  65         struct intel_gt *gt = to_gt(i915);
  66
  67         gt->i915 = i915;
  68         gt->uncore = &i915->uncore;
  69         gt->irq_lock = drmm_kzalloc(&i915->drm, sizeof(*gt->irq_lock), GFP_KERNEL);
  70         if (!gt->irq_lock)
  71                 return -ENOMEM;
  72
  73         intel_gt_common_init_early(gt);
  74
  75         return 0;
  76 }
  77
  78 static int intel_gt_probe_lmem(struct intel_gt *gt)
  79 {
  80         struct drm_i915_private *i915 = gt->i915;
  81         unsigned int instance = gt->info.id;
  82         int id = INTEL_REGION_LMEM_0 + instance;
  83         struct intel_memory_region *mem;
  84         int err;
  85
  86         mem = intel_gt_setup_lmem(gt);
  87         if (IS_ERR(mem)) {
  88                 err = PTR_ERR(mem);
  89                 if (err == -ENODEV)
  90                         return 0;
  91
  92                 drm_err(&i915->drm,
  93                         "Failed to setup region(%d) type=%d\n",
  94                         err, INTEL_MEMORY_LOCAL);
  95                 return err;
  96         }
  97
  98         mem->id = id;
  99         mem->instance = instance;
 100
 101         intel_memory_region_set_name(mem, "local%u", mem->instance);
 102
 103         GEM_BUG_ON(!HAS_REGION(i915, id));
 104         GEM_BUG_ON(i915->mm.regions[id]);
 105         i915->mm.regions[id] = mem;
 106
 107         return 0;
 108 }
 109
 110 int intel_gt_assign_ggtt(struct intel_gt *gt)
 111 {
 112         /* Media GT shares primary GT's GGTT */
 113         if (gt->type == GT_MEDIA) {
 114                 gt->ggtt = to_gt(gt->i915)->ggtt;
 115         } else {
 116                 gt->ggtt = i915_ggtt_create(gt->i915);
 117                 if (IS_ERR(gt->ggtt))
 118                         return PTR_ERR(gt->ggtt);
 119         }
 120
 121         list_add_tail(&gt->ggtt_link, &gt->ggtt->gt_list);
 122
 123         return 0;
 124 }
 125
 126 int intel_gt_init_mmio(struct intel_gt *gt)
 127 {
 128         intel_gt_init_clock_frequency(gt);
 129
 130         intel_uc_init_mmio(&gt->uc);
 131         intel_sseu_info_init(gt);
 132         intel_gt_mcr_init(gt);
 133
 134         return intel_engines_init_mmio(gt);
 135 }
 136
 137 static void init_unused_ring(struct intel_gt *gt, u32 base)
 138 {
 139         struct intel_uncore *uncore = gt->uncore;
 140
 141         intel_uncore_write(uncore, RING_CTL(base), 0);
 142         intel_uncore_write(uncore, RING_HEAD(base), 0);
 143         intel_uncore_write(uncore, RING_TAIL(base), 0);
 144         intel_uncore_write(uncore, RING_START(base), 0);
 145 }
 146
 147 static void init_unused_rings(struct intel_gt *gt)
 148 {
 149         struct drm_i915_private *i915 = gt->i915;
 150
 151         if (IS_I830(i915)) {
 152                 init_unused_ring(gt, PRB1_BASE);
 153                 init_unused_ring(gt, SRB0_BASE);
 154                 init_unused_ring(gt, SRB1_BASE);
 155                 init_unused_ring(gt, SRB2_BASE);
 156                 init_unused_ring(gt, SRB3_BASE);
 157         } else if (GRAPHICS_VER(i915) == 2) {
 158                 init_unused_ring(gt, SRB0_BASE);
 159                 init_unused_ring(gt, SRB1_BASE);
 160         } else if (GRAPHICS_VER(i915) == 3) {
 161                 init_unused_ring(gt, PRB1_BASE);
 162                 init_unused_ring(gt, PRB2_BASE);
 163         }
 164 }
 165
 166 int intel_gt_init_hw(struct intel_gt *gt)
 167 {
 168         struct drm_i915_private *i915 = gt->i915;
 169         struct intel_uncore *uncore = gt->uncore;
 170         int ret;
 171
 172         gt->last_init_time = ktime_get();
 173
 174         /* Double layer security blanket, see i915_gem_init() */
 175         intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 176
 177         if (HAS_EDRAM(i915) && GRAPHICS_VER(i915) < 9)
 178                 intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
 179
 180         if (IS_HASWELL(i915))
 181                 intel_uncore_write(uncore,
 182                                    HSW_MI_PREDICATE_RESULT_2,
 183                                    IS_HSW_GT3(i915) ?
 184                                    LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 185
 186         /* Apply the GT workarounds... */
 187         intel_gt_apply_workarounds(gt);
 188         /* ...and determine whether they are sticking. */
 189         intel_gt_verify_workarounds(gt, "init");
 190
 191         intel_gt_init_swizzling(gt);
 192
 193         /*
 194          * At least 830 can leave some of the unused rings
 195          * "active" (ie. head != tail) after resume which
 196          * will prevent c3 entry. Makes sure all unused rings
 197          * are totally idle.
 198          */
 199         init_unused_rings(gt);
 200
 201         ret = i915_ppgtt_init_hw(gt);
 202         if (ret) {
 203                 drm_err(&i915->drm, "Enabling PPGTT failed (%d)\n", ret);
 204                 goto out;
 205         }
 206
 207         /* We can't enable contexts until all firmware is loaded */
 208         ret = intel_uc_init_hw(&gt->uc);
 209         if (ret) {
 210                 i915_probe_error(i915, "Enabling uc failed (%d)\n", ret);
 211                 goto out;
 212         }
 213
 214         intel_mocs_init(gt);
 215
 216 out:
 217         intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 218         return ret;
 219 }
 220
 221 static void gen6_clear_engine_error_register(struct intel_engine_cs *engine)
 222 {
 223         GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
 224         GEN6_RING_FAULT_REG_POSTING_READ(engine);
 225 }
 226
 227 i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt)
 228 {
 229         /* GT0_PERF_LIMIT_REASONS is available only for Gen11+ */
 230         if (GRAPHICS_VER(gt->i915) < 11)
 231                 return INVALID_MMIO_REG;
 232
 233         return gt->type == GT_MEDIA ?
 234                 MTL_MEDIA_PERF_LIMIT_REASONS : GT0_PERF_LIMIT_REASONS;
 235 }
 236
 237 void
 238 intel_gt_clear_error_registers(struct intel_gt *gt,
 239                                intel_engine_mask_t engine_mask)
 240 {
 241         struct drm_i915_private *i915 = gt->i915;
 242         struct intel_uncore *uncore = gt->uncore;
 243         u32 eir;
 244
 245         if (GRAPHICS_VER(i915) != 2)
 246                 intel_uncore_write(uncore, PGTBL_ER, 0);
 247
 248         if (GRAPHICS_VER(i915) < 4)
 249                 intel_uncore_write(uncore, IPEIR(RENDER_RING_BASE), 0);
 250         else
 251                 intel_uncore_write(uncore, IPEIR_I965, 0);
 252
 253         intel_uncore_write(uncore, EIR, 0);
 254         eir = intel_uncore_read(uncore, EIR);
 255         if (eir) {
 256                 /*
 257                  * some errors might have become stuck,
 258                  * mask them.
 259                  */
 260                 drm_dbg(&gt->i915->drm, "EIR stuck: 0x%08x, masking\n", eir);
 261                 intel_uncore_rmw(uncore, EMR, 0, eir);
 262                 intel_uncore_write(uncore, GEN2_IIR,
 263                                    I915_MASTER_ERROR_INTERRUPT);
 264         }
 265
 266         if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
 267                 intel_gt_mcr_multicast_rmw(gt, XEHP_RING_FAULT_REG,
 268                                            RING_FAULT_VALID, 0);
 269                 intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG);
 270         } else if (GRAPHICS_VER(i915) >= 12) {
 271                 intel_uncore_rmw(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID, 0);
 272                 intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
 273         } else if (GRAPHICS_VER(i915) >= 8) {
 274                 intel_uncore_rmw(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID, 0);
 275                 intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
 276         } else if (GRAPHICS_VER(i915) >= 6) {
 277                 struct intel_engine_cs *engine;
 278                 enum intel_engine_id id;
 279
 280                 for_each_engine_masked(engine, gt, engine_mask, id)
 281                         gen6_clear_engine_error_register(engine);
 282         }
 283 }
 284
 285 static void gen6_check_faults(struct intel_gt *gt)
 286 {
 287         struct intel_engine_cs *engine;
 288         enum intel_engine_id id;
 289         u32 fault;
 290
 291         for_each_engine(engine, gt, id) {
 292                 fault = GEN6_RING_FAULT_REG_READ(engine);
 293                 if (fault & RING_FAULT_VALID) {
 294                         drm_dbg(&engine->i915->drm, "Unexpected fault\n"
 295                                 "\tAddr: 0x%08lx\n"
 296                                 "\tAddress space: %s\n"
 297                                 "\tSource ID: %d\n"
 298                                 "\tType: %d\n",
 299                                 fault & PAGE_MASK,
 300                                 fault & RING_FAULT_GTTSEL_MASK ?
 301                                 "GGTT" : "PPGTT",
 302                                 RING_FAULT_SRCID(fault),
 303                                 RING_FAULT_FAULT_TYPE(fault));
 304                 }
 305         }
 306 }
 307
 308 static void xehp_check_faults(struct intel_gt *gt)
 309 {
 310         u32 fault;
 311
 312         /*
 313          * Although the fault register now lives in an MCR register range,
 314          * the GAM registers are special and we only truly need to read
 315          * the "primary" GAM instance rather than handling each instance
 316          * individually.  intel_gt_mcr_read_any() will automatically steer
 317          * toward the primary instance.
 318          */
 319         fault = intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG);
 320         if (fault & RING_FAULT_VALID) {
 321                 u32 fault_data0, fault_data1;
 322                 u64 fault_addr;
 323
 324                 fault_data0 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA0);
 325                 fault_data1 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA1);
 326
 327                 fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
 328                              ((u64)fault_data0 << 12);
 329
 330                 drm_dbg(&gt->i915->drm, "Unexpected fault\n"
 331                         "\tAddr: 0x%08x_%08x\n"
 332                         "\tAddress space: %s\n"
 333                         "\tEngine ID: %d\n"
 334                         "\tSource ID: %d\n"
 335                         "\tType: %d\n",
 336                         upper_32_bits(fault_addr), lower_32_bits(fault_addr),
 337                         fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
 338                         GEN8_RING_FAULT_ENGINE_ID(fault),
 339                         RING_FAULT_SRCID(fault),
 340                         RING_FAULT_FAULT_TYPE(fault));
 341         }
 342 }
 343
 344 static void gen8_check_faults(struct intel_gt *gt)
 345 {
 346         struct intel_uncore *uncore = gt->uncore;
 347         i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
 348         u32 fault;
 349
 350         if (GRAPHICS_VER(gt->i915) >= 12) {
 351                 fault_reg = GEN12_RING_FAULT_REG;
 352                 fault_data0_reg = GEN12_FAULT_TLB_DATA0;
 353                 fault_data1_reg = GEN12_FAULT_TLB_DATA1;
 354         } else {
 355                 fault_reg = GEN8_RING_FAULT_REG;
 356                 fault_data0_reg = GEN8_FAULT_TLB_DATA0;
 357                 fault_data1_reg = GEN8_FAULT_TLB_DATA1;
 358         }
 359
 360         fault = intel_uncore_read(uncore, fault_reg);
 361         if (fault & RING_FAULT_VALID) {
 362                 u32 fault_data0, fault_data1;
 363                 u64 fault_addr;
 364
 365                 fault_data0 = intel_uncore_read(uncore, fault_data0_reg);
 366                 fault_data1 = intel_uncore_read(uncore, fault_data1_reg);
 367
 368                 fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
 369                              ((u64)fault_data0 << 12);
 370
 371                 drm_dbg(&uncore->i915->drm, "Unexpected fault\n"
 372                         "\tAddr: 0x%08x_%08x\n"
 373                         "\tAddress space: %s\n"
 374                         "\tEngine ID: %d\n"
 375                         "\tSource ID: %d\n"
 376                         "\tType: %d\n",
 377                         upper_32_bits(fault_addr), lower_32_bits(fault_addr),
 378                         fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
 379                         GEN8_RING_FAULT_ENGINE_ID(fault),
 380                         RING_FAULT_SRCID(fault),
 381                         RING_FAULT_FAULT_TYPE(fault));
 382         }
 383 }
 384
 385 void intel_gt_check_and_clear_faults(struct intel_gt *gt)
 386 {
 387         struct drm_i915_private *i915 = gt->i915;
 388
 389         /* From GEN8 onwards we only have one 'All Engine Fault Register' */
 390         if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
 391                 xehp_check_faults(gt);
 392         else if (GRAPHICS_VER(i915) >= 8)
 393                 gen8_check_faults(gt);
 394         else if (GRAPHICS_VER(i915) >= 6)
 395                 gen6_check_faults(gt);
 396         else
 397                 return;
 398
 399         intel_gt_clear_error_registers(gt, ALL_ENGINES);
 400 }
 401
 402 void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
 403 {
 404         struct intel_uncore *uncore = gt->uncore;
 405         intel_wakeref_t wakeref;
 406
 407         /*
 408          * No actual flushing is required for the GTT write domain for reads
 409          * from the GTT domain. Writes to it "immediately" go to main memory
 410          * as far as we know, so there's no chipset flush. It also doesn't
 411          * land in the GPU render cache.
 412          *
 413          * However, we do have to enforce the order so that all writes through
 414          * the GTT land before any writes to the device, such as updates to
 415          * the GATT itself.
 416          *
 417          * We also have to wait a bit for the writes to land from the GTT.
 418          * An uncached read (i.e. mmio) seems to be ideal for the round-trip
 419          * timing. This issue has only been observed when switching quickly
 420          * between GTT writes and CPU reads from inside the kernel on recent hw,
 421          * and it appears to only affect discrete GTT blocks (i.e. on LLC
 422          * system agents we cannot reproduce this behaviour, until Cannonlake
 423          * that was!).
 424          */
 425
 426         wmb();
 427
 428         if (INTEL_INFO(gt->i915)->has_coherent_ggtt)
 429                 return;
 430
 431         intel_gt_chipset_flush(gt);
 432
 433         with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) {
 434                 unsigned long flags;
 435
 436                 spin_lock_irqsave(&uncore->lock, flags);
 437                 intel_uncore_posting_read_fw(uncore,
 438                                              RING_HEAD(RENDER_RING_BASE));
 439                 spin_unlock_irqrestore(&uncore->lock, flags);
 440         }
 441 }
 442
 443 void intel_gt_chipset_flush(struct intel_gt *gt)
 444 {
 445         wmb();
 446         if (GRAPHICS_VER(gt->i915) < 6)
 447                 intel_ggtt_gmch_flush();
 448 }
 449
 450 void intel_gt_driver_register(struct intel_gt *gt)
 451 {
 452         intel_gsc_init(&gt->gsc, gt->i915);
 453
 454         intel_rps_driver_register(&gt->rps);
 455
 456         intel_gt_debugfs_register(gt);
 457         intel_gt_sysfs_register(gt);
 458 }
 459
 460 static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
 461 {
 462         struct drm_i915_private *i915 = gt->i915;
 463         struct drm_i915_gem_object *obj;
 464         struct i915_vma *vma;
 465         int ret;
 466
 467         obj = i915_gem_object_create_lmem(i915, size,
 468                                           I915_BO_ALLOC_VOLATILE |
 469                                           I915_BO_ALLOC_GPU_ONLY);
 470         if (IS_ERR(obj))
 471                 obj = i915_gem_object_create_stolen(i915, size);
 472         if (IS_ERR(obj))
 473                 obj = i915_gem_object_create_internal(i915, size);
 474         if (IS_ERR(obj)) {
 475                 drm_err(&i915->drm, "Failed to allocate scratch page\n");
 476                 return PTR_ERR(obj);
 477         }
 478
 479         vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
 480         if (IS_ERR(vma)) {
 481                 ret = PTR_ERR(vma);
 482                 goto err_unref;
 483         }
 484
 485         ret = i915_ggtt_pin(vma, NULL, 0, PIN_HIGH);
 486         if (ret)
 487                 goto err_unref;
 488
 489         gt->scratch = i915_vma_make_unshrinkable(vma);
 490
 491         return 0;
 492
 493 err_unref:
 494         i915_gem_object_put(obj);
 495         return ret;
 496 }
 497
 498 static void intel_gt_fini_scratch(struct intel_gt *gt)
 499 {
 500         i915_vma_unpin_and_release(&gt->scratch, 0);
 501 }
 502
 503 static struct i915_address_space *kernel_vm(struct intel_gt *gt)
 504 {
 505         if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING)
 506                 return &i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY)->vm;
 507         else
 508                 return i915_vm_get(&gt->ggtt->vm);
 509 }
 510
 511 static int __engines_record_defaults(struct intel_gt *gt)
 512 {
 513         struct i915_request *requests[I915_NUM_ENGINES] = {};
 514         struct intel_engine_cs *engine;
 515         enum intel_engine_id id;
 516         int err = 0;
 517
 518         /*
 519          * As we reset the gpu during very early sanitisation, the current
 520          * register state on the GPU should reflect its defaults values.
 521          * We load a context onto the hw (with restore-inhibit), then switch
 522          * over to a second context to save that default register state. We
 523          * can then prime every new context with that state so they all start
 524          * from the same default HW values.
 525          */
 526
 527         for_each_engine(engine, gt, id) {
 528                 struct intel_renderstate so;
 529                 struct intel_context *ce;
 530                 struct i915_request *rq;
 531
 532                 /* We must be able to switch to something! */
 533                 GEM_BUG_ON(!engine->kernel_context);
 534
 535                 ce = intel_context_create(engine);
 536                 if (IS_ERR(ce)) {
 537                         err = PTR_ERR(ce);
 538                         goto out;
 539                 }
 540
 541                 err = intel_renderstate_init(&so, ce);
 542                 if (err)
 543                         goto err;
 544
 545                 rq = i915_request_create(ce);
 546                 if (IS_ERR(rq)) {
 547                         err = PTR_ERR(rq);
 548                         goto err_fini;
 549                 }
 550
 551                 err = intel_engine_emit_ctx_wa(rq);
 552                 if (err)
 553                         goto err_rq;
 554
 555                 err = intel_renderstate_emit(&so, rq);
 556                 if (err)
 557                         goto err_rq;
 558
 559 err_rq:
 560                 requests[id] = i915_request_get(rq);
 561                 i915_request_add(rq);
 562 err_fini:
 563                 intel_renderstate_fini(&so, ce);
 564 err:
 565                 if (err) {
 566                         intel_context_put(ce);
 567                         goto out;
 568                 }
 569         }
 570
 571         /* Flush the default context image to memory, and enable powersaving. */
 572         if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
 573                 err = -EIO;
 574                 goto out;
 575         }
 576
 577         for (id = 0; id < ARRAY_SIZE(requests); id++) {
 578                 struct i915_request *rq;
 579                 struct file *state;
 580
 581                 rq = requests[id];
 582                 if (!rq)
 583                         continue;
 584
 585                 if (rq->fence.error) {
 586                         err = -EIO;
 587                         goto out;
 588                 }
 589
 590                 GEM_BUG_ON(!test_bit(CONTEXT_ALLOC_BIT, &rq->context->flags));
 591                 if (!rq->context->state)
 592                         continue;
 593
 594                 /* Keep a copy of the state's backing pages; free the obj */
 595                 state = shmem_create_from_object(rq->context->state->obj);
 596                 if (IS_ERR(state)) {
 597                         err = PTR_ERR(state);
 598                         goto out;
 599                 }
 600                 rq->engine->default_state = state;
 601         }
 602
 603 out:
 604         /*
 605          * If we have to abandon now, we expect the engines to be idle
 606          * and ready to be torn-down. The quickest way we can accomplish
 607          * this is by declaring ourselves wedged.
 608          */
 609         if (err)
 610                 intel_gt_set_wedged(gt);
 611
 612         for (id = 0; id < ARRAY_SIZE(requests); id++) {
 613                 struct intel_context *ce;
 614                 struct i915_request *rq;
 615
 616                 rq = requests[id];
 617                 if (!rq)
 618                         continue;
 619
 620                 ce = rq->context;
 621                 i915_request_put(rq);
 622                 intel_context_put(ce);
 623         }
 624         return err;
 625 }
 626
 627 static int __engines_verify_workarounds(struct intel_gt *gt)
 628 {
 629         struct intel_engine_cs *engine;
 630         enum intel_engine_id id;
 631         int err = 0;
 632
 633         if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 634                 return 0;
 635
 636         for_each_engine(engine, gt, id) {
 637                 if (intel_engine_verify_workarounds(engine, "load"))
 638                         err = -EIO;
 639         }
 640
 641         /* Flush and restore the kernel context for safety */
 642         if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME)
 643                 err = -EIO;
 644
 645         return err;
 646 }
 647
 648 static void __intel_gt_disable(struct intel_gt *gt)
 649 {
 650         intel_gt_set_wedged_on_fini(gt);
 651
 652         intel_gt_suspend_prepare(gt);
 653         intel_gt_suspend_late(gt);
 654
 655         GEM_BUG_ON(intel_gt_pm_is_awake(gt));
 656 }
 657
 658 int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
 659 {
 660         long remaining_timeout;
 661
 662         /* If the device is asleep, we have no requests outstanding */
 663         if (!intel_gt_pm_is_awake(gt))
 664                 return 0;
 665
 666         while ((timeout = intel_gt_retire_requests_timeout(gt, timeout,
 667                                                            &remaining_timeout)) > 0) {
 668                 cond_resched();
 669                 if (signal_pending(current))
 670                         return -EINTR;
 671         }
 672
 673         if (timeout)
 674                 return timeout;
 675
 676         if (remaining_timeout < 0)
 677                 remaining_timeout = 0;
 678
 679         return intel_uc_wait_for_idle(&gt->uc, remaining_timeout);
 680 }
 681
 682 int intel_gt_init(struct intel_gt *gt)
 683 {
 684         int err;
 685
 686         err = i915_inject_probe_error(gt->i915, -ENODEV);
 687         if (err)
 688                 return err;
 689
 690         intel_gt_init_workarounds(gt);
 691
 692         /*
 693          * This is just a security blanket to placate dragons.
 694          * On some systems, we very sporadically observe that the first TLBs
 695          * used by the CS may be stale, despite us poking the TLB reset. If
 696          * we hold the forcewake during initialisation these problems
 697          * just magically go away.
 698          */
 699         intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
 700
 701         err = intel_gt_init_scratch(gt,
 702                                     GRAPHICS_VER(gt->i915) == 2 ? SZ_256K : SZ_4K);
 703         if (err)
 704                 goto out_fw;
 705
 706         intel_gt_pm_init(gt);
 707
 708         gt->vm = kernel_vm(gt);
 709         if (!gt->vm) {
 710                 err = -ENOMEM;
 711                 goto err_pm;
 712         }
 713
 714         intel_set_mocs_index(gt);
 715
 716         err = intel_engines_init(gt);
 717         if (err)
 718                 goto err_engines;
 719
 720         err = intel_uc_init(&gt->uc);
 721         if (err)
 722                 goto err_engines;
 723
 724         err = intel_gt_resume(gt);
 725         if (err)
 726                 goto err_uc_init;
 727
 728         err = intel_gt_init_hwconfig(gt);
 729         if (err)
 730                 drm_err(&gt->i915->drm, "Failed to retrieve hwconfig table: %pe\n",
 731                         ERR_PTR(err));
 732
 733         err = __engines_record_defaults(gt);
 734         if (err)
 735                 goto err_gt;
 736
 737         err = __engines_verify_workarounds(gt);
 738         if (err)
 739                 goto err_gt;
 740
 741         intel_uc_init_late(&gt->uc);
 742
 743         err = i915_inject_probe_error(gt->i915, -EIO);
 744         if (err)
 745                 goto err_gt;
 746
 747         intel_migrate_init(&gt->migrate, gt);
 748
 749         goto out_fw;
 750 err_gt:
 751         __intel_gt_disable(gt);
 752         intel_uc_fini_hw(&gt->uc);
 753 err_uc_init:
 754         intel_uc_fini(&gt->uc);
 755 err_engines:
 756         intel_engines_release(gt);
 757         i915_vm_put(fetch_and_zero(&gt->vm));
 758 err_pm:
 759         intel_gt_pm_fini(gt);
 760         intel_gt_fini_scratch(gt);
 761 out_fw:
 762         if (err)
 763                 intel_gt_set_wedged_on_init(gt);
 764         intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
 765         return err;
 766 }
 767
 768 void intel_gt_driver_remove(struct intel_gt *gt)
 769 {
 770         __intel_gt_disable(gt);
 771
 772         intel_migrate_fini(&gt->migrate);
 773         intel_uc_driver_remove(&gt->uc);
 774
 775         intel_engines_release(gt);
 776
 777         intel_gt_flush_buffer_pool(gt);
 778 }
 779
 780 void intel_gt_driver_unregister(struct intel_gt *gt)
 781 {
 782         intel_wakeref_t wakeref;
 783
 784         intel_gt_sysfs_unregister(gt);
 785         intel_rps_driver_unregister(&gt->rps);
 786         intel_gsc_fini(&gt->gsc);
 787
 788         /*
 789          * Upon unregistering the device to prevent any new users, cancel
 790          * all in-flight requests so that we can quickly unbind the active
 791          * resources.
 792          */
 793         intel_gt_set_wedged_on_fini(gt);
 794
 795         /* Scrub all HW state upon release */
 796         with_intel_runtime_pm(gt->uncore->rpm, wakeref)
 797                 __intel_gt_reset(gt, ALL_ENGINES);
 798 }
 799
 800 void intel_gt_driver_release(struct intel_gt *gt)
 801 {
 802         struct i915_address_space *vm;
 803
 804         vm = fetch_and_zero(&gt->vm);
 805         if (vm) /* FIXME being called twice on error paths :( */
 806                 i915_vm_put(vm);
 807
 808         intel_wa_list_free(&gt->wa_list);
 809         intel_gt_pm_fini(gt);
 810         intel_gt_fini_scratch(gt);
 811         intel_gt_fini_buffer_pool(gt);
 812         intel_gt_fini_hwconfig(gt);
 813 }
 814
 815 void intel_gt_driver_late_release_all(struct drm_i915_private *i915)
 816 {
 817         struct intel_gt *gt;
 818         unsigned int id;
 819
 820         /* We need to wait for inflight RCU frees to release their grip */
 821         rcu_barrier();
 822
 823         for_each_gt(gt, i915, id) {
 824                 intel_uc_driver_late_release(&gt->uc);
 825                 intel_gt_fini_requests(gt);
 826                 intel_gt_fini_reset(gt);
 827                 intel_gt_fini_timelines(gt);
 828                 mutex_destroy(&gt->tlb.invalidate_lock);
 829                 intel_engines_free(gt);
 830         }
 831 }
 832
 833 static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
 834 {
 835         int ret;
 836
 837         if (!gt_is_root(gt)) {
 838                 struct intel_uncore *uncore;
 839                 spinlock_t *irq_lock;
 840
 841                 uncore = drmm_kzalloc(&gt->i915->drm, sizeof(*uncore), GFP_KERNEL);
 842                 if (!uncore)
 843                         return -ENOMEM;
 844
 845                 irq_lock = drmm_kzalloc(&gt->i915->drm, sizeof(*irq_lock), GFP_KERNEL);
 846                 if (!irq_lock)
 847                         return -ENOMEM;
 848
 849                 gt->uncore = uncore;
 850                 gt->irq_lock = irq_lock;
 851
 852                 intel_gt_common_init_early(gt);
 853         }
 854
 855         intel_uncore_init_early(gt->uncore, gt);
 856
 857         ret = intel_uncore_setup_mmio(gt->uncore, phys_addr);
 858         if (ret)
 859                 return ret;
 860
 861         gt->phys_addr = phys_addr;
 862
 863         return 0;
 864 }
 865
 866 int intel_gt_probe_all(struct drm_i915_private *i915)
 867 {
 868         struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
 869         struct intel_gt *gt = &i915->gt0;
 870         const struct intel_gt_definition *gtdef;
 871         phys_addr_t phys_addr;
 872         unsigned int mmio_bar;
 873         unsigned int i;
 874         int ret;
 875
 876         mmio_bar = intel_mmio_bar(GRAPHICS_VER(i915));
 877         phys_addr = pci_resource_start(pdev, mmio_bar);
 878
 879         /*
 880          * We always have at least one primary GT on any device
 881          * and it has been already initialized early during probe
 882          * in i915_driver_probe()
 883          */
 884         gt->i915 = i915;
 885         gt->name = "Primary GT";
 886         gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
 887
 888         drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
 889         ret = intel_gt_tile_setup(gt, phys_addr);
 890         if (ret)
 891                 return ret;
 892
 893         i915->gt[0] = gt;
 894
 895         if (!HAS_EXTRA_GT_LIST(i915))
 896                 return 0;
 897
 898         for (i = 1, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1];
 899              gtdef->name != NULL;
 900              i++, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1]) {
 901                 gt = drmm_kzalloc(&i915->drm, sizeof(*gt), GFP_KERNEL);
 902                 if (!gt) {
 903                         ret = -ENOMEM;
 904                         goto err;
 905                 }
 906
 907                 gt->i915 = i915;
 908                 gt->name = gtdef->name;
 909                 gt->type = gtdef->type;
 910                 gt->info.engine_mask = gtdef->engine_mask;
 911                 gt->info.id = i;
 912
 913                 drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
 914                 if (GEM_WARN_ON(range_overflows_t(resource_size_t,
 915                                                   gtdef->mapping_base,
 916                                                   SZ_16M,
 917                                                   pci_resource_len(pdev, mmio_bar)))) {
 918                         ret = -ENODEV;
 919                         goto err;
 920                 }
 921
 922                 switch (gtdef->type) {
 923                 case GT_TILE:
 924                         ret = intel_gt_tile_setup(gt, phys_addr + gtdef->mapping_base);
 925                         break;
 926
 927                 case GT_MEDIA:
 928                         ret = intel_sa_mediagt_setup(gt, phys_addr + gtdef->mapping_base,
 929                                                      gtdef->gsi_offset);
 930                         break;
 931
 932                 case GT_PRIMARY:
 933                         /* Primary GT should not appear in extra GT list */
 934                 default:
 935                         MISSING_CASE(gtdef->type);
 936                         ret = -ENODEV;
 937                 }
 938
 939                 if (ret)
 940                         goto err;
 941
 942                 i915->gt[i] = gt;
 943         }
 944
 945         return 0;
 946
 947 err:
 948         i915_probe_error(i915, "Failed to initialize %s! (%d)\n", gtdef->name, ret);
 949         intel_gt_release_all(i915);
 950
 951         return ret;
 952 }
 953
 954 int intel_gt_tiles_init(struct drm_i915_private *i915)
 955 {
 956         struct intel_gt *gt;
 957         unsigned int id;
 958         int ret;
 959
 960         for_each_gt(gt, i915, id) {
 961                 ret = intel_gt_probe_lmem(gt);
 962                 if (ret)
 963                         return ret;
 964         }
 965
 966         return 0;
 967 }
 968
 969 void intel_gt_release_all(struct drm_i915_private *i915)
 970 {
 971         struct intel_gt *gt;
 972         unsigned int id;
 973
 974         for_each_gt(gt, i915, id)
 975                 i915->gt[id] = NULL;
 976 }
 977
 978 void intel_gt_info_print(const struct intel_gt_info *info,
 979                          struct drm_printer *p)
 980 {
 981         drm_printf(p, "available engines: %x\n", info->engine_mask);
 982
 983         intel_sseu_dump(&info->sseu, p);
 984 }
 985
 986 struct reg_and_bit {
 987         union {
 988                 i915_reg_t reg;
 989                 i915_mcr_reg_t mcr_reg;
 990         };
 991         u32 bit;
 992 };
 993
 994 static struct reg_and_bit
 995 get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8,
 996                 const i915_reg_t *regs, const unsigned int num)
 997 {
 998         const unsigned int class = engine->class;
 999         struct reg_and_bit rb = { };
1000
1001         if (drm_WARN_ON_ONCE(&engine->i915->drm,
1002                              class >= num || !regs[class].reg))
1003                 return rb;
1004
1005         rb.reg = regs[class];
1006         if (gen8 && class == VIDEO_DECODE_CLASS)
1007                 rb.reg.reg += 4 * engine->instance; /* GEN8_M2TCR */
1008         else
1009                 rb.bit = engine->instance;
1010
1011         rb.bit = BIT(rb.bit);
1012
1013         return rb;
1014 }
1015
1016 /*
1017  * HW architecture suggest typical invalidation time at 40us,
1018  * with pessimistic cases up to 100us and a recommendation to
1019  * cap at 1ms. We go a bit higher just in case.
1020  */
1021 #define TLB_INVAL_TIMEOUT_US 100
1022 #define TLB_INVAL_TIMEOUT_MS 4
1023
1024 /*
1025  * On Xe_HP the TLB invalidation registers are located at the same MMIO offsets
1026  * but are now considered MCR registers.  Since they exist within a GAM range,
1027  * the primary instance of the register rolls up the status from each unit.
1028  */
1029 static int wait_for_invalidate(struct intel_gt *gt, struct reg_and_bit rb)
1030 {
1031         if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
1032                 return intel_gt_mcr_wait_for_reg(gt, rb.mcr_reg, rb.bit, 0,
1033                                                  TLB_INVAL_TIMEOUT_US,
1034                                                  TLB_INVAL_TIMEOUT_MS);
1035         else
1036                 return __intel_wait_for_register_fw(gt->uncore, rb.reg, rb.bit, 0,
1037                                                     TLB_INVAL_TIMEOUT_US,
1038                                                     TLB_INVAL_TIMEOUT_MS,
1039                                                     NULL);
1040 }
1041
1042 static void mmio_invalidate_full(struct intel_gt *gt)
1043 {
1044         static const i915_reg_t gen8_regs[] = {
1045                 [RENDER_CLASS]                  = GEN8_RTCR,
1046                 [VIDEO_DECODE_CLASS]            = GEN8_M1TCR, /* , GEN8_M2TCR */
1047                 [VIDEO_ENHANCEMENT_CLASS]       = GEN8_VTCR,
1048                 [COPY_ENGINE_CLASS]             = GEN8_BTCR,
1049         };
1050         static const i915_reg_t gen12_regs[] = {
1051                 [RENDER_CLASS]                  = GEN12_GFX_TLB_INV_CR,
1052                 [VIDEO_DECODE_CLASS]            = GEN12_VD_TLB_INV_CR,
1053                 [VIDEO_ENHANCEMENT_CLASS]       = GEN12_VE_TLB_INV_CR,
1054                 [COPY_ENGINE_CLASS]             = GEN12_BLT_TLB_INV_CR,
1055                 [COMPUTE_CLASS]                 = GEN12_COMPCTX_TLB_INV_CR,
1056         };
1057         static const i915_mcr_reg_t xehp_regs[] = {
1058                 [RENDER_CLASS]                  = XEHP_GFX_TLB_INV_CR,
1059                 [VIDEO_DECODE_CLASS]            = XEHP_VD_TLB_INV_CR,
1060                 [VIDEO_ENHANCEMENT_CLASS]       = XEHP_VE_TLB_INV_CR,
1061                 [COPY_ENGINE_CLASS]             = XEHP_BLT_TLB_INV_CR,
1062                 [COMPUTE_CLASS]                 = XEHP_COMPCTX_TLB_INV_CR,
1063         };
1064         struct drm_i915_private *i915 = gt->i915;
1065         struct intel_uncore *uncore = gt->uncore;
1066         struct intel_engine_cs *engine;
1067         intel_engine_mask_t awake, tmp;
1068         enum intel_engine_id id;
1069         const i915_reg_t *regs;
1070         unsigned int num = 0;
1071         unsigned long flags;
1072
1073         if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
1074                 regs = NULL;
1075                 num = ARRAY_SIZE(xehp_regs);
1076         } else if (GRAPHICS_VER(i915) == 12) {
1077                 regs = gen12_regs;
1078                 num = ARRAY_SIZE(gen12_regs);
1079         } else if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) <= 11) {
1080                 regs = gen8_regs;
1081                 num = ARRAY_SIZE(gen8_regs);
1082         } else if (GRAPHICS_VER(i915) < 8) {
1083                 return;
1084         }
1085
1086         if (drm_WARN_ONCE(&i915->drm, !num,
1087                           "Platform does not implement TLB invalidation!"))
1088                 return;
1089
1090         intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
1091
1092         intel_gt_mcr_lock(gt, &flags);
1093         spin_lock(&uncore->lock); /* serialise invalidate with GT reset */
1094
1095         awake = 0;
1096         for_each_engine(engine, gt, id) {
1097                 struct reg_and_bit rb;
1098
1099                 if (!intel_engine_pm_is_awake(engine))
1100                         continue;
1101
1102                 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
1103                         u32 val = BIT(engine->instance);
1104
1105                         if (engine->class == VIDEO_DECODE_CLASS ||
1106                             engine->class == VIDEO_ENHANCEMENT_CLASS ||
1107                             engine->class == COMPUTE_CLASS)
1108                                 val = _MASKED_BIT_ENABLE(val);
1109                         intel_gt_mcr_multicast_write_fw(gt,
1110                                                         xehp_regs[engine->class],
1111                                                         val);
1112                 } else {
1113                         rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
1114                         if (!i915_mmio_reg_offset(rb.reg))
1115                                 continue;
1116
1117                         if (GRAPHICS_VER(i915) == 12 && (engine->class == VIDEO_DECODE_CLASS ||
1118                             engine->class == VIDEO_ENHANCEMENT_CLASS ||
1119                             engine->class == COMPUTE_CLASS))
1120                                 rb.bit = _MASKED_BIT_ENABLE(rb.bit);
1121
1122                         intel_uncore_write_fw(uncore, rb.reg, rb.bit);
1123                 }
1124                 awake |= engine->mask;
1125         }
1126
1127         GT_TRACE(gt, "invalidated engines %08x\n", awake);
1128
1129         /* Wa_2207587034:tgl,dg1,rkl,adl-s,adl-p */
1130         if (awake &&
1131             (IS_TIGERLAKE(i915) ||
1132              IS_DG1(i915) ||
1133              IS_ROCKETLAKE(i915) ||
1134              IS_ALDERLAKE_S(i915) ||
1135              IS_ALDERLAKE_P(i915)))
1136                 intel_uncore_write_fw(uncore, GEN12_OA_TLB_INV_CR, 1);
1137
1138         spin_unlock(&uncore->lock);
1139         intel_gt_mcr_unlock(gt, flags);
1140
1141         for_each_engine_masked(engine, gt, awake, tmp) {
1142                 struct reg_and_bit rb;
1143
1144                 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
1145                         rb.mcr_reg = xehp_regs[engine->class];
1146                         rb.bit = BIT(engine->instance);
1147                 } else {
1148                         rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
1149                 }
1150
1151                 if (wait_for_invalidate(gt, rb))
1152                         drm_err_ratelimited(&gt->i915->drm,
1153                                             "%s TLB invalidation did not complete in %ums!\n",
1154                                             engine->name, TLB_INVAL_TIMEOUT_MS);
1155         }
1156
1157         /*
1158          * Use delayed put since a) we mostly expect a flurry of TLB
1159          * invalidations so it is good to avoid paying the forcewake cost and
1160          * b) it works around a bug in Icelake which cannot cope with too rapid
1161          * transitions.
1162          */
1163         intel_uncore_forcewake_put_delayed(uncore, FORCEWAKE_ALL);
1164 }
1165
1166 static bool tlb_seqno_passed(const struct intel_gt *gt, u32 seqno)
1167 {
1168         u32 cur = intel_gt_tlb_seqno(gt);
1169
1170         /* Only skip if a *full* TLB invalidate barrier has passed */
1171         return (s32)(cur - ALIGN(seqno, 2)) > 0;
1172 }
1173
1174 void intel_gt_invalidate_tlb(struct intel_gt *gt, u32 seqno)
1175 {
1176         intel_wakeref_t wakeref;
1177
1178         if (I915_SELFTEST_ONLY(gt->awake == -ENODEV))
1179                 return;
1180
1181         if (intel_gt_is_wedged(gt))
1182                 return;
1183
1184         if (tlb_seqno_passed(gt, seqno))
1185                 return;
1186
1187         with_intel_gt_pm_if_awake(gt, wakeref) {
1188                 mutex_lock(&gt->tlb.invalidate_lock);
1189                 if (tlb_seqno_passed(gt, seqno))
1190                         goto unlock;
1191
1192                 mmio_invalidate_full(gt);
1193
1194                 write_seqcount_invalidate(&gt->tlb.seqno);
1195 unlock:
1196                 mutex_unlock(&gt->tlb.invalidate_lock);
1197         }
1198 }