drivers/gpu/drm/i915/display/intel_vdsc.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2018 Intel Corporation
   4  *
   5  * Author: Gaurav K Singh <gaurav.k.singh@intel.com>
   6  *         Manasi Navare <manasi.d.navare@intel.com>
   7  */
   8
   9 #include "i915_drv.h"
  10 #include "intel_display_types.h"
  11 #include "intel_dsi.h"
  12 #include "intel_vdsc.h"
  13
  14 enum ROW_INDEX_BPP {
  15         ROW_INDEX_6BPP = 0,
  16         ROW_INDEX_8BPP,
  17         ROW_INDEX_10BPP,
  18         ROW_INDEX_12BPP,
  19         ROW_INDEX_15BPP,
  20         MAX_ROW_INDEX
  21 };
  22
  23 enum COLUMN_INDEX_BPC {
  24         COLUMN_INDEX_8BPC = 0,
  25         COLUMN_INDEX_10BPC,
  26         COLUMN_INDEX_12BPC,
  27         COLUMN_INDEX_14BPC,
  28         COLUMN_INDEX_16BPC,
  29         MAX_COLUMN_INDEX
  30 };
  31
  32 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
  33 static const u16 rc_buf_thresh[] = {
  34         896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
  35         7744, 7872, 8000, 8064
  36 };
  37
  38 struct rc_parameters {
  39         u16 initial_xmit_delay;
  40         u8 first_line_bpg_offset;
  41         u16 initial_offset;
  42         u8 flatness_min_qp;
  43         u8 flatness_max_qp;
  44         u8 rc_quant_incr_limit0;
  45         u8 rc_quant_incr_limit1;
  46         struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
  47 };
  48
  49 /*
  50  * Selected Rate Control Related Parameter Recommended Values
  51  * from DSC_v1.11 spec & C Model release: DSC_model_20161212
  52  */
  53 static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
  54 {
  55         /* 6BPP/8BPC */
  56         { 768, 15, 6144, 3, 13, 11, 11, {
  57                 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
  58                 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
  59                 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
  60                 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
  61                 }
  62         },
  63         /* 6BPP/10BPC */
  64         { 768, 15, 6144, 7, 17, 15, 15, {
  65                 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
  66                 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
  67                 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
  68                 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
  69                 { 17, 18, -12 }
  70                 }
  71         },
  72         /* 6BPP/12BPC */
  73         { 768, 15, 6144, 11, 21, 19, 19, {
  74                 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
  75                 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
  76                 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
  77                 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
  78                 { 21, 22, -12 }
  79                 }
  80         },
  81         /* 6BPP/14BPC */
  82         { 768, 15, 6144, 15, 25, 23, 27, {
  83                 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
  84                 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
  85                 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
  86                 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
  87                 { 25, 26, -12 }
  88                 }
  89         },
  90         /* 6BPP/16BPC */
  91         { 768, 15, 6144, 19, 29, 27, 27, {
  92                 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
  93                 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
  94                 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
  95                 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
  96                 { 29, 30, -12 }
  97                 }
  98         },
  99 },
 100 {
 101         /* 8BPP/8BPC */
 102         { 512, 12, 6144, 3, 12, 11, 11, {
 103                 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
 104                 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
 105                 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
 106                 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
 107                 }
 108         },
 109         /* 8BPP/10BPC */
 110         { 512, 12, 6144, 7, 16, 15, 15, {
 111                 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
 112                 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
 113                 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
 114                 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
 115                 }
 116         },
 117         /* 8BPP/12BPC */
 118         { 512, 12, 6144, 11, 20, 19, 19, {
 119                 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
 120                 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
 121                 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
 122                 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
 123                 { 21, 23, -12 }
 124                 }
 125         },
 126         /* 8BPP/14BPC */
 127         { 512, 12, 6144, 15, 24, 23, 23, {
 128                 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
 129                 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
 130                 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
 131                 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
 132                 { 24, 25, -12 }
 133                 }
 134         },
 135         /* 8BPP/16BPC */
 136         { 512, 12, 6144, 19, 28, 27, 27, {
 137                 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
 138                 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
 139                 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
 140                 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
 141                 { 28, 29, -12 }
 142                 }
 143         },
 144 },
 145 {
 146         /* 10BPP/8BPC */
 147         { 410, 15, 5632, 3, 12, 11, 11, {
 148                 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
 149                 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
 150                 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
 151                 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
 152                 }
 153         },
 154         /* 10BPP/10BPC */
 155         { 410, 15, 5632, 7, 16, 15, 15, {
 156                 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
 157                 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
 158                 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
 159                 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
 160                 }
 161         },
 162         /* 10BPP/12BPC */
 163         { 410, 15, 5632, 11, 20, 19, 19, {
 164                 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
 165                 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
 166                 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
 167                 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
 168                 { 19, 20, -12 }
 169                 }
 170         },
 171         /* 10BPP/14BPC */
 172         { 410, 15, 5632, 15, 24, 23, 23, {
 173                 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
 174                 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
 175                 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
 176                 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
 177                 { 23, 24, -12 }
 178                 }
 179         },
 180         /* 10BPP/16BPC */
 181         { 410, 15, 5632, 19, 28, 27, 27, {
 182                 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
 183                 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
 184                 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
 185                 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
 186                 { 27, 28, -12 }
 187                 }
 188         },
 189 },
 190 {
 191         /* 12BPP/8BPC */
 192         { 341, 15, 2048, 3, 12, 11, 11, {
 193                 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
 194                 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
 195                 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
 196                 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
 197                 }
 198         },
 199         /* 12BPP/10BPC */
 200         { 341, 15, 2048, 7, 16, 15, 15, {
 201                 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
 202                 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
 203                 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
 204                 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
 205                 }
 206         },
 207         /* 12BPP/12BPC */
 208         { 341, 15, 2048, 11, 20, 19, 19, {
 209                 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
 210                 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
 211                 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
 212                 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
 213                 { 21, 23, -12 }
 214                 }
 215         },
 216         /* 12BPP/14BPC */
 217         { 341, 15, 2048, 15, 24, 23, 23, {
 218                 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
 219                 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
 220                 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
 221                 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
 222                 { 22, 23, -12 }
 223                 }
 224         },
 225         /* 12BPP/16BPC */
 226         { 341, 15, 2048, 19, 28, 27, 27, {
 227                 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
 228                 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
 229                 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
 230                 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
 231                 { 26, 27, -12 }
 232                 }
 233         },
 234 },
 235 {
 236         /* 15BPP/8BPC */
 237         { 273, 15, 2048, 3, 12, 11, 11, {
 238                 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
 239                 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
 240                 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
 241                 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
 242                 }
 243         },
 244         /* 15BPP/10BPC */
 245         { 273, 15, 2048, 7, 16, 15, 15, {
 246                 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
 247                 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
 248                 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
 249                 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
 250                 }
 251         },
 252         /* 15BPP/12BPC */
 253         { 273, 15, 2048, 11, 20, 19, 19, {
 254                 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
 255                 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
 256                 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
 257                 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
 258                 { 16, 17, -12 }
 259                 }
 260         },
 261         /* 15BPP/14BPC */
 262         { 273, 15, 2048, 15, 24, 23, 23, {
 263                 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
 264                 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
 265                 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
 266                 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
 267                 { 20, 21, -12 }
 268                 }
 269         },
 270         /* 15BPP/16BPC */
 271         { 273, 15, 2048, 19, 28, 27, 27, {
 272                 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
 273                 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
 274                 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
 275                 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
 276                 { 24, 25, -12 }
 277                 }
 278         }
 279 }
 280
 281 };
 282
 283 static int get_row_index_for_rc_params(u16 compressed_bpp)
 284 {
 285         switch (compressed_bpp) {
 286         case 6:
 287                 return ROW_INDEX_6BPP;
 288         case 8:
 289                 return ROW_INDEX_8BPP;
 290         case 10:
 291                 return ROW_INDEX_10BPP;
 292         case 12:
 293                 return ROW_INDEX_12BPP;
 294         case 15:
 295                 return ROW_INDEX_15BPP;
 296         default:
 297                 return -EINVAL;
 298         }
 299 }
 300
 301 static int get_column_index_for_rc_params(u8 bits_per_component)
 302 {
 303         switch (bits_per_component) {
 304         case 8:
 305                 return COLUMN_INDEX_8BPC;
 306         case 10:
 307                 return COLUMN_INDEX_10BPC;
 308         case 12:
 309                 return COLUMN_INDEX_12BPC;
 310         case 14:
 311                 return COLUMN_INDEX_14BPC;
 312         case 16:
 313                 return COLUMN_INDEX_16BPC;
 314         default:
 315                 return -EINVAL;
 316         }
 317 }
 318
 319 static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
 320                                                  u8 bits_per_component)
 321 {
 322         int row_index, column_index;
 323
 324         row_index = get_row_index_for_rc_params(compressed_bpp);
 325         if (row_index < 0)
 326                 return NULL;
 327
 328         column_index = get_column_index_for_rc_params(bits_per_component);
 329         if (column_index < 0)
 330                 return NULL;
 331
 332         return &rc_parameters[row_index][column_index];
 333 }
 334
 335 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
 336 {
 337         const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 338         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 339         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 340         enum pipe pipe = crtc->pipe;
 341
 342         if (!INTEL_INFO(i915)->display.has_dsc)
 343                 return false;
 344
 345         /* On TGL, DSC is supported on all Pipes */
 346         if (INTEL_GEN(i915) >= 12)
 347                 return true;
 348
 349         if (INTEL_GEN(i915) >= 10 &&
 350             (pipe != PIPE_A ||
 351              (cpu_transcoder == TRANSCODER_EDP ||
 352               cpu_transcoder == TRANSCODER_DSI_0 ||
 353               cpu_transcoder == TRANSCODER_DSI_1)))
 354                 return true;
 355
 356         return false;
 357 }
 358
 359 static bool is_pipe_dsc(const struct intel_crtc_state *crtc_state)
 360 {
 361         const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 362         const struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 363         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 364
 365         if (INTEL_GEN(i915) >= 12)
 366                 return true;
 367
 368         if (cpu_transcoder == TRANSCODER_EDP ||
 369             cpu_transcoder == TRANSCODER_DSI_0 ||
 370             cpu_transcoder == TRANSCODER_DSI_1)
 371                 return false;
 372
 373         /* There's no pipe A DSC engine on ICL */
 374         drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A);
 375
 376         return true;
 377 }
 378
 379 int intel_dsc_compute_params(struct intel_encoder *encoder,
 380                              struct intel_crtc_state *pipe_config)
 381 {
 382         struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
 383         u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
 384         const struct rc_parameters *rc_params;
 385         u8 i = 0;
 386
 387         vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
 388         vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;
 389         vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
 390                                              pipe_config->dsc.slice_count);
 391
 392         /* Gen 11 does not support YCbCr */
 393         vdsc_cfg->simple_422 = false;
 394         /* Gen 11 does not support VBR */
 395         vdsc_cfg->vbr_enable = false;
 396
 397         /* Gen 11 only supports integral values of bpp */
 398         vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
 399         vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
 400
 401         for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
 402                 /*
 403                  * six 0s are appended to the lsb of each threshold value
 404                  * internally in h/w.
 405                  * Only 8 bits are allowed for programming RcBufThreshold
 406                  */
 407                 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
 408         }
 409
 410         /*
 411          * For 6bpp, RC Buffer threshold 12 and 13 need a different value
 412          * as per C Model
 413          */
 414         if (compressed_bpp == 6) {
 415                 vdsc_cfg->rc_buf_thresh[12] = 0x7C;
 416                 vdsc_cfg->rc_buf_thresh[13] = 0x7D;
 417         }
 418
 419         rc_params = get_rc_params(compressed_bpp, vdsc_cfg->bits_per_component);
 420         if (!rc_params)
 421                 return -EINVAL;
 422
 423         vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
 424         vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
 425         vdsc_cfg->initial_offset = rc_params->initial_offset;
 426         vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
 427         vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
 428         vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
 429         vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
 430
 431         for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
 432                 vdsc_cfg->rc_range_params[i].range_min_qp =
 433                         rc_params->rc_range_params[i].range_min_qp;
 434                 vdsc_cfg->rc_range_params[i].range_max_qp =
 435                         rc_params->rc_range_params[i].range_max_qp;
 436                 /*
 437                  * Range BPG Offset uses 2's complement and is only a 6 bits. So
 438                  * mask it to get only 6 bits.
 439                  */
 440                 vdsc_cfg->rc_range_params[i].range_bpg_offset =
 441                         rc_params->rc_range_params[i].range_bpg_offset &
 442                         DSC_RANGE_BPG_OFFSET_MASK;
 443         }
 444
 445         /*
 446          * BitsPerComponent value determines mux_word_size:
 447          * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits
 448          * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to
 449          * 48 bits
 450          */
 451         if (vdsc_cfg->bits_per_component == 8 ||
 452             vdsc_cfg->bits_per_component == 10)
 453                 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
 454         else if (vdsc_cfg->bits_per_component == 12)
 455                 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
 456
 457         /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
 458         vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
 459                 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
 460
 461         return 0;
 462 }
 463
 464 enum intel_display_power_domain
 465 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
 466 {
 467         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 468         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 469         enum pipe pipe = crtc->pipe;
 470
 471         /*
 472          * VDSC/joining uses a separate power well, PW2, and requires
 473          * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases:
 474          *
 475          *  - ICL eDP/DSI transcoder
 476          *  - Gen12+ (except RKL) pipe A
 477          *
 478          * For any other pipe, VDSC/joining uses the power well associated with
 479          * the pipe in use. Hence another reference on the pipe power domain
 480          * will suffice. (Except no VDSC/joining on ICL pipe A.)
 481          */
 482         if (INTEL_GEN(i915) >= 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
 483                 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
 484         else if (is_pipe_dsc(crtc_state))
 485                 return POWER_DOMAIN_PIPE(pipe);
 486         else
 487                 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
 488 }
 489
 490 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 491 {
 492         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 493         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 494         const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
 495         enum pipe pipe = crtc->pipe;
 496         u32 pps_val = 0;
 497         u32 rc_buf_thresh_dword[4];
 498         u32 rc_range_params_dword[8];
 499         u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;
 500         int i = 0;
 501
 502         if (crtc_state->bigjoiner)
 503                 num_vdsc_instances *= 2;
 504
 505         /* Populate PICTURE_PARAMETER_SET_0 registers */
 506         pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
 507                 DSC_VER_MIN_SHIFT |
 508                 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
 509                 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
 510         if (vdsc_cfg->block_pred_enable)
 511                 pps_val |= DSC_BLOCK_PREDICTION;
 512         if (vdsc_cfg->convert_rgb)
 513                 pps_val |= DSC_COLOR_SPACE_CONVERSION;
 514         if (vdsc_cfg->simple_422)
 515                 pps_val |= DSC_422_ENABLE;
 516         if (vdsc_cfg->vbr_enable)
 517                 pps_val |= DSC_VBR_ENABLE;
 518         drm_info(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
 519         if (!is_pipe_dsc(crtc_state)) {
 520                 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0,
 521                                pps_val);
 522                 /*
 523                  * If 2 VDSC instances are needed, configure PPS for second
 524                  * VDSC
 525                  */
 526                 if (crtc_state->dsc.dsc_split)
 527                         intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0,
 528                                        pps_val);
 529         } else {
 530                 intel_de_write(dev_priv,
 531                                ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe),
 532                                pps_val);
 533                 if (crtc_state->dsc.dsc_split)
 534                         intel_de_write(dev_priv,
 535                                        ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
 536                                        pps_val);
 537         }
 538
 539         /* Populate PICTURE_PARAMETER_SET_1 registers */
 540         pps_val = 0;
 541         pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
 542         drm_info(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
 543         if (!is_pipe_dsc(crtc_state)) {
 544                 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1,
 545                                pps_val);
 546                 /*
 547                  * If 2 VDSC instances are needed, configure PPS for second
 548                  * VDSC
 549                  */
 550                 if (crtc_state->dsc.dsc_split)
 551                         intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1,
 552                                        pps_val);
 553         } else {
 554                 intel_de_write(dev_priv,
 555                                ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe),
 556                                pps_val);
 557                 if (crtc_state->dsc.dsc_split)
 558                         intel_de_write(dev_priv,
 559                                        ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
 560                                        pps_val);
 561         }
 562
 563         /* Populate PICTURE_PARAMETER_SET_2 registers */
 564         pps_val = 0;
 565         pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
 566                 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
 567         drm_info(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
 568         if (!is_pipe_dsc(crtc_state)) {
 569                 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2,
 570                                pps_val);
 571                 /*
 572                  * If 2 VDSC instances are needed, configure PPS for second
 573                  * VDSC
 574                  */
 575                 if (crtc_state->dsc.dsc_split)
 576                         intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2,
 577                                        pps_val);
 578         } else {
 579                 intel_de_write(dev_priv,
 580                                ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe),
 581                                pps_val);
 582                 if (crtc_state->dsc.dsc_split)
 583                         intel_de_write(dev_priv,
 584                                        ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
 585                                        pps_val);
 586         }
 587
 588         /* Populate PICTURE_PARAMETER_SET_3 registers */
 589         pps_val = 0;
 590         pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
 591                 DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
 592         drm_info(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
 593         if (!is_pipe_dsc(crtc_state)) {
 594                 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3,
 595                                pps_val);
 596                 /*
 597                  * If 2 VDSC instances are needed, configure PPS for second
 598                  * VDSC
 599                  */
 600                 if (crtc_state->dsc.dsc_split)
 601                         intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3,
 602                                        pps_val);
 603         } else {
 604                 intel_de_write(dev_priv,
 605                                ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe),
 606                                pps_val);
 607                 if (crtc_state->dsc.dsc_split)
 608                         intel_de_write(dev_priv,
 609                                        ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
 610                                        pps_val);
 611         }
 612
 613         /* Populate PICTURE_PARAMETER_SET_4 registers */
 614         pps_val = 0;
 615         pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
 616                 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
 617         drm_info(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
 618         if (!is_pipe_dsc(crtc_state)) {
 619                 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4,
 620                                pps_val);
 621                 /*
 622                  * If 2 VDSC instances are needed, configure PPS for second
 623                  * VDSC
 624                  */
 625                 if (crtc_state->dsc.dsc_split)
 626                         intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4,
 627                                        pps_val);
 628         } else {
 629                 intel_de_write(dev_priv,
 630                                ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe),
 631                                pps_val);
 632                 if (crtc_state->dsc.dsc_split)
 633                         intel_de_write(dev_priv,
 634                                        ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
 635                                        pps_val);
 636         }
 637
 638         /* Populate PICTURE_PARAMETER_SET_5 registers */
 639         pps_val = 0;
 640         pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
 641                 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
 642         drm_info(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
 643         if (!is_pipe_dsc(crtc_state)) {
 644                 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5,
 645                                pps_val);
 646                 /*
 647                  * If 2 VDSC instances are needed, configure PPS for second
 648                  * VDSC
 649                  */
 650                 if (crtc_state->dsc.dsc_split)
 651                         intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5,
 652                                        pps_val);
 653         } else {
 654                 intel_de_write(dev_priv,
 655                                ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe),
 656                                pps_val);
 657                 if (crtc_state->dsc.dsc_split)
 658                         intel_de_write(dev_priv,
 659                                        ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
 660                                        pps_val);
 661         }
 662
 663         /* Populate PICTURE_PARAMETER_SET_6 registers */
 664         pps_val = 0;
 665         pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
 666                 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
 667                 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
 668                 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
 669         drm_info(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
 670         if (!is_pipe_dsc(crtc_state)) {
 671                 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6,
 672                                pps_val);
 673                 /*
 674                  * If 2 VDSC instances are needed, configure PPS for second
 675                  * VDSC
 676                  */
 677                 if (crtc_state->dsc.dsc_split)
 678                         intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6,
 679                                        pps_val);
 680         } else {
 681                 intel_de_write(dev_priv,
 682                                ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe),
 683                                pps_val);
 684                 if (crtc_state->dsc.dsc_split)
 685                         intel_de_write(dev_priv,
 686                                        ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
 687                                        pps_val);
 688         }
 689
 690         /* Populate PICTURE_PARAMETER_SET_7 registers */
 691         pps_val = 0;
 692         pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
 693                 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
 694         drm_info(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
 695         if (!is_pipe_dsc(crtc_state)) {
 696                 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7,
 697                                pps_val);
 698                 /*
 699                  * If 2 VDSC instances are needed, configure PPS for second
 700                  * VDSC
 701                  */
 702                 if (crtc_state->dsc.dsc_split)
 703                         intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7,
 704                                        pps_val);
 705         } else {
 706                 intel_de_write(dev_priv,
 707                                ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe),
 708                                pps_val);
 709                 if (crtc_state->dsc.dsc_split)
 710                         intel_de_write(dev_priv,
 711                                        ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
 712                                        pps_val);
 713         }
 714
 715         /* Populate PICTURE_PARAMETER_SET_8 registers */
 716         pps_val = 0;
 717         pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
 718                 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
 719         drm_info(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
 720         if (!is_pipe_dsc(crtc_state)) {
 721                 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8,
 722                                pps_val);
 723                 /*
 724                  * If 2 VDSC instances are needed, configure PPS for second
 725                  * VDSC
 726                  */
 727                 if (crtc_state->dsc.dsc_split)
 728                         intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8,
 729                                        pps_val);
 730         } else {
 731                 intel_de_write(dev_priv,
 732                                ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe),
 733                                pps_val);
 734                 if (crtc_state->dsc.dsc_split)
 735                         intel_de_write(dev_priv,
 736                                        ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
 737                                        pps_val);
 738         }
 739
 740         /* Populate PICTURE_PARAMETER_SET_9 registers */
 741         pps_val = 0;
 742         pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
 743                 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
 744         drm_info(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
 745         if (!is_pipe_dsc(crtc_state)) {
 746                 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9,
 747                                pps_val);
 748                 /*
 749                  * If 2 VDSC instances are needed, configure PPS for second
 750                  * VDSC
 751                  */
 752                 if (crtc_state->dsc.dsc_split)
 753                         intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9,
 754                                        pps_val);
 755         } else {
 756                 intel_de_write(dev_priv,
 757                                ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe),
 758                                pps_val);
 759                 if (crtc_state->dsc.dsc_split)
 760                         intel_de_write(dev_priv,
 761                                        ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
 762                                        pps_val);
 763         }
 764
 765         /* Populate PICTURE_PARAMETER_SET_10 registers */
 766         pps_val = 0;
 767         pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
 768                 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
 769                 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
 770                 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
 771         drm_info(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
 772         if (!is_pipe_dsc(crtc_state)) {
 773                 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10,
 774                                pps_val);
 775                 /*
 776                  * If 2 VDSC instances are needed, configure PPS for second
 777                  * VDSC
 778                  */
 779                 if (crtc_state->dsc.dsc_split)
 780                         intel_de_write(dev_priv,
 781                                        DSCC_PICTURE_PARAMETER_SET_10, pps_val);
 782         } else {
 783                 intel_de_write(dev_priv,
 784                                ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe),
 785                                pps_val);
 786                 if (crtc_state->dsc.dsc_split)
 787                         intel_de_write(dev_priv,
 788                                        ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
 789                                        pps_val);
 790         }
 791
 792         /* Populate Picture parameter set 16 */
 793         pps_val = 0;
 794         pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
 795                 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
 796                                    vdsc_cfg->slice_width) |
 797                 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
 798                                         vdsc_cfg->slice_height);
 799         drm_info(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
 800         if (!is_pipe_dsc(crtc_state)) {
 801                 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16,
 802                                pps_val);
 803                 /*
 804                  * If 2 VDSC instances are needed, configure PPS for second
 805                  * VDSC
 806                  */
 807                 if (crtc_state->dsc.dsc_split)
 808                         intel_de_write(dev_priv,
 809                                        DSCC_PICTURE_PARAMETER_SET_16, pps_val);
 810         } else {
 811                 intel_de_write(dev_priv,
 812                                ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe),
 813                                pps_val);
 814                 if (crtc_state->dsc.dsc_split)
 815                         intel_de_write(dev_priv,
 816                                        ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
 817                                        pps_val);
 818         }
 819
 820         /* Populate the RC_BUF_THRESH registers */
 821         memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
 822         for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
 823                 rc_buf_thresh_dword[i / 4] |=
 824                         (u32)(vdsc_cfg->rc_buf_thresh[i] <<
 825                               BITS_PER_BYTE * (i % 4));
 826                 drm_info(&dev_priv->drm, " RC_BUF_THRESH%d = 0x%08x\n", i,
 827                          rc_buf_thresh_dword[i / 4]);
 828         }
 829         if (!is_pipe_dsc(crtc_state)) {
 830                 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,
 831                                rc_buf_thresh_dword[0]);
 832                 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW,
 833                                rc_buf_thresh_dword[1]);
 834                 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1,
 835                                rc_buf_thresh_dword[2]);
 836                 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW,
 837                                rc_buf_thresh_dword[3]);
 838                 if (crtc_state->dsc.dsc_split) {
 839                         intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0,
 840                                        rc_buf_thresh_dword[0]);
 841                         intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW,
 842                                        rc_buf_thresh_dword[1]);
 843                         intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1,
 844                                        rc_buf_thresh_dword[2]);
 845                         intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW,
 846                                        rc_buf_thresh_dword[3]);
 847                 }
 848         } else {
 849                 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe),
 850                                rc_buf_thresh_dword[0]);
 851                 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
 852                                rc_buf_thresh_dword[1]);
 853                 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe),
 854                                rc_buf_thresh_dword[2]);
 855                 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
 856                                rc_buf_thresh_dword[3]);
 857                 if (crtc_state->dsc.dsc_split) {
 858                         intel_de_write(dev_priv,
 859                                        ICL_DSC1_RC_BUF_THRESH_0(pipe),
 860                                        rc_buf_thresh_dword[0]);
 861                         intel_de_write(dev_priv,
 862                                        ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
 863                                        rc_buf_thresh_dword[1]);
 864                         intel_de_write(dev_priv,
 865                                        ICL_DSC1_RC_BUF_THRESH_1(pipe),
 866                                        rc_buf_thresh_dword[2]);
 867                         intel_de_write(dev_priv,
 868                                        ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
 869                                        rc_buf_thresh_dword[3]);
 870                 }
 871         }
 872
 873         /* Populate the RC_RANGE_PARAMETERS registers */
 874         memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));
 875         for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
 876                 rc_range_params_dword[i / 2] |=
 877                         (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
 878                                 RC_BPG_OFFSET_SHIFT) |
 879                                (vdsc_cfg->rc_range_params[i].range_max_qp <<
 880                                 RC_MAX_QP_SHIFT) |
 881                                (vdsc_cfg->rc_range_params[i].range_min_qp <<
 882                                 RC_MIN_QP_SHIFT)) << 16 * (i % 2));
 883                 drm_info(&dev_priv->drm, " RC_RANGE_PARAM_%d = 0x%08x\n", i,
 884                          rc_range_params_dword[i / 2]);
 885         }
 886         if (!is_pipe_dsc(crtc_state)) {
 887                 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,
 888                                rc_range_params_dword[0]);
 889                 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW,
 890                                rc_range_params_dword[1]);
 891                 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1,
 892                                rc_range_params_dword[2]);
 893                 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW,
 894                                rc_range_params_dword[3]);
 895                 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2,
 896                                rc_range_params_dword[4]);
 897                 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW,
 898                                rc_range_params_dword[5]);
 899                 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3,
 900                                rc_range_params_dword[6]);
 901                 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW,
 902                                rc_range_params_dword[7]);
 903                 if (crtc_state->dsc.dsc_split) {
 904                         intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0,
 905                                        rc_range_params_dword[0]);
 906                         intel_de_write(dev_priv,
 907                                        DSCC_RC_RANGE_PARAMETERS_0_UDW,
 908                                        rc_range_params_dword[1]);
 909                         intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1,
 910                                        rc_range_params_dword[2]);
 911                         intel_de_write(dev_priv,
 912                                        DSCC_RC_RANGE_PARAMETERS_1_UDW,
 913                                        rc_range_params_dword[3]);
 914                         intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2,
 915                                        rc_range_params_dword[4]);
 916                         intel_de_write(dev_priv,
 917                                        DSCC_RC_RANGE_PARAMETERS_2_UDW,
 918                                        rc_range_params_dword[5]);
 919                         intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3,
 920                                        rc_range_params_dword[6]);
 921                         intel_de_write(dev_priv,
 922                                        DSCC_RC_RANGE_PARAMETERS_3_UDW,
 923                                        rc_range_params_dword[7]);
 924                 }
 925         } else {
 926                 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
 927                                rc_range_params_dword[0]);
 928                 intel_de_write(dev_priv,
 929                                ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
 930                                rc_range_params_dword[1]);
 931                 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
 932                                rc_range_params_dword[2]);
 933                 intel_de_write(dev_priv,
 934                                ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
 935                                rc_range_params_dword[3]);
 936                 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
 937                                rc_range_params_dword[4]);
 938                 intel_de_write(dev_priv,
 939                                ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
 940                                rc_range_params_dword[5]);
 941                 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
 942                                rc_range_params_dword[6]);
 943                 intel_de_write(dev_priv,
 944                                ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
 945                                rc_range_params_dword[7]);
 946                 if (crtc_state->dsc.dsc_split) {
 947                         intel_de_write(dev_priv,
 948                                        ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
 949                                        rc_range_params_dword[0]);
 950                         intel_de_write(dev_priv,
 951                                        ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
 952                                        rc_range_params_dword[1]);
 953                         intel_de_write(dev_priv,
 954                                        ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
 955                                        rc_range_params_dword[2]);
 956                         intel_de_write(dev_priv,
 957                                        ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
 958                                        rc_range_params_dword[3]);
 959                         intel_de_write(dev_priv,
 960                                        ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
 961                                        rc_range_params_dword[4]);
 962                         intel_de_write(dev_priv,
 963                                        ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
 964                                        rc_range_params_dword[5]);
 965                         intel_de_write(dev_priv,
 966                                        ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
 967                                        rc_range_params_dword[6]);
 968                         intel_de_write(dev_priv,
 969                                        ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
 970                                        rc_range_params_dword[7]);
 971                 }
 972         }
 973 }
 974
 975 static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
 976                                     const struct intel_crtc_state *crtc_state)
 977 {
 978         const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
 979         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 980         struct mipi_dsi_device *dsi;
 981         struct drm_dsc_picture_parameter_set pps;
 982         enum port port;
 983
 984         drm_dsc_pps_payload_pack(&pps, vdsc_cfg);
 985
 986         for_each_dsi_port(port, intel_dsi->ports) {
 987                 dsi = intel_dsi->dsi_hosts[port]->device;
 988
 989                 mipi_dsi_picture_parameter_set(dsi, &pps);
 990                 mipi_dsi_compression_mode(dsi, true);
 991         }
 992 }
 993
 994 static void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
 995                                    const struct intel_crtc_state *crtc_state)
 996 {
 997         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 998         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 999         const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1000         struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
1001
1002         /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
1003         drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header);
1004
1005         /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
1006         drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg);
1007
1008         dig_port->write_infoframe(encoder, crtc_state,
1009                                   DP_SDP_PPS, &dp_dsc_pps_sdp,
1010                                   sizeof(dp_dsc_pps_sdp));
1011 }
1012
1013 static i915_reg_t dss_ctl1_reg(const struct intel_crtc_state *crtc_state)
1014 {
1015         enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
1016
1017         return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL1(pipe) : DSS_CTL1;
1018 }
1019
1020 static i915_reg_t dss_ctl2_reg(const struct intel_crtc_state *crtc_state)
1021 {
1022         enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
1023
1024         return is_pipe_dsc(crtc_state) ? ICL_PIPE_DSS_CTL2(pipe) : DSS_CTL2;
1025 }
1026
1027 void intel_dsc_enable(struct intel_encoder *encoder,
1028                       const struct intel_crtc_state *crtc_state)
1029 {
1030         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1031         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1032         u32 dss_ctl1_val = 0;
1033         u32 dss_ctl2_val = 0;
1034
1035         if (!crtc_state->dsc.compression_enable)
1036                 return;
1037
1038         intel_dsc_pps_configure(crtc_state);
1039
1040         if (!crtc_state->bigjoiner_slave) {
1041                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1042                         intel_dsc_dsi_pps_write(encoder, crtc_state);
1043                 else
1044                         intel_dsc_dp_pps_write(encoder, crtc_state);
1045         }
1046
1047         dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
1048         if (crtc_state->dsc.dsc_split) {
1049                 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
1050                 dss_ctl1_val |= JOINER_ENABLE;
1051         }
1052         if (crtc_state->bigjoiner) {
1053                 dss_ctl1_val |= BIG_JOINER_ENABLE;
1054                 if (!crtc_state->bigjoiner_slave)
1055                         dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE;
1056         }
1057         intel_de_write(dev_priv, dss_ctl1_reg(crtc_state), dss_ctl1_val);
1058         intel_de_write(dev_priv, dss_ctl2_reg(crtc_state), dss_ctl2_val);
1059 }
1060
1061 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
1062 {
1063         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1064         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1065
1066         if (!old_crtc_state->dsc.compression_enable)
1067                 return;
1068
1069         intel_de_write(dev_priv, dss_ctl1_reg(old_crtc_state), 0);
1070         intel_de_write(dev_priv, dss_ctl2_reg(old_crtc_state), 0);
1071 }
1072
1073 void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
1074 {
1075         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1076         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1077         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1078         enum pipe pipe = crtc->pipe;
1079         enum intel_display_power_domain power_domain;
1080         intel_wakeref_t wakeref;
1081         u32 dss_ctl1, dss_ctl2, val;
1082
1083         if (!intel_dsc_source_support(crtc_state))
1084                 return;
1085
1086         power_domain = intel_dsc_power_domain(crtc_state);
1087
1088         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1089         if (!wakeref)
1090                 return;
1091
1092         dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc_state));
1093         dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc_state));
1094
1095         crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
1096         if (!crtc_state->dsc.compression_enable)
1097                 goto out;
1098
1099         crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
1100                 (dss_ctl1 & JOINER_ENABLE);
1101
1102         if (dss_ctl1 & BIG_JOINER_ENABLE) {
1103                 crtc_state->bigjoiner = true;
1104
1105                 if (!(dss_ctl1 & MASTER_BIG_JOINER_ENABLE)) {
1106                         crtc_state->bigjoiner_slave = true;
1107                         if (!WARN_ON(crtc->pipe == PIPE_A))
1108                                 crtc_state->bigjoiner_linked_crtc =
1109                                         intel_get_crtc_for_pipe(dev_priv, crtc->pipe - 1);
1110                 } else {
1111                         if (!WARN_ON(INTEL_NUM_PIPES(dev_priv) == crtc->pipe + 1))
1112                                 crtc_state->bigjoiner_linked_crtc =
1113                                         intel_get_crtc_for_pipe(dev_priv, crtc->pipe + 1);
1114                 }
1115         }
1116
1117         /* FIXME: add more state readout as needed */
1118
1119         /* PPS1 */
1120         if (!is_pipe_dsc(crtc_state))
1121                 val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
1122         else
1123                 val = intel_de_read(dev_priv,
1124                                     ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
1125         vdsc_cfg->bits_per_pixel = val;
1126         crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
1127 out:
1128         intel_display_power_put(dev_priv, power_domain, wakeref);
1129 }