Merge drm/drm-next into drm-intel-next-queued
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / display / intel_pipe_crc.c
1 /*
2  * Copyright © 2013 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Author: Damien Lespiau <damien.lespiau@intel.com>
24  *
25  */
26
27 #include <linux/circ_buf.h>
28 #include <linux/ctype.h>
29 #include <linux/debugfs.h>
30 #include <linux/seq_file.h>
31
32 #include "intel_atomic.h"
33 #include "intel_display_types.h"
34 #include "intel_pipe_crc.h"
35
36 static const char * const pipe_crc_sources[] = {
37         [INTEL_PIPE_CRC_SOURCE_NONE] = "none",
38         [INTEL_PIPE_CRC_SOURCE_PLANE1] = "plane1",
39         [INTEL_PIPE_CRC_SOURCE_PLANE2] = "plane2",
40         [INTEL_PIPE_CRC_SOURCE_PLANE3] = "plane3",
41         [INTEL_PIPE_CRC_SOURCE_PLANE4] = "plane4",
42         [INTEL_PIPE_CRC_SOURCE_PLANE5] = "plane5",
43         [INTEL_PIPE_CRC_SOURCE_PLANE6] = "plane6",
44         [INTEL_PIPE_CRC_SOURCE_PLANE7] = "plane7",
45         [INTEL_PIPE_CRC_SOURCE_PIPE] = "pipe",
46         [INTEL_PIPE_CRC_SOURCE_TV] = "TV",
47         [INTEL_PIPE_CRC_SOURCE_DP_B] = "DP-B",
48         [INTEL_PIPE_CRC_SOURCE_DP_C] = "DP-C",
49         [INTEL_PIPE_CRC_SOURCE_DP_D] = "DP-D",
50         [INTEL_PIPE_CRC_SOURCE_AUTO] = "auto",
51 };
52
53 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
54                                  u32 *val)
55 {
56         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
57                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
58
59         switch (*source) {
60         case INTEL_PIPE_CRC_SOURCE_PIPE:
61                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
62                 break;
63         case INTEL_PIPE_CRC_SOURCE_NONE:
64                 *val = 0;
65                 break;
66         default:
67                 return -EINVAL;
68         }
69
70         return 0;
71 }
72
73 static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
74                                      enum pipe pipe,
75                                      enum intel_pipe_crc_source *source)
76 {
77         struct drm_device *dev = &dev_priv->drm;
78         struct intel_encoder *encoder;
79         struct intel_crtc *crtc;
80         struct intel_digital_port *dig_port;
81         int ret = 0;
82
83         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
84
85         drm_modeset_lock_all(dev);
86         for_each_intel_encoder(dev, encoder) {
87                 if (!encoder->base.crtc)
88                         continue;
89
90                 crtc = to_intel_crtc(encoder->base.crtc);
91
92                 if (crtc->pipe != pipe)
93                         continue;
94
95                 switch (encoder->type) {
96                 case INTEL_OUTPUT_TVOUT:
97                         *source = INTEL_PIPE_CRC_SOURCE_TV;
98                         break;
99                 case INTEL_OUTPUT_DP:
100                 case INTEL_OUTPUT_EDP:
101                         dig_port = enc_to_dig_port(encoder);
102                         switch (dig_port->base.port) {
103                         case PORT_B:
104                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
105                                 break;
106                         case PORT_C:
107                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
108                                 break;
109                         case PORT_D:
110                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
111                                 break;
112                         default:
113                                 drm_WARN(dev, 1, "nonexisting DP port %c\n",
114                                          port_name(dig_port->base.port));
115                                 break;
116                         }
117                         break;
118                 default:
119                         break;
120                 }
121         }
122         drm_modeset_unlock_all(dev);
123
124         return ret;
125 }
126
127 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
128                                 enum pipe pipe,
129                                 enum intel_pipe_crc_source *source,
130                                 u32 *val)
131 {
132         bool need_stable_symbols = false;
133
134         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
135                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
136                 if (ret)
137                         return ret;
138         }
139
140         switch (*source) {
141         case INTEL_PIPE_CRC_SOURCE_PIPE:
142                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
143                 break;
144         case INTEL_PIPE_CRC_SOURCE_DP_B:
145                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
146                 need_stable_symbols = true;
147                 break;
148         case INTEL_PIPE_CRC_SOURCE_DP_C:
149                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
150                 need_stable_symbols = true;
151                 break;
152         case INTEL_PIPE_CRC_SOURCE_DP_D:
153                 if (!IS_CHERRYVIEW(dev_priv))
154                         return -EINVAL;
155                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
156                 need_stable_symbols = true;
157                 break;
158         case INTEL_PIPE_CRC_SOURCE_NONE:
159                 *val = 0;
160                 break;
161         default:
162                 return -EINVAL;
163         }
164
165         /*
166          * When the pipe CRC tap point is after the transcoders we need
167          * to tweak symbol-level features to produce a deterministic series of
168          * symbols for a given frame. We need to reset those features only once
169          * a frame (instead of every nth symbol):
170          *   - DC-balance: used to ensure a better clock recovery from the data
171          *     link (SDVO)
172          *   - DisplayPort scrambling: used for EMI reduction
173          */
174         if (need_stable_symbols) {
175                 u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X);
176
177                 tmp |= DC_BALANCE_RESET_VLV;
178                 switch (pipe) {
179                 case PIPE_A:
180                         tmp |= PIPE_A_SCRAMBLE_RESET;
181                         break;
182                 case PIPE_B:
183                         tmp |= PIPE_B_SCRAMBLE_RESET;
184                         break;
185                 case PIPE_C:
186                         tmp |= PIPE_C_SCRAMBLE_RESET;
187                         break;
188                 default:
189                         return -EINVAL;
190                 }
191                 intel_de_write(dev_priv, PORT_DFT2_G4X, tmp);
192         }
193
194         return 0;
195 }
196
197 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
198                                  enum pipe pipe,
199                                  enum intel_pipe_crc_source *source,
200                                  u32 *val)
201 {
202         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
203                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
204                 if (ret)
205                         return ret;
206         }
207
208         switch (*source) {
209         case INTEL_PIPE_CRC_SOURCE_PIPE:
210                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
211                 break;
212         case INTEL_PIPE_CRC_SOURCE_TV:
213                 if (!SUPPORTS_TV(dev_priv))
214                         return -EINVAL;
215                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
216                 break;
217         case INTEL_PIPE_CRC_SOURCE_NONE:
218                 *val = 0;
219                 break;
220         default:
221                 /*
222                  * The DP CRC source doesn't work on g4x.
223                  * It can be made to work to some degree by selecting
224                  * the correct CRC source before the port is enabled,
225                  * and not touching the CRC source bits again until
226                  * the port is disabled. But even then the bits
227                  * eventually get stuck and a reboot is needed to get
228                  * working CRCs on the pipe again. Let's simply
229                  * refuse to use DP CRCs on g4x.
230                  */
231                 return -EINVAL;
232         }
233
234         return 0;
235 }
236
237 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
238                                          enum pipe pipe)
239 {
240         u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X);
241
242         switch (pipe) {
243         case PIPE_A:
244                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
245                 break;
246         case PIPE_B:
247                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
248                 break;
249         case PIPE_C:
250                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
251                 break;
252         default:
253                 return;
254         }
255         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
256                 tmp &= ~DC_BALANCE_RESET_VLV;
257         intel_de_write(dev_priv, PORT_DFT2_G4X, tmp);
258 }
259
260 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
261                                 u32 *val)
262 {
263         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
264                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
265
266         switch (*source) {
267         case INTEL_PIPE_CRC_SOURCE_PLANE1:
268                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
269                 break;
270         case INTEL_PIPE_CRC_SOURCE_PLANE2:
271                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
272                 break;
273         case INTEL_PIPE_CRC_SOURCE_PIPE:
274                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
275                 break;
276         case INTEL_PIPE_CRC_SOURCE_NONE:
277                 *val = 0;
278                 break;
279         default:
280                 return -EINVAL;
281         }
282
283         return 0;
284 }
285
286 static void
287 intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
288 {
289         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
290         struct intel_crtc_state *pipe_config;
291         struct drm_atomic_state *state;
292         struct drm_modeset_acquire_ctx ctx;
293         int ret;
294
295         drm_modeset_acquire_init(&ctx, 0);
296
297         state = drm_atomic_state_alloc(&dev_priv->drm);
298         if (!state) {
299                 ret = -ENOMEM;
300                 goto unlock;
301         }
302
303         state->acquire_ctx = &ctx;
304
305 retry:
306         pipe_config = intel_atomic_get_crtc_state(state, crtc);
307         if (IS_ERR(pipe_config)) {
308                 ret = PTR_ERR(pipe_config);
309                 goto put_state;
310         }
311
312         pipe_config->uapi.mode_changed = pipe_config->has_psr;
313         pipe_config->crc_enabled = enable;
314
315         if (IS_HASWELL(dev_priv) &&
316             pipe_config->hw.active && crtc->pipe == PIPE_A &&
317             pipe_config->cpu_transcoder == TRANSCODER_EDP)
318                 pipe_config->uapi.mode_changed = true;
319
320         ret = drm_atomic_commit(state);
321
322 put_state:
323         if (ret == -EDEADLK) {
324                 drm_atomic_state_clear(state);
325                 drm_modeset_backoff(&ctx);
326                 goto retry;
327         }
328
329         drm_atomic_state_put(state);
330 unlock:
331         drm_WARN(&dev_priv->drm, ret,
332                  "Toggling workaround to %i returns %i\n", enable, ret);
333         drm_modeset_drop_locks(&ctx);
334         drm_modeset_acquire_fini(&ctx);
335 }
336
337 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
338                                 enum pipe pipe,
339                                 enum intel_pipe_crc_source *source,
340                                 u32 *val)
341 {
342         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
343                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
344
345         switch (*source) {
346         case INTEL_PIPE_CRC_SOURCE_PLANE1:
347                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
348                 break;
349         case INTEL_PIPE_CRC_SOURCE_PLANE2:
350                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
351                 break;
352         case INTEL_PIPE_CRC_SOURCE_PIPE:
353                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
354                 break;
355         case INTEL_PIPE_CRC_SOURCE_NONE:
356                 *val = 0;
357                 break;
358         default:
359                 return -EINVAL;
360         }
361
362         return 0;
363 }
364
365 static int skl_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
366                                 enum pipe pipe,
367                                 enum intel_pipe_crc_source *source,
368                                 u32 *val)
369 {
370         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
371                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
372
373         switch (*source) {
374         case INTEL_PIPE_CRC_SOURCE_PLANE1:
375                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_1_SKL;
376                 break;
377         case INTEL_PIPE_CRC_SOURCE_PLANE2:
378                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_2_SKL;
379                 break;
380         case INTEL_PIPE_CRC_SOURCE_PLANE3:
381                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_3_SKL;
382                 break;
383         case INTEL_PIPE_CRC_SOURCE_PLANE4:
384                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_4_SKL;
385                 break;
386         case INTEL_PIPE_CRC_SOURCE_PLANE5:
387                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_5_SKL;
388                 break;
389         case INTEL_PIPE_CRC_SOURCE_PLANE6:
390                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_6_SKL;
391                 break;
392         case INTEL_PIPE_CRC_SOURCE_PLANE7:
393                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_7_SKL;
394                 break;
395         case INTEL_PIPE_CRC_SOURCE_PIPE:
396                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DMUX_SKL;
397                 break;
398         case INTEL_PIPE_CRC_SOURCE_NONE:
399                 *val = 0;
400                 break;
401         default:
402                 return -EINVAL;
403         }
404
405         return 0;
406 }
407
408 static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
409                                enum pipe pipe,
410                                enum intel_pipe_crc_source *source, u32 *val)
411 {
412         if (IS_GEN(dev_priv, 2))
413                 return i8xx_pipe_crc_ctl_reg(source, val);
414         else if (INTEL_GEN(dev_priv) < 5)
415                 return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
416         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
417                 return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
418         else if (IS_GEN_RANGE(dev_priv, 5, 6))
419                 return ilk_pipe_crc_ctl_reg(source, val);
420         else if (INTEL_GEN(dev_priv) < 9)
421                 return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
422         else
423                 return skl_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
424 }
425
426 static int
427 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
428 {
429         int i;
430
431         if (!buf) {
432                 *s = INTEL_PIPE_CRC_SOURCE_NONE;
433                 return 0;
434         }
435
436         i = match_string(pipe_crc_sources, ARRAY_SIZE(pipe_crc_sources), buf);
437         if (i < 0)
438                 return i;
439
440         *s = i;
441         return 0;
442 }
443
444 void intel_display_crc_init(struct drm_i915_private *dev_priv)
445 {
446         enum pipe pipe;
447
448         for_each_pipe(dev_priv, pipe) {
449                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
450
451                 spin_lock_init(&pipe_crc->lock);
452         }
453 }
454
455 static int i8xx_crc_source_valid(struct drm_i915_private *dev_priv,
456                                  const enum intel_pipe_crc_source source)
457 {
458         switch (source) {
459         case INTEL_PIPE_CRC_SOURCE_PIPE:
460         case INTEL_PIPE_CRC_SOURCE_NONE:
461                 return 0;
462         default:
463                 return -EINVAL;
464         }
465 }
466
467 static int i9xx_crc_source_valid(struct drm_i915_private *dev_priv,
468                                  const enum intel_pipe_crc_source source)
469 {
470         switch (source) {
471         case INTEL_PIPE_CRC_SOURCE_PIPE:
472         case INTEL_PIPE_CRC_SOURCE_TV:
473         case INTEL_PIPE_CRC_SOURCE_NONE:
474                 return 0;
475         default:
476                 return -EINVAL;
477         }
478 }
479
480 static int vlv_crc_source_valid(struct drm_i915_private *dev_priv,
481                                 const enum intel_pipe_crc_source source)
482 {
483         switch (source) {
484         case INTEL_PIPE_CRC_SOURCE_PIPE:
485         case INTEL_PIPE_CRC_SOURCE_DP_B:
486         case INTEL_PIPE_CRC_SOURCE_DP_C:
487         case INTEL_PIPE_CRC_SOURCE_DP_D:
488         case INTEL_PIPE_CRC_SOURCE_NONE:
489                 return 0;
490         default:
491                 return -EINVAL;
492         }
493 }
494
495 static int ilk_crc_source_valid(struct drm_i915_private *dev_priv,
496                                 const enum intel_pipe_crc_source source)
497 {
498         switch (source) {
499         case INTEL_PIPE_CRC_SOURCE_PIPE:
500         case INTEL_PIPE_CRC_SOURCE_PLANE1:
501         case INTEL_PIPE_CRC_SOURCE_PLANE2:
502         case INTEL_PIPE_CRC_SOURCE_NONE:
503                 return 0;
504         default:
505                 return -EINVAL;
506         }
507 }
508
509 static int ivb_crc_source_valid(struct drm_i915_private *dev_priv,
510                                 const enum intel_pipe_crc_source source)
511 {
512         switch (source) {
513         case INTEL_PIPE_CRC_SOURCE_PIPE:
514         case INTEL_PIPE_CRC_SOURCE_PLANE1:
515         case INTEL_PIPE_CRC_SOURCE_PLANE2:
516         case INTEL_PIPE_CRC_SOURCE_NONE:
517                 return 0;
518         default:
519                 return -EINVAL;
520         }
521 }
522
523 static int skl_crc_source_valid(struct drm_i915_private *dev_priv,
524                                 const enum intel_pipe_crc_source source)
525 {
526         switch (source) {
527         case INTEL_PIPE_CRC_SOURCE_PIPE:
528         case INTEL_PIPE_CRC_SOURCE_PLANE1:
529         case INTEL_PIPE_CRC_SOURCE_PLANE2:
530         case INTEL_PIPE_CRC_SOURCE_PLANE3:
531         case INTEL_PIPE_CRC_SOURCE_PLANE4:
532         case INTEL_PIPE_CRC_SOURCE_PLANE5:
533         case INTEL_PIPE_CRC_SOURCE_PLANE6:
534         case INTEL_PIPE_CRC_SOURCE_PLANE7:
535         case INTEL_PIPE_CRC_SOURCE_NONE:
536                 return 0;
537         default:
538                 return -EINVAL;
539         }
540 }
541
542 static int
543 intel_is_valid_crc_source(struct drm_i915_private *dev_priv,
544                           const enum intel_pipe_crc_source source)
545 {
546         if (IS_GEN(dev_priv, 2))
547                 return i8xx_crc_source_valid(dev_priv, source);
548         else if (INTEL_GEN(dev_priv) < 5)
549                 return i9xx_crc_source_valid(dev_priv, source);
550         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
551                 return vlv_crc_source_valid(dev_priv, source);
552         else if (IS_GEN_RANGE(dev_priv, 5, 6))
553                 return ilk_crc_source_valid(dev_priv, source);
554         else if (INTEL_GEN(dev_priv) < 9)
555                 return ivb_crc_source_valid(dev_priv, source);
556         else
557                 return skl_crc_source_valid(dev_priv, source);
558 }
559
560 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
561                                               size_t *count)
562 {
563         *count = ARRAY_SIZE(pipe_crc_sources);
564         return pipe_crc_sources;
565 }
566
567 int intel_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
568                                  size_t *values_cnt)
569 {
570         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
571         enum intel_pipe_crc_source source;
572
573         if (display_crc_ctl_parse_source(source_name, &source) < 0) {
574                 drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name);
575                 return -EINVAL;
576         }
577
578         if (source == INTEL_PIPE_CRC_SOURCE_AUTO ||
579             intel_is_valid_crc_source(dev_priv, source) == 0) {
580                 *values_cnt = 5;
581                 return 0;
582         }
583
584         return -EINVAL;
585 }
586
587 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name)
588 {
589         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
590         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
591         enum intel_display_power_domain power_domain;
592         enum intel_pipe_crc_source source;
593         intel_wakeref_t wakeref;
594         u32 val = 0; /* shut up gcc */
595         int ret = 0;
596         bool enable;
597
598         if (display_crc_ctl_parse_source(source_name, &source) < 0) {
599                 drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name);
600                 return -EINVAL;
601         }
602
603         power_domain = POWER_DOMAIN_PIPE(crtc->index);
604         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
605         if (!wakeref) {
606                 drm_dbg_kms(&dev_priv->drm,
607                             "Trying to capture CRC while pipe is off\n");
608                 return -EIO;
609         }
610
611         enable = source != INTEL_PIPE_CRC_SOURCE_NONE;
612         if (enable)
613                 intel_crtc_crc_setup_workarounds(to_intel_crtc(crtc), true);
614
615         ret = get_new_crc_ctl_reg(dev_priv, crtc->index, &source, &val);
616         if (ret != 0)
617                 goto out;
618
619         pipe_crc->source = source;
620         intel_de_write(dev_priv, PIPE_CRC_CTL(crtc->index), val);
621         intel_de_posting_read(dev_priv, PIPE_CRC_CTL(crtc->index));
622
623         if (!source) {
624                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
625                         vlv_undo_pipe_scramble_reset(dev_priv, crtc->index);
626         }
627
628         pipe_crc->skipped = 0;
629
630 out:
631         if (!enable)
632                 intel_crtc_crc_setup_workarounds(to_intel_crtc(crtc), false);
633
634         intel_display_power_put(dev_priv, power_domain, wakeref);
635
636         return ret;
637 }
638
639 void intel_crtc_enable_pipe_crc(struct intel_crtc *intel_crtc)
640 {
641         struct drm_crtc *crtc = &intel_crtc->base;
642         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
643         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
644         u32 val = 0;
645
646         if (!crtc->crc.opened)
647                 return;
648
649         if (get_new_crc_ctl_reg(dev_priv, crtc->index, &pipe_crc->source, &val) < 0)
650                 return;
651
652         /* Don't need pipe_crc->lock here, IRQs are not generated. */
653         pipe_crc->skipped = 0;
654
655         intel_de_write(dev_priv, PIPE_CRC_CTL(crtc->index), val);
656         intel_de_posting_read(dev_priv, PIPE_CRC_CTL(crtc->index));
657 }
658
659 void intel_crtc_disable_pipe_crc(struct intel_crtc *intel_crtc)
660 {
661         struct drm_crtc *crtc = &intel_crtc->base;
662         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
663         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
664
665         /* Swallow crc's until we stop generating them. */
666         spin_lock_irq(&pipe_crc->lock);
667         pipe_crc->skipped = INT_MIN;
668         spin_unlock_irq(&pipe_crc->lock);
669
670         intel_de_write(dev_priv, PIPE_CRC_CTL(crtc->index), 0);
671         intel_de_posting_read(dev_priv, PIPE_CRC_CTL(crtc->index));
672         intel_synchronize_irq(dev_priv);
673 }