2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/delay.h>
30 #include <linux/hdmi.h>
31 #include <linux/i2c.h>
32 #include <linux/slab.h>
33 #include <linux/string_helpers.h>
35 #include <drm/display/drm_hdcp_helper.h>
36 #include <drm/display/drm_hdmi_helper.h>
37 #include <drm/display/drm_scdc_helper.h>
38 #include <drm/drm_atomic_helper.h>
39 #include <drm/drm_crtc.h>
40 #include <drm/drm_edid.h>
41 #include <drm/intel_lpe_audio.h>
46 #include "intel_atomic.h"
47 #include "intel_audio.h"
48 #include "intel_connector.h"
49 #include "intel_cx0_phy.h"
50 #include "intel_ddi.h"
52 #include "intel_display_types.h"
54 #include "intel_gmbus.h"
55 #include "intel_hdcp.h"
56 #include "intel_hdcp_regs.h"
57 #include "intel_hdmi.h"
58 #include "intel_lspcon.h"
59 #include "intel_panel.h"
60 #include "intel_snps_phy.h"
62 inline struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi)
64 return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev);
68 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
70 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(intel_hdmi);
73 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
75 drm_WARN(&dev_priv->drm,
76 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits,
77 "HDMI port enabled, expecting disabled\n");
81 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
82 enum transcoder cpu_transcoder)
84 drm_WARN(&dev_priv->drm,
85 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
86 TRANS_DDI_FUNC_ENABLE,
87 "HDMI transcoder function enabled, expecting disabled\n");
90 static u32 g4x_infoframe_index(unsigned int type)
93 case HDMI_PACKET_TYPE_GAMUT_METADATA:
94 return VIDEO_DIP_SELECT_GAMUT;
95 case HDMI_INFOFRAME_TYPE_AVI:
96 return VIDEO_DIP_SELECT_AVI;
97 case HDMI_INFOFRAME_TYPE_SPD:
98 return VIDEO_DIP_SELECT_SPD;
99 case HDMI_INFOFRAME_TYPE_VENDOR:
100 return VIDEO_DIP_SELECT_VENDOR;
107 static u32 g4x_infoframe_enable(unsigned int type)
110 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
111 return VIDEO_DIP_ENABLE_GCP;
112 case HDMI_PACKET_TYPE_GAMUT_METADATA:
113 return VIDEO_DIP_ENABLE_GAMUT;
116 case HDMI_INFOFRAME_TYPE_AVI:
117 return VIDEO_DIP_ENABLE_AVI;
118 case HDMI_INFOFRAME_TYPE_SPD:
119 return VIDEO_DIP_ENABLE_SPD;
120 case HDMI_INFOFRAME_TYPE_VENDOR:
121 return VIDEO_DIP_ENABLE_VENDOR;
122 case HDMI_INFOFRAME_TYPE_DRM:
130 static u32 hsw_infoframe_enable(unsigned int type)
133 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
134 return VIDEO_DIP_ENABLE_GCP_HSW;
135 case HDMI_PACKET_TYPE_GAMUT_METADATA:
136 return VIDEO_DIP_ENABLE_GMP_HSW;
138 return VIDEO_DIP_ENABLE_VSC_HSW;
140 return VDIP_ENABLE_PPS;
141 case HDMI_INFOFRAME_TYPE_AVI:
142 return VIDEO_DIP_ENABLE_AVI_HSW;
143 case HDMI_INFOFRAME_TYPE_SPD:
144 return VIDEO_DIP_ENABLE_SPD_HSW;
145 case HDMI_INFOFRAME_TYPE_VENDOR:
146 return VIDEO_DIP_ENABLE_VS_HSW;
147 case HDMI_INFOFRAME_TYPE_DRM:
148 return VIDEO_DIP_ENABLE_DRM_GLK;
156 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
157 enum transcoder cpu_transcoder,
162 case HDMI_PACKET_TYPE_GAMUT_METADATA:
163 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
165 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
167 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
168 case HDMI_INFOFRAME_TYPE_AVI:
169 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
170 case HDMI_INFOFRAME_TYPE_SPD:
171 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
172 case HDMI_INFOFRAME_TYPE_VENDOR:
173 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
174 case HDMI_INFOFRAME_TYPE_DRM:
175 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
178 return INVALID_MMIO_REG;
182 static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
187 return VIDEO_DIP_VSC_DATA_SIZE;
189 return VIDEO_DIP_PPS_DATA_SIZE;
190 case HDMI_PACKET_TYPE_GAMUT_METADATA:
191 if (DISPLAY_VER(dev_priv) >= 11)
192 return VIDEO_DIP_GMP_DATA_SIZE;
194 return VIDEO_DIP_DATA_SIZE;
196 return VIDEO_DIP_DATA_SIZE;
200 static void g4x_write_infoframe(struct intel_encoder *encoder,
201 const struct intel_crtc_state *crtc_state,
203 const void *frame, ssize_t len)
205 const u32 *data = frame;
206 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
207 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
210 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
211 "Writing DIP with CTL reg disabled\n");
213 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
214 val |= g4x_infoframe_index(type);
216 val &= ~g4x_infoframe_enable(type);
218 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
220 for (i = 0; i < len; i += 4) {
221 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data);
224 /* Write every possible data byte to force correct ECC calculation. */
225 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
226 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0);
228 val |= g4x_infoframe_enable(type);
229 val &= ~VIDEO_DIP_FREQ_MASK;
230 val |= VIDEO_DIP_FREQ_VSYNC;
232 intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
233 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL);
236 static void g4x_read_infoframe(struct intel_encoder *encoder,
237 const struct intel_crtc_state *crtc_state,
239 void *frame, ssize_t len)
241 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
245 intel_de_rmw(dev_priv, VIDEO_DIP_CTL,
246 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));
248 for (i = 0; i < len; i += 4)
249 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA);
252 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
253 const struct intel_crtc_state *pipe_config)
255 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
256 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
258 if ((val & VIDEO_DIP_ENABLE) == 0)
261 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
264 return val & (VIDEO_DIP_ENABLE_AVI |
265 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
268 static void ibx_write_infoframe(struct intel_encoder *encoder,
269 const struct intel_crtc_state *crtc_state,
271 const void *frame, ssize_t len)
273 const u32 *data = frame;
274 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
275 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
276 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
277 u32 val = intel_de_read(dev_priv, reg);
280 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
281 "Writing DIP with CTL reg disabled\n");
283 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
284 val |= g4x_infoframe_index(type);
286 val &= ~g4x_infoframe_enable(type);
288 intel_de_write(dev_priv, reg, val);
290 for (i = 0; i < len; i += 4) {
291 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
295 /* Write every possible data byte to force correct ECC calculation. */
296 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
297 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
299 val |= g4x_infoframe_enable(type);
300 val &= ~VIDEO_DIP_FREQ_MASK;
301 val |= VIDEO_DIP_FREQ_VSYNC;
303 intel_de_write(dev_priv, reg, val);
304 intel_de_posting_read(dev_priv, reg);
307 static void ibx_read_infoframe(struct intel_encoder *encoder,
308 const struct intel_crtc_state *crtc_state,
310 void *frame, ssize_t len)
312 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
313 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
317 intel_de_rmw(dev_priv, TVIDEO_DIP_CTL(crtc->pipe),
318 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));
320 for (i = 0; i < len; i += 4)
321 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
324 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
325 const struct intel_crtc_state *pipe_config)
327 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
328 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
329 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
330 u32 val = intel_de_read(dev_priv, reg);
332 if ((val & VIDEO_DIP_ENABLE) == 0)
335 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
338 return val & (VIDEO_DIP_ENABLE_AVI |
339 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
340 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
343 static void cpt_write_infoframe(struct intel_encoder *encoder,
344 const struct intel_crtc_state *crtc_state,
346 const void *frame, ssize_t len)
348 const u32 *data = frame;
349 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
350 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
351 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
352 u32 val = intel_de_read(dev_priv, reg);
355 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
356 "Writing DIP with CTL reg disabled\n");
358 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
359 val |= g4x_infoframe_index(type);
361 /* The DIP control register spec says that we need to update the AVI
362 * infoframe without clearing its enable bit */
363 if (type != HDMI_INFOFRAME_TYPE_AVI)
364 val &= ~g4x_infoframe_enable(type);
366 intel_de_write(dev_priv, reg, val);
368 for (i = 0; i < len; i += 4) {
369 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
373 /* Write every possible data byte to force correct ECC calculation. */
374 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
375 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
377 val |= g4x_infoframe_enable(type);
378 val &= ~VIDEO_DIP_FREQ_MASK;
379 val |= VIDEO_DIP_FREQ_VSYNC;
381 intel_de_write(dev_priv, reg, val);
382 intel_de_posting_read(dev_priv, reg);
385 static void cpt_read_infoframe(struct intel_encoder *encoder,
386 const struct intel_crtc_state *crtc_state,
388 void *frame, ssize_t len)
390 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
391 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
395 intel_de_rmw(dev_priv, TVIDEO_DIP_CTL(crtc->pipe),
396 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));
398 for (i = 0; i < len; i += 4)
399 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
402 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
403 const struct intel_crtc_state *pipe_config)
405 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
406 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
407 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe));
409 if ((val & VIDEO_DIP_ENABLE) == 0)
412 return val & (VIDEO_DIP_ENABLE_AVI |
413 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
414 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
417 static void vlv_write_infoframe(struct intel_encoder *encoder,
418 const struct intel_crtc_state *crtc_state,
420 const void *frame, ssize_t len)
422 const u32 *data = frame;
423 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
424 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
425 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
426 u32 val = intel_de_read(dev_priv, reg);
429 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
430 "Writing DIP with CTL reg disabled\n");
432 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
433 val |= g4x_infoframe_index(type);
435 val &= ~g4x_infoframe_enable(type);
437 intel_de_write(dev_priv, reg, val);
439 for (i = 0; i < len; i += 4) {
440 intel_de_write(dev_priv,
441 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data);
444 /* Write every possible data byte to force correct ECC calculation. */
445 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
446 intel_de_write(dev_priv,
447 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0);
449 val |= g4x_infoframe_enable(type);
450 val &= ~VIDEO_DIP_FREQ_MASK;
451 val |= VIDEO_DIP_FREQ_VSYNC;
453 intel_de_write(dev_priv, reg, val);
454 intel_de_posting_read(dev_priv, reg);
457 static void vlv_read_infoframe(struct intel_encoder *encoder,
458 const struct intel_crtc_state *crtc_state,
460 void *frame, ssize_t len)
462 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
463 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
467 intel_de_rmw(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe),
468 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));
470 for (i = 0; i < len; i += 4)
471 *data++ = intel_de_read(dev_priv,
472 VLV_TVIDEO_DIP_DATA(crtc->pipe));
475 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
476 const struct intel_crtc_state *pipe_config)
478 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
479 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
480 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe));
482 if ((val & VIDEO_DIP_ENABLE) == 0)
485 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
488 return val & (VIDEO_DIP_ENABLE_AVI |
489 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
490 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
493 void hsw_write_infoframe(struct intel_encoder *encoder,
494 const struct intel_crtc_state *crtc_state,
496 const void *frame, ssize_t len)
498 const u32 *data = frame;
499 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
500 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
501 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
504 u32 val = intel_de_read(dev_priv, ctl_reg);
506 data_size = hsw_dip_data_size(dev_priv, type);
508 drm_WARN_ON(&dev_priv->drm, len > data_size);
510 val &= ~hsw_infoframe_enable(type);
511 intel_de_write(dev_priv, ctl_reg, val);
513 for (i = 0; i < len; i += 4) {
514 intel_de_write(dev_priv,
515 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
519 /* Write every possible data byte to force correct ECC calculation. */
520 for (; i < data_size; i += 4)
521 intel_de_write(dev_priv,
522 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
526 if (IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr && type == DP_SDP_VSC)
529 val |= hsw_infoframe_enable(type);
530 intel_de_write(dev_priv, ctl_reg, val);
531 intel_de_posting_read(dev_priv, ctl_reg);
534 void hsw_read_infoframe(struct intel_encoder *encoder,
535 const struct intel_crtc_state *crtc_state,
536 unsigned int type, void *frame, ssize_t len)
538 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
539 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
543 for (i = 0; i < len; i += 4)
544 *data++ = intel_de_read(dev_priv,
545 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2));
548 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
549 const struct intel_crtc_state *pipe_config)
551 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
552 u32 val = intel_de_read(dev_priv,
553 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
556 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
557 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
558 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
560 if (DISPLAY_VER(dev_priv) >= 10)
561 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
566 static const u8 infoframe_type_to_idx[] = {
567 HDMI_PACKET_TYPE_GENERAL_CONTROL,
568 HDMI_PACKET_TYPE_GAMUT_METADATA,
570 HDMI_INFOFRAME_TYPE_AVI,
571 HDMI_INFOFRAME_TYPE_SPD,
572 HDMI_INFOFRAME_TYPE_VENDOR,
573 HDMI_INFOFRAME_TYPE_DRM,
576 u32 intel_hdmi_infoframe_enable(unsigned int type)
580 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
581 if (infoframe_type_to_idx[i] == type)
588 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
589 const struct intel_crtc_state *crtc_state)
591 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
592 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
596 val = dig_port->infoframes_enabled(encoder, crtc_state);
598 /* map from hardware bits to dip idx */
599 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
600 unsigned int type = infoframe_type_to_idx[i];
602 if (HAS_DDI(dev_priv)) {
603 if (val & hsw_infoframe_enable(type))
606 if (val & g4x_infoframe_enable(type))
615 * The data we write to the DIP data buffer registers is 1 byte bigger than the
616 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
617 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
618 * used for both technologies.
620 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
621 * DW1: DB3 | DB2 | DB1 | DB0
622 * DW2: DB7 | DB6 | DB5 | DB4
625 * (HB is Header Byte, DB is Data Byte)
627 * The hdmi pack() functions don't know about that hardware specific hole so we
628 * trick them by giving an offset into the buffer and moving back the header
631 static void intel_write_infoframe(struct intel_encoder *encoder,
632 const struct intel_crtc_state *crtc_state,
633 enum hdmi_infoframe_type type,
634 const union hdmi_infoframe *frame)
636 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
637 u8 buffer[VIDEO_DIP_DATA_SIZE];
640 if ((crtc_state->infoframes.enable &
641 intel_hdmi_infoframe_enable(type)) == 0)
644 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
647 /* see comment above for the reason for this offset */
648 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
649 if (drm_WARN_ON(encoder->base.dev, len < 0))
652 /* Insert the 'hole' (see big comment above) at position 3 */
653 memmove(&buffer[0], &buffer[1], 3);
657 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
660 void intel_read_infoframe(struct intel_encoder *encoder,
661 const struct intel_crtc_state *crtc_state,
662 enum hdmi_infoframe_type type,
663 union hdmi_infoframe *frame)
665 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
666 u8 buffer[VIDEO_DIP_DATA_SIZE];
669 if ((crtc_state->infoframes.enable &
670 intel_hdmi_infoframe_enable(type)) == 0)
673 dig_port->read_infoframe(encoder, crtc_state,
674 type, buffer, sizeof(buffer));
676 /* Fill the 'hole' (see big comment above) at position 3 */
677 memmove(&buffer[1], &buffer[0], 3);
679 /* see comment above for the reason for this offset */
680 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
682 drm_dbg_kms(encoder->base.dev,
683 "Failed to unpack infoframe type 0x%02x\n", type);
687 if (frame->any.type != type)
688 drm_dbg_kms(encoder->base.dev,
689 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
690 frame->any.type, type);
694 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
695 struct intel_crtc_state *crtc_state,
696 struct drm_connector_state *conn_state)
698 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
699 const struct drm_display_mode *adjusted_mode =
700 &crtc_state->hw.adjusted_mode;
701 struct drm_connector *connector = conn_state->connector;
704 if (!crtc_state->has_infoframe)
707 crtc_state->infoframes.enable |=
708 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
710 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
715 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
716 frame->colorspace = HDMI_COLORSPACE_YUV420;
717 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
718 frame->colorspace = HDMI_COLORSPACE_YUV444;
720 frame->colorspace = HDMI_COLORSPACE_RGB;
722 drm_hdmi_avi_infoframe_colorimetry(frame, conn_state);
724 /* nonsense combination */
725 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
726 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
728 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
729 drm_hdmi_avi_infoframe_quant_range(frame, connector,
731 crtc_state->limited_color_range ?
732 HDMI_QUANTIZATION_RANGE_LIMITED :
733 HDMI_QUANTIZATION_RANGE_FULL);
735 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
736 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
739 drm_hdmi_avi_infoframe_content_type(frame, conn_state);
741 /* TODO: handle pixel repetition for YCBCR420 outputs */
743 ret = hdmi_avi_infoframe_check(frame);
744 if (drm_WARN_ON(encoder->base.dev, ret))
751 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
752 struct intel_crtc_state *crtc_state,
753 struct drm_connector_state *conn_state)
755 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
756 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
759 if (!crtc_state->has_infoframe)
762 crtc_state->infoframes.enable |=
763 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
766 ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx");
768 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
770 if (drm_WARN_ON(encoder->base.dev, ret))
773 frame->sdi = HDMI_SPD_SDI_PC;
775 ret = hdmi_spd_infoframe_check(frame);
776 if (drm_WARN_ON(encoder->base.dev, ret))
783 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
784 struct intel_crtc_state *crtc_state,
785 struct drm_connector_state *conn_state)
787 struct hdmi_vendor_infoframe *frame =
788 &crtc_state->infoframes.hdmi.vendor.hdmi;
789 const struct drm_display_info *info =
790 &conn_state->connector->display_info;
793 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
796 crtc_state->infoframes.enable |=
797 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
799 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
800 conn_state->connector,
801 &crtc_state->hw.adjusted_mode);
802 if (drm_WARN_ON(encoder->base.dev, ret))
805 ret = hdmi_vendor_infoframe_check(frame);
806 if (drm_WARN_ON(encoder->base.dev, ret))
813 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
814 struct intel_crtc_state *crtc_state,
815 struct drm_connector_state *conn_state)
817 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
818 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
821 if (DISPLAY_VER(dev_priv) < 10)
824 if (!crtc_state->has_infoframe)
827 if (!conn_state->hdr_output_metadata)
830 crtc_state->infoframes.enable |=
831 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
833 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
835 drm_dbg_kms(&dev_priv->drm,
836 "couldn't set HDR metadata in infoframe\n");
840 ret = hdmi_drm_infoframe_check(frame);
841 if (drm_WARN_ON(&dev_priv->drm, ret))
847 static void g4x_set_infoframes(struct intel_encoder *encoder,
849 const struct intel_crtc_state *crtc_state,
850 const struct drm_connector_state *conn_state)
852 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
853 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
854 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
855 i915_reg_t reg = VIDEO_DIP_CTL;
856 u32 val = intel_de_read(dev_priv, reg);
857 u32 port = VIDEO_DIP_PORT(encoder->port);
859 assert_hdmi_port_disabled(intel_hdmi);
861 /* If the registers were not initialized yet, they might be zeroes,
862 * which means we're selecting the AVI DIP and we're setting its
863 * frequency to once. This seems to really confuse the HW and make
864 * things stop working (the register spec says the AVI always needs to
865 * be sent every VSync). So here we avoid writing to the register more
866 * than we need and also explicitly select the AVI DIP and explicitly
867 * set its frequency to every VSync. Avoiding to write it twice seems to
868 * be enough to solve the problem, but being defensive shouldn't hurt us
870 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
873 if (!(val & VIDEO_DIP_ENABLE))
875 if (port != (val & VIDEO_DIP_PORT_MASK)) {
876 drm_dbg_kms(&dev_priv->drm,
877 "video DIP still enabled on port %c\n",
878 (val & VIDEO_DIP_PORT_MASK) >> 29);
881 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
882 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
883 intel_de_write(dev_priv, reg, val);
884 intel_de_posting_read(dev_priv, reg);
888 if (port != (val & VIDEO_DIP_PORT_MASK)) {
889 if (val & VIDEO_DIP_ENABLE) {
890 drm_dbg_kms(&dev_priv->drm,
891 "video DIP already enabled on port %c\n",
892 (val & VIDEO_DIP_PORT_MASK) >> 29);
895 val &= ~VIDEO_DIP_PORT_MASK;
899 val |= VIDEO_DIP_ENABLE;
900 val &= ~(VIDEO_DIP_ENABLE_AVI |
901 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
903 intel_de_write(dev_priv, reg, val);
904 intel_de_posting_read(dev_priv, reg);
906 intel_write_infoframe(encoder, crtc_state,
907 HDMI_INFOFRAME_TYPE_AVI,
908 &crtc_state->infoframes.avi);
909 intel_write_infoframe(encoder, crtc_state,
910 HDMI_INFOFRAME_TYPE_SPD,
911 &crtc_state->infoframes.spd);
912 intel_write_infoframe(encoder, crtc_state,
913 HDMI_INFOFRAME_TYPE_VENDOR,
914 &crtc_state->infoframes.hdmi);
918 * Determine if default_phase=1 can be indicated in the GCP infoframe.
920 * From HDMI specification 1.4a:
921 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
922 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
923 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
924 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
927 static bool gcp_default_phase_possible(int pipe_bpp,
928 const struct drm_display_mode *mode)
930 unsigned int pixels_per_group;
934 /* 4 pixels in 5 clocks */
935 pixels_per_group = 4;
938 /* 2 pixels in 3 clocks */
939 pixels_per_group = 2;
942 /* 1 pixel in 2 clocks */
943 pixels_per_group = 1;
946 /* phase information not relevant for 8bpc */
950 return mode->crtc_hdisplay % pixels_per_group == 0 &&
951 mode->crtc_htotal % pixels_per_group == 0 &&
952 mode->crtc_hblank_start % pixels_per_group == 0 &&
953 mode->crtc_hblank_end % pixels_per_group == 0 &&
954 mode->crtc_hsync_start % pixels_per_group == 0 &&
955 mode->crtc_hsync_end % pixels_per_group == 0 &&
956 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
957 mode->crtc_htotal/2 % pixels_per_group == 0);
960 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
961 const struct intel_crtc_state *crtc_state,
962 const struct drm_connector_state *conn_state)
964 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
965 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
968 if ((crtc_state->infoframes.enable &
969 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
972 if (HAS_DDI(dev_priv))
973 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
974 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
975 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
976 else if (HAS_PCH_SPLIT(dev_priv))
977 reg = TVIDEO_DIP_GCP(crtc->pipe);
981 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp);
986 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
987 struct intel_crtc_state *crtc_state)
989 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
990 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
993 if ((crtc_state->infoframes.enable &
994 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
997 if (HAS_DDI(dev_priv))
998 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
999 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1000 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1001 else if (HAS_PCH_SPLIT(dev_priv))
1002 reg = TVIDEO_DIP_GCP(crtc->pipe);
1006 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg);
1009 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1010 struct intel_crtc_state *crtc_state,
1011 struct drm_connector_state *conn_state)
1013 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1015 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1018 crtc_state->infoframes.enable |=
1019 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1021 /* Indicate color indication for deep color mode */
1022 if (crtc_state->pipe_bpp > 24)
1023 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1025 /* Enable default_phase whenever the display mode is suitably aligned */
1026 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1027 &crtc_state->hw.adjusted_mode))
1028 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1031 static void ibx_set_infoframes(struct intel_encoder *encoder,
1033 const struct intel_crtc_state *crtc_state,
1034 const struct drm_connector_state *conn_state)
1036 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1037 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1038 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1039 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1040 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1041 u32 val = intel_de_read(dev_priv, reg);
1042 u32 port = VIDEO_DIP_PORT(encoder->port);
1044 assert_hdmi_port_disabled(intel_hdmi);
1046 /* See the big comment in g4x_set_infoframes() */
1047 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1050 if (!(val & VIDEO_DIP_ENABLE))
1052 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1053 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1054 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1055 intel_de_write(dev_priv, reg, val);
1056 intel_de_posting_read(dev_priv, reg);
1060 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1061 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1062 "DIP already enabled on port %c\n",
1063 (val & VIDEO_DIP_PORT_MASK) >> 29);
1064 val &= ~VIDEO_DIP_PORT_MASK;
1068 val |= VIDEO_DIP_ENABLE;
1069 val &= ~(VIDEO_DIP_ENABLE_AVI |
1070 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1071 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1073 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1074 val |= VIDEO_DIP_ENABLE_GCP;
1076 intel_de_write(dev_priv, reg, val);
1077 intel_de_posting_read(dev_priv, reg);
1079 intel_write_infoframe(encoder, crtc_state,
1080 HDMI_INFOFRAME_TYPE_AVI,
1081 &crtc_state->infoframes.avi);
1082 intel_write_infoframe(encoder, crtc_state,
1083 HDMI_INFOFRAME_TYPE_SPD,
1084 &crtc_state->infoframes.spd);
1085 intel_write_infoframe(encoder, crtc_state,
1086 HDMI_INFOFRAME_TYPE_VENDOR,
1087 &crtc_state->infoframes.hdmi);
1090 static void cpt_set_infoframes(struct intel_encoder *encoder,
1092 const struct intel_crtc_state *crtc_state,
1093 const struct drm_connector_state *conn_state)
1095 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1096 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1097 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1098 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1099 u32 val = intel_de_read(dev_priv, reg);
1101 assert_hdmi_port_disabled(intel_hdmi);
1103 /* See the big comment in g4x_set_infoframes() */
1104 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1107 if (!(val & VIDEO_DIP_ENABLE))
1109 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1110 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1111 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1112 intel_de_write(dev_priv, reg, val);
1113 intel_de_posting_read(dev_priv, reg);
1117 /* Set both together, unset both together: see the spec. */
1118 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1119 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1120 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1122 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1123 val |= VIDEO_DIP_ENABLE_GCP;
1125 intel_de_write(dev_priv, reg, val);
1126 intel_de_posting_read(dev_priv, reg);
1128 intel_write_infoframe(encoder, crtc_state,
1129 HDMI_INFOFRAME_TYPE_AVI,
1130 &crtc_state->infoframes.avi);
1131 intel_write_infoframe(encoder, crtc_state,
1132 HDMI_INFOFRAME_TYPE_SPD,
1133 &crtc_state->infoframes.spd);
1134 intel_write_infoframe(encoder, crtc_state,
1135 HDMI_INFOFRAME_TYPE_VENDOR,
1136 &crtc_state->infoframes.hdmi);
1139 static void vlv_set_infoframes(struct intel_encoder *encoder,
1141 const struct intel_crtc_state *crtc_state,
1142 const struct drm_connector_state *conn_state)
1144 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1145 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1146 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1147 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
1148 u32 val = intel_de_read(dev_priv, reg);
1149 u32 port = VIDEO_DIP_PORT(encoder->port);
1151 assert_hdmi_port_disabled(intel_hdmi);
1153 /* See the big comment in g4x_set_infoframes() */
1154 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1157 if (!(val & VIDEO_DIP_ENABLE))
1159 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1160 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1161 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1162 intel_de_write(dev_priv, reg, val);
1163 intel_de_posting_read(dev_priv, reg);
1167 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1168 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1169 "DIP already enabled on port %c\n",
1170 (val & VIDEO_DIP_PORT_MASK) >> 29);
1171 val &= ~VIDEO_DIP_PORT_MASK;
1175 val |= VIDEO_DIP_ENABLE;
1176 val &= ~(VIDEO_DIP_ENABLE_AVI |
1177 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1178 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1180 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1181 val |= VIDEO_DIP_ENABLE_GCP;
1183 intel_de_write(dev_priv, reg, val);
1184 intel_de_posting_read(dev_priv, reg);
1186 intel_write_infoframe(encoder, crtc_state,
1187 HDMI_INFOFRAME_TYPE_AVI,
1188 &crtc_state->infoframes.avi);
1189 intel_write_infoframe(encoder, crtc_state,
1190 HDMI_INFOFRAME_TYPE_SPD,
1191 &crtc_state->infoframes.spd);
1192 intel_write_infoframe(encoder, crtc_state,
1193 HDMI_INFOFRAME_TYPE_VENDOR,
1194 &crtc_state->infoframes.hdmi);
1197 static void hsw_set_infoframes(struct intel_encoder *encoder,
1199 const struct intel_crtc_state *crtc_state,
1200 const struct drm_connector_state *conn_state)
1202 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1203 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1204 u32 val = intel_de_read(dev_priv, reg);
1206 assert_hdmi_transcoder_func_disabled(dev_priv,
1207 crtc_state->cpu_transcoder);
1209 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1210 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1211 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1212 VIDEO_DIP_ENABLE_DRM_GLK);
1215 intel_de_write(dev_priv, reg, val);
1216 intel_de_posting_read(dev_priv, reg);
1220 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1221 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1223 intel_de_write(dev_priv, reg, val);
1224 intel_de_posting_read(dev_priv, reg);
1226 intel_write_infoframe(encoder, crtc_state,
1227 HDMI_INFOFRAME_TYPE_AVI,
1228 &crtc_state->infoframes.avi);
1229 intel_write_infoframe(encoder, crtc_state,
1230 HDMI_INFOFRAME_TYPE_SPD,
1231 &crtc_state->infoframes.spd);
1232 intel_write_infoframe(encoder, crtc_state,
1233 HDMI_INFOFRAME_TYPE_VENDOR,
1234 &crtc_state->infoframes.hdmi);
1235 intel_write_infoframe(encoder, crtc_state,
1236 HDMI_INFOFRAME_TYPE_DRM,
1237 &crtc_state->infoframes.drm);
1240 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1242 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1243 struct i2c_adapter *adapter;
1245 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1248 adapter = intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1250 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n",
1251 enable ? "Enabling" : "Disabling");
1253 drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, hdmi->dp_dual_mode.type, adapter, enable);
1256 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
1257 unsigned int offset, void *buffer, size_t size)
1259 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1260 struct intel_hdmi *hdmi = &dig_port->hdmi;
1261 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1264 u8 start = offset & 0xff;
1265 struct i2c_msg msgs[] = {
1267 .addr = DRM_HDCP_DDC_ADDR,
1273 .addr = DRM_HDCP_DDC_ADDR,
1279 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1280 if (ret == ARRAY_SIZE(msgs))
1282 return ret >= 0 ? -EIO : ret;
1285 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
1286 unsigned int offset, void *buffer, size_t size)
1288 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1289 struct intel_hdmi *hdmi = &dig_port->hdmi;
1290 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1296 write_buf = kzalloc(size + 1, GFP_KERNEL);
1300 write_buf[0] = offset & 0xff;
1301 memcpy(&write_buf[1], buffer, size);
1303 msg.addr = DRM_HDCP_DDC_ADDR;
1306 msg.buf = write_buf;
1308 ret = i2c_transfer(adapter, &msg, 1);
1319 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
1322 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1323 struct intel_hdmi *hdmi = &dig_port->hdmi;
1324 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1328 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
1331 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n",
1336 ret = intel_gmbus_output_aksv(adapter);
1338 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret);
1344 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
1347 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1350 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
1353 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n",
1359 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
1362 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1365 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
1366 bstatus, DRM_HDCP_BSTATUS_LEN);
1368 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n",
1374 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
1375 bool *repeater_present)
1377 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1381 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1383 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1387 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1392 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
1395 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1398 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
1399 ri_prime, DRM_HDCP_RI_LEN);
1401 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n",
1407 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
1410 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1414 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1416 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1420 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1425 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
1426 int num_downstream, u8 *ksv_fifo)
1428 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1430 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
1431 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1433 drm_dbg_kms(&i915->drm,
1434 "Read ksv fifo over DDC failed (%d)\n", ret);
1441 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
1444 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1447 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1450 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
1451 part, DRM_HDCP_V_PRIME_PART_LEN);
1453 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n",
1458 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
1459 enum transcoder cpu_transcoder)
1461 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1462 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1463 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc);
1468 scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe));
1469 if (scanline > 100 && scanline < 200)
1471 usleep_range(25, 50);
1474 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1475 false, TRANS_DDI_HDCP_SIGNALLING);
1477 drm_err(&dev_priv->drm,
1478 "Disable HDCP signalling failed (%d)\n", ret);
1482 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1483 true, TRANS_DDI_HDCP_SIGNALLING);
1485 drm_err(&dev_priv->drm,
1486 "Enable HDCP signalling failed (%d)\n", ret);
1494 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
1495 enum transcoder cpu_transcoder,
1498 struct intel_hdmi *hdmi = &dig_port->hdmi;
1499 struct intel_connector *connector = hdmi->attached_connector;
1500 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1504 usleep_range(6, 60); /* Bspec says >= 6us */
1506 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
1507 cpu_transcoder, enable,
1508 TRANS_DDI_HDCP_SIGNALLING);
1510 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
1511 enable ? "Enable" : "Disable", ret);
1516 * WA: To fix incorrect positioning of the window of
1517 * opportunity and enc_en signalling in KABYLAKE.
1519 if (IS_KABYLAKE(dev_priv) && enable)
1520 return kbl_repositioning_enc_en_signal(connector,
1527 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
1528 struct intel_connector *connector)
1530 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1531 enum port port = dig_port->base.port;
1532 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1536 u8 shim[DRM_HDCP_RI_LEN];
1539 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
1543 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
1545 /* Wait for Ri prime match */
1546 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1547 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1548 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1549 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n",
1550 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
1558 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port,
1559 struct intel_connector *connector)
1561 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1564 for (retry = 0; retry < 3; retry++)
1565 if (intel_hdmi_hdcp_check_link_once(dig_port, connector))
1568 drm_err(&i915->drm, "Link check failed\n");
1572 struct hdcp2_hdmi_msg_timeout {
1577 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1578 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1579 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1580 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1581 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1582 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1586 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
1589 return intel_hdmi_hdcp_read(dig_port,
1590 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1592 HDCP_2_2_HDMI_RXSTATUS_LEN);
1595 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1599 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1601 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1603 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1606 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1607 if (hdcp2_msg_timeout[i].msg_id == msg_id)
1608 return hdcp2_msg_timeout[i].timeout;
1615 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
1616 u8 msg_id, bool *msg_ready,
1619 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1620 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1623 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1625 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n",
1630 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1633 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1634 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1637 *msg_ready = *msg_sz;
1643 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
1644 u8 msg_id, bool paired)
1646 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1647 bool msg_ready = false;
1651 timeout = get_hdcp2_msg_timeout(msg_id, paired);
1655 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1658 !ret && msg_ready && msg_sz, timeout * 1000,
1661 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n",
1662 msg_id, ret, timeout);
1664 return ret ? ret : msg_sz;
1668 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port,
1669 void *buf, size_t size)
1671 unsigned int offset;
1673 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1674 return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
1678 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
1679 u8 msg_id, void *buf, size_t size)
1681 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1682 struct intel_hdmi *hdmi = &dig_port->hdmi;
1683 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1684 unsigned int offset;
1687 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
1693 * Available msg size should be equal to or lesser than the
1697 drm_dbg_kms(&i915->drm,
1698 "msg_sz(%zd) is more than exp size(%zu)\n",
1703 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1704 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
1706 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n",
1713 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
1714 struct intel_connector *connector)
1716 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1719 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1724 * Re-auth request and Link Integrity Failures are represented by
1725 * same bit. i.e reauth_req.
1727 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1728 ret = HDCP_REAUTH_REQUEST;
1729 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1730 ret = HDCP_TOPOLOGY_CHANGE;
1736 int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port,
1743 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1744 &hdcp2_version, sizeof(hdcp2_version));
1745 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1751 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1752 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1753 .read_bksv = intel_hdmi_hdcp_read_bksv,
1754 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1755 .repeater_present = intel_hdmi_hdcp_repeater_present,
1756 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1757 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1758 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1759 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1760 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1761 .check_link = intel_hdmi_hdcp_check_link,
1762 .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1763 .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1764 .check_2_2_link = intel_hdmi_hdcp2_check_link,
1765 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1766 .protocol = HDCP_PROTOCOL_HDMI,
1769 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1771 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1772 int max_tmds_clock, vbt_max_tmds_clock;
1774 if (DISPLAY_VER(dev_priv) >= 10)
1775 max_tmds_clock = 594000;
1776 else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1777 max_tmds_clock = 300000;
1778 else if (DISPLAY_VER(dev_priv) >= 5)
1779 max_tmds_clock = 225000;
1781 max_tmds_clock = 165000;
1783 vbt_max_tmds_clock = intel_bios_hdmi_max_tmds_clock(encoder->devdata);
1784 if (vbt_max_tmds_clock)
1785 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);
1787 return max_tmds_clock;
1790 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
1791 const struct drm_connector_state *conn_state)
1793 return hdmi->has_hdmi_sink &&
1794 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1797 static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state)
1799 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;
1802 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1803 bool respect_downstream_limits,
1806 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1807 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1809 if (respect_downstream_limits) {
1810 struct intel_connector *connector = hdmi->attached_connector;
1811 const struct drm_display_info *info = &connector->base.display_info;
1813 if (hdmi->dp_dual_mode.max_tmds_clock)
1814 max_tmds_clock = min(max_tmds_clock,
1815 hdmi->dp_dual_mode.max_tmds_clock);
1817 if (info->max_tmds_clock)
1818 max_tmds_clock = min(max_tmds_clock,
1819 info->max_tmds_clock);
1820 else if (!has_hdmi_sink)
1821 max_tmds_clock = min(max_tmds_clock, 165000);
1824 return max_tmds_clock;
1827 static enum drm_mode_status
1828 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1829 int clock, bool respect_downstream_limits,
1832 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1833 enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port);
1836 return MODE_CLOCK_LOW;
1837 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
1839 return MODE_CLOCK_HIGH;
1841 /* GLK DPLL can't generate 446-480 MHz */
1842 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000)
1843 return MODE_CLOCK_RANGE;
1845 /* BXT/GLK DPLL can't generate 223-240 MHz */
1846 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1847 clock > 223333 && clock < 240000)
1848 return MODE_CLOCK_RANGE;
1850 /* CHV DPLL can't generate 216-240 MHz */
1851 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1852 return MODE_CLOCK_RANGE;
1854 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */
1855 if (intel_phy_is_combo(dev_priv, phy) && clock > 500000 && clock < 533200)
1856 return MODE_CLOCK_RANGE;
1858 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */
1859 if (intel_phy_is_tc(dev_priv, phy) && clock > 500000 && clock < 532800)
1860 return MODE_CLOCK_RANGE;
1863 * SNPS PHYs' MPLLB table-based programming can only handle a fixed
1864 * set of link rates.
1866 * FIXME: We will hopefully get an algorithmic way of programming
1867 * the MPLLB for HDMI in the future.
1869 if (DISPLAY_VER(dev_priv) >= 14)
1870 return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock);
1871 else if (IS_DG2(dev_priv))
1872 return intel_snps_phy_check_hdmi_link_rate(clock);
1877 int intel_hdmi_tmds_clock(int clock, int bpc,
1878 enum intel_output_format sink_format)
1880 /* YCBCR420 TMDS rate requirement is half the pixel clock */
1881 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1885 * Need to adjust the port link by:
1889 return DIV_ROUND_CLOSEST(clock * bpc, 8);
1892 static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int bpc)
1896 return !HAS_GMCH(i915);
1898 return DISPLAY_VER(i915) >= 11;
1907 static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector,
1908 int bpc, bool has_hdmi_sink,
1909 enum intel_output_format sink_format)
1911 const struct drm_display_info *info = &connector->display_info;
1912 const struct drm_hdmi_info *hdmi = &info->hdmi;
1919 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1920 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36;
1922 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36;
1927 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1928 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30;
1930 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30;
1939 static enum drm_mode_status
1940 intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
1942 enum intel_output_format sink_format)
1944 struct drm_i915_private *i915 = to_i915(connector->dev);
1945 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1946 enum drm_mode_status status = MODE_OK;
1950 * Try all color depths since valid port clock range
1951 * can have holes. Any mode that can be used with at
1952 * least one color depth is accepted.
1954 for (bpc = 12; bpc >= 8; bpc -= 2) {
1955 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
1957 if (!intel_hdmi_source_bpc_possible(i915, bpc))
1960 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, sink_format))
1963 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);
1964 if (status == MODE_OK)
1968 /* can never happen */
1969 drm_WARN_ON(&i915->drm, status == MODE_OK);
1974 static enum drm_mode_status
1975 intel_hdmi_mode_valid(struct drm_connector *connector,
1976 struct drm_display_mode *mode)
1978 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1979 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1980 enum drm_mode_status status;
1981 int clock = mode->clock;
1982 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1983 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
1984 bool ycbcr_420_only;
1985 enum intel_output_format sink_format;
1987 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1990 if (clock > max_dotclk)
1991 return MODE_CLOCK_HIGH;
1993 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1995 return MODE_CLOCK_LOW;
2000 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be
2001 * enumerated only if FRL is supported. Current platforms do not support
2002 * FRL so prune the higher resolution modes that require doctclock more
2006 return MODE_CLOCK_HIGH;
2008 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode);
2011 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2013 sink_format = INTEL_OUTPUT_FORMAT_RGB;
2015 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format);
2016 if (status != MODE_OK) {
2017 if (ycbcr_420_only ||
2018 !connector->ycbcr_420_allowed ||
2019 !drm_mode_is_420_also(&connector->display_info, mode))
2022 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2023 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format);
2024 if (status != MODE_OK)
2028 return intel_mode_valid_max_plane_size(dev_priv, mode, false);
2031 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
2032 int bpc, bool has_hdmi_sink)
2034 struct drm_atomic_state *state = crtc_state->uapi.state;
2035 struct drm_connector_state *connector_state;
2036 struct drm_connector *connector;
2039 for_each_new_connector_in_state(state, connector, connector_state, i) {
2040 if (connector_state->crtc != crtc_state->uapi.crtc)
2043 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink,
2044 crtc_state->sink_format))
2051 static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc)
2053 struct drm_i915_private *dev_priv =
2054 to_i915(crtc_state->uapi.crtc->dev);
2055 const struct drm_display_mode *adjusted_mode =
2056 &crtc_state->hw.adjusted_mode;
2058 if (!intel_hdmi_source_bpc_possible(dev_priv, bpc))
2061 /* Display Wa_1405510057:icl,ehl */
2062 if (intel_hdmi_is_ycbcr420(crtc_state) &&
2063 bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
2064 (adjusted_mode->crtc_hblank_end -
2065 adjusted_mode->crtc_hblank_start) % 8 == 2)
2068 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink);
2071 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2072 struct intel_crtc_state *crtc_state,
2073 int clock, bool respect_downstream_limits)
2075 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2079 * pipe_bpp could already be below 8bpc due to FDI
2080 * bandwidth constraints. HDMI minimum is 8bpc however.
2082 bpc = max(crtc_state->pipe_bpp / 3, 8);
2085 * We will never exceed downstream TMDS clock limits while
2086 * attempting deep color. If the user insists on forcing an
2087 * out of spec mode they will have to be satisfied with 8bpc.
2089 if (!respect_downstream_limits)
2092 for (; bpc >= 8; bpc -= 2) {
2093 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc,
2094 crtc_state->sink_format);
2096 if (hdmi_bpc_possible(crtc_state, bpc) &&
2097 hdmi_port_clock_valid(intel_hdmi, tmds_clock,
2098 respect_downstream_limits,
2099 crtc_state->has_hdmi_sink) == MODE_OK)
2106 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2107 struct intel_crtc_state *crtc_state,
2108 bool respect_downstream_limits)
2110 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2111 const struct drm_display_mode *adjusted_mode =
2112 &crtc_state->hw.adjusted_mode;
2113 int bpc, clock = adjusted_mode->crtc_clock;
2115 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2118 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,
2119 respect_downstream_limits);
2123 crtc_state->port_clock =
2124 intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format);
2127 * pipe_bpp could already be below 8bpc due to
2128 * FDI bandwidth constraints. We shouldn't bump it
2129 * back up to the HDMI minimum 8bpc in that case.
2131 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3);
2133 drm_dbg_kms(&i915->drm,
2134 "picking %d bpc for HDMI output (pipe bpp: %d)\n",
2135 bpc, crtc_state->pipe_bpp);
2140 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2141 const struct drm_connector_state *conn_state)
2143 const struct intel_digital_connector_state *intel_conn_state =
2144 to_intel_digital_connector_state(conn_state);
2145 const struct drm_display_mode *adjusted_mode =
2146 &crtc_state->hw.adjusted_mode;
2149 * Our YCbCr output is always limited range.
2150 * crtc_state->limited_color_range only applies to RGB,
2151 * and it must never be set for YCbCr or we risk setting
2152 * some conflicting bits in TRANSCONF which will mess up
2153 * the colors on the monitor.
2155 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2158 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2159 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2160 return crtc_state->has_hdmi_sink &&
2161 drm_default_rgb_quant_range(adjusted_mode) ==
2162 HDMI_QUANTIZATION_RANGE_LIMITED;
2164 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2168 static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
2169 const struct intel_crtc_state *crtc_state,
2170 const struct drm_connector_state *conn_state)
2172 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2173 const struct intel_digital_connector_state *intel_conn_state =
2174 to_intel_digital_connector_state(conn_state);
2176 if (!crtc_state->has_hdmi_sink)
2179 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2180 return intel_hdmi->has_audio;
2182 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2185 static enum intel_output_format
2186 intel_hdmi_sink_format(const struct intel_crtc_state *crtc_state,
2187 struct intel_connector *connector,
2188 bool ycbcr_420_output)
2190 if (!crtc_state->has_hdmi_sink)
2191 return INTEL_OUTPUT_FORMAT_RGB;
2193 if (connector->base.ycbcr_420_allowed && ycbcr_420_output)
2194 return INTEL_OUTPUT_FORMAT_YCBCR420;
2196 return INTEL_OUTPUT_FORMAT_RGB;
2199 static enum intel_output_format
2200 intel_hdmi_output_format(const struct intel_crtc_state *crtc_state)
2202 return crtc_state->sink_format;
2205 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
2206 struct intel_crtc_state *crtc_state,
2207 const struct drm_connector_state *conn_state,
2208 bool respect_downstream_limits)
2210 struct intel_connector *connector = to_intel_connector(conn_state->connector);
2211 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2212 const struct drm_display_info *info = &connector->base.display_info;
2213 struct drm_i915_private *i915 = to_i915(connector->base.dev);
2214 bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2217 crtc_state->sink_format =
2218 intel_hdmi_sink_format(crtc_state, connector, ycbcr_420_only);
2220 if (ycbcr_420_only && crtc_state->sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) {
2221 drm_dbg_kms(&i915->drm,
2222 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2223 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
2226 crtc_state->output_format = intel_hdmi_output_format(crtc_state);
2227 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2229 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2230 !crtc_state->has_hdmi_sink ||
2231 !connector->base.ycbcr_420_allowed ||
2232 !drm_mode_is_420_also(info, adjusted_mode))
2235 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2236 crtc_state->output_format = intel_hdmi_output_format(crtc_state);
2237 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2243 static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state)
2245 return crtc_state->uapi.encoder_mask &&
2246 !is_power_of_2(crtc_state->uapi.encoder_mask);
2249 static bool source_supports_scrambling(struct intel_encoder *encoder)
2252 * Gen 10+ support HDMI 2.0 : the max tmds clock is 594MHz, and
2253 * scrambling is supported.
2254 * But there seem to be cases where certain platforms that support
2255 * HDMI 2.0, have an HDMI1.4 retimer chip, and the max tmds clock is
2256 * capped by VBT to less than 340MHz.
2258 * In such cases when an HDMI2.0 sink is connected, it creates a
2259 * problem : the platform and the sink both support scrambling but the
2260 * HDMI 1.4 retimer chip doesn't.
2262 * So go for scrambling, based on the max tmds clock taking into account,
2263 * restrictions coming from VBT.
2265 return intel_hdmi_source_max_tmds_clock(encoder) > 340000;
2268 bool intel_hdmi_compute_has_hdmi_sink(struct intel_encoder *encoder,
2269 const struct intel_crtc_state *crtc_state,
2270 const struct drm_connector_state *conn_state)
2272 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
2274 return intel_has_hdmi_sink(hdmi, conn_state) &&
2275 !intel_hdmi_is_cloned(crtc_state);
2278 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2279 struct intel_crtc_state *pipe_config,
2280 struct drm_connector_state *conn_state)
2282 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2283 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2284 struct drm_connector *connector = conn_state->connector;
2285 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2288 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2291 if (!connector->interlace_allowed &&
2292 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2295 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2297 if (pipe_config->has_hdmi_sink)
2298 pipe_config->has_infoframe = true;
2300 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2301 pipe_config->pixel_multiplier = 2;
2303 pipe_config->has_audio =
2304 intel_hdmi_has_audio(encoder, pipe_config, conn_state) &&
2305 intel_audio_compute_config(encoder, pipe_config, conn_state);
2308 * Try to respect downstream TMDS clock limits first, if
2309 * that fails assume the user might know something we don't.
2311 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true);
2313 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false);
2315 drm_dbg_kms(&dev_priv->drm,
2316 "unsupported HDMI clock (%d kHz), rejecting mode\n",
2317 pipe_config->hw.adjusted_mode.crtc_clock);
2321 if (intel_hdmi_is_ycbcr420(pipe_config)) {
2322 ret = intel_panel_fitting(pipe_config, conn_state);
2327 pipe_config->limited_color_range =
2328 intel_hdmi_limited_color_range(pipe_config, conn_state);
2330 if (conn_state->picture_aspect_ratio)
2331 adjusted_mode->picture_aspect_ratio =
2332 conn_state->picture_aspect_ratio;
2334 pipe_config->lane_count = 4;
2336 if (scdc->scrambling.supported && source_supports_scrambling(encoder)) {
2337 if (scdc->scrambling.low_rates)
2338 pipe_config->hdmi_scrambling = true;
2340 if (pipe_config->port_clock > 340000) {
2341 pipe_config->hdmi_scrambling = true;
2342 pipe_config->hdmi_high_tmds_clock_ratio = true;
2346 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
2349 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2350 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n");
2354 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2355 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n");
2359 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2360 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n");
2364 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2365 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n");
2372 void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder)
2374 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2377 * Give a hand to buggy BIOSen which forget to turn
2378 * the TMDS output buffers back on after a reboot.
2380 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2384 intel_hdmi_unset_edid(struct drm_connector *connector)
2386 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2388 intel_hdmi->has_hdmi_sink = false;
2389 intel_hdmi->has_audio = false;
2391 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2392 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2394 drm_edid_free(to_intel_connector(connector)->detect_edid);
2395 to_intel_connector(connector)->detect_edid = NULL;
2399 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector)
2401 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2402 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2403 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
2404 struct i2c_adapter *adapter =
2405 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2406 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(&dev_priv->drm, adapter);
2409 * Type 1 DVI adaptors are not required to implement any
2410 * registers, so we can't always detect their presence.
2411 * Ideally we should be able to check the state of the
2412 * CONFIG1 pin, but no such luck on our hardware.
2414 * The only method left to us is to check the VBT to see
2415 * if the port is a dual mode capable DP port.
2417 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2418 if (!connector->force &&
2419 intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) {
2420 drm_dbg_kms(&dev_priv->drm,
2421 "Assuming DP dual mode adaptor presence based on VBT\n");
2422 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2424 type = DRM_DP_DUAL_MODE_NONE;
2428 if (type == DRM_DP_DUAL_MODE_NONE)
2431 hdmi->dp_dual_mode.type = type;
2432 hdmi->dp_dual_mode.max_tmds_clock =
2433 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, adapter);
2435 drm_dbg_kms(&dev_priv->drm,
2436 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2437 drm_dp_get_dual_mode_type_name(type),
2438 hdmi->dp_dual_mode.max_tmds_clock);
2440 /* Older VBTs are often buggy and can't be trusted :( Play it safe. */
2441 if ((DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
2442 !intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) {
2443 drm_dbg_kms(&dev_priv->drm,
2444 "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n");
2445 hdmi->dp_dual_mode.max_tmds_clock = 0;
2450 intel_hdmi_set_edid(struct drm_connector *connector)
2452 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2453 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2454 intel_wakeref_t wakeref;
2455 const struct drm_edid *drm_edid;
2456 const struct edid *edid;
2457 bool connected = false;
2458 struct i2c_adapter *i2c;
2460 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2462 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2464 drm_edid = drm_edid_read_ddc(connector, i2c);
2466 if (!drm_edid && !intel_gmbus_is_forced_bit(i2c)) {
2467 drm_dbg_kms(&dev_priv->drm,
2468 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2469 intel_gmbus_force_bit(i2c, true);
2470 drm_edid = drm_edid_read_ddc(connector, i2c);
2471 intel_gmbus_force_bit(i2c, false);
2474 /* Below we depend on display info having been updated */
2475 drm_edid_connector_update(connector, drm_edid);
2477 to_intel_connector(connector)->detect_edid = drm_edid;
2479 /* FIXME: Get rid of drm_edid_raw() */
2480 edid = drm_edid_raw(drm_edid);
2481 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2482 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2483 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2485 intel_hdmi_dp_dual_mode_detect(connector);
2490 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2492 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2497 static enum drm_connector_status
2498 intel_hdmi_detect(struct drm_connector *connector, bool force)
2500 enum drm_connector_status status = connector_status_disconnected;
2501 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2502 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2503 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2504 intel_wakeref_t wakeref;
2506 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2507 connector->base.id, connector->name);
2509 if (!INTEL_DISPLAY_ENABLED(dev_priv))
2510 return connector_status_disconnected;
2512 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2514 if (DISPLAY_VER(dev_priv) >= 11 &&
2515 !intel_digital_port_connected(encoder))
2518 intel_hdmi_unset_edid(connector);
2520 if (intel_hdmi_set_edid(connector))
2521 status = connector_status_connected;
2524 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2526 if (status != connector_status_connected)
2527 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2530 * Make sure the refs for power wells enabled during detect are
2531 * dropped to avoid a new detect cycle triggered by HPD polling.
2533 intel_display_power_flush_work(dev_priv);
2539 intel_hdmi_force(struct drm_connector *connector)
2541 struct drm_i915_private *i915 = to_i915(connector->dev);
2543 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
2544 connector->base.id, connector->name);
2546 intel_hdmi_unset_edid(connector);
2548 if (connector->status != connector_status_connected)
2551 intel_hdmi_set_edid(connector);
2554 static int intel_hdmi_get_modes(struct drm_connector *connector)
2556 /* drm_edid_connector_update() done in ->detect() or ->force() */
2557 return drm_edid_connector_add_modes(connector);
2560 static struct i2c_adapter *
2561 intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2563 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2564 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2566 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2569 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2571 struct drm_i915_private *i915 = to_i915(connector->dev);
2572 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2573 struct kobject *i2c_kobj = &adapter->dev.kobj;
2574 struct kobject *connector_kobj = &connector->kdev->kobj;
2577 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2579 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret);
2582 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2584 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2585 struct kobject *i2c_kobj = &adapter->dev.kobj;
2586 struct kobject *connector_kobj = &connector->kdev->kobj;
2588 sysfs_remove_link(connector_kobj, i2c_kobj->name);
2592 intel_hdmi_connector_register(struct drm_connector *connector)
2596 ret = intel_connector_register(connector);
2600 intel_hdmi_create_i2c_symlink(connector);
2605 static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2607 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier;
2609 cec_notifier_conn_unregister(n);
2611 intel_hdmi_remove_i2c_symlink(connector);
2612 intel_connector_unregister(connector);
2615 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2616 .detect = intel_hdmi_detect,
2617 .force = intel_hdmi_force,
2618 .fill_modes = drm_helper_probe_single_connector_modes,
2619 .atomic_get_property = intel_digital_connector_atomic_get_property,
2620 .atomic_set_property = intel_digital_connector_atomic_set_property,
2621 .late_register = intel_hdmi_connector_register,
2622 .early_unregister = intel_hdmi_connector_unregister,
2623 .destroy = intel_connector_destroy,
2624 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2625 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2628 static int intel_hdmi_connector_atomic_check(struct drm_connector *connector,
2629 struct drm_atomic_state *state)
2631 struct drm_i915_private *i915 = to_i915(state->dev);
2634 return intel_digital_connector_atomic_check(connector, state);
2636 return g4x_hdmi_connector_atomic_check(connector, state);
2639 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2640 .get_modes = intel_hdmi_get_modes,
2641 .mode_valid = intel_hdmi_mode_valid,
2642 .atomic_check = intel_hdmi_connector_atomic_check,
2646 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2648 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2650 intel_attach_force_audio_property(connector);
2651 intel_attach_broadcast_rgb_property(connector);
2652 intel_attach_aspect_ratio_property(connector);
2654 intel_attach_hdmi_colorspace_property(connector);
2655 drm_connector_attach_content_type_property(connector);
2657 if (DISPLAY_VER(dev_priv) >= 10)
2658 drm_connector_attach_hdr_output_metadata_property(connector);
2660 if (!HAS_GMCH(dev_priv))
2661 drm_connector_attach_max_bpc_property(connector, 8, 12);
2665 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2666 * @encoder: intel_encoder
2667 * @connector: drm_connector
2668 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2669 * or reset the high tmds clock ratio for scrambling
2670 * @scrambling: bool to Indicate if the function needs to set or reset
2673 * This function handles scrambling on HDMI 2.0 capable sinks.
2674 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2675 * it enables scrambling. This should be called before enabling the HDMI
2676 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2677 * detect a scrambled clock within 100 ms.
2680 * True on success, false on failure.
2682 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2683 struct drm_connector *connector,
2684 bool high_tmds_clock_ratio,
2687 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2688 struct drm_scrambling *sink_scrambling =
2689 &connector->display_info.hdmi.scdc.scrambling;
2691 if (!sink_scrambling->supported)
2694 drm_dbg_kms(&dev_priv->drm,
2695 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2696 connector->base.id, connector->name,
2697 str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10);
2699 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2700 return drm_scdc_set_high_tmds_clock_ratio(connector, high_tmds_clock_ratio) &&
2701 drm_scdc_set_scrambling(connector, scrambling);
2704 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2710 ddc_pin = GMBUS_PIN_DPB;
2713 ddc_pin = GMBUS_PIN_DPC;
2716 ddc_pin = GMBUS_PIN_DPD_CHV;
2720 ddc_pin = GMBUS_PIN_DPB;
2726 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2732 ddc_pin = GMBUS_PIN_1_BXT;
2735 ddc_pin = GMBUS_PIN_2_BXT;
2739 ddc_pin = GMBUS_PIN_1_BXT;
2745 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2752 ddc_pin = GMBUS_PIN_1_BXT;
2755 ddc_pin = GMBUS_PIN_2_BXT;
2758 ddc_pin = GMBUS_PIN_4_CNP;
2761 ddc_pin = GMBUS_PIN_3_BXT;
2765 ddc_pin = GMBUS_PIN_1_BXT;
2771 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2773 enum phy phy = intel_port_to_phy(dev_priv, port);
2775 if (intel_phy_is_combo(dev_priv, phy))
2776 return GMBUS_PIN_1_BXT + port;
2777 else if (intel_phy_is_tc(dev_priv, phy))
2778 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
2780 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port));
2781 return GMBUS_PIN_2_BXT;
2784 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2786 enum phy phy = intel_port_to_phy(dev_priv, port);
2791 ddc_pin = GMBUS_PIN_1_BXT;
2794 ddc_pin = GMBUS_PIN_2_BXT;
2797 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2801 ddc_pin = GMBUS_PIN_1_BXT;
2807 static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2809 enum phy phy = intel_port_to_phy(dev_priv, port);
2811 WARN_ON(port == PORT_C);
2814 * Pin mapping for RKL depends on which PCH is present. With TGP, the
2815 * final two outputs use type-c pins, even though they're actually
2816 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2819 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
2820 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2822 return GMBUS_PIN_1_BXT + phy;
2825 static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port)
2827 enum phy phy = intel_port_to_phy(i915, port);
2829 drm_WARN_ON(&i915->drm, port == PORT_A);
2832 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP,
2833 * final two outputs use type-c pins, even though they're actually
2834 * combo outputs. With CMP, the traditional DDI A-D pins are used for
2837 if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C)
2838 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2840 return GMBUS_PIN_1_BXT + phy;
2843 static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2845 return intel_port_to_phy(dev_priv, port) + 1;
2848 static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2850 enum phy phy = intel_port_to_phy(dev_priv, port);
2852 WARN_ON(port == PORT_B || port == PORT_C);
2855 * Pin mapping for ADL-S requires TC pins for all combo phy outputs
2856 * except first combo output.
2859 return GMBUS_PIN_1_BXT;
2861 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
2864 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2871 ddc_pin = GMBUS_PIN_DPB;
2874 ddc_pin = GMBUS_PIN_DPC;
2877 ddc_pin = GMBUS_PIN_DPD;
2881 ddc_pin = GMBUS_PIN_DPB;
2887 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
2889 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2890 enum port port = encoder->port;
2893 ddc_pin = intel_bios_hdmi_ddc_pin(encoder->devdata);
2895 drm_dbg_kms(&dev_priv->drm,
2896 "[ENCODER:%d:%s] Using DDC pin 0x%x (VBT)\n",
2897 encoder->base.base.id, encoder->base.name,
2902 if (IS_ALDERLAKE_S(dev_priv))
2903 ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
2904 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
2905 ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
2906 else if (IS_ROCKETLAKE(dev_priv))
2907 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
2908 else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
2909 ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
2910 else if (IS_JSL_EHL(dev_priv) && HAS_PCH_TGP(dev_priv))
2911 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
2912 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2913 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2914 else if (HAS_PCH_CNP(dev_priv))
2915 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2916 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
2917 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2918 else if (IS_CHERRYVIEW(dev_priv))
2919 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2921 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2923 drm_dbg_kms(&dev_priv->drm,
2924 "[ENCODER:%d:%s] Using DDC pin 0x%x (platform default)\n",
2925 encoder->base.base.id, encoder->base.name,
2931 void intel_infoframe_init(struct intel_digital_port *dig_port)
2933 struct drm_i915_private *dev_priv =
2934 to_i915(dig_port->base.base.dev);
2936 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2937 dig_port->write_infoframe = vlv_write_infoframe;
2938 dig_port->read_infoframe = vlv_read_infoframe;
2939 dig_port->set_infoframes = vlv_set_infoframes;
2940 dig_port->infoframes_enabled = vlv_infoframes_enabled;
2941 } else if (IS_G4X(dev_priv)) {
2942 dig_port->write_infoframe = g4x_write_infoframe;
2943 dig_port->read_infoframe = g4x_read_infoframe;
2944 dig_port->set_infoframes = g4x_set_infoframes;
2945 dig_port->infoframes_enabled = g4x_infoframes_enabled;
2946 } else if (HAS_DDI(dev_priv)) {
2947 if (intel_bios_encoder_is_lspcon(dig_port->base.devdata)) {
2948 dig_port->write_infoframe = lspcon_write_infoframe;
2949 dig_port->read_infoframe = lspcon_read_infoframe;
2950 dig_port->set_infoframes = lspcon_set_infoframes;
2951 dig_port->infoframes_enabled = lspcon_infoframes_enabled;
2953 dig_port->write_infoframe = hsw_write_infoframe;
2954 dig_port->read_infoframe = hsw_read_infoframe;
2955 dig_port->set_infoframes = hsw_set_infoframes;
2956 dig_port->infoframes_enabled = hsw_infoframes_enabled;
2958 } else if (HAS_PCH_IBX(dev_priv)) {
2959 dig_port->write_infoframe = ibx_write_infoframe;
2960 dig_port->read_infoframe = ibx_read_infoframe;
2961 dig_port->set_infoframes = ibx_set_infoframes;
2962 dig_port->infoframes_enabled = ibx_infoframes_enabled;
2964 dig_port->write_infoframe = cpt_write_infoframe;
2965 dig_port->read_infoframe = cpt_read_infoframe;
2966 dig_port->set_infoframes = cpt_set_infoframes;
2967 dig_port->infoframes_enabled = cpt_infoframes_enabled;
2971 void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
2972 struct intel_connector *intel_connector)
2974 struct drm_connector *connector = &intel_connector->base;
2975 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2976 struct intel_encoder *intel_encoder = &dig_port->base;
2977 struct drm_device *dev = intel_encoder->base.dev;
2978 struct drm_i915_private *dev_priv = to_i915(dev);
2979 struct i2c_adapter *ddc;
2980 enum port port = intel_encoder->port;
2981 struct cec_connector_info conn_info;
2983 drm_dbg_kms(&dev_priv->drm,
2984 "Adding HDMI connector on [ENCODER:%d:%s]\n",
2985 intel_encoder->base.base.id, intel_encoder->base.name);
2987 if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A))
2990 if (drm_WARN(dev, dig_port->max_lanes < 4,
2991 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
2992 dig_port->max_lanes, intel_encoder->base.base.id,
2993 intel_encoder->base.name))
2996 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder);
2997 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2999 drm_connector_init_with_ddc(dev, connector,
3000 &intel_hdmi_connector_funcs,
3001 DRM_MODE_CONNECTOR_HDMIA,
3003 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
3005 if (DISPLAY_VER(dev_priv) < 12)
3006 connector->interlace_allowed = true;
3008 connector->stereo_allowed = true;
3010 if (DISPLAY_VER(dev_priv) >= 10)
3011 connector->ycbcr_420_allowed = true;
3013 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
3015 if (HAS_DDI(dev_priv))
3016 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3018 intel_connector->get_hw_state = intel_connector_get_hw_state;
3020 intel_hdmi_add_properties(intel_hdmi, connector);
3022 intel_connector_attach_encoder(intel_connector, intel_encoder);
3023 intel_hdmi->attached_connector = intel_connector;
3025 if (is_hdcp_supported(dev_priv, port)) {
3026 int ret = intel_hdcp_init(intel_connector, dig_port,
3027 &intel_hdmi_hdcp_shim);
3029 drm_dbg_kms(&dev_priv->drm,
3030 "HDCP init failed, skipping.\n");
3033 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3034 * 0xd. Failure to do so will result in spurious interrupts being
3035 * generated on the port when a cable is not attached.
3037 if (IS_G45(dev_priv)) {
3038 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
3039 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
3040 (temp & ~0xf) | 0xd);
3043 cec_fill_conn_info_from_drm(&conn_info, connector);
3045 intel_hdmi->cec_notifier =
3046 cec_notifier_conn_register(dev->dev, port_identifier(port),
3048 if (!intel_hdmi->cec_notifier)
3049 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n");
3053 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
3054 * @vactive: Vactive of a display mode
3056 * @return: appropriate dsc slice height for a given mode.
3058 int intel_hdmi_dsc_get_slice_height(int vactive)
3063 * Slice Height determination : HDMI2.1 Section 7.7.5.2
3064 * Select smallest slice height >=96, that results in a valid PPS and
3065 * requires minimum padding lines required for final slice.
3067 * Assumption : Vactive is even.
3069 for (slice_height = 96; slice_height <= vactive; slice_height += 2)
3070 if (vactive % slice_height == 0)
3071 return slice_height;
3077 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
3078 * and dsc decoder capabilities
3080 * @crtc_state: intel crtc_state
3081 * @src_max_slices: maximum slices supported by the DSC encoder
3082 * @src_max_slice_width: maximum slice width supported by DSC encoder
3083 * @hdmi_max_slices: maximum slices supported by sink DSC decoder
3084 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink
3086 * @return: num of dsc slices that can be supported by the dsc encoder
3090 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
3091 int src_max_slices, int src_max_slice_width,
3092 int hdmi_max_slices, int hdmi_throughput)
3094 /* Pixel rates in KPixels/sec */
3095 #define HDMI_DSC_PEAK_PIXEL_RATE 2720000
3097 * Rates at which the source and sink are required to process pixels in each
3098 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz.
3100 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000
3101 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000
3103 /* Spec limits the slice width to 2720 pixels */
3104 #define MAX_HDMI_SLICE_WIDTH 2720
3106 int adjusted_clk_khz;
3109 int max_throughput; /* max clock freq. in khz per slice */
3110 int max_slice_width;
3112 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
3114 if (!hdmi_throughput)
3118 * Slice Width determination : HDMI2.1 Section 7.7.5.1
3119 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as
3120 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later
3121 * dividing adjusted clock value by 10.
3123 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3124 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
3130 * As per spec, the rate at which the source and the sink process
3131 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz.
3132 * This depends upon the pixel clock rate and output formats
3134 * If pixel clock * kslice adjust >= 2720MHz slices can be processed
3135 * at max 340MHz, otherwise they can be processed at max 400MHz.
3138 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10);
3140 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE)
3141 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0;
3143 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1;
3146 * Taking into account the sink's capability for maximum
3147 * clock per slice (in MHz) as read from HF-VSDB.
3149 max_throughput = min(max_throughput, hdmi_throughput * 1000);
3151 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput);
3152 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width);
3155 * Keep on increasing the num of slices/line, starting from min_slices
3156 * per line till we get such a number, for which the slice_width is
3157 * just less than max_slice_width. The slices/line selected should be
3158 * less than or equal to the max horizontal slices that the combination
3159 * of PCON encoder and HDMI decoder can support.
3161 slice_width = max_slice_width;
3164 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1)
3166 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2)
3168 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4)
3170 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8)
3172 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12)
3174 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16)
3179 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
3180 if (slice_width >= max_slice_width)
3181 min_slices = target_slices + 1;
3182 } while (slice_width >= max_slice_width);
3184 return target_slices;
3188 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3189 * source and sink capabilities.
3191 * @src_fraction_bpp: fractional bpp supported by the source
3192 * @slice_width: dsc slice width supported by the source and sink
3193 * @num_slices: num of slices supported by the source and sink
3194 * @output_format: video output format
3195 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
3196 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
3198 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
3201 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
3202 int output_format, bool hdmi_all_bpp,
3203 int hdmi_max_chunk_bytes)
3205 int max_dsc_bpp, min_dsc_bpp;
3207 bool bpp_found = false;
3208 int bpp_decrement_x16;
3213 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
3214 * Start with the max bpp and keep on decrementing with
3215 * fractional bpp, if supported by PCON DSC encoder
3217 * for each bpp we check if no of bytes can be supported by HDMI sink
3220 /* Assuming: bpc as 8*/
3221 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3223 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */
3224 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3225 output_format == INTEL_OUTPUT_FORMAT_RGB) {
3227 max_dsc_bpp = 3 * 8; /* 3*bpc */
3229 /* Assuming 4:2:2 encoding */
3231 max_dsc_bpp = 2 * 8; /* 2*bpc */
3235 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
3236 * Section 7.7.34 : Source shall not enable compressed Video
3237 * Transport with bpp_target settings above 12 bpp unless
3238 * DSC_all_bpp is set to 1.
3241 max_dsc_bpp = min(max_dsc_bpp, 12);
3244 * The Sink has a limit of compressed data in bytes for a scanline,
3245 * as described in max_chunk_bytes field in HFVSDB block of edid.
3246 * The no. of bytes depend on the target bits per pixel that the
3247 * source configures. So we start with the max_bpp and calculate
3248 * the target_chunk_bytes. We keep on decrementing the target_bpp,
3249 * till we get the target_chunk_bytes just less than what the sink's
3250 * max_chunk_bytes, or else till we reach the min_dsc_bpp.
3252 * The decrement is according to the fractional support from PCON DSC
3253 * encoder. For fractional BPP we use bpp_target as a multiple of 16.
3255 * bpp_target_x16 = bpp_target * 16
3256 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps
3257 * {1/16, 1/8, 1/4, 1/2, 1} respectively.
3260 bpp_target = max_dsc_bpp;
3262 /* src does not support fractional bpp implies decrement by 16 for bppx16 */
3263 if (!src_fractional_bpp)
3264 src_fractional_bpp = 1;
3265 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp);
3266 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16;
3268 while (bpp_target_x16 > (min_dsc_bpp * 16)) {
3271 bpp = DIV_ROUND_UP(bpp_target_x16, 16);
3272 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);
3273 if (target_bytes <= hdmi_max_chunk_bytes) {
3277 bpp_target_x16 -= bpp_decrement_x16;
3280 return bpp_target_x16;