2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
23 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
27 #include <linux/gpio/consumer.h>
28 #include <linux/gpio/machine.h>
29 #include <linux/mfd/intel_soc_pmic.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <linux/pinctrl/machine.h>
32 #include <linux/slab.h>
34 #include <asm/intel-mid.h>
35 #include <asm/unaligned.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_edid.h>
39 #include <drm/i915_drm.h>
41 #include <video/mipi_display.h>
44 #include "intel_display_types.h"
45 #include "intel_dsi.h"
46 #include "intel_sideband.h"
48 #define MIPI_TRANSFER_MODE_SHIFT 0
49 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
50 #define MIPI_PORT_SHIFT 3
52 /* base offsets for gpio pads */
53 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130
54 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
55 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
56 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140
57 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150
58 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160
59 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180
60 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190
61 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170
62 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100
63 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0
64 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0
66 #define VLV_GPIO_PCONF0(base_offset) (base_offset)
67 #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8)
74 static struct gpio_map vlv_gpio_table[] = {
75 { VLV_GPIO_NC_0_HV_DDI0_HPD },
76 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA },
77 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL },
78 { VLV_GPIO_NC_3_PANEL0_VDDEN },
79 { VLV_GPIO_NC_4_PANEL0_BKLTEN },
80 { VLV_GPIO_NC_5_PANEL0_BKLTCTL },
81 { VLV_GPIO_NC_6_HV_DDI1_HPD },
82 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA },
83 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL },
84 { VLV_GPIO_NC_9_PANEL1_VDDEN },
85 { VLV_GPIO_NC_10_PANEL1_BKLTEN },
86 { VLV_GPIO_NC_11_PANEL1_BKLTCTL },
89 struct i2c_adapter_lookup {
91 struct intel_dsi *intel_dsi;
92 acpi_handle dev_handle;
95 #define CHV_GPIO_IDX_START_N 0
96 #define CHV_GPIO_IDX_START_E 73
97 #define CHV_GPIO_IDX_START_SW 100
98 #define CHV_GPIO_IDX_START_SE 198
100 #define CHV_VBT_MAX_PINS_PER_FMLY 15
102 #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8)
103 #define CHV_GPIO_GPIOEN (1 << 15)
104 #define CHV_GPIO_GPIOCFG_GPIO (0 << 8)
105 #define CHV_GPIO_GPIOCFG_GPO (1 << 8)
106 #define CHV_GPIO_GPIOCFG_GPI (2 << 8)
107 #define CHV_GPIO_GPIOCFG_HIZ (3 << 8)
108 #define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1)
110 #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4)
111 #define CHV_GPIO_CFGLOCK (1 << 31)
113 /* ICL DSI Display GPIO Pins */
114 #define ICL_GPIO_DDSP_HPD_A 0
115 #define ICL_GPIO_L_VDDEN_1 1
116 #define ICL_GPIO_L_BKLTEN_1 2
117 #define ICL_GPIO_DDPA_CTRLCLK_1 3
118 #define ICL_GPIO_DDPA_CTRLDATA_1 4
119 #define ICL_GPIO_DDSP_HPD_B 5
120 #define ICL_GPIO_L_VDDEN_2 6
121 #define ICL_GPIO_L_BKLTEN_2 7
122 #define ICL_GPIO_DDPA_CTRLCLK_2 8
123 #define ICL_GPIO_DDPA_CTRLDATA_2 9
125 static inline enum port intel_dsi_seq_port_to_port(u8 port)
127 return port ? PORT_C : PORT_A;
130 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
133 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
134 struct mipi_dsi_device *dsi_device;
135 u8 type, flags, seq_port;
144 len = *((u16 *) data);
147 seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
149 /* For DSI single link on Port A & C, the seq_port value which is
150 * parsed from Sequence Block#53 of VBT has been set to 0
151 * Now, read/write of packets for the DSI single link on Port A and
152 * Port C will based on the DVO port from VBT block 2.
154 if (intel_dsi->ports == (1 << PORT_C))
157 port = intel_dsi_seq_port_to_port(seq_port);
159 dsi_device = intel_dsi->dsi_hosts[port]->device;
161 DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port));
165 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
166 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
168 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
170 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
173 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
174 mipi_dsi_generic_write(dsi_device, NULL, 0);
176 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
177 mipi_dsi_generic_write(dsi_device, data, 1);
179 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
180 mipi_dsi_generic_write(dsi_device, data, 2);
182 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
183 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
184 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
185 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
187 case MIPI_DSI_GENERIC_LONG_WRITE:
188 mipi_dsi_generic_write(dsi_device, data, len);
190 case MIPI_DSI_DCS_SHORT_WRITE:
191 mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
193 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
194 mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
196 case MIPI_DSI_DCS_READ:
197 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
199 case MIPI_DSI_DCS_LONG_WRITE:
200 mipi_dsi_dcs_write_buffer(dsi_device, data, len);
204 if (INTEL_GEN(dev_priv) < 11)
205 vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
213 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
215 u32 delay = *((const u32 *) data);
219 usleep_range(delay, delay + 10);
225 static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
226 u8 gpio_source, u8 gpio_index, bool value)
228 struct gpio_map *map;
233 if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) {
234 DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index);
238 map = &vlv_gpio_table[gpio_index];
240 if (dev_priv->vbt.dsi.seq_version >= 3) {
241 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
242 port = IOSF_PORT_GPIO_NC;
244 if (gpio_source == 0) {
245 port = IOSF_PORT_GPIO_NC;
246 } else if (gpio_source == 1) {
247 DRM_DEBUG_KMS("SC gpio not supported\n");
250 DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
255 pconf0 = VLV_GPIO_PCONF0(map->base_offset);
256 padval = VLV_GPIO_PAD_VAL(map->base_offset);
258 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
260 /* FIXME: remove constant below */
261 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00);
266 vlv_iosf_sb_write(dev_priv, port, padval, tmp);
267 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
270 static void chv_exec_gpio(struct drm_i915_private *dev_priv,
271 u8 gpio_source, u8 gpio_index, bool value)
277 if (dev_priv->vbt.dsi.seq_version >= 3) {
278 if (gpio_index >= CHV_GPIO_IDX_START_SE) {
279 /* XXX: it's unclear whether 255->57 is part of SE. */
280 gpio_index -= CHV_GPIO_IDX_START_SE;
281 port = CHV_IOSF_PORT_GPIO_SE;
282 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) {
283 gpio_index -= CHV_GPIO_IDX_START_SW;
284 port = CHV_IOSF_PORT_GPIO_SW;
285 } else if (gpio_index >= CHV_GPIO_IDX_START_E) {
286 gpio_index -= CHV_GPIO_IDX_START_E;
287 port = CHV_IOSF_PORT_GPIO_E;
289 port = CHV_IOSF_PORT_GPIO_N;
292 /* XXX: The spec is unclear about CHV GPIO on seq v2 */
293 if (gpio_source != 0) {
294 DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
298 if (gpio_index >= CHV_GPIO_IDX_START_E) {
299 DRM_DEBUG_KMS("invalid gpio index %u for GPIO N\n",
304 port = CHV_IOSF_PORT_GPIO_N;
307 family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY;
308 gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY;
310 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index);
311 cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index);
313 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
314 vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
315 vlv_iosf_sb_write(dev_priv, port, cfg0,
316 CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO |
317 CHV_GPIO_GPIOTXSTATE(value));
318 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
321 static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
322 u8 gpio_source, u8 gpio_index, bool value)
324 /* XXX: this table is a quick ugly hack. */
325 static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
326 struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
329 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
331 value ? GPIOD_OUT_LOW :
334 if (IS_ERR_OR_NULL(gpio_desc)) {
335 DRM_ERROR("GPIO index %u request failed (%ld)\n",
336 gpio_index, PTR_ERR(gpio_desc));
340 bxt_gpio_table[gpio_index] = gpio_desc;
343 gpiod_set_value(gpio_desc, value);
346 static void icl_exec_gpio(struct drm_i915_private *dev_priv,
347 u8 gpio_source, u8 gpio_index, bool value)
349 DRM_DEBUG_KMS("Skipping ICL GPIO element execution\n");
352 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
354 struct drm_device *dev = intel_dsi->base.base.dev;
355 struct drm_i915_private *dev_priv = to_i915(dev);
356 u8 gpio_source, gpio_index = 0, gpio_number;
361 if (dev_priv->vbt.dsi.seq_version >= 3)
362 gpio_index = *data++;
364 gpio_number = *data++;
366 /* gpio source in sequence v2 only */
367 if (dev_priv->vbt.dsi.seq_version == 2)
368 gpio_source = (*data >> 1) & 3;
375 if (INTEL_GEN(dev_priv) >= 11)
376 icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
377 else if (IS_VALLEYVIEW(dev_priv))
378 vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
379 else if (IS_CHERRYVIEW(dev_priv))
380 chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
382 bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value);
388 static int i2c_adapter_lookup(struct acpi_resource *ares, void *data)
390 struct i2c_adapter_lookup *lookup = data;
391 struct intel_dsi *intel_dsi = lookup->intel_dsi;
392 struct acpi_resource_i2c_serialbus *sb;
393 struct i2c_adapter *adapter;
394 acpi_handle adapter_handle;
397 if (!i2c_acpi_get_i2c_resource(ares, &sb))
400 if (lookup->slave_addr != sb->slave_address)
403 status = acpi_get_handle(lookup->dev_handle,
404 sb->resource_source.string_ptr,
406 if (ACPI_FAILURE(status))
409 adapter = i2c_acpi_find_adapter_by_handle(adapter_handle);
411 intel_dsi->i2c_bus_num = adapter->nr;
416 static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
417 const u16 slave_addr)
419 struct drm_device *drm_dev = intel_dsi->base.base.dev;
420 struct device *dev = &drm_dev->pdev->dev;
421 struct acpi_device *acpi_dev;
422 struct list_head resource_list;
423 struct i2c_adapter_lookup lookup;
425 acpi_dev = ACPI_COMPANION(dev);
427 memset(&lookup, 0, sizeof(lookup));
428 lookup.slave_addr = slave_addr;
429 lookup.intel_dsi = intel_dsi;
430 lookup.dev_handle = acpi_device_handle(acpi_dev);
432 INIT_LIST_HEAD(&resource_list);
433 acpi_dev_get_resources(acpi_dev, &resource_list,
436 acpi_dev_free_resource_list(&resource_list);
440 static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
441 const u16 slave_addr)
446 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
448 struct drm_device *drm_dev = intel_dsi->base.base.dev;
449 struct device *dev = &drm_dev->pdev->dev;
450 struct i2c_adapter *adapter;
453 u8 vbt_i2c_bus_num = *(data + 2);
454 u16 slave_addr = *(u16 *)(data + 3);
455 u8 reg_offset = *(data + 5);
456 u8 payload_size = *(data + 6);
459 if (intel_dsi->i2c_bus_num < 0) {
460 intel_dsi->i2c_bus_num = vbt_i2c_bus_num;
461 i2c_acpi_find_adapter(intel_dsi, slave_addr);
464 adapter = i2c_get_adapter(intel_dsi->i2c_bus_num);
466 DRM_DEV_ERROR(dev, "Cannot find a valid i2c bus for xfer\n");
470 payload_data = kzalloc(payload_size + 1, GFP_KERNEL);
474 payload_data[0] = reg_offset;
475 memcpy(&payload_data[1], (data + 7), payload_size);
477 msg.addr = slave_addr;
479 msg.len = payload_size + 1;
480 msg.buf = payload_data;
482 ret = i2c_transfer(adapter, &msg, 1);
485 "Failed to xfer payload of size (%u) to reg (%u)\n",
486 payload_size, reg_offset);
490 i2c_put_adapter(adapter);
492 return data + payload_size + 7;
495 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data)
497 DRM_DEBUG_KMS("Skipping SPI element execution\n");
499 return data + *(data + 5) + 6;
502 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data)
504 #ifdef CONFIG_PMIC_OPREGION
505 u32 value, mask, reg_address;
509 /* byte 0 aka PMIC Flag is reserved */
510 i2c_address = get_unaligned_le16(data + 1);
511 reg_address = get_unaligned_le32(data + 3);
512 value = get_unaligned_le32(data + 7);
513 mask = get_unaligned_le32(data + 11);
515 ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address,
519 DRM_ERROR("%s failed, error: %d\n", __func__, ret);
521 DRM_ERROR("Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n");
527 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
529 static const fn_mipi_elem_exec exec_elem[] = {
530 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
531 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
532 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
533 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
534 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi,
535 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic,
539 * MIPI Sequence from VBT #53 parsing logic
540 * We have already separated each seqence during bios parsing
541 * Following is generic execution function for any sequence
544 static const char * const seq_name[] = {
545 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
546 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
547 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
548 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF",
549 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
550 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
551 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
552 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
553 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF",
554 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON",
555 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF",
558 static const char *sequence_name(enum mipi_seq seq_id)
560 if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id])
561 return seq_name[seq_id];
566 static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi,
567 enum mipi_seq seq_id)
569 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
571 fn_mipi_elem_exec mipi_elem_exec;
573 if (WARN_ON(seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence)))
576 data = dev_priv->vbt.dsi.sequence[seq_id];
580 WARN_ON(*data != seq_id);
582 DRM_DEBUG_KMS("Starting MIPI sequence %d - %s\n",
583 seq_id, sequence_name(seq_id));
585 /* Skip Sequence Byte. */
588 /* Skip Size of Sequence. */
589 if (dev_priv->vbt.dsi.seq_version >= 3)
593 u8 operation_byte = *data++;
594 u8 operation_size = 0;
596 if (operation_byte == MIPI_SEQ_ELEM_END)
599 if (operation_byte < ARRAY_SIZE(exec_elem))
600 mipi_elem_exec = exec_elem[operation_byte];
602 mipi_elem_exec = NULL;
604 /* Size of Operation. */
605 if (dev_priv->vbt.dsi.seq_version >= 3)
606 operation_size = *data++;
608 if (mipi_elem_exec) {
609 const u8 *next = data + operation_size;
611 data = mipi_elem_exec(intel_dsi, data);
613 /* Consistency check if we have size. */
614 if (operation_size && data != next) {
615 DRM_ERROR("Inconsistent operation size\n");
618 } else if (operation_size) {
619 /* We have size, skip. */
620 DRM_DEBUG_KMS("Unsupported MIPI operation byte %u\n",
622 data += operation_size;
624 /* No size, can't skip without parsing. */
625 DRM_ERROR("Unsupported MIPI operation byte %u\n",
632 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
633 enum mipi_seq seq_id)
635 if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel)
636 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
637 if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight)
638 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1);
640 intel_dsi_vbt_exec(intel_dsi, seq_id);
642 if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel)
643 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
644 if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight)
645 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0);
648 void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
650 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
652 /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
653 if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
659 void intel_dsi_log_params(struct intel_dsi *intel_dsi)
661 DRM_DEBUG_KMS("Pclk %d\n", intel_dsi->pclk);
662 DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi->pixel_overlap);
663 DRM_DEBUG_KMS("Lane count %d\n", intel_dsi->lane_count);
664 DRM_DEBUG_KMS("DPHY param reg 0x%x\n", intel_dsi->dphy_reg);
665 DRM_DEBUG_KMS("Video mode format %s\n",
666 intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ?
667 "non-burst with sync pulse" :
668 intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ?
669 "non-burst with sync events" :
670 intel_dsi->video_mode_format == VIDEO_MODE_BURST ?
671 "burst" : "<unknown>");
672 DRM_DEBUG_KMS("Burst mode ratio %d\n", intel_dsi->burst_mode_ratio);
673 DRM_DEBUG_KMS("Reset timer %d\n", intel_dsi->rst_timer_val);
674 DRM_DEBUG_KMS("Eot %s\n", enableddisabled(intel_dsi->eotp_pkt));
675 DRM_DEBUG_KMS("Clockstop %s\n", enableddisabled(!intel_dsi->clock_stop));
676 DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
677 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
678 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
679 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
680 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
682 DRM_DEBUG_KMS("Dual link: NONE\n");
683 DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
684 DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
685 DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
686 DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
687 DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
688 DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
689 DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
690 DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
691 DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
692 DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
693 DRM_DEBUG_KMS("BTA %s\n",
694 enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
697 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
699 struct drm_device *dev = intel_dsi->base.base.dev;
700 struct drm_i915_private *dev_priv = to_i915(dev);
701 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
702 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
703 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
704 u16 burst_mode_ratio;
709 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
710 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
711 intel_dsi->lane_count = mipi_config->lane_cnt + 1;
712 intel_dsi->pixel_format =
713 pixel_format_from_register_bits(
714 mipi_config->videomode_color_format << 7);
716 intel_dsi->dual_link = mipi_config->dual_link;
717 intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
718 intel_dsi->operation_mode = mipi_config->is_cmd_mode;
719 intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
720 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
721 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
722 intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout;
723 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
724 intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
725 intel_dsi->init_count = mipi_config->master_init_timer;
726 intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
727 intel_dsi->video_frmt_cfg_bits =
728 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
729 intel_dsi->bgr_enabled = mipi_config->rgb_flip;
731 /* Starting point, adjusted depending on dual link and burst mode */
732 intel_dsi->pclk = mode->clock;
734 /* In dual link mode each port needs half of pixel clock */
735 if (intel_dsi->dual_link) {
736 intel_dsi->pclk /= 2;
738 /* we can enable pixel_overlap if needed by panel. In this
739 * case we need to increase the pixelclock for extra pixels
741 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
742 intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
747 * Target ddr frequency from VBT / non burst ddr freq
748 * multiply by 100 to preserve remainder
750 if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
751 if (mipi_config->target_burst_mode_freq) {
752 u32 bitrate = intel_dsi_bitrate(intel_dsi);
755 * Sometimes the VBT contains a slightly lower clock,
756 * then the bitrate we have calculated, in this case
757 * just replace it with the calculated bitrate.
759 if (mipi_config->target_burst_mode_freq < bitrate &&
760 intel_fuzzy_clock_check(
761 mipi_config->target_burst_mode_freq,
763 mipi_config->target_burst_mode_freq = bitrate;
765 if (mipi_config->target_burst_mode_freq < bitrate) {
766 DRM_ERROR("Burst mode freq is less than computed\n");
770 burst_mode_ratio = DIV_ROUND_UP(
771 mipi_config->target_burst_mode_freq * 100,
774 intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);
776 DRM_ERROR("Burst mode target is not set\n");
780 burst_mode_ratio = 100;
782 intel_dsi->burst_mode_ratio = burst_mode_ratio;
784 /* delays in VBT are in unit of 100us, so need to convert
786 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
787 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
788 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
789 intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
790 intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
791 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
793 intel_dsi->i2c_bus_num = -1;
795 /* a regular driver would get the device in probe */
796 for_each_dsi_port(port, intel_dsi->ports) {
797 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
804 * On some BYT/CHT devs some sequences are incomplete and we need to manually
805 * control some GPIOs. We need to add a GPIO lookup table before we get these.
806 * If the GOP did not initialize the panel (HDMI inserted) we may need to also
807 * change the pinmux for the SoC's PWM0 pin from GPIO to PWM.
809 static struct gpiod_lookup_table pmic_panel_gpio_table = {
810 /* Intel GFX is consumer */
811 .dev_id = "0000:00:02.0",
813 /* Panel EN/DISABLE */
814 GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH),
819 static struct gpiod_lookup_table soc_panel_gpio_table = {
820 .dev_id = "0000:00:02.0",
822 GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH),
823 GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH),
828 static const struct pinctrl_map soc_pwm_pinctrl_map[] = {
829 PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00",
833 void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on)
835 struct drm_device *dev = intel_dsi->base.base.dev;
836 struct drm_i915_private *dev_priv = to_i915(dev);
837 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
838 enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
839 bool want_backlight_gpio = false;
840 bool want_panel_gpio = false;
841 struct pinctrl *pinctrl;
844 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
845 mipi_config->pwm_blc == PPS_BLC_PMIC) {
846 gpiod_add_lookup_table(&pmic_panel_gpio_table);
847 want_panel_gpio = true;
850 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) {
851 gpiod_add_lookup_table(&soc_panel_gpio_table);
852 want_panel_gpio = true;
853 want_backlight_gpio = true;
855 /* Ensure PWM0 pin is muxed as PWM instead of GPIO */
856 ret = pinctrl_register_mappings(soc_pwm_pinctrl_map,
857 ARRAY_SIZE(soc_pwm_pinctrl_map));
859 DRM_ERROR("Failed to register pwm0 pinmux mapping\n");
861 pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0");
863 DRM_ERROR("Failed to set pinmux to PWM\n");
866 if (want_panel_gpio) {
867 intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags);
868 if (IS_ERR(intel_dsi->gpio_panel)) {
869 DRM_ERROR("Failed to own gpio for panel control\n");
870 intel_dsi->gpio_panel = NULL;
874 if (want_backlight_gpio) {
875 intel_dsi->gpio_backlight =
876 gpiod_get(dev->dev, "backlight", flags);
877 if (IS_ERR(intel_dsi->gpio_backlight)) {
878 DRM_ERROR("Failed to own gpio for backlight control\n");
879 intel_dsi->gpio_backlight = NULL;
884 void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi)
886 struct drm_device *dev = intel_dsi->base.base.dev;
887 struct drm_i915_private *dev_priv = to_i915(dev);
888 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
890 if (intel_dsi->gpio_panel) {
891 gpiod_put(intel_dsi->gpio_panel);
892 intel_dsi->gpio_panel = NULL;
895 if (intel_dsi->gpio_backlight) {
896 gpiod_put(intel_dsi->gpio_backlight);
897 intel_dsi->gpio_backlight = NULL;
900 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
901 mipi_config->pwm_blc == PPS_BLC_PMIC)
902 gpiod_remove_lookup_table(&pmic_panel_gpio_table);
904 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) {
905 pinctrl_unregister_mappings(soc_pwm_pinctrl_map);
906 gpiod_remove_lookup_table(&soc_panel_gpio_table);