drivers/gpu/drm/i915/display/intel_dpll.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/string_helpers.h>
   8
   9 #include "intel_crtc.h"
  10 #include "intel_de.h"
  11 #include "intel_display.h"
  12 #include "intel_display_types.h"
  13 #include "intel_dpll.h"
  14 #include "intel_lvds.h"
  15 #include "intel_panel.h"
  16 #include "intel_pps.h"
  17 #include "intel_snps_phy.h"
  18 #include "vlv_sideband.h"
  19
  20 struct intel_dpll_funcs {
  21         int (*crtc_compute_clock)(struct intel_atomic_state *state,
  22                                   struct intel_crtc *crtc);
  23         int (*crtc_get_shared_dpll)(struct intel_atomic_state *state,
  24                                     struct intel_crtc *crtc);
  25 };
  26
  27 struct intel_limit {
  28         struct {
  29                 int min, max;
  30         } dot, vco, n, m, m1, m2, p, p1;
  31
  32         struct {
  33                 int dot_limit;
  34                 int p2_slow, p2_fast;
  35         } p2;
  36 };
  37 static const struct intel_limit intel_limits_i8xx_dac = {
  38         .dot = { .min = 25000, .max = 350000 },
  39         .vco = { .min = 908000, .max = 1512000 },
  40         .n = { .min = 2, .max = 16 },
  41         .m = { .min = 96, .max = 140 },
  42         .m1 = { .min = 18, .max = 26 },
  43         .m2 = { .min = 6, .max = 16 },
  44         .p = { .min = 4, .max = 128 },
  45         .p1 = { .min = 2, .max = 33 },
  46         .p2 = { .dot_limit = 165000,
  47                 .p2_slow = 4, .p2_fast = 2 },
  48 };
  49
  50 static const struct intel_limit intel_limits_i8xx_dvo = {
  51         .dot = { .min = 25000, .max = 350000 },
  52         .vco = { .min = 908000, .max = 1512000 },
  53         .n = { .min = 2, .max = 16 },
  54         .m = { .min = 96, .max = 140 },
  55         .m1 = { .min = 18, .max = 26 },
  56         .m2 = { .min = 6, .max = 16 },
  57         .p = { .min = 4, .max = 128 },
  58         .p1 = { .min = 2, .max = 33 },
  59         .p2 = { .dot_limit = 165000,
  60                 .p2_slow = 4, .p2_fast = 4 },
  61 };
  62
  63 static const struct intel_limit intel_limits_i8xx_lvds = {
  64         .dot = { .min = 25000, .max = 350000 },
  65         .vco = { .min = 908000, .max = 1512000 },
  66         .n = { .min = 2, .max = 16 },
  67         .m = { .min = 96, .max = 140 },
  68         .m1 = { .min = 18, .max = 26 },
  69         .m2 = { .min = 6, .max = 16 },
  70         .p = { .min = 4, .max = 128 },
  71         .p1 = { .min = 1, .max = 6 },
  72         .p2 = { .dot_limit = 165000,
  73                 .p2_slow = 14, .p2_fast = 7 },
  74 };
  75
  76 static const struct intel_limit intel_limits_i9xx_sdvo = {
  77         .dot = { .min = 20000, .max = 400000 },
  78         .vco = { .min = 1400000, .max = 2800000 },
  79         .n = { .min = 1, .max = 6 },
  80         .m = { .min = 70, .max = 120 },
  81         .m1 = { .min = 8, .max = 18 },
  82         .m2 = { .min = 3, .max = 7 },
  83         .p = { .min = 5, .max = 80 },
  84         .p1 = { .min = 1, .max = 8 },
  85         .p2 = { .dot_limit = 200000,
  86                 .p2_slow = 10, .p2_fast = 5 },
  87 };
  88
  89 static const struct intel_limit intel_limits_i9xx_lvds = {
  90         .dot = { .min = 20000, .max = 400000 },
  91         .vco = { .min = 1400000, .max = 2800000 },
  92         .n = { .min = 1, .max = 6 },
  93         .m = { .min = 70, .max = 120 },
  94         .m1 = { .min = 8, .max = 18 },
  95         .m2 = { .min = 3, .max = 7 },
  96         .p = { .min = 7, .max = 98 },
  97         .p1 = { .min = 1, .max = 8 },
  98         .p2 = { .dot_limit = 112000,
  99                 .p2_slow = 14, .p2_fast = 7 },
 100 };
 101
 102
 103 static const struct intel_limit intel_limits_g4x_sdvo = {
 104         .dot = { .min = 25000, .max = 270000 },
 105         .vco = { .min = 1750000, .max = 3500000},
 106         .n = { .min = 1, .max = 4 },
 107         .m = { .min = 104, .max = 138 },
 108         .m1 = { .min = 17, .max = 23 },
 109         .m2 = { .min = 5, .max = 11 },
 110         .p = { .min = 10, .max = 30 },
 111         .p1 = { .min = 1, .max = 3},
 112         .p2 = { .dot_limit = 270000,
 113                 .p2_slow = 10,
 114                 .p2_fast = 10
 115         },
 116 };
 117
 118 static const struct intel_limit intel_limits_g4x_hdmi = {
 119         .dot = { .min = 22000, .max = 400000 },
 120         .vco = { .min = 1750000, .max = 3500000},
 121         .n = { .min = 1, .max = 4 },
 122         .m = { .min = 104, .max = 138 },
 123         .m1 = { .min = 16, .max = 23 },
 124         .m2 = { .min = 5, .max = 11 },
 125         .p = { .min = 5, .max = 80 },
 126         .p1 = { .min = 1, .max = 8},
 127         .p2 = { .dot_limit = 165000,
 128                 .p2_slow = 10, .p2_fast = 5 },
 129 };
 130
 131 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 132         .dot = { .min = 20000, .max = 115000 },
 133         .vco = { .min = 1750000, .max = 3500000 },
 134         .n = { .min = 1, .max = 3 },
 135         .m = { .min = 104, .max = 138 },
 136         .m1 = { .min = 17, .max = 23 },
 137         .m2 = { .min = 5, .max = 11 },
 138         .p = { .min = 28, .max = 112 },
 139         .p1 = { .min = 2, .max = 8 },
 140         .p2 = { .dot_limit = 0,
 141                 .p2_slow = 14, .p2_fast = 14
 142         },
 143 };
 144
 145 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 146         .dot = { .min = 80000, .max = 224000 },
 147         .vco = { .min = 1750000, .max = 3500000 },
 148         .n = { .min = 1, .max = 3 },
 149         .m = { .min = 104, .max = 138 },
 150         .m1 = { .min = 17, .max = 23 },
 151         .m2 = { .min = 5, .max = 11 },
 152         .p = { .min = 14, .max = 42 },
 153         .p1 = { .min = 2, .max = 6 },
 154         .p2 = { .dot_limit = 0,
 155                 .p2_slow = 7, .p2_fast = 7
 156         },
 157 };
 158
 159 static const struct intel_limit pnv_limits_sdvo = {
 160         .dot = { .min = 20000, .max = 400000},
 161         .vco = { .min = 1700000, .max = 3500000 },
 162         /* Pineview's Ncounter is a ring counter */
 163         .n = { .min = 3, .max = 6 },
 164         .m = { .min = 2, .max = 256 },
 165         /* Pineview only has one combined m divider, which we treat as m2. */
 166         .m1 = { .min = 0, .max = 0 },
 167         .m2 = { .min = 0, .max = 254 },
 168         .p = { .min = 5, .max = 80 },
 169         .p1 = { .min = 1, .max = 8 },
 170         .p2 = { .dot_limit = 200000,
 171                 .p2_slow = 10, .p2_fast = 5 },
 172 };
 173
 174 static const struct intel_limit pnv_limits_lvds = {
 175         .dot = { .min = 20000, .max = 400000 },
 176         .vco = { .min = 1700000, .max = 3500000 },
 177         .n = { .min = 3, .max = 6 },
 178         .m = { .min = 2, .max = 256 },
 179         .m1 = { .min = 0, .max = 0 },
 180         .m2 = { .min = 0, .max = 254 },
 181         .p = { .min = 7, .max = 112 },
 182         .p1 = { .min = 1, .max = 8 },
 183         .p2 = { .dot_limit = 112000,
 184                 .p2_slow = 14, .p2_fast = 14 },
 185 };
 186
 187 /* Ironlake / Sandybridge
 188  *
 189  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 190  * the range value for them is (actual_value - 2).
 191  */
 192 static const struct intel_limit ilk_limits_dac = {
 193         .dot = { .min = 25000, .max = 350000 },
 194         .vco = { .min = 1760000, .max = 3510000 },
 195         .n = { .min = 1, .max = 5 },
 196         .m = { .min = 79, .max = 127 },
 197         .m1 = { .min = 12, .max = 22 },
 198         .m2 = { .min = 5, .max = 9 },
 199         .p = { .min = 5, .max = 80 },
 200         .p1 = { .min = 1, .max = 8 },
 201         .p2 = { .dot_limit = 225000,
 202                 .p2_slow = 10, .p2_fast = 5 },
 203 };
 204
 205 static const struct intel_limit ilk_limits_single_lvds = {
 206         .dot = { .min = 25000, .max = 350000 },
 207         .vco = { .min = 1760000, .max = 3510000 },
 208         .n = { .min = 1, .max = 3 },
 209         .m = { .min = 79, .max = 118 },
 210         .m1 = { .min = 12, .max = 22 },
 211         .m2 = { .min = 5, .max = 9 },
 212         .p = { .min = 28, .max = 112 },
 213         .p1 = { .min = 2, .max = 8 },
 214         .p2 = { .dot_limit = 225000,
 215                 .p2_slow = 14, .p2_fast = 14 },
 216 };
 217
 218 static const struct intel_limit ilk_limits_dual_lvds = {
 219         .dot = { .min = 25000, .max = 350000 },
 220         .vco = { .min = 1760000, .max = 3510000 },
 221         .n = { .min = 1, .max = 3 },
 222         .m = { .min = 79, .max = 127 },
 223         .m1 = { .min = 12, .max = 22 },
 224         .m2 = { .min = 5, .max = 9 },
 225         .p = { .min = 14, .max = 56 },
 226         .p1 = { .min = 2, .max = 8 },
 227         .p2 = { .dot_limit = 225000,
 228                 .p2_slow = 7, .p2_fast = 7 },
 229 };
 230
 231 /* LVDS 100mhz refclk limits. */
 232 static const struct intel_limit ilk_limits_single_lvds_100m = {
 233         .dot = { .min = 25000, .max = 350000 },
 234         .vco = { .min = 1760000, .max = 3510000 },
 235         .n = { .min = 1, .max = 2 },
 236         .m = { .min = 79, .max = 126 },
 237         .m1 = { .min = 12, .max = 22 },
 238         .m2 = { .min = 5, .max = 9 },
 239         .p = { .min = 28, .max = 112 },
 240         .p1 = { .min = 2, .max = 8 },
 241         .p2 = { .dot_limit = 225000,
 242                 .p2_slow = 14, .p2_fast = 14 },
 243 };
 244
 245 static const struct intel_limit ilk_limits_dual_lvds_100m = {
 246         .dot = { .min = 25000, .max = 350000 },
 247         .vco = { .min = 1760000, .max = 3510000 },
 248         .n = { .min = 1, .max = 3 },
 249         .m = { .min = 79, .max = 126 },
 250         .m1 = { .min = 12, .max = 22 },
 251         .m2 = { .min = 5, .max = 9 },
 252         .p = { .min = 14, .max = 42 },
 253         .p1 = { .min = 2, .max = 6 },
 254         .p2 = { .dot_limit = 225000,
 255                 .p2_slow = 7, .p2_fast = 7 },
 256 };
 257
 258 static const struct intel_limit intel_limits_vlv = {
 259          /*
 260           * These are based on the data rate limits (measured in fast clocks)
 261           * since those are the strictest limits we have. The fast
 262           * clock and actual rate limits are more relaxed, so checking
 263           * them would make no difference.
 264           */
 265         .dot = { .min = 25000, .max = 270000 },
 266         .vco = { .min = 4000000, .max = 6000000 },
 267         .n = { .min = 1, .max = 7 },
 268         .m1 = { .min = 2, .max = 3 },
 269         .m2 = { .min = 11, .max = 156 },
 270         .p1 = { .min = 2, .max = 3 },
 271         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 272 };
 273
 274 static const struct intel_limit intel_limits_chv = {
 275         /*
 276          * These are based on the data rate limits (measured in fast clocks)
 277          * since those are the strictest limits we have.  The fast
 278          * clock and actual rate limits are more relaxed, so checking
 279          * them would make no difference.
 280          */
 281         .dot = { .min = 25000, .max = 540000 },
 282         .vco = { .min = 4800000, .max = 6480000 },
 283         .n = { .min = 1, .max = 1 },
 284         .m1 = { .min = 2, .max = 2 },
 285         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 286         .p1 = { .min = 2, .max = 4 },
 287         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 288 };
 289
 290 static const struct intel_limit intel_limits_bxt = {
 291         .dot = { .min = 25000, .max = 594000 },
 292         .vco = { .min = 4800000, .max = 6700000 },
 293         .n = { .min = 1, .max = 1 },
 294         .m1 = { .min = 2, .max = 2 },
 295         /* FIXME: find real m2 limits */
 296         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 297         .p1 = { .min = 2, .max = 4 },
 298         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 299 };
 300
 301 /*
 302  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 303  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 304  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 305  * The helpers' return value is the rate of the clock that is fed to the
 306  * display engine's pipe which can be the above fast dot clock rate or a
 307  * divided-down version of it.
 308  */
 309 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 310 int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 311 {
 312         clock->m = clock->m2 + 2;
 313         clock->p = clock->p1 * clock->p2;
 314         if (WARN_ON(clock->n == 0 || clock->p == 0))
 315                 return 0;
 316         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 317         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 318
 319         return clock->dot;
 320 }
 321
 322 static u32 i9xx_dpll_compute_m(const struct dpll *dpll)
 323 {
 324         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 325 }
 326
 327 int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 328 {
 329         clock->m = i9xx_dpll_compute_m(clock);
 330         clock->p = clock->p1 * clock->p2;
 331         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 332                 return 0;
 333         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 334         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 335
 336         return clock->dot;
 337 }
 338
 339 int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 340 {
 341         clock->m = clock->m1 * clock->m2;
 342         clock->p = clock->p1 * clock->p2 * 5;
 343         if (WARN_ON(clock->n == 0 || clock->p == 0))
 344                 return 0;
 345         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 346         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 347
 348         return clock->dot;
 349 }
 350
 351 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 352 {
 353         clock->m = clock->m1 * clock->m2;
 354         clock->p = clock->p1 * clock->p2 * 5;
 355         if (WARN_ON(clock->n == 0 || clock->p == 0))
 356                 return 0;
 357         clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
 358                                            clock->n << 22);
 359         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 360
 361         return clock->dot;
 362 }
 363
 364 /*
 365  * Returns whether the given set of divisors are valid for a given refclk with
 366  * the given connectors.
 367  */
 368 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv,
 369                                const struct intel_limit *limit,
 370                                const struct dpll *clock)
 371 {
 372         if (clock->n < limit->n.min || limit->n.max < clock->n)
 373                 return false;
 374         if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
 375                 return false;
 376         if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
 377                 return false;
 378         if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
 379                 return false;
 380
 381         if (!IS_PINEVIEW(dev_priv) && !IS_LP(dev_priv))
 382                 if (clock->m1 <= clock->m2)
 383                         return false;
 384
 385         if (!IS_LP(dev_priv)) {
 386                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 387                         return false;
 388                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 389                         return false;
 390         }
 391
 392         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 393                 return false;
 394         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 395          * connector, etc., rather than just a single range.
 396          */
 397         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 398                 return false;
 399
 400         return true;
 401 }
 402
 403 static int
 404 i9xx_select_p2_div(const struct intel_limit *limit,
 405                    const struct intel_crtc_state *crtc_state,
 406                    int target)
 407 {
 408         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 409
 410         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 411                 /*
 412                  * For LVDS just rely on its current settings for dual-channel.
 413                  * We haven't figured out how to reliably set up different
 414                  * single/dual channel state, if we even can.
 415                  */
 416                 if (intel_is_dual_link_lvds(dev_priv))
 417                         return limit->p2.p2_fast;
 418                 else
 419                         return limit->p2.p2_slow;
 420         } else {
 421                 if (target < limit->p2.dot_limit)
 422                         return limit->p2.p2_slow;
 423                 else
 424                         return limit->p2.p2_fast;
 425         }
 426 }
 427
 428 /*
 429  * Returns a set of divisors for the desired target clock with the given
 430  * refclk, or FALSE.
 431  *
 432  * Target and reference clocks are specified in kHz.
 433  *
 434  * If match_clock is provided, then best_clock P divider must match the P
 435  * divider from @match_clock used for LVDS downclocking.
 436  */
 437 static bool
 438 i9xx_find_best_dpll(const struct intel_limit *limit,
 439                     struct intel_crtc_state *crtc_state,
 440                     int target, int refclk,
 441                     const struct dpll *match_clock,
 442                     struct dpll *best_clock)
 443 {
 444         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 445         struct dpll clock;
 446         int err = target;
 447
 448         memset(best_clock, 0, sizeof(*best_clock));
 449
 450         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 451
 452         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 453              clock.m1++) {
 454                 for (clock.m2 = limit->m2.min;
 455                      clock.m2 <= limit->m2.max; clock.m2++) {
 456                         if (clock.m2 >= clock.m1)
 457                                 break;
 458                         for (clock.n = limit->n.min;
 459                              clock.n <= limit->n.max; clock.n++) {
 460                                 for (clock.p1 = limit->p1.min;
 461                                         clock.p1 <= limit->p1.max; clock.p1++) {
 462                                         int this_err;
 463
 464                                         i9xx_calc_dpll_params(refclk, &clock);
 465                                         if (!intel_pll_is_valid(to_i915(dev),
 466                                                                 limit,
 467                                                                 &clock))
 468                                                 continue;
 469                                         if (match_clock &&
 470                                             clock.p != match_clock->p)
 471                                                 continue;
 472
 473                                         this_err = abs(clock.dot - target);
 474                                         if (this_err < err) {
 475                                                 *best_clock = clock;
 476                                                 err = this_err;
 477                                         }
 478                                 }
 479                         }
 480                 }
 481         }
 482
 483         return (err != target);
 484 }
 485
 486 /*
 487  * Returns a set of divisors for the desired target clock with the given
 488  * refclk, or FALSE.
 489  *
 490  * Target and reference clocks are specified in kHz.
 491  *
 492  * If match_clock is provided, then best_clock P divider must match the P
 493  * divider from @match_clock used for LVDS downclocking.
 494  */
 495 static bool
 496 pnv_find_best_dpll(const struct intel_limit *limit,
 497                    struct intel_crtc_state *crtc_state,
 498                    int target, int refclk,
 499                    const struct dpll *match_clock,
 500                    struct dpll *best_clock)
 501 {
 502         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 503         struct dpll clock;
 504         int err = target;
 505
 506         memset(best_clock, 0, sizeof(*best_clock));
 507
 508         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 509
 510         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 511              clock.m1++) {
 512                 for (clock.m2 = limit->m2.min;
 513                      clock.m2 <= limit->m2.max; clock.m2++) {
 514                         for (clock.n = limit->n.min;
 515                              clock.n <= limit->n.max; clock.n++) {
 516                                 for (clock.p1 = limit->p1.min;
 517                                         clock.p1 <= limit->p1.max; clock.p1++) {
 518                                         int this_err;
 519
 520                                         pnv_calc_dpll_params(refclk, &clock);
 521                                         if (!intel_pll_is_valid(to_i915(dev),
 522                                                                 limit,
 523                                                                 &clock))
 524                                                 continue;
 525                                         if (match_clock &&
 526                                             clock.p != match_clock->p)
 527                                                 continue;
 528
 529                                         this_err = abs(clock.dot - target);
 530                                         if (this_err < err) {
 531                                                 *best_clock = clock;
 532                                                 err = this_err;
 533                                         }
 534                                 }
 535                         }
 536                 }
 537         }
 538
 539         return (err != target);
 540 }
 541
 542 /*
 543  * Returns a set of divisors for the desired target clock with the given
 544  * refclk, or FALSE.
 545  *
 546  * Target and reference clocks are specified in kHz.
 547  *
 548  * If match_clock is provided, then best_clock P divider must match the P
 549  * divider from @match_clock used for LVDS downclocking.
 550  */
 551 static bool
 552 g4x_find_best_dpll(const struct intel_limit *limit,
 553                    struct intel_crtc_state *crtc_state,
 554                    int target, int refclk,
 555                    const struct dpll *match_clock,
 556                    struct dpll *best_clock)
 557 {
 558         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 559         struct dpll clock;
 560         int max_n;
 561         bool found = false;
 562         /* approximately equals target * 0.00585 */
 563         int err_most = (target >> 8) + (target >> 9);
 564
 565         memset(best_clock, 0, sizeof(*best_clock));
 566
 567         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 568
 569         max_n = limit->n.max;
 570         /* based on hardware requirement, prefer smaller n to precision */
 571         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 572                 /* based on hardware requirement, prefere larger m1,m2 */
 573                 for (clock.m1 = limit->m1.max;
 574                      clock.m1 >= limit->m1.min; clock.m1--) {
 575                         for (clock.m2 = limit->m2.max;
 576                              clock.m2 >= limit->m2.min; clock.m2--) {
 577                                 for (clock.p1 = limit->p1.max;
 578                                      clock.p1 >= limit->p1.min; clock.p1--) {
 579                                         int this_err;
 580
 581                                         i9xx_calc_dpll_params(refclk, &clock);
 582                                         if (!intel_pll_is_valid(to_i915(dev),
 583                                                                 limit,
 584                                                                 &clock))
 585                                                 continue;
 586
 587                                         this_err = abs(clock.dot - target);
 588                                         if (this_err < err_most) {
 589                                                 *best_clock = clock;
 590                                                 err_most = this_err;
 591                                                 max_n = clock.n;
 592                                                 found = true;
 593                                         }
 594                                 }
 595                         }
 596                 }
 597         }
 598         return found;
 599 }
 600
 601 /*
 602  * Check if the calculated PLL configuration is more optimal compared to the
 603  * best configuration and error found so far. Return the calculated error.
 604  */
 605 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 606                                const struct dpll *calculated_clock,
 607                                const struct dpll *best_clock,
 608                                unsigned int best_error_ppm,
 609                                unsigned int *error_ppm)
 610 {
 611         /*
 612          * For CHV ignore the error and consider only the P value.
 613          * Prefer a bigger P value based on HW requirements.
 614          */
 615         if (IS_CHERRYVIEW(to_i915(dev))) {
 616                 *error_ppm = 0;
 617
 618                 return calculated_clock->p > best_clock->p;
 619         }
 620
 621         if (drm_WARN_ON_ONCE(dev, !target_freq))
 622                 return false;
 623
 624         *error_ppm = div_u64(1000000ULL *
 625                                 abs(target_freq - calculated_clock->dot),
 626                              target_freq);
 627         /*
 628          * Prefer a better P value over a better (smaller) error if the error
 629          * is small. Ensure this preference for future configurations too by
 630          * setting the error to 0.
 631          */
 632         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 633                 *error_ppm = 0;
 634
 635                 return true;
 636         }
 637
 638         return *error_ppm + 10 < best_error_ppm;
 639 }
 640
 641 /*
 642  * Returns a set of divisors for the desired target clock with the given
 643  * refclk, or FALSE.
 644  */
 645 static bool
 646 vlv_find_best_dpll(const struct intel_limit *limit,
 647                    struct intel_crtc_state *crtc_state,
 648                    int target, int refclk,
 649                    const struct dpll *match_clock,
 650                    struct dpll *best_clock)
 651 {
 652         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 653         struct drm_device *dev = crtc->base.dev;
 654         struct dpll clock;
 655         unsigned int bestppm = 1000000;
 656         /* min update 19.2 MHz */
 657         int max_n = min(limit->n.max, refclk / 19200);
 658         bool found = false;
 659
 660         memset(best_clock, 0, sizeof(*best_clock));
 661
 662         /* based on hardware requirement, prefer smaller n to precision */
 663         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 664                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 665                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 666                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 667                                 clock.p = clock.p1 * clock.p2 * 5;
 668                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 669                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 670                                         unsigned int ppm;
 671
 672                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 673                                                                      refclk * clock.m1);
 674
 675                                         vlv_calc_dpll_params(refclk, &clock);
 676
 677                                         if (!intel_pll_is_valid(to_i915(dev),
 678                                                                 limit,
 679                                                                 &clock))
 680                                                 continue;
 681
 682                                         if (!vlv_PLL_is_optimal(dev, target,
 683                                                                 &clock,
 684                                                                 best_clock,
 685                                                                 bestppm, &ppm))
 686                                                 continue;
 687
 688                                         *best_clock = clock;
 689                                         bestppm = ppm;
 690                                         found = true;
 691                                 }
 692                         }
 693                 }
 694         }
 695
 696         return found;
 697 }
 698
 699 /*
 700  * Returns a set of divisors for the desired target clock with the given
 701  * refclk, or FALSE.
 702  */
 703 static bool
 704 chv_find_best_dpll(const struct intel_limit *limit,
 705                    struct intel_crtc_state *crtc_state,
 706                    int target, int refclk,
 707                    const struct dpll *match_clock,
 708                    struct dpll *best_clock)
 709 {
 710         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 711         struct drm_device *dev = crtc->base.dev;
 712         unsigned int best_error_ppm;
 713         struct dpll clock;
 714         u64 m2;
 715         int found = false;
 716
 717         memset(best_clock, 0, sizeof(*best_clock));
 718         best_error_ppm = 1000000;
 719
 720         /*
 721          * Based on hardware doc, the n always set to 1, and m1 always
 722          * set to 2.  If requires to support 200Mhz refclk, we need to
 723          * revisit this because n may not 1 anymore.
 724          */
 725         clock.n = 1;
 726         clock.m1 = 2;
 727
 728         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 729                 for (clock.p2 = limit->p2.p2_fast;
 730                                 clock.p2 >= limit->p2.p2_slow;
 731                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 732                         unsigned int error_ppm;
 733
 734                         clock.p = clock.p1 * clock.p2 * 5;
 735
 736                         m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
 737                                                    refclk * clock.m1);
 738
 739                         if (m2 > INT_MAX/clock.m1)
 740                                 continue;
 741
 742                         clock.m2 = m2;
 743
 744                         chv_calc_dpll_params(refclk, &clock);
 745
 746                         if (!intel_pll_is_valid(to_i915(dev), limit, &clock))
 747                                 continue;
 748
 749                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 750                                                 best_error_ppm, &error_ppm))
 751                                 continue;
 752
 753                         *best_clock = clock;
 754                         best_error_ppm = error_ppm;
 755                         found = true;
 756                 }
 757         }
 758
 759         return found;
 760 }
 761
 762 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
 763                         struct dpll *best_clock)
 764 {
 765         const struct intel_limit *limit = &intel_limits_bxt;
 766         int refclk = 100000;
 767
 768         return chv_find_best_dpll(limit, crtc_state,
 769                                   crtc_state->port_clock, refclk,
 770                                   NULL, best_clock);
 771 }
 772
 773 u32 i9xx_dpll_compute_fp(const struct dpll *dpll)
 774 {
 775         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
 776 }
 777
 778 static u32 pnv_dpll_compute_fp(const struct dpll *dpll)
 779 {
 780         return (1 << dpll->n) << 16 | dpll->m2;
 781 }
 782
 783 static void i9xx_update_pll_dividers(struct intel_crtc_state *crtc_state,
 784                                      const struct dpll *clock,
 785                                      const struct dpll *reduced_clock)
 786 {
 787         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 788         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 789         u32 fp, fp2;
 790
 791         if (IS_PINEVIEW(dev_priv)) {
 792                 fp = pnv_dpll_compute_fp(clock);
 793                 fp2 = pnv_dpll_compute_fp(reduced_clock);
 794         } else {
 795                 fp = i9xx_dpll_compute_fp(clock);
 796                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
 797         }
 798
 799         crtc_state->dpll_hw_state.fp0 = fp;
 800         crtc_state->dpll_hw_state.fp1 = fp2;
 801 }
 802
 803 static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,
 804                               const struct dpll *clock,
 805                               const struct dpll *reduced_clock)
 806 {
 807         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 808         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 809         u32 dpll;
 810
 811         i9xx_update_pll_dividers(crtc_state, clock, reduced_clock);
 812
 813         dpll = DPLL_VGA_MODE_DIS;
 814
 815         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
 816                 dpll |= DPLLB_MODE_LVDS;
 817         else
 818                 dpll |= DPLLB_MODE_DAC_SERIAL;
 819
 820         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
 821             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
 822                 dpll |= (crtc_state->pixel_multiplier - 1)
 823                         << SDVO_MULTIPLIER_SHIFT_HIRES;
 824         }
 825
 826         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
 827             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 828                 dpll |= DPLL_SDVO_HIGH_SPEED;
 829
 830         if (intel_crtc_has_dp_encoder(crtc_state))
 831                 dpll |= DPLL_SDVO_HIGH_SPEED;
 832
 833         /* compute bitmask from p1 value */
 834         if (IS_G4X(dev_priv)) {
 835                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
 836                 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
 837         } else if (IS_PINEVIEW(dev_priv)) {
 838                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
 839                 WARN_ON(reduced_clock->p1 != clock->p1);
 840         } else {
 841                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
 842                 WARN_ON(reduced_clock->p1 != clock->p1);
 843         }
 844
 845         switch (clock->p2) {
 846         case 5:
 847                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
 848                 break;
 849         case 7:
 850                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
 851                 break;
 852         case 10:
 853                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
 854                 break;
 855         case 14:
 856                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
 857                 break;
 858         }
 859         WARN_ON(reduced_clock->p2 != clock->p2);
 860
 861         if (DISPLAY_VER(dev_priv) >= 4)
 862                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
 863
 864         if (crtc_state->sdvo_tv_clock)
 865                 dpll |= PLL_REF_INPUT_TVCLKINBC;
 866         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
 867                  intel_panel_use_ssc(dev_priv))
 868                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
 869         else
 870                 dpll |= PLL_REF_INPUT_DREFCLK;
 871
 872         dpll |= DPLL_VCO_ENABLE;
 873         crtc_state->dpll_hw_state.dpll = dpll;
 874
 875         if (DISPLAY_VER(dev_priv) >= 4) {
 876                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
 877                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
 878                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
 879         }
 880 }
 881
 882 static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
 883                               const struct dpll *clock,
 884                               const struct dpll *reduced_clock)
 885 {
 886         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 887         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 888         u32 dpll;
 889
 890         i9xx_update_pll_dividers(crtc_state, clock, reduced_clock);
 891
 892         dpll = DPLL_VGA_MODE_DIS;
 893
 894         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 895                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
 896         } else {
 897                 if (clock->p1 == 2)
 898                         dpll |= PLL_P1_DIVIDE_BY_TWO;
 899                 else
 900                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
 901                 if (clock->p2 == 4)
 902                         dpll |= PLL_P2_DIVIDE_BY_4;
 903         }
 904         WARN_ON(reduced_clock->p1 != clock->p1);
 905         WARN_ON(reduced_clock->p2 != clock->p2);
 906
 907         /*
 908          * Bspec:
 909          * "[Almador Errata}: For the correct operation of the muxed DVO pins
 910          *  (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
 911          *  GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
 912          *  Enable) must be set to “1” in both the DPLL A Control Register
 913          *  (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
 914          *
 915          * For simplicity We simply keep both bits always enabled in
 916          * both DPLLS. The spec says we should disable the DVO 2X clock
 917          * when not needed, but this seems to work fine in practice.
 918          */
 919         if (IS_I830(dev_priv) ||
 920             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
 921                 dpll |= DPLL_DVO_2X_MODE;
 922
 923         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
 924             intel_panel_use_ssc(dev_priv))
 925                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
 926         else
 927                 dpll |= PLL_REF_INPUT_DREFCLK;
 928
 929         dpll |= DPLL_VCO_ENABLE;
 930         crtc_state->dpll_hw_state.dpll = dpll;
 931 }
 932
 933 static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
 934                                   struct intel_crtc *crtc)
 935 {
 936         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 937         struct intel_crtc_state *crtc_state =
 938                 intel_atomic_get_new_crtc_state(state, crtc);
 939         struct intel_encoder *encoder =
 940                 intel_get_crtc_new_encoder(state, crtc_state);
 941
 942         if (DISPLAY_VER(dev_priv) < 11 &&
 943             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
 944                 return 0;
 945
 946         return intel_compute_shared_dplls(state, crtc, encoder);
 947 }
 948
 949 static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
 950                                     struct intel_crtc *crtc)
 951 {
 952         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 953         struct intel_crtc_state *crtc_state =
 954                 intel_atomic_get_new_crtc_state(state, crtc);
 955         struct intel_encoder *encoder =
 956                 intel_get_crtc_new_encoder(state, crtc_state);
 957
 958         if (DISPLAY_VER(dev_priv) < 11 &&
 959             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
 960                 return 0;
 961
 962         return intel_reserve_shared_dplls(state, crtc, encoder);
 963 }
 964
 965 static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
 966                                   struct intel_crtc *crtc)
 967 {
 968         struct intel_crtc_state *crtc_state =
 969                 intel_atomic_get_new_crtc_state(state, crtc);
 970         struct intel_encoder *encoder =
 971                 intel_get_crtc_new_encoder(state, crtc_state);
 972
 973         return intel_mpllb_calc_state(crtc_state, encoder);
 974 }
 975
 976 static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
 977 {
 978         return dpll->m < factor * dpll->n;
 979 }
 980
 981 static void ilk_update_pll_dividers(struct intel_crtc_state *crtc_state,
 982                                     const struct dpll *clock,
 983                                     const struct dpll *reduced_clock)
 984 {
 985         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 986         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 987         u32 fp, fp2;
 988         int factor;
 989
 990         /* Enable autotuning of the PLL clock (if permissible) */
 991         factor = 21;
 992         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 993                 if ((intel_panel_use_ssc(dev_priv) &&
 994                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
 995                     (HAS_PCH_IBX(dev_priv) &&
 996                      intel_is_dual_link_lvds(dev_priv)))
 997                         factor = 25;
 998         } else if (crtc_state->sdvo_tv_clock) {
 999                 factor = 20;
1000         }
1001
1002         fp = i9xx_dpll_compute_fp(clock);
1003         if (ilk_needs_fb_cb_tune(clock, factor))
1004                 fp |= FP_CB_TUNE;
1005
1006         fp2 = i9xx_dpll_compute_fp(reduced_clock);
1007         if (ilk_needs_fb_cb_tune(reduced_clock, factor))
1008                 fp2 |= FP_CB_TUNE;
1009
1010         crtc_state->dpll_hw_state.fp0 = fp;
1011         crtc_state->dpll_hw_state.fp1 = fp2;
1012 }
1013
1014 static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,
1015                              const struct dpll *clock,
1016                              const struct dpll *reduced_clock)
1017 {
1018         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1019         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1020         u32 dpll;
1021
1022         ilk_update_pll_dividers(crtc_state, clock, reduced_clock);
1023
1024         dpll = 0;
1025
1026         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
1027                 dpll |= DPLLB_MODE_LVDS;
1028         else
1029                 dpll |= DPLLB_MODE_DAC_SERIAL;
1030
1031         dpll |= (crtc_state->pixel_multiplier - 1)
1032                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
1033
1034         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
1035             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1036                 dpll |= DPLL_SDVO_HIGH_SPEED;
1037
1038         if (intel_crtc_has_dp_encoder(crtc_state))
1039                 dpll |= DPLL_SDVO_HIGH_SPEED;
1040
1041         /*
1042          * The high speed IO clock is only really required for
1043          * SDVO/HDMI/DP, but we also enable it for CRT to make it
1044          * possible to share the DPLL between CRT and HDMI. Enabling
1045          * the clock needlessly does no real harm, except use up a
1046          * bit of power potentially.
1047          *
1048          * We'll limit this to IVB with 3 pipes, since it has only two
1049          * DPLLs and so DPLL sharing is the only way to get three pipes
1050          * driving PCH ports at the same time. On SNB we could do this,
1051          * and potentially avoid enabling the second DPLL, but it's not
1052          * clear if it''s a win or loss power wise. No point in doing
1053          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
1054          */
1055         if (INTEL_NUM_PIPES(dev_priv) == 3 &&
1056             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1057                 dpll |= DPLL_SDVO_HIGH_SPEED;
1058
1059         /* compute bitmask from p1 value */
1060         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1061         /* also FPA1 */
1062         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
1063
1064         switch (clock->p2) {
1065         case 5:
1066                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
1067                 break;
1068         case 7:
1069                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
1070                 break;
1071         case 10:
1072                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
1073                 break;
1074         case 14:
1075                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
1076                 break;
1077         }
1078         WARN_ON(reduced_clock->p2 != clock->p2);
1079
1080         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
1081             intel_panel_use_ssc(dev_priv))
1082                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1083         else
1084                 dpll |= PLL_REF_INPUT_DREFCLK;
1085
1086         dpll |= DPLL_VCO_ENABLE;
1087
1088         crtc_state->dpll_hw_state.dpll = dpll;
1089 }
1090
1091 static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
1092                                   struct intel_crtc *crtc)
1093 {
1094         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1095         struct intel_crtc_state *crtc_state =
1096                 intel_atomic_get_new_crtc_state(state, crtc);
1097         const struct intel_limit *limit;
1098         int refclk = 120000;
1099
1100         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
1101         if (!crtc_state->has_pch_encoder)
1102                 return 0;
1103
1104         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1105                 if (intel_panel_use_ssc(dev_priv)) {
1106                         drm_dbg_kms(&dev_priv->drm,
1107                                     "using SSC reference clock of %d kHz\n",
1108                                     dev_priv->vbt.lvds_ssc_freq);
1109                         refclk = dev_priv->vbt.lvds_ssc_freq;
1110                 }
1111
1112                 if (intel_is_dual_link_lvds(dev_priv)) {
1113                         if (refclk == 100000)
1114                                 limit = &ilk_limits_dual_lvds_100m;
1115                         else
1116                                 limit = &ilk_limits_dual_lvds;
1117                 } else {
1118                         if (refclk == 100000)
1119                                 limit = &ilk_limits_single_lvds_100m;
1120                         else
1121                                 limit = &ilk_limits_single_lvds;
1122                 }
1123         } else {
1124                 limit = &ilk_limits_dac;
1125         }
1126
1127         if (!crtc_state->clock_set &&
1128             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1129                                 refclk, NULL, &crtc_state->dpll))
1130                 return -EINVAL;
1131
1132         ilk_compute_dpll(crtc_state, &crtc_state->dpll,
1133                          &crtc_state->dpll);
1134
1135         return intel_compute_shared_dplls(state, crtc, NULL);
1136 }
1137
1138 static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
1139                                     struct intel_crtc *crtc)
1140 {
1141         struct intel_crtc_state *crtc_state =
1142                 intel_atomic_get_new_crtc_state(state, crtc);
1143
1144         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
1145         if (!crtc_state->has_pch_encoder)
1146                 return 0;
1147
1148         return intel_reserve_shared_dplls(state, crtc, NULL);
1149 }
1150
1151 void vlv_compute_dpll(struct intel_crtc_state *crtc_state)
1152 {
1153         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1154
1155         crtc_state->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
1156                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1157         if (crtc->pipe != PIPE_A)
1158                 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1159
1160         /* DPLL not used with DSI, but still need the rest set up */
1161         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1162                 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
1163                         DPLL_EXT_BUFFER_ENABLE_VLV;
1164
1165         crtc_state->dpll_hw_state.dpll_md =
1166                 (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1167 }
1168
1169 void chv_compute_dpll(struct intel_crtc_state *crtc_state)
1170 {
1171         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1172
1173         crtc_state->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
1174                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1175         if (crtc->pipe != PIPE_A)
1176                 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1177
1178         /* DPLL not used with DSI, but still need the rest set up */
1179         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1180                 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
1181
1182         crtc_state->dpll_hw_state.dpll_md =
1183                 (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1184 }
1185
1186 static int chv_crtc_compute_clock(struct intel_atomic_state *state,
1187                                   struct intel_crtc *crtc)
1188 {
1189         struct intel_crtc_state *crtc_state =
1190                 intel_atomic_get_new_crtc_state(state, crtc);
1191         const struct intel_limit *limit = &intel_limits_chv;
1192         int refclk = 100000;
1193
1194         if (!crtc_state->clock_set &&
1195             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1196                                 refclk, NULL, &crtc_state->dpll))
1197                 return -EINVAL;
1198
1199         chv_compute_dpll(crtc_state);
1200
1201         return 0;
1202 }
1203
1204 static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
1205                                   struct intel_crtc *crtc)
1206 {
1207         struct intel_crtc_state *crtc_state =
1208                 intel_atomic_get_new_crtc_state(state, crtc);
1209         const struct intel_limit *limit = &intel_limits_vlv;
1210         int refclk = 100000;
1211
1212         if (!crtc_state->clock_set &&
1213             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1214                                 refclk, NULL, &crtc_state->dpll)) {
1215                 return -EINVAL;
1216         }
1217
1218         vlv_compute_dpll(crtc_state);
1219
1220         return 0;
1221 }
1222
1223 static int g4x_crtc_compute_clock(struct intel_atomic_state *state,
1224                                   struct intel_crtc *crtc)
1225 {
1226         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1227         struct intel_crtc_state *crtc_state =
1228                 intel_atomic_get_new_crtc_state(state, crtc);
1229         const struct intel_limit *limit;
1230         int refclk = 96000;
1231
1232         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1233                 if (intel_panel_use_ssc(dev_priv)) {
1234                         refclk = dev_priv->vbt.lvds_ssc_freq;
1235                         drm_dbg_kms(&dev_priv->drm,
1236                                     "using SSC reference clock of %d kHz\n",
1237                                     refclk);
1238                 }
1239
1240                 if (intel_is_dual_link_lvds(dev_priv))
1241                         limit = &intel_limits_g4x_dual_channel_lvds;
1242                 else
1243                         limit = &intel_limits_g4x_single_channel_lvds;
1244         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
1245                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1246                 limit = &intel_limits_g4x_hdmi;
1247         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
1248                 limit = &intel_limits_g4x_sdvo;
1249         } else {
1250                 /* The option is for other outputs */
1251                 limit = &intel_limits_i9xx_sdvo;
1252         }
1253
1254         if (!crtc_state->clock_set &&
1255             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1256                                 refclk, NULL, &crtc_state->dpll))
1257                 return -EINVAL;
1258
1259         i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
1260                           &crtc_state->dpll);
1261
1262         return 0;
1263 }
1264
1265 static int pnv_crtc_compute_clock(struct intel_atomic_state *state,
1266                                   struct intel_crtc *crtc)
1267 {
1268         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1269         struct intel_crtc_state *crtc_state =
1270                 intel_atomic_get_new_crtc_state(state, crtc);
1271         const struct intel_limit *limit;
1272         int refclk = 96000;
1273
1274         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1275                 if (intel_panel_use_ssc(dev_priv)) {
1276                         refclk = dev_priv->vbt.lvds_ssc_freq;
1277                         drm_dbg_kms(&dev_priv->drm,
1278                                     "using SSC reference clock of %d kHz\n",
1279                                     refclk);
1280                 }
1281
1282                 limit = &pnv_limits_lvds;
1283         } else {
1284                 limit = &pnv_limits_sdvo;
1285         }
1286
1287         if (!crtc_state->clock_set &&
1288             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1289                                 refclk, NULL, &crtc_state->dpll))
1290                 return -EINVAL;
1291
1292         i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
1293                           &crtc_state->dpll);
1294
1295         return 0;
1296 }
1297
1298 static int i9xx_crtc_compute_clock(struct intel_atomic_state *state,
1299                                    struct intel_crtc *crtc)
1300 {
1301         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1302         struct intel_crtc_state *crtc_state =
1303                 intel_atomic_get_new_crtc_state(state, crtc);
1304         const struct intel_limit *limit;
1305         int refclk = 96000;
1306
1307         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1308                 if (intel_panel_use_ssc(dev_priv)) {
1309                         refclk = dev_priv->vbt.lvds_ssc_freq;
1310                         drm_dbg_kms(&dev_priv->drm,
1311                                     "using SSC reference clock of %d kHz\n",
1312                                     refclk);
1313                 }
1314
1315                 limit = &intel_limits_i9xx_lvds;
1316         } else {
1317                 limit = &intel_limits_i9xx_sdvo;
1318         }
1319
1320         if (!crtc_state->clock_set &&
1321             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1322                                  refclk, NULL, &crtc_state->dpll))
1323                 return -EINVAL;
1324
1325         i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
1326                           &crtc_state->dpll);
1327
1328         return 0;
1329 }
1330
1331 static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
1332                                    struct intel_crtc *crtc)
1333 {
1334         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1335         struct intel_crtc_state *crtc_state =
1336                 intel_atomic_get_new_crtc_state(state, crtc);
1337         const struct intel_limit *limit;
1338         int refclk = 48000;
1339
1340         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1341                 if (intel_panel_use_ssc(dev_priv)) {
1342                         refclk = dev_priv->vbt.lvds_ssc_freq;
1343                         drm_dbg_kms(&dev_priv->drm,
1344                                     "using SSC reference clock of %d kHz\n",
1345                                     refclk);
1346                 }
1347
1348                 limit = &intel_limits_i8xx_lvds;
1349         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
1350                 limit = &intel_limits_i8xx_dvo;
1351         } else {
1352                 limit = &intel_limits_i8xx_dac;
1353         }
1354
1355         if (!crtc_state->clock_set &&
1356             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1357                                  refclk, NULL, &crtc_state->dpll))
1358                 return -EINVAL;
1359
1360         i8xx_compute_dpll(crtc_state, &crtc_state->dpll,
1361                           &crtc_state->dpll);
1362
1363         return 0;
1364 }
1365
1366 static const struct intel_dpll_funcs dg2_dpll_funcs = {
1367         .crtc_compute_clock = dg2_crtc_compute_clock,
1368 };
1369
1370 static const struct intel_dpll_funcs hsw_dpll_funcs = {
1371         .crtc_compute_clock = hsw_crtc_compute_clock,
1372         .crtc_get_shared_dpll = hsw_crtc_get_shared_dpll,
1373 };
1374
1375 static const struct intel_dpll_funcs ilk_dpll_funcs = {
1376         .crtc_compute_clock = ilk_crtc_compute_clock,
1377         .crtc_get_shared_dpll = ilk_crtc_get_shared_dpll,
1378 };
1379
1380 static const struct intel_dpll_funcs chv_dpll_funcs = {
1381         .crtc_compute_clock = chv_crtc_compute_clock,
1382 };
1383
1384 static const struct intel_dpll_funcs vlv_dpll_funcs = {
1385         .crtc_compute_clock = vlv_crtc_compute_clock,
1386 };
1387
1388 static const struct intel_dpll_funcs g4x_dpll_funcs = {
1389         .crtc_compute_clock = g4x_crtc_compute_clock,
1390 };
1391
1392 static const struct intel_dpll_funcs pnv_dpll_funcs = {
1393         .crtc_compute_clock = pnv_crtc_compute_clock,
1394 };
1395
1396 static const struct intel_dpll_funcs i9xx_dpll_funcs = {
1397         .crtc_compute_clock = i9xx_crtc_compute_clock,
1398 };
1399
1400 static const struct intel_dpll_funcs i8xx_dpll_funcs = {
1401         .crtc_compute_clock = i8xx_crtc_compute_clock,
1402 };
1403
1404 int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
1405                                   struct intel_crtc *crtc)
1406 {
1407         struct drm_i915_private *i915 = to_i915(state->base.dev);
1408         struct intel_crtc_state *crtc_state =
1409                 intel_atomic_get_new_crtc_state(state, crtc);
1410         int ret;
1411
1412         drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
1413
1414         if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll))
1415                 return 0;
1416
1417         memset(&crtc_state->dpll_hw_state, 0,
1418                sizeof(crtc_state->dpll_hw_state));
1419
1420         if (!crtc_state->hw.enable)
1421                 return 0;
1422
1423         ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc);
1424         if (ret) {
1425                 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n",
1426                             crtc->base.base.id, crtc->base.name);
1427                 return ret;
1428         }
1429
1430         return 0;
1431 }
1432
1433 int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
1434                                     struct intel_crtc *crtc)
1435 {
1436         struct drm_i915_private *i915 = to_i915(state->base.dev);
1437         struct intel_crtc_state *crtc_state =
1438                 intel_atomic_get_new_crtc_state(state, crtc);
1439         int ret;
1440
1441         drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
1442
1443         if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll))
1444                 return 0;
1445
1446         if (!crtc_state->hw.enable)
1447                 return 0;
1448
1449         if (!i915->display.funcs.dpll->crtc_get_shared_dpll)
1450                 return 0;
1451
1452         ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc);
1453         if (ret) {
1454                 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",
1455                             crtc->base.base.id, crtc->base.name);
1456                 return ret;
1457         }
1458
1459         return 0;
1460 }
1461
1462 void
1463 intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
1464 {
1465         if (IS_DG2(dev_priv))
1466                 dev_priv->display.funcs.dpll = &dg2_dpll_funcs;
1467         else if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
1468                 dev_priv->display.funcs.dpll = &hsw_dpll_funcs;
1469         else if (HAS_PCH_SPLIT(dev_priv))
1470                 dev_priv->display.funcs.dpll = &ilk_dpll_funcs;
1471         else if (IS_CHERRYVIEW(dev_priv))
1472                 dev_priv->display.funcs.dpll = &chv_dpll_funcs;
1473         else if (IS_VALLEYVIEW(dev_priv))
1474                 dev_priv->display.funcs.dpll = &vlv_dpll_funcs;
1475         else if (IS_G4X(dev_priv))
1476                 dev_priv->display.funcs.dpll = &g4x_dpll_funcs;
1477         else if (IS_PINEVIEW(dev_priv))
1478                 dev_priv->display.funcs.dpll = &pnv_dpll_funcs;
1479         else if (DISPLAY_VER(dev_priv) != 2)
1480                 dev_priv->display.funcs.dpll = &i9xx_dpll_funcs;
1481         else
1482                 dev_priv->display.funcs.dpll = &i8xx_dpll_funcs;
1483 }
1484
1485 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1486 {
1487         if (IS_I830(dev_priv))
1488                 return false;
1489
1490         return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1491 }
1492
1493 void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
1494 {
1495         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1496         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1497         u32 dpll = crtc_state->dpll_hw_state.dpll;
1498         enum pipe pipe = crtc->pipe;
1499         int i;
1500
1501         assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1502
1503         /* PLL is protected by panel, make sure we can write it */
1504         if (i9xx_has_pps(dev_priv))
1505                 assert_pps_unlocked(dev_priv, pipe);
1506
1507         intel_de_write(dev_priv, FP0(pipe), crtc_state->dpll_hw_state.fp0);
1508         intel_de_write(dev_priv, FP1(pipe), crtc_state->dpll_hw_state.fp1);
1509
1510         /*
1511          * Apparently we need to have VGA mode enabled prior to changing
1512          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1513          * dividers, even though the register value does change.
1514          */
1515         intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
1516         intel_de_write(dev_priv, DPLL(pipe), dpll);
1517
1518         /* Wait for the clocks to stabilize. */
1519         intel_de_posting_read(dev_priv, DPLL(pipe));
1520         udelay(150);
1521
1522         if (DISPLAY_VER(dev_priv) >= 4) {
1523                 intel_de_write(dev_priv, DPLL_MD(pipe),
1524                                crtc_state->dpll_hw_state.dpll_md);
1525         } else {
1526                 /* The pixel multiplier can only be updated once the
1527                  * DPLL is enabled and the clocks are stable.
1528                  *
1529                  * So write it again.
1530                  */
1531                 intel_de_write(dev_priv, DPLL(pipe), dpll);
1532         }
1533
1534         /* We do this three times for luck */
1535         for (i = 0; i < 3; i++) {
1536                 intel_de_write(dev_priv, DPLL(pipe), dpll);
1537                 intel_de_posting_read(dev_priv, DPLL(pipe));
1538                 udelay(150); /* wait for warmup */
1539         }
1540 }
1541
1542 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
1543                                  enum pipe pipe)
1544 {
1545         u32 reg_val;
1546
1547         /*
1548          * PLLB opamp always calibrates to max value of 0x3f, force enable it
1549          * and set it to a reasonable value instead.
1550          */
1551         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
1552         reg_val &= 0xffffff00;
1553         reg_val |= 0x00000030;
1554         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
1555
1556         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
1557         reg_val &= 0x00ffffff;
1558         reg_val |= 0x8c000000;
1559         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
1560
1561         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
1562         reg_val &= 0xffffff00;
1563         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
1564
1565         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
1566         reg_val &= 0x00ffffff;
1567         reg_val |= 0xb0000000;
1568         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
1569 }
1570
1571 static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
1572 {
1573         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1574         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1575         enum pipe pipe = crtc->pipe;
1576         u32 mdiv;
1577         u32 bestn, bestm1, bestm2, bestp1, bestp2;
1578         u32 coreclk, reg_val;
1579
1580         vlv_dpio_get(dev_priv);
1581
1582         bestn = crtc_state->dpll.n;
1583         bestm1 = crtc_state->dpll.m1;
1584         bestm2 = crtc_state->dpll.m2;
1585         bestp1 = crtc_state->dpll.p1;
1586         bestp2 = crtc_state->dpll.p2;
1587
1588         /* See eDP HDMI DPIO driver vbios notes doc */
1589
1590         /* PLL B needs special handling */
1591         if (pipe == PIPE_B)
1592                 vlv_pllb_recal_opamp(dev_priv, pipe);
1593
1594         /* Set up Tx target for periodic Rcomp update */
1595         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
1596
1597         /* Disable target IRef on PLL */
1598         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
1599         reg_val &= 0x00ffffff;
1600         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
1601
1602         /* Disable fast lock */
1603         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
1604
1605         /* Set idtafcrecal before PLL is enabled */
1606         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
1607         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
1608         mdiv |= ((bestn << DPIO_N_SHIFT));
1609         mdiv |= (1 << DPIO_K_SHIFT);
1610
1611         /*
1612          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
1613          * but we don't support that).
1614          * Note: don't use the DAC post divider as it seems unstable.
1615          */
1616         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
1617         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
1618
1619         mdiv |= DPIO_ENABLE_CALIBRATION;
1620         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
1621
1622         /* Set HBR and RBR LPF coefficients */
1623         if (crtc_state->port_clock == 162000 ||
1624             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) ||
1625             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1626                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
1627                                  0x009f0003);
1628         else
1629                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
1630                                  0x00d0000f);
1631
1632         if (intel_crtc_has_dp_encoder(crtc_state)) {
1633                 /* Use SSC source */
1634                 if (pipe == PIPE_A)
1635                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
1636                                          0x0df40000);
1637                 else
1638                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
1639                                          0x0df70000);
1640         } else { /* HDMI or VGA */
1641                 /* Use bend source */
1642                 if (pipe == PIPE_A)
1643                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
1644                                          0x0df70000);
1645                 else
1646                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
1647                                          0x0df40000);
1648         }
1649
1650         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
1651         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
1652         if (intel_crtc_has_dp_encoder(crtc_state))
1653                 coreclk |= 0x01000000;
1654         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
1655
1656         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
1657
1658         vlv_dpio_put(dev_priv);
1659 }
1660
1661 static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state)
1662 {
1663         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1664         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1665         enum pipe pipe = crtc->pipe;
1666
1667         intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll);
1668         intel_de_posting_read(dev_priv, DPLL(pipe));
1669         udelay(150);
1670
1671         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1672                 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
1673 }
1674
1675 void vlv_enable_pll(const struct intel_crtc_state *crtc_state)
1676 {
1677         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1678         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1679         enum pipe pipe = crtc->pipe;
1680
1681         assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1682
1683         /* PLL is protected by panel, make sure we can write it */
1684         assert_pps_unlocked(dev_priv, pipe);
1685
1686         /* Enable Refclk */
1687         intel_de_write(dev_priv, DPLL(pipe),
1688                        crtc_state->dpll_hw_state.dpll &
1689                        ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
1690
1691         if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) {
1692                 vlv_prepare_pll(crtc_state);
1693                 _vlv_enable_pll(crtc_state);
1694         }
1695
1696         intel_de_write(dev_priv, DPLL_MD(pipe),
1697                        crtc_state->dpll_hw_state.dpll_md);
1698         intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1699 }
1700
1701 static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
1702 {
1703         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1704         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1705         enum pipe pipe = crtc->pipe;
1706         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1707         u32 loopfilter, tribuf_calcntr;
1708         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
1709         u32 dpio_val;
1710         int vco;
1711
1712         bestn = crtc_state->dpll.n;
1713         bestm2_frac = crtc_state->dpll.m2 & 0x3fffff;
1714         bestm1 = crtc_state->dpll.m1;
1715         bestm2 = crtc_state->dpll.m2 >> 22;
1716         bestp1 = crtc_state->dpll.p1;
1717         bestp2 = crtc_state->dpll.p2;
1718         vco = crtc_state->dpll.vco;
1719         dpio_val = 0;
1720         loopfilter = 0;
1721
1722         vlv_dpio_get(dev_priv);
1723
1724         /* p1 and p2 divider */
1725         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
1726                         5 << DPIO_CHV_S1_DIV_SHIFT |
1727                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
1728                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
1729                         1 << DPIO_CHV_K_DIV_SHIFT);
1730
1731         /* Feedback post-divider - m2 */
1732         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
1733
1734         /* Feedback refclk divider - n and m1 */
1735         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
1736                         DPIO_CHV_M1_DIV_BY_2 |
1737                         1 << DPIO_CHV_N_DIV_SHIFT);
1738
1739         /* M2 fraction division */
1740         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
1741
1742         /* M2 fraction division enable */
1743         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
1744         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
1745         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
1746         if (bestm2_frac)
1747                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
1748         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
1749
1750         /* Program digital lock detect threshold */
1751         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
1752         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
1753                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
1754         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
1755         if (!bestm2_frac)
1756                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
1757         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
1758
1759         /* Loop filter */
1760         if (vco == 5400000) {
1761                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
1762                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
1763                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
1764                 tribuf_calcntr = 0x9;
1765         } else if (vco <= 6200000) {
1766                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
1767                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
1768                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
1769                 tribuf_calcntr = 0x9;
1770         } else if (vco <= 6480000) {
1771                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
1772                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
1773                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
1774                 tribuf_calcntr = 0x8;
1775         } else {
1776                 /* Not supported. Apply the same limits as in the max case */
1777                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
1778                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
1779                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
1780                 tribuf_calcntr = 0;
1781         }
1782         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
1783
1784         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
1785         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
1786         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
1787         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
1788
1789         /* AFC Recal */
1790         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
1791                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
1792                         DPIO_AFC_RECAL);
1793
1794         vlv_dpio_put(dev_priv);
1795 }
1796
1797 static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)
1798 {
1799         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1800         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1801         enum pipe pipe = crtc->pipe;
1802         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1803         u32 tmp;
1804
1805         vlv_dpio_get(dev_priv);
1806
1807         /* Enable back the 10bit clock to display controller */
1808         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1809         tmp |= DPIO_DCLKP_EN;
1810         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1811
1812         vlv_dpio_put(dev_priv);
1813
1814         /*
1815          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1816          */
1817         udelay(1);
1818
1819         /* Enable PLL */
1820         intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll);
1821
1822         /* Check PLL is locked */
1823         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1824                 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
1825 }
1826
1827 void chv_enable_pll(const struct intel_crtc_state *crtc_state)
1828 {
1829         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1830         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1831         enum pipe pipe = crtc->pipe;
1832
1833         assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1834
1835         /* PLL is protected by panel, make sure we can write it */
1836         assert_pps_unlocked(dev_priv, pipe);
1837
1838         /* Enable Refclk and SSC */
1839         intel_de_write(dev_priv, DPLL(pipe),
1840                        crtc_state->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
1841
1842         if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) {
1843                 chv_prepare_pll(crtc_state);
1844                 _chv_enable_pll(crtc_state);
1845         }
1846
1847         if (pipe != PIPE_A) {
1848                 /*
1849                  * WaPixelRepeatModeFixForC0:chv
1850                  *
1851                  * DPLLCMD is AWOL. Use chicken bits to propagate
1852                  * the value from DPLLBMD to either pipe B or C.
1853                  */
1854                 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1855                 intel_de_write(dev_priv, DPLL_MD(PIPE_B),
1856                                crtc_state->dpll_hw_state.dpll_md);
1857                 intel_de_write(dev_priv, CBR4_VLV, 0);
1858                 dev_priv->chv_dpll_md[pipe] = crtc_state->dpll_hw_state.dpll_md;
1859
1860                 /*
1861                  * DPLLB VGA mode also seems to cause problems.
1862                  * We should always have it disabled.
1863                  */
1864                 drm_WARN_ON(&dev_priv->drm,
1865                             (intel_de_read(dev_priv, DPLL(PIPE_B)) &
1866                              DPLL_VGA_MODE_DIS) == 0);
1867         } else {
1868                 intel_de_write(dev_priv, DPLL_MD(pipe),
1869                                crtc_state->dpll_hw_state.dpll_md);
1870                 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1871         }
1872 }
1873
1874 /**
1875  * vlv_force_pll_on - forcibly enable just the PLL
1876  * @dev_priv: i915 private structure
1877  * @pipe: pipe PLL to enable
1878  * @dpll: PLL configuration
1879  *
1880  * Enable the PLL for @pipe using the supplied @dpll config. To be used
1881  * in cases where we need the PLL enabled even when @pipe is not going to
1882  * be enabled.
1883  */
1884 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1885                      const struct dpll *dpll)
1886 {
1887         struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
1888         struct intel_crtc_state *crtc_state;
1889
1890         crtc_state = intel_crtc_state_alloc(crtc);
1891         if (!crtc_state)
1892                 return -ENOMEM;
1893
1894         crtc_state->cpu_transcoder = (enum transcoder)pipe;
1895         crtc_state->pixel_multiplier = 1;
1896         crtc_state->dpll = *dpll;
1897         crtc_state->output_types = BIT(INTEL_OUTPUT_EDP);
1898
1899         if (IS_CHERRYVIEW(dev_priv)) {
1900                 chv_compute_dpll(crtc_state);
1901                 chv_enable_pll(crtc_state);
1902         } else {
1903                 vlv_compute_dpll(crtc_state);
1904                 vlv_enable_pll(crtc_state);
1905         }
1906
1907         kfree(crtc_state);
1908
1909         return 0;
1910 }
1911
1912 void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1913 {
1914         u32 val;
1915
1916         /* Make sure the pipe isn't still relying on us */
1917         assert_transcoder_disabled(dev_priv, (enum transcoder)pipe);
1918
1919         val = DPLL_INTEGRATED_REF_CLK_VLV |
1920                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1921         if (pipe != PIPE_A)
1922                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1923
1924         intel_de_write(dev_priv, DPLL(pipe), val);
1925         intel_de_posting_read(dev_priv, DPLL(pipe));
1926 }
1927
1928 void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1929 {
1930         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1931         u32 val;
1932
1933         /* Make sure the pipe isn't still relying on us */
1934         assert_transcoder_disabled(dev_priv, (enum transcoder)pipe);
1935
1936         val = DPLL_SSC_REF_CLK_CHV |
1937                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1938         if (pipe != PIPE_A)
1939                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1940
1941         intel_de_write(dev_priv, DPLL(pipe), val);
1942         intel_de_posting_read(dev_priv, DPLL(pipe));
1943
1944         vlv_dpio_get(dev_priv);
1945
1946         /* Disable 10bit clock to display controller */
1947         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1948         val &= ~DPIO_DCLKP_EN;
1949         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1950
1951         vlv_dpio_put(dev_priv);
1952 }
1953
1954 void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1955 {
1956         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1957         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1958         enum pipe pipe = crtc->pipe;
1959
1960         /* Don't disable pipe or pipe PLLs if needed */
1961         if (IS_I830(dev_priv))
1962                 return;
1963
1964         /* Make sure the pipe isn't still relying on us */
1965         assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1966
1967         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
1968         intel_de_posting_read(dev_priv, DPLL(pipe));
1969 }
1970
1971
1972 /**
1973  * vlv_force_pll_off - forcibly disable just the PLL
1974  * @dev_priv: i915 private structure
1975  * @pipe: pipe PLL to disable
1976  *
1977  * Disable the PLL for @pipe. To be used in cases where we need
1978  * the PLL enabled even when @pipe is not going to be enabled.
1979  */
1980 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
1981 {
1982         if (IS_CHERRYVIEW(dev_priv))
1983                 chv_disable_pll(dev_priv, pipe);
1984         else
1985                 vlv_disable_pll(dev_priv, pipe);
1986 }
1987
1988 /* Only for pre-ILK configs */
1989 static void assert_pll(struct drm_i915_private *dev_priv,
1990                        enum pipe pipe, bool state)
1991 {
1992         bool cur_state;
1993
1994         cur_state = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
1995         I915_STATE_WARN(cur_state != state,
1996                         "PLL state assertion failure (expected %s, current %s)\n",
1997                         str_on_off(state), str_on_off(cur_state));
1998 }
1999
2000 void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe)
2001 {
2002         assert_pll(i915, pipe, true);
2003 }
2004
2005 void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe)
2006 {
2007         assert_pll(i915, pipe, false);
2008 }