drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/slab.h>
  32 #include <linux/types.h>
  33
  34 #include <asm/byteorder.h>
  35
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_dp_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_probe_helper.h>
  41
  42 #include "i915_debugfs.h"
  43 #include "i915_drv.h"
  44 #include "i915_trace.h"
  45 #include "intel_atomic.h"
  46 #include "intel_audio.h"
  47 #include "intel_connector.h"
  48 #include "intel_ddi.h"
  49 #include "intel_display_types.h"
  50 #include "intel_dp.h"
  51 #include "intel_dp_link_training.h"
  52 #include "intel_dp_mst.h"
  53 #include "intel_dpio_phy.h"
  54 #include "intel_fifo_underrun.h"
  55 #include "intel_hdcp.h"
  56 #include "intel_hdmi.h"
  57 #include "intel_hotplug.h"
  58 #include "intel_lspcon.h"
  59 #include "intel_lvds.h"
  60 #include "intel_panel.h"
  61 #include "intel_psr.h"
  62 #include "intel_sideband.h"
  63 #include "intel_tc.h"
  64 #include "intel_vdsc.h"
  65
  66 #define DP_DPRX_ESI_LEN 14
  67
  68 /* DP DSC throughput values used for slice count calculations KPixels/s */
  69 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  70 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  71 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  72
  73 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  74 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  75
  76 /* Compliance test status bits  */
  77 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  78 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  79 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  80 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  81
  82 struct dp_link_dpll {
  83         int clock;
  84         struct dpll dpll;
  85 };
  86
  87 static const struct dp_link_dpll g4x_dpll[] = {
  88         { 162000,
  89                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  90         { 270000,
  91                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  92 };
  93
  94 static const struct dp_link_dpll pch_dpll[] = {
  95         { 162000,
  96                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  97         { 270000,
  98                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  99 };
 100
 101 static const struct dp_link_dpll vlv_dpll[] = {
 102         { 162000,
 103                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
 104         { 270000,
 105                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
 106 };
 107
 108 /*
 109  * CHV supports eDP 1.4 that have  more link rates.
 110  * Below only provides the fixed rate but exclude variable rate.
 111  */
 112 static const struct dp_link_dpll chv_dpll[] = {
 113         /*
 114          * CHV requires to program fractional division for m2.
 115          * m2 is stored in fixed point format using formula below
 116          * (m2_int << 22) | m2_fraction
 117          */
 118         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
 119                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
 120         { 270000,       /* m2_int = 27, m2_fraction = 0 */
 121                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
 122 };
 123
 124 /* Constants for DP DSC configurations */
 125 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 126
 127 /* With Single pipe configuration, HW is capable of supporting maximum
 128  * of 4 slices per line.
 129  */
 130 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 131
 132 /**
 133  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 134  * @intel_dp: DP struct
 135  *
 136  * If a CPU or PCH DP output is attached to an eDP panel, this function
 137  * will return true, and false otherwise.
 138  */
 139 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 140 {
 141         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 142
 143         return dig_port->base.type == INTEL_OUTPUT_EDP;
 144 }
 145
 146 static void intel_dp_link_down(struct intel_encoder *encoder,
 147                                const struct intel_crtc_state *old_crtc_state);
 148 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 149 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 150 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 151                                            const struct intel_crtc_state *crtc_state);
 152 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 153                                       enum pipe pipe);
 154 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 155
 156 /* update sink rates from dpcd */
 157 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 158 {
 159         static const int dp_rates[] = {
 160                 162000, 270000, 540000, 810000
 161         };
 162         int i, max_rate;
 163         int max_lttpr_rate;
 164
 165         if (drm_dp_has_quirk(&intel_dp->desc, 0,
 166                              DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 167                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 168                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 169
 170                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 171                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 172
 173                 return;
 174         }
 175
 176         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 177         max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 178         if (max_lttpr_rate)
 179                 max_rate = min(max_rate, max_lttpr_rate);
 180
 181         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 182                 if (dp_rates[i] > max_rate)
 183                         break;
 184                 intel_dp->sink_rates[i] = dp_rates[i];
 185         }
 186
 187         intel_dp->num_sink_rates = i;
 188 }
 189
 190 /* Get length of rates array potentially limited by max_rate. */
 191 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 192 {
 193         int i;
 194
 195         /* Limit results by potentially reduced max rate */
 196         for (i = 0; i < len; i++) {
 197                 if (rates[len - i - 1] <= max_rate)
 198                         return len - i;
 199         }
 200
 201         return 0;
 202 }
 203
 204 /* Get length of common rates array potentially limited by max_rate. */
 205 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 206                                           int max_rate)
 207 {
 208         return intel_dp_rate_limit_len(intel_dp->common_rates,
 209                                        intel_dp->num_common_rates, max_rate);
 210 }
 211
 212 /* Theoretical max between source and sink */
 213 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 214 {
 215         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 216 }
 217
 218 /* Theoretical max between source and sink */
 219 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 220 {
 221         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 222         int source_max = dig_port->max_lanes;
 223         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 224         int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
 225         int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 226
 227         if (lttpr_max)
 228                 sink_max = min(sink_max, lttpr_max);
 229
 230         return min3(source_max, sink_max, fia_max);
 231 }
 232
 233 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 234 {
 235         return intel_dp->max_link_lane_count;
 236 }
 237
 238 int
 239 intel_dp_link_required(int pixel_clock, int bpp)
 240 {
 241         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 242         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 243 }
 244
 245 int
 246 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 247 {
 248         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 249          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 250          * is transmitted every LS_Clk per lane, there is no need to account for
 251          * the channel encoding that is done in the PHY layer here.
 252          */
 253
 254         return max_link_clock * max_lanes;
 255 }
 256
 257 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 258 {
 259         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 260         struct intel_encoder *encoder = &intel_dig_port->base;
 261         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 262
 263         return INTEL_GEN(dev_priv) >= 12 ||
 264                 (INTEL_GEN(dev_priv) == 11 &&
 265                  encoder->port != PORT_A);
 266 }
 267
 268 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 269 {
 270         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 271         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 272         enum port port = dig_port->base.port;
 273
 274         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 275
 276         /* Low voltage SKUs are limited to max of 5.4G */
 277         if (voltage == VOLTAGE_INFO_0_85V)
 278                 return 540000;
 279
 280         /* For this SKU 8.1G is supported in all ports */
 281         if (IS_CNL_WITH_PORT_F(dev_priv))
 282                 return 810000;
 283
 284         /* For other SKUs, max rate on ports A and D is 5.4G */
 285         if (port == PORT_A || port == PORT_D)
 286                 return 540000;
 287
 288         return 810000;
 289 }
 290
 291 static int icl_max_source_rate(struct intel_dp *intel_dp)
 292 {
 293         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 294         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 295         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 296
 297         if (intel_phy_is_combo(dev_priv, phy) &&
 298             !intel_dp_is_edp(intel_dp))
 299                 return 540000;
 300
 301         return 810000;
 302 }
 303
 304 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 305 {
 306         if (intel_dp_is_edp(intel_dp))
 307                 return 540000;
 308
 309         return 810000;
 310 }
 311
 312 static void
 313 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 314 {
 315         /* The values must be in increasing order */
 316         static const int cnl_rates[] = {
 317                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 318         };
 319         static const int bxt_rates[] = {
 320                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 321         };
 322         static const int skl_rates[] = {
 323                 162000, 216000, 270000, 324000, 432000, 540000
 324         };
 325         static const int hsw_rates[] = {
 326                 162000, 270000, 540000
 327         };
 328         static const int g4x_rates[] = {
 329                 162000, 270000
 330         };
 331         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 332         struct intel_encoder *encoder = &dig_port->base;
 333         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 334         const int *source_rates;
 335         int size, max_rate = 0, vbt_max_rate;
 336
 337         /* This should only be done once */
 338         drm_WARN_ON(&dev_priv->drm,
 339                     intel_dp->source_rates || intel_dp->num_source_rates);
 340
 341         if (INTEL_GEN(dev_priv) >= 10) {
 342                 source_rates = cnl_rates;
 343                 size = ARRAY_SIZE(cnl_rates);
 344                 if (IS_GEN(dev_priv, 10))
 345                         max_rate = cnl_max_source_rate(intel_dp);
 346                 else if (IS_JSL_EHL(dev_priv))
 347                         max_rate = ehl_max_source_rate(intel_dp);
 348                 else
 349                         max_rate = icl_max_source_rate(intel_dp);
 350         } else if (IS_GEN9_LP(dev_priv)) {
 351                 source_rates = bxt_rates;
 352                 size = ARRAY_SIZE(bxt_rates);
 353         } else if (IS_GEN9_BC(dev_priv)) {
 354                 source_rates = skl_rates;
 355                 size = ARRAY_SIZE(skl_rates);
 356         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 357                    IS_BROADWELL(dev_priv)) {
 358                 source_rates = hsw_rates;
 359                 size = ARRAY_SIZE(hsw_rates);
 360         } else {
 361                 source_rates = g4x_rates;
 362                 size = ARRAY_SIZE(g4x_rates);
 363         }
 364
 365         vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
 366         if (max_rate && vbt_max_rate)
 367                 max_rate = min(max_rate, vbt_max_rate);
 368         else if (vbt_max_rate)
 369                 max_rate = vbt_max_rate;
 370
 371         if (max_rate)
 372                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 373
 374         intel_dp->source_rates = source_rates;
 375         intel_dp->num_source_rates = size;
 376 }
 377
 378 static int intersect_rates(const int *source_rates, int source_len,
 379                            const int *sink_rates, int sink_len,
 380                            int *common_rates)
 381 {
 382         int i = 0, j = 0, k = 0;
 383
 384         while (i < source_len && j < sink_len) {
 385                 if (source_rates[i] == sink_rates[j]) {
 386                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 387                                 return k;
 388                         common_rates[k] = source_rates[i];
 389                         ++k;
 390                         ++i;
 391                         ++j;
 392                 } else if (source_rates[i] < sink_rates[j]) {
 393                         ++i;
 394                 } else {
 395                         ++j;
 396                 }
 397         }
 398         return k;
 399 }
 400
 401 /* return index of rate in rates array, or -1 if not found */
 402 static int intel_dp_rate_index(const int *rates, int len, int rate)
 403 {
 404         int i;
 405
 406         for (i = 0; i < len; i++)
 407                 if (rate == rates[i])
 408                         return i;
 409
 410         return -1;
 411 }
 412
 413 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 414 {
 415         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 416
 417         drm_WARN_ON(&i915->drm,
 418                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 419
 420         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 421                                                      intel_dp->num_source_rates,
 422                                                      intel_dp->sink_rates,
 423                                                      intel_dp->num_sink_rates,
 424                                                      intel_dp->common_rates);
 425
 426         /* Paranoia, there should always be something in common. */
 427         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 428                 intel_dp->common_rates[0] = 162000;
 429                 intel_dp->num_common_rates = 1;
 430         }
 431 }
 432
 433 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 434                                        u8 lane_count)
 435 {
 436         /*
 437          * FIXME: we need to synchronize the current link parameters with
 438          * hardware readout. Currently fast link training doesn't work on
 439          * boot-up.
 440          */
 441         if (link_rate == 0 ||
 442             link_rate > intel_dp->max_link_rate)
 443                 return false;
 444
 445         if (lane_count == 0 ||
 446             lane_count > intel_dp_max_lane_count(intel_dp))
 447                 return false;
 448
 449         return true;
 450 }
 451
 452 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 453                                                      int link_rate,
 454                                                      u8 lane_count)
 455 {
 456         const struct drm_display_mode *fixed_mode =
 457                 intel_dp->attached_connector->panel.fixed_mode;
 458         int mode_rate, max_rate;
 459
 460         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 461         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 462         if (mode_rate > max_rate)
 463                 return false;
 464
 465         return true;
 466 }
 467
 468 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 469                                             int link_rate, u8 lane_count)
 470 {
 471         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 472         int index;
 473
 474         /*
 475          * TODO: Enable fallback on MST links once MST link compute can handle
 476          * the fallback params.
 477          */
 478         if (intel_dp->is_mst) {
 479                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 480                 return -1;
 481         }
 482
 483         index = intel_dp_rate_index(intel_dp->common_rates,
 484                                     intel_dp->num_common_rates,
 485                                     link_rate);
 486         if (index > 0) {
 487                 if (intel_dp_is_edp(intel_dp) &&
 488                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 489                                                               intel_dp->common_rates[index - 1],
 490                                                               lane_count)) {
 491                         drm_dbg_kms(&i915->drm,
 492                                     "Retrying Link training for eDP with same parameters\n");
 493                         return 0;
 494                 }
 495                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 496                 intel_dp->max_link_lane_count = lane_count;
 497         } else if (lane_count > 1) {
 498                 if (intel_dp_is_edp(intel_dp) &&
 499                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 500                                                               intel_dp_max_common_rate(intel_dp),
 501                                                               lane_count >> 1)) {
 502                         drm_dbg_kms(&i915->drm,
 503                                     "Retrying Link training for eDP with same parameters\n");
 504                         return 0;
 505                 }
 506                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 507                 intel_dp->max_link_lane_count = lane_count >> 1;
 508         } else {
 509                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 510                 return -1;
 511         }
 512
 513         return 0;
 514 }
 515
 516 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 517 {
 518         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 519                        DP_DSC_FEC_OVERHEAD_FACTOR);
 520 }
 521
 522 static int
 523 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 524 {
 525         if (INTEL_GEN(i915) >= 11)
 526                 return 7680 * 8;
 527         else
 528                 return 6144 * 8;
 529 }
 530
 531 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 532                                        u32 link_clock, u32 lane_count,
 533                                        u32 mode_clock, u32 mode_hdisplay,
 534                                        bool bigjoiner)
 535 {
 536         u32 bits_per_pixel, max_bpp_small_joiner_ram;
 537         int i;
 538
 539         /*
 540          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 541          * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
 542          * for SST -> TimeSlotsPerMTP is 1,
 543          * for MST -> TimeSlotsPerMTP has to be calculated
 544          */
 545         bits_per_pixel = (link_clock * lane_count * 8) /
 546                          intel_dp_mode_to_fec_clock(mode_clock);
 547         drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
 548
 549         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 550         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 551                 mode_hdisplay;
 552
 553         if (bigjoiner)
 554                 max_bpp_small_joiner_ram *= 2;
 555
 556         drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
 557                     max_bpp_small_joiner_ram);
 558
 559         /*
 560          * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 561          * check, output bpp from small joiner RAM check)
 562          */
 563         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 564
 565         if (bigjoiner) {
 566                 u32 max_bpp_bigjoiner =
 567                         i915->max_cdclk_freq * 48 /
 568                         intel_dp_mode_to_fec_clock(mode_clock);
 569
 570                 DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
 571                 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
 572         }
 573
 574         /* Error out if the max bpp is less than smallest allowed valid bpp */
 575         if (bits_per_pixel < valid_dsc_bpp[0]) {
 576                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 577                             bits_per_pixel, valid_dsc_bpp[0]);
 578                 return 0;
 579         }
 580
 581         /* Find the nearest match in the array of known BPPs from VESA */
 582         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 583                 if (bits_per_pixel < valid_dsc_bpp[i + 1])
 584                         break;
 585         }
 586         bits_per_pixel = valid_dsc_bpp[i];
 587
 588         /*
 589          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 590          * fractional part is 0
 591          */
 592         return bits_per_pixel << 4;
 593 }
 594
 595 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 596                                        int mode_clock, int mode_hdisplay,
 597                                        bool bigjoiner)
 598 {
 599         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 600         u8 min_slice_count, i;
 601         int max_slice_width;
 602
 603         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 604                 min_slice_count = DIV_ROUND_UP(mode_clock,
 605                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 606         else
 607                 min_slice_count = DIV_ROUND_UP(mode_clock,
 608                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 609
 610         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 611         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 612                 drm_dbg_kms(&i915->drm,
 613                             "Unsupported slice width %d by DP DSC Sink device\n",
 614                             max_slice_width);
 615                 return 0;
 616         }
 617         /* Also take into account max slice width */
 618         min_slice_count = min_t(u8, min_slice_count,
 619                                 DIV_ROUND_UP(mode_hdisplay,
 620                                              max_slice_width));
 621
 622         /* Find the closest match to the valid slice count values */
 623         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 624                 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 625
 626                 if (test_slice_count >
 627                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
 628                         break;
 629
 630                 /* big joiner needs small joiner to be enabled */
 631                 if (bigjoiner && test_slice_count < 4)
 632                         continue;
 633
 634                 if (min_slice_count <= test_slice_count)
 635                         return test_slice_count;
 636         }
 637
 638         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 639                     min_slice_count);
 640         return 0;
 641 }
 642
 643 static enum intel_output_format
 644 intel_dp_output_format(struct drm_connector *connector,
 645                        const struct drm_display_mode *mode)
 646 {
 647         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 648         const struct drm_display_info *info = &connector->display_info;
 649
 650         if (!connector->ycbcr_420_allowed ||
 651             !drm_mode_is_420_only(info, mode))
 652                 return INTEL_OUTPUT_FORMAT_RGB;
 653
 654         if (intel_dp->dfp.ycbcr_444_to_420)
 655                 return INTEL_OUTPUT_FORMAT_YCBCR444;
 656         else
 657                 return INTEL_OUTPUT_FORMAT_YCBCR420;
 658 }
 659
 660 int intel_dp_min_bpp(enum intel_output_format output_format)
 661 {
 662         if (output_format == INTEL_OUTPUT_FORMAT_RGB)
 663                 return 6 * 3;
 664         else
 665                 return 8 * 3;
 666 }
 667
 668 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
 669 {
 670         /*
 671          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
 672          * format of the number of bytes per pixel will be half the number
 673          * of bytes of RGB pixel.
 674          */
 675         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 676                 bpp /= 2;
 677
 678         return bpp;
 679 }
 680
 681 static int
 682 intel_dp_mode_min_output_bpp(struct drm_connector *connector,
 683                              const struct drm_display_mode *mode)
 684 {
 685         enum intel_output_format output_format =
 686                 intel_dp_output_format(connector, mode);
 687
 688         return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
 689 }
 690
 691 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 692                                   int hdisplay)
 693 {
 694         /*
 695          * Older platforms don't like hdisplay==4096 with DP.
 696          *
 697          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
 698          * and frame counter increment), but we don't get vblank interrupts,
 699          * and the pipe underruns immediately. The link also doesn't seem
 700          * to get trained properly.
 701          *
 702          * On CHV the vblank interrupts don't seem to disappear but
 703          * otherwise the symptoms are similar.
 704          *
 705          * TODO: confirm the behaviour on HSW+
 706          */
 707         return hdisplay == 4096 && !HAS_DDI(dev_priv);
 708 }
 709
 710 static enum drm_mode_status
 711 intel_dp_mode_valid_downstream(struct intel_connector *connector,
 712                                const struct drm_display_mode *mode,
 713                                int target_clock)
 714 {
 715         struct intel_dp *intel_dp = intel_attached_dp(connector);
 716         const struct drm_display_info *info = &connector->base.display_info;
 717         int tmds_clock;
 718
 719         /* If PCON supports FRL MODE, check FRL bandwidth constraints */
 720         if (intel_dp->dfp.pcon_max_frl_bw) {
 721                 int target_bw;
 722                 int max_frl_bw;
 723                 int bpp = intel_dp_mode_min_output_bpp(&connector->base, mode);
 724
 725                 target_bw = bpp * target_clock;
 726
 727                 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
 728
 729                 /* converting bw from Gbps to Kbps*/
 730                 max_frl_bw = max_frl_bw * 1000000;
 731
 732                 if (target_bw > max_frl_bw)
 733                         return MODE_CLOCK_HIGH;
 734
 735                 return MODE_OK;
 736         }
 737
 738         if (intel_dp->dfp.max_dotclock &&
 739             target_clock > intel_dp->dfp.max_dotclock)
 740                 return MODE_CLOCK_HIGH;
 741
 742         /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
 743         tmds_clock = target_clock;
 744         if (drm_mode_is_420_only(info, mode))
 745                 tmds_clock /= 2;
 746
 747         if (intel_dp->dfp.min_tmds_clock &&
 748             tmds_clock < intel_dp->dfp.min_tmds_clock)
 749                 return MODE_CLOCK_LOW;
 750         if (intel_dp->dfp.max_tmds_clock &&
 751             tmds_clock > intel_dp->dfp.max_tmds_clock)
 752                 return MODE_CLOCK_HIGH;
 753
 754         return MODE_OK;
 755 }
 756
 757 static enum drm_mode_status
 758 intel_dp_mode_valid(struct drm_connector *connector,
 759                     struct drm_display_mode *mode)
 760 {
 761         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 762         struct intel_connector *intel_connector = to_intel_connector(connector);
 763         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 764         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 765         int target_clock = mode->clock;
 766         int max_rate, mode_rate, max_lanes, max_link_clock;
 767         int max_dotclk = dev_priv->max_dotclk_freq;
 768         u16 dsc_max_output_bpp = 0;
 769         u8 dsc_slice_count = 0;
 770         enum drm_mode_status status;
 771         bool dsc = false, bigjoiner = false;
 772
 773         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 774                 return MODE_NO_DBLESCAN;
 775
 776         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 777                 return MODE_H_ILLEGAL;
 778
 779         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 780                 if (mode->hdisplay > fixed_mode->hdisplay)
 781                         return MODE_PANEL;
 782
 783                 if (mode->vdisplay > fixed_mode->vdisplay)
 784                         return MODE_PANEL;
 785
 786                 target_clock = fixed_mode->clock;
 787         }
 788
 789         if (mode->clock < 10000)
 790                 return MODE_CLOCK_LOW;
 791
 792         if ((target_clock > max_dotclk || mode->hdisplay > 5120) &&
 793             intel_dp_can_bigjoiner(intel_dp)) {
 794                 bigjoiner = true;
 795                 max_dotclk *= 2;
 796         }
 797         if (target_clock > max_dotclk)
 798                 return MODE_CLOCK_HIGH;
 799
 800         max_link_clock = intel_dp_max_link_rate(intel_dp);
 801         max_lanes = intel_dp_max_lane_count(intel_dp);
 802
 803         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 804         mode_rate = intel_dp_link_required(target_clock,
 805                                            intel_dp_mode_min_output_bpp(connector, mode));
 806
 807         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
 808                 return MODE_H_ILLEGAL;
 809
 810         /*
 811          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 812          * integer value since we support only integer values of bpp.
 813          */
 814         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
 815             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 816                 if (intel_dp_is_edp(intel_dp)) {
 817                         dsc_max_output_bpp =
 818                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 819                         dsc_slice_count =
 820                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 821                                                                 true);
 822                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 823                         dsc_max_output_bpp =
 824                                 intel_dp_dsc_get_output_bpp(dev_priv,
 825                                                             max_link_clock,
 826                                                             max_lanes,
 827                                                             target_clock,
 828                                                             mode->hdisplay,
 829                                                             bigjoiner) >> 4;
 830                         dsc_slice_count =
 831                                 intel_dp_dsc_get_slice_count(intel_dp,
 832                                                              target_clock,
 833                                                              mode->hdisplay,
 834                                                              bigjoiner);
 835                 }
 836
 837                 dsc = dsc_max_output_bpp && dsc_slice_count;
 838         }
 839
 840         /* big joiner configuration needs DSC */
 841         if (bigjoiner && !dsc)
 842                 return MODE_CLOCK_HIGH;
 843
 844         if (mode_rate > max_rate && !dsc)
 845                 return MODE_CLOCK_HIGH;
 846
 847         status = intel_dp_mode_valid_downstream(intel_connector,
 848                                                 mode, target_clock);
 849         if (status != MODE_OK)
 850                 return status;
 851
 852         return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
 853 }
 854
 855 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
 856 {
 857         int i;
 858         u32 v = 0;
 859
 860         if (src_bytes > 4)
 861                 src_bytes = 4;
 862         for (i = 0; i < src_bytes; i++)
 863                 v |= ((u32)src[i]) << ((3 - i) * 8);
 864         return v;
 865 }
 866
 867 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
 868 {
 869         int i;
 870         if (dst_bytes > 4)
 871                 dst_bytes = 4;
 872         for (i = 0; i < dst_bytes; i++)
 873                 dst[i] = src >> ((3-i) * 8);
 874 }
 875
 876 static void
 877 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 878 static void
 879 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 880                                               bool force_disable_vdd);
 881 static void
 882 intel_dp_pps_init(struct intel_dp *intel_dp);
 883
 884 static intel_wakeref_t
 885 pps_lock(struct intel_dp *intel_dp)
 886 {
 887         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 888         intel_wakeref_t wakeref;
 889
 890         /*
 891          * See intel_power_sequencer_reset() why we need
 892          * a power domain reference here.
 893          */
 894         wakeref = intel_display_power_get(dev_priv,
 895                                           intel_aux_power_domain(dp_to_dig_port(intel_dp)));
 896
 897         mutex_lock(&dev_priv->pps_mutex);
 898
 899         return wakeref;
 900 }
 901
 902 static intel_wakeref_t
 903 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
 904 {
 905         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 906
 907         mutex_unlock(&dev_priv->pps_mutex);
 908         intel_display_power_put(dev_priv,
 909                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
 910                                 wakeref);
 911         return 0;
 912 }
 913
 914 #define with_pps_lock(dp, wf) \
 915         for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
 916
 917 static void
 918 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 919 {
 920         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 921         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 922         enum pipe pipe = intel_dp->pps_pipe;
 923         bool pll_enabled, release_cl_override = false;
 924         enum dpio_phy phy = DPIO_PHY(pipe);
 925         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 926         u32 DP;
 927
 928         if (drm_WARN(&dev_priv->drm,
 929                      intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
 930                      "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
 931                      pipe_name(pipe), dig_port->base.base.base.id,
 932                      dig_port->base.base.name))
 933                 return;
 934
 935         drm_dbg_kms(&dev_priv->drm,
 936                     "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
 937                     pipe_name(pipe), dig_port->base.base.base.id,
 938                     dig_port->base.base.name);
 939
 940         /* Preserve the BIOS-computed detected bit. This is
 941          * supposed to be read-only.
 942          */
 943         DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
 944         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 945         DP |= DP_PORT_WIDTH(1);
 946         DP |= DP_LINK_TRAIN_PAT_1;
 947
 948         if (IS_CHERRYVIEW(dev_priv))
 949                 DP |= DP_PIPE_SEL_CHV(pipe);
 950         else
 951                 DP |= DP_PIPE_SEL(pipe);
 952
 953         pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
 954
 955         /*
 956          * The DPLL for the pipe must be enabled for this to work.
 957          * So enable temporarily it if it's not already enabled.
 958          */
 959         if (!pll_enabled) {
 960                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 961                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 962
 963                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 964                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 965                         drm_err(&dev_priv->drm,
 966                                 "Failed to force on pll for pipe %c!\n",
 967                                 pipe_name(pipe));
 968                         return;
 969                 }
 970         }
 971
 972         /*
 973          * Similar magic as in intel_dp_enable_port().
 974          * We _must_ do this port enable + disable trick
 975          * to make this power sequencer lock onto the port.
 976          * Otherwise even VDD force bit won't work.
 977          */
 978         intel_de_write(dev_priv, intel_dp->output_reg, DP);
 979         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 980
 981         intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
 982         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 983
 984         intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN);
 985         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 986
 987         if (!pll_enabled) {
 988                 vlv_force_pll_off(dev_priv, pipe);
 989
 990                 if (release_cl_override)
 991                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 992         }
 993 }
 994
 995 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 996 {
 997         struct intel_encoder *encoder;
 998         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 999
1000         /*
1001          * We don't have power sequencer currently.
1002          * Pick one that's not used by other ports.
1003          */
1004         for_each_intel_dp(&dev_priv->drm, encoder) {
1005                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1006
1007                 if (encoder->type == INTEL_OUTPUT_EDP) {
1008                         drm_WARN_ON(&dev_priv->drm,
1009                                     intel_dp->active_pipe != INVALID_PIPE &&
1010                                     intel_dp->active_pipe !=
1011                                     intel_dp->pps_pipe);
1012
1013                         if (intel_dp->pps_pipe != INVALID_PIPE)
1014                                 pipes &= ~(1 << intel_dp->pps_pipe);
1015                 } else {
1016                         drm_WARN_ON(&dev_priv->drm,
1017                                     intel_dp->pps_pipe != INVALID_PIPE);
1018
1019                         if (intel_dp->active_pipe != INVALID_PIPE)
1020                                 pipes &= ~(1 << intel_dp->active_pipe);
1021                 }
1022         }
1023
1024         if (pipes == 0)
1025                 return INVALID_PIPE;
1026
1027         return ffs(pipes) - 1;
1028 }
1029
1030 static enum pipe
1031 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
1032 {
1033         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1034         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1035         enum pipe pipe;
1036
1037         lockdep_assert_held(&dev_priv->pps_mutex);
1038
1039         /* We should never land here with regular DP ports */
1040         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
1041
1042         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&
1043                     intel_dp->active_pipe != intel_dp->pps_pipe);
1044
1045         if (intel_dp->pps_pipe != INVALID_PIPE)
1046                 return intel_dp->pps_pipe;
1047
1048         pipe = vlv_find_free_pps(dev_priv);
1049
1050         /*
1051          * Didn't find one. This should not happen since there
1052          * are two power sequencers and up to two eDP ports.
1053          */
1054         if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
1055                 pipe = PIPE_A;
1056
1057         vlv_steal_power_sequencer(dev_priv, pipe);
1058         intel_dp->pps_pipe = pipe;
1059
1060         drm_dbg_kms(&dev_priv->drm,
1061                     "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
1062                     pipe_name(intel_dp->pps_pipe),
1063                     dig_port->base.base.base.id,
1064                     dig_port->base.base.name);
1065
1066         /* init power sequencer on this pipe and port */
1067         intel_dp_init_panel_power_sequencer(intel_dp);
1068         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
1069
1070         /*
1071          * Even vdd force doesn't work until we've made
1072          * the power sequencer lock in on the port.
1073          */
1074         vlv_power_sequencer_kick(intel_dp);
1075
1076         return intel_dp->pps_pipe;
1077 }
1078
1079 static int
1080 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
1081 {
1082         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1083         int backlight_controller = dev_priv->vbt.backlight.controller;
1084
1085         lockdep_assert_held(&dev_priv->pps_mutex);
1086
1087         /* We should never land here with regular DP ports */
1088         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
1089
1090         if (!intel_dp->pps_reset)
1091                 return backlight_controller;
1092
1093         intel_dp->pps_reset = false;
1094
1095         /*
1096          * Only the HW needs to be reprogrammed, the SW state is fixed and
1097          * has been setup during connector init.
1098          */
1099         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1100
1101         return backlight_controller;
1102 }
1103
1104 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
1105                                enum pipe pipe);
1106
1107 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
1108                                enum pipe pipe)
1109 {
1110         return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON;
1111 }
1112
1113 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
1114                                 enum pipe pipe)
1115 {
1116         return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD;
1117 }
1118
1119 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
1120                          enum pipe pipe)
1121 {
1122         return true;
1123 }
1124
1125 static enum pipe
1126 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
1127                      enum port port,
1128                      vlv_pipe_check pipe_check)
1129 {
1130         enum pipe pipe;
1131
1132         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
1133                 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
1134                         PANEL_PORT_SELECT_MASK;
1135
1136                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
1137                         continue;
1138
1139                 if (!pipe_check(dev_priv, pipe))
1140                         continue;
1141
1142                 return pipe;
1143         }
1144
1145         return INVALID_PIPE;
1146 }
1147
1148 static void
1149 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
1150 {
1151         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1152         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1153         enum port port = dig_port->base.port;
1154
1155         lockdep_assert_held(&dev_priv->pps_mutex);
1156
1157         /* try to find a pipe with this port selected */
1158         /* first pick one where the panel is on */
1159         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1160                                                   vlv_pipe_has_pp_on);
1161         /* didn't find one? pick one where vdd is on */
1162         if (intel_dp->pps_pipe == INVALID_PIPE)
1163                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1164                                                           vlv_pipe_has_vdd_on);
1165         /* didn't find one? pick one with just the correct port */
1166         if (intel_dp->pps_pipe == INVALID_PIPE)
1167                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1168                                                           vlv_pipe_any);
1169
1170         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
1171         if (intel_dp->pps_pipe == INVALID_PIPE) {
1172                 drm_dbg_kms(&dev_priv->drm,
1173                             "no initial power sequencer for [ENCODER:%d:%s]\n",
1174                             dig_port->base.base.base.id,
1175                             dig_port->base.base.name);
1176                 return;
1177         }
1178
1179         drm_dbg_kms(&dev_priv->drm,
1180                     "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
1181                     dig_port->base.base.base.id,
1182                     dig_port->base.base.name,
1183                     pipe_name(intel_dp->pps_pipe));
1184
1185         intel_dp_init_panel_power_sequencer(intel_dp);
1186         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1187 }
1188
1189 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
1190 {
1191         struct intel_encoder *encoder;
1192
1193         if (drm_WARN_ON(&dev_priv->drm,
1194                         !(IS_VALLEYVIEW(dev_priv) ||
1195                           IS_CHERRYVIEW(dev_priv) ||
1196                           IS_GEN9_LP(dev_priv))))
1197                 return;
1198
1199         /*
1200          * We can't grab pps_mutex here due to deadlock with power_domain
1201          * mutex when power_domain functions are called while holding pps_mutex.
1202          * That also means that in order to use pps_pipe the code needs to
1203          * hold both a power domain reference and pps_mutex, and the power domain
1204          * reference get/put must be done while _not_ holding pps_mutex.
1205          * pps_{lock,unlock}() do these steps in the correct order, so one
1206          * should use them always.
1207          */
1208
1209         for_each_intel_dp(&dev_priv->drm, encoder) {
1210                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1211
1212                 drm_WARN_ON(&dev_priv->drm,
1213                             intel_dp->active_pipe != INVALID_PIPE);
1214
1215                 if (encoder->type != INTEL_OUTPUT_EDP)
1216                         continue;
1217
1218                 if (IS_GEN9_LP(dev_priv))
1219                         intel_dp->pps_reset = true;
1220                 else
1221                         intel_dp->pps_pipe = INVALID_PIPE;
1222         }
1223 }
1224
1225 struct pps_registers {
1226         i915_reg_t pp_ctrl;
1227         i915_reg_t pp_stat;
1228         i915_reg_t pp_on;
1229         i915_reg_t pp_off;
1230         i915_reg_t pp_div;
1231 };
1232
1233 static void intel_pps_get_registers(struct intel_dp *intel_dp,
1234                                     struct pps_registers *regs)
1235 {
1236         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1237         int pps_idx = 0;
1238
1239         memset(regs, 0, sizeof(*regs));
1240
1241         if (IS_GEN9_LP(dev_priv))
1242                 pps_idx = bxt_power_sequencer_idx(intel_dp);
1243         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1244                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
1245
1246         regs->pp_ctrl = PP_CONTROL(pps_idx);
1247         regs->pp_stat = PP_STATUS(pps_idx);
1248         regs->pp_on = PP_ON_DELAYS(pps_idx);
1249         regs->pp_off = PP_OFF_DELAYS(pps_idx);
1250
1251         /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
1252         if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1253                 regs->pp_div = INVALID_MMIO_REG;
1254         else
1255                 regs->pp_div = PP_DIVISOR(pps_idx);
1256 }
1257
1258 static i915_reg_t
1259 _pp_ctrl_reg(struct intel_dp *intel_dp)
1260 {
1261         struct pps_registers regs;
1262
1263         intel_pps_get_registers(intel_dp, &regs);
1264
1265         return regs.pp_ctrl;
1266 }
1267
1268 static i915_reg_t
1269 _pp_stat_reg(struct intel_dp *intel_dp)
1270 {
1271         struct pps_registers regs;
1272
1273         intel_pps_get_registers(intel_dp, &regs);
1274
1275         return regs.pp_stat;
1276 }
1277
1278 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1279 {
1280         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1281
1282         lockdep_assert_held(&dev_priv->pps_mutex);
1283
1284         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1285             intel_dp->pps_pipe == INVALID_PIPE)
1286                 return false;
1287
1288         return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
1289 }
1290
1291 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1292 {
1293         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1294
1295         lockdep_assert_held(&dev_priv->pps_mutex);
1296
1297         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1298             intel_dp->pps_pipe == INVALID_PIPE)
1299                 return false;
1300
1301         return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1302 }
1303
1304 static void
1305 intel_dp_check_edp(struct intel_dp *intel_dp)
1306 {
1307         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1308
1309         if (!intel_dp_is_edp(intel_dp))
1310                 return;
1311
1312         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1313                 drm_WARN(&dev_priv->drm, 1,
1314                          "eDP powered off while attempting aux channel communication.\n");
1315                 drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n",
1316                             intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
1317                             intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
1318         }
1319 }
1320
1321 static u32
1322 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1323 {
1324         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1325         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1326         const unsigned int timeout_ms = 10;
1327         u32 status;
1328         bool done;
1329
1330 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1331         done = wait_event_timeout(i915->gmbus_wait_queue, C,
1332                                   msecs_to_jiffies_timeout(timeout_ms));
1333
1334         /* just trace the final value */
1335         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1336
1337         if (!done)
1338                 drm_err(&i915->drm,
1339                         "%s: did not complete or timeout within %ums (status 0x%08x)\n",
1340                         intel_dp->aux.name, timeout_ms, status);
1341 #undef C
1342
1343         return status;
1344 }
1345
1346 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1347 {
1348         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1349
1350         if (index)
1351                 return 0;
1352
1353         /*
1354          * The clock divider is based off the hrawclk, and would like to run at
1355          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1356          */
1357         return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
1358 }
1359
1360 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1361 {
1362         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1363         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1364         u32 freq;
1365
1366         if (index)
1367                 return 0;
1368
1369         /*
1370          * The clock divider is based off the cdclk or PCH rawclk, and would
1371          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1372          * divide by 2000 and use that
1373          */
1374         if (dig_port->aux_ch == AUX_CH_A)
1375                 freq = dev_priv->cdclk.hw.cdclk;
1376         else
1377                 freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
1378         return DIV_ROUND_CLOSEST(freq, 2000);
1379 }
1380
1381 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1382 {
1383         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1384         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1385
1386         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1387                 /* Workaround for non-ULT HSW */
1388                 switch (index) {
1389                 case 0: return 63;
1390                 case 1: return 72;
1391                 default: return 0;
1392                 }
1393         }
1394
1395         return ilk_get_aux_clock_divider(intel_dp, index);
1396 }
1397
1398 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1399 {
1400         /*
1401          * SKL doesn't need us to program the AUX clock divider (Hardware will
1402          * derive the clock from CDCLK automatically). We still implement the
1403          * get_aux_clock_divider vfunc to plug-in into the existing code.
1404          */
1405         return index ? 0 : 1;
1406 }
1407
1408 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1409                                 int send_bytes,
1410                                 u32 aux_clock_divider)
1411 {
1412         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1413         struct drm_i915_private *dev_priv =
1414                         to_i915(dig_port->base.base.dev);
1415         u32 precharge, timeout;
1416
1417         if (IS_GEN(dev_priv, 6))
1418                 precharge = 3;
1419         else
1420                 precharge = 5;
1421
1422         if (IS_BROADWELL(dev_priv))
1423                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1424         else
1425                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1426
1427         return DP_AUX_CH_CTL_SEND_BUSY |
1428                DP_AUX_CH_CTL_DONE |
1429                DP_AUX_CH_CTL_INTERRUPT |
1430                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1431                timeout |
1432                DP_AUX_CH_CTL_RECEIVE_ERROR |
1433                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1434                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1435                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1436 }
1437
1438 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1439                                 int send_bytes,
1440                                 u32 unused)
1441 {
1442         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1443         struct drm_i915_private *i915 =
1444                         to_i915(dig_port->base.base.dev);
1445         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
1446         u32 ret;
1447
1448         ret = DP_AUX_CH_CTL_SEND_BUSY |
1449               DP_AUX_CH_CTL_DONE |
1450               DP_AUX_CH_CTL_INTERRUPT |
1451               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1452               DP_AUX_CH_CTL_TIME_OUT_MAX |
1453               DP_AUX_CH_CTL_RECEIVE_ERROR |
1454               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1455               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1456               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1457
1458         if (intel_phy_is_tc(i915, phy) &&
1459             dig_port->tc_mode == TC_PORT_TBT_ALT)
1460                 ret |= DP_AUX_CH_CTL_TBT_IO;
1461
1462         return ret;
1463 }
1464
1465 static int
1466 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1467                   const u8 *send, int send_bytes,
1468                   u8 *recv, int recv_size,
1469                   u32 aux_send_ctl_flags)
1470 {
1471         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1472         struct drm_i915_private *i915 =
1473                         to_i915(dig_port->base.base.dev);
1474         struct intel_uncore *uncore = &i915->uncore;
1475         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
1476         bool is_tc_port = intel_phy_is_tc(i915, phy);
1477         i915_reg_t ch_ctl, ch_data[5];
1478         u32 aux_clock_divider;
1479         enum intel_display_power_domain aux_domain;
1480         intel_wakeref_t aux_wakeref;
1481         intel_wakeref_t pps_wakeref;
1482         int i, ret, recv_bytes;
1483         int try, clock = 0;
1484         u32 status;
1485         bool vdd;
1486
1487         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1488         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1489                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1490
1491         if (is_tc_port)
1492                 intel_tc_port_lock(dig_port);
1493
1494         aux_domain = intel_aux_power_domain(dig_port);
1495
1496         aux_wakeref = intel_display_power_get(i915, aux_domain);
1497         pps_wakeref = pps_lock(intel_dp);
1498
1499         /*
1500          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1501          * In such cases we want to leave VDD enabled and it's up to upper layers
1502          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1503          * ourselves.
1504          */
1505         vdd = edp_panel_vdd_on(intel_dp);
1506
1507         /* dp aux is extremely sensitive to irq latency, hence request the
1508          * lowest possible wakeup latency and so prevent the cpu from going into
1509          * deep sleep states.
1510          */
1511         cpu_latency_qos_update_request(&i915->pm_qos, 0);
1512
1513         intel_dp_check_edp(intel_dp);
1514
1515         /* Try to wait for any previous AUX channel activity */
1516         for (try = 0; try < 3; try++) {
1517                 status = intel_uncore_read_notrace(uncore, ch_ctl);
1518                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1519                         break;
1520                 msleep(1);
1521         }
1522         /* just trace the final value */
1523         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1524
1525         if (try == 3) {
1526                 const u32 status = intel_uncore_read(uncore, ch_ctl);
1527
1528                 if (status != intel_dp->aux_busy_last_status) {
1529                         drm_WARN(&i915->drm, 1,
1530                                  "%s: not started (status 0x%08x)\n",
1531                                  intel_dp->aux.name, status);
1532                         intel_dp->aux_busy_last_status = status;
1533                 }
1534
1535                 ret = -EBUSY;
1536                 goto out;
1537         }
1538
1539         /* Only 5 data registers! */
1540         if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) {
1541                 ret = -E2BIG;
1542                 goto out;
1543         }
1544
1545         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1546                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1547                                                           send_bytes,
1548                                                           aux_clock_divider);
1549
1550                 send_ctl |= aux_send_ctl_flags;
1551
1552                 /* Must try at least 3 times according to DP spec */
1553                 for (try = 0; try < 5; try++) {
1554                         /* Load the send data into the aux channel data registers */
1555                         for (i = 0; i < send_bytes; i += 4)
1556                                 intel_uncore_write(uncore,
1557                                                    ch_data[i >> 2],
1558                                                    intel_dp_pack_aux(send + i,
1559                                                                      send_bytes - i));
1560
1561                         /* Send the command and wait for it to complete */
1562                         intel_uncore_write(uncore, ch_ctl, send_ctl);
1563
1564                         status = intel_dp_aux_wait_done(intel_dp);
1565
1566                         /* Clear done status and any errors */
1567                         intel_uncore_write(uncore,
1568                                            ch_ctl,
1569                                            status |
1570                                            DP_AUX_CH_CTL_DONE |
1571                                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
1572                                            DP_AUX_CH_CTL_RECEIVE_ERROR);
1573
1574                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1575                          *   400us delay required for errors and timeouts
1576                          *   Timeout errors from the HW already meet this
1577                          *   requirement so skip to next iteration
1578                          */
1579                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1580                                 continue;
1581
1582                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1583                                 usleep_range(400, 500);
1584                                 continue;
1585                         }
1586                         if (status & DP_AUX_CH_CTL_DONE)
1587                                 goto done;
1588                 }
1589         }
1590
1591         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1592                 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",
1593                         intel_dp->aux.name, status);
1594                 ret = -EBUSY;
1595                 goto out;
1596         }
1597
1598 done:
1599         /* Check for timeout or receive error.
1600          * Timeouts occur when the sink is not connected
1601          */
1602         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1603                 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",
1604                         intel_dp->aux.name, status);
1605                 ret = -EIO;
1606                 goto out;
1607         }
1608
1609         /* Timeouts occur when the device isn't connected, so they're
1610          * "normal" -- don't fill the kernel log with these */
1611         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1612                 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
1613                             intel_dp->aux.name, status);
1614                 ret = -ETIMEDOUT;
1615                 goto out;
1616         }
1617
1618         /* Unload any bytes sent back from the other side */
1619         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1620                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1621
1622         /*
1623          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1624          * We have no idea of what happened so we return -EBUSY so
1625          * drm layer takes care for the necessary retries.
1626          */
1627         if (recv_bytes == 0 || recv_bytes > 20) {
1628                 drm_dbg_kms(&i915->drm,
1629                             "%s: Forbidden recv_bytes = %d on aux transaction\n",
1630                             intel_dp->aux.name, recv_bytes);
1631                 ret = -EBUSY;
1632                 goto out;
1633         }
1634
1635         if (recv_bytes > recv_size)
1636                 recv_bytes = recv_size;
1637
1638         for (i = 0; i < recv_bytes; i += 4)
1639                 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
1640                                     recv + i, recv_bytes - i);
1641
1642         ret = recv_bytes;
1643 out:
1644         cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
1645
1646         if (vdd)
1647                 edp_panel_vdd_off(intel_dp, false);
1648
1649         pps_unlock(intel_dp, pps_wakeref);
1650         intel_display_power_put_async(i915, aux_domain, aux_wakeref);
1651
1652         if (is_tc_port)
1653                 intel_tc_port_unlock(dig_port);
1654
1655         return ret;
1656 }
1657
1658 #define BARE_ADDRESS_SIZE       3
1659 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1660
1661 static void
1662 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1663                     const struct drm_dp_aux_msg *msg)
1664 {
1665         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1666         txbuf[1] = (msg->address >> 8) & 0xff;
1667         txbuf[2] = msg->address & 0xff;
1668         txbuf[3] = msg->size - 1;
1669 }
1670
1671 static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg)
1672 {
1673         /*
1674          * If we're trying to send the HDCP Aksv, we need to set a the Aksv
1675          * select bit to inform the hardware to send the Aksv after our header
1676          * since we can't access that data from software.
1677          */
1678         if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE &&
1679             msg->address == DP_AUX_HDCP_AKSV)
1680                 return DP_AUX_CH_CTL_AUX_AKSV_SELECT;
1681
1682         return 0;
1683 }
1684
1685 static ssize_t
1686 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1687 {
1688         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1689         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1690         u8 txbuf[20], rxbuf[20];
1691         size_t txsize, rxsize;
1692         u32 flags = intel_dp_aux_xfer_flags(msg);
1693         int ret;
1694
1695         intel_dp_aux_header(txbuf, msg);
1696
1697         switch (msg->request & ~DP_AUX_I2C_MOT) {
1698         case DP_AUX_NATIVE_WRITE:
1699         case DP_AUX_I2C_WRITE:
1700         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1701                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1702                 rxsize = 2; /* 0 or 1 data bytes */
1703
1704                 if (drm_WARN_ON(&i915->drm, txsize > 20))
1705                         return -E2BIG;
1706
1707                 drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size);
1708
1709                 if (msg->buffer)
1710                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1711
1712                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1713                                         rxbuf, rxsize, flags);
1714                 if (ret > 0) {
1715                         msg->reply = rxbuf[0] >> 4;
1716
1717                         if (ret > 1) {
1718                                 /* Number of bytes written in a short write. */
1719                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1720                         } else {
1721                                 /* Return payload size. */
1722                                 ret = msg->size;
1723                         }
1724                 }
1725                 break;
1726
1727         case DP_AUX_NATIVE_READ:
1728         case DP_AUX_I2C_READ:
1729                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1730                 rxsize = msg->size + 1;
1731
1732                 if (drm_WARN_ON(&i915->drm, rxsize > 20))
1733                         return -E2BIG;
1734
1735                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1736                                         rxbuf, rxsize, flags);
1737                 if (ret > 0) {
1738                         msg->reply = rxbuf[0] >> 4;
1739                         /*
1740                          * Assume happy day, and copy the data. The caller is
1741                          * expected to check msg->reply before touching it.
1742                          *
1743                          * Return payload size.
1744                          */
1745                         ret--;
1746                         memcpy(msg->buffer, rxbuf + 1, ret);
1747                 }
1748                 break;
1749
1750         default:
1751                 ret = -EINVAL;
1752                 break;
1753         }
1754
1755         return ret;
1756 }
1757
1758
1759 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1760 {
1761         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1762         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1763         enum aux_ch aux_ch = dig_port->aux_ch;
1764
1765         switch (aux_ch) {
1766         case AUX_CH_B:
1767         case AUX_CH_C:
1768         case AUX_CH_D:
1769                 return DP_AUX_CH_CTL(aux_ch);
1770         default:
1771                 MISSING_CASE(aux_ch);
1772                 return DP_AUX_CH_CTL(AUX_CH_B);
1773         }
1774 }
1775
1776 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1777 {
1778         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1779         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1780         enum aux_ch aux_ch = dig_port->aux_ch;
1781
1782         switch (aux_ch) {
1783         case AUX_CH_B:
1784         case AUX_CH_C:
1785         case AUX_CH_D:
1786                 return DP_AUX_CH_DATA(aux_ch, index);
1787         default:
1788                 MISSING_CASE(aux_ch);
1789                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1790         }
1791 }
1792
1793 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1794 {
1795         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1796         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1797         enum aux_ch aux_ch = dig_port->aux_ch;
1798
1799         switch (aux_ch) {
1800         case AUX_CH_A:
1801                 return DP_AUX_CH_CTL(aux_ch);
1802         case AUX_CH_B:
1803         case AUX_CH_C:
1804         case AUX_CH_D:
1805                 return PCH_DP_AUX_CH_CTL(aux_ch);
1806         default:
1807                 MISSING_CASE(aux_ch);
1808                 return DP_AUX_CH_CTL(AUX_CH_A);
1809         }
1810 }
1811
1812 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1813 {
1814         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1815         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1816         enum aux_ch aux_ch = dig_port->aux_ch;
1817
1818         switch (aux_ch) {
1819         case AUX_CH_A:
1820                 return DP_AUX_CH_DATA(aux_ch, index);
1821         case AUX_CH_B:
1822         case AUX_CH_C:
1823         case AUX_CH_D:
1824                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1825         default:
1826                 MISSING_CASE(aux_ch);
1827                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1828         }
1829 }
1830
1831 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1832 {
1833         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1834         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1835         enum aux_ch aux_ch = dig_port->aux_ch;
1836
1837         switch (aux_ch) {
1838         case AUX_CH_A:
1839         case AUX_CH_B:
1840         case AUX_CH_C:
1841         case AUX_CH_D:
1842         case AUX_CH_E:
1843         case AUX_CH_F:
1844                 return DP_AUX_CH_CTL(aux_ch);
1845         default:
1846                 MISSING_CASE(aux_ch);
1847                 return DP_AUX_CH_CTL(AUX_CH_A);
1848         }
1849 }
1850
1851 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1852 {
1853         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1854         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1855         enum aux_ch aux_ch = dig_port->aux_ch;
1856
1857         switch (aux_ch) {
1858         case AUX_CH_A:
1859         case AUX_CH_B:
1860         case AUX_CH_C:
1861         case AUX_CH_D:
1862         case AUX_CH_E:
1863         case AUX_CH_F:
1864                 return DP_AUX_CH_DATA(aux_ch, index);
1865         default:
1866                 MISSING_CASE(aux_ch);
1867                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1868         }
1869 }
1870
1871 static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
1872 {
1873         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1874         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1875         enum aux_ch aux_ch = dig_port->aux_ch;
1876
1877         switch (aux_ch) {
1878         case AUX_CH_A:
1879         case AUX_CH_B:
1880         case AUX_CH_C:
1881         case AUX_CH_USBC1:
1882         case AUX_CH_USBC2:
1883         case AUX_CH_USBC3:
1884         case AUX_CH_USBC4:
1885         case AUX_CH_USBC5:
1886         case AUX_CH_USBC6:
1887                 return DP_AUX_CH_CTL(aux_ch);
1888         default:
1889                 MISSING_CASE(aux_ch);
1890                 return DP_AUX_CH_CTL(AUX_CH_A);
1891         }
1892 }
1893
1894 static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
1895 {
1896         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1897         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1898         enum aux_ch aux_ch = dig_port->aux_ch;
1899
1900         switch (aux_ch) {
1901         case AUX_CH_A:
1902         case AUX_CH_B:
1903         case AUX_CH_C:
1904         case AUX_CH_USBC1:
1905         case AUX_CH_USBC2:
1906         case AUX_CH_USBC3:
1907         case AUX_CH_USBC4:
1908         case AUX_CH_USBC5:
1909         case AUX_CH_USBC6:
1910                 return DP_AUX_CH_DATA(aux_ch, index);
1911         default:
1912                 MISSING_CASE(aux_ch);
1913                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1914         }
1915 }
1916
1917 static void
1918 intel_dp_aux_fini(struct intel_dp *intel_dp)
1919 {
1920         kfree(intel_dp->aux.name);
1921 }
1922
1923 static void
1924 intel_dp_aux_init(struct intel_dp *intel_dp)
1925 {
1926         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1927         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1928         struct intel_encoder *encoder = &dig_port->base;
1929         enum aux_ch aux_ch = dig_port->aux_ch;
1930
1931         if (INTEL_GEN(dev_priv) >= 12) {
1932                 intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
1933                 intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
1934         } else if (INTEL_GEN(dev_priv) >= 9) {
1935                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1936                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1937         } else if (HAS_PCH_SPLIT(dev_priv)) {
1938                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1939                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1940         } else {
1941                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1942                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1943         }
1944
1945         if (INTEL_GEN(dev_priv) >= 9)
1946                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1947         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1948                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1949         else if (HAS_PCH_SPLIT(dev_priv))
1950                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1951         else
1952                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1953
1954         if (INTEL_GEN(dev_priv) >= 9)
1955                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1956         else
1957                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1958
1959         drm_dp_aux_init(&intel_dp->aux);
1960
1961         /* Failure to allocate our preferred name is not critical */
1962         if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
1963                 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
1964                                                aux_ch - AUX_CH_USBC1 + '1',
1965                                                encoder->base.name);
1966         else
1967                 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
1968                                                aux_ch_name(aux_ch),
1969                                                encoder->base.name);
1970
1971         intel_dp->aux.transfer = intel_dp_aux_transfer;
1972 }
1973
1974 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1975 {
1976         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1977
1978         return max_rate >= 540000;
1979 }
1980
1981 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1982 {
1983         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1984
1985         return max_rate >= 810000;
1986 }
1987
1988 static void
1989 intel_dp_set_clock(struct intel_encoder *encoder,
1990                    struct intel_crtc_state *pipe_config)
1991 {
1992         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1993         const struct dp_link_dpll *divisor = NULL;
1994         int i, count = 0;
1995
1996         if (IS_G4X(dev_priv)) {
1997                 divisor = g4x_dpll;
1998                 count = ARRAY_SIZE(g4x_dpll);
1999         } else if (HAS_PCH_SPLIT(dev_priv)) {
2000                 divisor = pch_dpll;
2001                 count = ARRAY_SIZE(pch_dpll);
2002         } else if (IS_CHERRYVIEW(dev_priv)) {
2003                 divisor = chv_dpll;
2004                 count = ARRAY_SIZE(chv_dpll);
2005         } else if (IS_VALLEYVIEW(dev_priv)) {
2006                 divisor = vlv_dpll;
2007                 count = ARRAY_SIZE(vlv_dpll);
2008         }
2009
2010         if (divisor && count) {
2011                 for (i = 0; i < count; i++) {
2012                         if (pipe_config->port_clock == divisor[i].clock) {
2013                                 pipe_config->dpll = divisor[i].dpll;
2014                                 pipe_config->clock_set = true;
2015                                 break;
2016                         }
2017                 }
2018         }
2019 }
2020
2021 static void snprintf_int_array(char *str, size_t len,
2022                                const int *array, int nelem)
2023 {
2024         int i;
2025
2026         str[0] = '\0';
2027
2028         for (i = 0; i < nelem; i++) {
2029                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
2030                 if (r >= len)
2031                         return;
2032                 str += r;
2033                 len -= r;
2034         }
2035 }
2036
2037 static void intel_dp_print_rates(struct intel_dp *intel_dp)
2038 {
2039         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2040         char str[128]; /* FIXME: too big for stack? */
2041
2042         if (!drm_debug_enabled(DRM_UT_KMS))
2043                 return;
2044
2045         snprintf_int_array(str, sizeof(str),
2046                            intel_dp->source_rates, intel_dp->num_source_rates);
2047         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
2048
2049         snprintf_int_array(str, sizeof(str),
2050                            intel_dp->sink_rates, intel_dp->num_sink_rates);
2051         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
2052
2053         snprintf_int_array(str, sizeof(str),
2054                            intel_dp->common_rates, intel_dp->num_common_rates);
2055         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
2056 }
2057
2058 int
2059 intel_dp_max_link_rate(struct intel_dp *intel_dp)
2060 {
2061         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2062         int len;
2063
2064         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
2065         if (drm_WARN_ON(&i915->drm, len <= 0))
2066                 return 162000;
2067
2068         return intel_dp->common_rates[len - 1];
2069 }
2070
2071 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
2072 {
2073         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2074         int i = intel_dp_rate_index(intel_dp->sink_rates,
2075                                     intel_dp->num_sink_rates, rate);
2076
2077         if (drm_WARN_ON(&i915->drm, i < 0))
2078                 i = 0;
2079
2080         return i;
2081 }
2082
2083 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
2084                            u8 *link_bw, u8 *rate_select)
2085 {
2086         /* eDP 1.4 rate select method. */
2087         if (intel_dp->use_rate_select) {
2088                 *link_bw = 0;
2089                 *rate_select =
2090                         intel_dp_rate_select(intel_dp, port_clock);
2091         } else {
2092                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
2093                 *rate_select = 0;
2094         }
2095 }
2096
2097 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
2098                                          const struct intel_crtc_state *pipe_config)
2099 {
2100         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2101
2102         /* On TGL, FEC is supported on all Pipes */
2103         if (INTEL_GEN(dev_priv) >= 12)
2104                 return true;
2105
2106         if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
2107                 return true;
2108
2109         return false;
2110 }
2111
2112 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
2113                                   const struct intel_crtc_state *pipe_config)
2114 {
2115         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
2116                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
2117 }
2118
2119 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
2120                                   const struct intel_crtc_state *crtc_state)
2121 {
2122         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
2123                 return false;
2124
2125         return intel_dsc_source_support(crtc_state) &&
2126                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
2127 }
2128
2129 static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp,
2130                                    const struct intel_crtc_state *crtc_state)
2131 {
2132         return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2133                 (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
2134                  intel_dp->dfp.ycbcr_444_to_420);
2135 }
2136
2137 static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp,
2138                                     const struct intel_crtc_state *crtc_state, int bpc)
2139 {
2140         int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8;
2141
2142         if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state))
2143                 clock /= 2;
2144
2145         return clock;
2146 }
2147
2148 static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
2149                                            const struct intel_crtc_state *crtc_state, int bpc)
2150 {
2151         int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc);
2152
2153         if (intel_dp->dfp.min_tmds_clock &&
2154             tmds_clock < intel_dp->dfp.min_tmds_clock)
2155                 return false;
2156
2157         if (intel_dp->dfp.max_tmds_clock &&
2158             tmds_clock > intel_dp->dfp.max_tmds_clock)
2159                 return false;
2160
2161         return true;
2162 }
2163
2164 static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp,
2165                                               const struct intel_crtc_state *crtc_state,
2166                                               int bpc)
2167 {
2168
2169         return intel_hdmi_deep_color_possible(crtc_state, bpc,
2170                                               intel_dp->has_hdmi_sink,
2171                                               intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
2172                 intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
2173 }
2174
2175 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
2176                             const struct intel_crtc_state *crtc_state)
2177 {
2178         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2179         struct intel_connector *intel_connector = intel_dp->attached_connector;
2180         int bpp, bpc;
2181
2182         bpc = crtc_state->pipe_bpp / 3;
2183
2184         if (intel_dp->dfp.max_bpc)
2185                 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
2186
2187         if (intel_dp->dfp.min_tmds_clock) {
2188                 for (; bpc >= 10; bpc -= 2) {
2189                         if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc))
2190                                 break;
2191                 }
2192         }
2193
2194         bpp = bpc * 3;
2195         if (intel_dp_is_edp(intel_dp)) {
2196                 /* Get bpp from vbt only for panels that dont have bpp in edid */
2197                 if (intel_connector->base.display_info.bpc == 0 &&
2198                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
2199                         drm_dbg_kms(&dev_priv->drm,
2200                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
2201                                     dev_priv->vbt.edp.bpp);
2202                         bpp = dev_priv->vbt.edp.bpp;
2203                 }
2204         }
2205
2206         return bpp;
2207 }
2208
2209 /* Adjust link config limits based on compliance test requests. */
2210 void
2211 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
2212                                   struct intel_crtc_state *pipe_config,
2213                                   struct link_config_limits *limits)
2214 {
2215         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2216
2217         /* For DP Compliance we override the computed bpp for the pipe */
2218         if (intel_dp->compliance.test_data.bpc != 0) {
2219                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
2220
2221                 limits->min_bpp = limits->max_bpp = bpp;
2222                 pipe_config->dither_force_disable = bpp == 6 * 3;
2223
2224                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
2225         }
2226
2227         /* Use values requested by Compliance Test Request */
2228         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
2229                 int index;
2230
2231                 /* Validate the compliance test data since max values
2232                  * might have changed due to link train fallback.
2233                  */
2234                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
2235                                                intel_dp->compliance.test_lane_count)) {
2236                         index = intel_dp_rate_index(intel_dp->common_rates,
2237                                                     intel_dp->num_common_rates,
2238                                                     intel_dp->compliance.test_link_rate);
2239                         if (index >= 0)
2240                                 limits->min_clock = limits->max_clock = index;
2241                         limits->min_lane_count = limits->max_lane_count =
2242                                 intel_dp->compliance.test_lane_count;
2243                 }
2244         }
2245 }
2246
2247 /* Optimize link config in order: max bpp, min clock, min lanes */
2248 static int
2249 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
2250                                   struct intel_crtc_state *pipe_config,
2251                                   const struct link_config_limits *limits)
2252 {
2253         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2254         int bpp, clock, lane_count;
2255         int mode_rate, link_clock, link_avail;
2256
2257         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
2258                 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
2259
2260                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
2261                                                    output_bpp);
2262
2263                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
2264                         for (lane_count = limits->min_lane_count;
2265                              lane_count <= limits->max_lane_count;
2266                              lane_count <<= 1) {
2267                                 link_clock = intel_dp->common_rates[clock];
2268                                 link_avail = intel_dp_max_data_rate(link_clock,
2269                                                                     lane_count);
2270
2271                                 if (mode_rate <= link_avail) {
2272                                         pipe_config->lane_count = lane_count;
2273                                         pipe_config->pipe_bpp = bpp;
2274                                         pipe_config->port_clock = link_clock;
2275
2276                                         return 0;
2277                                 }
2278                         }
2279                 }
2280         }
2281
2282         return -EINVAL;
2283 }
2284
2285 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
2286 {
2287         int i, num_bpc;
2288         u8 dsc_bpc[3] = {0};
2289
2290         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
2291                                                        dsc_bpc);
2292         for (i = 0; i < num_bpc; i++) {
2293                 if (dsc_max_bpc >= dsc_bpc[i])
2294                         return dsc_bpc[i] * 3;
2295         }
2296
2297         return 0;
2298 }
2299
2300 #define DSC_SUPPORTED_VERSION_MIN               1
2301
2302 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
2303                                        struct intel_crtc_state *crtc_state)
2304 {
2305         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2306         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2307         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
2308         u8 line_buf_depth;
2309         int ret;
2310
2311         ret = intel_dsc_compute_params(encoder, crtc_state);
2312         if (ret)
2313                 return ret;
2314
2315         /*
2316          * Slice Height of 8 works for all currently available panels. So start
2317          * with that if pic_height is an integral multiple of 8. Eventually add
2318          * logic to try multiple slice heights.
2319          */
2320         if (vdsc_cfg->pic_height % 8 == 0)
2321                 vdsc_cfg->slice_height = 8;
2322         else if (vdsc_cfg->pic_height % 4 == 0)
2323                 vdsc_cfg->slice_height = 4;
2324         else
2325                 vdsc_cfg->slice_height = 2;
2326
2327         vdsc_cfg->dsc_version_major =
2328                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2329                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
2330         vdsc_cfg->dsc_version_minor =
2331                 min(DSC_SUPPORTED_VERSION_MIN,
2332                     (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2333                      DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
2334
2335         vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
2336                 DP_DSC_RGB;
2337
2338         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
2339         if (!line_buf_depth) {
2340                 drm_dbg_kms(&i915->drm,
2341                             "DSC Sink Line Buffer Depth invalid\n");
2342                 return -EINVAL;
2343         }
2344
2345         if (vdsc_cfg->dsc_version_minor == 2)
2346                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
2347                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
2348         else
2349                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
2350                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
2351
2352         vdsc_cfg->block_pred_enable =
2353                 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
2354                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
2355
2356         return drm_dsc_compute_rc_parameters(vdsc_cfg);
2357 }
2358
2359 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2360                                        struct intel_crtc_state *pipe_config,
2361                                        struct drm_connector_state *conn_state,
2362                                        struct link_config_limits *limits)
2363 {
2364         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2365         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2366         const struct drm_display_mode *adjusted_mode =
2367                 &pipe_config->hw.adjusted_mode;
2368         u8 dsc_max_bpc;
2369         int pipe_bpp;
2370         int ret;
2371
2372         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2373                 intel_dp_supports_fec(intel_dp, pipe_config);
2374
2375         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
2376                 return -EINVAL;
2377
2378         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
2379         if (INTEL_GEN(dev_priv) >= 12)
2380                 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
2381         else
2382                 dsc_max_bpc = min_t(u8, 10,
2383                                     conn_state->max_requested_bpc);
2384
2385         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
2386
2387         /* Min Input BPC for ICL+ is 8 */
2388         if (pipe_bpp < 8 * 3) {
2389                 drm_dbg_kms(&dev_priv->drm,
2390                             "No DSC support for less than 8bpc\n");
2391                 return -EINVAL;
2392         }
2393
2394         /*
2395          * For now enable DSC for max bpp, max link rate, max lane count.
2396          * Optimize this later for the minimum possible link rate/lane count
2397          * with DSC enabled for the requested mode.
2398          */
2399         pipe_config->pipe_bpp = pipe_bpp;
2400         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
2401         pipe_config->lane_count = limits->max_lane_count;
2402
2403         if (intel_dp_is_edp(intel_dp)) {
2404                 pipe_config->dsc.compressed_bpp =
2405                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
2406                               pipe_config->pipe_bpp);
2407                 pipe_config->dsc.slice_count =
2408                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
2409                                                         true);
2410         } else {
2411                 u16 dsc_max_output_bpp;
2412                 u8 dsc_dp_slice_count;
2413
2414                 dsc_max_output_bpp =
2415                         intel_dp_dsc_get_output_bpp(dev_priv,
2416                                                     pipe_config->port_clock,
2417                                                     pipe_config->lane_count,
2418                                                     adjusted_mode->crtc_clock,
2419                                                     adjusted_mode->crtc_hdisplay,
2420                                                     pipe_config->bigjoiner);
2421                 dsc_dp_slice_count =
2422                         intel_dp_dsc_get_slice_count(intel_dp,
2423                                                      adjusted_mode->crtc_clock,
2424                                                      adjusted_mode->crtc_hdisplay,
2425                                                      pipe_config->bigjoiner);
2426                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
2427                         drm_dbg_kms(&dev_priv->drm,
2428                                     "Compressed BPP/Slice Count not supported\n");
2429                         return -EINVAL;
2430                 }
2431                 pipe_config->dsc.compressed_bpp = min_t(u16,
2432                                                                dsc_max_output_bpp >> 4,
2433                                                                pipe_config->pipe_bpp);
2434                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2435         }
2436         /*
2437          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2438          * is greater than the maximum Cdclock and if slice count is even
2439          * then we need to use 2 VDSC instances.
2440          */
2441         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
2442             pipe_config->bigjoiner) {
2443                 if (pipe_config->dsc.slice_count < 2) {
2444                         drm_dbg_kms(&dev_priv->drm,
2445                                     "Cannot split stream to use 2 VDSC instances\n");
2446                         return -EINVAL;
2447                 }
2448
2449                 pipe_config->dsc.dsc_split = true;
2450         }
2451
2452         ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
2453         if (ret < 0) {
2454                 drm_dbg_kms(&dev_priv->drm,
2455                             "Cannot compute valid DSC parameters for Input Bpp = %d "
2456                             "Compressed BPP = %d\n",
2457                             pipe_config->pipe_bpp,
2458                             pipe_config->dsc.compressed_bpp);
2459                 return ret;
2460         }
2461
2462         pipe_config->dsc.compression_enable = true;
2463         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2464                     "Compressed Bpp = %d Slice Count = %d\n",
2465                     pipe_config->pipe_bpp,
2466                     pipe_config->dsc.compressed_bpp,
2467                     pipe_config->dsc.slice_count);
2468
2469         return 0;
2470 }
2471
2472 static int
2473 intel_dp_compute_link_config(struct intel_encoder *encoder,
2474                              struct intel_crtc_state *pipe_config,
2475                              struct drm_connector_state *conn_state)
2476 {
2477         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2478         const struct drm_display_mode *adjusted_mode =
2479                 &pipe_config->hw.adjusted_mode;
2480         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2481         struct link_config_limits limits;
2482         int common_len;
2483         int ret;
2484
2485         common_len = intel_dp_common_len_rate_limit(intel_dp,
2486                                                     intel_dp->max_link_rate);
2487
2488         /* No common link rates between source and sink */
2489         drm_WARN_ON(encoder->base.dev, common_len <= 0);
2490
2491         limits.min_clock = 0;
2492         limits.max_clock = common_len - 1;
2493
2494         limits.min_lane_count = 1;
2495         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2496
2497         limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
2498         limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config);
2499
2500         if (intel_dp_is_edp(intel_dp)) {
2501                 /*
2502                  * Use the maximum clock and number of lanes the eDP panel
2503                  * advertizes being capable of. The panels are generally
2504                  * designed to support only a single clock and lane
2505                  * configuration, and typically these values correspond to the
2506                  * native resolution of the panel.
2507                  */
2508                 limits.min_lane_count = limits.max_lane_count;
2509                 limits.min_clock = limits.max_clock;
2510         }
2511
2512         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2513
2514         drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
2515                     "max rate %d max bpp %d pixel clock %iKHz\n",
2516                     limits.max_lane_count,
2517                     intel_dp->common_rates[limits.max_clock],
2518                     limits.max_bpp, adjusted_mode->crtc_clock);
2519
2520         if ((adjusted_mode->crtc_clock > i915->max_dotclk_freq ||
2521              adjusted_mode->crtc_hdisplay > 5120) &&
2522             intel_dp_can_bigjoiner(intel_dp))
2523                 pipe_config->bigjoiner = true;
2524
2525         /*
2526          * Optimize for slow and wide. This is the place to add alternative
2527          * optimization policy.
2528          */
2529         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2530
2531         /* enable compression if the mode doesn't fit available BW */
2532         drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
2533         if (ret || intel_dp->force_dsc_en || pipe_config->bigjoiner) {
2534                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2535                                                   conn_state, &limits);
2536                 if (ret < 0)
2537                         return ret;
2538         }
2539
2540         if (pipe_config->dsc.compression_enable) {
2541                 drm_dbg_kms(&i915->drm,
2542                             "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2543                             pipe_config->lane_count, pipe_config->port_clock,
2544                             pipe_config->pipe_bpp,
2545                             pipe_config->dsc.compressed_bpp);
2546
2547                 drm_dbg_kms(&i915->drm,
2548                             "DP link rate required %i available %i\n",
2549                             intel_dp_link_required(adjusted_mode->crtc_clock,
2550                                                    pipe_config->dsc.compressed_bpp),
2551                             intel_dp_max_data_rate(pipe_config->port_clock,
2552                                                    pipe_config->lane_count));
2553         } else {
2554                 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
2555                             pipe_config->lane_count, pipe_config->port_clock,
2556                             pipe_config->pipe_bpp);
2557
2558                 drm_dbg_kms(&i915->drm,
2559                             "DP link rate required %i available %i\n",
2560                             intel_dp_link_required(adjusted_mode->crtc_clock,
2561                                                    pipe_config->pipe_bpp),
2562                             intel_dp_max_data_rate(pipe_config->port_clock,
2563                                                    pipe_config->lane_count));
2564         }
2565         return 0;
2566 }
2567
2568 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2569                                   const struct drm_connector_state *conn_state)
2570 {
2571         const struct intel_digital_connector_state *intel_conn_state =
2572                 to_intel_digital_connector_state(conn_state);
2573         const struct drm_display_mode *adjusted_mode =
2574                 &crtc_state->hw.adjusted_mode;
2575
2576         /*
2577          * Our YCbCr output is always limited range.
2578          * crtc_state->limited_color_range only applies to RGB,
2579          * and it must never be set for YCbCr or we risk setting
2580          * some conflicting bits in PIPECONF which will mess up
2581          * the colors on the monitor.
2582          */
2583         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2584                 return false;
2585
2586         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2587                 /*
2588                  * See:
2589                  * CEA-861-E - 5.1 Default Encoding Parameters
2590                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2591                  */
2592                 return crtc_state->pipe_bpp != 18 &&
2593                         drm_default_rgb_quant_range(adjusted_mode) ==
2594                         HDMI_QUANTIZATION_RANGE_LIMITED;
2595         } else {
2596                 return intel_conn_state->broadcast_rgb ==
2597                         INTEL_BROADCAST_RGB_LIMITED;
2598         }
2599 }
2600
2601 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2602                                     enum port port)
2603 {
2604         if (IS_G4X(dev_priv))
2605                 return false;
2606         if (INTEL_GEN(dev_priv) < 12 && port == PORT_A)
2607                 return false;
2608
2609         return true;
2610 }
2611
2612 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2613                                              const struct drm_connector_state *conn_state,
2614                                              struct drm_dp_vsc_sdp *vsc)
2615 {
2616         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2617         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2618
2619         /*
2620          * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2621          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2622          * Colorimetry Format indication.
2623          */
2624         vsc->revision = 0x5;
2625         vsc->length = 0x13;
2626
2627         /* DP 1.4a spec, Table 2-120 */
2628         switch (crtc_state->output_format) {
2629         case INTEL_OUTPUT_FORMAT_YCBCR444:
2630                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2631                 break;
2632         case INTEL_OUTPUT_FORMAT_YCBCR420:
2633                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2634                 break;
2635         case INTEL_OUTPUT_FORMAT_RGB:
2636         default:
2637                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2638         }
2639
2640         switch (conn_state->colorspace) {
2641         case DRM_MODE_COLORIMETRY_BT709_YCC:
2642                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2643                 break;
2644         case DRM_MODE_COLORIMETRY_XVYCC_601:
2645                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2646                 break;
2647         case DRM_MODE_COLORIMETRY_XVYCC_709:
2648                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2649                 break;
2650         case DRM_MODE_COLORIMETRY_SYCC_601:
2651                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2652                 break;
2653         case DRM_MODE_COLORIMETRY_OPYCC_601:
2654                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2655                 break;
2656         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2657                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2658                 break;
2659         case DRM_MODE_COLORIMETRY_BT2020_RGB:
2660                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2661                 break;
2662         case DRM_MODE_COLORIMETRY_BT2020_YCC:
2663                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2664                 break;
2665         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2666         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2667                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2668                 break;
2669         default:
2670                 /*
2671                  * RGB->YCBCR color conversion uses the BT.709
2672                  * color space.
2673                  */
2674                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2675                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2676                 else
2677                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2678                 break;
2679         }
2680
2681         vsc->bpc = crtc_state->pipe_bpp / 3;
2682
2683         /* only RGB pixelformat supports 6 bpc */
2684         drm_WARN_ON(&dev_priv->drm,
2685                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2686
2687         /* all YCbCr are always limited range */
2688         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2689         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2690 }
2691
2692 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2693                                      struct intel_crtc_state *crtc_state,
2694                                      const struct drm_connector_state *conn_state)
2695 {
2696         struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
2697
2698         /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
2699         if (crtc_state->has_psr)
2700                 return;
2701
2702         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
2703                 return;
2704
2705         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2706         vsc->sdp_type = DP_SDP_VSC;
2707         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2708                                          &crtc_state->infoframes.vsc);
2709 }
2710
2711 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
2712                                   const struct intel_crtc_state *crtc_state,
2713                                   const struct drm_connector_state *conn_state,
2714                                   struct drm_dp_vsc_sdp *vsc)
2715 {
2716         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2717
2718         vsc->sdp_type = DP_SDP_VSC;
2719
2720         if (dev_priv->psr.psr2_enabled) {
2721                 if (dev_priv->psr.colorimetry_support &&
2722                     intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2723                         /* [PSR2, +Colorimetry] */
2724                         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2725                                                          vsc);
2726                 } else {
2727                         /*
2728                          * [PSR2, -Colorimetry]
2729                          * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2730                          * 3D stereo + PSR/PSR2 + Y-coordinate.
2731                          */
2732                         vsc->revision = 0x4;
2733                         vsc->length = 0xe;
2734                 }
2735         } else {
2736                 /*
2737                  * [PSR1]
2738                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2739                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2740                  * higher).
2741                  */
2742                 vsc->revision = 0x2;
2743                 vsc->length = 0x8;
2744         }
2745 }
2746
2747 static void
2748 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2749                                             struct intel_crtc_state *crtc_state,
2750                                             const struct drm_connector_state *conn_state)
2751 {
2752         int ret;
2753         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2754         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2755
2756         if (!conn_state->hdr_output_metadata)
2757                 return;
2758
2759         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2760
2761         if (ret) {
2762                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2763                 return;
2764         }
2765
2766         crtc_state->infoframes.enable |=
2767                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2768 }
2769
2770 static void
2771 intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
2772                              struct intel_crtc_state *pipe_config,
2773                              int output_bpp, bool constant_n)
2774 {
2775         struct intel_connector *intel_connector = intel_dp->attached_connector;
2776         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2777
2778         /*
2779          * DRRS and PSR can't be enable together, so giving preference to PSR
2780          * as it allows more power-savings by complete shutting down display,
2781          * so to guarantee this, intel_dp_drrs_compute_config() must be called
2782          * after intel_psr_compute_config().
2783          */
2784         if (pipe_config->has_psr)
2785                 return;
2786
2787         if (!intel_connector->panel.downclock_mode ||
2788             dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
2789                 return;
2790
2791         pipe_config->has_drrs = true;
2792         intel_link_compute_m_n(output_bpp, pipe_config->lane_count,
2793                                intel_connector->panel.downclock_mode->clock,
2794                                pipe_config->port_clock, &pipe_config->dp_m2_n2,
2795                                constant_n, pipe_config->fec_enable);
2796 }
2797
2798 int
2799 intel_dp_compute_config(struct intel_encoder *encoder,
2800                         struct intel_crtc_state *pipe_config,
2801                         struct drm_connector_state *conn_state)
2802 {
2803         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2804         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2805         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2806         enum port port = encoder->port;
2807         struct intel_connector *intel_connector = intel_dp->attached_connector;
2808         struct intel_digital_connector_state *intel_conn_state =
2809                 to_intel_digital_connector_state(conn_state);
2810         bool constant_n = drm_dp_has_quirk(&intel_dp->desc, 0,
2811                                            DP_DPCD_QUIRK_CONSTANT_N);
2812         int ret = 0, output_bpp;
2813
2814         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2815                 pipe_config->has_pch_encoder = true;
2816
2817         pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
2818                                                             adjusted_mode);
2819
2820         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2821                 ret = intel_pch_panel_fitting(pipe_config, conn_state);
2822                 if (ret)
2823                         return ret;
2824         }
2825
2826         if (!intel_dp_port_has_audio(dev_priv, port))
2827                 pipe_config->has_audio = false;
2828         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2829                 pipe_config->has_audio = intel_dp->has_audio;
2830         else
2831                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2832
2833         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2834                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2835                                        adjusted_mode);
2836
2837                 if (HAS_GMCH(dev_priv))
2838                         ret = intel_gmch_panel_fitting(pipe_config, conn_state);
2839                 else
2840                         ret = intel_pch_panel_fitting(pipe_config, conn_state);
2841                 if (ret)
2842                         return ret;
2843         }
2844
2845         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2846                 return -EINVAL;
2847
2848         if (HAS_GMCH(dev_priv) &&
2849             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2850                 return -EINVAL;
2851
2852         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2853                 return -EINVAL;
2854
2855         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2856                 return -EINVAL;
2857
2858         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2859         if (ret < 0)
2860                 return ret;
2861
2862         pipe_config->limited_color_range =
2863                 intel_dp_limited_color_range(pipe_config, conn_state);
2864
2865         if (pipe_config->dsc.compression_enable)
2866                 output_bpp = pipe_config->dsc.compressed_bpp;
2867         else
2868                 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
2869                                                  pipe_config->pipe_bpp);
2870
2871         intel_link_compute_m_n(output_bpp,
2872                                pipe_config->lane_count,
2873                                adjusted_mode->crtc_clock,
2874                                pipe_config->port_clock,
2875                                &pipe_config->dp_m_n,
2876                                constant_n, pipe_config->fec_enable);
2877
2878         if (!HAS_DDI(dev_priv))
2879                 intel_dp_set_clock(encoder, pipe_config);
2880
2881         intel_psr_compute_config(intel_dp, pipe_config);
2882         intel_dp_drrs_compute_config(intel_dp, pipe_config, output_bpp,
2883                                      constant_n);
2884         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2885         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2886
2887         return 0;
2888 }
2889
2890 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2891                               int link_rate, int lane_count)
2892 {
2893         intel_dp->link_trained = false;
2894         intel_dp->link_rate = link_rate;
2895         intel_dp->lane_count = lane_count;
2896 }
2897
2898 static void intel_dp_prepare(struct intel_encoder *encoder,
2899                              const struct intel_crtc_state *pipe_config)
2900 {
2901         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2902         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2903         enum port port = encoder->port;
2904         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2905         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2906
2907         intel_dp_set_link_params(intel_dp,
2908                                  pipe_config->port_clock,
2909                                  pipe_config->lane_count);
2910
2911         /*
2912          * There are four kinds of DP registers:
2913          *
2914          *      IBX PCH
2915          *      SNB CPU
2916          *      IVB CPU
2917          *      CPT PCH
2918          *
2919          * IBX PCH and CPU are the same for almost everything,
2920          * except that the CPU DP PLL is configured in this
2921          * register
2922          *
2923          * CPT PCH is quite different, having many bits moved
2924          * to the TRANS_DP_CTL register instead. That
2925          * configuration happens (oddly) in ilk_pch_enable
2926          */
2927
2928         /* Preserve the BIOS-computed detected bit. This is
2929          * supposed to be read-only.
2930          */
2931         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
2932
2933         /* Handle DP bits in common between all three register formats */
2934         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2935         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2936
2937         /* Split out the IBX/CPU vs CPT settings */
2938
2939         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2940                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2941                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2942                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2943                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2944                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2945
2946                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2947                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2948
2949                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2950         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2951                 u32 trans_dp;
2952
2953                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2954
2955                 trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe));
2956                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2957                         trans_dp |= TRANS_DP_ENH_FRAMING;
2958                 else
2959                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2960                 intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp);
2961         } else {
2962                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2963                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2964
2965                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2966                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2967                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2968                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2969                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2970
2971                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2972                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2973
2974                 if (IS_CHERRYVIEW(dev_priv))
2975                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2976                 else
2977                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2978         }
2979 }
2980
2981 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2982 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2983
2984 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2985 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2986
2987 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2988 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2989
2990 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2991
2992 static void wait_panel_status(struct intel_dp *intel_dp,
2993                                        u32 mask,
2994                                        u32 value)
2995 {
2996         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2997         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2998
2999         lockdep_assert_held(&dev_priv->pps_mutex);
3000
3001         intel_pps_verify_state(intel_dp);
3002
3003         pp_stat_reg = _pp_stat_reg(intel_dp);
3004         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3005
3006         drm_dbg_kms(&dev_priv->drm,
3007                     "mask %08x value %08x status %08x control %08x\n",
3008                     mask, value,
3009                     intel_de_read(dev_priv, pp_stat_reg),
3010                     intel_de_read(dev_priv, pp_ctrl_reg));
3011
3012         if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
3013                                        mask, value, 5000))
3014                 drm_err(&dev_priv->drm,
3015                         "Panel status timeout: status %08x control %08x\n",
3016                         intel_de_read(dev_priv, pp_stat_reg),
3017                         intel_de_read(dev_priv, pp_ctrl_reg));
3018
3019         drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
3020 }
3021
3022 static void wait_panel_on(struct intel_dp *intel_dp)
3023 {
3024         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3025
3026         drm_dbg_kms(&i915->drm, "Wait for panel power on\n");
3027         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
3028 }
3029
3030 static void wait_panel_off(struct intel_dp *intel_dp)
3031 {
3032         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3033
3034         drm_dbg_kms(&i915->drm, "Wait for panel power off time\n");
3035         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
3036 }
3037
3038 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
3039 {
3040         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3041         ktime_t panel_power_on_time;
3042         s64 panel_power_off_duration;
3043
3044         drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n");
3045
3046         /* take the difference of currrent time and panel power off time
3047          * and then make panel wait for t11_t12 if needed. */
3048         panel_power_on_time = ktime_get_boottime();
3049         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
3050
3051         /* When we disable the VDD override bit last we have to do the manual
3052          * wait. */
3053         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
3054                 wait_remaining_ms_from_jiffies(jiffies,
3055                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
3056
3057         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
3058 }
3059
3060 static void wait_backlight_on(struct intel_dp *intel_dp)
3061 {
3062         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
3063                                        intel_dp->backlight_on_delay);
3064 }
3065
3066 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
3067 {
3068         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
3069                                        intel_dp->backlight_off_delay);
3070 }
3071
3072 /* Read the current pp_control value, unlocking the register if it
3073  * is locked
3074  */
3075
3076 static  u32 ilk_get_pp_control(struct intel_dp *intel_dp)
3077 {
3078         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3079         u32 control;
3080
3081         lockdep_assert_held(&dev_priv->pps_mutex);
3082
3083         control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
3084         if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
3085                         (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
3086                 control &= ~PANEL_UNLOCK_MASK;
3087                 control |= PANEL_UNLOCK_REGS;
3088         }
3089         return control;
3090 }
3091
3092 /*
3093  * Must be paired with edp_panel_vdd_off().
3094  * Must hold pps_mutex around the whole on/off sequence.
3095  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
3096  */
3097 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
3098 {
3099         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3100         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3101         u32 pp;
3102         i915_reg_t pp_stat_reg, pp_ctrl_reg;
3103         bool need_to_disable = !intel_dp->want_panel_vdd;
3104
3105         lockdep_assert_held(&dev_priv->pps_mutex);
3106
3107         if (!intel_dp_is_edp(intel_dp))
3108                 return false;
3109
3110         cancel_delayed_work(&intel_dp->panel_vdd_work);
3111         intel_dp->want_panel_vdd = true;
3112
3113         if (edp_have_panel_vdd(intel_dp))
3114                 return need_to_disable;
3115
3116         intel_display_power_get(dev_priv,
3117                                 intel_aux_power_domain(dig_port));
3118
3119         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
3120                     dig_port->base.base.base.id,
3121                     dig_port->base.base.name);
3122
3123         if (!edp_have_panel_power(intel_dp))
3124                 wait_panel_power_cycle(intel_dp);
3125
3126         pp = ilk_get_pp_control(intel_dp);
3127         pp |= EDP_FORCE_VDD;
3128
3129         pp_stat_reg = _pp_stat_reg(intel_dp);
3130         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3131
3132         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3133         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3134         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
3135                     intel_de_read(dev_priv, pp_stat_reg),
3136                     intel_de_read(dev_priv, pp_ctrl_reg));
3137         /*
3138          * If the panel wasn't on, delay before accessing aux channel
3139          */
3140         if (!edp_have_panel_power(intel_dp)) {
3141                 drm_dbg_kms(&dev_priv->drm,
3142                             "[ENCODER:%d:%s] panel power wasn't enabled\n",
3143                             dig_port->base.base.base.id,
3144                             dig_port->base.base.name);
3145                 msleep(intel_dp->panel_power_up_delay);
3146         }
3147
3148         return need_to_disable;
3149 }
3150
3151 /*
3152  * Must be paired with intel_edp_panel_vdd_off() or
3153  * intel_edp_panel_off().
3154  * Nested calls to these functions are not allowed since
3155  * we drop the lock. Caller must use some higher level
3156  * locking to prevent nested calls from other threads.
3157  */
3158 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
3159 {
3160         intel_wakeref_t wakeref;
3161         bool vdd;
3162
3163         if (!intel_dp_is_edp(intel_dp))
3164                 return;
3165
3166         vdd = false;
3167         with_pps_lock(intel_dp, wakeref)
3168                 vdd = edp_panel_vdd_on(intel_dp);
3169         I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
3170                         dp_to_dig_port(intel_dp)->base.base.base.id,
3171                         dp_to_dig_port(intel_dp)->base.base.name);
3172 }
3173
3174 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
3175 {
3176         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3177         struct intel_digital_port *dig_port =
3178                 dp_to_dig_port(intel_dp);
3179         u32 pp;
3180         i915_reg_t pp_stat_reg, pp_ctrl_reg;
3181
3182         lockdep_assert_held(&dev_priv->pps_mutex);
3183
3184         drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
3185
3186         if (!edp_have_panel_vdd(intel_dp))
3187                 return;
3188
3189         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n",
3190                     dig_port->base.base.base.id,
3191                     dig_port->base.base.name);
3192
3193         pp = ilk_get_pp_control(intel_dp);
3194         pp &= ~EDP_FORCE_VDD;
3195
3196         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3197         pp_stat_reg = _pp_stat_reg(intel_dp);
3198
3199         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3200         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3201
3202         /* Make sure sequencer is idle before allowing subsequent activity */
3203         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
3204                     intel_de_read(dev_priv, pp_stat_reg),
3205                     intel_de_read(dev_priv, pp_ctrl_reg));
3206
3207         if ((pp & PANEL_POWER_ON) == 0)
3208                 intel_dp->panel_power_off_time = ktime_get_boottime();
3209
3210         intel_display_power_put_unchecked(dev_priv,
3211                                           intel_aux_power_domain(dig_port));
3212 }
3213
3214 static void edp_panel_vdd_work(struct work_struct *__work)
3215 {
3216         struct intel_dp *intel_dp =
3217                 container_of(to_delayed_work(__work),
3218                              struct intel_dp, panel_vdd_work);
3219         intel_wakeref_t wakeref;
3220
3221         with_pps_lock(intel_dp, wakeref) {
3222                 if (!intel_dp->want_panel_vdd)
3223                         edp_panel_vdd_off_sync(intel_dp);
3224         }
3225 }
3226
3227 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
3228 {
3229         unsigned long delay;
3230
3231         /*
3232          * Queue the timer to fire a long time from now (relative to the power
3233          * down delay) to keep the panel power up across a sequence of
3234          * operations.
3235          */
3236         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
3237         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
3238 }
3239
3240 /*
3241  * Must be paired with edp_panel_vdd_on().
3242  * Must hold pps_mutex around the whole on/off sequence.
3243  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
3244  */
3245 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
3246 {
3247         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3248
3249         lockdep_assert_held(&dev_priv->pps_mutex);
3250
3251         if (!intel_dp_is_edp(intel_dp))
3252                 return;
3253
3254         I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
3255                         dp_to_dig_port(intel_dp)->base.base.base.id,
3256                         dp_to_dig_port(intel_dp)->base.base.name);
3257
3258         intel_dp->want_panel_vdd = false;
3259
3260         if (sync)
3261                 edp_panel_vdd_off_sync(intel_dp);
3262         else
3263                 edp_panel_vdd_schedule_off(intel_dp);
3264 }
3265
3266 static void edp_panel_on(struct intel_dp *intel_dp)
3267 {
3268         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3269         u32 pp;
3270         i915_reg_t pp_ctrl_reg;
3271
3272         lockdep_assert_held(&dev_priv->pps_mutex);
3273
3274         if (!intel_dp_is_edp(intel_dp))
3275                 return;
3276
3277         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n",
3278                     dp_to_dig_port(intel_dp)->base.base.base.id,
3279                     dp_to_dig_port(intel_dp)->base.base.name);
3280
3281         if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
3282                      "[ENCODER:%d:%s] panel power already on\n",
3283                      dp_to_dig_port(intel_dp)->base.base.base.id,
3284                      dp_to_dig_port(intel_dp)->base.base.name))
3285                 return;
3286
3287         wait_panel_power_cycle(intel_dp);
3288
3289         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3290         pp = ilk_get_pp_control(intel_dp);
3291         if (IS_GEN(dev_priv, 5)) {
3292                 /* ILK workaround: disable reset around power sequence */
3293                 pp &= ~PANEL_POWER_RESET;
3294                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3295                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3296         }
3297
3298         pp |= PANEL_POWER_ON;
3299         if (!IS_GEN(dev_priv, 5))
3300                 pp |= PANEL_POWER_RESET;
3301
3302         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3303         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3304
3305         wait_panel_on(intel_dp);
3306         intel_dp->last_power_on = jiffies;
3307
3308         if (IS_GEN(dev_priv, 5)) {
3309                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
3310                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3311                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3312         }
3313 }
3314
3315 void intel_edp_panel_on(struct intel_dp *intel_dp)
3316 {
3317         intel_wakeref_t wakeref;
3318
3319         if (!intel_dp_is_edp(intel_dp))
3320                 return;
3321
3322         with_pps_lock(intel_dp, wakeref)
3323                 edp_panel_on(intel_dp);
3324 }
3325
3326
3327 static void edp_panel_off(struct intel_dp *intel_dp)
3328 {
3329         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3330         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3331         u32 pp;
3332         i915_reg_t pp_ctrl_reg;
3333
3334         lockdep_assert_held(&dev_priv->pps_mutex);
3335
3336         if (!intel_dp_is_edp(intel_dp))
3337                 return;
3338
3339         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
3340                     dig_port->base.base.base.id, dig_port->base.base.name);
3341
3342         drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
3343                  "Need [ENCODER:%d:%s] VDD to turn off panel\n",
3344                  dig_port->base.base.base.id, dig_port->base.base.name);
3345
3346         pp = ilk_get_pp_control(intel_dp);
3347         /* We need to switch off panel power _and_ force vdd, for otherwise some
3348          * panels get very unhappy and cease to work. */
3349         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
3350                 EDP_BLC_ENABLE);
3351
3352         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3353
3354         intel_dp->want_panel_vdd = false;
3355
3356         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3357         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3358
3359         wait_panel_off(intel_dp);
3360         intel_dp->panel_power_off_time = ktime_get_boottime();
3361
3362         /* We got a reference when we enabled the VDD. */
3363         intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
3364 }
3365
3366 void intel_edp_panel_off(struct intel_dp *intel_dp)
3367 {
3368         intel_wakeref_t wakeref;
3369
3370         if (!intel_dp_is_edp(intel_dp))
3371                 return;
3372
3373         with_pps_lock(intel_dp, wakeref)
3374                 edp_panel_off(intel_dp);
3375 }
3376
3377 /* Enable backlight in the panel power control. */
3378 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
3379 {
3380         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3381         intel_wakeref_t wakeref;
3382
3383         /*
3384          * If we enable the backlight right away following a panel power
3385          * on, we may see slight flicker as the panel syncs with the eDP
3386          * link.  So delay a bit to make sure the image is solid before
3387          * allowing it to appear.
3388          */
3389         wait_backlight_on(intel_dp);
3390
3391         with_pps_lock(intel_dp, wakeref) {
3392                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3393                 u32 pp;
3394
3395                 pp = ilk_get_pp_control(intel_dp);
3396                 pp |= EDP_BLC_ENABLE;
3397
3398                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3399                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3400         }
3401 }
3402
3403 /* Enable backlight PWM and backlight PP control. */
3404 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3405                             const struct drm_connector_state *conn_state)
3406 {
3407         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3408         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3409
3410         if (!intel_dp_is_edp(intel_dp))
3411                 return;
3412
3413         drm_dbg_kms(&i915->drm, "\n");
3414
3415         intel_panel_enable_backlight(crtc_state, conn_state);
3416         _intel_edp_backlight_on(intel_dp);
3417 }
3418
3419 /* Disable backlight in the panel power control. */
3420 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
3421 {
3422         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3423         intel_wakeref_t wakeref;
3424
3425         if (!intel_dp_is_edp(intel_dp))
3426                 return;
3427
3428         with_pps_lock(intel_dp, wakeref) {
3429                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3430                 u32 pp;
3431
3432                 pp = ilk_get_pp_control(intel_dp);
3433                 pp &= ~EDP_BLC_ENABLE;
3434
3435                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3436                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3437         }
3438
3439         intel_dp->last_backlight_off = jiffies;
3440         edp_wait_backlight_off(intel_dp);
3441 }
3442
3443 /* Disable backlight PP control and backlight PWM. */
3444 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3445 {
3446         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3447         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3448
3449         if (!intel_dp_is_edp(intel_dp))
3450                 return;
3451
3452         drm_dbg_kms(&i915->drm, "\n");
3453
3454         _intel_edp_backlight_off(intel_dp);
3455         intel_panel_disable_backlight(old_conn_state);
3456 }
3457
3458 /*
3459  * Hook for controlling the panel power control backlight through the bl_power
3460  * sysfs attribute. Take care to handle multiple calls.
3461  */
3462 static void intel_edp_backlight_power(struct intel_connector *connector,
3463                                       bool enable)
3464 {
3465         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3466         struct intel_dp *intel_dp = intel_attached_dp(connector);
3467         intel_wakeref_t wakeref;
3468         bool is_enabled;
3469
3470         is_enabled = false;
3471         with_pps_lock(intel_dp, wakeref)
3472                 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
3473         if (is_enabled == enable)
3474                 return;
3475
3476         drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
3477                     enable ? "enable" : "disable");
3478
3479         if (enable)
3480                 _intel_edp_backlight_on(intel_dp);
3481         else
3482                 _intel_edp_backlight_off(intel_dp);
3483 }
3484
3485 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
3486 {
3487         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3488         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3489         bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN;
3490
3491         I915_STATE_WARN(cur_state != state,
3492                         "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
3493                         dig_port->base.base.base.id, dig_port->base.base.name,
3494                         onoff(state), onoff(cur_state));
3495 }
3496 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
3497
3498 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
3499 {
3500         bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE;
3501
3502         I915_STATE_WARN(cur_state != state,
3503                         "eDP PLL state assertion failure (expected %s, current %s)\n",
3504                         onoff(state), onoff(cur_state));
3505 }
3506 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
3507 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
3508
3509 static void ilk_edp_pll_on(struct intel_dp *intel_dp,
3510                            const struct intel_crtc_state *pipe_config)
3511 {
3512         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3513         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3514
3515         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
3516         assert_dp_port_disabled(intel_dp);
3517         assert_edp_pll_disabled(dev_priv);
3518
3519         drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",
3520                     pipe_config->port_clock);
3521
3522         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
3523
3524         if (pipe_config->port_clock == 162000)
3525                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
3526         else
3527                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
3528
3529         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3530         intel_de_posting_read(dev_priv, DP_A);
3531         udelay(500);
3532
3533         /*
3534          * [DevILK] Work around required when enabling DP PLL
3535          * while a pipe is enabled going to FDI:
3536          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
3537          * 2. Program DP PLL enable
3538          */
3539         if (IS_GEN(dev_priv, 5))
3540                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
3541
3542         intel_dp->DP |= DP_PLL_ENABLE;
3543
3544         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3545         intel_de_posting_read(dev_priv, DP_A);
3546         udelay(200);
3547 }
3548
3549 static void ilk_edp_pll_off(struct intel_dp *intel_dp,
3550                             const struct intel_crtc_state *old_crtc_state)
3551 {
3552         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3553         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3554
3555         assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
3556         assert_dp_port_disabled(intel_dp);
3557         assert_edp_pll_enabled(dev_priv);
3558
3559         drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n");
3560
3561         intel_dp->DP &= ~DP_PLL_ENABLE;
3562
3563         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3564         intel_de_posting_read(dev_priv, DP_A);
3565         udelay(200);
3566 }
3567
3568 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3569 {
3570         /*
3571          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3572          * be capable of signalling downstream hpd with a long pulse.
3573          * Whether or not that means D3 is safe to use is not clear,
3574          * but let's assume so until proven otherwise.
3575          *
3576          * FIXME should really check all downstream ports...
3577          */
3578         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3579                 drm_dp_is_branch(intel_dp->dpcd) &&
3580                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3581 }
3582
3583 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
3584                                            const struct intel_crtc_state *crtc_state,
3585                                            bool enable)
3586 {
3587         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3588         int ret;
3589
3590         if (!crtc_state->dsc.compression_enable)
3591                 return;
3592
3593         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
3594                                  enable ? DP_DECOMPRESSION_EN : 0);
3595         if (ret < 0)
3596                 drm_dbg_kms(&i915->drm,
3597                             "Failed to %s sink decompression state\n",
3598                             enable ? "enable" : "disable");
3599 }
3600
3601 /* If the device supports it, try to set the power state appropriately */
3602 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
3603 {
3604         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3605         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3606         int ret, i;
3607
3608         /* Should have a valid DPCD by this point */
3609         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3610                 return;
3611
3612         if (mode != DP_SET_POWER_D0) {
3613                 if (downstream_hpd_needs_d0(intel_dp))
3614                         return;
3615
3616                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3617         } else {
3618                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3619
3620                 lspcon_resume(dp_to_dig_port(intel_dp));
3621
3622                 /*
3623                  * When turning on, we need to retry for 1ms to give the sink
3624                  * time to wake up.
3625                  */
3626                 for (i = 0; i < 3; i++) {
3627                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3628                         if (ret == 1)
3629                                 break;
3630                         msleep(1);
3631                 }
3632
3633                 if (ret == 1 && lspcon->active)
3634                         lspcon_wait_pcon_mode(lspcon);
3635         }
3636
3637         if (ret != 1)
3638                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
3639                             encoder->base.base.id, encoder->base.name,
3640                             mode == DP_SET_POWER_D0 ? "D0" : "D3");
3641 }
3642
3643 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
3644                                  enum port port, enum pipe *pipe)
3645 {
3646         enum pipe p;
3647
3648         for_each_pipe(dev_priv, p) {
3649                 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p));
3650
3651                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
3652                         *pipe = p;
3653                         return true;
3654                 }
3655         }
3656
3657         drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n",
3658                     port_name(port));
3659
3660         /* must initialize pipe to something for the asserts */
3661         *pipe = PIPE_A;
3662
3663         return false;
3664 }
3665
3666 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
3667                            i915_reg_t dp_reg, enum port port,
3668                            enum pipe *pipe)
3669 {
3670         bool ret;
3671         u32 val;
3672
3673         val = intel_de_read(dev_priv, dp_reg);
3674
3675         ret = val & DP_PORT_EN;
3676
3677         /* asserts want to know the pipe even if the port is disabled */
3678         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3679                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
3680         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3681                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3682         else if (IS_CHERRYVIEW(dev_priv))
3683                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3684         else
3685                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3686
3687         return ret;
3688 }
3689
3690 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3691                                   enum pipe *pipe)
3692 {
3693         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3694         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3695         intel_wakeref_t wakeref;
3696         bool ret;
3697
3698         wakeref = intel_display_power_get_if_enabled(dev_priv,
3699                                                      encoder->power_domain);
3700         if (!wakeref)
3701                 return false;
3702
3703         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3704                                     encoder->port, pipe);
3705
3706         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3707
3708         return ret;
3709 }
3710
3711 static void intel_dp_get_config(struct intel_encoder *encoder,
3712                                 struct intel_crtc_state *pipe_config)
3713 {
3714         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3715         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3716         u32 tmp, flags = 0;
3717         enum port port = encoder->port;
3718         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3719
3720         if (encoder->type == INTEL_OUTPUT_EDP)
3721                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3722         else
3723                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3724
3725         tmp = intel_de_read(dev_priv, intel_dp->output_reg);
3726
3727         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3728
3729         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3730                 u32 trans_dp = intel_de_read(dev_priv,
3731                                              TRANS_DP_CTL(crtc->pipe));
3732
3733                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3734                         flags |= DRM_MODE_FLAG_PHSYNC;
3735                 else
3736                         flags |= DRM_MODE_FLAG_NHSYNC;
3737
3738                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3739                         flags |= DRM_MODE_FLAG_PVSYNC;
3740                 else
3741                         flags |= DRM_MODE_FLAG_NVSYNC;
3742         } else {
3743                 if (tmp & DP_SYNC_HS_HIGH)
3744                         flags |= DRM_MODE_FLAG_PHSYNC;
3745                 else
3746                         flags |= DRM_MODE_FLAG_NHSYNC;
3747
3748                 if (tmp & DP_SYNC_VS_HIGH)
3749                         flags |= DRM_MODE_FLAG_PVSYNC;
3750                 else
3751                         flags |= DRM_MODE_FLAG_NVSYNC;
3752         }
3753
3754         pipe_config->hw.adjusted_mode.flags |= flags;
3755
3756         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3757                 pipe_config->limited_color_range = true;
3758
3759         pipe_config->lane_count =
3760                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3761
3762         intel_dp_get_m_n(crtc, pipe_config);
3763
3764         if (port == PORT_A) {
3765                 if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3766                         pipe_config->port_clock = 162000;
3767                 else
3768                         pipe_config->port_clock = 270000;
3769         }
3770
3771         pipe_config->hw.adjusted_mode.crtc_clock =
3772                 intel_dotclock_calculate(pipe_config->port_clock,
3773                                          &pipe_config->dp_m_n);
3774
3775         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3776             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3777                 /*
3778                  * This is a big fat ugly hack.
3779                  *
3780                  * Some machines in UEFI boot mode provide us a VBT that has 18
3781                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3782                  * unknown we fail to light up. Yet the same BIOS boots up with
3783                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3784                  * max, not what it tells us to use.
3785                  *
3786                  * Note: This will still be broken if the eDP panel is not lit
3787                  * up by the BIOS, and thus we can't get the mode at module
3788                  * load.
3789                  */
3790                 drm_dbg_kms(&dev_priv->drm,
3791                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3792                             pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3793                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3794         }
3795 }
3796
3797 static bool
3798 intel_dp_get_dpcd(struct intel_dp *intel_dp);
3799
3800 /**
3801  * intel_dp_sync_state - sync the encoder state during init/resume
3802  * @encoder: intel encoder to sync
3803  * @crtc_state: state for the CRTC connected to the encoder
3804  *
3805  * Sync any state stored in the encoder wrt. HW state during driver init
3806  * and system resume.
3807  */
3808 void intel_dp_sync_state(struct intel_encoder *encoder,
3809                          const struct intel_crtc_state *crtc_state)
3810 {
3811         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3812
3813         /*
3814          * Don't clobber DPCD if it's been already read out during output
3815          * setup (eDP) or detect.
3816          */
3817         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3818                 intel_dp_get_dpcd(intel_dp);
3819
3820         intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
3821         intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
3822 }
3823
3824 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
3825                                     struct intel_crtc_state *crtc_state)
3826 {
3827         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3828         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3829
3830         /*
3831          * If BIOS has set an unsupported or non-standard link rate for some
3832          * reason force an encoder recompute and full modeset.
3833          */
3834         if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
3835                                 crtc_state->port_clock) < 0) {
3836                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
3837                 crtc_state->uapi.connectors_changed = true;
3838                 return false;
3839         }
3840
3841         /*
3842          * FIXME hack to force full modeset when DSC is being used.
3843          *
3844          * As long as we do not have full state readout and config comparison
3845          * of crtc_state->dsc, we have no way to ensure reliable fastset.
3846          * Remove once we have readout for DSC.
3847          */
3848         if (crtc_state->dsc.compression_enable) {
3849                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
3850                 crtc_state->uapi.mode_changed = true;
3851                 return false;
3852         }
3853
3854         if (CAN_PSR(i915) && intel_dp_is_edp(intel_dp)) {
3855                 drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
3856                 crtc_state->uapi.mode_changed = true;
3857                 return false;
3858         }
3859
3860         return true;
3861 }
3862
3863 static void intel_disable_dp(struct intel_atomic_state *state,
3864                              struct intel_encoder *encoder,
3865                              const struct intel_crtc_state *old_crtc_state,
3866                              const struct drm_connector_state *old_conn_state)
3867 {
3868         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3869
3870         intel_dp->link_trained = false;
3871
3872         if (old_crtc_state->has_audio)
3873                 intel_audio_codec_disable(encoder,
3874                                           old_crtc_state, old_conn_state);
3875
3876         /* Make sure the panel is off before trying to change the mode. But also
3877          * ensure that we have vdd while we switch off the panel. */
3878         intel_edp_panel_vdd_on(intel_dp);
3879         intel_edp_backlight_off(old_conn_state);
3880         intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
3881         intel_edp_panel_off(intel_dp);
3882         intel_dp->frl.is_trained = false;
3883         intel_dp->frl.trained_rate_gbps = 0;
3884 }
3885
3886 static void g4x_disable_dp(struct intel_atomic_state *state,
3887                            struct intel_encoder *encoder,
3888                            const struct intel_crtc_state *old_crtc_state,
3889                            const struct drm_connector_state *old_conn_state)
3890 {
3891         intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3892 }
3893
3894 static void vlv_disable_dp(struct intel_atomic_state *state,
3895                            struct intel_encoder *encoder,
3896                            const struct intel_crtc_state *old_crtc_state,
3897                            const struct drm_connector_state *old_conn_state)
3898 {
3899         intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3900 }
3901
3902 static void g4x_post_disable_dp(struct intel_atomic_state *state,
3903                                 struct intel_encoder *encoder,
3904                                 const struct intel_crtc_state *old_crtc_state,
3905                                 const struct drm_connector_state *old_conn_state)
3906 {
3907         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3908         enum port port = encoder->port;
3909
3910         /*
3911          * Bspec does not list a specific disable sequence for g4x DP.
3912          * Follow the ilk+ sequence (disable pipe before the port) for
3913          * g4x DP as it does not suffer from underruns like the normal
3914          * g4x modeset sequence (disable pipe after the port).
3915          */
3916         intel_dp_link_down(encoder, old_crtc_state);
3917
3918         /* Only ilk+ has port A */
3919         if (port == PORT_A)
3920                 ilk_edp_pll_off(intel_dp, old_crtc_state);
3921 }
3922
3923 static void vlv_post_disable_dp(struct intel_atomic_state *state,
3924                                 struct intel_encoder *encoder,
3925                                 const struct intel_crtc_state *old_crtc_state,
3926                                 const struct drm_connector_state *old_conn_state)
3927 {
3928         intel_dp_link_down(encoder, old_crtc_state);
3929 }
3930
3931 static void chv_post_disable_dp(struct intel_atomic_state *state,
3932                                 struct intel_encoder *encoder,
3933                                 const struct intel_crtc_state *old_crtc_state,
3934                                 const struct drm_connector_state *old_conn_state)
3935 {
3936         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3937
3938         intel_dp_link_down(encoder, old_crtc_state);
3939
3940         vlv_dpio_get(dev_priv);
3941
3942         /* Assert data lane reset */
3943         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3944
3945         vlv_dpio_put(dev_priv);
3946 }
3947
3948 static void
3949 cpt_set_link_train(struct intel_dp *intel_dp,
3950                    const struct intel_crtc_state *crtc_state,
3951                    u8 dp_train_pat)
3952 {
3953         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3954         u32 *DP = &intel_dp->DP;
3955
3956         *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3957
3958         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
3959         case DP_TRAINING_PATTERN_DISABLE:
3960                 *DP |= DP_LINK_TRAIN_OFF_CPT;
3961                 break;
3962         case DP_TRAINING_PATTERN_1:
3963                 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3964                 break;
3965         case DP_TRAINING_PATTERN_2:
3966                 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3967                 break;
3968         case DP_TRAINING_PATTERN_3:
3969                 drm_dbg_kms(&dev_priv->drm,
3970                             "TPS3 not supported, using TPS2 instead\n");
3971                 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3972                 break;
3973         }
3974
3975         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3976         intel_de_posting_read(dev_priv, intel_dp->output_reg);
3977 }
3978
3979 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
3980 {
3981         int bw_gbps[] = {9, 18, 24, 32, 40, 48};
3982         int i;
3983
3984         for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
3985                 if (frl_bw_mask & (1 << i))
3986                         return bw_gbps[i];
3987         }
3988         return 0;
3989 }
3990
3991 static int intel_dp_pcon_set_frl_mask(int max_frl)
3992 {
3993         switch (max_frl) {
3994         case 48:
3995                 return DP_PCON_FRL_BW_MASK_48GBPS;
3996         case 40:
3997                 return DP_PCON_FRL_BW_MASK_40GBPS;
3998         case 32:
3999                 return DP_PCON_FRL_BW_MASK_32GBPS;
4000         case 24:
4001                 return DP_PCON_FRL_BW_MASK_24GBPS;
4002         case 18:
4003                 return DP_PCON_FRL_BW_MASK_18GBPS;
4004         case 9:
4005                 return DP_PCON_FRL_BW_MASK_9GBPS;
4006         }
4007
4008         return 0;
4009 }
4010
4011 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
4012 {
4013         struct intel_connector *intel_connector = intel_dp->attached_connector;
4014         struct drm_connector *connector = &intel_connector->base;
4015
4016         return (connector->display_info.hdmi.max_frl_rate_per_lane *
4017                 connector->display_info.hdmi.max_lanes);
4018 }
4019
4020 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
4021 {
4022 #define PCON_EXTENDED_TRAIN_MODE (1 > 0)
4023 #define PCON_CONCURRENT_MODE (1 > 0)
4024 #define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE
4025 #define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE
4026 #define TIMEOUT_FRL_READY_MS 500
4027 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
4028
4029         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4030         int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
4031         u8 max_frl_bw_mask = 0, frl_trained_mask;
4032         bool is_active;
4033
4034         ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
4035         if (ret < 0)
4036                 return ret;
4037
4038         max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
4039         drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
4040
4041         max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
4042         drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
4043
4044         max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
4045
4046         if (max_frl_bw <= 0)
4047                 return -EINVAL;
4048
4049         ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
4050         if (ret < 0)
4051                 return ret;
4052         /* Wait for PCON to be FRL Ready */
4053         wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
4054
4055         if (!is_active)
4056                 return -ETIMEDOUT;
4057
4058         max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
4059         ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE);
4060         if (ret < 0)
4061                 return ret;
4062         ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE);
4063         if (ret < 0)
4064                 return ret;
4065         ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
4066         if (ret < 0)
4067                 return ret;
4068         /*
4069          * Wait for FRL to be completed
4070          * Check if the HDMI Link is up and active.
4071          */
4072         wait_for(is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux) == true, TIMEOUT_HDMI_LINK_ACTIVE_MS);
4073
4074         if (!is_active)
4075                 return -ETIMEDOUT;
4076
4077         /* Verify HDMI Link configuration shows FRL Mode */
4078         if (drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, &frl_trained_mask) !=
4079             DP_PCON_HDMI_MODE_FRL) {
4080                 drm_dbg(&i915->drm, "HDMI couldn't be trained in FRL Mode\n");
4081                 return -EINVAL;
4082         }
4083         drm_dbg(&i915->drm, "MAX_FRL_MASK = %u, FRL_TRAINED_MASK = %u\n", max_frl_bw_mask, frl_trained_mask);
4084
4085         intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
4086         intel_dp->frl.is_trained = true;
4087         drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
4088
4089         return 0;
4090 }
4091
4092 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
4093 {
4094         if (drm_dp_is_branch(intel_dp->dpcd) &&
4095             intel_dp->has_hdmi_sink &&
4096             intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
4097                 return true;
4098
4099         return false;
4100 }
4101
4102 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
4103 {
4104         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4105
4106         /* Always go for FRL training if supported */
4107         if (!intel_dp_is_hdmi_2_1_sink(intel_dp) ||
4108             intel_dp->frl.is_trained)
4109                 return;
4110
4111         if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
4112                 int ret, mode;
4113
4114                 drm_dbg(&dev_priv->drm, "Couldnt set FRL mode, continuing with TMDS mode\n");
4115                 ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
4116                 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
4117
4118                 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
4119                         drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
4120         } else {
4121                 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
4122         }
4123 }
4124
4125 static void
4126 g4x_set_link_train(struct intel_dp *intel_dp,
4127                    const struct intel_crtc_state *crtc_state,
4128                    u8 dp_train_pat)
4129 {
4130         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4131         u32 *DP = &intel_dp->DP;
4132
4133         *DP &= ~DP_LINK_TRAIN_MASK;
4134
4135         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
4136         case DP_TRAINING_PATTERN_DISABLE:
4137                 *DP |= DP_LINK_TRAIN_OFF;
4138                 break;
4139         case DP_TRAINING_PATTERN_1:
4140                 *DP |= DP_LINK_TRAIN_PAT_1;
4141                 break;
4142         case DP_TRAINING_PATTERN_2:
4143                 *DP |= DP_LINK_TRAIN_PAT_2;
4144                 break;
4145         case DP_TRAINING_PATTERN_3:
4146                 drm_dbg_kms(&dev_priv->drm,
4147                             "TPS3 not supported, using TPS2 instead\n");
4148                 *DP |= DP_LINK_TRAIN_PAT_2;
4149                 break;
4150         }
4151
4152         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4153         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4154 }
4155
4156 static void intel_dp_enable_port(struct intel_dp *intel_dp,
4157                                  const struct intel_crtc_state *crtc_state)
4158 {
4159         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4160
4161         /* enable with pattern 1 (as per spec) */
4162
4163         intel_dp_program_link_training_pattern(intel_dp, crtc_state,
4164                                                DP_TRAINING_PATTERN_1);
4165
4166         /*
4167          * Magic for VLV/CHV. We _must_ first set up the register
4168          * without actually enabling the port, and then do another
4169          * write to enable the port. Otherwise link training will
4170          * fail when the power sequencer is freshly used for this port.
4171          */
4172         intel_dp->DP |= DP_PORT_EN;
4173         if (crtc_state->has_audio)
4174                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
4175
4176         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4177         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4178 }
4179
4180 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp)
4181 {
4182         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4183         u8 tmp;
4184
4185         if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
4186                 return;
4187
4188         if (!drm_dp_is_branch(intel_dp->dpcd))
4189                 return;
4190
4191         tmp = intel_dp->has_hdmi_sink ?
4192                 DP_HDMI_DVI_OUTPUT_CONFIG : 0;
4193
4194         if (drm_dp_dpcd_writeb(&intel_dp->aux,
4195                                DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
4196                 drm_dbg_kms(&i915->drm, "Failed to set protocol converter HDMI mode to %s\n",
4197                             enableddisabled(intel_dp->has_hdmi_sink));
4198
4199         tmp = intel_dp->dfp.ycbcr_444_to_420 ?
4200                 DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
4201
4202         if (drm_dp_dpcd_writeb(&intel_dp->aux,
4203                                DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
4204                 drm_dbg_kms(&i915->drm,
4205                             "Failed to set protocol converter YCbCr 4:2:0 conversion mode to %s\n",
4206                             enableddisabled(intel_dp->dfp.ycbcr_444_to_420));
4207
4208         tmp = 0;
4209
4210         if (drm_dp_dpcd_writeb(&intel_dp->aux,
4211                                DP_PROTOCOL_CONVERTER_CONTROL_2, tmp) <= 0)
4212                 drm_dbg_kms(&i915->drm,
4213                             "Failed to set protocol converter YCbCr 4:2:2 conversion mode to %s\n",
4214                             enableddisabled(false));
4215 }
4216
4217 static void intel_enable_dp(struct intel_atomic_state *state,
4218                             struct intel_encoder *encoder,
4219                             const struct intel_crtc_state *pipe_config,
4220                             const struct drm_connector_state *conn_state)
4221 {
4222         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4223         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4224         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4225         u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);
4226         enum pipe pipe = crtc->pipe;
4227         intel_wakeref_t wakeref;
4228
4229         if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
4230                 return;
4231
4232         with_pps_lock(intel_dp, wakeref) {
4233                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4234                         vlv_init_panel_power_sequencer(encoder, pipe_config);
4235
4236                 intel_dp_enable_port(intel_dp, pipe_config);
4237
4238                 edp_panel_vdd_on(intel_dp);
4239                 edp_panel_on(intel_dp);
4240                 edp_panel_vdd_off(intel_dp, true);
4241         }
4242
4243         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4244                 unsigned int lane_mask = 0x0;
4245
4246                 if (IS_CHERRYVIEW(dev_priv))
4247                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
4248
4249                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
4250                                     lane_mask);
4251         }
4252
4253         intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
4254         intel_dp_configure_protocol_converter(intel_dp);
4255         intel_dp_check_frl_training(intel_dp);
4256         intel_dp_start_link_train(intel_dp, pipe_config);
4257         intel_dp_stop_link_train(intel_dp, pipe_config);
4258
4259         if (pipe_config->has_audio) {
4260                 drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",
4261                         pipe_name(pipe));
4262                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
4263         }
4264 }
4265
4266 static void g4x_enable_dp(struct intel_atomic_state *state,
4267                           struct intel_encoder *encoder,
4268                           const struct intel_crtc_state *pipe_config,
4269                           const struct drm_connector_state *conn_state)
4270 {
4271         intel_enable_dp(state, encoder, pipe_config, conn_state);
4272         intel_edp_backlight_on(pipe_config, conn_state);
4273 }
4274
4275 static void vlv_enable_dp(struct intel_atomic_state *state,
4276                           struct intel_encoder *encoder,
4277                           const struct intel_crtc_state *pipe_config,
4278                           const struct drm_connector_state *conn_state)
4279 {
4280         intel_edp_backlight_on(pipe_config, conn_state);
4281 }
4282
4283 static void g4x_pre_enable_dp(struct intel_atomic_state *state,
4284                               struct intel_encoder *encoder,
4285                               const struct intel_crtc_state *pipe_config,
4286                               const struct drm_connector_state *conn_state)
4287 {
4288         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4289         enum port port = encoder->port;
4290
4291         intel_dp_prepare(encoder, pipe_config);
4292
4293         /* Only ilk+ has port A */
4294         if (port == PORT_A)
4295                 ilk_edp_pll_on(intel_dp, pipe_config);
4296 }
4297
4298 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
4299 {
4300         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4301         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4302         enum pipe pipe = intel_dp->pps_pipe;
4303         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
4304
4305         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
4306
4307         if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
4308                 return;
4309
4310         edp_panel_vdd_off_sync(intel_dp);
4311
4312         /*
4313          * VLV seems to get confused when multiple power sequencers
4314          * have the same port selected (even if only one has power/vdd
4315          * enabled). The failure manifests as vlv_wait_port_ready() failing
4316          * CHV on the other hand doesn't seem to mind having the same port
4317          * selected in multiple power sequencers, but let's clear the
4318          * port select always when logically disconnecting a power sequencer
4319          * from a port.
4320          */
4321         drm_dbg_kms(&dev_priv->drm,
4322                     "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
4323                     pipe_name(pipe), dig_port->base.base.base.id,
4324                     dig_port->base.base.name);
4325         intel_de_write(dev_priv, pp_on_reg, 0);
4326         intel_de_posting_read(dev_priv, pp_on_reg);
4327
4328         intel_dp->pps_pipe = INVALID_PIPE;
4329 }
4330
4331 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
4332                                       enum pipe pipe)
4333 {
4334         struct intel_encoder *encoder;
4335
4336         lockdep_assert_held(&dev_priv->pps_mutex);
4337
4338         for_each_intel_dp(&dev_priv->drm, encoder) {
4339                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4340
4341                 drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe,
4342                          "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
4343                          pipe_name(pipe), encoder->base.base.id,
4344                          encoder->base.name);
4345
4346                 if (intel_dp->pps_pipe != pipe)
4347                         continue;
4348
4349                 drm_dbg_kms(&dev_priv->drm,
4350                             "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
4351                             pipe_name(pipe), encoder->base.base.id,
4352                             encoder->base.name);
4353
4354                 /* make sure vdd is off before we steal it */
4355                 vlv_detach_power_sequencer(intel_dp);
4356         }
4357 }
4358
4359 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
4360                                            const struct intel_crtc_state *crtc_state)
4361 {
4362         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4363         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4364         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4365
4366         lockdep_assert_held(&dev_priv->pps_mutex);
4367
4368         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
4369
4370         if (intel_dp->pps_pipe != INVALID_PIPE &&
4371             intel_dp->pps_pipe != crtc->pipe) {
4372                 /*
4373                  * If another power sequencer was being used on this
4374                  * port previously make sure to turn off vdd there while
4375                  * we still have control of it.
4376                  */
4377                 vlv_detach_power_sequencer(intel_dp);
4378         }
4379
4380         /*
4381          * We may be stealing the power
4382          * sequencer from another port.
4383          */
4384         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
4385
4386         intel_dp->active_pipe = crtc->pipe;
4387
4388         if (!intel_dp_is_edp(intel_dp))
4389                 return;
4390
4391         /* now it's all ours */
4392         intel_dp->pps_pipe = crtc->pipe;
4393
4394         drm_dbg_kms(&dev_priv->drm,
4395                     "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
4396                     pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
4397                     encoder->base.name);
4398
4399         /* init power sequencer on this pipe and port */
4400         intel_dp_init_panel_power_sequencer(intel_dp);
4401         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
4402 }
4403
4404 static void vlv_pre_enable_dp(struct intel_atomic_state *state,
4405                               struct intel_encoder *encoder,
4406                               const struct intel_crtc_state *pipe_config,
4407                               const struct drm_connector_state *conn_state)
4408 {
4409         vlv_phy_pre_encoder_enable(encoder, pipe_config);
4410
4411         intel_enable_dp(state, encoder, pipe_config, conn_state);
4412 }
4413
4414 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state,
4415                                   struct intel_encoder *encoder,
4416                                   const struct intel_crtc_state *pipe_config,
4417                                   const struct drm_connector_state *conn_state)
4418 {
4419         intel_dp_prepare(encoder, pipe_config);
4420
4421         vlv_phy_pre_pll_enable(encoder, pipe_config);
4422 }
4423
4424 static void chv_pre_enable_dp(struct intel_atomic_state *state,
4425                               struct intel_encoder *encoder,
4426                               const struct intel_crtc_state *pipe_config,
4427                               const struct drm_connector_state *conn_state)
4428 {
4429         chv_phy_pre_encoder_enable(encoder, pipe_config);
4430
4431         intel_enable_dp(state, encoder, pipe_config, conn_state);
4432
4433         /* Second common lane will stay alive on its own now */
4434         chv_phy_release_cl2_override(encoder);
4435 }
4436
4437 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state,
4438                                   struct intel_encoder *encoder,
4439                                   const struct intel_crtc_state *pipe_config,
4440                                   const struct drm_connector_state *conn_state)
4441 {
4442         intel_dp_prepare(encoder, pipe_config);
4443
4444         chv_phy_pre_pll_enable(encoder, pipe_config);
4445 }
4446
4447 static void chv_dp_post_pll_disable(struct intel_atomic_state *state,
4448                                     struct intel_encoder *encoder,
4449                                     const struct intel_crtc_state *old_crtc_state,
4450                                     const struct drm_connector_state *old_conn_state)
4451 {
4452         chv_phy_post_pll_disable(encoder, old_crtc_state);
4453 }
4454
4455 static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp,
4456                                  const struct intel_crtc_state *crtc_state)
4457 {
4458         return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
4459 }
4460
4461 static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp,
4462                                  const struct intel_crtc_state *crtc_state)
4463 {
4464         return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
4465 }
4466
4467 static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp)
4468 {
4469         return DP_TRAIN_PRE_EMPH_LEVEL_2;
4470 }
4471
4472 static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)
4473 {
4474         return DP_TRAIN_PRE_EMPH_LEVEL_3;
4475 }
4476
4477 static void vlv_set_signal_levels(struct intel_dp *intel_dp,
4478                                   const struct intel_crtc_state *crtc_state)
4479 {
4480         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4481         unsigned long demph_reg_value, preemph_reg_value,
4482                 uniqtranscale_reg_value;
4483         u8 train_set = intel_dp->train_set[0];
4484
4485         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4486         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4487                 preemph_reg_value = 0x0004000;
4488                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4489                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4490                         demph_reg_value = 0x2B405555;
4491                         uniqtranscale_reg_value = 0x552AB83A;
4492                         break;
4493                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4494                         demph_reg_value = 0x2B404040;
4495                         uniqtranscale_reg_value = 0x5548B83A;
4496                         break;
4497                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4498                         demph_reg_value = 0x2B245555;
4499                         uniqtranscale_reg_value = 0x5560B83A;
4500                         break;
4501                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4502                         demph_reg_value = 0x2B405555;
4503                         uniqtranscale_reg_value = 0x5598DA3A;
4504                         break;
4505                 default:
4506                         return;
4507                 }
4508                 break;
4509         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4510                 preemph_reg_value = 0x0002000;
4511                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4512                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4513                         demph_reg_value = 0x2B404040;
4514                         uniqtranscale_reg_value = 0x5552B83A;
4515                         break;
4516                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4517                         demph_reg_value = 0x2B404848;
4518                         uniqtranscale_reg_value = 0x5580B83A;
4519                         break;
4520                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4521                         demph_reg_value = 0x2B404040;
4522                         uniqtranscale_reg_value = 0x55ADDA3A;
4523                         break;
4524                 default:
4525                         return;
4526                 }
4527                 break;
4528         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4529                 preemph_reg_value = 0x0000000;
4530                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4531                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4532                         demph_reg_value = 0x2B305555;
4533                         uniqtranscale_reg_value = 0x5570B83A;
4534                         break;
4535                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4536                         demph_reg_value = 0x2B2B4040;
4537                         uniqtranscale_reg_value = 0x55ADDA3A;
4538                         break;
4539                 default:
4540                         return;
4541                 }
4542                 break;
4543         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4544                 preemph_reg_value = 0x0006000;
4545                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4546                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4547                         demph_reg_value = 0x1B405555;
4548                         uniqtranscale_reg_value = 0x55ADDA3A;
4549                         break;
4550                 default:
4551                         return;
4552                 }
4553                 break;
4554         default:
4555                 return;
4556         }
4557
4558         vlv_set_phy_signal_level(encoder, crtc_state,
4559                                  demph_reg_value, preemph_reg_value,
4560                                  uniqtranscale_reg_value, 0);
4561 }
4562
4563 static void chv_set_signal_levels(struct intel_dp *intel_dp,
4564                                   const struct intel_crtc_state *crtc_state)
4565 {
4566         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4567         u32 deemph_reg_value, margin_reg_value;
4568         bool uniq_trans_scale = false;
4569         u8 train_set = intel_dp->train_set[0];
4570
4571         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4572         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4573                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4574                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4575                         deemph_reg_value = 128;
4576                         margin_reg_value = 52;
4577                         break;
4578                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4579                         deemph_reg_value = 128;
4580                         margin_reg_value = 77;
4581                         break;
4582                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4583                         deemph_reg_value = 128;
4584                         margin_reg_value = 102;
4585                         break;
4586                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4587                         deemph_reg_value = 128;
4588                         margin_reg_value = 154;
4589                         uniq_trans_scale = true;
4590                         break;
4591                 default:
4592                         return;
4593                 }
4594                 break;
4595         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4596                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4597                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4598                         deemph_reg_value = 85;
4599                         margin_reg_value = 78;
4600                         break;
4601                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4602                         deemph_reg_value = 85;
4603                         margin_reg_value = 116;
4604                         break;
4605                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4606                         deemph_reg_value = 85;
4607                         margin_reg_value = 154;
4608                         break;
4609                 default:
4610                         return;
4611                 }
4612                 break;
4613         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4614                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4615                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4616                         deemph_reg_value = 64;
4617                         margin_reg_value = 104;
4618                         break;
4619                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4620                         deemph_reg_value = 64;
4621                         margin_reg_value = 154;
4622                         break;
4623                 default:
4624                         return;
4625                 }
4626                 break;
4627         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4628                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4629                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4630                         deemph_reg_value = 43;
4631                         margin_reg_value = 154;
4632                         break;
4633                 default:
4634                         return;
4635                 }
4636                 break;
4637         default:
4638                 return;
4639         }
4640
4641         chv_set_phy_signal_level(encoder, crtc_state,
4642                                  deemph_reg_value, margin_reg_value,
4643                                  uniq_trans_scale);
4644 }
4645
4646 static u32 g4x_signal_levels(u8 train_set)
4647 {
4648         u32 signal_levels = 0;
4649
4650         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4651         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4652         default:
4653                 signal_levels |= DP_VOLTAGE_0_4;
4654                 break;
4655         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4656                 signal_levels |= DP_VOLTAGE_0_6;
4657                 break;
4658         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4659                 signal_levels |= DP_VOLTAGE_0_8;
4660                 break;
4661         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4662                 signal_levels |= DP_VOLTAGE_1_2;
4663                 break;
4664         }
4665         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4666         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4667         default:
4668                 signal_levels |= DP_PRE_EMPHASIS_0;
4669                 break;
4670         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4671                 signal_levels |= DP_PRE_EMPHASIS_3_5;
4672                 break;
4673         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4674                 signal_levels |= DP_PRE_EMPHASIS_6;
4675                 break;
4676         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4677                 signal_levels |= DP_PRE_EMPHASIS_9_5;
4678                 break;
4679         }
4680         return signal_levels;
4681 }
4682
4683 static void
4684 g4x_set_signal_levels(struct intel_dp *intel_dp,
4685                       const struct intel_crtc_state *crtc_state)
4686 {
4687         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4688         u8 train_set = intel_dp->train_set[0];
4689         u32 signal_levels;
4690
4691         signal_levels = g4x_signal_levels(train_set);
4692
4693         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4694                     signal_levels);
4695
4696         intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);
4697         intel_dp->DP |= signal_levels;
4698
4699         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4700         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4701 }
4702
4703 /* SNB CPU eDP voltage swing and pre-emphasis control */
4704 static u32 snb_cpu_edp_signal_levels(u8 train_set)
4705 {
4706         u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4707                                         DP_TRAIN_PRE_EMPHASIS_MASK);
4708
4709         switch (signal_levels) {
4710         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4711         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4712                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4713         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4714                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
4715         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4716         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4717                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
4718         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4719         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4720                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
4721         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4722         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4723                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
4724         default:
4725                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4726                               "0x%x\n", signal_levels);
4727                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4728         }
4729 }
4730
4731 static void
4732 snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
4733                               const struct intel_crtc_state *crtc_state)
4734 {
4735         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4736         u8 train_set = intel_dp->train_set[0];
4737         u32 signal_levels;
4738
4739         signal_levels = snb_cpu_edp_signal_levels(train_set);
4740
4741         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4742                     signal_levels);
4743
4744         intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
4745         intel_dp->DP |= signal_levels;
4746
4747         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4748         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4749 }
4750
4751 /* IVB CPU eDP voltage swing and pre-emphasis control */
4752 static u32 ivb_cpu_edp_signal_levels(u8 train_set)
4753 {
4754         u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4755                                         DP_TRAIN_PRE_EMPHASIS_MASK);
4756
4757         switch (signal_levels) {
4758         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4759                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
4760         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4761                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
4762         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4763         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4764                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
4765
4766         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4767                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
4768         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4769                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
4770
4771         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4772                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
4773         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4774                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
4775
4776         default:
4777                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4778                               "0x%x\n", signal_levels);
4779                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
4780         }
4781 }
4782
4783 static void
4784 ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
4785                               const struct intel_crtc_state *crtc_state)
4786 {
4787         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4788         u8 train_set = intel_dp->train_set[0];
4789         u32 signal_levels;
4790
4791         signal_levels = ivb_cpu_edp_signal_levels(train_set);
4792
4793         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4794                     signal_levels);
4795
4796         intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
4797         intel_dp->DP |= signal_levels;
4798
4799         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4800         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4801 }
4802
4803 void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
4804                                 const struct intel_crtc_state *crtc_state)
4805 {
4806         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4807         u8 train_set = intel_dp->train_set[0];
4808
4809         drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
4810                     train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
4811                     train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
4812         drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
4813                     (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
4814                     DP_TRAIN_PRE_EMPHASIS_SHIFT,
4815                     train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
4816                     " (max)" : "");
4817
4818         intel_dp->set_signal_levels(intel_dp, crtc_state);
4819 }
4820
4821 void
4822 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
4823                                        const struct intel_crtc_state *crtc_state,
4824                                        u8 dp_train_pat)
4825 {
4826         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4827
4828         if ((intel_dp_training_pattern_symbol(dp_train_pat)) !=
4829             DP_TRAINING_PATTERN_DISABLE)
4830                 drm_dbg_kms(&dev_priv->drm,
4831                             "Using DP training pattern TPS%d\n",
4832                             intel_dp_training_pattern_symbol(dp_train_pat));
4833
4834         intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
4835 }
4836
4837 static void
4838 intel_dp_link_down(struct intel_encoder *encoder,
4839                    const struct intel_crtc_state *old_crtc_state)
4840 {
4841         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4842         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4843         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4844         enum port port = encoder->port;
4845         u32 DP = intel_dp->DP;
4846
4847         if (drm_WARN_ON(&dev_priv->drm,
4848                         (intel_de_read(dev_priv, intel_dp->output_reg) &
4849                          DP_PORT_EN) == 0))
4850                 return;
4851
4852         drm_dbg_kms(&dev_priv->drm, "\n");
4853
4854         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
4855             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
4856                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
4857                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
4858         } else {
4859                 DP &= ~DP_LINK_TRAIN_MASK;
4860                 DP |= DP_LINK_TRAIN_PAT_IDLE;
4861         }
4862         intel_de_write(dev_priv, intel_dp->output_reg, DP);
4863         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4864
4865         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
4866         intel_de_write(dev_priv, intel_dp->output_reg, DP);
4867         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4868
4869         /*
4870          * HW workaround for IBX, we need to move the port
4871          * to transcoder A after disabling it to allow the
4872          * matching HDMI port to be enabled on transcoder A.
4873          */
4874         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
4875                 /*
4876                  * We get CPU/PCH FIFO underruns on the other pipe when
4877                  * doing the workaround. Sweep them under the rug.
4878                  */
4879                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4880                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4881
4882                 /* always enable with pattern 1 (as per spec) */
4883                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
4884                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
4885                         DP_LINK_TRAIN_PAT_1;
4886                 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4887                 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4888
4889                 DP &= ~DP_PORT_EN;
4890                 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4891                 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4892
4893                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
4894                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4895                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4896         }
4897
4898         msleep(intel_dp->panel_power_down_delay);
4899
4900         intel_dp->DP = DP;
4901
4902         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4903                 intel_wakeref_t wakeref;
4904
4905                 with_pps_lock(intel_dp, wakeref)
4906                         intel_dp->active_pipe = INVALID_PIPE;
4907         }
4908 }
4909
4910 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4911 {
4912         u8 dprx = 0;
4913
4914         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4915                               &dprx) != 1)
4916                 return false;
4917         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4918 }
4919
4920 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4921 {
4922         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4923
4924         /*
4925          * Clear the cached register set to avoid using stale values
4926          * for the sinks that do not support DSC.
4927          */
4928         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4929
4930         /* Clear fec_capable to avoid using stale values */
4931         intel_dp->fec_capable = 0;
4932
4933         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4934         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4935             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4936                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4937                                      intel_dp->dsc_dpcd,
4938                                      sizeof(intel_dp->dsc_dpcd)) < 0)
4939                         drm_err(&i915->drm,
4940                                 "Failed to read DPCD register 0x%x\n",
4941                                 DP_DSC_SUPPORT);
4942
4943                 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
4944                             (int)sizeof(intel_dp->dsc_dpcd),
4945                             intel_dp->dsc_dpcd);
4946
4947                 /* FEC is supported only on DP 1.4 */
4948                 if (!intel_dp_is_edp(intel_dp) &&
4949                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4950                                       &intel_dp->fec_capable) < 0)
4951                         drm_err(&i915->drm,
4952                                 "Failed to read FEC DPCD register\n");
4953
4954                 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
4955                             intel_dp->fec_capable);
4956         }
4957 }
4958
4959 static bool
4960 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4961 {
4962         struct drm_i915_private *dev_priv =
4963                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4964
4965         /* this function is meant to be called only once */
4966         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
4967
4968         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
4969                 return false;
4970
4971         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4972                          drm_dp_is_branch(intel_dp->dpcd));
4973
4974         /*
4975          * Read the eDP display control registers.
4976          *
4977          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4978          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4979          * set, but require eDP 1.4+ detection (e.g. for supported link rates
4980          * method). The display control registers should read zero if they're
4981          * not supported anyway.
4982          */
4983         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4984                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4985                              sizeof(intel_dp->edp_dpcd))
4986                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
4987                             (int)sizeof(intel_dp->edp_dpcd),
4988                             intel_dp->edp_dpcd);
4989
4990         /*
4991          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4992          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4993          */
4994         intel_psr_init_dpcd(intel_dp);
4995
4996         /* Read the eDP 1.4+ supported link rates. */
4997         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4998                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4999                 int i;
5000
5001                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
5002                                 sink_rates, sizeof(sink_rates));
5003
5004                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
5005                         int val = le16_to_cpu(sink_rates[i]);
5006
5007                         if (val == 0)
5008                                 break;
5009
5010                         /* Value read multiplied by 200kHz gives the per-lane
5011                          * link rate in kHz. The source rates are, however,
5012                          * stored in terms of LS_Clk kHz. The full conversion
5013                          * back to symbols is
5014                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
5015                          */
5016                         intel_dp->sink_rates[i] = (val * 200) / 10;
5017                 }
5018                 intel_dp->num_sink_rates = i;
5019         }
5020
5021         /*
5022          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
5023          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
5024          */
5025         if (intel_dp->num_sink_rates)
5026                 intel_dp->use_rate_select = true;
5027         else
5028                 intel_dp_set_sink_rates(intel_dp);
5029
5030         intel_dp_set_common_rates(intel_dp);
5031
5032         /* Read the eDP DSC DPCD registers */
5033         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
5034                 intel_dp_get_dsc_sink_cap(intel_dp);
5035
5036         return true;
5037 }
5038
5039 static bool
5040 intel_dp_has_sink_count(struct intel_dp *intel_dp)
5041 {
5042         if (!intel_dp->attached_connector)
5043                 return false;
5044
5045         return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
5046                                           intel_dp->dpcd,
5047                                           &intel_dp->desc);
5048 }
5049
5050 static bool
5051 intel_dp_get_dpcd(struct intel_dp *intel_dp)
5052 {
5053         int ret;
5054
5055         intel_dp_lttpr_init(intel_dp);
5056
5057         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd))
5058                 return false;
5059
5060         /*
5061          * Don't clobber cached eDP rates. Also skip re-reading
5062          * the OUI/ID since we know it won't change.
5063          */
5064         if (!intel_dp_is_edp(intel_dp)) {
5065                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
5066                                  drm_dp_is_branch(intel_dp->dpcd));
5067
5068                 intel_dp_set_sink_rates(intel_dp);
5069                 intel_dp_set_common_rates(intel_dp);
5070         }
5071
5072         if (intel_dp_has_sink_count(intel_dp)) {
5073                 ret = drm_dp_read_sink_count(&intel_dp->aux);
5074                 if (ret < 0)
5075                         return false;
5076
5077                 /*
5078                  * Sink count can change between short pulse hpd hence
5079                  * a member variable in intel_dp will track any changes
5080                  * between short pulse interrupts.
5081                  */
5082                 intel_dp->sink_count = ret;
5083
5084                 /*
5085                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
5086                  * a dongle is present but no display. Unless we require to know
5087                  * if a dongle is present or not, we don't need to update
5088                  * downstream port information. So, an early return here saves
5089                  * time from performing other operations which are not required.
5090                  */
5091                 if (!intel_dp->sink_count)
5092                         return false;
5093         }
5094
5095         return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
5096                                            intel_dp->downstream_ports) == 0;
5097 }
5098
5099 static bool
5100 intel_dp_can_mst(struct intel_dp *intel_dp)
5101 {
5102         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5103
5104         return i915->params.enable_dp_mst &&
5105                 intel_dp->can_mst &&
5106                 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
5107 }
5108
5109 static void
5110 intel_dp_configure_mst(struct intel_dp *intel_dp)
5111 {
5112         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5113         struct intel_encoder *encoder =
5114                 &dp_to_dig_port(intel_dp)->base;
5115         bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
5116
5117         drm_dbg_kms(&i915->drm,
5118                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
5119                     encoder->base.base.id, encoder->base.name,
5120                     yesno(intel_dp->can_mst), yesno(sink_can_mst),
5121                     yesno(i915->params.enable_dp_mst));
5122
5123         if (!intel_dp->can_mst)
5124                 return;
5125
5126         intel_dp->is_mst = sink_can_mst &&
5127                 i915->params.enable_dp_mst;
5128
5129         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5130                                         intel_dp->is_mst);
5131 }
5132
5133 static bool
5134 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
5135 {
5136         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
5137                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
5138                 DP_DPRX_ESI_LEN;
5139 }
5140
5141 bool
5142 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
5143                        const struct drm_connector_state *conn_state)
5144 {
5145         /*
5146          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
5147          * of Color Encoding Format and Content Color Gamut], in order to
5148          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
5149          */
5150         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5151                 return true;
5152
5153         switch (conn_state->colorspace) {
5154         case DRM_MODE_COLORIMETRY_SYCC_601:
5155         case DRM_MODE_COLORIMETRY_OPYCC_601:
5156         case DRM_MODE_COLORIMETRY_BT2020_YCC:
5157         case DRM_MODE_COLORIMETRY_BT2020_RGB:
5158         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
5159                 return true;
5160         default:
5161                 break;
5162         }
5163
5164         return false;
5165 }
5166
5167 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
5168                                      struct dp_sdp *sdp, size_t size)
5169 {
5170         size_t length = sizeof(struct dp_sdp);
5171
5172         if (size < length)
5173                 return -ENOSPC;
5174
5175         memset(sdp, 0, size);
5176
5177         /*
5178          * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
5179          * VSC SDP Header Bytes
5180          */
5181         sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
5182         sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
5183         sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
5184         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
5185
5186         /*
5187          * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
5188          * per DP 1.4a spec.
5189          */
5190         if (vsc->revision != 0x5)
5191                 goto out;
5192
5193         /* VSC SDP Payload for DB16 through DB18 */
5194         /* Pixel Encoding and Colorimetry Formats  */
5195         sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
5196         sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
5197
5198         switch (vsc->bpc) {
5199         case 6:
5200                 /* 6bpc: 0x0 */
5201                 break;
5202         case 8:
5203                 sdp->db[17] = 0x1; /* DB17[3:0] */
5204                 break;
5205         case 10:
5206                 sdp->db[17] = 0x2;
5207                 break;
5208         case 12:
5209                 sdp->db[17] = 0x3;
5210                 break;
5211         case 16:
5212                 sdp->db[17] = 0x4;
5213                 break;
5214         default:
5215                 MISSING_CASE(vsc->bpc);
5216                 break;
5217         }
5218         /* Dynamic Range and Component Bit Depth */
5219         if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
5220                 sdp->db[17] |= 0x80;  /* DB17[7] */
5221
5222         /* Content Type */
5223         sdp->db[18] = vsc->content_type & 0x7;
5224
5225 out:
5226         return length;
5227 }
5228
5229 static ssize_t
5230 intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
5231                                          struct dp_sdp *sdp,
5232                                          size_t size)
5233 {
5234         size_t length = sizeof(struct dp_sdp);
5235         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
5236         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
5237         ssize_t len;
5238
5239         if (size < length)
5240                 return -ENOSPC;
5241
5242         memset(sdp, 0, size);
5243
5244         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
5245         if (len < 0) {
5246                 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
5247                 return -ENOSPC;
5248         }
5249
5250         if (len != infoframe_size) {
5251                 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
5252                 return -ENOSPC;
5253         }
5254
5255         /*
5256          * Set up the infoframe sdp packet for HDR static metadata.
5257          * Prepare VSC Header for SU as per DP 1.4a spec,
5258          * Table 2-100 and Table 2-101
5259          */
5260
5261         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
5262         sdp->sdp_header.HB0 = 0;
5263         /*
5264          * Packet Type 80h + Non-audio INFOFRAME Type value
5265          * HDMI_INFOFRAME_TYPE_DRM: 0x87
5266          * - 80h + Non-audio INFOFRAME Type value
5267          * - InfoFrame Type: 0x07
5268          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
5269          */
5270         sdp->sdp_header.HB1 = drm_infoframe->type;
5271         /*
5272          * Least Significant Eight Bits of (Data Byte Count – 1)
5273          * infoframe_size - 1
5274          */
5275         sdp->sdp_header.HB2 = 0x1D;
5276         /* INFOFRAME SDP Version Number */
5277         sdp->sdp_header.HB3 = (0x13 << 2);
5278         /* CTA Header Byte 2 (INFOFRAME Version Number) */
5279         sdp->db[0] = drm_infoframe->version;
5280         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
5281         sdp->db[1] = drm_infoframe->length;
5282         /*
5283          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
5284          * HDMI_INFOFRAME_HEADER_SIZE
5285          */
5286         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
5287         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
5288                HDMI_DRM_INFOFRAME_SIZE);
5289
5290         /*
5291          * Size of DP infoframe sdp packet for HDR static metadata consists of
5292          * - DP SDP Header(struct dp_sdp_header): 4 bytes
5293          * - Two Data Blocks: 2 bytes
5294          *    CTA Header Byte2 (INFOFRAME Version Number)
5295          *    CTA Header Byte3 (Length of INFOFRAME)
5296          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
5297          *
5298          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
5299          * infoframe size. But GEN11+ has larger than that size, write_infoframe
5300          * will pad rest of the size.
5301          */
5302         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
5303 }
5304
5305 static void intel_write_dp_sdp(struct intel_encoder *encoder,
5306                                const struct intel_crtc_state *crtc_state,
5307                                unsigned int type)
5308 {
5309         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5310         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5311         struct dp_sdp sdp = {};
5312         ssize_t len;
5313
5314         if ((crtc_state->infoframes.enable &
5315              intel_hdmi_infoframe_enable(type)) == 0)
5316                 return;
5317
5318         switch (type) {
5319         case DP_SDP_VSC:
5320                 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
5321                                             sizeof(sdp));
5322                 break;
5323         case HDMI_PACKET_TYPE_GAMUT_METADATA:
5324                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
5325                                                                &sdp, sizeof(sdp));
5326                 break;
5327         default:
5328                 MISSING_CASE(type);
5329                 return;
5330         }
5331
5332         if (drm_WARN_ON(&dev_priv->drm, len < 0))
5333                 return;
5334
5335         dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
5336 }
5337
5338 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
5339                             const struct intel_crtc_state *crtc_state,
5340                             struct drm_dp_vsc_sdp *vsc)
5341 {
5342         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5343         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5344         struct dp_sdp sdp = {};
5345         ssize_t len;
5346
5347         len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
5348
5349         if (drm_WARN_ON(&dev_priv->drm, len < 0))
5350                 return;
5351
5352         dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
5353                                         &sdp, len);
5354 }
5355
5356 void intel_dp_set_infoframes(struct intel_encoder *encoder,
5357                              bool enable,
5358                              const struct intel_crtc_state *crtc_state,
5359                              const struct drm_connector_state *conn_state)
5360 {
5361         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5362         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5363         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
5364         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
5365                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
5366                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
5367         u32 val = intel_de_read(dev_priv, reg);
5368
5369         /* TODO: Add DSC case (DIP_ENABLE_PPS) */
5370         /* When PSR is enabled, this routine doesn't disable VSC DIP */
5371         if (intel_psr_enabled(intel_dp))
5372                 val &= ~dip_enable;
5373         else
5374                 val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
5375
5376         if (!enable) {
5377                 intel_de_write(dev_priv, reg, val);
5378                 intel_de_posting_read(dev_priv, reg);
5379                 return;
5380         }
5381
5382         intel_de_write(dev_priv, reg, val);
5383         intel_de_posting_read(dev_priv, reg);
5384
5385         /* When PSR is enabled, VSC SDP is handled by PSR routine */
5386         if (!intel_psr_enabled(intel_dp))
5387                 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
5388
5389         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
5390 }
5391
5392 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
5393                                    const void *buffer, size_t size)
5394 {
5395         const struct dp_sdp *sdp = buffer;
5396
5397         if (size < sizeof(struct dp_sdp))
5398                 return -EINVAL;
5399
5400         memset(vsc, 0, size);
5401
5402         if (sdp->sdp_header.HB0 != 0)
5403                 return -EINVAL;
5404
5405         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
5406                 return -EINVAL;
5407
5408         vsc->sdp_type = sdp->sdp_header.HB1;
5409         vsc->revision = sdp->sdp_header.HB2;
5410         vsc->length = sdp->sdp_header.HB3;
5411
5412         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
5413             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
5414                 /*
5415                  * - HB2 = 0x2, HB3 = 0x8
5416                  *   VSC SDP supporting 3D stereo + PSR
5417                  * - HB2 = 0x4, HB3 = 0xe
5418                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
5419                  *   first scan line of the SU region (applies to eDP v1.4b
5420                  *   and higher).
5421                  */
5422                 return 0;
5423         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
5424                 /*
5425                  * - HB2 = 0x5, HB3 = 0x13
5426                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
5427                  *   Format.
5428                  */
5429                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
5430                 vsc->colorimetry = sdp->db[16] & 0xf;
5431                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
5432
5433                 switch (sdp->db[17] & 0x7) {
5434                 case 0x0:
5435                         vsc->bpc = 6;
5436                         break;
5437                 case 0x1:
5438                         vsc->bpc = 8;
5439                         break;
5440                 case 0x2:
5441                         vsc->bpc = 10;
5442                         break;
5443                 case 0x3:
5444                         vsc->bpc = 12;
5445                         break;
5446                 case 0x4:
5447                         vsc->bpc = 16;
5448                         break;
5449                 default:
5450                         MISSING_CASE(sdp->db[17] & 0x7);
5451                         return -EINVAL;
5452                 }
5453
5454                 vsc->content_type = sdp->db[18] & 0x7;
5455         } else {
5456                 return -EINVAL;
5457         }
5458
5459         return 0;
5460 }
5461
5462 static int
5463 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
5464                                            const void *buffer, size_t size)
5465 {
5466         int ret;
5467
5468         const struct dp_sdp *sdp = buffer;
5469
5470         if (size < sizeof(struct dp_sdp))
5471                 return -EINVAL;
5472
5473         if (sdp->sdp_header.HB0 != 0)
5474                 return -EINVAL;
5475
5476         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
5477                 return -EINVAL;
5478
5479         /*
5480          * Least Significant Eight Bits of (Data Byte Count – 1)
5481          * 1Dh (i.e., Data Byte Count = 30 bytes).
5482          */
5483         if (sdp->sdp_header.HB2 != 0x1D)
5484                 return -EINVAL;
5485
5486         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
5487         if ((sdp->sdp_header.HB3 & 0x3) != 0)
5488                 return -EINVAL;
5489
5490         /* INFOFRAME SDP Version Number */
5491         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
5492                 return -EINVAL;
5493
5494         /* CTA Header Byte 2 (INFOFRAME Version Number) */
5495         if (sdp->db[0] != 1)
5496                 return -EINVAL;
5497
5498         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
5499         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
5500                 return -EINVAL;
5501
5502         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
5503                                              HDMI_DRM_INFOFRAME_SIZE);
5504
5505         return ret;
5506 }
5507
5508 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
5509                                   struct intel_crtc_state *crtc_state,
5510                                   struct drm_dp_vsc_sdp *vsc)
5511 {
5512         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5513         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5514         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5515         unsigned int type = DP_SDP_VSC;
5516         struct dp_sdp sdp = {};
5517         int ret;
5518
5519         /* When PSR is enabled, VSC SDP is handled by PSR routine */
5520         if (intel_psr_enabled(intel_dp))
5521                 return;
5522
5523         if ((crtc_state->infoframes.enable &
5524              intel_hdmi_infoframe_enable(type)) == 0)
5525                 return;
5526
5527         dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
5528
5529         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
5530
5531         if (ret)
5532                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
5533 }
5534
5535 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
5536                                                      struct intel_crtc_state *crtc_state,
5537                                                      struct hdmi_drm_infoframe *drm_infoframe)
5538 {
5539         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5540         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5541         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
5542         struct dp_sdp sdp = {};
5543         int ret;
5544
5545         if ((crtc_state->infoframes.enable &
5546             intel_hdmi_infoframe_enable(type)) == 0)
5547                 return;
5548
5549         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
5550                                  sizeof(sdp));
5551
5552         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
5553                                                          sizeof(sdp));
5554
5555         if (ret)
5556                 drm_dbg_kms(&dev_priv->drm,
5557                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
5558 }
5559
5560 void intel_read_dp_sdp(struct intel_encoder *encoder,
5561                        struct intel_crtc_state *crtc_state,
5562                        unsigned int type)
5563 {
5564         if (encoder->type != INTEL_OUTPUT_DDI)
5565                 return;
5566
5567         switch (type) {
5568         case DP_SDP_VSC:
5569                 intel_read_dp_vsc_sdp(encoder, crtc_state,
5570                                       &crtc_state->infoframes.vsc);
5571                 break;
5572         case HDMI_PACKET_TYPE_GAMUT_METADATA:
5573                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
5574                                                          &crtc_state->infoframes.drm.drm);
5575                 break;
5576         default:
5577                 MISSING_CASE(type);
5578                 break;
5579         }
5580 }
5581
5582 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
5583 {
5584         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5585         int status = 0;
5586         int test_link_rate;
5587         u8 test_lane_count, test_link_bw;
5588         /* (DP CTS 1.2)
5589          * 4.3.1.11
5590          */
5591         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
5592         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
5593                                    &test_lane_count);
5594
5595         if (status <= 0) {
5596                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
5597                 return DP_TEST_NAK;
5598         }
5599         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
5600
5601         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
5602                                    &test_link_bw);
5603         if (status <= 0) {
5604                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
5605                 return DP_TEST_NAK;
5606         }
5607         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
5608
5609         /* Validate the requested link rate and lane count */
5610         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
5611                                         test_lane_count))
5612                 return DP_TEST_NAK;
5613
5614         intel_dp->compliance.test_lane_count = test_lane_count;
5615         intel_dp->compliance.test_link_rate = test_link_rate;
5616
5617         return DP_TEST_ACK;
5618 }
5619
5620 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
5621 {
5622         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5623         u8 test_pattern;
5624         u8 test_misc;
5625         __be16 h_width, v_height;
5626         int status = 0;
5627
5628         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
5629         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
5630                                    &test_pattern);
5631         if (status <= 0) {
5632                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
5633                 return DP_TEST_NAK;
5634         }
5635         if (test_pattern != DP_COLOR_RAMP)
5636                 return DP_TEST_NAK;
5637
5638         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
5639                                   &h_width, 2);
5640         if (status <= 0) {
5641                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
5642                 return DP_TEST_NAK;
5643         }
5644
5645         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
5646                                   &v_height, 2);
5647         if (status <= 0) {
5648                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
5649                 return DP_TEST_NAK;
5650         }
5651
5652         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
5653                                    &test_misc);
5654         if (status <= 0) {
5655                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
5656                 return DP_TEST_NAK;
5657         }
5658         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
5659                 return DP_TEST_NAK;
5660         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
5661                 return DP_TEST_NAK;
5662         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
5663         case DP_TEST_BIT_DEPTH_6:
5664                 intel_dp->compliance.test_data.bpc = 6;
5665                 break;
5666         case DP_TEST_BIT_DEPTH_8:
5667                 intel_dp->compliance.test_data.bpc = 8;
5668                 break;
5669         default:
5670                 return DP_TEST_NAK;
5671         }
5672
5673         intel_dp->compliance.test_data.video_pattern = test_pattern;
5674         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
5675         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
5676         /* Set test active flag here so userspace doesn't interrupt things */
5677         intel_dp->compliance.test_active = true;
5678
5679         return DP_TEST_ACK;
5680 }
5681
5682 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
5683 {
5684         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5685         u8 test_result = DP_TEST_ACK;
5686         struct intel_connector *intel_connector = intel_dp->attached_connector;
5687         struct drm_connector *connector = &intel_connector->base;
5688
5689         if (intel_connector->detect_edid == NULL ||
5690             connector->edid_corrupt ||
5691             intel_dp->aux.i2c_defer_count > 6) {
5692                 /* Check EDID read for NACKs, DEFERs and corruption
5693                  * (DP CTS 1.2 Core r1.1)
5694                  *    4.2.2.4 : Failed EDID read, I2C_NAK
5695                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
5696                  *    4.2.2.6 : EDID corruption detected
5697                  * Use failsafe mode for all cases
5698                  */
5699                 if (intel_dp->aux.i2c_nack_count > 0 ||
5700                         intel_dp->aux.i2c_defer_count > 0)
5701                         drm_dbg_kms(&i915->drm,
5702                                     "EDID read had %d NACKs, %d DEFERs\n",
5703                                     intel_dp->aux.i2c_nack_count,
5704                                     intel_dp->aux.i2c_defer_count);
5705                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
5706         } else {
5707                 struct edid *block = intel_connector->detect_edid;
5708
5709                 /* We have to write the checksum
5710                  * of the last block read
5711                  */
5712                 block += intel_connector->detect_edid->extensions;
5713
5714                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
5715                                        block->checksum) <= 0)
5716                         drm_dbg_kms(&i915->drm,
5717                                     "Failed to write EDID checksum\n");
5718
5719                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
5720                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
5721         }
5722
5723         /* Set test active flag here so userspace doesn't interrupt things */
5724         intel_dp->compliance.test_active = true;
5725
5726         return test_result;
5727 }
5728
5729 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
5730                                         const struct intel_crtc_state *crtc_state)
5731 {
5732         struct drm_i915_private *dev_priv =
5733                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
5734         struct drm_dp_phy_test_params *data =
5735                         &intel_dp->compliance.test_data.phytest;
5736         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5737         enum pipe pipe = crtc->pipe;
5738         u32 pattern_val;
5739
5740         switch (data->phy_pattern) {
5741         case DP_PHY_TEST_PATTERN_NONE:
5742                 DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
5743                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
5744                 break;
5745         case DP_PHY_TEST_PATTERN_D10_2:
5746                 DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
5747                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5748                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
5749                 break;
5750         case DP_PHY_TEST_PATTERN_ERROR_COUNT:
5751                 DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
5752                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5753                                DDI_DP_COMP_CTL_ENABLE |
5754                                DDI_DP_COMP_CTL_SCRAMBLED_0);
5755                 break;
5756         case DP_PHY_TEST_PATTERN_PRBS7:
5757                 DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
5758                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5759                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
5760                 break;
5761         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
5762                 /*
5763                  * FIXME: Ideally pattern should come from DPCD 0x250. As
5764                  * current firmware of DPR-100 could not set it, so hardcoding
5765                  * now for complaince test.
5766                  */
5767                 DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
5768                 pattern_val = 0x3e0f83e0;
5769                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
5770                 pattern_val = 0x0f83e0f8;
5771                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
5772                 pattern_val = 0x0000f83e;
5773                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
5774                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5775                                DDI_DP_COMP_CTL_ENABLE |
5776                                DDI_DP_COMP_CTL_CUSTOM80);
5777                 break;
5778         case DP_PHY_TEST_PATTERN_CP2520:
5779                 /*
5780                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
5781                  * current firmware of DPR-100 could not set it, so hardcoding
5782                  * now for complaince test.
5783                  */
5784                 DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
5785                 pattern_val = 0xFB;
5786                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5787                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
5788                                pattern_val);
5789                 break;
5790         default:
5791                 WARN(1, "Invalid Phy Test Pattern\n");
5792         }
5793 }
5794
5795 static void
5796 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
5797                                   const struct intel_crtc_state *crtc_state)
5798 {
5799         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5800         struct drm_device *dev = dig_port->base.base.dev;
5801         struct drm_i915_private *dev_priv = to_i915(dev);
5802         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
5803         enum pipe pipe = crtc->pipe;
5804         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
5805
5806         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
5807                                                  TRANS_DDI_FUNC_CTL(pipe));
5808         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
5809         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
5810
5811         trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
5812                                       TGL_TRANS_DDI_PORT_MASK);
5813         trans_conf_value &= ~PIPECONF_ENABLE;
5814         dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
5815
5816         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
5817         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
5818                        trans_ddi_func_ctl_value);
5819         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
5820 }
5821
5822 static void
5823 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
5824                                  const struct intel_crtc_state *crtc_state)
5825 {
5826         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5827         struct drm_device *dev = dig_port->base.base.dev;
5828         struct drm_i915_private *dev_priv = to_i915(dev);
5829         enum port port = dig_port->base.port;
5830         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
5831         enum pipe pipe = crtc->pipe;
5832         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
5833
5834         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
5835                                                  TRANS_DDI_FUNC_CTL(pipe));
5836         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
5837         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
5838
5839         trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
5840                                     TGL_TRANS_DDI_SELECT_PORT(port);
5841         trans_conf_value |= PIPECONF_ENABLE;
5842         dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
5843
5844         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
5845         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
5846         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
5847                        trans_ddi_func_ctl_value);
5848 }
5849
5850 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
5851                                          const struct intel_crtc_state *crtc_state)
5852 {
5853         struct drm_dp_phy_test_params *data =
5854                 &intel_dp->compliance.test_data.phytest;
5855         u8 link_status[DP_LINK_STATUS_SIZE];
5856
5857         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
5858                                              link_status) < 0) {
5859                 DRM_DEBUG_KMS("failed to get link status\n");
5860                 return;
5861         }
5862
5863         /* retrieve vswing & pre-emphasis setting */
5864         intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
5865                                   link_status);
5866
5867         intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
5868
5869         intel_dp_set_signal_levels(intel_dp, crtc_state);
5870
5871         intel_dp_phy_pattern_update(intel_dp, crtc_state);
5872
5873         intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
5874
5875         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
5876                                     link_status[DP_DPCD_REV]);
5877 }
5878
5879 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
5880 {
5881         struct drm_dp_phy_test_params *data =
5882                 &intel_dp->compliance.test_data.phytest;
5883
5884         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
5885                 DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
5886                 return DP_TEST_NAK;
5887         }
5888
5889         /* Set test active flag here so userspace doesn't interrupt things */
5890         intel_dp->compliance.test_active = true;
5891
5892         return DP_TEST_ACK;
5893 }
5894
5895 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
5896 {
5897         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5898         u8 response = DP_TEST_NAK;
5899         u8 request = 0;
5900         int status;
5901
5902         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
5903         if (status <= 0) {
5904                 drm_dbg_kms(&i915->drm,
5905                             "Could not read test request from sink\n");
5906                 goto update_status;
5907         }
5908
5909         switch (request) {
5910         case DP_TEST_LINK_TRAINING:
5911                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
5912                 response = intel_dp_autotest_link_training(intel_dp);
5913                 break;
5914         case DP_TEST_LINK_VIDEO_PATTERN:
5915                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
5916                 response = intel_dp_autotest_video_pattern(intel_dp);
5917                 break;
5918         case DP_TEST_LINK_EDID_READ:
5919                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
5920                 response = intel_dp_autotest_edid(intel_dp);
5921                 break;
5922         case DP_TEST_LINK_PHY_TEST_PATTERN:
5923                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
5924                 response = intel_dp_autotest_phy_pattern(intel_dp);
5925                 break;
5926         default:
5927                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
5928                             request);
5929                 break;
5930         }
5931
5932         if (response & DP_TEST_ACK)
5933                 intel_dp->compliance.test_type = request;
5934
5935 update_status:
5936         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
5937         if (status <= 0)
5938                 drm_dbg_kms(&i915->drm,
5939                             "Could not write test response to sink\n");
5940 }
5941
5942 /**
5943  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
5944  * @intel_dp: Intel DP struct
5945  *
5946  * Read any pending MST interrupts, call MST core to handle these and ack the
5947  * interrupts. Check if the main and AUX link state is ok.
5948  *
5949  * Returns:
5950  * - %true if pending interrupts were serviced (or no interrupts were
5951  *   pending) w/o detecting an error condition.
5952  * - %false if an error condition - like AUX failure or a loss of link - is
5953  *   detected, which needs servicing from the hotplug work.
5954  */
5955 static bool
5956 intel_dp_check_mst_status(struct intel_dp *intel_dp)
5957 {
5958         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5959         bool link_ok = true;
5960
5961         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
5962
5963         for (;;) {
5964                 u8 esi[DP_DPRX_ESI_LEN] = {};
5965                 bool handled;
5966                 int retry;
5967
5968                 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
5969                         drm_dbg_kms(&i915->drm,
5970                                     "failed to get ESI - device may have failed\n");
5971                         link_ok = false;
5972
5973                         break;
5974                 }
5975
5976                 /* check link status - esi[10] = 0x200c */
5977                 if (intel_dp->active_mst_links > 0 && link_ok &&
5978                     !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
5979                         drm_dbg_kms(&i915->drm,
5980                                     "channel EQ not ok, retraining\n");
5981                         link_ok = false;
5982                 }
5983
5984                 drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
5985
5986                 drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
5987                 if (!handled)
5988                         break;
5989
5990                 for (retry = 0; retry < 3; retry++) {
5991                         int wret;
5992
5993                         wret = drm_dp_dpcd_write(&intel_dp->aux,
5994                                                  DP_SINK_COUNT_ESI+1,
5995                                                  &esi[1], 3);
5996                         if (wret == 3)
5997                                 break;
5998                 }
5999         }
6000
6001         return link_ok;
6002 }
6003
6004 static bool
6005 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
6006 {
6007         u8 link_status[DP_LINK_STATUS_SIZE];
6008
6009         if (!intel_dp->link_trained)
6010                 return false;
6011
6012         /*
6013          * While PSR source HW is enabled, it will control main-link sending
6014          * frames, enabling and disabling it so trying to do a retrain will fail
6015          * as the link would or not be on or it could mix training patterns
6016          * and frame data at the same time causing retrain to fail.
6017          * Also when exiting PSR, HW will retrain the link anyways fixing
6018          * any link status error.
6019          */
6020         if (intel_psr_enabled(intel_dp))
6021                 return false;
6022
6023         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
6024                                              link_status) < 0)
6025                 return false;
6026
6027         /*
6028          * Validate the cached values of intel_dp->link_rate and
6029          * intel_dp->lane_count before attempting to retrain.
6030          *
6031          * FIXME would be nice to user the crtc state here, but since
6032          * we need to call this from the short HPD handler that seems
6033          * a bit hard.
6034          */
6035         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
6036                                         intel_dp->lane_count))
6037                 return false;
6038
6039         /* Retrain if Channel EQ or CR not ok */
6040         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
6041 }
6042
6043 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
6044                                    const struct drm_connector_state *conn_state)
6045 {
6046         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6047         struct intel_encoder *encoder;
6048         enum pipe pipe;
6049
6050         if (!conn_state->best_encoder)
6051                 return false;
6052
6053         /* SST */
6054         encoder = &dp_to_dig_port(intel_dp)->base;
6055         if (conn_state->best_encoder == &encoder->base)
6056                 return true;
6057
6058         /* MST */
6059         for_each_pipe(i915, pipe) {
6060                 encoder = &intel_dp->mst_encoders[pipe]->base;
6061                 if (conn_state->best_encoder == &encoder->base)
6062                         return true;
6063         }
6064
6065         return false;
6066 }
6067
6068 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
6069                                       struct drm_modeset_acquire_ctx *ctx,
6070                                       u32 *crtc_mask)
6071 {
6072         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6073         struct drm_connector_list_iter conn_iter;
6074         struct intel_connector *connector;
6075         int ret = 0;
6076
6077         *crtc_mask = 0;
6078
6079         if (!intel_dp_needs_link_retrain(intel_dp))
6080                 return 0;
6081
6082         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
6083         for_each_intel_connector_iter(connector, &conn_iter) {
6084                 struct drm_connector_state *conn_state =
6085                         connector->base.state;
6086                 struct intel_crtc_state *crtc_state;
6087                 struct intel_crtc *crtc;
6088
6089                 if (!intel_dp_has_connector(intel_dp, conn_state))
6090                         continue;
6091
6092                 crtc = to_intel_crtc(conn_state->crtc);
6093                 if (!crtc)
6094                         continue;
6095
6096                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
6097                 if (ret)
6098                         break;
6099
6100                 crtc_state = to_intel_crtc_state(crtc->base.state);
6101
6102                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
6103
6104                 if (!crtc_state->hw.active)
6105                         continue;
6106
6107                 if (conn_state->commit &&
6108                     !try_wait_for_completion(&conn_state->commit->hw_done))
6109                         continue;
6110
6111                 *crtc_mask |= drm_crtc_mask(&crtc->base);
6112         }
6113         drm_connector_list_iter_end(&conn_iter);
6114
6115         if (!intel_dp_needs_link_retrain(intel_dp))
6116                 *crtc_mask = 0;
6117
6118         return ret;
6119 }
6120
6121 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
6122 {
6123         struct intel_connector *connector = intel_dp->attached_connector;
6124
6125         return connector->base.status == connector_status_connected ||
6126                 intel_dp->is_mst;
6127 }
6128
6129 int intel_dp_retrain_link(struct intel_encoder *encoder,
6130                           struct drm_modeset_acquire_ctx *ctx)
6131 {
6132         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6133         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6134         struct intel_crtc *crtc;
6135         u32 crtc_mask;
6136         int ret;
6137
6138         if (!intel_dp_is_connected(intel_dp))
6139                 return 0;
6140
6141         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
6142                                ctx);
6143         if (ret)
6144                 return ret;
6145
6146         ret = intel_dp_prep_link_retrain(intel_dp, ctx, &crtc_mask);
6147         if (ret)
6148                 return ret;
6149
6150         if (crtc_mask == 0)
6151                 return 0;
6152
6153         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
6154                     encoder->base.base.id, encoder->base.name);
6155
6156         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
6157                 const struct intel_crtc_state *crtc_state =
6158                         to_intel_crtc_state(crtc->base.state);
6159
6160                 /* Suppress underruns caused by re-training */
6161                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
6162                 if (crtc_state->has_pch_encoder)
6163                         intel_set_pch_fifo_underrun_reporting(dev_priv,
6164                                                               intel_crtc_pch_transcoder(crtc), false);
6165         }
6166
6167         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
6168                 const struct intel_crtc_state *crtc_state =
6169                         to_intel_crtc_state(crtc->base.state);
6170
6171                 /* retrain on the MST master transcoder */
6172                 if (INTEL_GEN(dev_priv) >= 12 &&
6173                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
6174                     !intel_dp_mst_is_master_trans(crtc_state))
6175                         continue;
6176
6177                 intel_dp_check_frl_training(intel_dp);
6178                 intel_dp_start_link_train(intel_dp, crtc_state);
6179                 intel_dp_stop_link_train(intel_dp, crtc_state);
6180                 break;
6181         }
6182
6183         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
6184                 const struct intel_crtc_state *crtc_state =
6185                         to_intel_crtc_state(crtc->base.state);
6186
6187                 /* Keep underrun reporting disabled until things are stable */
6188                 intel_wait_for_vblank(dev_priv, crtc->pipe);
6189
6190                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
6191                 if (crtc_state->has_pch_encoder)
6192                         intel_set_pch_fifo_underrun_reporting(dev_priv,
6193                                                               intel_crtc_pch_transcoder(crtc), true);
6194         }
6195
6196         return 0;
6197 }
6198
6199 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
6200                                   struct drm_modeset_acquire_ctx *ctx,
6201                                   u32 *crtc_mask)
6202 {
6203         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6204         struct drm_connector_list_iter conn_iter;
6205         struct intel_connector *connector;
6206         int ret = 0;
6207
6208         *crtc_mask = 0;
6209
6210         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
6211         for_each_intel_connector_iter(connector, &conn_iter) {
6212                 struct drm_connector_state *conn_state =
6213                         connector->base.state;
6214                 struct intel_crtc_state *crtc_state;
6215                 struct intel_crtc *crtc;
6216
6217                 if (!intel_dp_has_connector(intel_dp, conn_state))
6218                         continue;
6219
6220                 crtc = to_intel_crtc(conn_state->crtc);
6221                 if (!crtc)
6222                         continue;
6223
6224                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
6225                 if (ret)
6226                         break;
6227
6228                 crtc_state = to_intel_crtc_state(crtc->base.state);
6229
6230                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
6231
6232                 if (!crtc_state->hw.active)
6233                         continue;
6234
6235                 if (conn_state->commit &&
6236                     !try_wait_for_completion(&conn_state->commit->hw_done))
6237                         continue;
6238
6239                 *crtc_mask |= drm_crtc_mask(&crtc->base);
6240         }
6241         drm_connector_list_iter_end(&conn_iter);
6242
6243         return ret;
6244 }
6245
6246 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
6247                                 struct drm_modeset_acquire_ctx *ctx)
6248 {
6249         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6250         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6251         struct intel_crtc *crtc;
6252         u32 crtc_mask;
6253         int ret;
6254
6255         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
6256                                ctx);
6257         if (ret)
6258                 return ret;
6259
6260         ret = intel_dp_prep_phy_test(intel_dp, ctx, &crtc_mask);
6261         if (ret)
6262                 return ret;
6263
6264         if (crtc_mask == 0)
6265                 return 0;
6266
6267         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
6268                     encoder->base.base.id, encoder->base.name);
6269
6270         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
6271                 const struct intel_crtc_state *crtc_state =
6272                         to_intel_crtc_state(crtc->base.state);
6273
6274                 /* test on the MST master transcoder */
6275                 if (INTEL_GEN(dev_priv) >= 12 &&
6276                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
6277                     !intel_dp_mst_is_master_trans(crtc_state))
6278                         continue;
6279
6280                 intel_dp_process_phy_request(intel_dp, crtc_state);
6281                 break;
6282         }
6283
6284         return 0;
6285 }
6286
6287 static void intel_dp_phy_test(struct intel_encoder *encoder)
6288 {
6289         struct drm_modeset_acquire_ctx ctx;
6290         int ret;
6291
6292         drm_modeset_acquire_init(&ctx, 0);
6293
6294         for (;;) {
6295                 ret = intel_dp_do_phy_test(encoder, &ctx);
6296
6297                 if (ret == -EDEADLK) {
6298                         drm_modeset_backoff(&ctx);
6299                         continue;
6300                 }
6301
6302                 break;
6303         }
6304
6305         drm_modeset_drop_locks(&ctx);
6306         drm_modeset_acquire_fini(&ctx);
6307         drm_WARN(encoder->base.dev, ret,
6308                  "Acquiring modeset locks failed with %i\n", ret);
6309 }
6310
6311 /*
6312  * If display is now connected check links status,
6313  * there has been known issues of link loss triggering
6314  * long pulse.
6315  *
6316  * Some sinks (eg. ASUS PB287Q) seem to perform some
6317  * weird HPD ping pong during modesets. So we can apparently
6318  * end up with HPD going low during a modeset, and then
6319  * going back up soon after. And once that happens we must
6320  * retrain the link to get a picture. That's in case no
6321  * userspace component reacted to intermittent HPD dip.
6322  */
6323 static enum intel_hotplug_state
6324 intel_dp_hotplug(struct intel_encoder *encoder,
6325                  struct intel_connector *connector)
6326 {
6327         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6328         struct drm_modeset_acquire_ctx ctx;
6329         enum intel_hotplug_state state;
6330         int ret;
6331
6332         if (intel_dp->compliance.test_active &&
6333             intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
6334                 intel_dp_phy_test(encoder);
6335                 /* just do the PHY test and nothing else */
6336                 return INTEL_HOTPLUG_UNCHANGED;
6337         }
6338
6339         state = intel_encoder_hotplug(encoder, connector);
6340
6341         drm_modeset_acquire_init(&ctx, 0);
6342
6343         for (;;) {
6344                 ret = intel_dp_retrain_link(encoder, &ctx);
6345
6346                 if (ret == -EDEADLK) {
6347                         drm_modeset_backoff(&ctx);
6348                         continue;
6349                 }
6350
6351                 break;
6352         }
6353
6354         drm_modeset_drop_locks(&ctx);
6355         drm_modeset_acquire_fini(&ctx);
6356         drm_WARN(encoder->base.dev, ret,
6357                  "Acquiring modeset locks failed with %i\n", ret);
6358
6359         /*
6360          * Keeping it consistent with intel_ddi_hotplug() and
6361          * intel_hdmi_hotplug().
6362          */
6363         if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
6364                 state = INTEL_HOTPLUG_RETRY;
6365
6366         return state;
6367 }
6368
6369 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
6370 {
6371         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6372         u8 val;
6373
6374         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
6375                 return;
6376
6377         if (drm_dp_dpcd_readb(&intel_dp->aux,
6378                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
6379                 return;
6380
6381         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
6382
6383         if (val & DP_AUTOMATED_TEST_REQUEST)
6384                 intel_dp_handle_test_request(intel_dp);
6385
6386         if (val & DP_CP_IRQ)
6387                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
6388
6389         if (val & DP_SINK_SPECIFIC_IRQ)
6390                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
6391 }
6392
6393 /*
6394  * According to DP spec
6395  * 5.1.2:
6396  *  1. Read DPCD
6397  *  2. Configure link according to Receiver Capabilities
6398  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
6399  *  4. Check link status on receipt of hot-plug interrupt
6400  *
6401  * intel_dp_short_pulse -  handles short pulse interrupts
6402  * when full detection is not required.
6403  * Returns %true if short pulse is handled and full detection
6404  * is NOT required and %false otherwise.
6405  */
6406 static bool
6407 intel_dp_short_pulse(struct intel_dp *intel_dp)
6408 {
6409         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6410         u8 old_sink_count = intel_dp->sink_count;
6411         bool ret;
6412
6413         /*
6414          * Clearing compliance test variables to allow capturing
6415          * of values for next automated test request.
6416          */
6417         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
6418
6419         /*
6420          * Now read the DPCD to see if it's actually running
6421          * If the current value of sink count doesn't match with
6422          * the value that was stored earlier or dpcd read failed
6423          * we need to do full detection
6424          */
6425         ret = intel_dp_get_dpcd(intel_dp);
6426
6427         if ((old_sink_count != intel_dp->sink_count) || !ret) {
6428                 /* No need to proceed if we are going to do full detect */
6429                 return false;
6430         }
6431
6432         intel_dp_check_service_irq(intel_dp);
6433
6434         /* Handle CEC interrupts, if any */
6435         drm_dp_cec_irq(&intel_dp->aux);
6436
6437         /* defer to the hotplug work for link retraining if needed */
6438         if (intel_dp_needs_link_retrain(intel_dp))
6439                 return false;
6440
6441         intel_psr_short_pulse(intel_dp);
6442
6443         switch (intel_dp->compliance.test_type) {
6444         case DP_TEST_LINK_TRAINING:
6445                 drm_dbg_kms(&dev_priv->drm,
6446                             "Link Training Compliance Test requested\n");
6447                 /* Send a Hotplug Uevent to userspace to start modeset */
6448                 drm_kms_helper_hotplug_event(&dev_priv->drm);
6449                 break;
6450         case DP_TEST_LINK_PHY_TEST_PATTERN:
6451                 drm_dbg_kms(&dev_priv->drm,
6452                             "PHY test pattern Compliance Test requested\n");
6453                 /*
6454                  * Schedule long hpd to do the test
6455                  *
6456                  * FIXME get rid of the ad-hoc phy test modeset code
6457                  * and properly incorporate it into the normal modeset.
6458                  */
6459                 return false;
6460         }
6461
6462         return true;
6463 }
6464
6465 /* XXX this is probably wrong for multiple downstream ports */
6466 static enum drm_connector_status
6467 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
6468 {
6469         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6470         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6471         u8 *dpcd = intel_dp->dpcd;
6472         u8 type;
6473
6474         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
6475                 return connector_status_connected;
6476
6477         lspcon_resume(dig_port);
6478
6479         if (!intel_dp_get_dpcd(intel_dp))
6480                 return connector_status_disconnected;
6481
6482         /* if there's no downstream port, we're done */
6483         if (!drm_dp_is_branch(dpcd))
6484                 return connector_status_connected;
6485
6486         /* If we're HPD-aware, SINK_COUNT changes dynamically */
6487         if (intel_dp_has_sink_count(intel_dp) &&
6488             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
6489                 return intel_dp->sink_count ?
6490                 connector_status_connected : connector_status_disconnected;
6491         }
6492
6493         if (intel_dp_can_mst(intel_dp))
6494                 return connector_status_connected;
6495
6496         /* If no HPD, poke DDC gently */
6497         if (drm_probe_ddc(&intel_dp->aux.ddc))
6498                 return connector_status_connected;
6499
6500         /* Well we tried, say unknown for unreliable port types */
6501         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
6502                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
6503                 if (type == DP_DS_PORT_TYPE_VGA ||
6504                     type == DP_DS_PORT_TYPE_NON_EDID)
6505                         return connector_status_unknown;
6506         } else {
6507                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
6508                         DP_DWN_STRM_PORT_TYPE_MASK;
6509                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
6510                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
6511                         return connector_status_unknown;
6512         }
6513
6514         /* Anything else is out of spec, warn and ignore */
6515         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
6516         return connector_status_disconnected;
6517 }
6518
6519 static enum drm_connector_status
6520 edp_detect(struct intel_dp *intel_dp)
6521 {
6522         return connector_status_connected;
6523 }
6524
6525 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
6526 {
6527         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6528         u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
6529
6530         return intel_de_read(dev_priv, SDEISR) & bit;
6531 }
6532
6533 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
6534 {
6535         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6536         u32 bit;
6537
6538         switch (encoder->hpd_pin) {
6539         case HPD_PORT_B:
6540                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
6541                 break;
6542         case HPD_PORT_C:
6543                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
6544                 break;
6545         case HPD_PORT_D:
6546                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
6547                 break;
6548         default:
6549                 MISSING_CASE(encoder->hpd_pin);
6550                 return false;
6551         }
6552
6553         return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
6554 }
6555
6556 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
6557 {
6558         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6559         u32 bit;
6560
6561         switch (encoder->hpd_pin) {
6562         case HPD_PORT_B:
6563                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
6564                 break;
6565         case HPD_PORT_C:
6566                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
6567                 break;
6568         case HPD_PORT_D:
6569                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
6570                 break;
6571         default:
6572                 MISSING_CASE(encoder->hpd_pin);
6573                 return false;
6574         }
6575
6576         return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
6577 }
6578
6579 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
6580 {
6581         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6582         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
6583
6584         return intel_de_read(dev_priv, DEISR) & bit;
6585 }
6586
6587 /*
6588  * intel_digital_port_connected - is the specified port connected?
6589  * @encoder: intel_encoder
6590  *
6591  * In cases where there's a connector physically connected but it can't be used
6592  * by our hardware we also return false, since the rest of the driver should
6593  * pretty much treat the port as disconnected. This is relevant for type-C
6594  * (starting on ICL) where there's ownership involved.
6595  *
6596  * Return %true if port is connected, %false otherwise.
6597  */
6598 bool intel_digital_port_connected(struct intel_encoder *encoder)
6599 {
6600         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6601         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
6602         bool is_connected = false;
6603         intel_wakeref_t wakeref;
6604
6605         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
6606                 is_connected = dig_port->connected(encoder);
6607
6608         return is_connected;
6609 }
6610
6611 static struct edid *
6612 intel_dp_get_edid(struct intel_dp *intel_dp)
6613 {
6614         struct intel_connector *intel_connector = intel_dp->attached_connector;
6615
6616         /* use cached edid if we have one */
6617         if (intel_connector->edid) {
6618                 /* invalid edid */
6619                 if (IS_ERR(intel_connector->edid))
6620                         return NULL;
6621
6622                 return drm_edid_duplicate(intel_connector->edid);
6623         } else
6624                 return drm_get_edid(&intel_connector->base,
6625                                     &intel_dp->aux.ddc);
6626 }
6627
6628 static void
6629 intel_dp_update_dfp(struct intel_dp *intel_dp,
6630                     const struct edid *edid)
6631 {
6632         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6633         struct intel_connector *connector = intel_dp->attached_connector;
6634
6635         intel_dp->dfp.max_bpc =
6636                 drm_dp_downstream_max_bpc(intel_dp->dpcd,
6637                                           intel_dp->downstream_ports, edid);
6638
6639         intel_dp->dfp.max_dotclock =
6640                 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
6641                                                intel_dp->downstream_ports);
6642
6643         intel_dp->dfp.min_tmds_clock =
6644                 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
6645                                                  intel_dp->downstream_ports,
6646                                                  edid);
6647         intel_dp->dfp.max_tmds_clock =
6648                 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
6649                                                  intel_dp->downstream_ports,
6650                                                  edid);
6651
6652         intel_dp->dfp.pcon_max_frl_bw =
6653                 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
6654                                            intel_dp->downstream_ports);
6655
6656         drm_dbg_kms(&i915->drm,
6657                     "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
6658                     connector->base.base.id, connector->base.name,
6659                     intel_dp->dfp.max_bpc,
6660                     intel_dp->dfp.max_dotclock,
6661                     intel_dp->dfp.min_tmds_clock,
6662                     intel_dp->dfp.max_tmds_clock,
6663                     intel_dp->dfp.pcon_max_frl_bw);
6664 }
6665
6666 static void
6667 intel_dp_update_420(struct intel_dp *intel_dp)
6668 {
6669         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6670         struct intel_connector *connector = intel_dp->attached_connector;
6671         bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420;
6672
6673         /* No YCbCr output support on gmch platforms */
6674         if (HAS_GMCH(i915))
6675                 return;
6676
6677         /*
6678          * ILK doesn't seem capable of DP YCbCr output. The
6679          * displayed image is severly corrupted. SNB+ is fine.
6680          */
6681         if (IS_GEN(i915, 5))
6682                 return;
6683
6684         is_branch = drm_dp_is_branch(intel_dp->dpcd);
6685         ycbcr_420_passthrough =
6686                 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
6687                                                   intel_dp->downstream_ports);
6688         /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
6689         ycbcr_444_to_420 =
6690                 dp_to_dig_port(intel_dp)->lspcon.active ||
6691                 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
6692                                                         intel_dp->downstream_ports);
6693
6694         if (INTEL_GEN(i915) >= 11) {
6695                 /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
6696                 intel_dp->dfp.ycbcr_444_to_420 =
6697                         ycbcr_444_to_420 && !ycbcr_420_passthrough;
6698
6699                 connector->base.ycbcr_420_allowed =
6700                         !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
6701         } else {
6702                 /* 4:4:4->4:2:0 conversion is the only way */
6703                 intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
6704
6705                 connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
6706         }
6707
6708         drm_dbg_kms(&i915->drm,
6709                     "[CONNECTOR:%d:%s] YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
6710                     connector->base.base.id, connector->base.name,
6711                     yesno(connector->base.ycbcr_420_allowed),
6712                     yesno(intel_dp->dfp.ycbcr_444_to_420));
6713 }
6714
6715 static void
6716 intel_dp_set_edid(struct intel_dp *intel_dp)
6717 {
6718         struct intel_connector *connector = intel_dp->attached_connector;
6719         struct edid *edid;
6720
6721         intel_dp_unset_edid(intel_dp);
6722         edid = intel_dp_get_edid(intel_dp);
6723         connector->detect_edid = edid;
6724
6725         intel_dp_update_dfp(intel_dp, edid);
6726         intel_dp_update_420(intel_dp);
6727
6728         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
6729                 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
6730                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
6731         }
6732
6733         drm_dp_cec_set_edid(&intel_dp->aux, edid);
6734         intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
6735 }
6736
6737 static void
6738 intel_dp_unset_edid(struct intel_dp *intel_dp)
6739 {
6740         struct intel_connector *connector = intel_dp->attached_connector;
6741
6742         drm_dp_cec_unset_edid(&intel_dp->aux);
6743         kfree(connector->detect_edid);
6744         connector->detect_edid = NULL;
6745
6746         intel_dp->has_hdmi_sink = false;
6747         intel_dp->has_audio = false;
6748         intel_dp->edid_quirks = 0;
6749
6750         intel_dp->dfp.max_bpc = 0;
6751         intel_dp->dfp.max_dotclock = 0;
6752         intel_dp->dfp.min_tmds_clock = 0;
6753         intel_dp->dfp.max_tmds_clock = 0;
6754
6755         intel_dp->dfp.pcon_max_frl_bw = 0;
6756
6757         intel_dp->dfp.ycbcr_444_to_420 = false;
6758         connector->base.ycbcr_420_allowed = false;
6759 }
6760
6761 static int
6762 intel_dp_detect(struct drm_connector *connector,
6763                 struct drm_modeset_acquire_ctx *ctx,
6764                 bool force)
6765 {
6766         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6767         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6768         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6769         struct intel_encoder *encoder = &dig_port->base;
6770         enum drm_connector_status status;
6771
6772         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
6773                     connector->base.id, connector->name);
6774         drm_WARN_ON(&dev_priv->drm,
6775                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
6776
6777         if (!INTEL_DISPLAY_ENABLED(dev_priv))
6778                 return connector_status_disconnected;
6779
6780         /* Can't disconnect eDP */
6781         if (intel_dp_is_edp(intel_dp))
6782                 status = edp_detect(intel_dp);
6783         else if (intel_digital_port_connected(encoder))
6784                 status = intel_dp_detect_dpcd(intel_dp);
6785         else
6786                 status = connector_status_disconnected;
6787
6788         if (status == connector_status_disconnected) {
6789                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
6790                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
6791
6792                 if (intel_dp->is_mst) {
6793                         drm_dbg_kms(&dev_priv->drm,
6794                                     "MST device may have disappeared %d vs %d\n",
6795                                     intel_dp->is_mst,
6796                                     intel_dp->mst_mgr.mst_state);
6797                         intel_dp->is_mst = false;
6798                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6799                                                         intel_dp->is_mst);
6800                 }
6801
6802                 goto out;
6803         }
6804
6805         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
6806         if (INTEL_GEN(dev_priv) >= 11)
6807                 intel_dp_get_dsc_sink_cap(intel_dp);
6808
6809         intel_dp_configure_mst(intel_dp);
6810
6811         /*
6812          * TODO: Reset link params when switching to MST mode, until MST
6813          * supports link training fallback params.
6814          */
6815         if (intel_dp->reset_link_params || intel_dp->is_mst) {
6816                 /* Initial max link lane count */
6817                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
6818
6819                 /* Initial max link rate */
6820                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
6821
6822                 intel_dp->reset_link_params = false;
6823         }
6824
6825         intel_dp_print_rates(intel_dp);
6826
6827         if (intel_dp->is_mst) {
6828                 /*
6829                  * If we are in MST mode then this connector
6830                  * won't appear connected or have anything
6831                  * with EDID on it
6832                  */
6833                 status = connector_status_disconnected;
6834                 goto out;
6835         }
6836
6837         /*
6838          * Some external monitors do not signal loss of link synchronization
6839          * with an IRQ_HPD, so force a link status check.
6840          */
6841         if (!intel_dp_is_edp(intel_dp)) {
6842                 int ret;
6843
6844                 ret = intel_dp_retrain_link(encoder, ctx);
6845                 if (ret)
6846                         return ret;
6847         }
6848
6849         /*
6850          * Clearing NACK and defer counts to get their exact values
6851          * while reading EDID which are required by Compliance tests
6852          * 4.2.2.4 and 4.2.2.5
6853          */
6854         intel_dp->aux.i2c_nack_count = 0;
6855         intel_dp->aux.i2c_defer_count = 0;
6856
6857         intel_dp_set_edid(intel_dp);
6858         if (intel_dp_is_edp(intel_dp) ||
6859             to_intel_connector(connector)->detect_edid)
6860                 status = connector_status_connected;
6861
6862         intel_dp_check_service_irq(intel_dp);
6863
6864 out:
6865         if (status != connector_status_connected && !intel_dp->is_mst)
6866                 intel_dp_unset_edid(intel_dp);
6867
6868         /*
6869          * Make sure the refs for power wells enabled during detect are
6870          * dropped to avoid a new detect cycle triggered by HPD polling.
6871          */
6872         intel_display_power_flush_work(dev_priv);
6873
6874         if (!intel_dp_is_edp(intel_dp))
6875                 drm_dp_set_subconnector_property(connector,
6876                                                  status,
6877                                                  intel_dp->dpcd,
6878                                                  intel_dp->downstream_ports);
6879         return status;
6880 }
6881
6882 static void
6883 intel_dp_force(struct drm_connector *connector)
6884 {
6885         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6886         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6887         struct intel_encoder *intel_encoder = &dig_port->base;
6888         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
6889         enum intel_display_power_domain aux_domain =
6890                 intel_aux_power_domain(dig_port);
6891         intel_wakeref_t wakeref;
6892
6893         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
6894                     connector->base.id, connector->name);
6895         intel_dp_unset_edid(intel_dp);
6896
6897         if (connector->status != connector_status_connected)
6898                 return;
6899
6900         wakeref = intel_display_power_get(dev_priv, aux_domain);
6901
6902         intel_dp_set_edid(intel_dp);
6903
6904         intel_display_power_put(dev_priv, aux_domain, wakeref);
6905 }
6906
6907 static int intel_dp_get_modes(struct drm_connector *connector)
6908 {
6909         struct intel_connector *intel_connector = to_intel_connector(connector);
6910         struct edid *edid;
6911
6912         edid = intel_connector->detect_edid;
6913         if (edid) {
6914                 int ret = intel_connector_update_modes(connector, edid);
6915                 if (ret)
6916                         return ret;
6917         }
6918
6919         /* if eDP has no EDID, fall back to fixed mode */
6920         if (intel_dp_is_edp(intel_attached_dp(intel_connector)) &&
6921             intel_connector->panel.fixed_mode) {
6922                 struct drm_display_mode *mode;
6923
6924                 mode = drm_mode_duplicate(connector->dev,
6925                                           intel_connector->panel.fixed_mode);
6926                 if (mode) {
6927                         drm_mode_probed_add(connector, mode);
6928                         return 1;
6929                 }
6930         }
6931
6932         if (!edid) {
6933                 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
6934                 struct drm_display_mode *mode;
6935
6936                 mode = drm_dp_downstream_mode(connector->dev,
6937                                               intel_dp->dpcd,
6938                                               intel_dp->downstream_ports);
6939                 if (mode) {
6940                         drm_mode_probed_add(connector, mode);
6941                         return 1;
6942                 }
6943         }
6944
6945         return 0;
6946 }
6947
6948 static int
6949 intel_dp_connector_register(struct drm_connector *connector)
6950 {
6951         struct drm_i915_private *i915 = to_i915(connector->dev);
6952         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6953         int ret;
6954
6955         ret = intel_connector_register(connector);
6956         if (ret)
6957                 return ret;
6958
6959         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
6960                     intel_dp->aux.name, connector->kdev->kobj.name);
6961
6962         intel_dp->aux.dev = connector->kdev;
6963         ret = drm_dp_aux_register(&intel_dp->aux);
6964         if (!ret)
6965                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
6966         return ret;
6967 }
6968
6969 static void
6970 intel_dp_connector_unregister(struct drm_connector *connector)
6971 {
6972         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6973
6974         drm_dp_cec_unregister_connector(&intel_dp->aux);
6975         drm_dp_aux_unregister(&intel_dp->aux);
6976         intel_connector_unregister(connector);
6977 }
6978
6979 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
6980 {
6981         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
6982         struct intel_dp *intel_dp = &dig_port->dp;
6983
6984         intel_dp_mst_encoder_cleanup(dig_port);
6985         if (intel_dp_is_edp(intel_dp)) {
6986                 intel_wakeref_t wakeref;
6987
6988                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6989                 /*
6990                  * vdd might still be enabled do to the delayed vdd off.
6991                  * Make sure vdd is actually turned off here.
6992                  */
6993                 with_pps_lock(intel_dp, wakeref)
6994                         edp_panel_vdd_off_sync(intel_dp);
6995         }
6996
6997         intel_dp_aux_fini(intel_dp);
6998 }
6999
7000 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
7001 {
7002         intel_dp_encoder_flush_work(encoder);
7003
7004         drm_encoder_cleanup(encoder);
7005         kfree(enc_to_dig_port(to_intel_encoder(encoder)));
7006 }
7007
7008 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
7009 {
7010         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
7011         intel_wakeref_t wakeref;
7012
7013         if (!intel_dp_is_edp(intel_dp))
7014                 return;
7015
7016         /*
7017          * vdd might still be enabled do to the delayed vdd off.
7018          * Make sure vdd is actually turned off here.
7019          */
7020         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
7021         with_pps_lock(intel_dp, wakeref)
7022                 edp_panel_vdd_off_sync(intel_dp);
7023 }
7024
7025 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
7026 {
7027         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
7028         intel_wakeref_t wakeref;
7029
7030         if (!intel_dp_is_edp(intel_dp))
7031                 return;
7032
7033         with_pps_lock(intel_dp, wakeref)
7034                 wait_panel_power_cycle(intel_dp);
7035 }
7036
7037 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
7038 {
7039         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7040         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
7041
7042         lockdep_assert_held(&dev_priv->pps_mutex);
7043
7044         if (!edp_have_panel_vdd(intel_dp))
7045                 return;
7046
7047         /*
7048          * The VDD bit needs a power domain reference, so if the bit is
7049          * already enabled when we boot or resume, grab this reference and
7050          * schedule a vdd off, so we don't hold on to the reference
7051          * indefinitely.
7052          */
7053         drm_dbg_kms(&dev_priv->drm,
7054                     "VDD left on by BIOS, adjusting state tracking\n");
7055         intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
7056
7057         edp_panel_vdd_schedule_off(intel_dp);
7058 }
7059
7060 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
7061 {
7062         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7063         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
7064         enum pipe pipe;
7065
7066         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
7067                                   encoder->port, &pipe))
7068                 return pipe;
7069
7070         return INVALID_PIPE;
7071 }
7072
7073 void intel_dp_encoder_reset(struct drm_encoder *encoder)
7074 {
7075         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
7076         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
7077         intel_wakeref_t wakeref;
7078
7079         if (!HAS_DDI(dev_priv))
7080                 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
7081
7082         intel_dp->reset_link_params = true;
7083
7084         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
7085             !intel_dp_is_edp(intel_dp))
7086                 return;
7087
7088         with_pps_lock(intel_dp, wakeref) {
7089                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7090                         intel_dp->active_pipe = vlv_active_pipe(intel_dp);
7091
7092                 if (intel_dp_is_edp(intel_dp)) {
7093                         /*
7094                          * Reinit the power sequencer, in case BIOS did
7095                          * something nasty with it.
7096                          */
7097                         intel_dp_pps_init(intel_dp);
7098                         intel_edp_panel_vdd_sanitize(intel_dp);
7099                 }
7100         }
7101 }
7102
7103 static int intel_modeset_tile_group(struct intel_atomic_state *state,
7104                                     int tile_group_id)
7105 {
7106         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7107         struct drm_connector_list_iter conn_iter;
7108         struct drm_connector *connector;
7109         int ret = 0;
7110
7111         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
7112         drm_for_each_connector_iter(connector, &conn_iter) {
7113                 struct drm_connector_state *conn_state;
7114                 struct intel_crtc_state *crtc_state;
7115                 struct intel_crtc *crtc;
7116
7117                 if (!connector->has_tile ||
7118                     connector->tile_group->id != tile_group_id)
7119                         continue;
7120
7121                 conn_state = drm_atomic_get_connector_state(&state->base,
7122                                                             connector);
7123                 if (IS_ERR(conn_state)) {
7124                         ret = PTR_ERR(conn_state);
7125                         break;
7126                 }
7127
7128                 crtc = to_intel_crtc(conn_state->crtc);
7129
7130                 if (!crtc)
7131                         continue;
7132
7133                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
7134                 crtc_state->uapi.mode_changed = true;
7135
7136                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
7137                 if (ret)
7138                         break;
7139         }
7140         drm_connector_list_iter_end(&conn_iter);
7141
7142         return ret;
7143 }
7144
7145 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
7146 {
7147         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7148         struct intel_crtc *crtc;
7149
7150         if (transcoders == 0)
7151                 return 0;
7152
7153         for_each_intel_crtc(&dev_priv->drm, crtc) {
7154                 struct intel_crtc_state *crtc_state;
7155                 int ret;
7156
7157                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
7158                 if (IS_ERR(crtc_state))
7159                         return PTR_ERR(crtc_state);
7160
7161                 if (!crtc_state->hw.enable)
7162                         continue;
7163
7164                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
7165                         continue;
7166
7167                 crtc_state->uapi.mode_changed = true;
7168
7169                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
7170                 if (ret)
7171                         return ret;
7172
7173                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
7174                 if (ret)
7175                         return ret;
7176
7177                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
7178         }
7179
7180         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
7181
7182         return 0;
7183 }
7184
7185 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
7186                                       struct drm_connector *connector)
7187 {
7188         const struct drm_connector_state *old_conn_state =
7189                 drm_atomic_get_old_connector_state(&state->base, connector);
7190         const struct intel_crtc_state *old_crtc_state;
7191         struct intel_crtc *crtc;
7192         u8 transcoders;
7193
7194         crtc = to_intel_crtc(old_conn_state->crtc);
7195         if (!crtc)
7196                 return 0;
7197
7198         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
7199
7200         if (!old_crtc_state->hw.active)
7201                 return 0;
7202
7203         transcoders = old_crtc_state->sync_mode_slaves_mask;
7204         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
7205                 transcoders |= BIT(old_crtc_state->master_transcoder);
7206
7207         return intel_modeset_affected_transcoders(state,
7208                                                   transcoders);
7209 }
7210
7211 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
7212                                            struct drm_atomic_state *_state)
7213 {
7214         struct drm_i915_private *dev_priv = to_i915(conn->dev);
7215         struct intel_atomic_state *state = to_intel_atomic_state(_state);
7216         int ret;
7217
7218         ret = intel_digital_connector_atomic_check(conn, &state->base);
7219         if (ret)
7220                 return ret;
7221
7222         /*
7223          * We don't enable port sync on BDW due to missing w/as and
7224          * due to not having adjusted the modeset sequence appropriately.
7225          */
7226         if (INTEL_GEN(dev_priv) < 9)
7227                 return 0;
7228
7229         if (!intel_connector_needs_modeset(state, conn))
7230                 return 0;
7231
7232         if (conn->has_tile) {
7233                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
7234                 if (ret)
7235                         return ret;
7236         }
7237
7238         return intel_modeset_synced_crtcs(state, conn);
7239 }
7240
7241 static const struct drm_connector_funcs intel_dp_connector_funcs = {
7242         .force = intel_dp_force,
7243         .fill_modes = drm_helper_probe_single_connector_modes,
7244         .atomic_get_property = intel_digital_connector_atomic_get_property,
7245         .atomic_set_property = intel_digital_connector_atomic_set_property,
7246         .late_register = intel_dp_connector_register,
7247         .early_unregister = intel_dp_connector_unregister,
7248         .destroy = intel_connector_destroy,
7249         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
7250         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
7251 };
7252
7253 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
7254         .detect_ctx = intel_dp_detect,
7255         .get_modes = intel_dp_get_modes,
7256         .mode_valid = intel_dp_mode_valid,
7257         .atomic_check = intel_dp_connector_atomic_check,
7258 };
7259
7260 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
7261         .reset = intel_dp_encoder_reset,
7262         .destroy = intel_dp_encoder_destroy,
7263 };
7264
7265 static bool intel_edp_have_power(struct intel_dp *intel_dp)
7266 {
7267         intel_wakeref_t wakeref;
7268         bool have_power = false;
7269
7270         with_pps_lock(intel_dp, wakeref) {
7271                 have_power = edp_have_panel_power(intel_dp) &&
7272                                                   edp_have_panel_vdd(intel_dp);
7273         }
7274
7275         return have_power;
7276 }
7277
7278 enum irqreturn
7279 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
7280 {
7281         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
7282         struct intel_dp *intel_dp = &dig_port->dp;
7283
7284         if (dig_port->base.type == INTEL_OUTPUT_EDP &&
7285             (long_hpd || !intel_edp_have_power(intel_dp))) {
7286                 /*
7287                  * vdd off can generate a long/short pulse on eDP which
7288                  * would require vdd on to handle it, and thus we
7289                  * would end up in an endless cycle of
7290                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
7291                  */
7292                 drm_dbg_kms(&i915->drm,
7293                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
7294                             long_hpd ? "long" : "short",
7295                             dig_port->base.base.base.id,
7296                             dig_port->base.base.name);
7297                 return IRQ_HANDLED;
7298         }
7299
7300         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
7301                     dig_port->base.base.base.id,
7302                     dig_port->base.base.name,
7303                     long_hpd ? "long" : "short");
7304
7305         if (long_hpd) {
7306                 intel_dp->reset_link_params = true;
7307                 return IRQ_NONE;
7308         }
7309
7310         if (intel_dp->is_mst) {
7311                 if (!intel_dp_check_mst_status(intel_dp))
7312                         return IRQ_NONE;
7313         } else if (!intel_dp_short_pulse(intel_dp)) {
7314                 return IRQ_NONE;
7315         }
7316
7317         return IRQ_HANDLED;
7318 }
7319
7320 /* check the VBT to see whether the eDP is on another port */
7321 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
7322 {
7323         /*
7324          * eDP not supported on g4x. so bail out early just
7325          * for a bit extra safety in case the VBT is bonkers.
7326          */
7327         if (INTEL_GEN(dev_priv) < 5)
7328                 return false;
7329
7330         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
7331                 return true;
7332
7333         return intel_bios_is_port_edp(dev_priv, port);
7334 }
7335
7336 static void
7337 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
7338 {
7339         struct drm_i915_private *dev_priv = to_i915(connector->dev);
7340         enum port port = dp_to_dig_port(intel_dp)->base.port;
7341
7342         if (!intel_dp_is_edp(intel_dp))
7343                 drm_connector_attach_dp_subconnector_property(connector);
7344
7345         if (!IS_G4X(dev_priv) && port != PORT_A)
7346                 intel_attach_force_audio_property(connector);
7347
7348         intel_attach_broadcast_rgb_property(connector);
7349         if (HAS_GMCH(dev_priv))
7350                 drm_connector_attach_max_bpc_property(connector, 6, 10);
7351         else if (INTEL_GEN(dev_priv) >= 5)
7352                 drm_connector_attach_max_bpc_property(connector, 6, 12);
7353
7354         intel_attach_colorspace_property(connector);
7355
7356         if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
7357                 drm_object_attach_property(&connector->base,
7358                                            connector->dev->mode_config.hdr_output_metadata_property,
7359                                            0);
7360
7361         if (intel_dp_is_edp(intel_dp)) {
7362                 u32 allowed_scalers;
7363
7364                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
7365                 if (!HAS_GMCH(dev_priv))
7366                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
7367
7368                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
7369
7370                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
7371
7372         }
7373 }
7374
7375 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
7376 {
7377         intel_dp->panel_power_off_time = ktime_get_boottime();
7378         intel_dp->last_power_on = jiffies;
7379         intel_dp->last_backlight_off = jiffies;
7380 }
7381
7382 static void
7383 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
7384 {
7385         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7386         u32 pp_on, pp_off, pp_ctl;
7387         struct pps_registers regs;
7388
7389         intel_pps_get_registers(intel_dp, &regs);
7390
7391         pp_ctl = ilk_get_pp_control(intel_dp);
7392
7393         /* Ensure PPS is unlocked */
7394         if (!HAS_DDI(dev_priv))
7395                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7396
7397         pp_on = intel_de_read(dev_priv, regs.pp_on);
7398         pp_off = intel_de_read(dev_priv, regs.pp_off);
7399
7400         /* Pull timing values out of registers */
7401         seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
7402         seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
7403         seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
7404         seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
7405
7406         if (i915_mmio_reg_valid(regs.pp_div)) {
7407                 u32 pp_div;
7408
7409                 pp_div = intel_de_read(dev_priv, regs.pp_div);
7410
7411                 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
7412         } else {
7413                 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
7414         }
7415 }
7416
7417 static void
7418 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
7419 {
7420         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
7421                       state_name,
7422                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
7423 }
7424
7425 static void
7426 intel_pps_verify_state(struct intel_dp *intel_dp)
7427 {
7428         struct edp_power_seq hw;
7429         struct edp_power_seq *sw = &intel_dp->pps_delays;
7430
7431         intel_pps_readout_hw_state(intel_dp, &hw);
7432
7433         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
7434             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
7435                 DRM_ERROR("PPS state mismatch\n");
7436                 intel_pps_dump_state("sw", sw);
7437                 intel_pps_dump_state("hw", &hw);
7438         }
7439 }
7440
7441 static void
7442 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
7443 {
7444         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7445         struct edp_power_seq cur, vbt, spec,
7446                 *final = &intel_dp->pps_delays;
7447
7448         lockdep_assert_held(&dev_priv->pps_mutex);
7449
7450         /* already initialized? */
7451         if (final->t11_t12 != 0)
7452                 return;
7453
7454         intel_pps_readout_hw_state(intel_dp, &cur);
7455
7456         intel_pps_dump_state("cur", &cur);
7457
7458         vbt = dev_priv->vbt.edp.pps;
7459         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
7460          * of 500ms appears to be too short. Ocassionally the panel
7461          * just fails to power back on. Increasing the delay to 800ms
7462          * seems sufficient to avoid this problem.
7463          */
7464         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
7465                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
7466                 drm_dbg_kms(&dev_priv->drm,
7467                             "Increasing T12 panel delay as per the quirk to %d\n",
7468                             vbt.t11_t12);
7469         }
7470         /* T11_T12 delay is special and actually in units of 100ms, but zero
7471          * based in the hw (so we need to add 100 ms). But the sw vbt
7472          * table multiplies it with 1000 to make it in units of 100usec,
7473          * too. */
7474         vbt.t11_t12 += 100 * 10;
7475
7476         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
7477          * our hw here, which are all in 100usec. */
7478         spec.t1_t3 = 210 * 10;
7479         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
7480         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
7481         spec.t10 = 500 * 10;
7482         /* This one is special and actually in units of 100ms, but zero
7483          * based in the hw (so we need to add 100 ms). But the sw vbt
7484          * table multiplies it with 1000 to make it in units of 100usec,
7485          * too. */
7486         spec.t11_t12 = (510 + 100) * 10;
7487
7488         intel_pps_dump_state("vbt", &vbt);
7489
7490         /* Use the max of the register settings and vbt. If both are
7491          * unset, fall back to the spec limits. */
7492 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
7493                                        spec.field : \
7494                                        max(cur.field, vbt.field))
7495         assign_final(t1_t3);
7496         assign_final(t8);
7497         assign_final(t9);
7498         assign_final(t10);
7499         assign_final(t11_t12);
7500 #undef assign_final
7501
7502 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
7503         intel_dp->panel_power_up_delay = get_delay(t1_t3);
7504         intel_dp->backlight_on_delay = get_delay(t8);
7505         intel_dp->backlight_off_delay = get_delay(t9);
7506         intel_dp->panel_power_down_delay = get_delay(t10);
7507         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
7508 #undef get_delay
7509
7510         drm_dbg_kms(&dev_priv->drm,
7511                     "panel power up delay %d, power down delay %d, power cycle delay %d\n",
7512                     intel_dp->panel_power_up_delay,
7513                     intel_dp->panel_power_down_delay,
7514                     intel_dp->panel_power_cycle_delay);
7515
7516         drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
7517                     intel_dp->backlight_on_delay,
7518                     intel_dp->backlight_off_delay);
7519
7520         /*
7521          * We override the HW backlight delays to 1 because we do manual waits
7522          * on them. For T8, even BSpec recommends doing it. For T9, if we
7523          * don't do this, we'll end up waiting for the backlight off delay
7524          * twice: once when we do the manual sleep, and once when we disable
7525          * the panel and wait for the PP_STATUS bit to become zero.
7526          */
7527         final->t8 = 1;
7528         final->t9 = 1;
7529
7530         /*
7531          * HW has only a 100msec granularity for t11_t12 so round it up
7532          * accordingly.
7533          */
7534         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
7535 }
7536
7537 static void
7538 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
7539                                               bool force_disable_vdd)
7540 {
7541         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7542         u32 pp_on, pp_off, port_sel = 0;
7543         int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
7544         struct pps_registers regs;
7545         enum port port = dp_to_dig_port(intel_dp)->base.port;
7546         const struct edp_power_seq *seq = &intel_dp->pps_delays;
7547
7548         lockdep_assert_held(&dev_priv->pps_mutex);
7549
7550         intel_pps_get_registers(intel_dp, &regs);
7551
7552         /*
7553          * On some VLV machines the BIOS can leave the VDD
7554          * enabled even on power sequencers which aren't
7555          * hooked up to any port. This would mess up the
7556          * power domain tracking the first time we pick
7557          * one of these power sequencers for use since
7558          * edp_panel_vdd_on() would notice that the VDD was
7559          * already on and therefore wouldn't grab the power
7560          * domain reference. Disable VDD first to avoid this.
7561          * This also avoids spuriously turning the VDD on as
7562          * soon as the new power sequencer gets initialized.
7563          */
7564         if (force_disable_vdd) {
7565                 u32 pp = ilk_get_pp_control(intel_dp);
7566
7567                 drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
7568                          "Panel power already on\n");
7569
7570                 if (pp & EDP_FORCE_VDD)
7571                         drm_dbg_kms(&dev_priv->drm,
7572                                     "VDD already on, disabling first\n");
7573
7574                 pp &= ~EDP_FORCE_VDD;
7575
7576                 intel_de_write(dev_priv, regs.pp_ctrl, pp);
7577         }
7578
7579         pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
7580                 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
7581         pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
7582                 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
7583
7584         /* Haswell doesn't have any port selection bits for the panel
7585          * power sequencer any more. */
7586         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7587                 port_sel = PANEL_PORT_SELECT_VLV(port);
7588         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
7589                 switch (port) {
7590                 case PORT_A:
7591                         port_sel = PANEL_PORT_SELECT_DPA;
7592                         break;
7593                 case PORT_C:
7594                         port_sel = PANEL_PORT_SELECT_DPC;
7595                         break;
7596                 case PORT_D:
7597                         port_sel = PANEL_PORT_SELECT_DPD;
7598                         break;
7599                 default:
7600                         MISSING_CASE(port);
7601                         break;
7602                 }
7603         }
7604
7605         pp_on |= port_sel;
7606
7607         intel_de_write(dev_priv, regs.pp_on, pp_on);
7608         intel_de_write(dev_priv, regs.pp_off, pp_off);
7609
7610         /*
7611          * Compute the divisor for the pp clock, simply match the Bspec formula.
7612          */
7613         if (i915_mmio_reg_valid(regs.pp_div)) {
7614                 intel_de_write(dev_priv, regs.pp_div,
7615                                REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
7616         } else {
7617                 u32 pp_ctl;
7618
7619                 pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl);
7620                 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
7621                 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
7622                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7623         }
7624
7625         drm_dbg_kms(&dev_priv->drm,
7626                     "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
7627                     intel_de_read(dev_priv, regs.pp_on),
7628                     intel_de_read(dev_priv, regs.pp_off),
7629                     i915_mmio_reg_valid(regs.pp_div) ?
7630                     intel_de_read(dev_priv, regs.pp_div) :
7631                     (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
7632 }
7633
7634 static void intel_dp_pps_init(struct intel_dp *intel_dp)
7635 {
7636         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7637
7638         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7639                 vlv_initial_power_sequencer_setup(intel_dp);
7640         } else {
7641                 intel_dp_init_panel_power_sequencer(intel_dp);
7642                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
7643         }
7644 }
7645
7646 /**
7647  * intel_dp_set_drrs_state - program registers for RR switch to take effect
7648  * @dev_priv: i915 device
7649  * @crtc_state: a pointer to the active intel_crtc_state
7650  * @refresh_rate: RR to be programmed
7651  *
7652  * This function gets called when refresh rate (RR) has to be changed from
7653  * one frequency to another. Switches can be between high and low RR
7654  * supported by the panel or to any other RR based on media playback (in
7655  * this case, RR value needs to be passed from user space).
7656  *
7657  * The caller of this function needs to take a lock on dev_priv->drrs.
7658  */
7659 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
7660                                     const struct intel_crtc_state *crtc_state,
7661                                     int refresh_rate)
7662 {
7663         struct intel_dp *intel_dp = dev_priv->drrs.dp;
7664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
7665         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
7666
7667         if (refresh_rate <= 0) {
7668                 drm_dbg_kms(&dev_priv->drm,
7669                             "Refresh rate should be positive non-zero.\n");
7670                 return;
7671         }
7672
7673         if (intel_dp == NULL) {
7674                 drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
7675                 return;
7676         }
7677
7678         if (!intel_crtc) {
7679                 drm_dbg_kms(&dev_priv->drm,
7680                             "DRRS: intel_crtc not initialized\n");
7681                 return;
7682         }
7683
7684         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
7685                 drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
7686                 return;
7687         }
7688
7689         if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) ==
7690                         refresh_rate)
7691                 index = DRRS_LOW_RR;
7692
7693         if (index == dev_priv->drrs.refresh_rate_type) {
7694                 drm_dbg_kms(&dev_priv->drm,
7695                             "DRRS requested for previously set RR...ignoring\n");
7696                 return;
7697         }
7698
7699         if (!crtc_state->hw.active) {
7700                 drm_dbg_kms(&dev_priv->drm,
7701                             "eDP encoder disabled. CRTC not Active\n");
7702                 return;
7703         }
7704
7705         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
7706                 switch (index) {
7707                 case DRRS_HIGH_RR:
7708                         intel_dp_set_m_n(crtc_state, M1_N1);
7709                         break;
7710                 case DRRS_LOW_RR:
7711                         intel_dp_set_m_n(crtc_state, M2_N2);
7712                         break;
7713                 case DRRS_MAX_RR:
7714                 default:
7715                         drm_err(&dev_priv->drm,
7716                                 "Unsupported refreshrate type\n");
7717                 }
7718         } else if (INTEL_GEN(dev_priv) > 6) {
7719                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
7720                 u32 val;
7721
7722                 val = intel_de_read(dev_priv, reg);
7723                 if (index > DRRS_HIGH_RR) {
7724                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7725                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7726                         else
7727                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
7728                 } else {
7729                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7730                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7731                         else
7732                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
7733                 }
7734                 intel_de_write(dev_priv, reg, val);
7735         }
7736
7737         dev_priv->drrs.refresh_rate_type = index;
7738
7739         drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
7740                     refresh_rate);
7741 }
7742
7743 static void
7744 intel_edp_drrs_enable_locked(struct intel_dp *intel_dp)
7745 {
7746         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7747
7748         dev_priv->drrs.busy_frontbuffer_bits = 0;
7749         dev_priv->drrs.dp = intel_dp;
7750 }
7751
7752 /**
7753  * intel_edp_drrs_enable - init drrs struct if supported
7754  * @intel_dp: DP struct
7755  * @crtc_state: A pointer to the active crtc state.
7756  *
7757  * Initializes frontbuffer_bits and drrs.dp
7758  */
7759 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
7760                            const struct intel_crtc_state *crtc_state)
7761 {
7762         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7763
7764         if (!crtc_state->has_drrs)
7765                 return;
7766
7767         drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
7768
7769         mutex_lock(&dev_priv->drrs.mutex);
7770
7771         if (dev_priv->drrs.dp) {
7772                 drm_warn(&dev_priv->drm, "DRRS already enabled\n");
7773                 goto unlock;
7774         }
7775
7776         intel_edp_drrs_enable_locked(intel_dp);
7777
7778 unlock:
7779         mutex_unlock(&dev_priv->drrs.mutex);
7780 }
7781
7782 static void
7783 intel_edp_drrs_disable_locked(struct intel_dp *intel_dp,
7784                               const struct intel_crtc_state *crtc_state)
7785 {
7786         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7787
7788         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
7789                 int refresh;
7790
7791                 refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
7792                 intel_dp_set_drrs_state(dev_priv, crtc_state, refresh);
7793         }
7794
7795         dev_priv->drrs.dp = NULL;
7796 }
7797
7798 /**
7799  * intel_edp_drrs_disable - Disable DRRS
7800  * @intel_dp: DP struct
7801  * @old_crtc_state: Pointer to old crtc_state.
7802  *
7803  */
7804 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
7805                             const struct intel_crtc_state *old_crtc_state)
7806 {
7807         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7808
7809         if (!old_crtc_state->has_drrs)
7810                 return;
7811
7812         mutex_lock(&dev_priv->drrs.mutex);
7813         if (!dev_priv->drrs.dp) {
7814                 mutex_unlock(&dev_priv->drrs.mutex);
7815                 return;
7816         }
7817
7818         intel_edp_drrs_disable_locked(intel_dp, old_crtc_state);
7819         mutex_unlock(&dev_priv->drrs.mutex);
7820
7821         cancel_delayed_work_sync(&dev_priv->drrs.work);
7822 }
7823
7824 /**
7825  * intel_edp_drrs_update - Update DRRS state
7826  * @intel_dp: Intel DP
7827  * @crtc_state: new CRTC state
7828  *
7829  * This function will update DRRS states, disabling or enabling DRRS when
7830  * executing fastsets. For full modeset, intel_edp_drrs_disable() and
7831  * intel_edp_drrs_enable() should be called instead.
7832  */
7833 void
7834 intel_edp_drrs_update(struct intel_dp *intel_dp,
7835                       const struct intel_crtc_state *crtc_state)
7836 {
7837         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7838
7839         if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
7840                 return;
7841
7842         mutex_lock(&dev_priv->drrs.mutex);
7843
7844         /* New state matches current one? */
7845         if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
7846                 goto unlock;
7847
7848         if (crtc_state->has_drrs)
7849                 intel_edp_drrs_enable_locked(intel_dp);
7850         else
7851                 intel_edp_drrs_disable_locked(intel_dp, crtc_state);
7852
7853 unlock:
7854         mutex_unlock(&dev_priv->drrs.mutex);
7855 }
7856
7857 static void intel_edp_drrs_downclock_work(struct work_struct *work)
7858 {
7859         struct drm_i915_private *dev_priv =
7860                 container_of(work, typeof(*dev_priv), drrs.work.work);
7861         struct intel_dp *intel_dp;
7862
7863         mutex_lock(&dev_priv->drrs.mutex);
7864
7865         intel_dp = dev_priv->drrs.dp;
7866
7867         if (!intel_dp)
7868                 goto unlock;
7869
7870         /*
7871          * The delayed work can race with an invalidate hence we need to
7872          * recheck.
7873          */
7874
7875         if (dev_priv->drrs.busy_frontbuffer_bits)
7876                 goto unlock;
7877
7878         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
7879                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
7880
7881                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7882                         drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode));
7883         }
7884
7885 unlock:
7886         mutex_unlock(&dev_priv->drrs.mutex);
7887 }
7888
7889 /**
7890  * intel_edp_drrs_invalidate - Disable Idleness DRRS
7891  * @dev_priv: i915 device
7892  * @frontbuffer_bits: frontbuffer plane tracking bits
7893  *
7894  * This function gets called everytime rendering on the given planes start.
7895  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
7896  *
7897  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7898  */
7899 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
7900                                unsigned int frontbuffer_bits)
7901 {
7902         struct intel_dp *intel_dp;
7903         struct drm_crtc *crtc;
7904         enum pipe pipe;
7905
7906         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7907                 return;
7908
7909         cancel_delayed_work(&dev_priv->drrs.work);
7910
7911         mutex_lock(&dev_priv->drrs.mutex);
7912
7913         intel_dp = dev_priv->drrs.dp;
7914         if (!intel_dp) {
7915                 mutex_unlock(&dev_priv->drrs.mutex);
7916                 return;
7917         }
7918
7919         crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
7920         pipe = to_intel_crtc(crtc)->pipe;
7921
7922         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
7923         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
7924
7925         /* invalidate means busy screen hence upclock */
7926         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7927                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7928                                         drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
7929
7930         mutex_unlock(&dev_priv->drrs.mutex);
7931 }
7932
7933 /**
7934  * intel_edp_drrs_flush - Restart Idleness DRRS
7935  * @dev_priv: i915 device
7936  * @frontbuffer_bits: frontbuffer plane tracking bits
7937  *
7938  * This function gets called every time rendering on the given planes has
7939  * completed or flip on a crtc is completed. So DRRS should be upclocked
7940  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
7941  * if no other planes are dirty.
7942  *
7943  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7944  */
7945 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
7946                           unsigned int frontbuffer_bits)
7947 {
7948         struct intel_dp *intel_dp;
7949         struct drm_crtc *crtc;
7950         enum pipe pipe;
7951
7952         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7953                 return;
7954
7955         cancel_delayed_work(&dev_priv->drrs.work);
7956
7957         mutex_lock(&dev_priv->drrs.mutex);
7958
7959         intel_dp = dev_priv->drrs.dp;
7960         if (!intel_dp) {
7961                 mutex_unlock(&dev_priv->drrs.mutex);
7962                 return;
7963         }
7964
7965         crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
7966         pipe = to_intel_crtc(crtc)->pipe;
7967
7968         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
7969         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
7970
7971         /* flush means busy screen hence upclock */
7972         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7973                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7974                                         drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
7975
7976         /*
7977          * flush also means no more activity hence schedule downclock, if all
7978          * other fbs are quiescent too
7979          */
7980         if (!dev_priv->drrs.busy_frontbuffer_bits)
7981                 schedule_delayed_work(&dev_priv->drrs.work,
7982                                 msecs_to_jiffies(1000));
7983         mutex_unlock(&dev_priv->drrs.mutex);
7984 }
7985
7986 /**
7987  * DOC: Display Refresh Rate Switching (DRRS)
7988  *
7989  * Display Refresh Rate Switching (DRRS) is a power conservation feature
7990  * which enables swtching between low and high refresh rates,
7991  * dynamically, based on the usage scenario. This feature is applicable
7992  * for internal panels.
7993  *
7994  * Indication that the panel supports DRRS is given by the panel EDID, which
7995  * would list multiple refresh rates for one resolution.
7996  *
7997  * DRRS is of 2 types - static and seamless.
7998  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
7999  * (may appear as a blink on screen) and is used in dock-undock scenario.
8000  * Seamless DRRS involves changing RR without any visual effect to the user
8001  * and can be used during normal system usage. This is done by programming
8002  * certain registers.
8003  *
8004  * Support for static/seamless DRRS may be indicated in the VBT based on
8005  * inputs from the panel spec.
8006  *
8007  * DRRS saves power by switching to low RR based on usage scenarios.
8008  *
8009  * The implementation is based on frontbuffer tracking implementation.  When
8010  * there is a disturbance on the screen triggered by user activity or a periodic
8011  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
8012  * no movement on screen, after a timeout of 1 second, a switch to low RR is
8013  * made.
8014  *
8015  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
8016  * and intel_edp_drrs_flush() are called.
8017  *
8018  * DRRS can be further extended to support other internal panels and also
8019  * the scenario of video playback wherein RR is set based on the rate
8020  * requested by userspace.
8021  */
8022
8023 /**
8024  * intel_dp_drrs_init - Init basic DRRS work and mutex.
8025  * @connector: eDP connector
8026  * @fixed_mode: preferred mode of panel
8027  *
8028  * This function is  called only once at driver load to initialize basic
8029  * DRRS stuff.
8030  *
8031  * Returns:
8032  * Downclock mode if panel supports it, else return NULL.
8033  * DRRS support is determined by the presence of downclock mode (apart
8034  * from VBT setting).
8035  */
8036 static struct drm_display_mode *
8037 intel_dp_drrs_init(struct intel_connector *connector,
8038                    struct drm_display_mode *fixed_mode)
8039 {
8040         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
8041         struct drm_display_mode *downclock_mode = NULL;
8042
8043         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
8044         mutex_init(&dev_priv->drrs.mutex);
8045
8046         if (INTEL_GEN(dev_priv) <= 6) {
8047                 drm_dbg_kms(&dev_priv->drm,
8048                             "DRRS supported for Gen7 and above\n");
8049                 return NULL;
8050         }
8051
8052         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
8053                 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
8054                 return NULL;
8055         }
8056
8057         downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
8058         if (!downclock_mode) {
8059                 drm_dbg_kms(&dev_priv->drm,
8060                             "Downclock mode is not found. DRRS not supported\n");
8061                 return NULL;
8062         }
8063
8064         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
8065
8066         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
8067         drm_dbg_kms(&dev_priv->drm,
8068                     "seamless DRRS supported for eDP panel.\n");
8069         return downclock_mode;
8070 }
8071
8072 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
8073                                      struct intel_connector *intel_connector)
8074 {
8075         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
8076         struct drm_device *dev = &dev_priv->drm;
8077         struct drm_connector *connector = &intel_connector->base;
8078         struct drm_display_mode *fixed_mode = NULL;
8079         struct drm_display_mode *downclock_mode = NULL;
8080         bool has_dpcd;
8081         enum pipe pipe = INVALID_PIPE;
8082         intel_wakeref_t wakeref;
8083         struct edid *edid;
8084
8085         if (!intel_dp_is_edp(intel_dp))
8086                 return true;
8087
8088         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
8089
8090         /*
8091          * On IBX/CPT we may get here with LVDS already registered. Since the
8092          * driver uses the only internal power sequencer available for both
8093          * eDP and LVDS bail out early in this case to prevent interfering
8094          * with an already powered-on LVDS power sequencer.
8095          */
8096         if (intel_get_lvds_encoder(dev_priv)) {
8097                 drm_WARN_ON(dev,
8098                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
8099                 drm_info(&dev_priv->drm,
8100                          "LVDS was detected, not registering eDP\n");
8101
8102                 return false;
8103         }
8104
8105         with_pps_lock(intel_dp, wakeref) {
8106                 intel_dp_init_panel_power_timestamps(intel_dp);
8107                 intel_dp_pps_init(intel_dp);
8108                 intel_edp_panel_vdd_sanitize(intel_dp);
8109         }
8110
8111         /* Cache DPCD and EDID for edp. */
8112         has_dpcd = intel_edp_init_dpcd(intel_dp);
8113
8114         if (!has_dpcd) {
8115                 /* if this fails, presume the device is a ghost */
8116                 drm_info(&dev_priv->drm,
8117                          "failed to retrieve link info, disabling eDP\n");
8118                 goto out_vdd_off;
8119         }
8120
8121         mutex_lock(&dev->mode_config.mutex);
8122         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
8123         if (edid) {
8124                 if (drm_add_edid_modes(connector, edid)) {
8125                         drm_connector_update_edid_property(connector, edid);
8126                         intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
8127                 } else {
8128                         kfree(edid);
8129                         edid = ERR_PTR(-EINVAL);
8130                 }
8131         } else {
8132                 edid = ERR_PTR(-ENOENT);
8133         }
8134         intel_connector->edid = edid;
8135
8136         fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
8137         if (fixed_mode)
8138                 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
8139
8140         /* fallback to VBT if available for eDP */
8141         if (!fixed_mode)
8142                 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
8143         mutex_unlock(&dev->mode_config.mutex);
8144
8145         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
8146                 /*
8147                  * Figure out the current pipe for the initial backlight setup.
8148                  * If the current pipe isn't valid, try the PPS pipe, and if that
8149                  * fails just assume pipe A.
8150                  */
8151                 pipe = vlv_active_pipe(intel_dp);
8152
8153                 if (pipe != PIPE_A && pipe != PIPE_B)
8154                         pipe = intel_dp->pps_pipe;
8155
8156                 if (pipe != PIPE_A && pipe != PIPE_B)
8157                         pipe = PIPE_A;
8158
8159                 drm_dbg_kms(&dev_priv->drm,
8160                             "using pipe %c for initial backlight setup\n",
8161                             pipe_name(pipe));
8162         }
8163
8164         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
8165         intel_connector->panel.backlight.power = intel_edp_backlight_power;
8166         intel_panel_setup_backlight(connector, pipe);
8167
8168         if (fixed_mode) {
8169                 drm_connector_set_panel_orientation_with_quirk(connector,
8170                                 dev_priv->vbt.orientation,
8171                                 fixed_mode->hdisplay, fixed_mode->vdisplay);
8172         }
8173
8174         return true;
8175
8176 out_vdd_off:
8177         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
8178         /*
8179          * vdd might still be enabled do to the delayed vdd off.
8180          * Make sure vdd is actually turned off here.
8181          */
8182         with_pps_lock(intel_dp, wakeref)
8183                 edp_panel_vdd_off_sync(intel_dp);
8184
8185         return false;
8186 }
8187
8188 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
8189 {
8190         struct intel_connector *intel_connector;
8191         struct drm_connector *connector;
8192
8193         intel_connector = container_of(work, typeof(*intel_connector),
8194                                        modeset_retry_work);
8195         connector = &intel_connector->base;
8196         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
8197                       connector->name);
8198
8199         /* Grab the locks before changing connector property*/
8200         mutex_lock(&connector->dev->mode_config.mutex);
8201         /* Set connector link status to BAD and send a Uevent to notify
8202          * userspace to do a modeset.
8203          */
8204         drm_connector_set_link_status_property(connector,
8205                                                DRM_MODE_LINK_STATUS_BAD);
8206         mutex_unlock(&connector->dev->mode_config.mutex);
8207         /* Send Hotplug uevent so userspace can reprobe */
8208         drm_kms_helper_hotplug_event(connector->dev);
8209 }
8210
8211 bool
8212 intel_dp_init_connector(struct intel_digital_port *dig_port,
8213                         struct intel_connector *intel_connector)
8214 {
8215         struct drm_connector *connector = &intel_connector->base;
8216         struct intel_dp *intel_dp = &dig_port->dp;
8217         struct intel_encoder *intel_encoder = &dig_port->base;
8218         struct drm_device *dev = intel_encoder->base.dev;
8219         struct drm_i915_private *dev_priv = to_i915(dev);
8220         enum port port = intel_encoder->port;
8221         enum phy phy = intel_port_to_phy(dev_priv, port);
8222         int type;
8223
8224         /* Initialize the work for modeset in case of link train failure */
8225         INIT_WORK(&intel_connector->modeset_retry_work,
8226                   intel_dp_modeset_retry_work_fn);
8227
8228         if (drm_WARN(dev, dig_port->max_lanes < 1,
8229                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
8230                      dig_port->max_lanes, intel_encoder->base.base.id,
8231                      intel_encoder->base.name))
8232                 return false;
8233
8234         intel_dp_set_source_rates(intel_dp);
8235
8236         intel_dp->reset_link_params = true;
8237         intel_dp->pps_pipe = INVALID_PIPE;
8238         intel_dp->active_pipe = INVALID_PIPE;
8239
8240         /* Preserve the current hw state. */
8241         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
8242         intel_dp->attached_connector = intel_connector;
8243
8244         if (intel_dp_is_port_edp(dev_priv, port)) {
8245                 /*
8246                  * Currently we don't support eDP on TypeC ports, although in
8247                  * theory it could work on TypeC legacy ports.
8248                  */
8249                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
8250                 type = DRM_MODE_CONNECTOR_eDP;
8251         } else {
8252                 type = DRM_MODE_CONNECTOR_DisplayPort;
8253         }
8254
8255         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
8256                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
8257
8258         /*
8259          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
8260          * for DP the encoder type can be set by the caller to
8261          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
8262          */
8263         if (type == DRM_MODE_CONNECTOR_eDP)
8264                 intel_encoder->type = INTEL_OUTPUT_EDP;
8265
8266         /* eDP only on port B and/or C on vlv/chv */
8267         if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
8268                               IS_CHERRYVIEW(dev_priv)) &&
8269                         intel_dp_is_edp(intel_dp) &&
8270                         port != PORT_B && port != PORT_C))
8271                 return false;
8272
8273         drm_dbg_kms(&dev_priv->drm,
8274                     "Adding %s connector on [ENCODER:%d:%s]\n",
8275                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
8276                     intel_encoder->base.base.id, intel_encoder->base.name);
8277
8278         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
8279         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
8280
8281         if (!HAS_GMCH(dev_priv))
8282                 connector->interlace_allowed = true;
8283         connector->doublescan_allowed = 0;
8284
8285         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
8286
8287         intel_dp_aux_init(intel_dp);
8288
8289         intel_connector_attach_encoder(intel_connector, intel_encoder);
8290
8291         if (HAS_DDI(dev_priv))
8292                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
8293         else
8294                 intel_connector->get_hw_state = intel_connector_get_hw_state;
8295
8296         /* init MST on ports that can support it */
8297         intel_dp_mst_encoder_init(dig_port,
8298                                   intel_connector->base.base.id);
8299
8300         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
8301                 intel_dp_aux_fini(intel_dp);
8302                 intel_dp_mst_encoder_cleanup(dig_port);
8303                 goto fail;
8304         }
8305
8306         intel_dp_add_properties(intel_dp, connector);
8307
8308         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
8309                 int ret = intel_dp_init_hdcp(dig_port, intel_connector);
8310                 if (ret)
8311                         drm_dbg_kms(&dev_priv->drm,
8312                                     "HDCP init failed, skipping.\n");
8313         }
8314
8315         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
8316          * 0xd.  Failure to do so will result in spurious interrupts being
8317          * generated on the port when a cable is not attached.
8318          */
8319         if (IS_G45(dev_priv)) {
8320                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
8321                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
8322                                (temp & ~0xf) | 0xd);
8323         }
8324
8325         intel_dp->frl.is_trained = false;
8326         intel_dp->frl.trained_rate_gbps = 0;
8327
8328         return true;
8329
8330 fail:
8331         drm_connector_cleanup(connector);
8332
8333         return false;
8334 }
8335
8336 bool intel_dp_init(struct drm_i915_private *dev_priv,
8337                    i915_reg_t output_reg,
8338                    enum port port)
8339 {
8340         struct intel_digital_port *dig_port;
8341         struct intel_encoder *intel_encoder;
8342         struct drm_encoder *encoder;
8343         struct intel_connector *intel_connector;
8344
8345         dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
8346         if (!dig_port)
8347                 return false;
8348
8349         intel_connector = intel_connector_alloc();
8350         if (!intel_connector)
8351                 goto err_connector_alloc;
8352
8353         intel_encoder = &dig_port->base;
8354         encoder = &intel_encoder->base;
8355
8356         mutex_init(&dig_port->hdcp_mutex);
8357
8358         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
8359                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
8360                              "DP %c", port_name(port)))
8361                 goto err_encoder_init;
8362
8363         intel_encoder->hotplug = intel_dp_hotplug;
8364         intel_encoder->compute_config = intel_dp_compute_config;
8365         intel_encoder->get_hw_state = intel_dp_get_hw_state;
8366         intel_encoder->get_config = intel_dp_get_config;
8367         intel_encoder->sync_state = intel_dp_sync_state;
8368         intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
8369         intel_encoder->update_pipe = intel_panel_update_backlight;
8370         intel_encoder->suspend = intel_dp_encoder_suspend;
8371         intel_encoder->shutdown = intel_dp_encoder_shutdown;
8372         if (IS_CHERRYVIEW(dev_priv)) {
8373                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
8374                 intel_encoder->pre_enable = chv_pre_enable_dp;
8375                 intel_encoder->enable = vlv_enable_dp;
8376                 intel_encoder->disable = vlv_disable_dp;
8377                 intel_encoder->post_disable = chv_post_disable_dp;
8378                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
8379         } else if (IS_VALLEYVIEW(dev_priv)) {
8380                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
8381                 intel_encoder->pre_enable = vlv_pre_enable_dp;
8382                 intel_encoder->enable = vlv_enable_dp;
8383                 intel_encoder->disable = vlv_disable_dp;
8384                 intel_encoder->post_disable = vlv_post_disable_dp;
8385         } else {
8386                 intel_encoder->pre_enable = g4x_pre_enable_dp;
8387                 intel_encoder->enable = g4x_enable_dp;
8388                 intel_encoder->disable = g4x_disable_dp;
8389                 intel_encoder->post_disable = g4x_post_disable_dp;
8390         }
8391
8392         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
8393             (HAS_PCH_CPT(dev_priv) && port != PORT_A))
8394                 dig_port->dp.set_link_train = cpt_set_link_train;
8395         else
8396                 dig_port->dp.set_link_train = g4x_set_link_train;
8397
8398         if (IS_CHERRYVIEW(dev_priv))
8399                 dig_port->dp.set_signal_levels = chv_set_signal_levels;
8400         else if (IS_VALLEYVIEW(dev_priv))
8401                 dig_port->dp.set_signal_levels = vlv_set_signal_levels;
8402         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
8403                 dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels;
8404         else if (IS_GEN(dev_priv, 6) && port == PORT_A)
8405                 dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels;
8406         else
8407                 dig_port->dp.set_signal_levels = g4x_set_signal_levels;
8408
8409         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
8410             (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
8411                 dig_port->dp.preemph_max = intel_dp_preemph_max_3;
8412                 dig_port->dp.voltage_max = intel_dp_voltage_max_3;
8413         } else {
8414                 dig_port->dp.preemph_max = intel_dp_preemph_max_2;
8415                 dig_port->dp.voltage_max = intel_dp_voltage_max_2;
8416         }
8417
8418         dig_port->dp.output_reg = output_reg;
8419         dig_port->max_lanes = 4;
8420
8421         intel_encoder->type = INTEL_OUTPUT_DP;
8422         intel_encoder->power_domain = intel_port_to_power_domain(port);
8423         if (IS_CHERRYVIEW(dev_priv)) {
8424                 if (port == PORT_D)
8425                         intel_encoder->pipe_mask = BIT(PIPE_C);
8426                 else
8427                         intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
8428         } else {
8429                 intel_encoder->pipe_mask = ~0;
8430         }
8431         intel_encoder->cloneable = 0;
8432         intel_encoder->port = port;
8433         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
8434
8435         dig_port->hpd_pulse = intel_dp_hpd_pulse;
8436
8437         if (HAS_GMCH(dev_priv)) {
8438                 if (IS_GM45(dev_priv))
8439                         dig_port->connected = gm45_digital_port_connected;
8440                 else
8441                         dig_port->connected = g4x_digital_port_connected;
8442         } else {
8443                 if (port == PORT_A)
8444                         dig_port->connected = ilk_digital_port_connected;
8445                 else
8446                         dig_port->connected = ibx_digital_port_connected;
8447         }
8448
8449         if (port != PORT_A)
8450                 intel_infoframe_init(dig_port);
8451
8452         dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
8453         if (!intel_dp_init_connector(dig_port, intel_connector))
8454                 goto err_init_connector;
8455
8456         return true;
8457
8458 err_init_connector:
8459         drm_encoder_cleanup(encoder);
8460 err_encoder_init:
8461         kfree(intel_connector);
8462 err_connector_alloc:
8463         kfree(dig_port);
8464         return false;
8465 }
8466
8467 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
8468 {
8469         struct intel_encoder *encoder;
8470
8471         for_each_intel_encoder(&dev_priv->drm, encoder) {
8472                 struct intel_dp *intel_dp;
8473
8474                 if (encoder->type != INTEL_OUTPUT_DDI)
8475                         continue;
8476
8477                 intel_dp = enc_to_intel_dp(encoder);
8478
8479                 if (!intel_dp->can_mst)
8480                         continue;
8481
8482                 if (intel_dp->is_mst)
8483                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
8484         }
8485 }
8486
8487 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
8488 {
8489         struct intel_encoder *encoder;
8490
8491         for_each_intel_encoder(&dev_priv->drm, encoder) {
8492                 struct intel_dp *intel_dp;
8493                 int ret;
8494
8495                 if (encoder->type != INTEL_OUTPUT_DDI)
8496                         continue;
8497
8498                 intel_dp = enc_to_intel_dp(encoder);
8499
8500                 if (!intel_dp->can_mst)
8501                         continue;
8502
8503                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
8504                                                      true);
8505                 if (ret) {
8506                         intel_dp->is_mst = false;
8507                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
8508                                                         false);
8509                 }
8510         }
8511 }