drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/slab.h>
  32 #include <linux/types.h>
  33
  34 #include <asm/byteorder.h>
  35
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_dp_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_probe_helper.h>
  41
  42 #include "i915_debugfs.h"
  43 #include "i915_drv.h"
  44 #include "i915_trace.h"
  45 #include "intel_atomic.h"
  46 #include "intel_audio.h"
  47 #include "intel_connector.h"
  48 #include "intel_ddi.h"
  49 #include "intel_display_types.h"
  50 #include "intel_dp.h"
  51 #include "intel_dp_link_training.h"
  52 #include "intel_dp_mst.h"
  53 #include "intel_dpio_phy.h"
  54 #include "intel_fifo_underrun.h"
  55 #include "intel_hdcp.h"
  56 #include "intel_hdmi.h"
  57 #include "intel_hotplug.h"
  58 #include "intel_lspcon.h"
  59 #include "intel_lvds.h"
  60 #include "intel_panel.h"
  61 #include "intel_psr.h"
  62 #include "intel_sideband.h"
  63 #include "intel_tc.h"
  64 #include "intel_vdsc.h"
  65
  66 #define DP_DPRX_ESI_LEN 14
  67
  68 /* DP DSC throughput values used for slice count calculations KPixels/s */
  69 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  70 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  71 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  72
  73 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  74 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  75
  76 /* Compliance test status bits  */
  77 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  78 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  79 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  80 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  81
  82 struct dp_link_dpll {
  83         int clock;
  84         struct dpll dpll;
  85 };
  86
  87 static const struct dp_link_dpll g4x_dpll[] = {
  88         { 162000,
  89                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  90         { 270000,
  91                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  92 };
  93
  94 static const struct dp_link_dpll pch_dpll[] = {
  95         { 162000,
  96                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  97         { 270000,
  98                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  99 };
 100
 101 static const struct dp_link_dpll vlv_dpll[] = {
 102         { 162000,
 103                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
 104         { 270000,
 105                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
 106 };
 107
 108 /*
 109  * CHV supports eDP 1.4 that have  more link rates.
 110  * Below only provides the fixed rate but exclude variable rate.
 111  */
 112 static const struct dp_link_dpll chv_dpll[] = {
 113         /*
 114          * CHV requires to program fractional division for m2.
 115          * m2 is stored in fixed point format using formula below
 116          * (m2_int << 22) | m2_fraction
 117          */
 118         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
 119                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
 120         { 270000,       /* m2_int = 27, m2_fraction = 0 */
 121                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
 122 };
 123
 124 /* Constants for DP DSC configurations */
 125 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 126
 127 /* With Single pipe configuration, HW is capable of supporting maximum
 128  * of 4 slices per line.
 129  */
 130 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 131
 132 /**
 133  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 134  * @intel_dp: DP struct
 135  *
 136  * If a CPU or PCH DP output is attached to an eDP panel, this function
 137  * will return true, and false otherwise.
 138  */
 139 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 140 {
 141         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 142
 143         return dig_port->base.type == INTEL_OUTPUT_EDP;
 144 }
 145
 146 static void intel_dp_link_down(struct intel_encoder *encoder,
 147                                const struct intel_crtc_state *old_crtc_state);
 148 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 149 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 150 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 151                                            const struct intel_crtc_state *crtc_state);
 152 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 153                                       enum pipe pipe);
 154 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 155
 156 /* update sink rates from dpcd */
 157 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 158 {
 159         static const int dp_rates[] = {
 160                 162000, 270000, 540000, 810000
 161         };
 162         int i, max_rate;
 163         int max_lttpr_rate;
 164
 165         if (drm_dp_has_quirk(&intel_dp->desc, 0,
 166                              DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 167                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 168                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 169
 170                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 171                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 172
 173                 return;
 174         }
 175
 176         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 177         max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 178         if (max_lttpr_rate)
 179                 max_rate = min(max_rate, max_lttpr_rate);
 180
 181         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 182                 if (dp_rates[i] > max_rate)
 183                         break;
 184                 intel_dp->sink_rates[i] = dp_rates[i];
 185         }
 186
 187         intel_dp->num_sink_rates = i;
 188 }
 189
 190 /* Get length of rates array potentially limited by max_rate. */
 191 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 192 {
 193         int i;
 194
 195         /* Limit results by potentially reduced max rate */
 196         for (i = 0; i < len; i++) {
 197                 if (rates[len - i - 1] <= max_rate)
 198                         return len - i;
 199         }
 200
 201         return 0;
 202 }
 203
 204 /* Get length of common rates array potentially limited by max_rate. */
 205 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 206                                           int max_rate)
 207 {
 208         return intel_dp_rate_limit_len(intel_dp->common_rates,
 209                                        intel_dp->num_common_rates, max_rate);
 210 }
 211
 212 /* Theoretical max between source and sink */
 213 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 214 {
 215         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 216 }
 217
 218 /* Theoretical max between source and sink */
 219 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 220 {
 221         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 222         int source_max = dig_port->max_lanes;
 223         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 224         int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
 225         int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 226
 227         if (lttpr_max)
 228                 sink_max = min(sink_max, lttpr_max);
 229
 230         return min3(source_max, sink_max, fia_max);
 231 }
 232
 233 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 234 {
 235         return intel_dp->max_link_lane_count;
 236 }
 237
 238 int
 239 intel_dp_link_required(int pixel_clock, int bpp)
 240 {
 241         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 242         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 243 }
 244
 245 int
 246 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 247 {
 248         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 249          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 250          * is transmitted every LS_Clk per lane, there is no need to account for
 251          * the channel encoding that is done in the PHY layer here.
 252          */
 253
 254         return max_link_clock * max_lanes;
 255 }
 256
 257 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 258 {
 259         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 260         struct intel_encoder *encoder = &intel_dig_port->base;
 261         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 262
 263         return INTEL_GEN(dev_priv) >= 12 ||
 264                 (INTEL_GEN(dev_priv) == 11 &&
 265                  encoder->port != PORT_A);
 266 }
 267
 268 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 269 {
 270         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 271         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 272         enum port port = dig_port->base.port;
 273
 274         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 275
 276         /* Low voltage SKUs are limited to max of 5.4G */
 277         if (voltage == VOLTAGE_INFO_0_85V)
 278                 return 540000;
 279
 280         /* For this SKU 8.1G is supported in all ports */
 281         if (IS_CNL_WITH_PORT_F(dev_priv))
 282                 return 810000;
 283
 284         /* For other SKUs, max rate on ports A and D is 5.4G */
 285         if (port == PORT_A || port == PORT_D)
 286                 return 540000;
 287
 288         return 810000;
 289 }
 290
 291 static int icl_max_source_rate(struct intel_dp *intel_dp)
 292 {
 293         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 294         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 295         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 296
 297         if (intel_phy_is_combo(dev_priv, phy) &&
 298             !intel_dp_is_edp(intel_dp))
 299                 return 540000;
 300
 301         return 810000;
 302 }
 303
 304 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 305 {
 306         if (intel_dp_is_edp(intel_dp))
 307                 return 540000;
 308
 309         return 810000;
 310 }
 311
 312 static void
 313 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 314 {
 315         /* The values must be in increasing order */
 316         static const int cnl_rates[] = {
 317                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 318         };
 319         static const int bxt_rates[] = {
 320                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 321         };
 322         static const int skl_rates[] = {
 323                 162000, 216000, 270000, 324000, 432000, 540000
 324         };
 325         static const int hsw_rates[] = {
 326                 162000, 270000, 540000
 327         };
 328         static const int g4x_rates[] = {
 329                 162000, 270000
 330         };
 331         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 332         struct intel_encoder *encoder = &dig_port->base;
 333         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 334         const int *source_rates;
 335         int size, max_rate = 0, vbt_max_rate;
 336
 337         /* This should only be done once */
 338         drm_WARN_ON(&dev_priv->drm,
 339                     intel_dp->source_rates || intel_dp->num_source_rates);
 340
 341         if (INTEL_GEN(dev_priv) >= 10) {
 342                 source_rates = cnl_rates;
 343                 size = ARRAY_SIZE(cnl_rates);
 344                 if (IS_GEN(dev_priv, 10))
 345                         max_rate = cnl_max_source_rate(intel_dp);
 346                 else if (IS_JSL_EHL(dev_priv))
 347                         max_rate = ehl_max_source_rate(intel_dp);
 348                 else
 349                         max_rate = icl_max_source_rate(intel_dp);
 350         } else if (IS_GEN9_LP(dev_priv)) {
 351                 source_rates = bxt_rates;
 352                 size = ARRAY_SIZE(bxt_rates);
 353         } else if (IS_GEN9_BC(dev_priv)) {
 354                 source_rates = skl_rates;
 355                 size = ARRAY_SIZE(skl_rates);
 356         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 357                    IS_BROADWELL(dev_priv)) {
 358                 source_rates = hsw_rates;
 359                 size = ARRAY_SIZE(hsw_rates);
 360         } else {
 361                 source_rates = g4x_rates;
 362                 size = ARRAY_SIZE(g4x_rates);
 363         }
 364
 365         vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
 366         if (max_rate && vbt_max_rate)
 367                 max_rate = min(max_rate, vbt_max_rate);
 368         else if (vbt_max_rate)
 369                 max_rate = vbt_max_rate;
 370
 371         if (max_rate)
 372                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 373
 374         intel_dp->source_rates = source_rates;
 375         intel_dp->num_source_rates = size;
 376 }
 377
 378 static int intersect_rates(const int *source_rates, int source_len,
 379                            const int *sink_rates, int sink_len,
 380                            int *common_rates)
 381 {
 382         int i = 0, j = 0, k = 0;
 383
 384         while (i < source_len && j < sink_len) {
 385                 if (source_rates[i] == sink_rates[j]) {
 386                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 387                                 return k;
 388                         common_rates[k] = source_rates[i];
 389                         ++k;
 390                         ++i;
 391                         ++j;
 392                 } else if (source_rates[i] < sink_rates[j]) {
 393                         ++i;
 394                 } else {
 395                         ++j;
 396                 }
 397         }
 398         return k;
 399 }
 400
 401 /* return index of rate in rates array, or -1 if not found */
 402 static int intel_dp_rate_index(const int *rates, int len, int rate)
 403 {
 404         int i;
 405
 406         for (i = 0; i < len; i++)
 407                 if (rate == rates[i])
 408                         return i;
 409
 410         return -1;
 411 }
 412
 413 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 414 {
 415         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 416
 417         drm_WARN_ON(&i915->drm,
 418                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 419
 420         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 421                                                      intel_dp->num_source_rates,
 422                                                      intel_dp->sink_rates,
 423                                                      intel_dp->num_sink_rates,
 424                                                      intel_dp->common_rates);
 425
 426         /* Paranoia, there should always be something in common. */
 427         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 428                 intel_dp->common_rates[0] = 162000;
 429                 intel_dp->num_common_rates = 1;
 430         }
 431 }
 432
 433 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 434                                        u8 lane_count)
 435 {
 436         /*
 437          * FIXME: we need to synchronize the current link parameters with
 438          * hardware readout. Currently fast link training doesn't work on
 439          * boot-up.
 440          */
 441         if (link_rate == 0 ||
 442             link_rate > intel_dp->max_link_rate)
 443                 return false;
 444
 445         if (lane_count == 0 ||
 446             lane_count > intel_dp_max_lane_count(intel_dp))
 447                 return false;
 448
 449         return true;
 450 }
 451
 452 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 453                                                      int link_rate,
 454                                                      u8 lane_count)
 455 {
 456         const struct drm_display_mode *fixed_mode =
 457                 intel_dp->attached_connector->panel.fixed_mode;
 458         int mode_rate, max_rate;
 459
 460         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 461         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 462         if (mode_rate > max_rate)
 463                 return false;
 464
 465         return true;
 466 }
 467
 468 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 469                                             int link_rate, u8 lane_count)
 470 {
 471         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 472         int index;
 473
 474         /*
 475          * TODO: Enable fallback on MST links once MST link compute can handle
 476          * the fallback params.
 477          */
 478         if (intel_dp->is_mst) {
 479                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 480                 return -1;
 481         }
 482
 483         index = intel_dp_rate_index(intel_dp->common_rates,
 484                                     intel_dp->num_common_rates,
 485                                     link_rate);
 486         if (index > 0) {
 487                 if (intel_dp_is_edp(intel_dp) &&
 488                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 489                                                               intel_dp->common_rates[index - 1],
 490                                                               lane_count)) {
 491                         drm_dbg_kms(&i915->drm,
 492                                     "Retrying Link training for eDP with same parameters\n");
 493                         return 0;
 494                 }
 495                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 496                 intel_dp->max_link_lane_count = lane_count;
 497         } else if (lane_count > 1) {
 498                 if (intel_dp_is_edp(intel_dp) &&
 499                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 500                                                               intel_dp_max_common_rate(intel_dp),
 501                                                               lane_count >> 1)) {
 502                         drm_dbg_kms(&i915->drm,
 503                                     "Retrying Link training for eDP with same parameters\n");
 504                         return 0;
 505                 }
 506                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 507                 intel_dp->max_link_lane_count = lane_count >> 1;
 508         } else {
 509                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 510                 return -1;
 511         }
 512
 513         return 0;
 514 }
 515
 516 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 517 {
 518         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 519                        DP_DSC_FEC_OVERHEAD_FACTOR);
 520 }
 521
 522 static int
 523 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 524 {
 525         if (INTEL_GEN(i915) >= 11)
 526                 return 7680 * 8;
 527         else
 528                 return 6144 * 8;
 529 }
 530
 531 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 532                                        u32 link_clock, u32 lane_count,
 533                                        u32 mode_clock, u32 mode_hdisplay,
 534                                        bool bigjoiner)
 535 {
 536         u32 bits_per_pixel, max_bpp_small_joiner_ram;
 537         int i;
 538
 539         /*
 540          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 541          * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
 542          * for SST -> TimeSlotsPerMTP is 1,
 543          * for MST -> TimeSlotsPerMTP has to be calculated
 544          */
 545         bits_per_pixel = (link_clock * lane_count * 8) /
 546                          intel_dp_mode_to_fec_clock(mode_clock);
 547         drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
 548
 549         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 550         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 551                 mode_hdisplay;
 552
 553         if (bigjoiner)
 554                 max_bpp_small_joiner_ram *= 2;
 555
 556         drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
 557                     max_bpp_small_joiner_ram);
 558
 559         /*
 560          * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 561          * check, output bpp from small joiner RAM check)
 562          */
 563         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 564
 565         if (bigjoiner) {
 566                 u32 max_bpp_bigjoiner =
 567                         i915->max_cdclk_freq * 48 /
 568                         intel_dp_mode_to_fec_clock(mode_clock);
 569
 570                 DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
 571                 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
 572         }
 573
 574         /* Error out if the max bpp is less than smallest allowed valid bpp */
 575         if (bits_per_pixel < valid_dsc_bpp[0]) {
 576                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 577                             bits_per_pixel, valid_dsc_bpp[0]);
 578                 return 0;
 579         }
 580
 581         /* Find the nearest match in the array of known BPPs from VESA */
 582         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 583                 if (bits_per_pixel < valid_dsc_bpp[i + 1])
 584                         break;
 585         }
 586         bits_per_pixel = valid_dsc_bpp[i];
 587
 588         /*
 589          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 590          * fractional part is 0
 591          */
 592         return bits_per_pixel << 4;
 593 }
 594
 595 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 596                                        int mode_clock, int mode_hdisplay,
 597                                        bool bigjoiner)
 598 {
 599         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 600         u8 min_slice_count, i;
 601         int max_slice_width;
 602
 603         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 604                 min_slice_count = DIV_ROUND_UP(mode_clock,
 605                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 606         else
 607                 min_slice_count = DIV_ROUND_UP(mode_clock,
 608                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 609
 610         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 611         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 612                 drm_dbg_kms(&i915->drm,
 613                             "Unsupported slice width %d by DP DSC Sink device\n",
 614                             max_slice_width);
 615                 return 0;
 616         }
 617         /* Also take into account max slice width */
 618         min_slice_count = min_t(u8, min_slice_count,
 619                                 DIV_ROUND_UP(mode_hdisplay,
 620                                              max_slice_width));
 621
 622         /* Find the closest match to the valid slice count values */
 623         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 624                 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 625
 626                 if (test_slice_count >
 627                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
 628                         break;
 629
 630                 /* big joiner needs small joiner to be enabled */
 631                 if (bigjoiner && test_slice_count < 4)
 632                         continue;
 633
 634                 if (min_slice_count <= test_slice_count)
 635                         return test_slice_count;
 636         }
 637
 638         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 639                     min_slice_count);
 640         return 0;
 641 }
 642
 643 static enum intel_output_format
 644 intel_dp_output_format(struct drm_connector *connector,
 645                        const struct drm_display_mode *mode)
 646 {
 647         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 648         const struct drm_display_info *info = &connector->display_info;
 649
 650         if (!connector->ycbcr_420_allowed ||
 651             !drm_mode_is_420_only(info, mode))
 652                 return INTEL_OUTPUT_FORMAT_RGB;
 653
 654         if (intel_dp->dfp.ycbcr_444_to_420)
 655                 return INTEL_OUTPUT_FORMAT_YCBCR444;
 656         else
 657                 return INTEL_OUTPUT_FORMAT_YCBCR420;
 658 }
 659
 660 int intel_dp_min_bpp(enum intel_output_format output_format)
 661 {
 662         if (output_format == INTEL_OUTPUT_FORMAT_RGB)
 663                 return 6 * 3;
 664         else
 665                 return 8 * 3;
 666 }
 667
 668 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
 669 {
 670         /*
 671          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
 672          * format of the number of bytes per pixel will be half the number
 673          * of bytes of RGB pixel.
 674          */
 675         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 676                 bpp /= 2;
 677
 678         return bpp;
 679 }
 680
 681 static int
 682 intel_dp_mode_min_output_bpp(struct drm_connector *connector,
 683                              const struct drm_display_mode *mode)
 684 {
 685         enum intel_output_format output_format =
 686                 intel_dp_output_format(connector, mode);
 687
 688         return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
 689 }
 690
 691 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 692                                   int hdisplay)
 693 {
 694         /*
 695          * Older platforms don't like hdisplay==4096 with DP.
 696          *
 697          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
 698          * and frame counter increment), but we don't get vblank interrupts,
 699          * and the pipe underruns immediately. The link also doesn't seem
 700          * to get trained properly.
 701          *
 702          * On CHV the vblank interrupts don't seem to disappear but
 703          * otherwise the symptoms are similar.
 704          *
 705          * TODO: confirm the behaviour on HSW+
 706          */
 707         return hdisplay == 4096 && !HAS_DDI(dev_priv);
 708 }
 709
 710 static enum drm_mode_status
 711 intel_dp_mode_valid_downstream(struct intel_connector *connector,
 712                                const struct drm_display_mode *mode,
 713                                int target_clock)
 714 {
 715         struct intel_dp *intel_dp = intel_attached_dp(connector);
 716         const struct drm_display_info *info = &connector->base.display_info;
 717         int tmds_clock;
 718
 719         /* If PCON supports FRL MODE, check FRL bandwidth constraints */
 720         if (intel_dp->dfp.pcon_max_frl_bw) {
 721                 int target_bw;
 722                 int max_frl_bw;
 723                 int bpp = intel_dp_mode_min_output_bpp(&connector->base, mode);
 724
 725                 target_bw = bpp * target_clock;
 726
 727                 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
 728
 729                 /* converting bw from Gbps to Kbps*/
 730                 max_frl_bw = max_frl_bw * 1000000;
 731
 732                 if (target_bw > max_frl_bw)
 733                         return MODE_CLOCK_HIGH;
 734
 735                 return MODE_OK;
 736         }
 737
 738         if (intel_dp->dfp.max_dotclock &&
 739             target_clock > intel_dp->dfp.max_dotclock)
 740                 return MODE_CLOCK_HIGH;
 741
 742         /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
 743         tmds_clock = target_clock;
 744         if (drm_mode_is_420_only(info, mode))
 745                 tmds_clock /= 2;
 746
 747         if (intel_dp->dfp.min_tmds_clock &&
 748             tmds_clock < intel_dp->dfp.min_tmds_clock)
 749                 return MODE_CLOCK_LOW;
 750         if (intel_dp->dfp.max_tmds_clock &&
 751             tmds_clock > intel_dp->dfp.max_tmds_clock)
 752                 return MODE_CLOCK_HIGH;
 753
 754         return MODE_OK;
 755 }
 756
 757 static enum drm_mode_status
 758 intel_dp_mode_valid(struct drm_connector *connector,
 759                     struct drm_display_mode *mode)
 760 {
 761         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 762         struct intel_connector *intel_connector = to_intel_connector(connector);
 763         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 764         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 765         int target_clock = mode->clock;
 766         int max_rate, mode_rate, max_lanes, max_link_clock;
 767         int max_dotclk = dev_priv->max_dotclk_freq;
 768         u16 dsc_max_output_bpp = 0;
 769         u8 dsc_slice_count = 0;
 770         enum drm_mode_status status;
 771         bool dsc = false, bigjoiner = false;
 772
 773         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 774                 return MODE_NO_DBLESCAN;
 775
 776         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 777                 return MODE_H_ILLEGAL;
 778
 779         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 780                 if (mode->hdisplay > fixed_mode->hdisplay)
 781                         return MODE_PANEL;
 782
 783                 if (mode->vdisplay > fixed_mode->vdisplay)
 784                         return MODE_PANEL;
 785
 786                 target_clock = fixed_mode->clock;
 787         }
 788
 789         if (mode->clock < 10000)
 790                 return MODE_CLOCK_LOW;
 791
 792         if ((target_clock > max_dotclk || mode->hdisplay > 5120) &&
 793             intel_dp_can_bigjoiner(intel_dp)) {
 794                 bigjoiner = true;
 795                 max_dotclk *= 2;
 796         }
 797         if (target_clock > max_dotclk)
 798                 return MODE_CLOCK_HIGH;
 799
 800         max_link_clock = intel_dp_max_link_rate(intel_dp);
 801         max_lanes = intel_dp_max_lane_count(intel_dp);
 802
 803         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 804         mode_rate = intel_dp_link_required(target_clock,
 805                                            intel_dp_mode_min_output_bpp(connector, mode));
 806
 807         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
 808                 return MODE_H_ILLEGAL;
 809
 810         /*
 811          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 812          * integer value since we support only integer values of bpp.
 813          */
 814         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
 815             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 816                 if (intel_dp_is_edp(intel_dp)) {
 817                         dsc_max_output_bpp =
 818                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 819                         dsc_slice_count =
 820                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 821                                                                 true);
 822                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 823                         dsc_max_output_bpp =
 824                                 intel_dp_dsc_get_output_bpp(dev_priv,
 825                                                             max_link_clock,
 826                                                             max_lanes,
 827                                                             target_clock,
 828                                                             mode->hdisplay,
 829                                                             bigjoiner) >> 4;
 830                         dsc_slice_count =
 831                                 intel_dp_dsc_get_slice_count(intel_dp,
 832                                                              target_clock,
 833                                                              mode->hdisplay,
 834                                                              bigjoiner);
 835                 }
 836
 837                 dsc = dsc_max_output_bpp && dsc_slice_count;
 838         }
 839
 840         /* big joiner configuration needs DSC */
 841         if (bigjoiner && !dsc)
 842                 return MODE_CLOCK_HIGH;
 843
 844         if (mode_rate > max_rate && !dsc)
 845                 return MODE_CLOCK_HIGH;
 846
 847         status = intel_dp_mode_valid_downstream(intel_connector,
 848                                                 mode, target_clock);
 849         if (status != MODE_OK)
 850                 return status;
 851
 852         return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
 853 }
 854
 855 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
 856 {
 857         int i;
 858         u32 v = 0;
 859
 860         if (src_bytes > 4)
 861                 src_bytes = 4;
 862         for (i = 0; i < src_bytes; i++)
 863                 v |= ((u32)src[i]) << ((3 - i) * 8);
 864         return v;
 865 }
 866
 867 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
 868 {
 869         int i;
 870         if (dst_bytes > 4)
 871                 dst_bytes = 4;
 872         for (i = 0; i < dst_bytes; i++)
 873                 dst[i] = src >> ((3-i) * 8);
 874 }
 875
 876 static void
 877 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 878 static void
 879 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 880                                               bool force_disable_vdd);
 881 static void
 882 intel_dp_pps_init(struct intel_dp *intel_dp);
 883
 884 static intel_wakeref_t
 885 pps_lock(struct intel_dp *intel_dp)
 886 {
 887         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 888         intel_wakeref_t wakeref;
 889
 890         /*
 891          * See intel_power_sequencer_reset() why we need
 892          * a power domain reference here.
 893          */
 894         wakeref = intel_display_power_get(dev_priv,
 895                                           intel_aux_power_domain(dp_to_dig_port(intel_dp)));
 896
 897         mutex_lock(&dev_priv->pps_mutex);
 898
 899         return wakeref;
 900 }
 901
 902 static intel_wakeref_t
 903 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
 904 {
 905         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 906
 907         mutex_unlock(&dev_priv->pps_mutex);
 908         intel_display_power_put(dev_priv,
 909                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
 910                                 wakeref);
 911         return 0;
 912 }
 913
 914 #define with_pps_lock(dp, wf) \
 915         for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
 916
 917 static void
 918 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 919 {
 920         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 921         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 922         enum pipe pipe = intel_dp->pps_pipe;
 923         bool pll_enabled, release_cl_override = false;
 924         enum dpio_phy phy = DPIO_PHY(pipe);
 925         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 926         u32 DP;
 927
 928         if (drm_WARN(&dev_priv->drm,
 929                      intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
 930                      "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
 931                      pipe_name(pipe), dig_port->base.base.base.id,
 932                      dig_port->base.base.name))
 933                 return;
 934
 935         drm_dbg_kms(&dev_priv->drm,
 936                     "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
 937                     pipe_name(pipe), dig_port->base.base.base.id,
 938                     dig_port->base.base.name);
 939
 940         /* Preserve the BIOS-computed detected bit. This is
 941          * supposed to be read-only.
 942          */
 943         DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
 944         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 945         DP |= DP_PORT_WIDTH(1);
 946         DP |= DP_LINK_TRAIN_PAT_1;
 947
 948         if (IS_CHERRYVIEW(dev_priv))
 949                 DP |= DP_PIPE_SEL_CHV(pipe);
 950         else
 951                 DP |= DP_PIPE_SEL(pipe);
 952
 953         pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
 954
 955         /*
 956          * The DPLL for the pipe must be enabled for this to work.
 957          * So enable temporarily it if it's not already enabled.
 958          */
 959         if (!pll_enabled) {
 960                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 961                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 962
 963                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 964                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 965                         drm_err(&dev_priv->drm,
 966                                 "Failed to force on pll for pipe %c!\n",
 967                                 pipe_name(pipe));
 968                         return;
 969                 }
 970         }
 971
 972         /*
 973          * Similar magic as in intel_dp_enable_port().
 974          * We _must_ do this port enable + disable trick
 975          * to make this power sequencer lock onto the port.
 976          * Otherwise even VDD force bit won't work.
 977          */
 978         intel_de_write(dev_priv, intel_dp->output_reg, DP);
 979         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 980
 981         intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
 982         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 983
 984         intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN);
 985         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 986
 987         if (!pll_enabled) {
 988                 vlv_force_pll_off(dev_priv, pipe);
 989
 990                 if (release_cl_override)
 991                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 992         }
 993 }
 994
 995 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 996 {
 997         struct intel_encoder *encoder;
 998         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 999
1000         /*
1001          * We don't have power sequencer currently.
1002          * Pick one that's not used by other ports.
1003          */
1004         for_each_intel_dp(&dev_priv->drm, encoder) {
1005                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1006
1007                 if (encoder->type == INTEL_OUTPUT_EDP) {
1008                         drm_WARN_ON(&dev_priv->drm,
1009                                     intel_dp->active_pipe != INVALID_PIPE &&
1010                                     intel_dp->active_pipe !=
1011                                     intel_dp->pps_pipe);
1012
1013                         if (intel_dp->pps_pipe != INVALID_PIPE)
1014                                 pipes &= ~(1 << intel_dp->pps_pipe);
1015                 } else {
1016                         drm_WARN_ON(&dev_priv->drm,
1017                                     intel_dp->pps_pipe != INVALID_PIPE);
1018
1019                         if (intel_dp->active_pipe != INVALID_PIPE)
1020                                 pipes &= ~(1 << intel_dp->active_pipe);
1021                 }
1022         }
1023
1024         if (pipes == 0)
1025                 return INVALID_PIPE;
1026
1027         return ffs(pipes) - 1;
1028 }
1029
1030 static enum pipe
1031 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
1032 {
1033         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1034         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1035         enum pipe pipe;
1036
1037         lockdep_assert_held(&dev_priv->pps_mutex);
1038
1039         /* We should never land here with regular DP ports */
1040         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
1041
1042         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&
1043                     intel_dp->active_pipe != intel_dp->pps_pipe);
1044
1045         if (intel_dp->pps_pipe != INVALID_PIPE)
1046                 return intel_dp->pps_pipe;
1047
1048         pipe = vlv_find_free_pps(dev_priv);
1049
1050         /*
1051          * Didn't find one. This should not happen since there
1052          * are two power sequencers and up to two eDP ports.
1053          */
1054         if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
1055                 pipe = PIPE_A;
1056
1057         vlv_steal_power_sequencer(dev_priv, pipe);
1058         intel_dp->pps_pipe = pipe;
1059
1060         drm_dbg_kms(&dev_priv->drm,
1061                     "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
1062                     pipe_name(intel_dp->pps_pipe),
1063                     dig_port->base.base.base.id,
1064                     dig_port->base.base.name);
1065
1066         /* init power sequencer on this pipe and port */
1067         intel_dp_init_panel_power_sequencer(intel_dp);
1068         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
1069
1070         /*
1071          * Even vdd force doesn't work until we've made
1072          * the power sequencer lock in on the port.
1073          */
1074         vlv_power_sequencer_kick(intel_dp);
1075
1076         return intel_dp->pps_pipe;
1077 }
1078
1079 static int
1080 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
1081 {
1082         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1083         int backlight_controller = dev_priv->vbt.backlight.controller;
1084
1085         lockdep_assert_held(&dev_priv->pps_mutex);
1086
1087         /* We should never land here with regular DP ports */
1088         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
1089
1090         if (!intel_dp->pps_reset)
1091                 return backlight_controller;
1092
1093         intel_dp->pps_reset = false;
1094
1095         /*
1096          * Only the HW needs to be reprogrammed, the SW state is fixed and
1097          * has been setup during connector init.
1098          */
1099         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1100
1101         return backlight_controller;
1102 }
1103
1104 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
1105                                enum pipe pipe);
1106
1107 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
1108                                enum pipe pipe)
1109 {
1110         return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON;
1111 }
1112
1113 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
1114                                 enum pipe pipe)
1115 {
1116         return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD;
1117 }
1118
1119 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
1120                          enum pipe pipe)
1121 {
1122         return true;
1123 }
1124
1125 static enum pipe
1126 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
1127                      enum port port,
1128                      vlv_pipe_check pipe_check)
1129 {
1130         enum pipe pipe;
1131
1132         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
1133                 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
1134                         PANEL_PORT_SELECT_MASK;
1135
1136                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
1137                         continue;
1138
1139                 if (!pipe_check(dev_priv, pipe))
1140                         continue;
1141
1142                 return pipe;
1143         }
1144
1145         return INVALID_PIPE;
1146 }
1147
1148 static void
1149 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
1150 {
1151         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1152         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1153         enum port port = dig_port->base.port;
1154
1155         lockdep_assert_held(&dev_priv->pps_mutex);
1156
1157         /* try to find a pipe with this port selected */
1158         /* first pick one where the panel is on */
1159         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1160                                                   vlv_pipe_has_pp_on);
1161         /* didn't find one? pick one where vdd is on */
1162         if (intel_dp->pps_pipe == INVALID_PIPE)
1163                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1164                                                           vlv_pipe_has_vdd_on);
1165         /* didn't find one? pick one with just the correct port */
1166         if (intel_dp->pps_pipe == INVALID_PIPE)
1167                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1168                                                           vlv_pipe_any);
1169
1170         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
1171         if (intel_dp->pps_pipe == INVALID_PIPE) {
1172                 drm_dbg_kms(&dev_priv->drm,
1173                             "no initial power sequencer for [ENCODER:%d:%s]\n",
1174                             dig_port->base.base.base.id,
1175                             dig_port->base.base.name);
1176                 return;
1177         }
1178
1179         drm_dbg_kms(&dev_priv->drm,
1180                     "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
1181                     dig_port->base.base.base.id,
1182                     dig_port->base.base.name,
1183                     pipe_name(intel_dp->pps_pipe));
1184
1185         intel_dp_init_panel_power_sequencer(intel_dp);
1186         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1187 }
1188
1189 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
1190 {
1191         struct intel_encoder *encoder;
1192
1193         if (drm_WARN_ON(&dev_priv->drm,
1194                         !(IS_VALLEYVIEW(dev_priv) ||
1195                           IS_CHERRYVIEW(dev_priv) ||
1196                           IS_GEN9_LP(dev_priv))))
1197                 return;
1198
1199         /*
1200          * We can't grab pps_mutex here due to deadlock with power_domain
1201          * mutex when power_domain functions are called while holding pps_mutex.
1202          * That also means that in order to use pps_pipe the code needs to
1203          * hold both a power domain reference and pps_mutex, and the power domain
1204          * reference get/put must be done while _not_ holding pps_mutex.
1205          * pps_{lock,unlock}() do these steps in the correct order, so one
1206          * should use them always.
1207          */
1208
1209         for_each_intel_dp(&dev_priv->drm, encoder) {
1210                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1211
1212                 drm_WARN_ON(&dev_priv->drm,
1213                             intel_dp->active_pipe != INVALID_PIPE);
1214
1215                 if (encoder->type != INTEL_OUTPUT_EDP)
1216                         continue;
1217
1218                 if (IS_GEN9_LP(dev_priv))
1219                         intel_dp->pps_reset = true;
1220                 else
1221                         intel_dp->pps_pipe = INVALID_PIPE;
1222         }
1223 }
1224
1225 struct pps_registers {
1226         i915_reg_t pp_ctrl;
1227         i915_reg_t pp_stat;
1228         i915_reg_t pp_on;
1229         i915_reg_t pp_off;
1230         i915_reg_t pp_div;
1231 };
1232
1233 static void intel_pps_get_registers(struct intel_dp *intel_dp,
1234                                     struct pps_registers *regs)
1235 {
1236         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1237         int pps_idx = 0;
1238
1239         memset(regs, 0, sizeof(*regs));
1240
1241         if (IS_GEN9_LP(dev_priv))
1242                 pps_idx = bxt_power_sequencer_idx(intel_dp);
1243         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1244                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
1245
1246         regs->pp_ctrl = PP_CONTROL(pps_idx);
1247         regs->pp_stat = PP_STATUS(pps_idx);
1248         regs->pp_on = PP_ON_DELAYS(pps_idx);
1249         regs->pp_off = PP_OFF_DELAYS(pps_idx);
1250
1251         /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
1252         if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1253                 regs->pp_div = INVALID_MMIO_REG;
1254         else
1255                 regs->pp_div = PP_DIVISOR(pps_idx);
1256 }
1257
1258 static i915_reg_t
1259 _pp_ctrl_reg(struct intel_dp *intel_dp)
1260 {
1261         struct pps_registers regs;
1262
1263         intel_pps_get_registers(intel_dp, &regs);
1264
1265         return regs.pp_ctrl;
1266 }
1267
1268 static i915_reg_t
1269 _pp_stat_reg(struct intel_dp *intel_dp)
1270 {
1271         struct pps_registers regs;
1272
1273         intel_pps_get_registers(intel_dp, &regs);
1274
1275         return regs.pp_stat;
1276 }
1277
1278 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1279 {
1280         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1281
1282         lockdep_assert_held(&dev_priv->pps_mutex);
1283
1284         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1285             intel_dp->pps_pipe == INVALID_PIPE)
1286                 return false;
1287
1288         return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
1289 }
1290
1291 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1292 {
1293         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1294
1295         lockdep_assert_held(&dev_priv->pps_mutex);
1296
1297         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1298             intel_dp->pps_pipe == INVALID_PIPE)
1299                 return false;
1300
1301         return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1302 }
1303
1304 static void
1305 intel_dp_check_edp(struct intel_dp *intel_dp)
1306 {
1307         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1308
1309         if (!intel_dp_is_edp(intel_dp))
1310                 return;
1311
1312         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1313                 drm_WARN(&dev_priv->drm, 1,
1314                          "eDP powered off while attempting aux channel communication.\n");
1315                 drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n",
1316                             intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
1317                             intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
1318         }
1319 }
1320
1321 static u32
1322 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1323 {
1324         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1325         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1326         const unsigned int timeout_ms = 10;
1327         u32 status;
1328         bool done;
1329
1330 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1331         done = wait_event_timeout(i915->gmbus_wait_queue, C,
1332                                   msecs_to_jiffies_timeout(timeout_ms));
1333
1334         /* just trace the final value */
1335         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1336
1337         if (!done)
1338                 drm_err(&i915->drm,
1339                         "%s: did not complete or timeout within %ums (status 0x%08x)\n",
1340                         intel_dp->aux.name, timeout_ms, status);
1341 #undef C
1342
1343         return status;
1344 }
1345
1346 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1347 {
1348         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1349
1350         if (index)
1351                 return 0;
1352
1353         /*
1354          * The clock divider is based off the hrawclk, and would like to run at
1355          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1356          */
1357         return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
1358 }
1359
1360 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1361 {
1362         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1363         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1364         u32 freq;
1365
1366         if (index)
1367                 return 0;
1368
1369         /*
1370          * The clock divider is based off the cdclk or PCH rawclk, and would
1371          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1372          * divide by 2000 and use that
1373          */
1374         if (dig_port->aux_ch == AUX_CH_A)
1375                 freq = dev_priv->cdclk.hw.cdclk;
1376         else
1377                 freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
1378         return DIV_ROUND_CLOSEST(freq, 2000);
1379 }
1380
1381 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1382 {
1383         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1384         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1385
1386         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1387                 /* Workaround for non-ULT HSW */
1388                 switch (index) {
1389                 case 0: return 63;
1390                 case 1: return 72;
1391                 default: return 0;
1392                 }
1393         }
1394
1395         return ilk_get_aux_clock_divider(intel_dp, index);
1396 }
1397
1398 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1399 {
1400         /*
1401          * SKL doesn't need us to program the AUX clock divider (Hardware will
1402          * derive the clock from CDCLK automatically). We still implement the
1403          * get_aux_clock_divider vfunc to plug-in into the existing code.
1404          */
1405         return index ? 0 : 1;
1406 }
1407
1408 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1409                                 int send_bytes,
1410                                 u32 aux_clock_divider)
1411 {
1412         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1413         struct drm_i915_private *dev_priv =
1414                         to_i915(dig_port->base.base.dev);
1415         u32 precharge, timeout;
1416
1417         if (IS_GEN(dev_priv, 6))
1418                 precharge = 3;
1419         else
1420                 precharge = 5;
1421
1422         if (IS_BROADWELL(dev_priv))
1423                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1424         else
1425                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1426
1427         return DP_AUX_CH_CTL_SEND_BUSY |
1428                DP_AUX_CH_CTL_DONE |
1429                DP_AUX_CH_CTL_INTERRUPT |
1430                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1431                timeout |
1432                DP_AUX_CH_CTL_RECEIVE_ERROR |
1433                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1434                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1435                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1436 }
1437
1438 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1439                                 int send_bytes,
1440                                 u32 unused)
1441 {
1442         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1443         struct drm_i915_private *i915 =
1444                         to_i915(dig_port->base.base.dev);
1445         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
1446         u32 ret;
1447
1448         ret = DP_AUX_CH_CTL_SEND_BUSY |
1449               DP_AUX_CH_CTL_DONE |
1450               DP_AUX_CH_CTL_INTERRUPT |
1451               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1452               DP_AUX_CH_CTL_TIME_OUT_MAX |
1453               DP_AUX_CH_CTL_RECEIVE_ERROR |
1454               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1455               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1456               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1457
1458         if (intel_phy_is_tc(i915, phy) &&
1459             dig_port->tc_mode == TC_PORT_TBT_ALT)
1460                 ret |= DP_AUX_CH_CTL_TBT_IO;
1461
1462         return ret;
1463 }
1464
1465 static int
1466 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1467                   const u8 *send, int send_bytes,
1468                   u8 *recv, int recv_size,
1469                   u32 aux_send_ctl_flags)
1470 {
1471         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1472         struct drm_i915_private *i915 =
1473                         to_i915(dig_port->base.base.dev);
1474         struct intel_uncore *uncore = &i915->uncore;
1475         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
1476         bool is_tc_port = intel_phy_is_tc(i915, phy);
1477         i915_reg_t ch_ctl, ch_data[5];
1478         u32 aux_clock_divider;
1479         enum intel_display_power_domain aux_domain;
1480         intel_wakeref_t aux_wakeref;
1481         intel_wakeref_t pps_wakeref;
1482         int i, ret, recv_bytes;
1483         int try, clock = 0;
1484         u32 status;
1485         bool vdd;
1486
1487         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1488         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1489                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1490
1491         if (is_tc_port)
1492                 intel_tc_port_lock(dig_port);
1493
1494         aux_domain = intel_aux_power_domain(dig_port);
1495
1496         aux_wakeref = intel_display_power_get(i915, aux_domain);
1497         pps_wakeref = pps_lock(intel_dp);
1498
1499         /*
1500          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1501          * In such cases we want to leave VDD enabled and it's up to upper layers
1502          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1503          * ourselves.
1504          */
1505         vdd = edp_panel_vdd_on(intel_dp);
1506
1507         /* dp aux is extremely sensitive to irq latency, hence request the
1508          * lowest possible wakeup latency and so prevent the cpu from going into
1509          * deep sleep states.
1510          */
1511         cpu_latency_qos_update_request(&i915->pm_qos, 0);
1512
1513         intel_dp_check_edp(intel_dp);
1514
1515         /* Try to wait for any previous AUX channel activity */
1516         for (try = 0; try < 3; try++) {
1517                 status = intel_uncore_read_notrace(uncore, ch_ctl);
1518                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1519                         break;
1520                 msleep(1);
1521         }
1522         /* just trace the final value */
1523         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1524
1525         if (try == 3) {
1526                 const u32 status = intel_uncore_read(uncore, ch_ctl);
1527
1528                 if (status != intel_dp->aux_busy_last_status) {
1529                         drm_WARN(&i915->drm, 1,
1530                                  "%s: not started (status 0x%08x)\n",
1531                                  intel_dp->aux.name, status);
1532                         intel_dp->aux_busy_last_status = status;
1533                 }
1534
1535                 ret = -EBUSY;
1536                 goto out;
1537         }
1538
1539         /* Only 5 data registers! */
1540         if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) {
1541                 ret = -E2BIG;
1542                 goto out;
1543         }
1544
1545         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1546                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1547                                                           send_bytes,
1548                                                           aux_clock_divider);
1549
1550                 send_ctl |= aux_send_ctl_flags;
1551
1552                 /* Must try at least 3 times according to DP spec */
1553                 for (try = 0; try < 5; try++) {
1554                         /* Load the send data into the aux channel data registers */
1555                         for (i = 0; i < send_bytes; i += 4)
1556                                 intel_uncore_write(uncore,
1557                                                    ch_data[i >> 2],
1558                                                    intel_dp_pack_aux(send + i,
1559                                                                      send_bytes - i));
1560
1561                         /* Send the command and wait for it to complete */
1562                         intel_uncore_write(uncore, ch_ctl, send_ctl);
1563
1564                         status = intel_dp_aux_wait_done(intel_dp);
1565
1566                         /* Clear done status and any errors */
1567                         intel_uncore_write(uncore,
1568                                            ch_ctl,
1569                                            status |
1570                                            DP_AUX_CH_CTL_DONE |
1571                                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
1572                                            DP_AUX_CH_CTL_RECEIVE_ERROR);
1573
1574                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1575                          *   400us delay required for errors and timeouts
1576                          *   Timeout errors from the HW already meet this
1577                          *   requirement so skip to next iteration
1578                          */
1579                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1580                                 continue;
1581
1582                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1583                                 usleep_range(400, 500);
1584                                 continue;
1585                         }
1586                         if (status & DP_AUX_CH_CTL_DONE)
1587                                 goto done;
1588                 }
1589         }
1590
1591         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1592                 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",
1593                         intel_dp->aux.name, status);
1594                 ret = -EBUSY;
1595                 goto out;
1596         }
1597
1598 done:
1599         /* Check for timeout or receive error.
1600          * Timeouts occur when the sink is not connected
1601          */
1602         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1603                 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",
1604                         intel_dp->aux.name, status);
1605                 ret = -EIO;
1606                 goto out;
1607         }
1608
1609         /* Timeouts occur when the device isn't connected, so they're
1610          * "normal" -- don't fill the kernel log with these */
1611         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1612                 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
1613                             intel_dp->aux.name, status);
1614                 ret = -ETIMEDOUT;
1615                 goto out;
1616         }
1617
1618         /* Unload any bytes sent back from the other side */
1619         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1620                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1621
1622         /*
1623          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1624          * We have no idea of what happened so we return -EBUSY so
1625          * drm layer takes care for the necessary retries.
1626          */
1627         if (recv_bytes == 0 || recv_bytes > 20) {
1628                 drm_dbg_kms(&i915->drm,
1629                             "%s: Forbidden recv_bytes = %d on aux transaction\n",
1630                             intel_dp->aux.name, recv_bytes);
1631                 ret = -EBUSY;
1632                 goto out;
1633         }
1634
1635         if (recv_bytes > recv_size)
1636                 recv_bytes = recv_size;
1637
1638         for (i = 0; i < recv_bytes; i += 4)
1639                 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
1640                                     recv + i, recv_bytes - i);
1641
1642         ret = recv_bytes;
1643 out:
1644         cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
1645
1646         if (vdd)
1647                 edp_panel_vdd_off(intel_dp, false);
1648
1649         pps_unlock(intel_dp, pps_wakeref);
1650         intel_display_power_put_async(i915, aux_domain, aux_wakeref);
1651
1652         if (is_tc_port)
1653                 intel_tc_port_unlock(dig_port);
1654
1655         return ret;
1656 }
1657
1658 #define BARE_ADDRESS_SIZE       3
1659 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1660
1661 static void
1662 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1663                     const struct drm_dp_aux_msg *msg)
1664 {
1665         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1666         txbuf[1] = (msg->address >> 8) & 0xff;
1667         txbuf[2] = msg->address & 0xff;
1668         txbuf[3] = msg->size - 1;
1669 }
1670
1671 static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg)
1672 {
1673         /*
1674          * If we're trying to send the HDCP Aksv, we need to set a the Aksv
1675          * select bit to inform the hardware to send the Aksv after our header
1676          * since we can't access that data from software.
1677          */
1678         if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE &&
1679             msg->address == DP_AUX_HDCP_AKSV)
1680                 return DP_AUX_CH_CTL_AUX_AKSV_SELECT;
1681
1682         return 0;
1683 }
1684
1685 static ssize_t
1686 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1687 {
1688         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1689         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1690         u8 txbuf[20], rxbuf[20];
1691         size_t txsize, rxsize;
1692         u32 flags = intel_dp_aux_xfer_flags(msg);
1693         int ret;
1694
1695         intel_dp_aux_header(txbuf, msg);
1696
1697         switch (msg->request & ~DP_AUX_I2C_MOT) {
1698         case DP_AUX_NATIVE_WRITE:
1699         case DP_AUX_I2C_WRITE:
1700         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1701                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1702                 rxsize = 2; /* 0 or 1 data bytes */
1703
1704                 if (drm_WARN_ON(&i915->drm, txsize > 20))
1705                         return -E2BIG;
1706
1707                 drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size);
1708
1709                 if (msg->buffer)
1710                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1711
1712                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1713                                         rxbuf, rxsize, flags);
1714                 if (ret > 0) {
1715                         msg->reply = rxbuf[0] >> 4;
1716
1717                         if (ret > 1) {
1718                                 /* Number of bytes written in a short write. */
1719                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1720                         } else {
1721                                 /* Return payload size. */
1722                                 ret = msg->size;
1723                         }
1724                 }
1725                 break;
1726
1727         case DP_AUX_NATIVE_READ:
1728         case DP_AUX_I2C_READ:
1729                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1730                 rxsize = msg->size + 1;
1731
1732                 if (drm_WARN_ON(&i915->drm, rxsize > 20))
1733                         return -E2BIG;
1734
1735                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1736                                         rxbuf, rxsize, flags);
1737                 if (ret > 0) {
1738                         msg->reply = rxbuf[0] >> 4;
1739                         /*
1740                          * Assume happy day, and copy the data. The caller is
1741                          * expected to check msg->reply before touching it.
1742                          *
1743                          * Return payload size.
1744                          */
1745                         ret--;
1746                         memcpy(msg->buffer, rxbuf + 1, ret);
1747                 }
1748                 break;
1749
1750         default:
1751                 ret = -EINVAL;
1752                 break;
1753         }
1754
1755         return ret;
1756 }
1757
1758
1759 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1760 {
1761         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1762         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1763         enum aux_ch aux_ch = dig_port->aux_ch;
1764
1765         switch (aux_ch) {
1766         case AUX_CH_B:
1767         case AUX_CH_C:
1768         case AUX_CH_D:
1769                 return DP_AUX_CH_CTL(aux_ch);
1770         default:
1771                 MISSING_CASE(aux_ch);
1772                 return DP_AUX_CH_CTL(AUX_CH_B);
1773         }
1774 }
1775
1776 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1777 {
1778         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1779         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1780         enum aux_ch aux_ch = dig_port->aux_ch;
1781
1782         switch (aux_ch) {
1783         case AUX_CH_B:
1784         case AUX_CH_C:
1785         case AUX_CH_D:
1786                 return DP_AUX_CH_DATA(aux_ch, index);
1787         default:
1788                 MISSING_CASE(aux_ch);
1789                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1790         }
1791 }
1792
1793 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1794 {
1795         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1796         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1797         enum aux_ch aux_ch = dig_port->aux_ch;
1798
1799         switch (aux_ch) {
1800         case AUX_CH_A:
1801                 return DP_AUX_CH_CTL(aux_ch);
1802         case AUX_CH_B:
1803         case AUX_CH_C:
1804         case AUX_CH_D:
1805                 return PCH_DP_AUX_CH_CTL(aux_ch);
1806         default:
1807                 MISSING_CASE(aux_ch);
1808                 return DP_AUX_CH_CTL(AUX_CH_A);
1809         }
1810 }
1811
1812 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1813 {
1814         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1815         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1816         enum aux_ch aux_ch = dig_port->aux_ch;
1817
1818         switch (aux_ch) {
1819         case AUX_CH_A:
1820                 return DP_AUX_CH_DATA(aux_ch, index);
1821         case AUX_CH_B:
1822         case AUX_CH_C:
1823         case AUX_CH_D:
1824                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1825         default:
1826                 MISSING_CASE(aux_ch);
1827                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1828         }
1829 }
1830
1831 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1832 {
1833         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1834         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1835         enum aux_ch aux_ch = dig_port->aux_ch;
1836
1837         switch (aux_ch) {
1838         case AUX_CH_A:
1839         case AUX_CH_B:
1840         case AUX_CH_C:
1841         case AUX_CH_D:
1842         case AUX_CH_E:
1843         case AUX_CH_F:
1844                 return DP_AUX_CH_CTL(aux_ch);
1845         default:
1846                 MISSING_CASE(aux_ch);
1847                 return DP_AUX_CH_CTL(AUX_CH_A);
1848         }
1849 }
1850
1851 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1852 {
1853         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1854         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1855         enum aux_ch aux_ch = dig_port->aux_ch;
1856
1857         switch (aux_ch) {
1858         case AUX_CH_A:
1859         case AUX_CH_B:
1860         case AUX_CH_C:
1861         case AUX_CH_D:
1862         case AUX_CH_E:
1863         case AUX_CH_F:
1864                 return DP_AUX_CH_DATA(aux_ch, index);
1865         default:
1866                 MISSING_CASE(aux_ch);
1867                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1868         }
1869 }
1870
1871 static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
1872 {
1873         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1874         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1875         enum aux_ch aux_ch = dig_port->aux_ch;
1876
1877         switch (aux_ch) {
1878         case AUX_CH_A:
1879         case AUX_CH_B:
1880         case AUX_CH_C:
1881         case AUX_CH_USBC1:
1882         case AUX_CH_USBC2:
1883         case AUX_CH_USBC3:
1884         case AUX_CH_USBC4:
1885         case AUX_CH_USBC5:
1886         case AUX_CH_USBC6:
1887                 return DP_AUX_CH_CTL(aux_ch);
1888         default:
1889                 MISSING_CASE(aux_ch);
1890                 return DP_AUX_CH_CTL(AUX_CH_A);
1891         }
1892 }
1893
1894 static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
1895 {
1896         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1897         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1898         enum aux_ch aux_ch = dig_port->aux_ch;
1899
1900         switch (aux_ch) {
1901         case AUX_CH_A:
1902         case AUX_CH_B:
1903         case AUX_CH_C:
1904         case AUX_CH_USBC1:
1905         case AUX_CH_USBC2:
1906         case AUX_CH_USBC3:
1907         case AUX_CH_USBC4:
1908         case AUX_CH_USBC5:
1909         case AUX_CH_USBC6:
1910                 return DP_AUX_CH_DATA(aux_ch, index);
1911         default:
1912                 MISSING_CASE(aux_ch);
1913                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1914         }
1915 }
1916
1917 static void
1918 intel_dp_aux_fini(struct intel_dp *intel_dp)
1919 {
1920         kfree(intel_dp->aux.name);
1921 }
1922
1923 static void
1924 intel_dp_aux_init(struct intel_dp *intel_dp)
1925 {
1926         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1927         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1928         struct intel_encoder *encoder = &dig_port->base;
1929         enum aux_ch aux_ch = dig_port->aux_ch;
1930
1931         if (INTEL_GEN(dev_priv) >= 12) {
1932                 intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
1933                 intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
1934         } else if (INTEL_GEN(dev_priv) >= 9) {
1935                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1936                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1937         } else if (HAS_PCH_SPLIT(dev_priv)) {
1938                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1939                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1940         } else {
1941                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1942                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1943         }
1944
1945         if (INTEL_GEN(dev_priv) >= 9)
1946                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1947         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1948                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1949         else if (HAS_PCH_SPLIT(dev_priv))
1950                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1951         else
1952                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1953
1954         if (INTEL_GEN(dev_priv) >= 9)
1955                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1956         else
1957                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1958
1959         drm_dp_aux_init(&intel_dp->aux);
1960
1961         /* Failure to allocate our preferred name is not critical */
1962         if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
1963                 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
1964                                                aux_ch - AUX_CH_USBC1 + '1',
1965                                                encoder->base.name);
1966         else
1967                 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
1968                                                aux_ch_name(aux_ch),
1969                                                encoder->base.name);
1970
1971         intel_dp->aux.transfer = intel_dp_aux_transfer;
1972 }
1973
1974 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1975 {
1976         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1977
1978         return max_rate >= 540000;
1979 }
1980
1981 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1982 {
1983         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1984
1985         return max_rate >= 810000;
1986 }
1987
1988 static void
1989 intel_dp_set_clock(struct intel_encoder *encoder,
1990                    struct intel_crtc_state *pipe_config)
1991 {
1992         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1993         const struct dp_link_dpll *divisor = NULL;
1994         int i, count = 0;
1995
1996         if (IS_G4X(dev_priv)) {
1997                 divisor = g4x_dpll;
1998                 count = ARRAY_SIZE(g4x_dpll);
1999         } else if (HAS_PCH_SPLIT(dev_priv)) {
2000                 divisor = pch_dpll;
2001                 count = ARRAY_SIZE(pch_dpll);
2002         } else if (IS_CHERRYVIEW(dev_priv)) {
2003                 divisor = chv_dpll;
2004                 count = ARRAY_SIZE(chv_dpll);
2005         } else if (IS_VALLEYVIEW(dev_priv)) {
2006                 divisor = vlv_dpll;
2007                 count = ARRAY_SIZE(vlv_dpll);
2008         }
2009
2010         if (divisor && count) {
2011                 for (i = 0; i < count; i++) {
2012                         if (pipe_config->port_clock == divisor[i].clock) {
2013                                 pipe_config->dpll = divisor[i].dpll;
2014                                 pipe_config->clock_set = true;
2015                                 break;
2016                         }
2017                 }
2018         }
2019 }
2020
2021 static void snprintf_int_array(char *str, size_t len,
2022                                const int *array, int nelem)
2023 {
2024         int i;
2025
2026         str[0] = '\0';
2027
2028         for (i = 0; i < nelem; i++) {
2029                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
2030                 if (r >= len)
2031                         return;
2032                 str += r;
2033                 len -= r;
2034         }
2035 }
2036
2037 static void intel_dp_print_rates(struct intel_dp *intel_dp)
2038 {
2039         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2040         char str[128]; /* FIXME: too big for stack? */
2041
2042         if (!drm_debug_enabled(DRM_UT_KMS))
2043                 return;
2044
2045         snprintf_int_array(str, sizeof(str),
2046                            intel_dp->source_rates, intel_dp->num_source_rates);
2047         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
2048
2049         snprintf_int_array(str, sizeof(str),
2050                            intel_dp->sink_rates, intel_dp->num_sink_rates);
2051         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
2052
2053         snprintf_int_array(str, sizeof(str),
2054                            intel_dp->common_rates, intel_dp->num_common_rates);
2055         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
2056 }
2057
2058 int
2059 intel_dp_max_link_rate(struct intel_dp *intel_dp)
2060 {
2061         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2062         int len;
2063
2064         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
2065         if (drm_WARN_ON(&i915->drm, len <= 0))
2066                 return 162000;
2067
2068         return intel_dp->common_rates[len - 1];
2069 }
2070
2071 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
2072 {
2073         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2074         int i = intel_dp_rate_index(intel_dp->sink_rates,
2075                                     intel_dp->num_sink_rates, rate);
2076
2077         if (drm_WARN_ON(&i915->drm, i < 0))
2078                 i = 0;
2079
2080         return i;
2081 }
2082
2083 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
2084                            u8 *link_bw, u8 *rate_select)
2085 {
2086         /* eDP 1.4 rate select method. */
2087         if (intel_dp->use_rate_select) {
2088                 *link_bw = 0;
2089                 *rate_select =
2090                         intel_dp_rate_select(intel_dp, port_clock);
2091         } else {
2092                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
2093                 *rate_select = 0;
2094         }
2095 }
2096
2097 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
2098                                          const struct intel_crtc_state *pipe_config)
2099 {
2100         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2101
2102         /* On TGL, FEC is supported on all Pipes */
2103         if (INTEL_GEN(dev_priv) >= 12)
2104                 return true;
2105
2106         if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
2107                 return true;
2108
2109         return false;
2110 }
2111
2112 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
2113                                   const struct intel_crtc_state *pipe_config)
2114 {
2115         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
2116                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
2117 }
2118
2119 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
2120                                   const struct intel_crtc_state *crtc_state)
2121 {
2122         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
2123                 return false;
2124
2125         return intel_dsc_source_support(crtc_state) &&
2126                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
2127 }
2128
2129 static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp,
2130                                    const struct intel_crtc_state *crtc_state)
2131 {
2132         return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2133                 (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
2134                  intel_dp->dfp.ycbcr_444_to_420);
2135 }
2136
2137 static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp,
2138                                     const struct intel_crtc_state *crtc_state, int bpc)
2139 {
2140         int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8;
2141
2142         if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state))
2143                 clock /= 2;
2144
2145         return clock;
2146 }
2147
2148 static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
2149                                            const struct intel_crtc_state *crtc_state, int bpc)
2150 {
2151         int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc);
2152
2153         if (intel_dp->dfp.min_tmds_clock &&
2154             tmds_clock < intel_dp->dfp.min_tmds_clock)
2155                 return false;
2156
2157         if (intel_dp->dfp.max_tmds_clock &&
2158             tmds_clock > intel_dp->dfp.max_tmds_clock)
2159                 return false;
2160
2161         return true;
2162 }
2163
2164 static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp,
2165                                               const struct intel_crtc_state *crtc_state,
2166                                               int bpc)
2167 {
2168
2169         return intel_hdmi_deep_color_possible(crtc_state, bpc,
2170                                               intel_dp->has_hdmi_sink,
2171                                               intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
2172                 intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
2173 }
2174
2175 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
2176                             const struct intel_crtc_state *crtc_state)
2177 {
2178         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2179         struct intel_connector *intel_connector = intel_dp->attached_connector;
2180         int bpp, bpc;
2181
2182         bpc = crtc_state->pipe_bpp / 3;
2183
2184         if (intel_dp->dfp.max_bpc)
2185                 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
2186
2187         if (intel_dp->dfp.min_tmds_clock) {
2188                 for (; bpc >= 10; bpc -= 2) {
2189                         if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc))
2190                                 break;
2191                 }
2192         }
2193
2194         bpp = bpc * 3;
2195         if (intel_dp_is_edp(intel_dp)) {
2196                 /* Get bpp from vbt only for panels that dont have bpp in edid */
2197                 if (intel_connector->base.display_info.bpc == 0 &&
2198                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
2199                         drm_dbg_kms(&dev_priv->drm,
2200                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
2201                                     dev_priv->vbt.edp.bpp);
2202                         bpp = dev_priv->vbt.edp.bpp;
2203                 }
2204         }
2205
2206         return bpp;
2207 }
2208
2209 /* Adjust link config limits based on compliance test requests. */
2210 void
2211 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
2212                                   struct intel_crtc_state *pipe_config,
2213                                   struct link_config_limits *limits)
2214 {
2215         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2216
2217         /* For DP Compliance we override the computed bpp for the pipe */
2218         if (intel_dp->compliance.test_data.bpc != 0) {
2219                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
2220
2221                 limits->min_bpp = limits->max_bpp = bpp;
2222                 pipe_config->dither_force_disable = bpp == 6 * 3;
2223
2224                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
2225         }
2226
2227         /* Use values requested by Compliance Test Request */
2228         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
2229                 int index;
2230
2231                 /* Validate the compliance test data since max values
2232                  * might have changed due to link train fallback.
2233                  */
2234                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
2235                                                intel_dp->compliance.test_lane_count)) {
2236                         index = intel_dp_rate_index(intel_dp->common_rates,
2237                                                     intel_dp->num_common_rates,
2238                                                     intel_dp->compliance.test_link_rate);
2239                         if (index >= 0)
2240                                 limits->min_clock = limits->max_clock = index;
2241                         limits->min_lane_count = limits->max_lane_count =
2242                                 intel_dp->compliance.test_lane_count;
2243                 }
2244         }
2245 }
2246
2247 /* Optimize link config in order: max bpp, min clock, min lanes */
2248 static int
2249 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
2250                                   struct intel_crtc_state *pipe_config,
2251                                   const struct link_config_limits *limits)
2252 {
2253         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2254         int bpp, clock, lane_count;
2255         int mode_rate, link_clock, link_avail;
2256
2257         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
2258                 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
2259
2260                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
2261                                                    output_bpp);
2262
2263                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
2264                         for (lane_count = limits->min_lane_count;
2265                              lane_count <= limits->max_lane_count;
2266                              lane_count <<= 1) {
2267                                 link_clock = intel_dp->common_rates[clock];
2268                                 link_avail = intel_dp_max_data_rate(link_clock,
2269                                                                     lane_count);
2270
2271                                 if (mode_rate <= link_avail) {
2272                                         pipe_config->lane_count = lane_count;
2273                                         pipe_config->pipe_bpp = bpp;
2274                                         pipe_config->port_clock = link_clock;
2275
2276                                         return 0;
2277                                 }
2278                         }
2279                 }
2280         }
2281
2282         return -EINVAL;
2283 }
2284
2285 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
2286 {
2287         int i, num_bpc;
2288         u8 dsc_bpc[3] = {0};
2289
2290         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
2291                                                        dsc_bpc);
2292         for (i = 0; i < num_bpc; i++) {
2293                 if (dsc_max_bpc >= dsc_bpc[i])
2294                         return dsc_bpc[i] * 3;
2295         }
2296
2297         return 0;
2298 }
2299
2300 #define DSC_SUPPORTED_VERSION_MIN               1
2301
2302 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
2303                                        struct intel_crtc_state *crtc_state)
2304 {
2305         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2306         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2307         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
2308         u8 line_buf_depth;
2309         int ret;
2310
2311         ret = intel_dsc_compute_params(encoder, crtc_state);
2312         if (ret)
2313                 return ret;
2314
2315         /*
2316          * Slice Height of 8 works for all currently available panels. So start
2317          * with that if pic_height is an integral multiple of 8. Eventually add
2318          * logic to try multiple slice heights.
2319          */
2320         if (vdsc_cfg->pic_height % 8 == 0)
2321                 vdsc_cfg->slice_height = 8;
2322         else if (vdsc_cfg->pic_height % 4 == 0)
2323                 vdsc_cfg->slice_height = 4;
2324         else
2325                 vdsc_cfg->slice_height = 2;
2326
2327         vdsc_cfg->dsc_version_major =
2328                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2329                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
2330         vdsc_cfg->dsc_version_minor =
2331                 min(DSC_SUPPORTED_VERSION_MIN,
2332                     (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2333                      DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
2334
2335         vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
2336                 DP_DSC_RGB;
2337
2338         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
2339         if (!line_buf_depth) {
2340                 drm_dbg_kms(&i915->drm,
2341                             "DSC Sink Line Buffer Depth invalid\n");
2342                 return -EINVAL;
2343         }
2344
2345         if (vdsc_cfg->dsc_version_minor == 2)
2346                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
2347                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
2348         else
2349                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
2350                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
2351
2352         vdsc_cfg->block_pred_enable =
2353                 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
2354                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
2355
2356         return drm_dsc_compute_rc_parameters(vdsc_cfg);
2357 }
2358
2359 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2360                                        struct intel_crtc_state *pipe_config,
2361                                        struct drm_connector_state *conn_state,
2362                                        struct link_config_limits *limits)
2363 {
2364         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2365         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2366         const struct drm_display_mode *adjusted_mode =
2367                 &pipe_config->hw.adjusted_mode;
2368         u8 dsc_max_bpc;
2369         int pipe_bpp;
2370         int ret;
2371
2372         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2373                 intel_dp_supports_fec(intel_dp, pipe_config);
2374
2375         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
2376                 return -EINVAL;
2377
2378         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
2379         if (INTEL_GEN(dev_priv) >= 12)
2380                 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
2381         else
2382                 dsc_max_bpc = min_t(u8, 10,
2383                                     conn_state->max_requested_bpc);
2384
2385         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
2386
2387         /* Min Input BPC for ICL+ is 8 */
2388         if (pipe_bpp < 8 * 3) {
2389                 drm_dbg_kms(&dev_priv->drm,
2390                             "No DSC support for less than 8bpc\n");
2391                 return -EINVAL;
2392         }
2393
2394         /*
2395          * For now enable DSC for max bpp, max link rate, max lane count.
2396          * Optimize this later for the minimum possible link rate/lane count
2397          * with DSC enabled for the requested mode.
2398          */
2399         pipe_config->pipe_bpp = pipe_bpp;
2400         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
2401         pipe_config->lane_count = limits->max_lane_count;
2402
2403         if (intel_dp_is_edp(intel_dp)) {
2404                 pipe_config->dsc.compressed_bpp =
2405                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
2406                               pipe_config->pipe_bpp);
2407                 pipe_config->dsc.slice_count =
2408                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
2409                                                         true);
2410         } else {
2411                 u16 dsc_max_output_bpp;
2412                 u8 dsc_dp_slice_count;
2413
2414                 dsc_max_output_bpp =
2415                         intel_dp_dsc_get_output_bpp(dev_priv,
2416                                                     pipe_config->port_clock,
2417                                                     pipe_config->lane_count,
2418                                                     adjusted_mode->crtc_clock,
2419                                                     adjusted_mode->crtc_hdisplay,
2420                                                     pipe_config->bigjoiner);
2421                 dsc_dp_slice_count =
2422                         intel_dp_dsc_get_slice_count(intel_dp,
2423                                                      adjusted_mode->crtc_clock,
2424                                                      adjusted_mode->crtc_hdisplay,
2425                                                      pipe_config->bigjoiner);
2426                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
2427                         drm_dbg_kms(&dev_priv->drm,
2428                                     "Compressed BPP/Slice Count not supported\n");
2429                         return -EINVAL;
2430                 }
2431                 pipe_config->dsc.compressed_bpp = min_t(u16,
2432                                                                dsc_max_output_bpp >> 4,
2433                                                                pipe_config->pipe_bpp);
2434                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2435         }
2436         /*
2437          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2438          * is greater than the maximum Cdclock and if slice count is even
2439          * then we need to use 2 VDSC instances.
2440          */
2441         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
2442             pipe_config->bigjoiner) {
2443                 if (pipe_config->dsc.slice_count < 2) {
2444                         drm_dbg_kms(&dev_priv->drm,
2445                                     "Cannot split stream to use 2 VDSC instances\n");
2446                         return -EINVAL;
2447                 }
2448
2449                 pipe_config->dsc.dsc_split = true;
2450         }
2451
2452         ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
2453         if (ret < 0) {
2454                 drm_dbg_kms(&dev_priv->drm,
2455                             "Cannot compute valid DSC parameters for Input Bpp = %d "
2456                             "Compressed BPP = %d\n",
2457                             pipe_config->pipe_bpp,
2458                             pipe_config->dsc.compressed_bpp);
2459                 return ret;
2460         }
2461
2462         pipe_config->dsc.compression_enable = true;
2463         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2464                     "Compressed Bpp = %d Slice Count = %d\n",
2465                     pipe_config->pipe_bpp,
2466                     pipe_config->dsc.compressed_bpp,
2467                     pipe_config->dsc.slice_count);
2468
2469         return 0;
2470 }
2471
2472 static int
2473 intel_dp_compute_link_config(struct intel_encoder *encoder,
2474                              struct intel_crtc_state *pipe_config,
2475                              struct drm_connector_state *conn_state)
2476 {
2477         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2478         const struct drm_display_mode *adjusted_mode =
2479                 &pipe_config->hw.adjusted_mode;
2480         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2481         struct link_config_limits limits;
2482         int common_len;
2483         int ret;
2484
2485         common_len = intel_dp_common_len_rate_limit(intel_dp,
2486                                                     intel_dp->max_link_rate);
2487
2488         /* No common link rates between source and sink */
2489         drm_WARN_ON(encoder->base.dev, common_len <= 0);
2490
2491         limits.min_clock = 0;
2492         limits.max_clock = common_len - 1;
2493
2494         limits.min_lane_count = 1;
2495         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2496
2497         limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
2498         limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config);
2499
2500         if (intel_dp_is_edp(intel_dp)) {
2501                 /*
2502                  * Use the maximum clock and number of lanes the eDP panel
2503                  * advertizes being capable of. The panels are generally
2504                  * designed to support only a single clock and lane
2505                  * configuration, and typically these values correspond to the
2506                  * native resolution of the panel.
2507                  */
2508                 limits.min_lane_count = limits.max_lane_count;
2509                 limits.min_clock = limits.max_clock;
2510         }
2511
2512         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2513
2514         drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
2515                     "max rate %d max bpp %d pixel clock %iKHz\n",
2516                     limits.max_lane_count,
2517                     intel_dp->common_rates[limits.max_clock],
2518                     limits.max_bpp, adjusted_mode->crtc_clock);
2519
2520         if ((adjusted_mode->crtc_clock > i915->max_dotclk_freq ||
2521              adjusted_mode->crtc_hdisplay > 5120) &&
2522             intel_dp_can_bigjoiner(intel_dp))
2523                 pipe_config->bigjoiner = true;
2524
2525         /*
2526          * Optimize for slow and wide. This is the place to add alternative
2527          * optimization policy.
2528          */
2529         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2530
2531         /* enable compression if the mode doesn't fit available BW */
2532         drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
2533         if (ret || intel_dp->force_dsc_en || pipe_config->bigjoiner) {
2534                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2535                                                   conn_state, &limits);
2536                 if (ret < 0)
2537                         return ret;
2538         }
2539
2540         if (pipe_config->dsc.compression_enable) {
2541                 drm_dbg_kms(&i915->drm,
2542                             "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2543                             pipe_config->lane_count, pipe_config->port_clock,
2544                             pipe_config->pipe_bpp,
2545                             pipe_config->dsc.compressed_bpp);
2546
2547                 drm_dbg_kms(&i915->drm,
2548                             "DP link rate required %i available %i\n",
2549                             intel_dp_link_required(adjusted_mode->crtc_clock,
2550                                                    pipe_config->dsc.compressed_bpp),
2551                             intel_dp_max_data_rate(pipe_config->port_clock,
2552                                                    pipe_config->lane_count));
2553         } else {
2554                 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
2555                             pipe_config->lane_count, pipe_config->port_clock,
2556                             pipe_config->pipe_bpp);
2557
2558                 drm_dbg_kms(&i915->drm,
2559                             "DP link rate required %i available %i\n",
2560                             intel_dp_link_required(adjusted_mode->crtc_clock,
2561                                                    pipe_config->pipe_bpp),
2562                             intel_dp_max_data_rate(pipe_config->port_clock,
2563                                                    pipe_config->lane_count));
2564         }
2565         return 0;
2566 }
2567
2568 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2569                                   const struct drm_connector_state *conn_state)
2570 {
2571         const struct intel_digital_connector_state *intel_conn_state =
2572                 to_intel_digital_connector_state(conn_state);
2573         const struct drm_display_mode *adjusted_mode =
2574                 &crtc_state->hw.adjusted_mode;
2575
2576         /*
2577          * Our YCbCr output is always limited range.
2578          * crtc_state->limited_color_range only applies to RGB,
2579          * and it must never be set for YCbCr or we risk setting
2580          * some conflicting bits in PIPECONF which will mess up
2581          * the colors on the monitor.
2582          */
2583         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2584                 return false;
2585
2586         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2587                 /*
2588                  * See:
2589                  * CEA-861-E - 5.1 Default Encoding Parameters
2590                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2591                  */
2592                 return crtc_state->pipe_bpp != 18 &&
2593                         drm_default_rgb_quant_range(adjusted_mode) ==
2594                         HDMI_QUANTIZATION_RANGE_LIMITED;
2595         } else {
2596                 return intel_conn_state->broadcast_rgb ==
2597                         INTEL_BROADCAST_RGB_LIMITED;
2598         }
2599 }
2600
2601 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2602                                     enum port port)
2603 {
2604         if (IS_G4X(dev_priv))
2605                 return false;
2606         if (INTEL_GEN(dev_priv) < 12 && port == PORT_A)
2607                 return false;
2608
2609         return true;
2610 }
2611
2612 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2613                                              const struct drm_connector_state *conn_state,
2614                                              struct drm_dp_vsc_sdp *vsc)
2615 {
2616         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2617         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2618
2619         /*
2620          * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2621          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2622          * Colorimetry Format indication.
2623          */
2624         vsc->revision = 0x5;
2625         vsc->length = 0x13;
2626
2627         /* DP 1.4a spec, Table 2-120 */
2628         switch (crtc_state->output_format) {
2629         case INTEL_OUTPUT_FORMAT_YCBCR444:
2630                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2631                 break;
2632         case INTEL_OUTPUT_FORMAT_YCBCR420:
2633                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2634                 break;
2635         case INTEL_OUTPUT_FORMAT_RGB:
2636         default:
2637                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2638         }
2639
2640         switch (conn_state->colorspace) {
2641         case DRM_MODE_COLORIMETRY_BT709_YCC:
2642                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2643                 break;
2644         case DRM_MODE_COLORIMETRY_XVYCC_601:
2645                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2646                 break;
2647         case DRM_MODE_COLORIMETRY_XVYCC_709:
2648                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2649                 break;
2650         case DRM_MODE_COLORIMETRY_SYCC_601:
2651                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2652                 break;
2653         case DRM_MODE_COLORIMETRY_OPYCC_601:
2654                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2655                 break;
2656         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2657                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2658                 break;
2659         case DRM_MODE_COLORIMETRY_BT2020_RGB:
2660                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2661                 break;
2662         case DRM_MODE_COLORIMETRY_BT2020_YCC:
2663                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2664                 break;
2665         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2666         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2667                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2668                 break;
2669         default:
2670                 /*
2671                  * RGB->YCBCR color conversion uses the BT.709
2672                  * color space.
2673                  */
2674                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2675                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2676                 else
2677                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2678                 break;
2679         }
2680
2681         vsc->bpc = crtc_state->pipe_bpp / 3;
2682
2683         /* only RGB pixelformat supports 6 bpc */
2684         drm_WARN_ON(&dev_priv->drm,
2685                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2686
2687         /* all YCbCr are always limited range */
2688         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2689         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2690 }
2691
2692 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2693                                      struct intel_crtc_state *crtc_state,
2694                                      const struct drm_connector_state *conn_state)
2695 {
2696         struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
2697
2698         /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
2699         if (crtc_state->has_psr)
2700                 return;
2701
2702         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
2703                 return;
2704
2705         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2706         vsc->sdp_type = DP_SDP_VSC;
2707         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2708                                          &crtc_state->infoframes.vsc);
2709 }
2710
2711 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
2712                                   const struct intel_crtc_state *crtc_state,
2713                                   const struct drm_connector_state *conn_state,
2714                                   struct drm_dp_vsc_sdp *vsc)
2715 {
2716         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2717
2718         vsc->sdp_type = DP_SDP_VSC;
2719
2720         if (dev_priv->psr.psr2_enabled) {
2721                 if (dev_priv->psr.colorimetry_support &&
2722                     intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2723                         /* [PSR2, +Colorimetry] */
2724                         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2725                                                          vsc);
2726                 } else {
2727                         /*
2728                          * [PSR2, -Colorimetry]
2729                          * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2730                          * 3D stereo + PSR/PSR2 + Y-coordinate.
2731                          */
2732                         vsc->revision = 0x4;
2733                         vsc->length = 0xe;
2734                 }
2735         } else {
2736                 /*
2737                  * [PSR1]
2738                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2739                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2740                  * higher).
2741                  */
2742                 vsc->revision = 0x2;
2743                 vsc->length = 0x8;
2744         }
2745 }
2746
2747 static void
2748 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2749                                             struct intel_crtc_state *crtc_state,
2750                                             const struct drm_connector_state *conn_state)
2751 {
2752         int ret;
2753         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2754         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2755
2756         if (!conn_state->hdr_output_metadata)
2757                 return;
2758
2759         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2760
2761         if (ret) {
2762                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2763                 return;
2764         }
2765
2766         crtc_state->infoframes.enable |=
2767                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2768 }
2769
2770 static void
2771 intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
2772                              struct intel_crtc_state *pipe_config,
2773                              int output_bpp, bool constant_n)
2774 {
2775         struct intel_connector *intel_connector = intel_dp->attached_connector;
2776         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2777
2778         /*
2779          * DRRS and PSR can't be enable together, so giving preference to PSR
2780          * as it allows more power-savings by complete shutting down display,
2781          * so to guarantee this, intel_dp_drrs_compute_config() must be called
2782          * after intel_psr_compute_config().
2783          */
2784         if (pipe_config->has_psr)
2785                 return;
2786
2787         if (!intel_connector->panel.downclock_mode ||
2788             dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
2789                 return;
2790
2791         pipe_config->has_drrs = true;
2792         intel_link_compute_m_n(output_bpp, pipe_config->lane_count,
2793                                intel_connector->panel.downclock_mode->clock,
2794                                pipe_config->port_clock, &pipe_config->dp_m2_n2,
2795                                constant_n, pipe_config->fec_enable);
2796 }
2797
2798 int
2799 intel_dp_compute_config(struct intel_encoder *encoder,
2800                         struct intel_crtc_state *pipe_config,
2801                         struct drm_connector_state *conn_state)
2802 {
2803         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2804         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2805         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2806         enum port port = encoder->port;
2807         struct intel_connector *intel_connector = intel_dp->attached_connector;
2808         struct intel_digital_connector_state *intel_conn_state =
2809                 to_intel_digital_connector_state(conn_state);
2810         bool constant_n = drm_dp_has_quirk(&intel_dp->desc, 0,
2811                                            DP_DPCD_QUIRK_CONSTANT_N);
2812         int ret = 0, output_bpp;
2813
2814         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2815                 pipe_config->has_pch_encoder = true;
2816
2817         pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
2818                                                             adjusted_mode);
2819
2820         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2821                 ret = intel_pch_panel_fitting(pipe_config, conn_state);
2822                 if (ret)
2823                         return ret;
2824         }
2825
2826         if (!intel_dp_port_has_audio(dev_priv, port))
2827                 pipe_config->has_audio = false;
2828         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2829                 pipe_config->has_audio = intel_dp->has_audio;
2830         else
2831                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2832
2833         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2834                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2835                                        adjusted_mode);
2836
2837                 if (HAS_GMCH(dev_priv))
2838                         ret = intel_gmch_panel_fitting(pipe_config, conn_state);
2839                 else
2840                         ret = intel_pch_panel_fitting(pipe_config, conn_state);
2841                 if (ret)
2842                         return ret;
2843         }
2844
2845         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2846                 return -EINVAL;
2847
2848         if (HAS_GMCH(dev_priv) &&
2849             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2850                 return -EINVAL;
2851
2852         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2853                 return -EINVAL;
2854
2855         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2856                 return -EINVAL;
2857
2858         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2859         if (ret < 0)
2860                 return ret;
2861
2862         pipe_config->limited_color_range =
2863                 intel_dp_limited_color_range(pipe_config, conn_state);
2864
2865         if (pipe_config->dsc.compression_enable)
2866                 output_bpp = pipe_config->dsc.compressed_bpp;
2867         else
2868                 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
2869                                                  pipe_config->pipe_bpp);
2870
2871         intel_link_compute_m_n(output_bpp,
2872                                pipe_config->lane_count,
2873                                adjusted_mode->crtc_clock,
2874                                pipe_config->port_clock,
2875                                &pipe_config->dp_m_n,
2876                                constant_n, pipe_config->fec_enable);
2877
2878         if (!HAS_DDI(dev_priv))
2879                 intel_dp_set_clock(encoder, pipe_config);
2880
2881         intel_psr_compute_config(intel_dp, pipe_config);
2882         intel_dp_drrs_compute_config(intel_dp, pipe_config, output_bpp,
2883                                      constant_n);
2884         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2885         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2886
2887         return 0;
2888 }
2889
2890 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2891                               int link_rate, int lane_count)
2892 {
2893         intel_dp->link_trained = false;
2894         intel_dp->link_rate = link_rate;
2895         intel_dp->lane_count = lane_count;
2896 }
2897
2898 static void intel_dp_prepare(struct intel_encoder *encoder,
2899                              const struct intel_crtc_state *pipe_config)
2900 {
2901         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2902         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2903         enum port port = encoder->port;
2904         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2905         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2906
2907         intel_dp_set_link_params(intel_dp,
2908                                  pipe_config->port_clock,
2909                                  pipe_config->lane_count);
2910
2911         /*
2912          * There are four kinds of DP registers:
2913          *
2914          *      IBX PCH
2915          *      SNB CPU
2916          *      IVB CPU
2917          *      CPT PCH
2918          *
2919          * IBX PCH and CPU are the same for almost everything,
2920          * except that the CPU DP PLL is configured in this
2921          * register
2922          *
2923          * CPT PCH is quite different, having many bits moved
2924          * to the TRANS_DP_CTL register instead. That
2925          * configuration happens (oddly) in ilk_pch_enable
2926          */
2927
2928         /* Preserve the BIOS-computed detected bit. This is
2929          * supposed to be read-only.
2930          */
2931         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
2932
2933         /* Handle DP bits in common between all three register formats */
2934         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2935         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2936
2937         /* Split out the IBX/CPU vs CPT settings */
2938
2939         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2940                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2941                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2942                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2943                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2944                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2945
2946                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2947                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2948
2949                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2950         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2951                 u32 trans_dp;
2952
2953                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2954
2955                 trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe));
2956                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2957                         trans_dp |= TRANS_DP_ENH_FRAMING;
2958                 else
2959                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2960                 intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp);
2961         } else {
2962                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2963                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2964
2965                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2966                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2967                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2968                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2969                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2970
2971                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2972                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2973
2974                 if (IS_CHERRYVIEW(dev_priv))
2975                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2976                 else
2977                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2978         }
2979 }
2980
2981 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2982 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2983
2984 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2985 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2986
2987 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2988 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2989
2990 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2991
2992 static void wait_panel_status(struct intel_dp *intel_dp,
2993                                        u32 mask,
2994                                        u32 value)
2995 {
2996         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2997         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2998
2999         lockdep_assert_held(&dev_priv->pps_mutex);
3000
3001         intel_pps_verify_state(intel_dp);
3002
3003         pp_stat_reg = _pp_stat_reg(intel_dp);
3004         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3005
3006         drm_dbg_kms(&dev_priv->drm,
3007                     "mask %08x value %08x status %08x control %08x\n",
3008                     mask, value,
3009                     intel_de_read(dev_priv, pp_stat_reg),
3010                     intel_de_read(dev_priv, pp_ctrl_reg));
3011
3012         if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
3013                                        mask, value, 5000))
3014                 drm_err(&dev_priv->drm,
3015                         "Panel status timeout: status %08x control %08x\n",
3016                         intel_de_read(dev_priv, pp_stat_reg),
3017                         intel_de_read(dev_priv, pp_ctrl_reg));
3018
3019         drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
3020 }
3021
3022 static void wait_panel_on(struct intel_dp *intel_dp)
3023 {
3024         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3025
3026         drm_dbg_kms(&i915->drm, "Wait for panel power on\n");
3027         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
3028 }
3029
3030 static void wait_panel_off(struct intel_dp *intel_dp)
3031 {
3032         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3033
3034         drm_dbg_kms(&i915->drm, "Wait for panel power off time\n");
3035         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
3036 }
3037
3038 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
3039 {
3040         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3041         ktime_t panel_power_on_time;
3042         s64 panel_power_off_duration;
3043
3044         drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n");
3045
3046         /* take the difference of currrent time and panel power off time
3047          * and then make panel wait for t11_t12 if needed. */
3048         panel_power_on_time = ktime_get_boottime();
3049         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
3050
3051         /* When we disable the VDD override bit last we have to do the manual
3052          * wait. */
3053         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
3054                 wait_remaining_ms_from_jiffies(jiffies,
3055                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
3056
3057         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
3058 }
3059
3060 static void wait_backlight_on(struct intel_dp *intel_dp)
3061 {
3062         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
3063                                        intel_dp->backlight_on_delay);
3064 }
3065
3066 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
3067 {
3068         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
3069                                        intel_dp->backlight_off_delay);
3070 }
3071
3072 /* Read the current pp_control value, unlocking the register if it
3073  * is locked
3074  */
3075
3076 static  u32 ilk_get_pp_control(struct intel_dp *intel_dp)
3077 {
3078         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3079         u32 control;
3080
3081         lockdep_assert_held(&dev_priv->pps_mutex);
3082
3083         control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
3084         if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
3085                         (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
3086                 control &= ~PANEL_UNLOCK_MASK;
3087                 control |= PANEL_UNLOCK_REGS;
3088         }
3089         return control;
3090 }
3091
3092 /*
3093  * Must be paired with edp_panel_vdd_off().
3094  * Must hold pps_mutex around the whole on/off sequence.
3095  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
3096  */
3097 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
3098 {
3099         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3100         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3101         u32 pp;
3102         i915_reg_t pp_stat_reg, pp_ctrl_reg;
3103         bool need_to_disable = !intel_dp->want_panel_vdd;
3104
3105         lockdep_assert_held(&dev_priv->pps_mutex);
3106
3107         if (!intel_dp_is_edp(intel_dp))
3108                 return false;
3109
3110         cancel_delayed_work(&intel_dp->panel_vdd_work);
3111         intel_dp->want_panel_vdd = true;
3112
3113         if (edp_have_panel_vdd(intel_dp))
3114                 return need_to_disable;
3115
3116         intel_display_power_get(dev_priv,
3117                                 intel_aux_power_domain(dig_port));
3118
3119         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
3120                     dig_port->base.base.base.id,
3121                     dig_port->base.base.name);
3122
3123         if (!edp_have_panel_power(intel_dp))
3124                 wait_panel_power_cycle(intel_dp);
3125
3126         pp = ilk_get_pp_control(intel_dp);
3127         pp |= EDP_FORCE_VDD;
3128
3129         pp_stat_reg = _pp_stat_reg(intel_dp);
3130         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3131
3132         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3133         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3134         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
3135                     intel_de_read(dev_priv, pp_stat_reg),
3136                     intel_de_read(dev_priv, pp_ctrl_reg));
3137         /*
3138          * If the panel wasn't on, delay before accessing aux channel
3139          */
3140         if (!edp_have_panel_power(intel_dp)) {
3141                 drm_dbg_kms(&dev_priv->drm,
3142                             "[ENCODER:%d:%s] panel power wasn't enabled\n",
3143                             dig_port->base.base.base.id,
3144                             dig_port->base.base.name);
3145                 msleep(intel_dp->panel_power_up_delay);
3146         }
3147
3148         return need_to_disable;
3149 }
3150
3151 /*
3152  * Must be paired with intel_edp_panel_vdd_off() or
3153  * intel_edp_panel_off().
3154  * Nested calls to these functions are not allowed since
3155  * we drop the lock. Caller must use some higher level
3156  * locking to prevent nested calls from other threads.
3157  */
3158 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
3159 {
3160         intel_wakeref_t wakeref;
3161         bool vdd;
3162
3163         if (!intel_dp_is_edp(intel_dp))
3164                 return;
3165
3166         vdd = false;
3167         with_pps_lock(intel_dp, wakeref)
3168                 vdd = edp_panel_vdd_on(intel_dp);
3169         I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
3170                         dp_to_dig_port(intel_dp)->base.base.base.id,
3171                         dp_to_dig_port(intel_dp)->base.base.name);
3172 }
3173
3174 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
3175 {
3176         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3177         struct intel_digital_port *dig_port =
3178                 dp_to_dig_port(intel_dp);
3179         u32 pp;
3180         i915_reg_t pp_stat_reg, pp_ctrl_reg;
3181
3182         lockdep_assert_held(&dev_priv->pps_mutex);
3183
3184         drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
3185
3186         if (!edp_have_panel_vdd(intel_dp))
3187                 return;
3188
3189         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n",
3190                     dig_port->base.base.base.id,
3191                     dig_port->base.base.name);
3192
3193         pp = ilk_get_pp_control(intel_dp);
3194         pp &= ~EDP_FORCE_VDD;
3195
3196         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3197         pp_stat_reg = _pp_stat_reg(intel_dp);
3198
3199         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3200         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3201
3202         /* Make sure sequencer is idle before allowing subsequent activity */
3203         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
3204                     intel_de_read(dev_priv, pp_stat_reg),
3205                     intel_de_read(dev_priv, pp_ctrl_reg));
3206
3207         if ((pp & PANEL_POWER_ON) == 0)
3208                 intel_dp->panel_power_off_time = ktime_get_boottime();
3209
3210         intel_display_power_put_unchecked(dev_priv,
3211                                           intel_aux_power_domain(dig_port));
3212 }
3213
3214 static void edp_panel_vdd_work(struct work_struct *__work)
3215 {
3216         struct intel_dp *intel_dp =
3217                 container_of(to_delayed_work(__work),
3218                              struct intel_dp, panel_vdd_work);
3219         intel_wakeref_t wakeref;
3220
3221         with_pps_lock(intel_dp, wakeref) {
3222                 if (!intel_dp->want_panel_vdd)
3223                         edp_panel_vdd_off_sync(intel_dp);
3224         }
3225 }
3226
3227 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
3228 {
3229         unsigned long delay;
3230
3231         /*
3232          * Queue the timer to fire a long time from now (relative to the power
3233          * down delay) to keep the panel power up across a sequence of
3234          * operations.
3235          */
3236         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
3237         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
3238 }
3239
3240 /*
3241  * Must be paired with edp_panel_vdd_on().
3242  * Must hold pps_mutex around the whole on/off sequence.
3243  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
3244  */
3245 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
3246 {
3247         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3248
3249         lockdep_assert_held(&dev_priv->pps_mutex);
3250
3251         if (!intel_dp_is_edp(intel_dp))
3252                 return;
3253
3254         I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
3255                         dp_to_dig_port(intel_dp)->base.base.base.id,
3256                         dp_to_dig_port(intel_dp)->base.base.name);
3257
3258         intel_dp->want_panel_vdd = false;
3259
3260         if (sync)
3261                 edp_panel_vdd_off_sync(intel_dp);
3262         else
3263                 edp_panel_vdd_schedule_off(intel_dp);
3264 }
3265
3266 static void edp_panel_on(struct intel_dp *intel_dp)
3267 {
3268         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3269         u32 pp;
3270         i915_reg_t pp_ctrl_reg;
3271
3272         lockdep_assert_held(&dev_priv->pps_mutex);
3273
3274         if (!intel_dp_is_edp(intel_dp))
3275                 return;
3276
3277         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n",
3278                     dp_to_dig_port(intel_dp)->base.base.base.id,
3279                     dp_to_dig_port(intel_dp)->base.base.name);
3280
3281         if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
3282                      "[ENCODER:%d:%s] panel power already on\n",
3283                      dp_to_dig_port(intel_dp)->base.base.base.id,
3284                      dp_to_dig_port(intel_dp)->base.base.name))
3285                 return;
3286
3287         wait_panel_power_cycle(intel_dp);
3288
3289         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3290         pp = ilk_get_pp_control(intel_dp);
3291         if (IS_GEN(dev_priv, 5)) {
3292                 /* ILK workaround: disable reset around power sequence */
3293                 pp &= ~PANEL_POWER_RESET;
3294                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3295                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3296         }
3297
3298         pp |= PANEL_POWER_ON;
3299         if (!IS_GEN(dev_priv, 5))
3300                 pp |= PANEL_POWER_RESET;
3301
3302         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3303         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3304
3305         wait_panel_on(intel_dp);
3306         intel_dp->last_power_on = jiffies;
3307
3308         if (IS_GEN(dev_priv, 5)) {
3309                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
3310                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3311                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3312         }
3313 }
3314
3315 void intel_edp_panel_on(struct intel_dp *intel_dp)
3316 {
3317         intel_wakeref_t wakeref;
3318
3319         if (!intel_dp_is_edp(intel_dp))
3320                 return;
3321
3322         with_pps_lock(intel_dp, wakeref)
3323                 edp_panel_on(intel_dp);
3324 }
3325
3326
3327 static void edp_panel_off(struct intel_dp *intel_dp)
3328 {
3329         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3330         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3331         u32 pp;
3332         i915_reg_t pp_ctrl_reg;
3333
3334         lockdep_assert_held(&dev_priv->pps_mutex);
3335
3336         if (!intel_dp_is_edp(intel_dp))
3337                 return;
3338
3339         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
3340                     dig_port->base.base.base.id, dig_port->base.base.name);
3341
3342         drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
3343                  "Need [ENCODER:%d:%s] VDD to turn off panel\n",
3344                  dig_port->base.base.base.id, dig_port->base.base.name);
3345
3346         pp = ilk_get_pp_control(intel_dp);
3347         /* We need to switch off panel power _and_ force vdd, for otherwise some
3348          * panels get very unhappy and cease to work. */
3349         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
3350                 EDP_BLC_ENABLE);
3351
3352         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3353
3354         intel_dp->want_panel_vdd = false;
3355
3356         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3357         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3358
3359         wait_panel_off(intel_dp);
3360         intel_dp->panel_power_off_time = ktime_get_boottime();
3361
3362         /* We got a reference when we enabled the VDD. */
3363         intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
3364 }
3365
3366 void intel_edp_panel_off(struct intel_dp *intel_dp)
3367 {
3368         intel_wakeref_t wakeref;
3369
3370         if (!intel_dp_is_edp(intel_dp))
3371                 return;
3372
3373         with_pps_lock(intel_dp, wakeref)
3374                 edp_panel_off(intel_dp);
3375 }
3376
3377 /* Enable backlight in the panel power control. */
3378 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
3379 {
3380         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3381         intel_wakeref_t wakeref;
3382
3383         /*
3384          * If we enable the backlight right away following a panel power
3385          * on, we may see slight flicker as the panel syncs with the eDP
3386          * link.  So delay a bit to make sure the image is solid before
3387          * allowing it to appear.
3388          */
3389         wait_backlight_on(intel_dp);
3390
3391         with_pps_lock(intel_dp, wakeref) {
3392                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3393                 u32 pp;
3394
3395                 pp = ilk_get_pp_control(intel_dp);
3396                 pp |= EDP_BLC_ENABLE;
3397
3398                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3399                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3400         }
3401 }
3402
3403 /* Enable backlight PWM and backlight PP control. */
3404 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3405                             const struct drm_connector_state *conn_state)
3406 {
3407         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3408         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3409
3410         if (!intel_dp_is_edp(intel_dp))
3411                 return;
3412
3413         drm_dbg_kms(&i915->drm, "\n");
3414
3415         intel_panel_enable_backlight(crtc_state, conn_state);
3416         _intel_edp_backlight_on(intel_dp);
3417 }
3418
3419 /* Disable backlight in the panel power control. */
3420 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
3421 {
3422         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3423         intel_wakeref_t wakeref;
3424
3425         if (!intel_dp_is_edp(intel_dp))
3426                 return;
3427
3428         with_pps_lock(intel_dp, wakeref) {
3429                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3430                 u32 pp;
3431
3432                 pp = ilk_get_pp_control(intel_dp);
3433                 pp &= ~EDP_BLC_ENABLE;
3434
3435                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3436                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3437         }
3438
3439         intel_dp->last_backlight_off = jiffies;
3440         edp_wait_backlight_off(intel_dp);
3441 }
3442
3443 /* Disable backlight PP control and backlight PWM. */
3444 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3445 {
3446         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3447         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3448
3449         if (!intel_dp_is_edp(intel_dp))
3450                 return;
3451
3452         drm_dbg_kms(&i915->drm, "\n");
3453
3454         _intel_edp_backlight_off(intel_dp);
3455         intel_panel_disable_backlight(old_conn_state);
3456 }
3457
3458 /*
3459  * Hook for controlling the panel power control backlight through the bl_power
3460  * sysfs attribute. Take care to handle multiple calls.
3461  */
3462 static void intel_edp_backlight_power(struct intel_connector *connector,
3463                                       bool enable)
3464 {
3465         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3466         struct intel_dp *intel_dp = intel_attached_dp(connector);
3467         intel_wakeref_t wakeref;
3468         bool is_enabled;
3469
3470         is_enabled = false;
3471         with_pps_lock(intel_dp, wakeref)
3472                 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
3473         if (is_enabled == enable)
3474                 return;
3475
3476         drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
3477                     enable ? "enable" : "disable");
3478
3479         if (enable)
3480                 _intel_edp_backlight_on(intel_dp);
3481         else
3482                 _intel_edp_backlight_off(intel_dp);
3483 }
3484
3485 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
3486 {
3487         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3488         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3489         bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN;
3490
3491         I915_STATE_WARN(cur_state != state,
3492                         "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
3493                         dig_port->base.base.base.id, dig_port->base.base.name,
3494                         onoff(state), onoff(cur_state));
3495 }
3496 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
3497
3498 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
3499 {
3500         bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE;
3501
3502         I915_STATE_WARN(cur_state != state,
3503                         "eDP PLL state assertion failure (expected %s, current %s)\n",
3504                         onoff(state), onoff(cur_state));
3505 }
3506 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
3507 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
3508
3509 static void ilk_edp_pll_on(struct intel_dp *intel_dp,
3510                            const struct intel_crtc_state *pipe_config)
3511 {
3512         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3513         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3514
3515         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
3516         assert_dp_port_disabled(intel_dp);
3517         assert_edp_pll_disabled(dev_priv);
3518
3519         drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",
3520                     pipe_config->port_clock);
3521
3522         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
3523
3524         if (pipe_config->port_clock == 162000)
3525                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
3526         else
3527                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
3528
3529         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3530         intel_de_posting_read(dev_priv, DP_A);
3531         udelay(500);
3532
3533         /*
3534          * [DevILK] Work around required when enabling DP PLL
3535          * while a pipe is enabled going to FDI:
3536          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
3537          * 2. Program DP PLL enable
3538          */
3539         if (IS_GEN(dev_priv, 5))
3540                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
3541
3542         intel_dp->DP |= DP_PLL_ENABLE;
3543
3544         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3545         intel_de_posting_read(dev_priv, DP_A);
3546         udelay(200);
3547 }
3548
3549 static void ilk_edp_pll_off(struct intel_dp *intel_dp,
3550                             const struct intel_crtc_state *old_crtc_state)
3551 {
3552         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3553         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3554
3555         assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
3556         assert_dp_port_disabled(intel_dp);
3557         assert_edp_pll_enabled(dev_priv);
3558
3559         drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n");
3560
3561         intel_dp->DP &= ~DP_PLL_ENABLE;
3562
3563         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3564         intel_de_posting_read(dev_priv, DP_A);
3565         udelay(200);
3566 }
3567
3568 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3569 {
3570         /*
3571          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3572          * be capable of signalling downstream hpd with a long pulse.
3573          * Whether or not that means D3 is safe to use is not clear,
3574          * but let's assume so until proven otherwise.
3575          *
3576          * FIXME should really check all downstream ports...
3577          */
3578         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3579                 drm_dp_is_branch(intel_dp->dpcd) &&
3580                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3581 }
3582
3583 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
3584                                            const struct intel_crtc_state *crtc_state,
3585                                            bool enable)
3586 {
3587         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3588         int ret;
3589
3590         if (!crtc_state->dsc.compression_enable)
3591                 return;
3592
3593         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
3594                                  enable ? DP_DECOMPRESSION_EN : 0);
3595         if (ret < 0)
3596                 drm_dbg_kms(&i915->drm,
3597                             "Failed to %s sink decompression state\n",
3598                             enable ? "enable" : "disable");
3599 }
3600
3601 /* If the device supports it, try to set the power state appropriately */
3602 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
3603 {
3604         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3605         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3606         int ret, i;
3607
3608         /* Should have a valid DPCD by this point */
3609         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3610                 return;
3611
3612         if (mode != DP_SET_POWER_D0) {
3613                 if (downstream_hpd_needs_d0(intel_dp))
3614                         return;
3615
3616                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3617         } else {
3618                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3619
3620                 lspcon_resume(dp_to_dig_port(intel_dp));
3621
3622                 /*
3623                  * When turning on, we need to retry for 1ms to give the sink
3624                  * time to wake up.
3625                  */
3626                 for (i = 0; i < 3; i++) {
3627                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3628                         if (ret == 1)
3629                                 break;
3630                         msleep(1);
3631                 }
3632
3633                 if (ret == 1 && lspcon->active)
3634                         lspcon_wait_pcon_mode(lspcon);
3635         }
3636
3637         if (ret != 1)
3638                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
3639                             encoder->base.base.id, encoder->base.name,
3640                             mode == DP_SET_POWER_D0 ? "D0" : "D3");
3641 }
3642
3643 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
3644                                  enum port port, enum pipe *pipe)
3645 {
3646         enum pipe p;
3647
3648         for_each_pipe(dev_priv, p) {
3649                 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p));
3650
3651                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
3652                         *pipe = p;
3653                         return true;
3654                 }
3655         }
3656
3657         drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n",
3658                     port_name(port));
3659
3660         /* must initialize pipe to something for the asserts */
3661         *pipe = PIPE_A;
3662
3663         return false;
3664 }
3665
3666 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
3667                            i915_reg_t dp_reg, enum port port,
3668                            enum pipe *pipe)
3669 {
3670         bool ret;
3671         u32 val;
3672
3673         val = intel_de_read(dev_priv, dp_reg);
3674
3675         ret = val & DP_PORT_EN;
3676
3677         /* asserts want to know the pipe even if the port is disabled */
3678         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3679                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
3680         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3681                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3682         else if (IS_CHERRYVIEW(dev_priv))
3683                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3684         else
3685                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3686
3687         return ret;
3688 }
3689
3690 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3691                                   enum pipe *pipe)
3692 {
3693         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3694         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3695         intel_wakeref_t wakeref;
3696         bool ret;
3697
3698         wakeref = intel_display_power_get_if_enabled(dev_priv,
3699                                                      encoder->power_domain);
3700         if (!wakeref)
3701                 return false;
3702
3703         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3704                                     encoder->port, pipe);
3705
3706         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3707
3708         return ret;
3709 }
3710
3711 static void intel_dp_get_config(struct intel_encoder *encoder,
3712                                 struct intel_crtc_state *pipe_config)
3713 {
3714         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3715         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3716         u32 tmp, flags = 0;
3717         enum port port = encoder->port;
3718         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3719
3720         if (encoder->type == INTEL_OUTPUT_EDP)
3721                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3722         else
3723                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3724
3725         tmp = intel_de_read(dev_priv, intel_dp->output_reg);
3726
3727         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3728
3729         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3730                 u32 trans_dp = intel_de_read(dev_priv,
3731                                              TRANS_DP_CTL(crtc->pipe));
3732
3733                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3734                         flags |= DRM_MODE_FLAG_PHSYNC;
3735                 else
3736                         flags |= DRM_MODE_FLAG_NHSYNC;
3737
3738                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3739                         flags |= DRM_MODE_FLAG_PVSYNC;
3740                 else
3741                         flags |= DRM_MODE_FLAG_NVSYNC;
3742         } else {
3743                 if (tmp & DP_SYNC_HS_HIGH)
3744                         flags |= DRM_MODE_FLAG_PHSYNC;
3745                 else
3746                         flags |= DRM_MODE_FLAG_NHSYNC;
3747
3748                 if (tmp & DP_SYNC_VS_HIGH)
3749                         flags |= DRM_MODE_FLAG_PVSYNC;
3750                 else
3751                         flags |= DRM_MODE_FLAG_NVSYNC;
3752         }
3753
3754         pipe_config->hw.adjusted_mode.flags |= flags;
3755
3756         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3757                 pipe_config->limited_color_range = true;
3758
3759         pipe_config->lane_count =
3760                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3761
3762         intel_dp_get_m_n(crtc, pipe_config);
3763
3764         if (port == PORT_A) {
3765                 if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3766                         pipe_config->port_clock = 162000;
3767                 else
3768                         pipe_config->port_clock = 270000;
3769         }
3770
3771         pipe_config->hw.adjusted_mode.crtc_clock =
3772                 intel_dotclock_calculate(pipe_config->port_clock,
3773                                          &pipe_config->dp_m_n);
3774
3775         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3776             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3777                 /*
3778                  * This is a big fat ugly hack.
3779                  *
3780                  * Some machines in UEFI boot mode provide us a VBT that has 18
3781                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3782                  * unknown we fail to light up. Yet the same BIOS boots up with
3783                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3784                  * max, not what it tells us to use.
3785                  *
3786                  * Note: This will still be broken if the eDP panel is not lit
3787                  * up by the BIOS, and thus we can't get the mode at module
3788                  * load.
3789                  */
3790                 drm_dbg_kms(&dev_priv->drm,
3791                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3792                             pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3793                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3794         }
3795 }
3796
3797 static bool
3798 intel_dp_get_dpcd(struct intel_dp *intel_dp);
3799
3800 /**
3801  * intel_dp_sync_state - sync the encoder state during init/resume
3802  * @encoder: intel encoder to sync
3803  * @crtc_state: state for the CRTC connected to the encoder
3804  *
3805  * Sync any state stored in the encoder wrt. HW state during driver init
3806  * and system resume.
3807  */
3808 void intel_dp_sync_state(struct intel_encoder *encoder,
3809                          const struct intel_crtc_state *crtc_state)
3810 {
3811         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3812
3813         /*
3814          * Don't clobber DPCD if it's been already read out during output
3815          * setup (eDP) or detect.
3816          */
3817         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3818                 intel_dp_get_dpcd(intel_dp);
3819
3820         intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
3821         intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
3822 }
3823
3824 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
3825                                     struct intel_crtc_state *crtc_state)
3826 {
3827         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3828         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3829
3830         /*
3831          * If BIOS has set an unsupported or non-standard link rate for some
3832          * reason force an encoder recompute and full modeset.
3833          */
3834         if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
3835                                 crtc_state->port_clock) < 0) {
3836                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
3837                 crtc_state->uapi.connectors_changed = true;
3838                 return false;
3839         }
3840
3841         /*
3842          * FIXME hack to force full modeset when DSC is being used.
3843          *
3844          * As long as we do not have full state readout and config comparison
3845          * of crtc_state->dsc, we have no way to ensure reliable fastset.
3846          * Remove once we have readout for DSC.
3847          */
3848         if (crtc_state->dsc.compression_enable) {
3849                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
3850                 crtc_state->uapi.mode_changed = true;
3851                 return false;
3852         }
3853
3854         if (CAN_PSR(i915) && intel_dp_is_edp(intel_dp)) {
3855                 drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
3856                 crtc_state->uapi.mode_changed = true;
3857                 return false;
3858         }
3859
3860         return true;
3861 }
3862
3863 static void intel_disable_dp(struct intel_atomic_state *state,
3864                              struct intel_encoder *encoder,
3865                              const struct intel_crtc_state *old_crtc_state,
3866                              const struct drm_connector_state *old_conn_state)
3867 {
3868         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3869
3870         intel_dp->link_trained = false;
3871
3872         if (old_crtc_state->has_audio)
3873                 intel_audio_codec_disable(encoder,
3874                                           old_crtc_state, old_conn_state);
3875
3876         /* Make sure the panel is off before trying to change the mode. But also
3877          * ensure that we have vdd while we switch off the panel. */
3878         intel_edp_panel_vdd_on(intel_dp);
3879         intel_edp_backlight_off(old_conn_state);
3880         intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
3881         intel_edp_panel_off(intel_dp);
3882         intel_dp->frl.is_trained = false;
3883         intel_dp->frl.trained_rate_gbps = 0;
3884 }
3885
3886 static void g4x_disable_dp(struct intel_atomic_state *state,
3887                            struct intel_encoder *encoder,
3888                            const struct intel_crtc_state *old_crtc_state,
3889                            const struct drm_connector_state *old_conn_state)
3890 {
3891         intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3892 }
3893
3894 static void vlv_disable_dp(struct intel_atomic_state *state,
3895                            struct intel_encoder *encoder,
3896                            const struct intel_crtc_state *old_crtc_state,
3897                            const struct drm_connector_state *old_conn_state)
3898 {
3899         intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3900 }
3901
3902 static void g4x_post_disable_dp(struct intel_atomic_state *state,
3903                                 struct intel_encoder *encoder,
3904                                 const struct intel_crtc_state *old_crtc_state,
3905                                 const struct drm_connector_state *old_conn_state)
3906 {
3907         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3908         enum port port = encoder->port;
3909
3910         /*
3911          * Bspec does not list a specific disable sequence for g4x DP.
3912          * Follow the ilk+ sequence (disable pipe before the port) for
3913          * g4x DP as it does not suffer from underruns like the normal
3914          * g4x modeset sequence (disable pipe after the port).
3915          */
3916         intel_dp_link_down(encoder, old_crtc_state);
3917
3918         /* Only ilk+ has port A */
3919         if (port == PORT_A)
3920                 ilk_edp_pll_off(intel_dp, old_crtc_state);
3921 }
3922
3923 static void vlv_post_disable_dp(struct intel_atomic_state *state,
3924                                 struct intel_encoder *encoder,
3925                                 const struct intel_crtc_state *old_crtc_state,
3926                                 const struct drm_connector_state *old_conn_state)
3927 {
3928         intel_dp_link_down(encoder, old_crtc_state);
3929 }
3930
3931 static void chv_post_disable_dp(struct intel_atomic_state *state,
3932                                 struct intel_encoder *encoder,
3933                                 const struct intel_crtc_state *old_crtc_state,
3934                                 const struct drm_connector_state *old_conn_state)
3935 {
3936         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3937
3938         intel_dp_link_down(encoder, old_crtc_state);
3939
3940         vlv_dpio_get(dev_priv);
3941
3942         /* Assert data lane reset */
3943         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3944
3945         vlv_dpio_put(dev_priv);
3946 }
3947
3948 static void
3949 cpt_set_link_train(struct intel_dp *intel_dp,
3950                    const struct intel_crtc_state *crtc_state,
3951                    u8 dp_train_pat)
3952 {
3953         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3954         u32 *DP = &intel_dp->DP;
3955
3956         *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3957
3958         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
3959         case DP_TRAINING_PATTERN_DISABLE:
3960                 *DP |= DP_LINK_TRAIN_OFF_CPT;
3961                 break;
3962         case DP_TRAINING_PATTERN_1:
3963                 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3964                 break;
3965         case DP_TRAINING_PATTERN_2:
3966                 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3967                 break;
3968         case DP_TRAINING_PATTERN_3:
3969                 drm_dbg_kms(&dev_priv->drm,
3970                             "TPS3 not supported, using TPS2 instead\n");
3971                 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3972                 break;
3973         }
3974
3975         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3976         intel_de_posting_read(dev_priv, intel_dp->output_reg);
3977 }
3978
3979 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
3980 {
3981         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3982
3983         /* Clear the cached register set to avoid using stale values */
3984
3985         memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
3986
3987         if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
3988                              intel_dp->pcon_dsc_dpcd,
3989                              sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
3990                 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
3991                         DP_PCON_DSC_ENCODER);
3992
3993         drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
3994                     (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
3995 }
3996
3997 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
3998 {
3999         int bw_gbps[] = {9, 18, 24, 32, 40, 48};
4000         int i;
4001
4002         for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
4003                 if (frl_bw_mask & (1 << i))
4004                         return bw_gbps[i];
4005         }
4006         return 0;
4007 }
4008
4009 static int intel_dp_pcon_set_frl_mask(int max_frl)
4010 {
4011         switch (max_frl) {
4012         case 48:
4013                 return DP_PCON_FRL_BW_MASK_48GBPS;
4014         case 40:
4015                 return DP_PCON_FRL_BW_MASK_40GBPS;
4016         case 32:
4017                 return DP_PCON_FRL_BW_MASK_32GBPS;
4018         case 24:
4019                 return DP_PCON_FRL_BW_MASK_24GBPS;
4020         case 18:
4021                 return DP_PCON_FRL_BW_MASK_18GBPS;
4022         case 9:
4023                 return DP_PCON_FRL_BW_MASK_9GBPS;
4024         }
4025
4026         return 0;
4027 }
4028
4029 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
4030 {
4031         struct intel_connector *intel_connector = intel_dp->attached_connector;
4032         struct drm_connector *connector = &intel_connector->base;
4033         int max_frl_rate;
4034         int max_lanes, rate_per_lane;
4035         int max_dsc_lanes, dsc_rate_per_lane;
4036
4037         max_lanes = connector->display_info.hdmi.max_lanes;
4038         rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
4039         max_frl_rate = max_lanes * rate_per_lane;
4040
4041         if (connector->display_info.hdmi.dsc_cap.v_1p2) {
4042                 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
4043                 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
4044                 if (max_dsc_lanes && dsc_rate_per_lane)
4045                         max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
4046         }
4047
4048         return max_frl_rate;
4049 }
4050
4051 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
4052 {
4053 #define PCON_EXTENDED_TRAIN_MODE (1 > 0)
4054 #define PCON_CONCURRENT_MODE (1 > 0)
4055 #define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE
4056 #define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE
4057 #define TIMEOUT_FRL_READY_MS 500
4058 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
4059
4060         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4061         int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
4062         u8 max_frl_bw_mask = 0, frl_trained_mask;
4063         bool is_active;
4064
4065         ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
4066         if (ret < 0)
4067                 return ret;
4068
4069         max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
4070         drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
4071
4072         max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
4073         drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
4074
4075         max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
4076
4077         if (max_frl_bw <= 0)
4078                 return -EINVAL;
4079
4080         ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
4081         if (ret < 0)
4082                 return ret;
4083         /* Wait for PCON to be FRL Ready */
4084         wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
4085
4086         if (!is_active)
4087                 return -ETIMEDOUT;
4088
4089         max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
4090         ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE);
4091         if (ret < 0)
4092                 return ret;
4093         ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE);
4094         if (ret < 0)
4095                 return ret;
4096         ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
4097         if (ret < 0)
4098                 return ret;
4099         /*
4100          * Wait for FRL to be completed
4101          * Check if the HDMI Link is up and active.
4102          */
4103         wait_for(is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux) == true, TIMEOUT_HDMI_LINK_ACTIVE_MS);
4104
4105         if (!is_active)
4106                 return -ETIMEDOUT;
4107
4108         /* Verify HDMI Link configuration shows FRL Mode */
4109         if (drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, &frl_trained_mask) !=
4110             DP_PCON_HDMI_MODE_FRL) {
4111                 drm_dbg(&i915->drm, "HDMI couldn't be trained in FRL Mode\n");
4112                 return -EINVAL;
4113         }
4114         drm_dbg(&i915->drm, "MAX_FRL_MASK = %u, FRL_TRAINED_MASK = %u\n", max_frl_bw_mask, frl_trained_mask);
4115
4116         intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
4117         intel_dp->frl.is_trained = true;
4118         drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
4119
4120         return 0;
4121 }
4122
4123 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
4124 {
4125         if (drm_dp_is_branch(intel_dp->dpcd) &&
4126             intel_dp->has_hdmi_sink &&
4127             intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
4128                 return true;
4129
4130         return false;
4131 }
4132
4133 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
4134 {
4135         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4136
4137         /* Always go for FRL training if supported */
4138         if (!intel_dp_is_hdmi_2_1_sink(intel_dp) ||
4139             intel_dp->frl.is_trained)
4140                 return;
4141
4142         if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
4143                 int ret, mode;
4144
4145                 drm_dbg(&dev_priv->drm, "Couldnt set FRL mode, continuing with TMDS mode\n");
4146                 ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
4147                 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
4148
4149                 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
4150                         drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
4151         } else {
4152                 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
4153         }
4154 }
4155
4156 static int
4157 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
4158 {
4159         int vactive = crtc_state->hw.adjusted_mode.vdisplay;
4160
4161         return intel_hdmi_dsc_get_slice_height(vactive);
4162 }
4163
4164 static int
4165 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
4166                              const struct intel_crtc_state *crtc_state)
4167 {
4168         struct intel_connector *intel_connector = intel_dp->attached_connector;
4169         struct drm_connector *connector = &intel_connector->base;
4170         int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
4171         int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
4172         int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
4173         int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
4174
4175         return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
4176                                              pcon_max_slice_width,
4177                                              hdmi_max_slices, hdmi_throughput);
4178 }
4179
4180 static int
4181 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
4182                           const struct intel_crtc_state *crtc_state,
4183                           int num_slices, int slice_width)
4184 {
4185         struct intel_connector *intel_connector = intel_dp->attached_connector;
4186         struct drm_connector *connector = &intel_connector->base;
4187         int output_format = crtc_state->output_format;
4188         bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
4189         int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
4190         int hdmi_max_chunk_bytes =
4191                 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
4192
4193         return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
4194                                       num_slices, output_format, hdmi_all_bpp,
4195                                       hdmi_max_chunk_bytes);
4196 }
4197
4198 void
4199 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
4200                             const struct intel_crtc_state *crtc_state)
4201 {
4202         u8 pps_param[6];
4203         int slice_height;
4204         int slice_width;
4205         int num_slices;
4206         int bits_per_pixel;
4207         int ret;
4208         struct intel_connector *intel_connector = intel_dp->attached_connector;
4209         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4210         struct drm_connector *connector;
4211         bool hdmi_is_dsc_1_2;
4212
4213         if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
4214                 return;
4215
4216         if (!intel_connector)
4217                 return;
4218         connector = &intel_connector->base;
4219         hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
4220
4221         if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
4222             !hdmi_is_dsc_1_2)
4223                 return;
4224
4225         slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
4226         if (!slice_height)
4227                 return;
4228
4229         num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
4230         if (!num_slices)
4231                 return;
4232
4233         slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
4234                                    num_slices);
4235
4236         bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
4237                                                    num_slices, slice_width);
4238         if (!bits_per_pixel)
4239                 return;
4240
4241         pps_param[0] = slice_height & 0xFF;
4242         pps_param[1] = slice_height >> 8;
4243         pps_param[2] = slice_width & 0xFF;
4244         pps_param[3] = slice_width >> 8;
4245         pps_param[4] = bits_per_pixel & 0xFF;
4246         pps_param[5] = (bits_per_pixel >> 8) & 0x3;
4247
4248         ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
4249         if (ret < 0)
4250                 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
4251 }
4252
4253 static void
4254 g4x_set_link_train(struct intel_dp *intel_dp,
4255                    const struct intel_crtc_state *crtc_state,
4256                    u8 dp_train_pat)
4257 {
4258         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4259         u32 *DP = &intel_dp->DP;
4260
4261         *DP &= ~DP_LINK_TRAIN_MASK;
4262
4263         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
4264         case DP_TRAINING_PATTERN_DISABLE:
4265                 *DP |= DP_LINK_TRAIN_OFF;
4266                 break;
4267         case DP_TRAINING_PATTERN_1:
4268                 *DP |= DP_LINK_TRAIN_PAT_1;
4269                 break;
4270         case DP_TRAINING_PATTERN_2:
4271                 *DP |= DP_LINK_TRAIN_PAT_2;
4272                 break;
4273         case DP_TRAINING_PATTERN_3:
4274                 drm_dbg_kms(&dev_priv->drm,
4275                             "TPS3 not supported, using TPS2 instead\n");
4276                 *DP |= DP_LINK_TRAIN_PAT_2;
4277                 break;
4278         }
4279
4280         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4281         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4282 }
4283
4284 static void intel_dp_enable_port(struct intel_dp *intel_dp,
4285                                  const struct intel_crtc_state *crtc_state)
4286 {
4287         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4288
4289         /* enable with pattern 1 (as per spec) */
4290
4291         intel_dp_program_link_training_pattern(intel_dp, crtc_state,
4292                                                DP_TRAINING_PATTERN_1);
4293
4294         /*
4295          * Magic for VLV/CHV. We _must_ first set up the register
4296          * without actually enabling the port, and then do another
4297          * write to enable the port. Otherwise link training will
4298          * fail when the power sequencer is freshly used for this port.
4299          */
4300         intel_dp->DP |= DP_PORT_EN;
4301         if (crtc_state->has_audio)
4302                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
4303
4304         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4305         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4306 }
4307
4308 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp)
4309 {
4310         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4311         u8 tmp;
4312
4313         if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
4314                 return;
4315
4316         if (!drm_dp_is_branch(intel_dp->dpcd))
4317                 return;
4318
4319         tmp = intel_dp->has_hdmi_sink ?
4320                 DP_HDMI_DVI_OUTPUT_CONFIG : 0;
4321
4322         if (drm_dp_dpcd_writeb(&intel_dp->aux,
4323                                DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
4324                 drm_dbg_kms(&i915->drm, "Failed to set protocol converter HDMI mode to %s\n",
4325                             enableddisabled(intel_dp->has_hdmi_sink));
4326
4327         tmp = intel_dp->dfp.ycbcr_444_to_420 ?
4328                 DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
4329
4330         if (drm_dp_dpcd_writeb(&intel_dp->aux,
4331                                DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
4332                 drm_dbg_kms(&i915->drm,
4333                             "Failed to set protocol converter YCbCr 4:2:0 conversion mode to %s\n",
4334                             enableddisabled(intel_dp->dfp.ycbcr_444_to_420));
4335
4336         tmp = 0;
4337
4338         if (drm_dp_dpcd_writeb(&intel_dp->aux,
4339                                DP_PROTOCOL_CONVERTER_CONTROL_2, tmp) <= 0)
4340                 drm_dbg_kms(&i915->drm,
4341                             "Failed to set protocol converter YCbCr 4:2:2 conversion mode to %s\n",
4342                             enableddisabled(false));
4343 }
4344
4345 static void intel_enable_dp(struct intel_atomic_state *state,
4346                             struct intel_encoder *encoder,
4347                             const struct intel_crtc_state *pipe_config,
4348                             const struct drm_connector_state *conn_state)
4349 {
4350         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4351         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4352         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4353         u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);
4354         enum pipe pipe = crtc->pipe;
4355         intel_wakeref_t wakeref;
4356
4357         if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
4358                 return;
4359
4360         with_pps_lock(intel_dp, wakeref) {
4361                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4362                         vlv_init_panel_power_sequencer(encoder, pipe_config);
4363
4364                 intel_dp_enable_port(intel_dp, pipe_config);
4365
4366                 edp_panel_vdd_on(intel_dp);
4367                 edp_panel_on(intel_dp);
4368                 edp_panel_vdd_off(intel_dp, true);
4369         }
4370
4371         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4372                 unsigned int lane_mask = 0x0;
4373
4374                 if (IS_CHERRYVIEW(dev_priv))
4375                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
4376
4377                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
4378                                     lane_mask);
4379         }
4380
4381         intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
4382         intel_dp_configure_protocol_converter(intel_dp);
4383         intel_dp_check_frl_training(intel_dp);
4384         intel_dp_pcon_dsc_configure(intel_dp, pipe_config);
4385         intel_dp_start_link_train(intel_dp, pipe_config);
4386         intel_dp_stop_link_train(intel_dp, pipe_config);
4387
4388         if (pipe_config->has_audio) {
4389                 drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",
4390                         pipe_name(pipe));
4391                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
4392         }
4393 }
4394
4395 static void g4x_enable_dp(struct intel_atomic_state *state,
4396                           struct intel_encoder *encoder,
4397                           const struct intel_crtc_state *pipe_config,
4398                           const struct drm_connector_state *conn_state)
4399 {
4400         intel_enable_dp(state, encoder, pipe_config, conn_state);
4401         intel_edp_backlight_on(pipe_config, conn_state);
4402 }
4403
4404 static void vlv_enable_dp(struct intel_atomic_state *state,
4405                           struct intel_encoder *encoder,
4406                           const struct intel_crtc_state *pipe_config,
4407                           const struct drm_connector_state *conn_state)
4408 {
4409         intel_edp_backlight_on(pipe_config, conn_state);
4410 }
4411
4412 static void g4x_pre_enable_dp(struct intel_atomic_state *state,
4413                               struct intel_encoder *encoder,
4414                               const struct intel_crtc_state *pipe_config,
4415                               const struct drm_connector_state *conn_state)
4416 {
4417         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4418         enum port port = encoder->port;
4419
4420         intel_dp_prepare(encoder, pipe_config);
4421
4422         /* Only ilk+ has port A */
4423         if (port == PORT_A)
4424                 ilk_edp_pll_on(intel_dp, pipe_config);
4425 }
4426
4427 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
4428 {
4429         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4430         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4431         enum pipe pipe = intel_dp->pps_pipe;
4432         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
4433
4434         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
4435
4436         if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
4437                 return;
4438
4439         edp_panel_vdd_off_sync(intel_dp);
4440
4441         /*
4442          * VLV seems to get confused when multiple power sequencers
4443          * have the same port selected (even if only one has power/vdd
4444          * enabled). The failure manifests as vlv_wait_port_ready() failing
4445          * CHV on the other hand doesn't seem to mind having the same port
4446          * selected in multiple power sequencers, but let's clear the
4447          * port select always when logically disconnecting a power sequencer
4448          * from a port.
4449          */
4450         drm_dbg_kms(&dev_priv->drm,
4451                     "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
4452                     pipe_name(pipe), dig_port->base.base.base.id,
4453                     dig_port->base.base.name);
4454         intel_de_write(dev_priv, pp_on_reg, 0);
4455         intel_de_posting_read(dev_priv, pp_on_reg);
4456
4457         intel_dp->pps_pipe = INVALID_PIPE;
4458 }
4459
4460 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
4461                                       enum pipe pipe)
4462 {
4463         struct intel_encoder *encoder;
4464
4465         lockdep_assert_held(&dev_priv->pps_mutex);
4466
4467         for_each_intel_dp(&dev_priv->drm, encoder) {
4468                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4469
4470                 drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe,
4471                          "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
4472                          pipe_name(pipe), encoder->base.base.id,
4473                          encoder->base.name);
4474
4475                 if (intel_dp->pps_pipe != pipe)
4476                         continue;
4477
4478                 drm_dbg_kms(&dev_priv->drm,
4479                             "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
4480                             pipe_name(pipe), encoder->base.base.id,
4481                             encoder->base.name);
4482
4483                 /* make sure vdd is off before we steal it */
4484                 vlv_detach_power_sequencer(intel_dp);
4485         }
4486 }
4487
4488 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
4489                                            const struct intel_crtc_state *crtc_state)
4490 {
4491         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4492         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4493         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4494
4495         lockdep_assert_held(&dev_priv->pps_mutex);
4496
4497         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
4498
4499         if (intel_dp->pps_pipe != INVALID_PIPE &&
4500             intel_dp->pps_pipe != crtc->pipe) {
4501                 /*
4502                  * If another power sequencer was being used on this
4503                  * port previously make sure to turn off vdd there while
4504                  * we still have control of it.
4505                  */
4506                 vlv_detach_power_sequencer(intel_dp);
4507         }
4508
4509         /*
4510          * We may be stealing the power
4511          * sequencer from another port.
4512          */
4513         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
4514
4515         intel_dp->active_pipe = crtc->pipe;
4516
4517         if (!intel_dp_is_edp(intel_dp))
4518                 return;
4519
4520         /* now it's all ours */
4521         intel_dp->pps_pipe = crtc->pipe;
4522
4523         drm_dbg_kms(&dev_priv->drm,
4524                     "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
4525                     pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
4526                     encoder->base.name);
4527
4528         /* init power sequencer on this pipe and port */
4529         intel_dp_init_panel_power_sequencer(intel_dp);
4530         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
4531 }
4532
4533 static void vlv_pre_enable_dp(struct intel_atomic_state *state,
4534                               struct intel_encoder *encoder,
4535                               const struct intel_crtc_state *pipe_config,
4536                               const struct drm_connector_state *conn_state)
4537 {
4538         vlv_phy_pre_encoder_enable(encoder, pipe_config);
4539
4540         intel_enable_dp(state, encoder, pipe_config, conn_state);
4541 }
4542
4543 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state,
4544                                   struct intel_encoder *encoder,
4545                                   const struct intel_crtc_state *pipe_config,
4546                                   const struct drm_connector_state *conn_state)
4547 {
4548         intel_dp_prepare(encoder, pipe_config);
4549
4550         vlv_phy_pre_pll_enable(encoder, pipe_config);
4551 }
4552
4553 static void chv_pre_enable_dp(struct intel_atomic_state *state,
4554                               struct intel_encoder *encoder,
4555                               const struct intel_crtc_state *pipe_config,
4556                               const struct drm_connector_state *conn_state)
4557 {
4558         chv_phy_pre_encoder_enable(encoder, pipe_config);
4559
4560         intel_enable_dp(state, encoder, pipe_config, conn_state);
4561
4562         /* Second common lane will stay alive on its own now */
4563         chv_phy_release_cl2_override(encoder);
4564 }
4565
4566 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state,
4567                                   struct intel_encoder *encoder,
4568                                   const struct intel_crtc_state *pipe_config,
4569                                   const struct drm_connector_state *conn_state)
4570 {
4571         intel_dp_prepare(encoder, pipe_config);
4572
4573         chv_phy_pre_pll_enable(encoder, pipe_config);
4574 }
4575
4576 static void chv_dp_post_pll_disable(struct intel_atomic_state *state,
4577                                     struct intel_encoder *encoder,
4578                                     const struct intel_crtc_state *old_crtc_state,
4579                                     const struct drm_connector_state *old_conn_state)
4580 {
4581         chv_phy_post_pll_disable(encoder, old_crtc_state);
4582 }
4583
4584 static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp,
4585                                  const struct intel_crtc_state *crtc_state)
4586 {
4587         return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
4588 }
4589
4590 static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp,
4591                                  const struct intel_crtc_state *crtc_state)
4592 {
4593         return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
4594 }
4595
4596 static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp)
4597 {
4598         return DP_TRAIN_PRE_EMPH_LEVEL_2;
4599 }
4600
4601 static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)
4602 {
4603         return DP_TRAIN_PRE_EMPH_LEVEL_3;
4604 }
4605
4606 static void vlv_set_signal_levels(struct intel_dp *intel_dp,
4607                                   const struct intel_crtc_state *crtc_state)
4608 {
4609         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4610         unsigned long demph_reg_value, preemph_reg_value,
4611                 uniqtranscale_reg_value;
4612         u8 train_set = intel_dp->train_set[0];
4613
4614         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4615         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4616                 preemph_reg_value = 0x0004000;
4617                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4618                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4619                         demph_reg_value = 0x2B405555;
4620                         uniqtranscale_reg_value = 0x552AB83A;
4621                         break;
4622                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4623                         demph_reg_value = 0x2B404040;
4624                         uniqtranscale_reg_value = 0x5548B83A;
4625                         break;
4626                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4627                         demph_reg_value = 0x2B245555;
4628                         uniqtranscale_reg_value = 0x5560B83A;
4629                         break;
4630                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4631                         demph_reg_value = 0x2B405555;
4632                         uniqtranscale_reg_value = 0x5598DA3A;
4633                         break;
4634                 default:
4635                         return;
4636                 }
4637                 break;
4638         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4639                 preemph_reg_value = 0x0002000;
4640                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4641                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4642                         demph_reg_value = 0x2B404040;
4643                         uniqtranscale_reg_value = 0x5552B83A;
4644                         break;
4645                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4646                         demph_reg_value = 0x2B404848;
4647                         uniqtranscale_reg_value = 0x5580B83A;
4648                         break;
4649                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4650                         demph_reg_value = 0x2B404040;
4651                         uniqtranscale_reg_value = 0x55ADDA3A;
4652                         break;
4653                 default:
4654                         return;
4655                 }
4656                 break;
4657         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4658                 preemph_reg_value = 0x0000000;
4659                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4660                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4661                         demph_reg_value = 0x2B305555;
4662                         uniqtranscale_reg_value = 0x5570B83A;
4663                         break;
4664                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4665                         demph_reg_value = 0x2B2B4040;
4666                         uniqtranscale_reg_value = 0x55ADDA3A;
4667                         break;
4668                 default:
4669                         return;
4670                 }
4671                 break;
4672         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4673                 preemph_reg_value = 0x0006000;
4674                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4675                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4676                         demph_reg_value = 0x1B405555;
4677                         uniqtranscale_reg_value = 0x55ADDA3A;
4678                         break;
4679                 default:
4680                         return;
4681                 }
4682                 break;
4683         default:
4684                 return;
4685         }
4686
4687         vlv_set_phy_signal_level(encoder, crtc_state,
4688                                  demph_reg_value, preemph_reg_value,
4689                                  uniqtranscale_reg_value, 0);
4690 }
4691
4692 static void chv_set_signal_levels(struct intel_dp *intel_dp,
4693                                   const struct intel_crtc_state *crtc_state)
4694 {
4695         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4696         u32 deemph_reg_value, margin_reg_value;
4697         bool uniq_trans_scale = false;
4698         u8 train_set = intel_dp->train_set[0];
4699
4700         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4701         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4702                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4703                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4704                         deemph_reg_value = 128;
4705                         margin_reg_value = 52;
4706                         break;
4707                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4708                         deemph_reg_value = 128;
4709                         margin_reg_value = 77;
4710                         break;
4711                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4712                         deemph_reg_value = 128;
4713                         margin_reg_value = 102;
4714                         break;
4715                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4716                         deemph_reg_value = 128;
4717                         margin_reg_value = 154;
4718                         uniq_trans_scale = true;
4719                         break;
4720                 default:
4721                         return;
4722                 }
4723                 break;
4724         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4725                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4726                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4727                         deemph_reg_value = 85;
4728                         margin_reg_value = 78;
4729                         break;
4730                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4731                         deemph_reg_value = 85;
4732                         margin_reg_value = 116;
4733                         break;
4734                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4735                         deemph_reg_value = 85;
4736                         margin_reg_value = 154;
4737                         break;
4738                 default:
4739                         return;
4740                 }
4741                 break;
4742         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4743                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4744                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4745                         deemph_reg_value = 64;
4746                         margin_reg_value = 104;
4747                         break;
4748                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4749                         deemph_reg_value = 64;
4750                         margin_reg_value = 154;
4751                         break;
4752                 default:
4753                         return;
4754                 }
4755                 break;
4756         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4757                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4758                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4759                         deemph_reg_value = 43;
4760                         margin_reg_value = 154;
4761                         break;
4762                 default:
4763                         return;
4764                 }
4765                 break;
4766         default:
4767                 return;
4768         }
4769
4770         chv_set_phy_signal_level(encoder, crtc_state,
4771                                  deemph_reg_value, margin_reg_value,
4772                                  uniq_trans_scale);
4773 }
4774
4775 static u32 g4x_signal_levels(u8 train_set)
4776 {
4777         u32 signal_levels = 0;
4778
4779         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4780         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4781         default:
4782                 signal_levels |= DP_VOLTAGE_0_4;
4783                 break;
4784         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4785                 signal_levels |= DP_VOLTAGE_0_6;
4786                 break;
4787         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4788                 signal_levels |= DP_VOLTAGE_0_8;
4789                 break;
4790         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4791                 signal_levels |= DP_VOLTAGE_1_2;
4792                 break;
4793         }
4794         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4795         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4796         default:
4797                 signal_levels |= DP_PRE_EMPHASIS_0;
4798                 break;
4799         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4800                 signal_levels |= DP_PRE_EMPHASIS_3_5;
4801                 break;
4802         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4803                 signal_levels |= DP_PRE_EMPHASIS_6;
4804                 break;
4805         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4806                 signal_levels |= DP_PRE_EMPHASIS_9_5;
4807                 break;
4808         }
4809         return signal_levels;
4810 }
4811
4812 static void
4813 g4x_set_signal_levels(struct intel_dp *intel_dp,
4814                       const struct intel_crtc_state *crtc_state)
4815 {
4816         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4817         u8 train_set = intel_dp->train_set[0];
4818         u32 signal_levels;
4819
4820         signal_levels = g4x_signal_levels(train_set);
4821
4822         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4823                     signal_levels);
4824
4825         intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);
4826         intel_dp->DP |= signal_levels;
4827
4828         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4829         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4830 }
4831
4832 /* SNB CPU eDP voltage swing and pre-emphasis control */
4833 static u32 snb_cpu_edp_signal_levels(u8 train_set)
4834 {
4835         u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4836                                         DP_TRAIN_PRE_EMPHASIS_MASK);
4837
4838         switch (signal_levels) {
4839         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4840         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4841                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4842         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4843                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
4844         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4845         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4846                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
4847         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4848         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4849                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
4850         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4851         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4852                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
4853         default:
4854                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4855                               "0x%x\n", signal_levels);
4856                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4857         }
4858 }
4859
4860 static void
4861 snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
4862                               const struct intel_crtc_state *crtc_state)
4863 {
4864         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4865         u8 train_set = intel_dp->train_set[0];
4866         u32 signal_levels;
4867
4868         signal_levels = snb_cpu_edp_signal_levels(train_set);
4869
4870         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4871                     signal_levels);
4872
4873         intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
4874         intel_dp->DP |= signal_levels;
4875
4876         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4877         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4878 }
4879
4880 /* IVB CPU eDP voltage swing and pre-emphasis control */
4881 static u32 ivb_cpu_edp_signal_levels(u8 train_set)
4882 {
4883         u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4884                                         DP_TRAIN_PRE_EMPHASIS_MASK);
4885
4886         switch (signal_levels) {
4887         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4888                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
4889         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4890                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
4891         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4892         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4893                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
4894
4895         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4896                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
4897         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4898                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
4899
4900         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4901                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
4902         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4903                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
4904
4905         default:
4906                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4907                               "0x%x\n", signal_levels);
4908                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
4909         }
4910 }
4911
4912 static void
4913 ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
4914                               const struct intel_crtc_state *crtc_state)
4915 {
4916         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4917         u8 train_set = intel_dp->train_set[0];
4918         u32 signal_levels;
4919
4920         signal_levels = ivb_cpu_edp_signal_levels(train_set);
4921
4922         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4923                     signal_levels);
4924
4925         intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
4926         intel_dp->DP |= signal_levels;
4927
4928         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4929         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4930 }
4931
4932 void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
4933                                 const struct intel_crtc_state *crtc_state)
4934 {
4935         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4936         u8 train_set = intel_dp->train_set[0];
4937
4938         drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
4939                     train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
4940                     train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
4941         drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
4942                     (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
4943                     DP_TRAIN_PRE_EMPHASIS_SHIFT,
4944                     train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
4945                     " (max)" : "");
4946
4947         intel_dp->set_signal_levels(intel_dp, crtc_state);
4948 }
4949
4950 void
4951 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
4952                                        const struct intel_crtc_state *crtc_state,
4953                                        u8 dp_train_pat)
4954 {
4955         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4956
4957         if ((intel_dp_training_pattern_symbol(dp_train_pat)) !=
4958             DP_TRAINING_PATTERN_DISABLE)
4959                 drm_dbg_kms(&dev_priv->drm,
4960                             "Using DP training pattern TPS%d\n",
4961                             intel_dp_training_pattern_symbol(dp_train_pat));
4962
4963         intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
4964 }
4965
4966 static void
4967 intel_dp_link_down(struct intel_encoder *encoder,
4968                    const struct intel_crtc_state *old_crtc_state)
4969 {
4970         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4971         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4972         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4973         enum port port = encoder->port;
4974         u32 DP = intel_dp->DP;
4975
4976         if (drm_WARN_ON(&dev_priv->drm,
4977                         (intel_de_read(dev_priv, intel_dp->output_reg) &
4978                          DP_PORT_EN) == 0))
4979                 return;
4980
4981         drm_dbg_kms(&dev_priv->drm, "\n");
4982
4983         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
4984             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
4985                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
4986                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
4987         } else {
4988                 DP &= ~DP_LINK_TRAIN_MASK;
4989                 DP |= DP_LINK_TRAIN_PAT_IDLE;
4990         }
4991         intel_de_write(dev_priv, intel_dp->output_reg, DP);
4992         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4993
4994         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
4995         intel_de_write(dev_priv, intel_dp->output_reg, DP);
4996         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4997
4998         /*
4999          * HW workaround for IBX, we need to move the port
5000          * to transcoder A after disabling it to allow the
5001          * matching HDMI port to be enabled on transcoder A.
5002          */
5003         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
5004                 /*
5005                  * We get CPU/PCH FIFO underruns on the other pipe when
5006                  * doing the workaround. Sweep them under the rug.
5007                  */
5008                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
5009                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
5010
5011                 /* always enable with pattern 1 (as per spec) */
5012                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
5013                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
5014                         DP_LINK_TRAIN_PAT_1;
5015                 intel_de_write(dev_priv, intel_dp->output_reg, DP);
5016                 intel_de_posting_read(dev_priv, intel_dp->output_reg);
5017
5018                 DP &= ~DP_PORT_EN;
5019                 intel_de_write(dev_priv, intel_dp->output_reg, DP);
5020                 intel_de_posting_read(dev_priv, intel_dp->output_reg);
5021
5022                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
5023                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5024                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5025         }
5026
5027         msleep(intel_dp->panel_power_down_delay);
5028
5029         intel_dp->DP = DP;
5030
5031         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5032                 intel_wakeref_t wakeref;
5033
5034                 with_pps_lock(intel_dp, wakeref)
5035                         intel_dp->active_pipe = INVALID_PIPE;
5036         }
5037 }
5038
5039 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
5040 {
5041         u8 dprx = 0;
5042
5043         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
5044                               &dprx) != 1)
5045                 return false;
5046         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
5047 }
5048
5049 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
5050 {
5051         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5052
5053         /*
5054          * Clear the cached register set to avoid using stale values
5055          * for the sinks that do not support DSC.
5056          */
5057         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
5058
5059         /* Clear fec_capable to avoid using stale values */
5060         intel_dp->fec_capable = 0;
5061
5062         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
5063         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
5064             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
5065                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
5066                                      intel_dp->dsc_dpcd,
5067                                      sizeof(intel_dp->dsc_dpcd)) < 0)
5068                         drm_err(&i915->drm,
5069                                 "Failed to read DPCD register 0x%x\n",
5070                                 DP_DSC_SUPPORT);
5071
5072                 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
5073                             (int)sizeof(intel_dp->dsc_dpcd),
5074                             intel_dp->dsc_dpcd);
5075
5076                 /* FEC is supported only on DP 1.4 */
5077                 if (!intel_dp_is_edp(intel_dp) &&
5078                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
5079                                       &intel_dp->fec_capable) < 0)
5080                         drm_err(&i915->drm,
5081                                 "Failed to read FEC DPCD register\n");
5082
5083                 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
5084                             intel_dp->fec_capable);
5085         }
5086 }
5087
5088 static bool
5089 intel_edp_init_dpcd(struct intel_dp *intel_dp)
5090 {
5091         struct drm_i915_private *dev_priv =
5092                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
5093
5094         /* this function is meant to be called only once */
5095         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
5096
5097         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
5098                 return false;
5099
5100         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
5101                          drm_dp_is_branch(intel_dp->dpcd));
5102
5103         /*
5104          * Read the eDP display control registers.
5105          *
5106          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
5107          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
5108          * set, but require eDP 1.4+ detection (e.g. for supported link rates
5109          * method). The display control registers should read zero if they're
5110          * not supported anyway.
5111          */
5112         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
5113                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
5114                              sizeof(intel_dp->edp_dpcd))
5115                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
5116                             (int)sizeof(intel_dp->edp_dpcd),
5117                             intel_dp->edp_dpcd);
5118
5119         /*
5120          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
5121          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
5122          */
5123         intel_psr_init_dpcd(intel_dp);
5124
5125         /* Read the eDP 1.4+ supported link rates. */
5126         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
5127                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
5128                 int i;
5129
5130                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
5131                                 sink_rates, sizeof(sink_rates));
5132
5133                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
5134                         int val = le16_to_cpu(sink_rates[i]);
5135
5136                         if (val == 0)
5137                                 break;
5138
5139                         /* Value read multiplied by 200kHz gives the per-lane
5140                          * link rate in kHz. The source rates are, however,
5141                          * stored in terms of LS_Clk kHz. The full conversion
5142                          * back to symbols is
5143                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
5144                          */
5145                         intel_dp->sink_rates[i] = (val * 200) / 10;
5146                 }
5147                 intel_dp->num_sink_rates = i;
5148         }
5149
5150         /*
5151          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
5152          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
5153          */
5154         if (intel_dp->num_sink_rates)
5155                 intel_dp->use_rate_select = true;
5156         else
5157                 intel_dp_set_sink_rates(intel_dp);
5158
5159         intel_dp_set_common_rates(intel_dp);
5160
5161         /* Read the eDP DSC DPCD registers */
5162         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
5163                 intel_dp_get_dsc_sink_cap(intel_dp);
5164
5165         return true;
5166 }
5167
5168 static bool
5169 intel_dp_has_sink_count(struct intel_dp *intel_dp)
5170 {
5171         if (!intel_dp->attached_connector)
5172                 return false;
5173
5174         return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
5175                                           intel_dp->dpcd,
5176                                           &intel_dp->desc);
5177 }
5178
5179 static bool
5180 intel_dp_get_dpcd(struct intel_dp *intel_dp)
5181 {
5182         int ret;
5183
5184         intel_dp_lttpr_init(intel_dp);
5185
5186         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd))
5187                 return false;
5188
5189         /*
5190          * Don't clobber cached eDP rates. Also skip re-reading
5191          * the OUI/ID since we know it won't change.
5192          */
5193         if (!intel_dp_is_edp(intel_dp)) {
5194                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
5195                                  drm_dp_is_branch(intel_dp->dpcd));
5196
5197                 intel_dp_set_sink_rates(intel_dp);
5198                 intel_dp_set_common_rates(intel_dp);
5199         }
5200
5201         if (intel_dp_has_sink_count(intel_dp)) {
5202                 ret = drm_dp_read_sink_count(&intel_dp->aux);
5203                 if (ret < 0)
5204                         return false;
5205
5206                 /*
5207                  * Sink count can change between short pulse hpd hence
5208                  * a member variable in intel_dp will track any changes
5209                  * between short pulse interrupts.
5210                  */
5211                 intel_dp->sink_count = ret;
5212
5213                 /*
5214                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
5215                  * a dongle is present but no display. Unless we require to know
5216                  * if a dongle is present or not, we don't need to update
5217                  * downstream port information. So, an early return here saves
5218                  * time from performing other operations which are not required.
5219                  */
5220                 if (!intel_dp->sink_count)
5221                         return false;
5222         }
5223
5224         return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
5225                                            intel_dp->downstream_ports) == 0;
5226 }
5227
5228 static bool
5229 intel_dp_can_mst(struct intel_dp *intel_dp)
5230 {
5231         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5232
5233         return i915->params.enable_dp_mst &&
5234                 intel_dp->can_mst &&
5235                 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
5236 }
5237
5238 static void
5239 intel_dp_configure_mst(struct intel_dp *intel_dp)
5240 {
5241         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5242         struct intel_encoder *encoder =
5243                 &dp_to_dig_port(intel_dp)->base;
5244         bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
5245
5246         drm_dbg_kms(&i915->drm,
5247                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
5248                     encoder->base.base.id, encoder->base.name,
5249                     yesno(intel_dp->can_mst), yesno(sink_can_mst),
5250                     yesno(i915->params.enable_dp_mst));
5251
5252         if (!intel_dp->can_mst)
5253                 return;
5254
5255         intel_dp->is_mst = sink_can_mst &&
5256                 i915->params.enable_dp_mst;
5257
5258         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5259                                         intel_dp->is_mst);
5260 }
5261
5262 static bool
5263 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
5264 {
5265         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
5266                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
5267                 DP_DPRX_ESI_LEN;
5268 }
5269
5270 bool
5271 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
5272                        const struct drm_connector_state *conn_state)
5273 {
5274         /*
5275          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
5276          * of Color Encoding Format and Content Color Gamut], in order to
5277          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
5278          */
5279         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
5280                 return true;
5281
5282         switch (conn_state->colorspace) {
5283         case DRM_MODE_COLORIMETRY_SYCC_601:
5284         case DRM_MODE_COLORIMETRY_OPYCC_601:
5285         case DRM_MODE_COLORIMETRY_BT2020_YCC:
5286         case DRM_MODE_COLORIMETRY_BT2020_RGB:
5287         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
5288                 return true;
5289         default:
5290                 break;
5291         }
5292
5293         return false;
5294 }
5295
5296 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
5297                                      struct dp_sdp *sdp, size_t size)
5298 {
5299         size_t length = sizeof(struct dp_sdp);
5300
5301         if (size < length)
5302                 return -ENOSPC;
5303
5304         memset(sdp, 0, size);
5305
5306         /*
5307          * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
5308          * VSC SDP Header Bytes
5309          */
5310         sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
5311         sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
5312         sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
5313         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
5314
5315         /*
5316          * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
5317          * per DP 1.4a spec.
5318          */
5319         if (vsc->revision != 0x5)
5320                 goto out;
5321
5322         /* VSC SDP Payload for DB16 through DB18 */
5323         /* Pixel Encoding and Colorimetry Formats  */
5324         sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
5325         sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
5326
5327         switch (vsc->bpc) {
5328         case 6:
5329                 /* 6bpc: 0x0 */
5330                 break;
5331         case 8:
5332                 sdp->db[17] = 0x1; /* DB17[3:0] */
5333                 break;
5334         case 10:
5335                 sdp->db[17] = 0x2;
5336                 break;
5337         case 12:
5338                 sdp->db[17] = 0x3;
5339                 break;
5340         case 16:
5341                 sdp->db[17] = 0x4;
5342                 break;
5343         default:
5344                 MISSING_CASE(vsc->bpc);
5345                 break;
5346         }
5347         /* Dynamic Range and Component Bit Depth */
5348         if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
5349                 sdp->db[17] |= 0x80;  /* DB17[7] */
5350
5351         /* Content Type */
5352         sdp->db[18] = vsc->content_type & 0x7;
5353
5354 out:
5355         return length;
5356 }
5357
5358 static ssize_t
5359 intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
5360                                          struct dp_sdp *sdp,
5361                                          size_t size)
5362 {
5363         size_t length = sizeof(struct dp_sdp);
5364         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
5365         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
5366         ssize_t len;
5367
5368         if (size < length)
5369                 return -ENOSPC;
5370
5371         memset(sdp, 0, size);
5372
5373         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
5374         if (len < 0) {
5375                 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
5376                 return -ENOSPC;
5377         }
5378
5379         if (len != infoframe_size) {
5380                 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
5381                 return -ENOSPC;
5382         }
5383
5384         /*
5385          * Set up the infoframe sdp packet for HDR static metadata.
5386          * Prepare VSC Header for SU as per DP 1.4a spec,
5387          * Table 2-100 and Table 2-101
5388          */
5389
5390         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
5391         sdp->sdp_header.HB0 = 0;
5392         /*
5393          * Packet Type 80h + Non-audio INFOFRAME Type value
5394          * HDMI_INFOFRAME_TYPE_DRM: 0x87
5395          * - 80h + Non-audio INFOFRAME Type value
5396          * - InfoFrame Type: 0x07
5397          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
5398          */
5399         sdp->sdp_header.HB1 = drm_infoframe->type;
5400         /*
5401          * Least Significant Eight Bits of (Data Byte Count – 1)
5402          * infoframe_size - 1
5403          */
5404         sdp->sdp_header.HB2 = 0x1D;
5405         /* INFOFRAME SDP Version Number */
5406         sdp->sdp_header.HB3 = (0x13 << 2);
5407         /* CTA Header Byte 2 (INFOFRAME Version Number) */
5408         sdp->db[0] = drm_infoframe->version;
5409         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
5410         sdp->db[1] = drm_infoframe->length;
5411         /*
5412          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
5413          * HDMI_INFOFRAME_HEADER_SIZE
5414          */
5415         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
5416         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
5417                HDMI_DRM_INFOFRAME_SIZE);
5418
5419         /*
5420          * Size of DP infoframe sdp packet for HDR static metadata consists of
5421          * - DP SDP Header(struct dp_sdp_header): 4 bytes
5422          * - Two Data Blocks: 2 bytes
5423          *    CTA Header Byte2 (INFOFRAME Version Number)
5424          *    CTA Header Byte3 (Length of INFOFRAME)
5425          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
5426          *
5427          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
5428          * infoframe size. But GEN11+ has larger than that size, write_infoframe
5429          * will pad rest of the size.
5430          */
5431         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
5432 }
5433
5434 static void intel_write_dp_sdp(struct intel_encoder *encoder,
5435                                const struct intel_crtc_state *crtc_state,
5436                                unsigned int type)
5437 {
5438         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5439         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5440         struct dp_sdp sdp = {};
5441         ssize_t len;
5442
5443         if ((crtc_state->infoframes.enable &
5444              intel_hdmi_infoframe_enable(type)) == 0)
5445                 return;
5446
5447         switch (type) {
5448         case DP_SDP_VSC:
5449                 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
5450                                             sizeof(sdp));
5451                 break;
5452         case HDMI_PACKET_TYPE_GAMUT_METADATA:
5453                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
5454                                                                &sdp, sizeof(sdp));
5455                 break;
5456         default:
5457                 MISSING_CASE(type);
5458                 return;
5459         }
5460
5461         if (drm_WARN_ON(&dev_priv->drm, len < 0))
5462                 return;
5463
5464         dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
5465 }
5466
5467 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
5468                             const struct intel_crtc_state *crtc_state,
5469                             struct drm_dp_vsc_sdp *vsc)
5470 {
5471         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5472         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5473         struct dp_sdp sdp = {};
5474         ssize_t len;
5475
5476         len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
5477
5478         if (drm_WARN_ON(&dev_priv->drm, len < 0))
5479                 return;
5480
5481         dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
5482                                         &sdp, len);
5483 }
5484
5485 void intel_dp_set_infoframes(struct intel_encoder *encoder,
5486                              bool enable,
5487                              const struct intel_crtc_state *crtc_state,
5488                              const struct drm_connector_state *conn_state)
5489 {
5490         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5491         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5492         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
5493         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
5494                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
5495                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
5496         u32 val = intel_de_read(dev_priv, reg);
5497
5498         /* TODO: Add DSC case (DIP_ENABLE_PPS) */
5499         /* When PSR is enabled, this routine doesn't disable VSC DIP */
5500         if (intel_psr_enabled(intel_dp))
5501                 val &= ~dip_enable;
5502         else
5503                 val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
5504
5505         if (!enable) {
5506                 intel_de_write(dev_priv, reg, val);
5507                 intel_de_posting_read(dev_priv, reg);
5508                 return;
5509         }
5510
5511         intel_de_write(dev_priv, reg, val);
5512         intel_de_posting_read(dev_priv, reg);
5513
5514         /* When PSR is enabled, VSC SDP is handled by PSR routine */
5515         if (!intel_psr_enabled(intel_dp))
5516                 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
5517
5518         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
5519 }
5520
5521 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
5522                                    const void *buffer, size_t size)
5523 {
5524         const struct dp_sdp *sdp = buffer;
5525
5526         if (size < sizeof(struct dp_sdp))
5527                 return -EINVAL;
5528
5529         memset(vsc, 0, size);
5530
5531         if (sdp->sdp_header.HB0 != 0)
5532                 return -EINVAL;
5533
5534         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
5535                 return -EINVAL;
5536
5537         vsc->sdp_type = sdp->sdp_header.HB1;
5538         vsc->revision = sdp->sdp_header.HB2;
5539         vsc->length = sdp->sdp_header.HB3;
5540
5541         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
5542             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
5543                 /*
5544                  * - HB2 = 0x2, HB3 = 0x8
5545                  *   VSC SDP supporting 3D stereo + PSR
5546                  * - HB2 = 0x4, HB3 = 0xe
5547                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
5548                  *   first scan line of the SU region (applies to eDP v1.4b
5549                  *   and higher).
5550                  */
5551                 return 0;
5552         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
5553                 /*
5554                  * - HB2 = 0x5, HB3 = 0x13
5555                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
5556                  *   Format.
5557                  */
5558                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
5559                 vsc->colorimetry = sdp->db[16] & 0xf;
5560                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
5561
5562                 switch (sdp->db[17] & 0x7) {
5563                 case 0x0:
5564                         vsc->bpc = 6;
5565                         break;
5566                 case 0x1:
5567                         vsc->bpc = 8;
5568                         break;
5569                 case 0x2:
5570                         vsc->bpc = 10;
5571                         break;
5572                 case 0x3:
5573                         vsc->bpc = 12;
5574                         break;
5575                 case 0x4:
5576                         vsc->bpc = 16;
5577                         break;
5578                 default:
5579                         MISSING_CASE(sdp->db[17] & 0x7);
5580                         return -EINVAL;
5581                 }
5582
5583                 vsc->content_type = sdp->db[18] & 0x7;
5584         } else {
5585                 return -EINVAL;
5586         }
5587
5588         return 0;
5589 }
5590
5591 static int
5592 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
5593                                            const void *buffer, size_t size)
5594 {
5595         int ret;
5596
5597         const struct dp_sdp *sdp = buffer;
5598
5599         if (size < sizeof(struct dp_sdp))
5600                 return -EINVAL;
5601
5602         if (sdp->sdp_header.HB0 != 0)
5603                 return -EINVAL;
5604
5605         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
5606                 return -EINVAL;
5607
5608         /*
5609          * Least Significant Eight Bits of (Data Byte Count – 1)
5610          * 1Dh (i.e., Data Byte Count = 30 bytes).
5611          */
5612         if (sdp->sdp_header.HB2 != 0x1D)
5613                 return -EINVAL;
5614
5615         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
5616         if ((sdp->sdp_header.HB3 & 0x3) != 0)
5617                 return -EINVAL;
5618
5619         /* INFOFRAME SDP Version Number */
5620         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
5621                 return -EINVAL;
5622
5623         /* CTA Header Byte 2 (INFOFRAME Version Number) */
5624         if (sdp->db[0] != 1)
5625                 return -EINVAL;
5626
5627         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
5628         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
5629                 return -EINVAL;
5630
5631         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
5632                                              HDMI_DRM_INFOFRAME_SIZE);
5633
5634         return ret;
5635 }
5636
5637 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
5638                                   struct intel_crtc_state *crtc_state,
5639                                   struct drm_dp_vsc_sdp *vsc)
5640 {
5641         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5642         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5643         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5644         unsigned int type = DP_SDP_VSC;
5645         struct dp_sdp sdp = {};
5646         int ret;
5647
5648         /* When PSR is enabled, VSC SDP is handled by PSR routine */
5649         if (intel_psr_enabled(intel_dp))
5650                 return;
5651
5652         if ((crtc_state->infoframes.enable &
5653              intel_hdmi_infoframe_enable(type)) == 0)
5654                 return;
5655
5656         dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
5657
5658         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
5659
5660         if (ret)
5661                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
5662 }
5663
5664 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
5665                                                      struct intel_crtc_state *crtc_state,
5666                                                      struct hdmi_drm_infoframe *drm_infoframe)
5667 {
5668         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5669         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5670         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
5671         struct dp_sdp sdp = {};
5672         int ret;
5673
5674         if ((crtc_state->infoframes.enable &
5675             intel_hdmi_infoframe_enable(type)) == 0)
5676                 return;
5677
5678         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
5679                                  sizeof(sdp));
5680
5681         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
5682                                                          sizeof(sdp));
5683
5684         if (ret)
5685                 drm_dbg_kms(&dev_priv->drm,
5686                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
5687 }
5688
5689 void intel_read_dp_sdp(struct intel_encoder *encoder,
5690                        struct intel_crtc_state *crtc_state,
5691                        unsigned int type)
5692 {
5693         if (encoder->type != INTEL_OUTPUT_DDI)
5694                 return;
5695
5696         switch (type) {
5697         case DP_SDP_VSC:
5698                 intel_read_dp_vsc_sdp(encoder, crtc_state,
5699                                       &crtc_state->infoframes.vsc);
5700                 break;
5701         case HDMI_PACKET_TYPE_GAMUT_METADATA:
5702                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
5703                                                          &crtc_state->infoframes.drm.drm);
5704                 break;
5705         default:
5706                 MISSING_CASE(type);
5707                 break;
5708         }
5709 }
5710
5711 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
5712 {
5713         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5714         int status = 0;
5715         int test_link_rate;
5716         u8 test_lane_count, test_link_bw;
5717         /* (DP CTS 1.2)
5718          * 4.3.1.11
5719          */
5720         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
5721         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
5722                                    &test_lane_count);
5723
5724         if (status <= 0) {
5725                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
5726                 return DP_TEST_NAK;
5727         }
5728         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
5729
5730         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
5731                                    &test_link_bw);
5732         if (status <= 0) {
5733                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
5734                 return DP_TEST_NAK;
5735         }
5736         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
5737
5738         /* Validate the requested link rate and lane count */
5739         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
5740                                         test_lane_count))
5741                 return DP_TEST_NAK;
5742
5743         intel_dp->compliance.test_lane_count = test_lane_count;
5744         intel_dp->compliance.test_link_rate = test_link_rate;
5745
5746         return DP_TEST_ACK;
5747 }
5748
5749 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
5750 {
5751         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5752         u8 test_pattern;
5753         u8 test_misc;
5754         __be16 h_width, v_height;
5755         int status = 0;
5756
5757         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
5758         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
5759                                    &test_pattern);
5760         if (status <= 0) {
5761                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
5762                 return DP_TEST_NAK;
5763         }
5764         if (test_pattern != DP_COLOR_RAMP)
5765                 return DP_TEST_NAK;
5766
5767         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
5768                                   &h_width, 2);
5769         if (status <= 0) {
5770                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
5771                 return DP_TEST_NAK;
5772         }
5773
5774         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
5775                                   &v_height, 2);
5776         if (status <= 0) {
5777                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
5778                 return DP_TEST_NAK;
5779         }
5780
5781         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
5782                                    &test_misc);
5783         if (status <= 0) {
5784                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
5785                 return DP_TEST_NAK;
5786         }
5787         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
5788                 return DP_TEST_NAK;
5789         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
5790                 return DP_TEST_NAK;
5791         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
5792         case DP_TEST_BIT_DEPTH_6:
5793                 intel_dp->compliance.test_data.bpc = 6;
5794                 break;
5795         case DP_TEST_BIT_DEPTH_8:
5796                 intel_dp->compliance.test_data.bpc = 8;
5797                 break;
5798         default:
5799                 return DP_TEST_NAK;
5800         }
5801
5802         intel_dp->compliance.test_data.video_pattern = test_pattern;
5803         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
5804         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
5805         /* Set test active flag here so userspace doesn't interrupt things */
5806         intel_dp->compliance.test_active = true;
5807
5808         return DP_TEST_ACK;
5809 }
5810
5811 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
5812 {
5813         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5814         u8 test_result = DP_TEST_ACK;
5815         struct intel_connector *intel_connector = intel_dp->attached_connector;
5816         struct drm_connector *connector = &intel_connector->base;
5817
5818         if (intel_connector->detect_edid == NULL ||
5819             connector->edid_corrupt ||
5820             intel_dp->aux.i2c_defer_count > 6) {
5821                 /* Check EDID read for NACKs, DEFERs and corruption
5822                  * (DP CTS 1.2 Core r1.1)
5823                  *    4.2.2.4 : Failed EDID read, I2C_NAK
5824                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
5825                  *    4.2.2.6 : EDID corruption detected
5826                  * Use failsafe mode for all cases
5827                  */
5828                 if (intel_dp->aux.i2c_nack_count > 0 ||
5829                         intel_dp->aux.i2c_defer_count > 0)
5830                         drm_dbg_kms(&i915->drm,
5831                                     "EDID read had %d NACKs, %d DEFERs\n",
5832                                     intel_dp->aux.i2c_nack_count,
5833                                     intel_dp->aux.i2c_defer_count);
5834                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
5835         } else {
5836                 struct edid *block = intel_connector->detect_edid;
5837
5838                 /* We have to write the checksum
5839                  * of the last block read
5840                  */
5841                 block += intel_connector->detect_edid->extensions;
5842
5843                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
5844                                        block->checksum) <= 0)
5845                         drm_dbg_kms(&i915->drm,
5846                                     "Failed to write EDID checksum\n");
5847
5848                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
5849                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
5850         }
5851
5852         /* Set test active flag here so userspace doesn't interrupt things */
5853         intel_dp->compliance.test_active = true;
5854
5855         return test_result;
5856 }
5857
5858 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
5859                                         const struct intel_crtc_state *crtc_state)
5860 {
5861         struct drm_i915_private *dev_priv =
5862                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
5863         struct drm_dp_phy_test_params *data =
5864                         &intel_dp->compliance.test_data.phytest;
5865         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5866         enum pipe pipe = crtc->pipe;
5867         u32 pattern_val;
5868
5869         switch (data->phy_pattern) {
5870         case DP_PHY_TEST_PATTERN_NONE:
5871                 DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
5872                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
5873                 break;
5874         case DP_PHY_TEST_PATTERN_D10_2:
5875                 DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
5876                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5877                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
5878                 break;
5879         case DP_PHY_TEST_PATTERN_ERROR_COUNT:
5880                 DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
5881                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5882                                DDI_DP_COMP_CTL_ENABLE |
5883                                DDI_DP_COMP_CTL_SCRAMBLED_0);
5884                 break;
5885         case DP_PHY_TEST_PATTERN_PRBS7:
5886                 DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
5887                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5888                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
5889                 break;
5890         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
5891                 /*
5892                  * FIXME: Ideally pattern should come from DPCD 0x250. As
5893                  * current firmware of DPR-100 could not set it, so hardcoding
5894                  * now for complaince test.
5895                  */
5896                 DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
5897                 pattern_val = 0x3e0f83e0;
5898                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
5899                 pattern_val = 0x0f83e0f8;
5900                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
5901                 pattern_val = 0x0000f83e;
5902                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
5903                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5904                                DDI_DP_COMP_CTL_ENABLE |
5905                                DDI_DP_COMP_CTL_CUSTOM80);
5906                 break;
5907         case DP_PHY_TEST_PATTERN_CP2520:
5908                 /*
5909                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
5910                  * current firmware of DPR-100 could not set it, so hardcoding
5911                  * now for complaince test.
5912                  */
5913                 DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
5914                 pattern_val = 0xFB;
5915                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5916                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
5917                                pattern_val);
5918                 break;
5919         default:
5920                 WARN(1, "Invalid Phy Test Pattern\n");
5921         }
5922 }
5923
5924 static void
5925 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
5926                                   const struct intel_crtc_state *crtc_state)
5927 {
5928         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5929         struct drm_device *dev = dig_port->base.base.dev;
5930         struct drm_i915_private *dev_priv = to_i915(dev);
5931         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
5932         enum pipe pipe = crtc->pipe;
5933         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
5934
5935         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
5936                                                  TRANS_DDI_FUNC_CTL(pipe));
5937         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
5938         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
5939
5940         trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
5941                                       TGL_TRANS_DDI_PORT_MASK);
5942         trans_conf_value &= ~PIPECONF_ENABLE;
5943         dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
5944
5945         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
5946         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
5947                        trans_ddi_func_ctl_value);
5948         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
5949 }
5950
5951 static void
5952 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
5953                                  const struct intel_crtc_state *crtc_state)
5954 {
5955         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5956         struct drm_device *dev = dig_port->base.base.dev;
5957         struct drm_i915_private *dev_priv = to_i915(dev);
5958         enum port port = dig_port->base.port;
5959         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
5960         enum pipe pipe = crtc->pipe;
5961         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
5962
5963         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
5964                                                  TRANS_DDI_FUNC_CTL(pipe));
5965         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
5966         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
5967
5968         trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
5969                                     TGL_TRANS_DDI_SELECT_PORT(port);
5970         trans_conf_value |= PIPECONF_ENABLE;
5971         dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
5972
5973         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
5974         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
5975         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
5976                        trans_ddi_func_ctl_value);
5977 }
5978
5979 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
5980                                          const struct intel_crtc_state *crtc_state)
5981 {
5982         struct drm_dp_phy_test_params *data =
5983                 &intel_dp->compliance.test_data.phytest;
5984         u8 link_status[DP_LINK_STATUS_SIZE];
5985
5986         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
5987                                              link_status) < 0) {
5988                 DRM_DEBUG_KMS("failed to get link status\n");
5989                 return;
5990         }
5991
5992         /* retrieve vswing & pre-emphasis setting */
5993         intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
5994                                   link_status);
5995
5996         intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
5997
5998         intel_dp_set_signal_levels(intel_dp, crtc_state);
5999
6000         intel_dp_phy_pattern_update(intel_dp, crtc_state);
6001
6002         intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
6003
6004         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
6005                                     link_status[DP_DPCD_REV]);
6006 }
6007
6008 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
6009 {
6010         struct drm_dp_phy_test_params *data =
6011                 &intel_dp->compliance.test_data.phytest;
6012
6013         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
6014                 DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
6015                 return DP_TEST_NAK;
6016         }
6017
6018         /* Set test active flag here so userspace doesn't interrupt things */
6019         intel_dp->compliance.test_active = true;
6020
6021         return DP_TEST_ACK;
6022 }
6023
6024 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
6025 {
6026         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6027         u8 response = DP_TEST_NAK;
6028         u8 request = 0;
6029         int status;
6030
6031         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
6032         if (status <= 0) {
6033                 drm_dbg_kms(&i915->drm,
6034                             "Could not read test request from sink\n");
6035                 goto update_status;
6036         }
6037
6038         switch (request) {
6039         case DP_TEST_LINK_TRAINING:
6040                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
6041                 response = intel_dp_autotest_link_training(intel_dp);
6042                 break;
6043         case DP_TEST_LINK_VIDEO_PATTERN:
6044                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
6045                 response = intel_dp_autotest_video_pattern(intel_dp);
6046                 break;
6047         case DP_TEST_LINK_EDID_READ:
6048                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
6049                 response = intel_dp_autotest_edid(intel_dp);
6050                 break;
6051         case DP_TEST_LINK_PHY_TEST_PATTERN:
6052                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
6053                 response = intel_dp_autotest_phy_pattern(intel_dp);
6054                 break;
6055         default:
6056                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
6057                             request);
6058                 break;
6059         }
6060
6061         if (response & DP_TEST_ACK)
6062                 intel_dp->compliance.test_type = request;
6063
6064 update_status:
6065         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
6066         if (status <= 0)
6067                 drm_dbg_kms(&i915->drm,
6068                             "Could not write test response to sink\n");
6069 }
6070
6071 /**
6072  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
6073  * @intel_dp: Intel DP struct
6074  *
6075  * Read any pending MST interrupts, call MST core to handle these and ack the
6076  * interrupts. Check if the main and AUX link state is ok.
6077  *
6078  * Returns:
6079  * - %true if pending interrupts were serviced (or no interrupts were
6080  *   pending) w/o detecting an error condition.
6081  * - %false if an error condition - like AUX failure or a loss of link - is
6082  *   detected, which needs servicing from the hotplug work.
6083  */
6084 static bool
6085 intel_dp_check_mst_status(struct intel_dp *intel_dp)
6086 {
6087         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6088         bool link_ok = true;
6089
6090         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
6091
6092         for (;;) {
6093                 u8 esi[DP_DPRX_ESI_LEN] = {};
6094                 bool handled;
6095                 int retry;
6096
6097                 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
6098                         drm_dbg_kms(&i915->drm,
6099                                     "failed to get ESI - device may have failed\n");
6100                         link_ok = false;
6101
6102                         break;
6103                 }
6104
6105                 /* check link status - esi[10] = 0x200c */
6106                 if (intel_dp->active_mst_links > 0 && link_ok &&
6107                     !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
6108                         drm_dbg_kms(&i915->drm,
6109                                     "channel EQ not ok, retraining\n");
6110                         link_ok = false;
6111                 }
6112
6113                 drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
6114
6115                 drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
6116                 if (!handled)
6117                         break;
6118
6119                 for (retry = 0; retry < 3; retry++) {
6120                         int wret;
6121
6122                         wret = drm_dp_dpcd_write(&intel_dp->aux,
6123                                                  DP_SINK_COUNT_ESI+1,
6124                                                  &esi[1], 3);
6125                         if (wret == 3)
6126                                 break;
6127                 }
6128         }
6129
6130         return link_ok;
6131 }
6132
6133 static void
6134 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
6135 {
6136         bool is_active;
6137         u8 buf = 0;
6138
6139         is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
6140         if (intel_dp->frl.is_trained && !is_active) {
6141                 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
6142                         return;
6143
6144                 buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
6145                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
6146                         return;
6147
6148                 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
6149
6150                 /* Restart FRL training or fall back to TMDS mode */
6151                 intel_dp_check_frl_training(intel_dp);
6152         }
6153 }
6154
6155 static bool
6156 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
6157 {
6158         u8 link_status[DP_LINK_STATUS_SIZE];
6159
6160         if (!intel_dp->link_trained)
6161                 return false;
6162
6163         /*
6164          * While PSR source HW is enabled, it will control main-link sending
6165          * frames, enabling and disabling it so trying to do a retrain will fail
6166          * as the link would or not be on or it could mix training patterns
6167          * and frame data at the same time causing retrain to fail.
6168          * Also when exiting PSR, HW will retrain the link anyways fixing
6169          * any link status error.
6170          */
6171         if (intel_psr_enabled(intel_dp))
6172                 return false;
6173
6174         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
6175                                              link_status) < 0)
6176                 return false;
6177
6178         /*
6179          * Validate the cached values of intel_dp->link_rate and
6180          * intel_dp->lane_count before attempting to retrain.
6181          *
6182          * FIXME would be nice to user the crtc state here, but since
6183          * we need to call this from the short HPD handler that seems
6184          * a bit hard.
6185          */
6186         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
6187                                         intel_dp->lane_count))
6188                 return false;
6189
6190         /* Retrain if Channel EQ or CR not ok */
6191         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
6192 }
6193
6194 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
6195                                    const struct drm_connector_state *conn_state)
6196 {
6197         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6198         struct intel_encoder *encoder;
6199         enum pipe pipe;
6200
6201         if (!conn_state->best_encoder)
6202                 return false;
6203
6204         /* SST */
6205         encoder = &dp_to_dig_port(intel_dp)->base;
6206         if (conn_state->best_encoder == &encoder->base)
6207                 return true;
6208
6209         /* MST */
6210         for_each_pipe(i915, pipe) {
6211                 encoder = &intel_dp->mst_encoders[pipe]->base;
6212                 if (conn_state->best_encoder == &encoder->base)
6213                         return true;
6214         }
6215
6216         return false;
6217 }
6218
6219 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
6220                                       struct drm_modeset_acquire_ctx *ctx,
6221                                       u32 *crtc_mask)
6222 {
6223         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6224         struct drm_connector_list_iter conn_iter;
6225         struct intel_connector *connector;
6226         int ret = 0;
6227
6228         *crtc_mask = 0;
6229
6230         if (!intel_dp_needs_link_retrain(intel_dp))
6231                 return 0;
6232
6233         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
6234         for_each_intel_connector_iter(connector, &conn_iter) {
6235                 struct drm_connector_state *conn_state =
6236                         connector->base.state;
6237                 struct intel_crtc_state *crtc_state;
6238                 struct intel_crtc *crtc;
6239
6240                 if (!intel_dp_has_connector(intel_dp, conn_state))
6241                         continue;
6242
6243                 crtc = to_intel_crtc(conn_state->crtc);
6244                 if (!crtc)
6245                         continue;
6246
6247                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
6248                 if (ret)
6249                         break;
6250
6251                 crtc_state = to_intel_crtc_state(crtc->base.state);
6252
6253                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
6254
6255                 if (!crtc_state->hw.active)
6256                         continue;
6257
6258                 if (conn_state->commit &&
6259                     !try_wait_for_completion(&conn_state->commit->hw_done))
6260                         continue;
6261
6262                 *crtc_mask |= drm_crtc_mask(&crtc->base);
6263         }
6264         drm_connector_list_iter_end(&conn_iter);
6265
6266         if (!intel_dp_needs_link_retrain(intel_dp))
6267                 *crtc_mask = 0;
6268
6269         return ret;
6270 }
6271
6272 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
6273 {
6274         struct intel_connector *connector = intel_dp->attached_connector;
6275
6276         return connector->base.status == connector_status_connected ||
6277                 intel_dp->is_mst;
6278 }
6279
6280 int intel_dp_retrain_link(struct intel_encoder *encoder,
6281                           struct drm_modeset_acquire_ctx *ctx)
6282 {
6283         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6284         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6285         struct intel_crtc *crtc;
6286         u32 crtc_mask;
6287         int ret;
6288
6289         if (!intel_dp_is_connected(intel_dp))
6290                 return 0;
6291
6292         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
6293                                ctx);
6294         if (ret)
6295                 return ret;
6296
6297         ret = intel_dp_prep_link_retrain(intel_dp, ctx, &crtc_mask);
6298         if (ret)
6299                 return ret;
6300
6301         if (crtc_mask == 0)
6302                 return 0;
6303
6304         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
6305                     encoder->base.base.id, encoder->base.name);
6306
6307         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
6308                 const struct intel_crtc_state *crtc_state =
6309                         to_intel_crtc_state(crtc->base.state);
6310
6311                 /* Suppress underruns caused by re-training */
6312                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
6313                 if (crtc_state->has_pch_encoder)
6314                         intel_set_pch_fifo_underrun_reporting(dev_priv,
6315                                                               intel_crtc_pch_transcoder(crtc), false);
6316         }
6317
6318         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
6319                 const struct intel_crtc_state *crtc_state =
6320                         to_intel_crtc_state(crtc->base.state);
6321
6322                 /* retrain on the MST master transcoder */
6323                 if (INTEL_GEN(dev_priv) >= 12 &&
6324                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
6325                     !intel_dp_mst_is_master_trans(crtc_state))
6326                         continue;
6327
6328                 intel_dp_check_frl_training(intel_dp);
6329                 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
6330                 intel_dp_start_link_train(intel_dp, crtc_state);
6331                 intel_dp_stop_link_train(intel_dp, crtc_state);
6332                 break;
6333         }
6334
6335         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
6336                 const struct intel_crtc_state *crtc_state =
6337                         to_intel_crtc_state(crtc->base.state);
6338
6339                 /* Keep underrun reporting disabled until things are stable */
6340                 intel_wait_for_vblank(dev_priv, crtc->pipe);
6341
6342                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
6343                 if (crtc_state->has_pch_encoder)
6344                         intel_set_pch_fifo_underrun_reporting(dev_priv,
6345                                                               intel_crtc_pch_transcoder(crtc), true);
6346         }
6347
6348         return 0;
6349 }
6350
6351 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
6352                                   struct drm_modeset_acquire_ctx *ctx,
6353                                   u32 *crtc_mask)
6354 {
6355         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6356         struct drm_connector_list_iter conn_iter;
6357         struct intel_connector *connector;
6358         int ret = 0;
6359
6360         *crtc_mask = 0;
6361
6362         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
6363         for_each_intel_connector_iter(connector, &conn_iter) {
6364                 struct drm_connector_state *conn_state =
6365                         connector->base.state;
6366                 struct intel_crtc_state *crtc_state;
6367                 struct intel_crtc *crtc;
6368
6369                 if (!intel_dp_has_connector(intel_dp, conn_state))
6370                         continue;
6371
6372                 crtc = to_intel_crtc(conn_state->crtc);
6373                 if (!crtc)
6374                         continue;
6375
6376                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
6377                 if (ret)
6378                         break;
6379
6380                 crtc_state = to_intel_crtc_state(crtc->base.state);
6381
6382                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
6383
6384                 if (!crtc_state->hw.active)
6385                         continue;
6386
6387                 if (conn_state->commit &&
6388                     !try_wait_for_completion(&conn_state->commit->hw_done))
6389                         continue;
6390
6391                 *crtc_mask |= drm_crtc_mask(&crtc->base);
6392         }
6393         drm_connector_list_iter_end(&conn_iter);
6394
6395         return ret;
6396 }
6397
6398 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
6399                                 struct drm_modeset_acquire_ctx *ctx)
6400 {
6401         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6402         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6403         struct intel_crtc *crtc;
6404         u32 crtc_mask;
6405         int ret;
6406
6407         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
6408                                ctx);
6409         if (ret)
6410                 return ret;
6411
6412         ret = intel_dp_prep_phy_test(intel_dp, ctx, &crtc_mask);
6413         if (ret)
6414                 return ret;
6415
6416         if (crtc_mask == 0)
6417                 return 0;
6418
6419         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
6420                     encoder->base.base.id, encoder->base.name);
6421
6422         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
6423                 const struct intel_crtc_state *crtc_state =
6424                         to_intel_crtc_state(crtc->base.state);
6425
6426                 /* test on the MST master transcoder */
6427                 if (INTEL_GEN(dev_priv) >= 12 &&
6428                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
6429                     !intel_dp_mst_is_master_trans(crtc_state))
6430                         continue;
6431
6432                 intel_dp_process_phy_request(intel_dp, crtc_state);
6433                 break;
6434         }
6435
6436         return 0;
6437 }
6438
6439 static void intel_dp_phy_test(struct intel_encoder *encoder)
6440 {
6441         struct drm_modeset_acquire_ctx ctx;
6442         int ret;
6443
6444         drm_modeset_acquire_init(&ctx, 0);
6445
6446         for (;;) {
6447                 ret = intel_dp_do_phy_test(encoder, &ctx);
6448
6449                 if (ret == -EDEADLK) {
6450                         drm_modeset_backoff(&ctx);
6451                         continue;
6452                 }
6453
6454                 break;
6455         }
6456
6457         drm_modeset_drop_locks(&ctx);
6458         drm_modeset_acquire_fini(&ctx);
6459         drm_WARN(encoder->base.dev, ret,
6460                  "Acquiring modeset locks failed with %i\n", ret);
6461 }
6462
6463 /*
6464  * If display is now connected check links status,
6465  * there has been known issues of link loss triggering
6466  * long pulse.
6467  *
6468  * Some sinks (eg. ASUS PB287Q) seem to perform some
6469  * weird HPD ping pong during modesets. So we can apparently
6470  * end up with HPD going low during a modeset, and then
6471  * going back up soon after. And once that happens we must
6472  * retrain the link to get a picture. That's in case no
6473  * userspace component reacted to intermittent HPD dip.
6474  */
6475 static enum intel_hotplug_state
6476 intel_dp_hotplug(struct intel_encoder *encoder,
6477                  struct intel_connector *connector)
6478 {
6479         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6480         struct drm_modeset_acquire_ctx ctx;
6481         enum intel_hotplug_state state;
6482         int ret;
6483
6484         if (intel_dp->compliance.test_active &&
6485             intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
6486                 intel_dp_phy_test(encoder);
6487                 /* just do the PHY test and nothing else */
6488                 return INTEL_HOTPLUG_UNCHANGED;
6489         }
6490
6491         state = intel_encoder_hotplug(encoder, connector);
6492
6493         drm_modeset_acquire_init(&ctx, 0);
6494
6495         for (;;) {
6496                 ret = intel_dp_retrain_link(encoder, &ctx);
6497
6498                 if (ret == -EDEADLK) {
6499                         drm_modeset_backoff(&ctx);
6500                         continue;
6501                 }
6502
6503                 break;
6504         }
6505
6506         drm_modeset_drop_locks(&ctx);
6507         drm_modeset_acquire_fini(&ctx);
6508         drm_WARN(encoder->base.dev, ret,
6509                  "Acquiring modeset locks failed with %i\n", ret);
6510
6511         /*
6512          * Keeping it consistent with intel_ddi_hotplug() and
6513          * intel_hdmi_hotplug().
6514          */
6515         if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
6516                 state = INTEL_HOTPLUG_RETRY;
6517
6518         return state;
6519 }
6520
6521 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
6522 {
6523         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6524         u8 val;
6525
6526         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
6527                 return;
6528
6529         if (drm_dp_dpcd_readb(&intel_dp->aux,
6530                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
6531                 return;
6532
6533         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
6534
6535         if (val & DP_AUTOMATED_TEST_REQUEST)
6536                 intel_dp_handle_test_request(intel_dp);
6537
6538         if (val & DP_CP_IRQ)
6539                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
6540
6541         if (val & DP_SINK_SPECIFIC_IRQ)
6542                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
6543 }
6544
6545 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
6546 {
6547         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6548         u8 val;
6549
6550         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
6551                 return;
6552
6553         if (drm_dp_dpcd_readb(&intel_dp->aux,
6554                               DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val) {
6555                 drm_dbg_kms(&i915->drm, "Error in reading link service irq vector\n");
6556                 return;
6557         }
6558
6559         if (drm_dp_dpcd_writeb(&intel_dp->aux,
6560                                DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1) {
6561                 drm_dbg_kms(&i915->drm, "Error in writing link service irq vector\n");
6562                 return;
6563         }
6564
6565         if (val & HDMI_LINK_STATUS_CHANGED)
6566                 intel_dp_handle_hdmi_link_status_change(intel_dp);
6567 }
6568
6569 /*
6570  * According to DP spec
6571  * 5.1.2:
6572  *  1. Read DPCD
6573  *  2. Configure link according to Receiver Capabilities
6574  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
6575  *  4. Check link status on receipt of hot-plug interrupt
6576  *
6577  * intel_dp_short_pulse -  handles short pulse interrupts
6578  * when full detection is not required.
6579  * Returns %true if short pulse is handled and full detection
6580  * is NOT required and %false otherwise.
6581  */
6582 static bool
6583 intel_dp_short_pulse(struct intel_dp *intel_dp)
6584 {
6585         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6586         u8 old_sink_count = intel_dp->sink_count;
6587         bool ret;
6588
6589         /*
6590          * Clearing compliance test variables to allow capturing
6591          * of values for next automated test request.
6592          */
6593         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
6594
6595         /*
6596          * Now read the DPCD to see if it's actually running
6597          * If the current value of sink count doesn't match with
6598          * the value that was stored earlier or dpcd read failed
6599          * we need to do full detection
6600          */
6601         ret = intel_dp_get_dpcd(intel_dp);
6602
6603         if ((old_sink_count != intel_dp->sink_count) || !ret) {
6604                 /* No need to proceed if we are going to do full detect */
6605                 return false;
6606         }
6607
6608         intel_dp_check_device_service_irq(intel_dp);
6609         intel_dp_check_link_service_irq(intel_dp);
6610
6611         /* Handle CEC interrupts, if any */
6612         drm_dp_cec_irq(&intel_dp->aux);
6613
6614         /* defer to the hotplug work for link retraining if needed */
6615         if (intel_dp_needs_link_retrain(intel_dp))
6616                 return false;
6617
6618         intel_psr_short_pulse(intel_dp);
6619
6620         switch (intel_dp->compliance.test_type) {
6621         case DP_TEST_LINK_TRAINING:
6622                 drm_dbg_kms(&dev_priv->drm,
6623                             "Link Training Compliance Test requested\n");
6624                 /* Send a Hotplug Uevent to userspace to start modeset */
6625                 drm_kms_helper_hotplug_event(&dev_priv->drm);
6626                 break;
6627         case DP_TEST_LINK_PHY_TEST_PATTERN:
6628                 drm_dbg_kms(&dev_priv->drm,
6629                             "PHY test pattern Compliance Test requested\n");
6630                 /*
6631                  * Schedule long hpd to do the test
6632                  *
6633                  * FIXME get rid of the ad-hoc phy test modeset code
6634                  * and properly incorporate it into the normal modeset.
6635                  */
6636                 return false;
6637         }
6638
6639         return true;
6640 }
6641
6642 /* XXX this is probably wrong for multiple downstream ports */
6643 static enum drm_connector_status
6644 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
6645 {
6646         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6647         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6648         u8 *dpcd = intel_dp->dpcd;
6649         u8 type;
6650
6651         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
6652                 return connector_status_connected;
6653
6654         lspcon_resume(dig_port);
6655
6656         if (!intel_dp_get_dpcd(intel_dp))
6657                 return connector_status_disconnected;
6658
6659         /* if there's no downstream port, we're done */
6660         if (!drm_dp_is_branch(dpcd))
6661                 return connector_status_connected;
6662
6663         /* If we're HPD-aware, SINK_COUNT changes dynamically */
6664         if (intel_dp_has_sink_count(intel_dp) &&
6665             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
6666                 return intel_dp->sink_count ?
6667                 connector_status_connected : connector_status_disconnected;
6668         }
6669
6670         if (intel_dp_can_mst(intel_dp))
6671                 return connector_status_connected;
6672
6673         /* If no HPD, poke DDC gently */
6674         if (drm_probe_ddc(&intel_dp->aux.ddc))
6675                 return connector_status_connected;
6676
6677         /* Well we tried, say unknown for unreliable port types */
6678         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
6679                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
6680                 if (type == DP_DS_PORT_TYPE_VGA ||
6681                     type == DP_DS_PORT_TYPE_NON_EDID)
6682                         return connector_status_unknown;
6683         } else {
6684                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
6685                         DP_DWN_STRM_PORT_TYPE_MASK;
6686                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
6687                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
6688                         return connector_status_unknown;
6689         }
6690
6691         /* Anything else is out of spec, warn and ignore */
6692         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
6693         return connector_status_disconnected;
6694 }
6695
6696 static enum drm_connector_status
6697 edp_detect(struct intel_dp *intel_dp)
6698 {
6699         return connector_status_connected;
6700 }
6701
6702 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
6703 {
6704         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6705         u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
6706
6707         return intel_de_read(dev_priv, SDEISR) & bit;
6708 }
6709
6710 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
6711 {
6712         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6713         u32 bit;
6714
6715         switch (encoder->hpd_pin) {
6716         case HPD_PORT_B:
6717                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
6718                 break;
6719         case HPD_PORT_C:
6720                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
6721                 break;
6722         case HPD_PORT_D:
6723                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
6724                 break;
6725         default:
6726                 MISSING_CASE(encoder->hpd_pin);
6727                 return false;
6728         }
6729
6730         return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
6731 }
6732
6733 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
6734 {
6735         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6736         u32 bit;
6737
6738         switch (encoder->hpd_pin) {
6739         case HPD_PORT_B:
6740                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
6741                 break;
6742         case HPD_PORT_C:
6743                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
6744                 break;
6745         case HPD_PORT_D:
6746                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
6747                 break;
6748         default:
6749                 MISSING_CASE(encoder->hpd_pin);
6750                 return false;
6751         }
6752
6753         return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
6754 }
6755
6756 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
6757 {
6758         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6759         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
6760
6761         return intel_de_read(dev_priv, DEISR) & bit;
6762 }
6763
6764 /*
6765  * intel_digital_port_connected - is the specified port connected?
6766  * @encoder: intel_encoder
6767  *
6768  * In cases where there's a connector physically connected but it can't be used
6769  * by our hardware we also return false, since the rest of the driver should
6770  * pretty much treat the port as disconnected. This is relevant for type-C
6771  * (starting on ICL) where there's ownership involved.
6772  *
6773  * Return %true if port is connected, %false otherwise.
6774  */
6775 bool intel_digital_port_connected(struct intel_encoder *encoder)
6776 {
6777         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6778         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
6779         bool is_connected = false;
6780         intel_wakeref_t wakeref;
6781
6782         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
6783                 is_connected = dig_port->connected(encoder);
6784
6785         return is_connected;
6786 }
6787
6788 static struct edid *
6789 intel_dp_get_edid(struct intel_dp *intel_dp)
6790 {
6791         struct intel_connector *intel_connector = intel_dp->attached_connector;
6792
6793         /* use cached edid if we have one */
6794         if (intel_connector->edid) {
6795                 /* invalid edid */
6796                 if (IS_ERR(intel_connector->edid))
6797                         return NULL;
6798
6799                 return drm_edid_duplicate(intel_connector->edid);
6800         } else
6801                 return drm_get_edid(&intel_connector->base,
6802                                     &intel_dp->aux.ddc);
6803 }
6804
6805 static void
6806 intel_dp_update_dfp(struct intel_dp *intel_dp,
6807                     const struct edid *edid)
6808 {
6809         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6810         struct intel_connector *connector = intel_dp->attached_connector;
6811
6812         intel_dp->dfp.max_bpc =
6813                 drm_dp_downstream_max_bpc(intel_dp->dpcd,
6814                                           intel_dp->downstream_ports, edid);
6815
6816         intel_dp->dfp.max_dotclock =
6817                 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
6818                                                intel_dp->downstream_ports);
6819
6820         intel_dp->dfp.min_tmds_clock =
6821                 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
6822                                                  intel_dp->downstream_ports,
6823                                                  edid);
6824         intel_dp->dfp.max_tmds_clock =
6825                 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
6826                                                  intel_dp->downstream_ports,
6827                                                  edid);
6828
6829         intel_dp->dfp.pcon_max_frl_bw =
6830                 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
6831                                            intel_dp->downstream_ports);
6832
6833         drm_dbg_kms(&i915->drm,
6834                     "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
6835                     connector->base.base.id, connector->base.name,
6836                     intel_dp->dfp.max_bpc,
6837                     intel_dp->dfp.max_dotclock,
6838                     intel_dp->dfp.min_tmds_clock,
6839                     intel_dp->dfp.max_tmds_clock,
6840                     intel_dp->dfp.pcon_max_frl_bw);
6841
6842         intel_dp_get_pcon_dsc_cap(intel_dp);
6843 }
6844
6845 static void
6846 intel_dp_update_420(struct intel_dp *intel_dp)
6847 {
6848         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6849         struct intel_connector *connector = intel_dp->attached_connector;
6850         bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420;
6851
6852         /* No YCbCr output support on gmch platforms */
6853         if (HAS_GMCH(i915))
6854                 return;
6855
6856         /*
6857          * ILK doesn't seem capable of DP YCbCr output. The
6858          * displayed image is severly corrupted. SNB+ is fine.
6859          */
6860         if (IS_GEN(i915, 5))
6861                 return;
6862
6863         is_branch = drm_dp_is_branch(intel_dp->dpcd);
6864         ycbcr_420_passthrough =
6865                 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
6866                                                   intel_dp->downstream_ports);
6867         /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
6868         ycbcr_444_to_420 =
6869                 dp_to_dig_port(intel_dp)->lspcon.active ||
6870                 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
6871                                                         intel_dp->downstream_ports);
6872
6873         if (INTEL_GEN(i915) >= 11) {
6874                 /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
6875                 intel_dp->dfp.ycbcr_444_to_420 =
6876                         ycbcr_444_to_420 && !ycbcr_420_passthrough;
6877
6878                 connector->base.ycbcr_420_allowed =
6879                         !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
6880         } else {
6881                 /* 4:4:4->4:2:0 conversion is the only way */
6882                 intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
6883
6884                 connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
6885         }
6886
6887         drm_dbg_kms(&i915->drm,
6888                     "[CONNECTOR:%d:%s] YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
6889                     connector->base.base.id, connector->base.name,
6890                     yesno(connector->base.ycbcr_420_allowed),
6891                     yesno(intel_dp->dfp.ycbcr_444_to_420));
6892 }
6893
6894 static void
6895 intel_dp_set_edid(struct intel_dp *intel_dp)
6896 {
6897         struct intel_connector *connector = intel_dp->attached_connector;
6898         struct edid *edid;
6899
6900         intel_dp_unset_edid(intel_dp);
6901         edid = intel_dp_get_edid(intel_dp);
6902         connector->detect_edid = edid;
6903
6904         intel_dp_update_dfp(intel_dp, edid);
6905         intel_dp_update_420(intel_dp);
6906
6907         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
6908                 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
6909                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
6910         }
6911
6912         drm_dp_cec_set_edid(&intel_dp->aux, edid);
6913         intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
6914 }
6915
6916 static void
6917 intel_dp_unset_edid(struct intel_dp *intel_dp)
6918 {
6919         struct intel_connector *connector = intel_dp->attached_connector;
6920
6921         drm_dp_cec_unset_edid(&intel_dp->aux);
6922         kfree(connector->detect_edid);
6923         connector->detect_edid = NULL;
6924
6925         intel_dp->has_hdmi_sink = false;
6926         intel_dp->has_audio = false;
6927         intel_dp->edid_quirks = 0;
6928
6929         intel_dp->dfp.max_bpc = 0;
6930         intel_dp->dfp.max_dotclock = 0;
6931         intel_dp->dfp.min_tmds_clock = 0;
6932         intel_dp->dfp.max_tmds_clock = 0;
6933
6934         intel_dp->dfp.pcon_max_frl_bw = 0;
6935
6936         intel_dp->dfp.ycbcr_444_to_420 = false;
6937         connector->base.ycbcr_420_allowed = false;
6938 }
6939
6940 static int
6941 intel_dp_detect(struct drm_connector *connector,
6942                 struct drm_modeset_acquire_ctx *ctx,
6943                 bool force)
6944 {
6945         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6946         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6947         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6948         struct intel_encoder *encoder = &dig_port->base;
6949         enum drm_connector_status status;
6950
6951         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
6952                     connector->base.id, connector->name);
6953         drm_WARN_ON(&dev_priv->drm,
6954                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
6955
6956         if (!INTEL_DISPLAY_ENABLED(dev_priv))
6957                 return connector_status_disconnected;
6958
6959         /* Can't disconnect eDP */
6960         if (intel_dp_is_edp(intel_dp))
6961                 status = edp_detect(intel_dp);
6962         else if (intel_digital_port_connected(encoder))
6963                 status = intel_dp_detect_dpcd(intel_dp);
6964         else
6965                 status = connector_status_disconnected;
6966
6967         if (status == connector_status_disconnected) {
6968                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
6969                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
6970
6971                 if (intel_dp->is_mst) {
6972                         drm_dbg_kms(&dev_priv->drm,
6973                                     "MST device may have disappeared %d vs %d\n",
6974                                     intel_dp->is_mst,
6975                                     intel_dp->mst_mgr.mst_state);
6976                         intel_dp->is_mst = false;
6977                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6978                                                         intel_dp->is_mst);
6979                 }
6980
6981                 goto out;
6982         }
6983
6984         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
6985         if (INTEL_GEN(dev_priv) >= 11)
6986                 intel_dp_get_dsc_sink_cap(intel_dp);
6987
6988         intel_dp_configure_mst(intel_dp);
6989
6990         /*
6991          * TODO: Reset link params when switching to MST mode, until MST
6992          * supports link training fallback params.
6993          */
6994         if (intel_dp->reset_link_params || intel_dp->is_mst) {
6995                 /* Initial max link lane count */
6996                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
6997
6998                 /* Initial max link rate */
6999                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
7000
7001                 intel_dp->reset_link_params = false;
7002         }
7003
7004         intel_dp_print_rates(intel_dp);
7005
7006         if (intel_dp->is_mst) {
7007                 /*
7008                  * If we are in MST mode then this connector
7009                  * won't appear connected or have anything
7010                  * with EDID on it
7011                  */
7012                 status = connector_status_disconnected;
7013                 goto out;
7014         }
7015
7016         /*
7017          * Some external monitors do not signal loss of link synchronization
7018          * with an IRQ_HPD, so force a link status check.
7019          */
7020         if (!intel_dp_is_edp(intel_dp)) {
7021                 int ret;
7022
7023                 ret = intel_dp_retrain_link(encoder, ctx);
7024                 if (ret)
7025                         return ret;
7026         }
7027
7028         /*
7029          * Clearing NACK and defer counts to get their exact values
7030          * while reading EDID which are required by Compliance tests
7031          * 4.2.2.4 and 4.2.2.5
7032          */
7033         intel_dp->aux.i2c_nack_count = 0;
7034         intel_dp->aux.i2c_defer_count = 0;
7035
7036         intel_dp_set_edid(intel_dp);
7037         if (intel_dp_is_edp(intel_dp) ||
7038             to_intel_connector(connector)->detect_edid)
7039                 status = connector_status_connected;
7040
7041         intel_dp_check_device_service_irq(intel_dp);
7042
7043 out:
7044         if (status != connector_status_connected && !intel_dp->is_mst)
7045                 intel_dp_unset_edid(intel_dp);
7046
7047         /*
7048          * Make sure the refs for power wells enabled during detect are
7049          * dropped to avoid a new detect cycle triggered by HPD polling.
7050          */
7051         intel_display_power_flush_work(dev_priv);
7052
7053         if (!intel_dp_is_edp(intel_dp))
7054                 drm_dp_set_subconnector_property(connector,
7055                                                  status,
7056                                                  intel_dp->dpcd,
7057                                                  intel_dp->downstream_ports);
7058         return status;
7059 }
7060
7061 static void
7062 intel_dp_force(struct drm_connector *connector)
7063 {
7064         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
7065         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
7066         struct intel_encoder *intel_encoder = &dig_port->base;
7067         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
7068         enum intel_display_power_domain aux_domain =
7069                 intel_aux_power_domain(dig_port);
7070         intel_wakeref_t wakeref;
7071
7072         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
7073                     connector->base.id, connector->name);
7074         intel_dp_unset_edid(intel_dp);
7075
7076         if (connector->status != connector_status_connected)
7077                 return;
7078
7079         wakeref = intel_display_power_get(dev_priv, aux_domain);
7080
7081         intel_dp_set_edid(intel_dp);
7082
7083         intel_display_power_put(dev_priv, aux_domain, wakeref);
7084 }
7085
7086 static int intel_dp_get_modes(struct drm_connector *connector)
7087 {
7088         struct intel_connector *intel_connector = to_intel_connector(connector);
7089         struct edid *edid;
7090
7091         edid = intel_connector->detect_edid;
7092         if (edid) {
7093                 int ret = intel_connector_update_modes(connector, edid);
7094                 if (ret)
7095                         return ret;
7096         }
7097
7098         /* if eDP has no EDID, fall back to fixed mode */
7099         if (intel_dp_is_edp(intel_attached_dp(intel_connector)) &&
7100             intel_connector->panel.fixed_mode) {
7101                 struct drm_display_mode *mode;
7102
7103                 mode = drm_mode_duplicate(connector->dev,
7104                                           intel_connector->panel.fixed_mode);
7105                 if (mode) {
7106                         drm_mode_probed_add(connector, mode);
7107                         return 1;
7108                 }
7109         }
7110
7111         if (!edid) {
7112                 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
7113                 struct drm_display_mode *mode;
7114
7115                 mode = drm_dp_downstream_mode(connector->dev,
7116                                               intel_dp->dpcd,
7117                                               intel_dp->downstream_ports);
7118                 if (mode) {
7119                         drm_mode_probed_add(connector, mode);
7120                         return 1;
7121                 }
7122         }
7123
7124         return 0;
7125 }
7126
7127 static int
7128 intel_dp_connector_register(struct drm_connector *connector)
7129 {
7130         struct drm_i915_private *i915 = to_i915(connector->dev);
7131         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
7132         int ret;
7133
7134         ret = intel_connector_register(connector);
7135         if (ret)
7136                 return ret;
7137
7138         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
7139                     intel_dp->aux.name, connector->kdev->kobj.name);
7140
7141         intel_dp->aux.dev = connector->kdev;
7142         ret = drm_dp_aux_register(&intel_dp->aux);
7143         if (!ret)
7144                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
7145         return ret;
7146 }
7147
7148 static void
7149 intel_dp_connector_unregister(struct drm_connector *connector)
7150 {
7151         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
7152
7153         drm_dp_cec_unregister_connector(&intel_dp->aux);
7154         drm_dp_aux_unregister(&intel_dp->aux);
7155         intel_connector_unregister(connector);
7156 }
7157
7158 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
7159 {
7160         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
7161         struct intel_dp *intel_dp = &dig_port->dp;
7162
7163         intel_dp_mst_encoder_cleanup(dig_port);
7164         if (intel_dp_is_edp(intel_dp)) {
7165                 intel_wakeref_t wakeref;
7166
7167                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
7168                 /*
7169                  * vdd might still be enabled do to the delayed vdd off.
7170                  * Make sure vdd is actually turned off here.
7171                  */
7172                 with_pps_lock(intel_dp, wakeref)
7173                         edp_panel_vdd_off_sync(intel_dp);
7174         }
7175
7176         intel_dp_aux_fini(intel_dp);
7177 }
7178
7179 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
7180 {
7181         intel_dp_encoder_flush_work(encoder);
7182
7183         drm_encoder_cleanup(encoder);
7184         kfree(enc_to_dig_port(to_intel_encoder(encoder)));
7185 }
7186
7187 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
7188 {
7189         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
7190         intel_wakeref_t wakeref;
7191
7192         if (!intel_dp_is_edp(intel_dp))
7193                 return;
7194
7195         /*
7196          * vdd might still be enabled do to the delayed vdd off.
7197          * Make sure vdd is actually turned off here.
7198          */
7199         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
7200         with_pps_lock(intel_dp, wakeref)
7201                 edp_panel_vdd_off_sync(intel_dp);
7202 }
7203
7204 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
7205 {
7206         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
7207         intel_wakeref_t wakeref;
7208
7209         if (!intel_dp_is_edp(intel_dp))
7210                 return;
7211
7212         with_pps_lock(intel_dp, wakeref)
7213                 wait_panel_power_cycle(intel_dp);
7214 }
7215
7216 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
7217 {
7218         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7219         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
7220
7221         lockdep_assert_held(&dev_priv->pps_mutex);
7222
7223         if (!edp_have_panel_vdd(intel_dp))
7224                 return;
7225
7226         /*
7227          * The VDD bit needs a power domain reference, so if the bit is
7228          * already enabled when we boot or resume, grab this reference and
7229          * schedule a vdd off, so we don't hold on to the reference
7230          * indefinitely.
7231          */
7232         drm_dbg_kms(&dev_priv->drm,
7233                     "VDD left on by BIOS, adjusting state tracking\n");
7234         intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
7235
7236         edp_panel_vdd_schedule_off(intel_dp);
7237 }
7238
7239 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
7240 {
7241         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7242         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
7243         enum pipe pipe;
7244
7245         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
7246                                   encoder->port, &pipe))
7247                 return pipe;
7248
7249         return INVALID_PIPE;
7250 }
7251
7252 void intel_dp_encoder_reset(struct drm_encoder *encoder)
7253 {
7254         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
7255         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
7256         intel_wakeref_t wakeref;
7257
7258         if (!HAS_DDI(dev_priv))
7259                 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
7260
7261         intel_dp->reset_link_params = true;
7262
7263         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
7264             !intel_dp_is_edp(intel_dp))
7265                 return;
7266
7267         with_pps_lock(intel_dp, wakeref) {
7268                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7269                         intel_dp->active_pipe = vlv_active_pipe(intel_dp);
7270
7271                 if (intel_dp_is_edp(intel_dp)) {
7272                         /*
7273                          * Reinit the power sequencer, in case BIOS did
7274                          * something nasty with it.
7275                          */
7276                         intel_dp_pps_init(intel_dp);
7277                         intel_edp_panel_vdd_sanitize(intel_dp);
7278                 }
7279         }
7280 }
7281
7282 static int intel_modeset_tile_group(struct intel_atomic_state *state,
7283                                     int tile_group_id)
7284 {
7285         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7286         struct drm_connector_list_iter conn_iter;
7287         struct drm_connector *connector;
7288         int ret = 0;
7289
7290         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
7291         drm_for_each_connector_iter(connector, &conn_iter) {
7292                 struct drm_connector_state *conn_state;
7293                 struct intel_crtc_state *crtc_state;
7294                 struct intel_crtc *crtc;
7295
7296                 if (!connector->has_tile ||
7297                     connector->tile_group->id != tile_group_id)
7298                         continue;
7299
7300                 conn_state = drm_atomic_get_connector_state(&state->base,
7301                                                             connector);
7302                 if (IS_ERR(conn_state)) {
7303                         ret = PTR_ERR(conn_state);
7304                         break;
7305                 }
7306
7307                 crtc = to_intel_crtc(conn_state->crtc);
7308
7309                 if (!crtc)
7310                         continue;
7311
7312                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
7313                 crtc_state->uapi.mode_changed = true;
7314
7315                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
7316                 if (ret)
7317                         break;
7318         }
7319         drm_connector_list_iter_end(&conn_iter);
7320
7321         return ret;
7322 }
7323
7324 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
7325 {
7326         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7327         struct intel_crtc *crtc;
7328
7329         if (transcoders == 0)
7330                 return 0;
7331
7332         for_each_intel_crtc(&dev_priv->drm, crtc) {
7333                 struct intel_crtc_state *crtc_state;
7334                 int ret;
7335
7336                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
7337                 if (IS_ERR(crtc_state))
7338                         return PTR_ERR(crtc_state);
7339
7340                 if (!crtc_state->hw.enable)
7341                         continue;
7342
7343                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
7344                         continue;
7345
7346                 crtc_state->uapi.mode_changed = true;
7347
7348                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
7349                 if (ret)
7350                         return ret;
7351
7352                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
7353                 if (ret)
7354                         return ret;
7355
7356                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
7357         }
7358
7359         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
7360
7361         return 0;
7362 }
7363
7364 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
7365                                       struct drm_connector *connector)
7366 {
7367         const struct drm_connector_state *old_conn_state =
7368                 drm_atomic_get_old_connector_state(&state->base, connector);
7369         const struct intel_crtc_state *old_crtc_state;
7370         struct intel_crtc *crtc;
7371         u8 transcoders;
7372
7373         crtc = to_intel_crtc(old_conn_state->crtc);
7374         if (!crtc)
7375                 return 0;
7376
7377         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
7378
7379         if (!old_crtc_state->hw.active)
7380                 return 0;
7381
7382         transcoders = old_crtc_state->sync_mode_slaves_mask;
7383         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
7384                 transcoders |= BIT(old_crtc_state->master_transcoder);
7385
7386         return intel_modeset_affected_transcoders(state,
7387                                                   transcoders);
7388 }
7389
7390 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
7391                                            struct drm_atomic_state *_state)
7392 {
7393         struct drm_i915_private *dev_priv = to_i915(conn->dev);
7394         struct intel_atomic_state *state = to_intel_atomic_state(_state);
7395         int ret;
7396
7397         ret = intel_digital_connector_atomic_check(conn, &state->base);
7398         if (ret)
7399                 return ret;
7400
7401         /*
7402          * We don't enable port sync on BDW due to missing w/as and
7403          * due to not having adjusted the modeset sequence appropriately.
7404          */
7405         if (INTEL_GEN(dev_priv) < 9)
7406                 return 0;
7407
7408         if (!intel_connector_needs_modeset(state, conn))
7409                 return 0;
7410
7411         if (conn->has_tile) {
7412                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
7413                 if (ret)
7414                         return ret;
7415         }
7416
7417         return intel_modeset_synced_crtcs(state, conn);
7418 }
7419
7420 static const struct drm_connector_funcs intel_dp_connector_funcs = {
7421         .force = intel_dp_force,
7422         .fill_modes = drm_helper_probe_single_connector_modes,
7423         .atomic_get_property = intel_digital_connector_atomic_get_property,
7424         .atomic_set_property = intel_digital_connector_atomic_set_property,
7425         .late_register = intel_dp_connector_register,
7426         .early_unregister = intel_dp_connector_unregister,
7427         .destroy = intel_connector_destroy,
7428         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
7429         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
7430 };
7431
7432 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
7433         .detect_ctx = intel_dp_detect,
7434         .get_modes = intel_dp_get_modes,
7435         .mode_valid = intel_dp_mode_valid,
7436         .atomic_check = intel_dp_connector_atomic_check,
7437 };
7438
7439 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
7440         .reset = intel_dp_encoder_reset,
7441         .destroy = intel_dp_encoder_destroy,
7442 };
7443
7444 static bool intel_edp_have_power(struct intel_dp *intel_dp)
7445 {
7446         intel_wakeref_t wakeref;
7447         bool have_power = false;
7448
7449         with_pps_lock(intel_dp, wakeref) {
7450                 have_power = edp_have_panel_power(intel_dp) &&
7451                                                   edp_have_panel_vdd(intel_dp);
7452         }
7453
7454         return have_power;
7455 }
7456
7457 enum irqreturn
7458 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
7459 {
7460         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
7461         struct intel_dp *intel_dp = &dig_port->dp;
7462
7463         if (dig_port->base.type == INTEL_OUTPUT_EDP &&
7464             (long_hpd || !intel_edp_have_power(intel_dp))) {
7465                 /*
7466                  * vdd off can generate a long/short pulse on eDP which
7467                  * would require vdd on to handle it, and thus we
7468                  * would end up in an endless cycle of
7469                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
7470                  */
7471                 drm_dbg_kms(&i915->drm,
7472                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
7473                             long_hpd ? "long" : "short",
7474                             dig_port->base.base.base.id,
7475                             dig_port->base.base.name);
7476                 return IRQ_HANDLED;
7477         }
7478
7479         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
7480                     dig_port->base.base.base.id,
7481                     dig_port->base.base.name,
7482                     long_hpd ? "long" : "short");
7483
7484         if (long_hpd) {
7485                 intel_dp->reset_link_params = true;
7486                 return IRQ_NONE;
7487         }
7488
7489         if (intel_dp->is_mst) {
7490                 if (!intel_dp_check_mst_status(intel_dp))
7491                         return IRQ_NONE;
7492         } else if (!intel_dp_short_pulse(intel_dp)) {
7493                 return IRQ_NONE;
7494         }
7495
7496         return IRQ_HANDLED;
7497 }
7498
7499 /* check the VBT to see whether the eDP is on another port */
7500 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
7501 {
7502         /*
7503          * eDP not supported on g4x. so bail out early just
7504          * for a bit extra safety in case the VBT is bonkers.
7505          */
7506         if (INTEL_GEN(dev_priv) < 5)
7507                 return false;
7508
7509         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
7510                 return true;
7511
7512         return intel_bios_is_port_edp(dev_priv, port);
7513 }
7514
7515 static void
7516 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
7517 {
7518         struct drm_i915_private *dev_priv = to_i915(connector->dev);
7519         enum port port = dp_to_dig_port(intel_dp)->base.port;
7520
7521         if (!intel_dp_is_edp(intel_dp))
7522                 drm_connector_attach_dp_subconnector_property(connector);
7523
7524         if (!IS_G4X(dev_priv) && port != PORT_A)
7525                 intel_attach_force_audio_property(connector);
7526
7527         intel_attach_broadcast_rgb_property(connector);
7528         if (HAS_GMCH(dev_priv))
7529                 drm_connector_attach_max_bpc_property(connector, 6, 10);
7530         else if (INTEL_GEN(dev_priv) >= 5)
7531                 drm_connector_attach_max_bpc_property(connector, 6, 12);
7532
7533         intel_attach_colorspace_property(connector);
7534
7535         if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
7536                 drm_object_attach_property(&connector->base,
7537                                            connector->dev->mode_config.hdr_output_metadata_property,
7538                                            0);
7539
7540         if (intel_dp_is_edp(intel_dp)) {
7541                 u32 allowed_scalers;
7542
7543                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
7544                 if (!HAS_GMCH(dev_priv))
7545                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
7546
7547                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
7548
7549                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
7550
7551         }
7552 }
7553
7554 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
7555 {
7556         intel_dp->panel_power_off_time = ktime_get_boottime();
7557         intel_dp->last_power_on = jiffies;
7558         intel_dp->last_backlight_off = jiffies;
7559 }
7560
7561 static void
7562 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
7563 {
7564         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7565         u32 pp_on, pp_off, pp_ctl;
7566         struct pps_registers regs;
7567
7568         intel_pps_get_registers(intel_dp, &regs);
7569
7570         pp_ctl = ilk_get_pp_control(intel_dp);
7571
7572         /* Ensure PPS is unlocked */
7573         if (!HAS_DDI(dev_priv))
7574                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7575
7576         pp_on = intel_de_read(dev_priv, regs.pp_on);
7577         pp_off = intel_de_read(dev_priv, regs.pp_off);
7578
7579         /* Pull timing values out of registers */
7580         seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
7581         seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
7582         seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
7583         seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
7584
7585         if (i915_mmio_reg_valid(regs.pp_div)) {
7586                 u32 pp_div;
7587
7588                 pp_div = intel_de_read(dev_priv, regs.pp_div);
7589
7590                 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
7591         } else {
7592                 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
7593         }
7594 }
7595
7596 static void
7597 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
7598 {
7599         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
7600                       state_name,
7601                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
7602 }
7603
7604 static void
7605 intel_pps_verify_state(struct intel_dp *intel_dp)
7606 {
7607         struct edp_power_seq hw;
7608         struct edp_power_seq *sw = &intel_dp->pps_delays;
7609
7610         intel_pps_readout_hw_state(intel_dp, &hw);
7611
7612         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
7613             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
7614                 DRM_ERROR("PPS state mismatch\n");
7615                 intel_pps_dump_state("sw", sw);
7616                 intel_pps_dump_state("hw", &hw);
7617         }
7618 }
7619
7620 static void
7621 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
7622 {
7623         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7624         struct edp_power_seq cur, vbt, spec,
7625                 *final = &intel_dp->pps_delays;
7626
7627         lockdep_assert_held(&dev_priv->pps_mutex);
7628
7629         /* already initialized? */
7630         if (final->t11_t12 != 0)
7631                 return;
7632
7633         intel_pps_readout_hw_state(intel_dp, &cur);
7634
7635         intel_pps_dump_state("cur", &cur);
7636
7637         vbt = dev_priv->vbt.edp.pps;
7638         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
7639          * of 500ms appears to be too short. Ocassionally the panel
7640          * just fails to power back on. Increasing the delay to 800ms
7641          * seems sufficient to avoid this problem.
7642          */
7643         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
7644                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
7645                 drm_dbg_kms(&dev_priv->drm,
7646                             "Increasing T12 panel delay as per the quirk to %d\n",
7647                             vbt.t11_t12);
7648         }
7649         /* T11_T12 delay is special and actually in units of 100ms, but zero
7650          * based in the hw (so we need to add 100 ms). But the sw vbt
7651          * table multiplies it with 1000 to make it in units of 100usec,
7652          * too. */
7653         vbt.t11_t12 += 100 * 10;
7654
7655         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
7656          * our hw here, which are all in 100usec. */
7657         spec.t1_t3 = 210 * 10;
7658         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
7659         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
7660         spec.t10 = 500 * 10;
7661         /* This one is special and actually in units of 100ms, but zero
7662          * based in the hw (so we need to add 100 ms). But the sw vbt
7663          * table multiplies it with 1000 to make it in units of 100usec,
7664          * too. */
7665         spec.t11_t12 = (510 + 100) * 10;
7666
7667         intel_pps_dump_state("vbt", &vbt);
7668
7669         /* Use the max of the register settings and vbt. If both are
7670          * unset, fall back to the spec limits. */
7671 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
7672                                        spec.field : \
7673                                        max(cur.field, vbt.field))
7674         assign_final(t1_t3);
7675         assign_final(t8);
7676         assign_final(t9);
7677         assign_final(t10);
7678         assign_final(t11_t12);
7679 #undef assign_final
7680
7681 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
7682         intel_dp->panel_power_up_delay = get_delay(t1_t3);
7683         intel_dp->backlight_on_delay = get_delay(t8);
7684         intel_dp->backlight_off_delay = get_delay(t9);
7685         intel_dp->panel_power_down_delay = get_delay(t10);
7686         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
7687 #undef get_delay
7688
7689         drm_dbg_kms(&dev_priv->drm,
7690                     "panel power up delay %d, power down delay %d, power cycle delay %d\n",
7691                     intel_dp->panel_power_up_delay,
7692                     intel_dp->panel_power_down_delay,
7693                     intel_dp->panel_power_cycle_delay);
7694
7695         drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
7696                     intel_dp->backlight_on_delay,
7697                     intel_dp->backlight_off_delay);
7698
7699         /*
7700          * We override the HW backlight delays to 1 because we do manual waits
7701          * on them. For T8, even BSpec recommends doing it. For T9, if we
7702          * don't do this, we'll end up waiting for the backlight off delay
7703          * twice: once when we do the manual sleep, and once when we disable
7704          * the panel and wait for the PP_STATUS bit to become zero.
7705          */
7706         final->t8 = 1;
7707         final->t9 = 1;
7708
7709         /*
7710          * HW has only a 100msec granularity for t11_t12 so round it up
7711          * accordingly.
7712          */
7713         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
7714 }
7715
7716 static void
7717 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
7718                                               bool force_disable_vdd)
7719 {
7720         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7721         u32 pp_on, pp_off, port_sel = 0;
7722         int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
7723         struct pps_registers regs;
7724         enum port port = dp_to_dig_port(intel_dp)->base.port;
7725         const struct edp_power_seq *seq = &intel_dp->pps_delays;
7726
7727         lockdep_assert_held(&dev_priv->pps_mutex);
7728
7729         intel_pps_get_registers(intel_dp, &regs);
7730
7731         /*
7732          * On some VLV machines the BIOS can leave the VDD
7733          * enabled even on power sequencers which aren't
7734          * hooked up to any port. This would mess up the
7735          * power domain tracking the first time we pick
7736          * one of these power sequencers for use since
7737          * edp_panel_vdd_on() would notice that the VDD was
7738          * already on and therefore wouldn't grab the power
7739          * domain reference. Disable VDD first to avoid this.
7740          * This also avoids spuriously turning the VDD on as
7741          * soon as the new power sequencer gets initialized.
7742          */
7743         if (force_disable_vdd) {
7744                 u32 pp = ilk_get_pp_control(intel_dp);
7745
7746                 drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
7747                          "Panel power already on\n");
7748
7749                 if (pp & EDP_FORCE_VDD)
7750                         drm_dbg_kms(&dev_priv->drm,
7751                                     "VDD already on, disabling first\n");
7752
7753                 pp &= ~EDP_FORCE_VDD;
7754
7755                 intel_de_write(dev_priv, regs.pp_ctrl, pp);
7756         }
7757
7758         pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
7759                 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
7760         pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
7761                 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
7762
7763         /* Haswell doesn't have any port selection bits for the panel
7764          * power sequencer any more. */
7765         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7766                 port_sel = PANEL_PORT_SELECT_VLV(port);
7767         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
7768                 switch (port) {
7769                 case PORT_A:
7770                         port_sel = PANEL_PORT_SELECT_DPA;
7771                         break;
7772                 case PORT_C:
7773                         port_sel = PANEL_PORT_SELECT_DPC;
7774                         break;
7775                 case PORT_D:
7776                         port_sel = PANEL_PORT_SELECT_DPD;
7777                         break;
7778                 default:
7779                         MISSING_CASE(port);
7780                         break;
7781                 }
7782         }
7783
7784         pp_on |= port_sel;
7785
7786         intel_de_write(dev_priv, regs.pp_on, pp_on);
7787         intel_de_write(dev_priv, regs.pp_off, pp_off);
7788
7789         /*
7790          * Compute the divisor for the pp clock, simply match the Bspec formula.
7791          */
7792         if (i915_mmio_reg_valid(regs.pp_div)) {
7793                 intel_de_write(dev_priv, regs.pp_div,
7794                                REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
7795         } else {
7796                 u32 pp_ctl;
7797
7798                 pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl);
7799                 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
7800                 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
7801                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7802         }
7803
7804         drm_dbg_kms(&dev_priv->drm,
7805                     "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
7806                     intel_de_read(dev_priv, regs.pp_on),
7807                     intel_de_read(dev_priv, regs.pp_off),
7808                     i915_mmio_reg_valid(regs.pp_div) ?
7809                     intel_de_read(dev_priv, regs.pp_div) :
7810                     (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
7811 }
7812
7813 static void intel_dp_pps_init(struct intel_dp *intel_dp)
7814 {
7815         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7816
7817         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7818                 vlv_initial_power_sequencer_setup(intel_dp);
7819         } else {
7820                 intel_dp_init_panel_power_sequencer(intel_dp);
7821                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
7822         }
7823 }
7824
7825 /**
7826  * intel_dp_set_drrs_state - program registers for RR switch to take effect
7827  * @dev_priv: i915 device
7828  * @crtc_state: a pointer to the active intel_crtc_state
7829  * @refresh_rate: RR to be programmed
7830  *
7831  * This function gets called when refresh rate (RR) has to be changed from
7832  * one frequency to another. Switches can be between high and low RR
7833  * supported by the panel or to any other RR based on media playback (in
7834  * this case, RR value needs to be passed from user space).
7835  *
7836  * The caller of this function needs to take a lock on dev_priv->drrs.
7837  */
7838 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
7839                                     const struct intel_crtc_state *crtc_state,
7840                                     int refresh_rate)
7841 {
7842         struct intel_dp *intel_dp = dev_priv->drrs.dp;
7843         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
7844         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
7845
7846         if (refresh_rate <= 0) {
7847                 drm_dbg_kms(&dev_priv->drm,
7848                             "Refresh rate should be positive non-zero.\n");
7849                 return;
7850         }
7851
7852         if (intel_dp == NULL) {
7853                 drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
7854                 return;
7855         }
7856
7857         if (!intel_crtc) {
7858                 drm_dbg_kms(&dev_priv->drm,
7859                             "DRRS: intel_crtc not initialized\n");
7860                 return;
7861         }
7862
7863         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
7864                 drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
7865                 return;
7866         }
7867
7868         if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) ==
7869                         refresh_rate)
7870                 index = DRRS_LOW_RR;
7871
7872         if (index == dev_priv->drrs.refresh_rate_type) {
7873                 drm_dbg_kms(&dev_priv->drm,
7874                             "DRRS requested for previously set RR...ignoring\n");
7875                 return;
7876         }
7877
7878         if (!crtc_state->hw.active) {
7879                 drm_dbg_kms(&dev_priv->drm,
7880                             "eDP encoder disabled. CRTC not Active\n");
7881                 return;
7882         }
7883
7884         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
7885                 switch (index) {
7886                 case DRRS_HIGH_RR:
7887                         intel_dp_set_m_n(crtc_state, M1_N1);
7888                         break;
7889                 case DRRS_LOW_RR:
7890                         intel_dp_set_m_n(crtc_state, M2_N2);
7891                         break;
7892                 case DRRS_MAX_RR:
7893                 default:
7894                         drm_err(&dev_priv->drm,
7895                                 "Unsupported refreshrate type\n");
7896                 }
7897         } else if (INTEL_GEN(dev_priv) > 6) {
7898                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
7899                 u32 val;
7900
7901                 val = intel_de_read(dev_priv, reg);
7902                 if (index > DRRS_HIGH_RR) {
7903                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7904                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7905                         else
7906                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
7907                 } else {
7908                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7909                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7910                         else
7911                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
7912                 }
7913                 intel_de_write(dev_priv, reg, val);
7914         }
7915
7916         dev_priv->drrs.refresh_rate_type = index;
7917
7918         drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
7919                     refresh_rate);
7920 }
7921
7922 static void
7923 intel_edp_drrs_enable_locked(struct intel_dp *intel_dp)
7924 {
7925         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7926
7927         dev_priv->drrs.busy_frontbuffer_bits = 0;
7928         dev_priv->drrs.dp = intel_dp;
7929 }
7930
7931 /**
7932  * intel_edp_drrs_enable - init drrs struct if supported
7933  * @intel_dp: DP struct
7934  * @crtc_state: A pointer to the active crtc state.
7935  *
7936  * Initializes frontbuffer_bits and drrs.dp
7937  */
7938 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
7939                            const struct intel_crtc_state *crtc_state)
7940 {
7941         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7942
7943         if (!crtc_state->has_drrs)
7944                 return;
7945
7946         drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
7947
7948         mutex_lock(&dev_priv->drrs.mutex);
7949
7950         if (dev_priv->drrs.dp) {
7951                 drm_warn(&dev_priv->drm, "DRRS already enabled\n");
7952                 goto unlock;
7953         }
7954
7955         intel_edp_drrs_enable_locked(intel_dp);
7956
7957 unlock:
7958         mutex_unlock(&dev_priv->drrs.mutex);
7959 }
7960
7961 static void
7962 intel_edp_drrs_disable_locked(struct intel_dp *intel_dp,
7963                               const struct intel_crtc_state *crtc_state)
7964 {
7965         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7966
7967         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
7968                 int refresh;
7969
7970                 refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
7971                 intel_dp_set_drrs_state(dev_priv, crtc_state, refresh);
7972         }
7973
7974         dev_priv->drrs.dp = NULL;
7975 }
7976
7977 /**
7978  * intel_edp_drrs_disable - Disable DRRS
7979  * @intel_dp: DP struct
7980  * @old_crtc_state: Pointer to old crtc_state.
7981  *
7982  */
7983 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
7984                             const struct intel_crtc_state *old_crtc_state)
7985 {
7986         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7987
7988         if (!old_crtc_state->has_drrs)
7989                 return;
7990
7991         mutex_lock(&dev_priv->drrs.mutex);
7992         if (!dev_priv->drrs.dp) {
7993                 mutex_unlock(&dev_priv->drrs.mutex);
7994                 return;
7995         }
7996
7997         intel_edp_drrs_disable_locked(intel_dp, old_crtc_state);
7998         mutex_unlock(&dev_priv->drrs.mutex);
7999
8000         cancel_delayed_work_sync(&dev_priv->drrs.work);
8001 }
8002
8003 /**
8004  * intel_edp_drrs_update - Update DRRS state
8005  * @intel_dp: Intel DP
8006  * @crtc_state: new CRTC state
8007  *
8008  * This function will update DRRS states, disabling or enabling DRRS when
8009  * executing fastsets. For full modeset, intel_edp_drrs_disable() and
8010  * intel_edp_drrs_enable() should be called instead.
8011  */
8012 void
8013 intel_edp_drrs_update(struct intel_dp *intel_dp,
8014                       const struct intel_crtc_state *crtc_state)
8015 {
8016         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
8017
8018         if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
8019                 return;
8020
8021         mutex_lock(&dev_priv->drrs.mutex);
8022
8023         /* New state matches current one? */
8024         if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
8025                 goto unlock;
8026
8027         if (crtc_state->has_drrs)
8028                 intel_edp_drrs_enable_locked(intel_dp);
8029         else
8030                 intel_edp_drrs_disable_locked(intel_dp, crtc_state);
8031
8032 unlock:
8033         mutex_unlock(&dev_priv->drrs.mutex);
8034 }
8035
8036 static void intel_edp_drrs_downclock_work(struct work_struct *work)
8037 {
8038         struct drm_i915_private *dev_priv =
8039                 container_of(work, typeof(*dev_priv), drrs.work.work);
8040         struct intel_dp *intel_dp;
8041
8042         mutex_lock(&dev_priv->drrs.mutex);
8043
8044         intel_dp = dev_priv->drrs.dp;
8045
8046         if (!intel_dp)
8047                 goto unlock;
8048
8049         /*
8050          * The delayed work can race with an invalidate hence we need to
8051          * recheck.
8052          */
8053
8054         if (dev_priv->drrs.busy_frontbuffer_bits)
8055                 goto unlock;
8056
8057         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
8058                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
8059
8060                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
8061                         drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode));
8062         }
8063
8064 unlock:
8065         mutex_unlock(&dev_priv->drrs.mutex);
8066 }
8067
8068 /**
8069  * intel_edp_drrs_invalidate - Disable Idleness DRRS
8070  * @dev_priv: i915 device
8071  * @frontbuffer_bits: frontbuffer plane tracking bits
8072  *
8073  * This function gets called everytime rendering on the given planes start.
8074  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
8075  *
8076  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
8077  */
8078 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
8079                                unsigned int frontbuffer_bits)
8080 {
8081         struct intel_dp *intel_dp;
8082         struct drm_crtc *crtc;
8083         enum pipe pipe;
8084
8085         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
8086                 return;
8087
8088         cancel_delayed_work(&dev_priv->drrs.work);
8089
8090         mutex_lock(&dev_priv->drrs.mutex);
8091
8092         intel_dp = dev_priv->drrs.dp;
8093         if (!intel_dp) {
8094                 mutex_unlock(&dev_priv->drrs.mutex);
8095                 return;
8096         }
8097
8098         crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
8099         pipe = to_intel_crtc(crtc)->pipe;
8100
8101         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
8102         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
8103
8104         /* invalidate means busy screen hence upclock */
8105         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
8106                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
8107                                         drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
8108
8109         mutex_unlock(&dev_priv->drrs.mutex);
8110 }
8111
8112 /**
8113  * intel_edp_drrs_flush - Restart Idleness DRRS
8114  * @dev_priv: i915 device
8115  * @frontbuffer_bits: frontbuffer plane tracking bits
8116  *
8117  * This function gets called every time rendering on the given planes has
8118  * completed or flip on a crtc is completed. So DRRS should be upclocked
8119  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
8120  * if no other planes are dirty.
8121  *
8122  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
8123  */
8124 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
8125                           unsigned int frontbuffer_bits)
8126 {
8127         struct intel_dp *intel_dp;
8128         struct drm_crtc *crtc;
8129         enum pipe pipe;
8130
8131         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
8132                 return;
8133
8134         cancel_delayed_work(&dev_priv->drrs.work);
8135
8136         mutex_lock(&dev_priv->drrs.mutex);
8137
8138         intel_dp = dev_priv->drrs.dp;
8139         if (!intel_dp) {
8140                 mutex_unlock(&dev_priv->drrs.mutex);
8141                 return;
8142         }
8143
8144         crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
8145         pipe = to_intel_crtc(crtc)->pipe;
8146
8147         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
8148         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
8149
8150         /* flush means busy screen hence upclock */
8151         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
8152                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
8153                                         drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
8154
8155         /*
8156          * flush also means no more activity hence schedule downclock, if all
8157          * other fbs are quiescent too
8158          */
8159         if (!dev_priv->drrs.busy_frontbuffer_bits)
8160                 schedule_delayed_work(&dev_priv->drrs.work,
8161                                 msecs_to_jiffies(1000));
8162         mutex_unlock(&dev_priv->drrs.mutex);
8163 }
8164
8165 /**
8166  * DOC: Display Refresh Rate Switching (DRRS)
8167  *
8168  * Display Refresh Rate Switching (DRRS) is a power conservation feature
8169  * which enables swtching between low and high refresh rates,
8170  * dynamically, based on the usage scenario. This feature is applicable
8171  * for internal panels.
8172  *
8173  * Indication that the panel supports DRRS is given by the panel EDID, which
8174  * would list multiple refresh rates for one resolution.
8175  *
8176  * DRRS is of 2 types - static and seamless.
8177  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
8178  * (may appear as a blink on screen) and is used in dock-undock scenario.
8179  * Seamless DRRS involves changing RR without any visual effect to the user
8180  * and can be used during normal system usage. This is done by programming
8181  * certain registers.
8182  *
8183  * Support for static/seamless DRRS may be indicated in the VBT based on
8184  * inputs from the panel spec.
8185  *
8186  * DRRS saves power by switching to low RR based on usage scenarios.
8187  *
8188  * The implementation is based on frontbuffer tracking implementation.  When
8189  * there is a disturbance on the screen triggered by user activity or a periodic
8190  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
8191  * no movement on screen, after a timeout of 1 second, a switch to low RR is
8192  * made.
8193  *
8194  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
8195  * and intel_edp_drrs_flush() are called.
8196  *
8197  * DRRS can be further extended to support other internal panels and also
8198  * the scenario of video playback wherein RR is set based on the rate
8199  * requested by userspace.
8200  */
8201
8202 /**
8203  * intel_dp_drrs_init - Init basic DRRS work and mutex.
8204  * @connector: eDP connector
8205  * @fixed_mode: preferred mode of panel
8206  *
8207  * This function is  called only once at driver load to initialize basic
8208  * DRRS stuff.
8209  *
8210  * Returns:
8211  * Downclock mode if panel supports it, else return NULL.
8212  * DRRS support is determined by the presence of downclock mode (apart
8213  * from VBT setting).
8214  */
8215 static struct drm_display_mode *
8216 intel_dp_drrs_init(struct intel_connector *connector,
8217                    struct drm_display_mode *fixed_mode)
8218 {
8219         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
8220         struct drm_display_mode *downclock_mode = NULL;
8221
8222         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
8223         mutex_init(&dev_priv->drrs.mutex);
8224
8225         if (INTEL_GEN(dev_priv) <= 6) {
8226                 drm_dbg_kms(&dev_priv->drm,
8227                             "DRRS supported for Gen7 and above\n");
8228                 return NULL;
8229         }
8230
8231         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
8232                 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
8233                 return NULL;
8234         }
8235
8236         downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
8237         if (!downclock_mode) {
8238                 drm_dbg_kms(&dev_priv->drm,
8239                             "Downclock mode is not found. DRRS not supported\n");
8240                 return NULL;
8241         }
8242
8243         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
8244
8245         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
8246         drm_dbg_kms(&dev_priv->drm,
8247                     "seamless DRRS supported for eDP panel.\n");
8248         return downclock_mode;
8249 }
8250
8251 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
8252                                      struct intel_connector *intel_connector)
8253 {
8254         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
8255         struct drm_device *dev = &dev_priv->drm;
8256         struct drm_connector *connector = &intel_connector->base;
8257         struct drm_display_mode *fixed_mode = NULL;
8258         struct drm_display_mode *downclock_mode = NULL;
8259         bool has_dpcd;
8260         enum pipe pipe = INVALID_PIPE;
8261         intel_wakeref_t wakeref;
8262         struct edid *edid;
8263
8264         if (!intel_dp_is_edp(intel_dp))
8265                 return true;
8266
8267         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
8268
8269         /*
8270          * On IBX/CPT we may get here with LVDS already registered. Since the
8271          * driver uses the only internal power sequencer available for both
8272          * eDP and LVDS bail out early in this case to prevent interfering
8273          * with an already powered-on LVDS power sequencer.
8274          */
8275         if (intel_get_lvds_encoder(dev_priv)) {
8276                 drm_WARN_ON(dev,
8277                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
8278                 drm_info(&dev_priv->drm,
8279                          "LVDS was detected, not registering eDP\n");
8280
8281                 return false;
8282         }
8283
8284         with_pps_lock(intel_dp, wakeref) {
8285                 intel_dp_init_panel_power_timestamps(intel_dp);
8286                 intel_dp_pps_init(intel_dp);
8287                 intel_edp_panel_vdd_sanitize(intel_dp);
8288         }
8289
8290         /* Cache DPCD and EDID for edp. */
8291         has_dpcd = intel_edp_init_dpcd(intel_dp);
8292
8293         if (!has_dpcd) {
8294                 /* if this fails, presume the device is a ghost */
8295                 drm_info(&dev_priv->drm,
8296                          "failed to retrieve link info, disabling eDP\n");
8297                 goto out_vdd_off;
8298         }
8299
8300         mutex_lock(&dev->mode_config.mutex);
8301         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
8302         if (edid) {
8303                 if (drm_add_edid_modes(connector, edid)) {
8304                         drm_connector_update_edid_property(connector, edid);
8305                         intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
8306                 } else {
8307                         kfree(edid);
8308                         edid = ERR_PTR(-EINVAL);
8309                 }
8310         } else {
8311                 edid = ERR_PTR(-ENOENT);
8312         }
8313         intel_connector->edid = edid;
8314
8315         fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
8316         if (fixed_mode)
8317                 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
8318
8319         /* fallback to VBT if available for eDP */
8320         if (!fixed_mode)
8321                 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
8322         mutex_unlock(&dev->mode_config.mutex);
8323
8324         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
8325                 /*
8326                  * Figure out the current pipe for the initial backlight setup.
8327                  * If the current pipe isn't valid, try the PPS pipe, and if that
8328                  * fails just assume pipe A.
8329                  */
8330                 pipe = vlv_active_pipe(intel_dp);
8331
8332                 if (pipe != PIPE_A && pipe != PIPE_B)
8333                         pipe = intel_dp->pps_pipe;
8334
8335                 if (pipe != PIPE_A && pipe != PIPE_B)
8336                         pipe = PIPE_A;
8337
8338                 drm_dbg_kms(&dev_priv->drm,
8339                             "using pipe %c for initial backlight setup\n",
8340                             pipe_name(pipe));
8341         }
8342
8343         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
8344         intel_connector->panel.backlight.power = intel_edp_backlight_power;
8345         intel_panel_setup_backlight(connector, pipe);
8346
8347         if (fixed_mode) {
8348                 drm_connector_set_panel_orientation_with_quirk(connector,
8349                                 dev_priv->vbt.orientation,
8350                                 fixed_mode->hdisplay, fixed_mode->vdisplay);
8351         }
8352
8353         return true;
8354
8355 out_vdd_off:
8356         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
8357         /*
8358          * vdd might still be enabled do to the delayed vdd off.
8359          * Make sure vdd is actually turned off here.
8360          */
8361         with_pps_lock(intel_dp, wakeref)
8362                 edp_panel_vdd_off_sync(intel_dp);
8363
8364         return false;
8365 }
8366
8367 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
8368 {
8369         struct intel_connector *intel_connector;
8370         struct drm_connector *connector;
8371
8372         intel_connector = container_of(work, typeof(*intel_connector),
8373                                        modeset_retry_work);
8374         connector = &intel_connector->base;
8375         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
8376                       connector->name);
8377
8378         /* Grab the locks before changing connector property*/
8379         mutex_lock(&connector->dev->mode_config.mutex);
8380         /* Set connector link status to BAD and send a Uevent to notify
8381          * userspace to do a modeset.
8382          */
8383         drm_connector_set_link_status_property(connector,
8384                                                DRM_MODE_LINK_STATUS_BAD);
8385         mutex_unlock(&connector->dev->mode_config.mutex);
8386         /* Send Hotplug uevent so userspace can reprobe */
8387         drm_kms_helper_hotplug_event(connector->dev);
8388 }
8389
8390 bool
8391 intel_dp_init_connector(struct intel_digital_port *dig_port,
8392                         struct intel_connector *intel_connector)
8393 {
8394         struct drm_connector *connector = &intel_connector->base;
8395         struct intel_dp *intel_dp = &dig_port->dp;
8396         struct intel_encoder *intel_encoder = &dig_port->base;
8397         struct drm_device *dev = intel_encoder->base.dev;
8398         struct drm_i915_private *dev_priv = to_i915(dev);
8399         enum port port = intel_encoder->port;
8400         enum phy phy = intel_port_to_phy(dev_priv, port);
8401         int type;
8402
8403         /* Initialize the work for modeset in case of link train failure */
8404         INIT_WORK(&intel_connector->modeset_retry_work,
8405                   intel_dp_modeset_retry_work_fn);
8406
8407         if (drm_WARN(dev, dig_port->max_lanes < 1,
8408                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
8409                      dig_port->max_lanes, intel_encoder->base.base.id,
8410                      intel_encoder->base.name))
8411                 return false;
8412
8413         intel_dp_set_source_rates(intel_dp);
8414
8415         intel_dp->reset_link_params = true;
8416         intel_dp->pps_pipe = INVALID_PIPE;
8417         intel_dp->active_pipe = INVALID_PIPE;
8418
8419         /* Preserve the current hw state. */
8420         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
8421         intel_dp->attached_connector = intel_connector;
8422
8423         if (intel_dp_is_port_edp(dev_priv, port)) {
8424                 /*
8425                  * Currently we don't support eDP on TypeC ports, although in
8426                  * theory it could work on TypeC legacy ports.
8427                  */
8428                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
8429                 type = DRM_MODE_CONNECTOR_eDP;
8430         } else {
8431                 type = DRM_MODE_CONNECTOR_DisplayPort;
8432         }
8433
8434         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
8435                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
8436
8437         /*
8438          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
8439          * for DP the encoder type can be set by the caller to
8440          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
8441          */
8442         if (type == DRM_MODE_CONNECTOR_eDP)
8443                 intel_encoder->type = INTEL_OUTPUT_EDP;
8444
8445         /* eDP only on port B and/or C on vlv/chv */
8446         if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
8447                               IS_CHERRYVIEW(dev_priv)) &&
8448                         intel_dp_is_edp(intel_dp) &&
8449                         port != PORT_B && port != PORT_C))
8450                 return false;
8451
8452         drm_dbg_kms(&dev_priv->drm,
8453                     "Adding %s connector on [ENCODER:%d:%s]\n",
8454                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
8455                     intel_encoder->base.base.id, intel_encoder->base.name);
8456
8457         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
8458         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
8459
8460         if (!HAS_GMCH(dev_priv))
8461                 connector->interlace_allowed = true;
8462         connector->doublescan_allowed = 0;
8463
8464         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
8465
8466         intel_dp_aux_init(intel_dp);
8467
8468         intel_connector_attach_encoder(intel_connector, intel_encoder);
8469
8470         if (HAS_DDI(dev_priv))
8471                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
8472         else
8473                 intel_connector->get_hw_state = intel_connector_get_hw_state;
8474
8475         /* init MST on ports that can support it */
8476         intel_dp_mst_encoder_init(dig_port,
8477                                   intel_connector->base.base.id);
8478
8479         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
8480                 intel_dp_aux_fini(intel_dp);
8481                 intel_dp_mst_encoder_cleanup(dig_port);
8482                 goto fail;
8483         }
8484
8485         intel_dp_add_properties(intel_dp, connector);
8486
8487         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
8488                 int ret = intel_dp_init_hdcp(dig_port, intel_connector);
8489                 if (ret)
8490                         drm_dbg_kms(&dev_priv->drm,
8491                                     "HDCP init failed, skipping.\n");
8492         }
8493
8494         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
8495          * 0xd.  Failure to do so will result in spurious interrupts being
8496          * generated on the port when a cable is not attached.
8497          */
8498         if (IS_G45(dev_priv)) {
8499                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
8500                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
8501                                (temp & ~0xf) | 0xd);
8502         }
8503
8504         intel_dp->frl.is_trained = false;
8505         intel_dp->frl.trained_rate_gbps = 0;
8506
8507         return true;
8508
8509 fail:
8510         drm_connector_cleanup(connector);
8511
8512         return false;
8513 }
8514
8515 bool intel_dp_init(struct drm_i915_private *dev_priv,
8516                    i915_reg_t output_reg,
8517                    enum port port)
8518 {
8519         struct intel_digital_port *dig_port;
8520         struct intel_encoder *intel_encoder;
8521         struct drm_encoder *encoder;
8522         struct intel_connector *intel_connector;
8523
8524         dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
8525         if (!dig_port)
8526                 return false;
8527
8528         intel_connector = intel_connector_alloc();
8529         if (!intel_connector)
8530                 goto err_connector_alloc;
8531
8532         intel_encoder = &dig_port->base;
8533         encoder = &intel_encoder->base;
8534
8535         mutex_init(&dig_port->hdcp_mutex);
8536
8537         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
8538                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
8539                              "DP %c", port_name(port)))
8540                 goto err_encoder_init;
8541
8542         intel_encoder->hotplug = intel_dp_hotplug;
8543         intel_encoder->compute_config = intel_dp_compute_config;
8544         intel_encoder->get_hw_state = intel_dp_get_hw_state;
8545         intel_encoder->get_config = intel_dp_get_config;
8546         intel_encoder->sync_state = intel_dp_sync_state;
8547         intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
8548         intel_encoder->update_pipe = intel_panel_update_backlight;
8549         intel_encoder->suspend = intel_dp_encoder_suspend;
8550         intel_encoder->shutdown = intel_dp_encoder_shutdown;
8551         if (IS_CHERRYVIEW(dev_priv)) {
8552                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
8553                 intel_encoder->pre_enable = chv_pre_enable_dp;
8554                 intel_encoder->enable = vlv_enable_dp;
8555                 intel_encoder->disable = vlv_disable_dp;
8556                 intel_encoder->post_disable = chv_post_disable_dp;
8557                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
8558         } else if (IS_VALLEYVIEW(dev_priv)) {
8559                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
8560                 intel_encoder->pre_enable = vlv_pre_enable_dp;
8561                 intel_encoder->enable = vlv_enable_dp;
8562                 intel_encoder->disable = vlv_disable_dp;
8563                 intel_encoder->post_disable = vlv_post_disable_dp;
8564         } else {
8565                 intel_encoder->pre_enable = g4x_pre_enable_dp;
8566                 intel_encoder->enable = g4x_enable_dp;
8567                 intel_encoder->disable = g4x_disable_dp;
8568                 intel_encoder->post_disable = g4x_post_disable_dp;
8569         }
8570
8571         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
8572             (HAS_PCH_CPT(dev_priv) && port != PORT_A))
8573                 dig_port->dp.set_link_train = cpt_set_link_train;
8574         else
8575                 dig_port->dp.set_link_train = g4x_set_link_train;
8576
8577         if (IS_CHERRYVIEW(dev_priv))
8578                 dig_port->dp.set_signal_levels = chv_set_signal_levels;
8579         else if (IS_VALLEYVIEW(dev_priv))
8580                 dig_port->dp.set_signal_levels = vlv_set_signal_levels;
8581         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
8582                 dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels;
8583         else if (IS_GEN(dev_priv, 6) && port == PORT_A)
8584                 dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels;
8585         else
8586                 dig_port->dp.set_signal_levels = g4x_set_signal_levels;
8587
8588         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
8589             (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
8590                 dig_port->dp.preemph_max = intel_dp_preemph_max_3;
8591                 dig_port->dp.voltage_max = intel_dp_voltage_max_3;
8592         } else {
8593                 dig_port->dp.preemph_max = intel_dp_preemph_max_2;
8594                 dig_port->dp.voltage_max = intel_dp_voltage_max_2;
8595         }
8596
8597         dig_port->dp.output_reg = output_reg;
8598         dig_port->max_lanes = 4;
8599
8600         intel_encoder->type = INTEL_OUTPUT_DP;
8601         intel_encoder->power_domain = intel_port_to_power_domain(port);
8602         if (IS_CHERRYVIEW(dev_priv)) {
8603                 if (port == PORT_D)
8604                         intel_encoder->pipe_mask = BIT(PIPE_C);
8605                 else
8606                         intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
8607         } else {
8608                 intel_encoder->pipe_mask = ~0;
8609         }
8610         intel_encoder->cloneable = 0;
8611         intel_encoder->port = port;
8612         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
8613
8614         dig_port->hpd_pulse = intel_dp_hpd_pulse;
8615
8616         if (HAS_GMCH(dev_priv)) {
8617                 if (IS_GM45(dev_priv))
8618                         dig_port->connected = gm45_digital_port_connected;
8619                 else
8620                         dig_port->connected = g4x_digital_port_connected;
8621         } else {
8622                 if (port == PORT_A)
8623                         dig_port->connected = ilk_digital_port_connected;
8624                 else
8625                         dig_port->connected = ibx_digital_port_connected;
8626         }
8627
8628         if (port != PORT_A)
8629                 intel_infoframe_init(dig_port);
8630
8631         dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
8632         if (!intel_dp_init_connector(dig_port, intel_connector))
8633                 goto err_init_connector;
8634
8635         return true;
8636
8637 err_init_connector:
8638         drm_encoder_cleanup(encoder);
8639 err_encoder_init:
8640         kfree(intel_connector);
8641 err_connector_alloc:
8642         kfree(dig_port);
8643         return false;
8644 }
8645
8646 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
8647 {
8648         struct intel_encoder *encoder;
8649
8650         for_each_intel_encoder(&dev_priv->drm, encoder) {
8651                 struct intel_dp *intel_dp;
8652
8653                 if (encoder->type != INTEL_OUTPUT_DDI)
8654                         continue;
8655
8656                 intel_dp = enc_to_intel_dp(encoder);
8657
8658                 if (!intel_dp->can_mst)
8659                         continue;
8660
8661                 if (intel_dp->is_mst)
8662                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
8663         }
8664 }
8665
8666 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
8667 {
8668         struct intel_encoder *encoder;
8669
8670         for_each_intel_encoder(&dev_priv->drm, encoder) {
8671                 struct intel_dp *intel_dp;
8672                 int ret;
8673
8674                 if (encoder->type != INTEL_OUTPUT_DDI)
8675                         continue;
8676
8677                 intel_dp = enc_to_intel_dp(encoder);
8678
8679                 if (!intel_dp->can_mst)
8680                         continue;
8681
8682                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
8683                                                      true);
8684                 if (ret) {
8685                         intel_dp->is_mst = false;
8686                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
8687                                                         false);
8688                 }
8689         }
8690 }