drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/slab.h>
  32 #include <linux/types.h>
  33
  34 #include <asm/byteorder.h>
  35
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_dp_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_probe_helper.h>
  41
  42 #include "g4x_dp.h"
  43 #include "i915_debugfs.h"
  44 #include "i915_drv.h"
  45 #include "intel_atomic.h"
  46 #include "intel_audio.h"
  47 #include "intel_connector.h"
  48 #include "intel_ddi.h"
  49 #include "intel_de.h"
  50 #include "intel_display_types.h"
  51 #include "intel_dp.h"
  52 #include "intel_dp_aux.h"
  53 #include "intel_dp_hdcp.h"
  54 #include "intel_dp_link_training.h"
  55 #include "intel_dp_mst.h"
  56 #include "intel_dpio_phy.h"
  57 #include "intel_dpll.h"
  58 #include "intel_fifo_underrun.h"
  59 #include "intel_hdcp.h"
  60 #include "intel_hdmi.h"
  61 #include "intel_hotplug.h"
  62 #include "intel_lspcon.h"
  63 #include "intel_lvds.h"
  64 #include "intel_panel.h"
  65 #include "intel_pps.h"
  66 #include "intel_psr.h"
  67 #include "intel_sideband.h"
  68 #include "intel_tc.h"
  69 #include "intel_vdsc.h"
  70 #include "intel_vrr.h"
  71
  72 #define DP_DPRX_ESI_LEN 14
  73
  74 /* DP DSC throughput values used for slice count calculations KPixels/s */
  75 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  76 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  77 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  78
  79 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  80 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  81
  82 /* Compliance test status bits  */
  83 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  84 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  85 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  86 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  87
  88
  89 /* Constants for DP DSC configurations */
  90 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
  91
  92 /* With Single pipe configuration, HW is capable of supporting maximum
  93  * of 4 slices per line.
  94  */
  95 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
  96
  97 /**
  98  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  99  * @intel_dp: DP struct
 100  *
 101  * If a CPU or PCH DP output is attached to an eDP panel, this function
 102  * will return true, and false otherwise.
 103  */
 104 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 105 {
 106         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 107
 108         return dig_port->base.type == INTEL_OUTPUT_EDP;
 109 }
 110
 111 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 112 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
 113
 114 /* update sink rates from dpcd */
 115 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 116 {
 117         static const int dp_rates[] = {
 118                 162000, 270000, 540000, 810000
 119         };
 120         int i, max_rate;
 121         int max_lttpr_rate;
 122
 123         if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 124                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 125                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 126
 127                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 128                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 129
 130                 return;
 131         }
 132
 133         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 134         max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 135         if (max_lttpr_rate)
 136                 max_rate = min(max_rate, max_lttpr_rate);
 137
 138         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 139                 if (dp_rates[i] > max_rate)
 140                         break;
 141                 intel_dp->sink_rates[i] = dp_rates[i];
 142         }
 143
 144         intel_dp->num_sink_rates = i;
 145 }
 146
 147 /* Get length of rates array potentially limited by max_rate. */
 148 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 149 {
 150         int i;
 151
 152         /* Limit results by potentially reduced max rate */
 153         for (i = 0; i < len; i++) {
 154                 if (rates[len - i - 1] <= max_rate)
 155                         return len - i;
 156         }
 157
 158         return 0;
 159 }
 160
 161 /* Get length of common rates array potentially limited by max_rate. */
 162 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 163                                           int max_rate)
 164 {
 165         return intel_dp_rate_limit_len(intel_dp->common_rates,
 166                                        intel_dp->num_common_rates, max_rate);
 167 }
 168
 169 /* Theoretical max between source and sink */
 170 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 171 {
 172         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 173 }
 174
 175 /* Theoretical max between source and sink */
 176 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 177 {
 178         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 179         int source_max = dig_port->max_lanes;
 180         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 181         int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
 182         int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 183
 184         if (lttpr_max)
 185                 sink_max = min(sink_max, lttpr_max);
 186
 187         return min3(source_max, sink_max, fia_max);
 188 }
 189
 190 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 191 {
 192         return intel_dp->max_link_lane_count;
 193 }
 194
 195 int
 196 intel_dp_link_required(int pixel_clock, int bpp)
 197 {
 198         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 199         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 200 }
 201
 202 int
 203 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 204 {
 205         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 206          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 207          * is transmitted every LS_Clk per lane, there is no need to account for
 208          * the channel encoding that is done in the PHY layer here.
 209          */
 210
 211         return max_link_clock * max_lanes;
 212 }
 213
 214 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 215 {
 216         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 217         struct intel_encoder *encoder = &intel_dig_port->base;
 218         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 219
 220         return DISPLAY_VER(dev_priv) >= 12 ||
 221                 (DISPLAY_VER(dev_priv) == 11 &&
 222                  encoder->port != PORT_A);
 223 }
 224
 225 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 226 {
 227         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 228         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 229         enum port port = dig_port->base.port;
 230
 231         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 232
 233         /* Low voltage SKUs are limited to max of 5.4G */
 234         if (voltage == VOLTAGE_INFO_0_85V)
 235                 return 540000;
 236
 237         /* For this SKU 8.1G is supported in all ports */
 238         if (IS_CNL_WITH_PORT_F(dev_priv))
 239                 return 810000;
 240
 241         /* For other SKUs, max rate on ports A and D is 5.4G */
 242         if (port == PORT_A || port == PORT_D)
 243                 return 540000;
 244
 245         return 810000;
 246 }
 247
 248 static int icl_max_source_rate(struct intel_dp *intel_dp)
 249 {
 250         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 251         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 252         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 253
 254         if (intel_phy_is_combo(dev_priv, phy) &&
 255             !intel_dp_is_edp(intel_dp))
 256                 return 540000;
 257
 258         return 810000;
 259 }
 260
 261 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 262 {
 263         if (intel_dp_is_edp(intel_dp))
 264                 return 540000;
 265
 266         return 810000;
 267 }
 268
 269 static void
 270 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 271 {
 272         /* The values must be in increasing order */
 273         static const int cnl_rates[] = {
 274                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 275         };
 276         static const int bxt_rates[] = {
 277                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 278         };
 279         static const int skl_rates[] = {
 280                 162000, 216000, 270000, 324000, 432000, 540000
 281         };
 282         static const int hsw_rates[] = {
 283                 162000, 270000, 540000
 284         };
 285         static const int g4x_rates[] = {
 286                 162000, 270000
 287         };
 288         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 289         struct intel_encoder *encoder = &dig_port->base;
 290         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 291         const int *source_rates;
 292         int size, max_rate = 0, vbt_max_rate;
 293
 294         /* This should only be done once */
 295         drm_WARN_ON(&dev_priv->drm,
 296                     intel_dp->source_rates || intel_dp->num_source_rates);
 297
 298         if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
 299                 source_rates = cnl_rates;
 300                 size = ARRAY_SIZE(cnl_rates);
 301                 if (DISPLAY_VER(dev_priv) == 10)
 302                         max_rate = cnl_max_source_rate(intel_dp);
 303                 else if (IS_JSL_EHL(dev_priv))
 304                         max_rate = ehl_max_source_rate(intel_dp);
 305                 else
 306                         max_rate = icl_max_source_rate(intel_dp);
 307         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 308                 source_rates = bxt_rates;
 309                 size = ARRAY_SIZE(bxt_rates);
 310         } else if (DISPLAY_VER(dev_priv) == 9) {
 311                 source_rates = skl_rates;
 312                 size = ARRAY_SIZE(skl_rates);
 313         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 314                    IS_BROADWELL(dev_priv)) {
 315                 source_rates = hsw_rates;
 316                 size = ARRAY_SIZE(hsw_rates);
 317         } else {
 318                 source_rates = g4x_rates;
 319                 size = ARRAY_SIZE(g4x_rates);
 320         }
 321
 322         vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
 323         if (max_rate && vbt_max_rate)
 324                 max_rate = min(max_rate, vbt_max_rate);
 325         else if (vbt_max_rate)
 326                 max_rate = vbt_max_rate;
 327
 328         if (max_rate)
 329                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 330
 331         intel_dp->source_rates = source_rates;
 332         intel_dp->num_source_rates = size;
 333 }
 334
 335 static int intersect_rates(const int *source_rates, int source_len,
 336                            const int *sink_rates, int sink_len,
 337                            int *common_rates)
 338 {
 339         int i = 0, j = 0, k = 0;
 340
 341         while (i < source_len && j < sink_len) {
 342                 if (source_rates[i] == sink_rates[j]) {
 343                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 344                                 return k;
 345                         common_rates[k] = source_rates[i];
 346                         ++k;
 347                         ++i;
 348                         ++j;
 349                 } else if (source_rates[i] < sink_rates[j]) {
 350                         ++i;
 351                 } else {
 352                         ++j;
 353                 }
 354         }
 355         return k;
 356 }
 357
 358 /* return index of rate in rates array, or -1 if not found */
 359 static int intel_dp_rate_index(const int *rates, int len, int rate)
 360 {
 361         int i;
 362
 363         for (i = 0; i < len; i++)
 364                 if (rate == rates[i])
 365                         return i;
 366
 367         return -1;
 368 }
 369
 370 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 371 {
 372         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 373
 374         drm_WARN_ON(&i915->drm,
 375                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 376
 377         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 378                                                      intel_dp->num_source_rates,
 379                                                      intel_dp->sink_rates,
 380                                                      intel_dp->num_sink_rates,
 381                                                      intel_dp->common_rates);
 382
 383         /* Paranoia, there should always be something in common. */
 384         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 385                 intel_dp->common_rates[0] = 162000;
 386                 intel_dp->num_common_rates = 1;
 387         }
 388 }
 389
 390 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 391                                        u8 lane_count)
 392 {
 393         /*
 394          * FIXME: we need to synchronize the current link parameters with
 395          * hardware readout. Currently fast link training doesn't work on
 396          * boot-up.
 397          */
 398         if (link_rate == 0 ||
 399             link_rate > intel_dp->max_link_rate)
 400                 return false;
 401
 402         if (lane_count == 0 ||
 403             lane_count > intel_dp_max_lane_count(intel_dp))
 404                 return false;
 405
 406         return true;
 407 }
 408
 409 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 410                                                      int link_rate,
 411                                                      u8 lane_count)
 412 {
 413         const struct drm_display_mode *fixed_mode =
 414                 intel_dp->attached_connector->panel.fixed_mode;
 415         int mode_rate, max_rate;
 416
 417         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 418         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 419         if (mode_rate > max_rate)
 420                 return false;
 421
 422         return true;
 423 }
 424
 425 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 426                                             int link_rate, u8 lane_count)
 427 {
 428         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 429         int index;
 430
 431         /*
 432          * TODO: Enable fallback on MST links once MST link compute can handle
 433          * the fallback params.
 434          */
 435         if (intel_dp->is_mst) {
 436                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 437                 return -1;
 438         }
 439
 440         if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
 441                 drm_dbg_kms(&i915->drm,
 442                             "Retrying Link training for eDP with max parameters\n");
 443                 intel_dp->use_max_params = true;
 444                 return 0;
 445         }
 446
 447         index = intel_dp_rate_index(intel_dp->common_rates,
 448                                     intel_dp->num_common_rates,
 449                                     link_rate);
 450         if (index > 0) {
 451                 if (intel_dp_is_edp(intel_dp) &&
 452                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 453                                                               intel_dp->common_rates[index - 1],
 454                                                               lane_count)) {
 455                         drm_dbg_kms(&i915->drm,
 456                                     "Retrying Link training for eDP with same parameters\n");
 457                         return 0;
 458                 }
 459                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 460                 intel_dp->max_link_lane_count = lane_count;
 461         } else if (lane_count > 1) {
 462                 if (intel_dp_is_edp(intel_dp) &&
 463                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 464                                                               intel_dp_max_common_rate(intel_dp),
 465                                                               lane_count >> 1)) {
 466                         drm_dbg_kms(&i915->drm,
 467                                     "Retrying Link training for eDP with same parameters\n");
 468                         return 0;
 469                 }
 470                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 471                 intel_dp->max_link_lane_count = lane_count >> 1;
 472         } else {
 473                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 474                 return -1;
 475         }
 476
 477         return 0;
 478 }
 479
 480 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 481 {
 482         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 483                        DP_DSC_FEC_OVERHEAD_FACTOR);
 484 }
 485
 486 static int
 487 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 488 {
 489         if (DISPLAY_VER(i915) >= 11)
 490                 return 7680 * 8;
 491         else
 492                 return 6144 * 8;
 493 }
 494
 495 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 496                                        u32 link_clock, u32 lane_count,
 497                                        u32 mode_clock, u32 mode_hdisplay,
 498                                        bool bigjoiner,
 499                                        u32 pipe_bpp)
 500 {
 501         u32 bits_per_pixel, max_bpp_small_joiner_ram;
 502         int i;
 503
 504         /*
 505          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 506          * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
 507          * for SST -> TimeSlotsPerMTP is 1,
 508          * for MST -> TimeSlotsPerMTP has to be calculated
 509          */
 510         bits_per_pixel = (link_clock * lane_count * 8) /
 511                          intel_dp_mode_to_fec_clock(mode_clock);
 512         drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
 513
 514         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 515         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 516                 mode_hdisplay;
 517
 518         if (bigjoiner)
 519                 max_bpp_small_joiner_ram *= 2;
 520
 521         drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
 522                     max_bpp_small_joiner_ram);
 523
 524         /*
 525          * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 526          * check, output bpp from small joiner RAM check)
 527          */
 528         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 529
 530         if (bigjoiner) {
 531                 u32 max_bpp_bigjoiner =
 532                         i915->max_cdclk_freq * 48 /
 533                         intel_dp_mode_to_fec_clock(mode_clock);
 534
 535                 DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
 536                 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
 537         }
 538
 539         /* Error out if the max bpp is less than smallest allowed valid bpp */
 540         if (bits_per_pixel < valid_dsc_bpp[0]) {
 541                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 542                             bits_per_pixel, valid_dsc_bpp[0]);
 543                 return 0;
 544         }
 545
 546         /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
 547         if (DISPLAY_VER(i915) >= 13) {
 548                 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
 549         } else {
 550                 /* Find the nearest match in the array of known BPPs from VESA */
 551                 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 552                         if (bits_per_pixel < valid_dsc_bpp[i + 1])
 553                                 break;
 554                 }
 555                 bits_per_pixel = valid_dsc_bpp[i];
 556         }
 557
 558         /*
 559          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 560          * fractional part is 0
 561          */
 562         return bits_per_pixel << 4;
 563 }
 564
 565 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 566                                        int mode_clock, int mode_hdisplay,
 567                                        bool bigjoiner)
 568 {
 569         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 570         u8 min_slice_count, i;
 571         int max_slice_width;
 572
 573         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 574                 min_slice_count = DIV_ROUND_UP(mode_clock,
 575                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 576         else
 577                 min_slice_count = DIV_ROUND_UP(mode_clock,
 578                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 579
 580         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 581         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 582                 drm_dbg_kms(&i915->drm,
 583                             "Unsupported slice width %d by DP DSC Sink device\n",
 584                             max_slice_width);
 585                 return 0;
 586         }
 587         /* Also take into account max slice width */
 588         min_slice_count = max_t(u8, min_slice_count,
 589                                 DIV_ROUND_UP(mode_hdisplay,
 590                                              max_slice_width));
 591
 592         /* Find the closest match to the valid slice count values */
 593         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 594                 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 595
 596                 if (test_slice_count >
 597                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
 598                         break;
 599
 600                 /* big joiner needs small joiner to be enabled */
 601                 if (bigjoiner && test_slice_count < 4)
 602                         continue;
 603
 604                 if (min_slice_count <= test_slice_count)
 605                         return test_slice_count;
 606         }
 607
 608         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 609                     min_slice_count);
 610         return 0;
 611 }
 612
 613 static enum intel_output_format
 614 intel_dp_output_format(struct drm_connector *connector,
 615                        const struct drm_display_mode *mode)
 616 {
 617         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 618         const struct drm_display_info *info = &connector->display_info;
 619
 620         if (!connector->ycbcr_420_allowed ||
 621             !drm_mode_is_420_only(info, mode))
 622                 return INTEL_OUTPUT_FORMAT_RGB;
 623
 624         if (intel_dp->dfp.rgb_to_ycbcr &&
 625             intel_dp->dfp.ycbcr_444_to_420)
 626                 return INTEL_OUTPUT_FORMAT_RGB;
 627
 628         if (intel_dp->dfp.ycbcr_444_to_420)
 629                 return INTEL_OUTPUT_FORMAT_YCBCR444;
 630         else
 631                 return INTEL_OUTPUT_FORMAT_YCBCR420;
 632 }
 633
 634 int intel_dp_min_bpp(enum intel_output_format output_format)
 635 {
 636         if (output_format == INTEL_OUTPUT_FORMAT_RGB)
 637                 return 6 * 3;
 638         else
 639                 return 8 * 3;
 640 }
 641
 642 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
 643 {
 644         /*
 645          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
 646          * format of the number of bytes per pixel will be half the number
 647          * of bytes of RGB pixel.
 648          */
 649         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 650                 bpp /= 2;
 651
 652         return bpp;
 653 }
 654
 655 static int
 656 intel_dp_mode_min_output_bpp(struct drm_connector *connector,
 657                              const struct drm_display_mode *mode)
 658 {
 659         enum intel_output_format output_format =
 660                 intel_dp_output_format(connector, mode);
 661
 662         return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
 663 }
 664
 665 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 666                                   int hdisplay)
 667 {
 668         /*
 669          * Older platforms don't like hdisplay==4096 with DP.
 670          *
 671          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
 672          * and frame counter increment), but we don't get vblank interrupts,
 673          * and the pipe underruns immediately. The link also doesn't seem
 674          * to get trained properly.
 675          *
 676          * On CHV the vblank interrupts don't seem to disappear but
 677          * otherwise the symptoms are similar.
 678          *
 679          * TODO: confirm the behaviour on HSW+
 680          */
 681         return hdisplay == 4096 && !HAS_DDI(dev_priv);
 682 }
 683
 684 static enum drm_mode_status
 685 intel_dp_mode_valid_downstream(struct intel_connector *connector,
 686                                const struct drm_display_mode *mode,
 687                                int target_clock)
 688 {
 689         struct intel_dp *intel_dp = intel_attached_dp(connector);
 690         const struct drm_display_info *info = &connector->base.display_info;
 691         int tmds_clock;
 692
 693         /* If PCON supports FRL MODE, check FRL bandwidth constraints */
 694         if (intel_dp->dfp.pcon_max_frl_bw) {
 695                 int target_bw;
 696                 int max_frl_bw;
 697                 int bpp = intel_dp_mode_min_output_bpp(&connector->base, mode);
 698
 699                 target_bw = bpp * target_clock;
 700
 701                 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
 702
 703                 /* converting bw from Gbps to Kbps*/
 704                 max_frl_bw = max_frl_bw * 1000000;
 705
 706                 if (target_bw > max_frl_bw)
 707                         return MODE_CLOCK_HIGH;
 708
 709                 return MODE_OK;
 710         }
 711
 712         if (intel_dp->dfp.max_dotclock &&
 713             target_clock > intel_dp->dfp.max_dotclock)
 714                 return MODE_CLOCK_HIGH;
 715
 716         /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
 717         tmds_clock = target_clock;
 718         if (drm_mode_is_420_only(info, mode))
 719                 tmds_clock /= 2;
 720
 721         if (intel_dp->dfp.min_tmds_clock &&
 722             tmds_clock < intel_dp->dfp.min_tmds_clock)
 723                 return MODE_CLOCK_LOW;
 724         if (intel_dp->dfp.max_tmds_clock &&
 725             tmds_clock > intel_dp->dfp.max_tmds_clock)
 726                 return MODE_CLOCK_HIGH;
 727
 728         return MODE_OK;
 729 }
 730
 731 static enum drm_mode_status
 732 intel_dp_mode_valid(struct drm_connector *connector,
 733                     struct drm_display_mode *mode)
 734 {
 735         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 736         struct intel_connector *intel_connector = to_intel_connector(connector);
 737         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 738         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 739         int target_clock = mode->clock;
 740         int max_rate, mode_rate, max_lanes, max_link_clock;
 741         int max_dotclk = dev_priv->max_dotclk_freq;
 742         u16 dsc_max_output_bpp = 0;
 743         u8 dsc_slice_count = 0;
 744         enum drm_mode_status status;
 745         bool dsc = false, bigjoiner = false;
 746
 747         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 748                 return MODE_NO_DBLESCAN;
 749
 750         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 751                 return MODE_H_ILLEGAL;
 752
 753         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 754                 if (mode->hdisplay != fixed_mode->hdisplay)
 755                         return MODE_PANEL;
 756
 757                 if (mode->vdisplay != fixed_mode->vdisplay)
 758                         return MODE_PANEL;
 759
 760                 target_clock = fixed_mode->clock;
 761         }
 762
 763         if (mode->clock < 10000)
 764                 return MODE_CLOCK_LOW;
 765
 766         if ((target_clock > max_dotclk || mode->hdisplay > 5120) &&
 767             intel_dp_can_bigjoiner(intel_dp)) {
 768                 bigjoiner = true;
 769                 max_dotclk *= 2;
 770         }
 771         if (target_clock > max_dotclk)
 772                 return MODE_CLOCK_HIGH;
 773
 774         max_link_clock = intel_dp_max_link_rate(intel_dp);
 775         max_lanes = intel_dp_max_lane_count(intel_dp);
 776
 777         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 778         mode_rate = intel_dp_link_required(target_clock,
 779                                            intel_dp_mode_min_output_bpp(connector, mode));
 780
 781         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
 782                 return MODE_H_ILLEGAL;
 783
 784         /*
 785          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 786          * integer value since we support only integer values of bpp.
 787          */
 788         if (DISPLAY_VER(dev_priv) >= 10 &&
 789             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 790                 /*
 791                  * TBD pass the connector BPC,
 792                  * for now U8_MAX so that max BPC on that platform would be picked
 793                  */
 794                 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
 795
 796                 if (intel_dp_is_edp(intel_dp)) {
 797                         dsc_max_output_bpp =
 798                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 799                         dsc_slice_count =
 800                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 801                                                                 true);
 802                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 803                         dsc_max_output_bpp =
 804                                 intel_dp_dsc_get_output_bpp(dev_priv,
 805                                                             max_link_clock,
 806                                                             max_lanes,
 807                                                             target_clock,
 808                                                             mode->hdisplay,
 809                                                             bigjoiner,
 810                                                             pipe_bpp) >> 4;
 811                         dsc_slice_count =
 812                                 intel_dp_dsc_get_slice_count(intel_dp,
 813                                                              target_clock,
 814                                                              mode->hdisplay,
 815                                                              bigjoiner);
 816                 }
 817
 818                 dsc = dsc_max_output_bpp && dsc_slice_count;
 819         }
 820
 821         /*
 822          * Big joiner configuration needs DSC for TGL which is not true for
 823          * XE_LPD where uncompressed joiner is supported.
 824          */
 825         if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
 826                 return MODE_CLOCK_HIGH;
 827
 828         if (mode_rate > max_rate && !dsc)
 829                 return MODE_CLOCK_HIGH;
 830
 831         status = intel_dp_mode_valid_downstream(intel_connector,
 832                                                 mode, target_clock);
 833         if (status != MODE_OK)
 834                 return status;
 835
 836         return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
 837 }
 838
 839 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
 840 {
 841         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
 842
 843         return max_rate >= 540000;
 844 }
 845
 846 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
 847 {
 848         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
 849
 850         return max_rate >= 810000;
 851 }
 852
 853 static void snprintf_int_array(char *str, size_t len,
 854                                const int *array, int nelem)
 855 {
 856         int i;
 857
 858         str[0] = '\0';
 859
 860         for (i = 0; i < nelem; i++) {
 861                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
 862                 if (r >= len)
 863                         return;
 864                 str += r;
 865                 len -= r;
 866         }
 867 }
 868
 869 static void intel_dp_print_rates(struct intel_dp *intel_dp)
 870 {
 871         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 872         char str[128]; /* FIXME: too big for stack? */
 873
 874         if (!drm_debug_enabled(DRM_UT_KMS))
 875                 return;
 876
 877         snprintf_int_array(str, sizeof(str),
 878                            intel_dp->source_rates, intel_dp->num_source_rates);
 879         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
 880
 881         snprintf_int_array(str, sizeof(str),
 882                            intel_dp->sink_rates, intel_dp->num_sink_rates);
 883         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
 884
 885         snprintf_int_array(str, sizeof(str),
 886                            intel_dp->common_rates, intel_dp->num_common_rates);
 887         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
 888 }
 889
 890 int
 891 intel_dp_max_link_rate(struct intel_dp *intel_dp)
 892 {
 893         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 894         int len;
 895
 896         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
 897         if (drm_WARN_ON(&i915->drm, len <= 0))
 898                 return 162000;
 899
 900         return intel_dp->common_rates[len - 1];
 901 }
 902
 903 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
 904 {
 905         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 906         int i = intel_dp_rate_index(intel_dp->sink_rates,
 907                                     intel_dp->num_sink_rates, rate);
 908
 909         if (drm_WARN_ON(&i915->drm, i < 0))
 910                 i = 0;
 911
 912         return i;
 913 }
 914
 915 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
 916                            u8 *link_bw, u8 *rate_select)
 917 {
 918         /* eDP 1.4 rate select method. */
 919         if (intel_dp->use_rate_select) {
 920                 *link_bw = 0;
 921                 *rate_select =
 922                         intel_dp_rate_select(intel_dp, port_clock);
 923         } else {
 924                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
 925                 *rate_select = 0;
 926         }
 927 }
 928
 929 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
 930                                          const struct intel_crtc_state *pipe_config)
 931 {
 932         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 933
 934         /* On TGL, FEC is supported on all Pipes */
 935         if (DISPLAY_VER(dev_priv) >= 12)
 936                 return true;
 937
 938         if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A)
 939                 return true;
 940
 941         return false;
 942 }
 943
 944 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
 945                                   const struct intel_crtc_state *pipe_config)
 946 {
 947         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
 948                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
 949 }
 950
 951 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
 952                                   const struct intel_crtc_state *crtc_state)
 953 {
 954         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
 955                 return false;
 956
 957         return intel_dsc_source_support(crtc_state) &&
 958                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
 959 }
 960
 961 static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp,
 962                                    const struct intel_crtc_state *crtc_state)
 963 {
 964         return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
 965                 (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
 966                  intel_dp->dfp.ycbcr_444_to_420);
 967 }
 968
 969 static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp,
 970                                     const struct intel_crtc_state *crtc_state, int bpc)
 971 {
 972         int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8;
 973
 974         if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state))
 975                 clock /= 2;
 976
 977         return clock;
 978 }
 979
 980 static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
 981                                            const struct intel_crtc_state *crtc_state, int bpc)
 982 {
 983         int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc);
 984
 985         if (intel_dp->dfp.min_tmds_clock &&
 986             tmds_clock < intel_dp->dfp.min_tmds_clock)
 987                 return false;
 988
 989         if (intel_dp->dfp.max_tmds_clock &&
 990             tmds_clock > intel_dp->dfp.max_tmds_clock)
 991                 return false;
 992
 993         return true;
 994 }
 995
 996 static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp,
 997                                               const struct intel_crtc_state *crtc_state,
 998                                               int bpc)
 999 {
1000
1001         return intel_hdmi_deep_color_possible(crtc_state, bpc,
1002                                               intel_dp->has_hdmi_sink,
1003                                               intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
1004                 intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
1005 }
1006
1007 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1008                             const struct intel_crtc_state *crtc_state)
1009 {
1010         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1011         struct intel_connector *intel_connector = intel_dp->attached_connector;
1012         int bpp, bpc;
1013
1014         bpc = crtc_state->pipe_bpp / 3;
1015
1016         if (intel_dp->dfp.max_bpc)
1017                 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1018
1019         if (intel_dp->dfp.min_tmds_clock) {
1020                 for (; bpc >= 10; bpc -= 2) {
1021                         if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc))
1022                                 break;
1023                 }
1024         }
1025
1026         bpp = bpc * 3;
1027         if (intel_dp_is_edp(intel_dp)) {
1028                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1029                 if (intel_connector->base.display_info.bpc == 0 &&
1030                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1031                         drm_dbg_kms(&dev_priv->drm,
1032                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
1033                                     dev_priv->vbt.edp.bpp);
1034                         bpp = dev_priv->vbt.edp.bpp;
1035                 }
1036         }
1037
1038         return bpp;
1039 }
1040
1041 /* Adjust link config limits based on compliance test requests. */
1042 void
1043 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1044                                   struct intel_crtc_state *pipe_config,
1045                                   struct link_config_limits *limits)
1046 {
1047         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1048
1049         /* For DP Compliance we override the computed bpp for the pipe */
1050         if (intel_dp->compliance.test_data.bpc != 0) {
1051                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1052
1053                 limits->min_bpp = limits->max_bpp = bpp;
1054                 pipe_config->dither_force_disable = bpp == 6 * 3;
1055
1056                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1057         }
1058
1059         /* Use values requested by Compliance Test Request */
1060         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1061                 int index;
1062
1063                 /* Validate the compliance test data since max values
1064                  * might have changed due to link train fallback.
1065                  */
1066                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1067                                                intel_dp->compliance.test_lane_count)) {
1068                         index = intel_dp_rate_index(intel_dp->common_rates,
1069                                                     intel_dp->num_common_rates,
1070                                                     intel_dp->compliance.test_link_rate);
1071                         if (index >= 0)
1072                                 limits->min_clock = limits->max_clock = index;
1073                         limits->min_lane_count = limits->max_lane_count =
1074                                 intel_dp->compliance.test_lane_count;
1075                 }
1076         }
1077 }
1078
1079 /* Optimize link config in order: max bpp, min clock, min lanes */
1080 static int
1081 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1082                                   struct intel_crtc_state *pipe_config,
1083                                   const struct link_config_limits *limits)
1084 {
1085         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1086         int bpp, clock, lane_count;
1087         int mode_rate, link_clock, link_avail;
1088
1089         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1090                 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1091
1092                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1093                                                    output_bpp);
1094
1095                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1096                         for (lane_count = limits->min_lane_count;
1097                              lane_count <= limits->max_lane_count;
1098                              lane_count <<= 1) {
1099                                 link_clock = intel_dp->common_rates[clock];
1100                                 link_avail = intel_dp_max_data_rate(link_clock,
1101                                                                     lane_count);
1102
1103                                 if (mode_rate <= link_avail) {
1104                                         pipe_config->lane_count = lane_count;
1105                                         pipe_config->pipe_bpp = bpp;
1106                                         pipe_config->port_clock = link_clock;
1107
1108                                         return 0;
1109                                 }
1110                         }
1111                 }
1112         }
1113
1114         return -EINVAL;
1115 }
1116
1117 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
1118 {
1119         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1120         int i, num_bpc;
1121         u8 dsc_bpc[3] = {0};
1122         u8 dsc_max_bpc;
1123
1124         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1125         if (DISPLAY_VER(i915) >= 12)
1126                 dsc_max_bpc = min_t(u8, 12, max_req_bpc);
1127         else
1128                 dsc_max_bpc = min_t(u8, 10, max_req_bpc);
1129
1130         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1131                                                        dsc_bpc);
1132         for (i = 0; i < num_bpc; i++) {
1133                 if (dsc_max_bpc >= dsc_bpc[i])
1134                         return dsc_bpc[i] * 3;
1135         }
1136
1137         return 0;
1138 }
1139
1140 #define DSC_SUPPORTED_VERSION_MIN               1
1141
1142 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
1143                                        struct intel_crtc_state *crtc_state)
1144 {
1145         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1146         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1147         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1148         u8 line_buf_depth;
1149         int ret;
1150
1151         /*
1152          * RC_MODEL_SIZE is currently a constant across all configurations.
1153          *
1154          * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1155          * DP_DSC_RC_BUF_SIZE for this.
1156          */
1157         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1158
1159         /*
1160          * Slice Height of 8 works for all currently available panels. So start
1161          * with that if pic_height is an integral multiple of 8. Eventually add
1162          * logic to try multiple slice heights.
1163          */
1164         if (vdsc_cfg->pic_height % 8 == 0)
1165                 vdsc_cfg->slice_height = 8;
1166         else if (vdsc_cfg->pic_height % 4 == 0)
1167                 vdsc_cfg->slice_height = 4;
1168         else
1169                 vdsc_cfg->slice_height = 2;
1170
1171         ret = intel_dsc_compute_params(encoder, crtc_state);
1172         if (ret)
1173                 return ret;
1174
1175         vdsc_cfg->dsc_version_major =
1176                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1177                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1178         vdsc_cfg->dsc_version_minor =
1179                 min(DSC_SUPPORTED_VERSION_MIN,
1180                     (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1181                      DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
1182
1183         vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1184                 DP_DSC_RGB;
1185
1186         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
1187         if (!line_buf_depth) {
1188                 drm_dbg_kms(&i915->drm,
1189                             "DSC Sink Line Buffer Depth invalid\n");
1190                 return -EINVAL;
1191         }
1192
1193         if (vdsc_cfg->dsc_version_minor == 2)
1194                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1195                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1196         else
1197                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1198                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1199
1200         vdsc_cfg->block_pred_enable =
1201                 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1202                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1203
1204         return drm_dsc_compute_rc_parameters(vdsc_cfg);
1205 }
1206
1207 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1208                                        struct intel_crtc_state *pipe_config,
1209                                        struct drm_connector_state *conn_state,
1210                                        struct link_config_limits *limits)
1211 {
1212         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1213         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1214         const struct drm_display_mode *adjusted_mode =
1215                 &pipe_config->hw.adjusted_mode;
1216         int pipe_bpp;
1217         int ret;
1218
1219         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1220                 intel_dp_supports_fec(intel_dp, pipe_config);
1221
1222         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1223                 return -EINVAL;
1224
1225         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
1226
1227         /* Min Input BPC for ICL+ is 8 */
1228         if (pipe_bpp < 8 * 3) {
1229                 drm_dbg_kms(&dev_priv->drm,
1230                             "No DSC support for less than 8bpc\n");
1231                 return -EINVAL;
1232         }
1233
1234         /*
1235          * For now enable DSC for max bpp, max link rate, max lane count.
1236          * Optimize this later for the minimum possible link rate/lane count
1237          * with DSC enabled for the requested mode.
1238          */
1239         pipe_config->pipe_bpp = pipe_bpp;
1240         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
1241         pipe_config->lane_count = limits->max_lane_count;
1242
1243         if (intel_dp_is_edp(intel_dp)) {
1244                 pipe_config->dsc.compressed_bpp =
1245                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1246                               pipe_config->pipe_bpp);
1247                 pipe_config->dsc.slice_count =
1248                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1249                                                         true);
1250         } else {
1251                 u16 dsc_max_output_bpp;
1252                 u8 dsc_dp_slice_count;
1253
1254                 dsc_max_output_bpp =
1255                         intel_dp_dsc_get_output_bpp(dev_priv,
1256                                                     pipe_config->port_clock,
1257                                                     pipe_config->lane_count,
1258                                                     adjusted_mode->crtc_clock,
1259                                                     adjusted_mode->crtc_hdisplay,
1260                                                     pipe_config->bigjoiner,
1261                                                     pipe_bpp);
1262                 dsc_dp_slice_count =
1263                         intel_dp_dsc_get_slice_count(intel_dp,
1264                                                      adjusted_mode->crtc_clock,
1265                                                      adjusted_mode->crtc_hdisplay,
1266                                                      pipe_config->bigjoiner);
1267                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1268                         drm_dbg_kms(&dev_priv->drm,
1269                                     "Compressed BPP/Slice Count not supported\n");
1270                         return -EINVAL;
1271                 }
1272                 pipe_config->dsc.compressed_bpp = min_t(u16,
1273                                                                dsc_max_output_bpp >> 4,
1274                                                                pipe_config->pipe_bpp);
1275                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
1276         }
1277         /*
1278          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1279          * is greater than the maximum Cdclock and if slice count is even
1280          * then we need to use 2 VDSC instances.
1281          */
1282         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
1283             pipe_config->bigjoiner) {
1284                 if (pipe_config->dsc.slice_count < 2) {
1285                         drm_dbg_kms(&dev_priv->drm,
1286                                     "Cannot split stream to use 2 VDSC instances\n");
1287                         return -EINVAL;
1288                 }
1289
1290                 pipe_config->dsc.dsc_split = true;
1291         }
1292
1293         ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
1294         if (ret < 0) {
1295                 drm_dbg_kms(&dev_priv->drm,
1296                             "Cannot compute valid DSC parameters for Input Bpp = %d "
1297                             "Compressed BPP = %d\n",
1298                             pipe_config->pipe_bpp,
1299                             pipe_config->dsc.compressed_bpp);
1300                 return ret;
1301         }
1302
1303         pipe_config->dsc.compression_enable = true;
1304         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
1305                     "Compressed Bpp = %d Slice Count = %d\n",
1306                     pipe_config->pipe_bpp,
1307                     pipe_config->dsc.compressed_bpp,
1308                     pipe_config->dsc.slice_count);
1309
1310         return 0;
1311 }
1312
1313 static int
1314 intel_dp_compute_link_config(struct intel_encoder *encoder,
1315                              struct intel_crtc_state *pipe_config,
1316                              struct drm_connector_state *conn_state)
1317 {
1318         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1319         const struct drm_display_mode *adjusted_mode =
1320                 &pipe_config->hw.adjusted_mode;
1321         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1322         struct link_config_limits limits;
1323         int common_len;
1324         int ret;
1325
1326         common_len = intel_dp_common_len_rate_limit(intel_dp,
1327                                                     intel_dp->max_link_rate);
1328
1329         /* No common link rates between source and sink */
1330         drm_WARN_ON(encoder->base.dev, common_len <= 0);
1331
1332         limits.min_clock = 0;
1333         limits.max_clock = common_len - 1;
1334
1335         limits.min_lane_count = 1;
1336         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1337
1338         limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
1339         limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config);
1340
1341         if (intel_dp->use_max_params) {
1342                 /*
1343                  * Use the maximum clock and number of lanes the eDP panel
1344                  * advertizes being capable of in case the initial fast
1345                  * optimal params failed us. The panels are generally
1346                  * designed to support only a single clock and lane
1347                  * configuration, and typically on older panels these
1348                  * values correspond to the native resolution of the panel.
1349                  */
1350                 limits.min_lane_count = limits.max_lane_count;
1351                 limits.min_clock = limits.max_clock;
1352         }
1353
1354         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1355
1356         drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
1357                     "max rate %d max bpp %d pixel clock %iKHz\n",
1358                     limits.max_lane_count,
1359                     intel_dp->common_rates[limits.max_clock],
1360                     limits.max_bpp, adjusted_mode->crtc_clock);
1361
1362         if ((adjusted_mode->crtc_clock > i915->max_dotclk_freq ||
1363              adjusted_mode->crtc_hdisplay > 5120) &&
1364             intel_dp_can_bigjoiner(intel_dp))
1365                 pipe_config->bigjoiner = true;
1366
1367         /*
1368          * Optimize for slow and wide for everything, because there are some
1369          * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
1370          */
1371         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
1372
1373         /*
1374          * Pipe joiner needs compression upto display12 due to BW limitation. DG2
1375          * onwards pipe joiner can be enabled without compression.
1376          */
1377         drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
1378         if (ret || intel_dp->force_dsc_en || (DISPLAY_VER(i915) < 13 &&
1379                                               pipe_config->bigjoiner)) {
1380                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
1381                                                   conn_state, &limits);
1382                 if (ret < 0)
1383                         return ret;
1384         }
1385
1386         if (pipe_config->dsc.compression_enable) {
1387                 drm_dbg_kms(&i915->drm,
1388                             "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
1389                             pipe_config->lane_count, pipe_config->port_clock,
1390                             pipe_config->pipe_bpp,
1391                             pipe_config->dsc.compressed_bpp);
1392
1393                 drm_dbg_kms(&i915->drm,
1394                             "DP link rate required %i available %i\n",
1395                             intel_dp_link_required(adjusted_mode->crtc_clock,
1396                                                    pipe_config->dsc.compressed_bpp),
1397                             intel_dp_max_data_rate(pipe_config->port_clock,
1398                                                    pipe_config->lane_count));
1399         } else {
1400                 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
1401                             pipe_config->lane_count, pipe_config->port_clock,
1402                             pipe_config->pipe_bpp);
1403
1404                 drm_dbg_kms(&i915->drm,
1405                             "DP link rate required %i available %i\n",
1406                             intel_dp_link_required(adjusted_mode->crtc_clock,
1407                                                    pipe_config->pipe_bpp),
1408                             intel_dp_max_data_rate(pipe_config->port_clock,
1409                                                    pipe_config->lane_count));
1410         }
1411         return 0;
1412 }
1413
1414 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
1415                                   const struct drm_connector_state *conn_state)
1416 {
1417         const struct intel_digital_connector_state *intel_conn_state =
1418                 to_intel_digital_connector_state(conn_state);
1419         const struct drm_display_mode *adjusted_mode =
1420                 &crtc_state->hw.adjusted_mode;
1421
1422         /*
1423          * Our YCbCr output is always limited range.
1424          * crtc_state->limited_color_range only applies to RGB,
1425          * and it must never be set for YCbCr or we risk setting
1426          * some conflicting bits in PIPECONF which will mess up
1427          * the colors on the monitor.
1428          */
1429         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1430                 return false;
1431
1432         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1433                 /*
1434                  * See:
1435                  * CEA-861-E - 5.1 Default Encoding Parameters
1436                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1437                  */
1438                 return crtc_state->pipe_bpp != 18 &&
1439                         drm_default_rgb_quant_range(adjusted_mode) ==
1440                         HDMI_QUANTIZATION_RANGE_LIMITED;
1441         } else {
1442                 return intel_conn_state->broadcast_rgb ==
1443                         INTEL_BROADCAST_RGB_LIMITED;
1444         }
1445 }
1446
1447 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
1448                                     enum port port)
1449 {
1450         if (IS_G4X(dev_priv))
1451                 return false;
1452         if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
1453                 return false;
1454
1455         return true;
1456 }
1457
1458 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
1459                                              const struct drm_connector_state *conn_state,
1460                                              struct drm_dp_vsc_sdp *vsc)
1461 {
1462         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1463         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1464
1465         /*
1466          * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1467          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
1468          * Colorimetry Format indication.
1469          */
1470         vsc->revision = 0x5;
1471         vsc->length = 0x13;
1472
1473         /* DP 1.4a spec, Table 2-120 */
1474         switch (crtc_state->output_format) {
1475         case INTEL_OUTPUT_FORMAT_YCBCR444:
1476                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
1477                 break;
1478         case INTEL_OUTPUT_FORMAT_YCBCR420:
1479                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
1480                 break;
1481         case INTEL_OUTPUT_FORMAT_RGB:
1482         default:
1483                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
1484         }
1485
1486         switch (conn_state->colorspace) {
1487         case DRM_MODE_COLORIMETRY_BT709_YCC:
1488                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1489                 break;
1490         case DRM_MODE_COLORIMETRY_XVYCC_601:
1491                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
1492                 break;
1493         case DRM_MODE_COLORIMETRY_XVYCC_709:
1494                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
1495                 break;
1496         case DRM_MODE_COLORIMETRY_SYCC_601:
1497                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
1498                 break;
1499         case DRM_MODE_COLORIMETRY_OPYCC_601:
1500                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
1501                 break;
1502         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1503                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
1504                 break;
1505         case DRM_MODE_COLORIMETRY_BT2020_RGB:
1506                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
1507                 break;
1508         case DRM_MODE_COLORIMETRY_BT2020_YCC:
1509                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
1510                 break;
1511         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1512         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1513                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
1514                 break;
1515         default:
1516                 /*
1517                  * RGB->YCBCR color conversion uses the BT.709
1518                  * color space.
1519                  */
1520                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1521                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1522                 else
1523                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
1524                 break;
1525         }
1526
1527         vsc->bpc = crtc_state->pipe_bpp / 3;
1528
1529         /* only RGB pixelformat supports 6 bpc */
1530         drm_WARN_ON(&dev_priv->drm,
1531                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
1532
1533         /* all YCbCr are always limited range */
1534         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
1535         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
1536 }
1537
1538 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
1539                                      struct intel_crtc_state *crtc_state,
1540                                      const struct drm_connector_state *conn_state)
1541 {
1542         struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
1543
1544         /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
1545         if (crtc_state->has_psr)
1546                 return;
1547
1548         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1549                 return;
1550
1551         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1552         vsc->sdp_type = DP_SDP_VSC;
1553         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1554                                          &crtc_state->infoframes.vsc);
1555 }
1556
1557 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
1558                                   const struct intel_crtc_state *crtc_state,
1559                                   const struct drm_connector_state *conn_state,
1560                                   struct drm_dp_vsc_sdp *vsc)
1561 {
1562         vsc->sdp_type = DP_SDP_VSC;
1563
1564         if (intel_dp->psr.psr2_enabled) {
1565                 if (intel_dp->psr.colorimetry_support &&
1566                     intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
1567                         /* [PSR2, +Colorimetry] */
1568                         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1569                                                          vsc);
1570                 } else {
1571                         /*
1572                          * [PSR2, -Colorimetry]
1573                          * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
1574                          * 3D stereo + PSR/PSR2 + Y-coordinate.
1575                          */
1576                         vsc->revision = 0x4;
1577                         vsc->length = 0xe;
1578                 }
1579         } else {
1580                 /*
1581                  * [PSR1]
1582                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1583                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
1584                  * higher).
1585                  */
1586                 vsc->revision = 0x2;
1587                 vsc->length = 0x8;
1588         }
1589 }
1590
1591 static void
1592 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
1593                                             struct intel_crtc_state *crtc_state,
1594                                             const struct drm_connector_state *conn_state)
1595 {
1596         int ret;
1597         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1598         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
1599
1600         if (!conn_state->hdr_output_metadata)
1601                 return;
1602
1603         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
1604
1605         if (ret) {
1606                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
1607                 return;
1608         }
1609
1610         crtc_state->infoframes.enable |=
1611                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
1612 }
1613
1614 static void
1615 intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
1616                              struct intel_crtc_state *pipe_config,
1617                              int output_bpp, bool constant_n)
1618 {
1619         struct intel_connector *intel_connector = intel_dp->attached_connector;
1620         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1621         int pixel_clock;
1622
1623         if (pipe_config->vrr.enable)
1624                 return;
1625
1626         /*
1627          * DRRS and PSR can't be enable together, so giving preference to PSR
1628          * as it allows more power-savings by complete shutting down display,
1629          * so to guarantee this, intel_dp_drrs_compute_config() must be called
1630          * after intel_psr_compute_config().
1631          */
1632         if (pipe_config->has_psr)
1633                 return;
1634
1635         if (!intel_connector->panel.downclock_mode ||
1636             dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
1637                 return;
1638
1639         pipe_config->has_drrs = true;
1640
1641         pixel_clock = intel_connector->panel.downclock_mode->clock;
1642         if (pipe_config->splitter.enable)
1643                 pixel_clock /= pipe_config->splitter.link_count;
1644
1645         intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
1646                                pipe_config->port_clock, &pipe_config->dp_m2_n2,
1647                                constant_n, pipe_config->fec_enable);
1648
1649         /* FIXME: abstract this better */
1650         if (pipe_config->splitter.enable)
1651                 pipe_config->dp_m2_n2.gmch_m *= pipe_config->splitter.link_count;
1652 }
1653
1654 int
1655 intel_dp_compute_config(struct intel_encoder *encoder,
1656                         struct intel_crtc_state *pipe_config,
1657                         struct drm_connector_state *conn_state)
1658 {
1659         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1660         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1661         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1662         enum port port = encoder->port;
1663         struct intel_connector *intel_connector = intel_dp->attached_connector;
1664         struct intel_digital_connector_state *intel_conn_state =
1665                 to_intel_digital_connector_state(conn_state);
1666         bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
1667         int ret = 0, output_bpp;
1668
1669         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1670                 pipe_config->has_pch_encoder = true;
1671
1672         pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
1673                                                             adjusted_mode);
1674
1675         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
1676                 ret = intel_pch_panel_fitting(pipe_config, conn_state);
1677                 if (ret)
1678                         return ret;
1679         }
1680
1681         if (!intel_dp_port_has_audio(dev_priv, port))
1682                 pipe_config->has_audio = false;
1683         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1684                 pipe_config->has_audio = intel_dp->has_audio;
1685         else
1686                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1687
1688         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1689                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1690                                        adjusted_mode);
1691
1692                 if (HAS_GMCH(dev_priv))
1693                         ret = intel_gmch_panel_fitting(pipe_config, conn_state);
1694                 else
1695                         ret = intel_pch_panel_fitting(pipe_config, conn_state);
1696                 if (ret)
1697                         return ret;
1698         }
1699
1700         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1701                 return -EINVAL;
1702
1703         if (HAS_GMCH(dev_priv) &&
1704             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1705                 return -EINVAL;
1706
1707         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1708                 return -EINVAL;
1709
1710         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
1711                 return -EINVAL;
1712
1713         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
1714         if (ret < 0)
1715                 return ret;
1716
1717         pipe_config->limited_color_range =
1718                 intel_dp_limited_color_range(pipe_config, conn_state);
1719
1720         if (pipe_config->dsc.compression_enable)
1721                 output_bpp = pipe_config->dsc.compressed_bpp;
1722         else
1723                 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
1724                                                  pipe_config->pipe_bpp);
1725
1726         if (intel_dp->mso_link_count) {
1727                 int n = intel_dp->mso_link_count;
1728                 int overlap = intel_dp->mso_pixel_overlap;
1729
1730                 pipe_config->splitter.enable = true;
1731                 pipe_config->splitter.link_count = n;
1732                 pipe_config->splitter.pixel_overlap = overlap;
1733
1734                 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
1735                             n, overlap);
1736
1737                 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
1738                 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
1739                 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
1740                 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
1741                 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
1742                 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
1743                 adjusted_mode->crtc_clock /= n;
1744         }
1745
1746         intel_link_compute_m_n(output_bpp,
1747                                pipe_config->lane_count,
1748                                adjusted_mode->crtc_clock,
1749                                pipe_config->port_clock,
1750                                &pipe_config->dp_m_n,
1751                                constant_n, pipe_config->fec_enable);
1752
1753         /* FIXME: abstract this better */
1754         if (pipe_config->splitter.enable)
1755                 pipe_config->dp_m_n.gmch_m *= pipe_config->splitter.link_count;
1756
1757         if (!HAS_DDI(dev_priv))
1758                 g4x_dp_set_clock(encoder, pipe_config);
1759
1760         intel_vrr_compute_config(pipe_config, conn_state);
1761         intel_psr_compute_config(intel_dp, pipe_config);
1762         intel_dp_drrs_compute_config(intel_dp, pipe_config, output_bpp,
1763                                      constant_n);
1764         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
1765         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
1766
1767         return 0;
1768 }
1769
1770 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1771                               int link_rate, int lane_count)
1772 {
1773         intel_dp->link_trained = false;
1774         intel_dp->link_rate = link_rate;
1775         intel_dp->lane_count = lane_count;
1776 }
1777
1778 /* Enable backlight PWM and backlight PP control. */
1779 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1780                             const struct drm_connector_state *conn_state)
1781 {
1782         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
1783         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1784
1785         if (!intel_dp_is_edp(intel_dp))
1786                 return;
1787
1788         drm_dbg_kms(&i915->drm, "\n");
1789
1790         intel_panel_enable_backlight(crtc_state, conn_state);
1791         intel_pps_backlight_on(intel_dp);
1792 }
1793
1794 /* Disable backlight PP control and backlight PWM. */
1795 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
1796 {
1797         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
1798         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1799
1800         if (!intel_dp_is_edp(intel_dp))
1801                 return;
1802
1803         drm_dbg_kms(&i915->drm, "\n");
1804
1805         intel_pps_backlight_off(intel_dp);
1806         intel_panel_disable_backlight(old_conn_state);
1807 }
1808
1809 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
1810 {
1811         /*
1812          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
1813          * be capable of signalling downstream hpd with a long pulse.
1814          * Whether or not that means D3 is safe to use is not clear,
1815          * but let's assume so until proven otherwise.
1816          *
1817          * FIXME should really check all downstream ports...
1818          */
1819         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
1820                 drm_dp_is_branch(intel_dp->dpcd) &&
1821                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
1822 }
1823
1824 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
1825                                            const struct intel_crtc_state *crtc_state,
1826                                            bool enable)
1827 {
1828         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1829         int ret;
1830
1831         if (!crtc_state->dsc.compression_enable)
1832                 return;
1833
1834         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
1835                                  enable ? DP_DECOMPRESSION_EN : 0);
1836         if (ret < 0)
1837                 drm_dbg_kms(&i915->drm,
1838                             "Failed to %s sink decompression state\n",
1839                             enabledisable(enable));
1840 }
1841
1842 static void
1843 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
1844 {
1845         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1846         u8 oui[] = { 0x00, 0xaa, 0x01 };
1847         u8 buf[3] = { 0 };
1848
1849         /*
1850          * During driver init, we want to be careful and avoid changing the source OUI if it's
1851          * already set to what we want, so as to avoid clearing any state by accident
1852          */
1853         if (careful) {
1854                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
1855                         drm_err(&i915->drm, "Failed to read source OUI\n");
1856
1857                 if (memcmp(oui, buf, sizeof(oui)) == 0)
1858                         return;
1859         }
1860
1861         if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
1862                 drm_err(&i915->drm, "Failed to write source OUI\n");
1863 }
1864
1865 /* If the device supports it, try to set the power state appropriately */
1866 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
1867 {
1868         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1869         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1870         int ret, i;
1871
1872         /* Should have a valid DPCD by this point */
1873         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1874                 return;
1875
1876         if (mode != DP_SET_POWER_D0) {
1877                 if (downstream_hpd_needs_d0(intel_dp))
1878                         return;
1879
1880                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
1881         } else {
1882                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
1883
1884                 lspcon_resume(dp_to_dig_port(intel_dp));
1885
1886                 /* Write the source OUI as early as possible */
1887                 if (intel_dp_is_edp(intel_dp))
1888                         intel_edp_init_source_oui(intel_dp, false);
1889
1890                 /*
1891                  * When turning on, we need to retry for 1ms to give the sink
1892                  * time to wake up.
1893                  */
1894                 for (i = 0; i < 3; i++) {
1895                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
1896                         if (ret == 1)
1897                                 break;
1898                         msleep(1);
1899                 }
1900
1901                 if (ret == 1 && lspcon->active)
1902                         lspcon_wait_pcon_mode(lspcon);
1903         }
1904
1905         if (ret != 1)
1906                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
1907                             encoder->base.base.id, encoder->base.name,
1908                             mode == DP_SET_POWER_D0 ? "D0" : "D3");
1909 }
1910
1911 static bool
1912 intel_dp_get_dpcd(struct intel_dp *intel_dp);
1913
1914 /**
1915  * intel_dp_sync_state - sync the encoder state during init/resume
1916  * @encoder: intel encoder to sync
1917  * @crtc_state: state for the CRTC connected to the encoder
1918  *
1919  * Sync any state stored in the encoder wrt. HW state during driver init
1920  * and system resume.
1921  */
1922 void intel_dp_sync_state(struct intel_encoder *encoder,
1923                          const struct intel_crtc_state *crtc_state)
1924 {
1925         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1926
1927         /*
1928          * Don't clobber DPCD if it's been already read out during output
1929          * setup (eDP) or detect.
1930          */
1931         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
1932                 intel_dp_get_dpcd(intel_dp);
1933
1934         intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
1935         intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
1936 }
1937
1938 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
1939                                     struct intel_crtc_state *crtc_state)
1940 {
1941         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1942         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1943
1944         /*
1945          * If BIOS has set an unsupported or non-standard link rate for some
1946          * reason force an encoder recompute and full modeset.
1947          */
1948         if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
1949                                 crtc_state->port_clock) < 0) {
1950                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
1951                 crtc_state->uapi.connectors_changed = true;
1952                 return false;
1953         }
1954
1955         /*
1956          * FIXME hack to force full modeset when DSC is being used.
1957          *
1958          * As long as we do not have full state readout and config comparison
1959          * of crtc_state->dsc, we have no way to ensure reliable fastset.
1960          * Remove once we have readout for DSC.
1961          */
1962         if (crtc_state->dsc.compression_enable) {
1963                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
1964                 crtc_state->uapi.mode_changed = true;
1965                 return false;
1966         }
1967
1968         if (CAN_PSR(intel_dp)) {
1969                 drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
1970                 crtc_state->uapi.mode_changed = true;
1971                 return false;
1972         }
1973
1974         return true;
1975 }
1976
1977 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
1978 {
1979         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1980
1981         /* Clear the cached register set to avoid using stale values */
1982
1983         memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
1984
1985         if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
1986                              intel_dp->pcon_dsc_dpcd,
1987                              sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
1988                 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
1989                         DP_PCON_DSC_ENCODER);
1990
1991         drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
1992                     (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
1993 }
1994
1995 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
1996 {
1997         int bw_gbps[] = {9, 18, 24, 32, 40, 48};
1998         int i;
1999
2000         for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
2001                 if (frl_bw_mask & (1 << i))
2002                         return bw_gbps[i];
2003         }
2004         return 0;
2005 }
2006
2007 static int intel_dp_pcon_set_frl_mask(int max_frl)
2008 {
2009         switch (max_frl) {
2010         case 48:
2011                 return DP_PCON_FRL_BW_MASK_48GBPS;
2012         case 40:
2013                 return DP_PCON_FRL_BW_MASK_40GBPS;
2014         case 32:
2015                 return DP_PCON_FRL_BW_MASK_32GBPS;
2016         case 24:
2017                 return DP_PCON_FRL_BW_MASK_24GBPS;
2018         case 18:
2019                 return DP_PCON_FRL_BW_MASK_18GBPS;
2020         case 9:
2021                 return DP_PCON_FRL_BW_MASK_9GBPS;
2022         }
2023
2024         return 0;
2025 }
2026
2027 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
2028 {
2029         struct intel_connector *intel_connector = intel_dp->attached_connector;
2030         struct drm_connector *connector = &intel_connector->base;
2031         int max_frl_rate;
2032         int max_lanes, rate_per_lane;
2033         int max_dsc_lanes, dsc_rate_per_lane;
2034
2035         max_lanes = connector->display_info.hdmi.max_lanes;
2036         rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
2037         max_frl_rate = max_lanes * rate_per_lane;
2038
2039         if (connector->display_info.hdmi.dsc_cap.v_1p2) {
2040                 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
2041                 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
2042                 if (max_dsc_lanes && dsc_rate_per_lane)
2043                         max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
2044         }
2045
2046         return max_frl_rate;
2047 }
2048
2049 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
2050 {
2051 #define TIMEOUT_FRL_READY_MS 500
2052 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
2053
2054         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2055         int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
2056         u8 max_frl_bw_mask = 0, frl_trained_mask;
2057         bool is_active;
2058
2059         ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
2060         if (ret < 0)
2061                 return ret;
2062
2063         max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
2064         drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
2065
2066         max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
2067         drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
2068
2069         max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
2070
2071         if (max_frl_bw <= 0)
2072                 return -EINVAL;
2073
2074         ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
2075         if (ret < 0)
2076                 return ret;
2077         /* Wait for PCON to be FRL Ready */
2078         wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
2079
2080         if (!is_active)
2081                 return -ETIMEDOUT;
2082
2083         max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
2084         ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
2085                                           DP_PCON_ENABLE_SEQUENTIAL_LINK);
2086         if (ret < 0)
2087                 return ret;
2088         ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
2089                                           DP_PCON_FRL_LINK_TRAIN_NORMAL);
2090         if (ret < 0)
2091                 return ret;
2092         ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
2093         if (ret < 0)
2094                 return ret;
2095         /*
2096          * Wait for FRL to be completed
2097          * Check if the HDMI Link is up and active.
2098          */
2099         wait_for(is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux) == true, TIMEOUT_HDMI_LINK_ACTIVE_MS);
2100
2101         if (!is_active)
2102                 return -ETIMEDOUT;
2103
2104         /* Verify HDMI Link configuration shows FRL Mode */
2105         if (drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, &frl_trained_mask) !=
2106             DP_PCON_HDMI_MODE_FRL) {
2107                 drm_dbg(&i915->drm, "HDMI couldn't be trained in FRL Mode\n");
2108                 return -EINVAL;
2109         }
2110         drm_dbg(&i915->drm, "MAX_FRL_MASK = %u, FRL_TRAINED_MASK = %u\n", max_frl_bw_mask, frl_trained_mask);
2111
2112         intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
2113         intel_dp->frl.is_trained = true;
2114         drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
2115
2116         return 0;
2117 }
2118
2119 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
2120 {
2121         if (drm_dp_is_branch(intel_dp->dpcd) &&
2122             intel_dp->has_hdmi_sink &&
2123             intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
2124                 return true;
2125
2126         return false;
2127 }
2128
2129 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
2130 {
2131         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2132
2133         /*
2134          * Always go for FRL training if:
2135          * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
2136          * -sink is HDMI2.1
2137          */
2138         if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
2139             !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
2140             intel_dp->frl.is_trained)
2141                 return;
2142
2143         if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
2144                 int ret, mode;
2145
2146                 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
2147                 ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
2148                 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
2149
2150                 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
2151                         drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
2152         } else {
2153                 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
2154         }
2155 }
2156
2157 static int
2158 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
2159 {
2160         int vactive = crtc_state->hw.adjusted_mode.vdisplay;
2161
2162         return intel_hdmi_dsc_get_slice_height(vactive);
2163 }
2164
2165 static int
2166 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
2167                              const struct intel_crtc_state *crtc_state)
2168 {
2169         struct intel_connector *intel_connector = intel_dp->attached_connector;
2170         struct drm_connector *connector = &intel_connector->base;
2171         int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
2172         int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
2173         int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
2174         int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
2175
2176         return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
2177                                              pcon_max_slice_width,
2178                                              hdmi_max_slices, hdmi_throughput);
2179 }
2180
2181 static int
2182 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
2183                           const struct intel_crtc_state *crtc_state,
2184                           int num_slices, int slice_width)
2185 {
2186         struct intel_connector *intel_connector = intel_dp->attached_connector;
2187         struct drm_connector *connector = &intel_connector->base;
2188         int output_format = crtc_state->output_format;
2189         bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
2190         int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
2191         int hdmi_max_chunk_bytes =
2192                 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
2193
2194         return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
2195                                       num_slices, output_format, hdmi_all_bpp,
2196                                       hdmi_max_chunk_bytes);
2197 }
2198
2199 void
2200 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
2201                             const struct intel_crtc_state *crtc_state)
2202 {
2203         u8 pps_param[6];
2204         int slice_height;
2205         int slice_width;
2206         int num_slices;
2207         int bits_per_pixel;
2208         int ret;
2209         struct intel_connector *intel_connector = intel_dp->attached_connector;
2210         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2211         struct drm_connector *connector;
2212         bool hdmi_is_dsc_1_2;
2213
2214         if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
2215                 return;
2216
2217         if (!intel_connector)
2218                 return;
2219         connector = &intel_connector->base;
2220         hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
2221
2222         if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
2223             !hdmi_is_dsc_1_2)
2224                 return;
2225
2226         slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
2227         if (!slice_height)
2228                 return;
2229
2230         num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
2231         if (!num_slices)
2232                 return;
2233
2234         slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
2235                                    num_slices);
2236
2237         bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
2238                                                    num_slices, slice_width);
2239         if (!bits_per_pixel)
2240                 return;
2241
2242         pps_param[0] = slice_height & 0xFF;
2243         pps_param[1] = slice_height >> 8;
2244         pps_param[2] = slice_width & 0xFF;
2245         pps_param[3] = slice_width >> 8;
2246         pps_param[4] = bits_per_pixel & 0xFF;
2247         pps_param[5] = (bits_per_pixel >> 8) & 0x3;
2248
2249         ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
2250         if (ret < 0)
2251                 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
2252 }
2253
2254 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
2255                                            const struct intel_crtc_state *crtc_state)
2256 {
2257         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2258         u8 tmp;
2259
2260         if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
2261                 return;
2262
2263         if (!drm_dp_is_branch(intel_dp->dpcd))
2264                 return;
2265
2266         tmp = intel_dp->has_hdmi_sink ?
2267                 DP_HDMI_DVI_OUTPUT_CONFIG : 0;
2268
2269         if (drm_dp_dpcd_writeb(&intel_dp->aux,
2270                                DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
2271                 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
2272                             enabledisable(intel_dp->has_hdmi_sink));
2273
2274         tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
2275                 intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
2276
2277         if (drm_dp_dpcd_writeb(&intel_dp->aux,
2278                                DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
2279                 drm_dbg_kms(&i915->drm,
2280                             "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
2281                             enabledisable(intel_dp->dfp.ycbcr_444_to_420));
2282
2283         tmp = 0;
2284         if (intel_dp->dfp.rgb_to_ycbcr) {
2285                 bool bt2020, bt709;
2286
2287                 /*
2288                  * FIXME: Currently if userspace selects BT2020 or BT709, but PCON supports only
2289                  * RGB->YCbCr for BT601 colorspace, we go ahead with BT601, as default.
2290                  *
2291                  */
2292                 tmp = DP_CONVERSION_BT601_RGB_YCBCR_ENABLE;
2293
2294                 bt2020 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
2295                                                                    intel_dp->downstream_ports,
2296                                                                    DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
2297                 bt709 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
2298                                                                   intel_dp->downstream_ports,
2299                                                                   DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
2300                 switch (crtc_state->infoframes.vsc.colorimetry) {
2301                 case DP_COLORIMETRY_BT2020_RGB:
2302                 case DP_COLORIMETRY_BT2020_YCC:
2303                         if (bt2020)
2304                                 tmp = DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE;
2305                         break;
2306                 case DP_COLORIMETRY_BT709_YCC:
2307                 case DP_COLORIMETRY_XVYCC_709:
2308                         if (bt709)
2309                                 tmp = DP_CONVERSION_BT709_RGB_YCBCR_ENABLE;
2310                         break;
2311                 default:
2312                         break;
2313                 }
2314         }
2315
2316         if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
2317                 drm_dbg_kms(&i915->drm,
2318                            "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
2319                            enabledisable(tmp));
2320 }
2321
2322
2323 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
2324 {
2325         u8 dprx = 0;
2326
2327         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
2328                               &dprx) != 1)
2329                 return false;
2330         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
2331 }
2332
2333 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
2334 {
2335         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2336
2337         /*
2338          * Clear the cached register set to avoid using stale values
2339          * for the sinks that do not support DSC.
2340          */
2341         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
2342
2343         /* Clear fec_capable to avoid using stale values */
2344         intel_dp->fec_capable = 0;
2345
2346         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
2347         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
2348             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2349                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
2350                                      intel_dp->dsc_dpcd,
2351                                      sizeof(intel_dp->dsc_dpcd)) < 0)
2352                         drm_err(&i915->drm,
2353                                 "Failed to read DPCD register 0x%x\n",
2354                                 DP_DSC_SUPPORT);
2355
2356                 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
2357                             (int)sizeof(intel_dp->dsc_dpcd),
2358                             intel_dp->dsc_dpcd);
2359
2360                 /* FEC is supported only on DP 1.4 */
2361                 if (!intel_dp_is_edp(intel_dp) &&
2362                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
2363                                       &intel_dp->fec_capable) < 0)
2364                         drm_err(&i915->drm,
2365                                 "Failed to read FEC DPCD register\n");
2366
2367                 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
2368                             intel_dp->fec_capable);
2369         }
2370 }
2371
2372 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
2373                                      struct drm_display_mode *mode)
2374 {
2375         struct intel_dp *intel_dp = intel_attached_dp(connector);
2376         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2377         int n = intel_dp->mso_link_count;
2378         int overlap = intel_dp->mso_pixel_overlap;
2379
2380         if (!mode || !n)
2381                 return;
2382
2383         mode->hdisplay = (mode->hdisplay - overlap) * n;
2384         mode->hsync_start = (mode->hsync_start - overlap) * n;
2385         mode->hsync_end = (mode->hsync_end - overlap) * n;
2386         mode->htotal = (mode->htotal - overlap) * n;
2387         mode->clock *= n;
2388
2389         drm_mode_set_name(mode);
2390
2391         drm_dbg_kms(&i915->drm,
2392                     "[CONNECTOR:%d:%s] using generated MSO mode: ",
2393                     connector->base.base.id, connector->base.name);
2394         drm_mode_debug_printmodeline(mode);
2395 }
2396
2397 static void intel_edp_mso_init(struct intel_dp *intel_dp)
2398 {
2399         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2400         u8 mso;
2401
2402         if (intel_dp->edp_dpcd[0] < DP_EDP_14)
2403                 return;
2404
2405         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
2406                 drm_err(&i915->drm, "Failed to read MSO cap\n");
2407                 return;
2408         }
2409
2410         /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
2411         mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
2412         if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
2413                 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
2414                 mso = 0;
2415         }
2416
2417         if (mso) {
2418                 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration\n",
2419                             mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso);
2420                 if (!HAS_MSO(i915)) {
2421                         drm_err(&i915->drm, "No source MSO support, disabling\n");
2422                         mso = 0;
2423                 }
2424         }
2425
2426         intel_dp->mso_link_count = mso;
2427         intel_dp->mso_pixel_overlap = 0; /* FIXME: read from DisplayID v2.0 */
2428 }
2429
2430 static bool
2431 intel_edp_init_dpcd(struct intel_dp *intel_dp)
2432 {
2433         struct drm_i915_private *dev_priv =
2434                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
2435
2436         /* this function is meant to be called only once */
2437         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
2438
2439         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
2440                 return false;
2441
2442         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2443                          drm_dp_is_branch(intel_dp->dpcd));
2444
2445         /*
2446          * Read the eDP display control registers.
2447          *
2448          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
2449          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
2450          * set, but require eDP 1.4+ detection (e.g. for supported link rates
2451          * method). The display control registers should read zero if they're
2452          * not supported anyway.
2453          */
2454         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
2455                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
2456                              sizeof(intel_dp->edp_dpcd))
2457                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
2458                             (int)sizeof(intel_dp->edp_dpcd),
2459                             intel_dp->edp_dpcd);
2460
2461         /*
2462          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
2463          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
2464          */
2465         intel_psr_init_dpcd(intel_dp);
2466
2467         /* Read the eDP 1.4+ supported link rates. */
2468         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2469                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
2470                 int i;
2471
2472                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
2473                                 sink_rates, sizeof(sink_rates));
2474
2475                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
2476                         int val = le16_to_cpu(sink_rates[i]);
2477
2478                         if (val == 0)
2479                                 break;
2480
2481                         /* Value read multiplied by 200kHz gives the per-lane
2482                          * link rate in kHz. The source rates are, however,
2483                          * stored in terms of LS_Clk kHz. The full conversion
2484                          * back to symbols is
2485                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
2486                          */
2487                         intel_dp->sink_rates[i] = (val * 200) / 10;
2488                 }
2489                 intel_dp->num_sink_rates = i;
2490         }
2491
2492         /*
2493          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
2494          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
2495          */
2496         if (intel_dp->num_sink_rates)
2497                 intel_dp->use_rate_select = true;
2498         else
2499                 intel_dp_set_sink_rates(intel_dp);
2500
2501         intel_dp_set_common_rates(intel_dp);
2502
2503         /* Read the eDP DSC DPCD registers */
2504         if (DISPLAY_VER(dev_priv) >= 10)
2505                 intel_dp_get_dsc_sink_cap(intel_dp);
2506
2507         /*
2508          * If needed, program our source OUI so we can make various Intel-specific AUX services
2509          * available (such as HDR backlight controls)
2510          */
2511         intel_edp_init_source_oui(intel_dp, true);
2512
2513         intel_edp_mso_init(intel_dp);
2514
2515         return true;
2516 }
2517
2518 static bool
2519 intel_dp_has_sink_count(struct intel_dp *intel_dp)
2520 {
2521         if (!intel_dp->attached_connector)
2522                 return false;
2523
2524         return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
2525                                           intel_dp->dpcd,
2526                                           &intel_dp->desc);
2527 }
2528
2529 static bool
2530 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2531 {
2532         int ret;
2533
2534         if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
2535                 return false;
2536
2537         /*
2538          * Don't clobber cached eDP rates. Also skip re-reading
2539          * the OUI/ID since we know it won't change.
2540          */
2541         if (!intel_dp_is_edp(intel_dp)) {
2542                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2543                                  drm_dp_is_branch(intel_dp->dpcd));
2544
2545                 intel_dp_set_sink_rates(intel_dp);
2546                 intel_dp_set_common_rates(intel_dp);
2547         }
2548
2549         if (intel_dp_has_sink_count(intel_dp)) {
2550                 ret = drm_dp_read_sink_count(&intel_dp->aux);
2551                 if (ret < 0)
2552                         return false;
2553
2554                 /*
2555                  * Sink count can change between short pulse hpd hence
2556                  * a member variable in intel_dp will track any changes
2557                  * between short pulse interrupts.
2558                  */
2559                 intel_dp->sink_count = ret;
2560
2561                 /*
2562                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
2563                  * a dongle is present but no display. Unless we require to know
2564                  * if a dongle is present or not, we don't need to update
2565                  * downstream port information. So, an early return here saves
2566                  * time from performing other operations which are not required.
2567                  */
2568                 if (!intel_dp->sink_count)
2569                         return false;
2570         }
2571
2572         return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
2573                                            intel_dp->downstream_ports) == 0;
2574 }
2575
2576 static bool
2577 intel_dp_can_mst(struct intel_dp *intel_dp)
2578 {
2579         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2580
2581         return i915->params.enable_dp_mst &&
2582                 intel_dp->can_mst &&
2583                 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2584 }
2585
2586 static void
2587 intel_dp_configure_mst(struct intel_dp *intel_dp)
2588 {
2589         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2590         struct intel_encoder *encoder =
2591                 &dp_to_dig_port(intel_dp)->base;
2592         bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2593
2594         drm_dbg_kms(&i915->drm,
2595                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
2596                     encoder->base.base.id, encoder->base.name,
2597                     yesno(intel_dp->can_mst), yesno(sink_can_mst),
2598                     yesno(i915->params.enable_dp_mst));
2599
2600         if (!intel_dp->can_mst)
2601                 return;
2602
2603         intel_dp->is_mst = sink_can_mst &&
2604                 i915->params.enable_dp_mst;
2605
2606         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
2607                                         intel_dp->is_mst);
2608 }
2609
2610 static bool
2611 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2612 {
2613         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
2614                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
2615                 DP_DPRX_ESI_LEN;
2616 }
2617
2618 bool
2619 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
2620                        const struct drm_connector_state *conn_state)
2621 {
2622         /*
2623          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
2624          * of Color Encoding Format and Content Color Gamut], in order to
2625          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
2626          */
2627         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2628                 return true;
2629
2630         switch (conn_state->colorspace) {
2631         case DRM_MODE_COLORIMETRY_SYCC_601:
2632         case DRM_MODE_COLORIMETRY_OPYCC_601:
2633         case DRM_MODE_COLORIMETRY_BT2020_YCC:
2634         case DRM_MODE_COLORIMETRY_BT2020_RGB:
2635         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2636                 return true;
2637         default:
2638                 break;
2639         }
2640
2641         return false;
2642 }
2643
2644 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
2645                                      struct dp_sdp *sdp, size_t size)
2646 {
2647         size_t length = sizeof(struct dp_sdp);
2648
2649         if (size < length)
2650                 return -ENOSPC;
2651
2652         memset(sdp, 0, size);
2653
2654         /*
2655          * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
2656          * VSC SDP Header Bytes
2657          */
2658         sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
2659         sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
2660         sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
2661         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
2662
2663         /*
2664          * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
2665          * per DP 1.4a spec.
2666          */
2667         if (vsc->revision != 0x5)
2668                 goto out;
2669
2670         /* VSC SDP Payload for DB16 through DB18 */
2671         /* Pixel Encoding and Colorimetry Formats  */
2672         sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
2673         sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
2674
2675         switch (vsc->bpc) {
2676         case 6:
2677                 /* 6bpc: 0x0 */
2678                 break;
2679         case 8:
2680                 sdp->db[17] = 0x1; /* DB17[3:0] */
2681                 break;
2682         case 10:
2683                 sdp->db[17] = 0x2;
2684                 break;
2685         case 12:
2686                 sdp->db[17] = 0x3;
2687                 break;
2688         case 16:
2689                 sdp->db[17] = 0x4;
2690                 break;
2691         default:
2692                 MISSING_CASE(vsc->bpc);
2693                 break;
2694         }
2695         /* Dynamic Range and Component Bit Depth */
2696         if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
2697                 sdp->db[17] |= 0x80;  /* DB17[7] */
2698
2699         /* Content Type */
2700         sdp->db[18] = vsc->content_type & 0x7;
2701
2702 out:
2703         return length;
2704 }
2705
2706 static ssize_t
2707 intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
2708                                          struct dp_sdp *sdp,
2709                                          size_t size)
2710 {
2711         size_t length = sizeof(struct dp_sdp);
2712         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
2713         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
2714         ssize_t len;
2715
2716         if (size < length)
2717                 return -ENOSPC;
2718
2719         memset(sdp, 0, size);
2720
2721         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
2722         if (len < 0) {
2723                 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
2724                 return -ENOSPC;
2725         }
2726
2727         if (len != infoframe_size) {
2728                 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
2729                 return -ENOSPC;
2730         }
2731
2732         /*
2733          * Set up the infoframe sdp packet for HDR static metadata.
2734          * Prepare VSC Header for SU as per DP 1.4a spec,
2735          * Table 2-100 and Table 2-101
2736          */
2737
2738         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
2739         sdp->sdp_header.HB0 = 0;
2740         /*
2741          * Packet Type 80h + Non-audio INFOFRAME Type value
2742          * HDMI_INFOFRAME_TYPE_DRM: 0x87
2743          * - 80h + Non-audio INFOFRAME Type value
2744          * - InfoFrame Type: 0x07
2745          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
2746          */
2747         sdp->sdp_header.HB1 = drm_infoframe->type;
2748         /*
2749          * Least Significant Eight Bits of (Data Byte Count – 1)
2750          * infoframe_size - 1
2751          */
2752         sdp->sdp_header.HB2 = 0x1D;
2753         /* INFOFRAME SDP Version Number */
2754         sdp->sdp_header.HB3 = (0x13 << 2);
2755         /* CTA Header Byte 2 (INFOFRAME Version Number) */
2756         sdp->db[0] = drm_infoframe->version;
2757         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
2758         sdp->db[1] = drm_infoframe->length;
2759         /*
2760          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
2761          * HDMI_INFOFRAME_HEADER_SIZE
2762          */
2763         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
2764         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
2765                HDMI_DRM_INFOFRAME_SIZE);
2766
2767         /*
2768          * Size of DP infoframe sdp packet for HDR static metadata consists of
2769          * - DP SDP Header(struct dp_sdp_header): 4 bytes
2770          * - Two Data Blocks: 2 bytes
2771          *    CTA Header Byte2 (INFOFRAME Version Number)
2772          *    CTA Header Byte3 (Length of INFOFRAME)
2773          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
2774          *
2775          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
2776          * infoframe size. But GEN11+ has larger than that size, write_infoframe
2777          * will pad rest of the size.
2778          */
2779         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
2780 }
2781
2782 static void intel_write_dp_sdp(struct intel_encoder *encoder,
2783                                const struct intel_crtc_state *crtc_state,
2784                                unsigned int type)
2785 {
2786         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2787         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2788         struct dp_sdp sdp = {};
2789         ssize_t len;
2790
2791         if ((crtc_state->infoframes.enable &
2792              intel_hdmi_infoframe_enable(type)) == 0)
2793                 return;
2794
2795         switch (type) {
2796         case DP_SDP_VSC:
2797                 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
2798                                             sizeof(sdp));
2799                 break;
2800         case HDMI_PACKET_TYPE_GAMUT_METADATA:
2801                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
2802                                                                &sdp, sizeof(sdp));
2803                 break;
2804         default:
2805                 MISSING_CASE(type);
2806                 return;
2807         }
2808
2809         if (drm_WARN_ON(&dev_priv->drm, len < 0))
2810                 return;
2811
2812         dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
2813 }
2814
2815 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
2816                             const struct intel_crtc_state *crtc_state,
2817                             struct drm_dp_vsc_sdp *vsc)
2818 {
2819         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2820         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2821         struct dp_sdp sdp = {};
2822         ssize_t len;
2823
2824         len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
2825
2826         if (drm_WARN_ON(&dev_priv->drm, len < 0))
2827                 return;
2828
2829         dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
2830                                         &sdp, len);
2831 }
2832
2833 void intel_dp_set_infoframes(struct intel_encoder *encoder,
2834                              bool enable,
2835                              const struct intel_crtc_state *crtc_state,
2836                              const struct drm_connector_state *conn_state)
2837 {
2838         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2839         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
2840         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
2841                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
2842                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
2843         u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
2844
2845         /* TODO: Add DSC case (DIP_ENABLE_PPS) */
2846         /* When PSR is enabled, this routine doesn't disable VSC DIP */
2847         if (!crtc_state->has_psr)
2848                 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
2849
2850         intel_de_write(dev_priv, reg, val);
2851         intel_de_posting_read(dev_priv, reg);
2852
2853         if (!enable)
2854                 return;
2855
2856         /* When PSR is enabled, VSC SDP is handled by PSR routine */
2857         if (!crtc_state->has_psr)
2858                 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
2859
2860         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
2861 }
2862
2863 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
2864                                    const void *buffer, size_t size)
2865 {
2866         const struct dp_sdp *sdp = buffer;
2867
2868         if (size < sizeof(struct dp_sdp))
2869                 return -EINVAL;
2870
2871         memset(vsc, 0, sizeof(*vsc));
2872
2873         if (sdp->sdp_header.HB0 != 0)
2874                 return -EINVAL;
2875
2876         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
2877                 return -EINVAL;
2878
2879         vsc->sdp_type = sdp->sdp_header.HB1;
2880         vsc->revision = sdp->sdp_header.HB2;
2881         vsc->length = sdp->sdp_header.HB3;
2882
2883         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
2884             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
2885                 /*
2886                  * - HB2 = 0x2, HB3 = 0x8
2887                  *   VSC SDP supporting 3D stereo + PSR
2888                  * - HB2 = 0x4, HB3 = 0xe
2889                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
2890                  *   first scan line of the SU region (applies to eDP v1.4b
2891                  *   and higher).
2892                  */
2893                 return 0;
2894         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
2895                 /*
2896                  * - HB2 = 0x5, HB3 = 0x13
2897                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
2898                  *   Format.
2899                  */
2900                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
2901                 vsc->colorimetry = sdp->db[16] & 0xf;
2902                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
2903
2904                 switch (sdp->db[17] & 0x7) {
2905                 case 0x0:
2906                         vsc->bpc = 6;
2907                         break;
2908                 case 0x1:
2909                         vsc->bpc = 8;
2910                         break;
2911                 case 0x2:
2912                         vsc->bpc = 10;
2913                         break;
2914                 case 0x3:
2915                         vsc->bpc = 12;
2916                         break;
2917                 case 0x4:
2918                         vsc->bpc = 16;
2919                         break;
2920                 default:
2921                         MISSING_CASE(sdp->db[17] & 0x7);
2922                         return -EINVAL;
2923                 }
2924
2925                 vsc->content_type = sdp->db[18] & 0x7;
2926         } else {
2927                 return -EINVAL;
2928         }
2929
2930         return 0;
2931 }
2932
2933 static int
2934 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
2935                                            const void *buffer, size_t size)
2936 {
2937         int ret;
2938
2939         const struct dp_sdp *sdp = buffer;
2940
2941         if (size < sizeof(struct dp_sdp))
2942                 return -EINVAL;
2943
2944         if (sdp->sdp_header.HB0 != 0)
2945                 return -EINVAL;
2946
2947         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
2948                 return -EINVAL;
2949
2950         /*
2951          * Least Significant Eight Bits of (Data Byte Count – 1)
2952          * 1Dh (i.e., Data Byte Count = 30 bytes).
2953          */
2954         if (sdp->sdp_header.HB2 != 0x1D)
2955                 return -EINVAL;
2956
2957         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
2958         if ((sdp->sdp_header.HB3 & 0x3) != 0)
2959                 return -EINVAL;
2960
2961         /* INFOFRAME SDP Version Number */
2962         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
2963                 return -EINVAL;
2964
2965         /* CTA Header Byte 2 (INFOFRAME Version Number) */
2966         if (sdp->db[0] != 1)
2967                 return -EINVAL;
2968
2969         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
2970         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
2971                 return -EINVAL;
2972
2973         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
2974                                              HDMI_DRM_INFOFRAME_SIZE);
2975
2976         return ret;
2977 }
2978
2979 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
2980                                   struct intel_crtc_state *crtc_state,
2981                                   struct drm_dp_vsc_sdp *vsc)
2982 {
2983         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2984         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2985         unsigned int type = DP_SDP_VSC;
2986         struct dp_sdp sdp = {};
2987         int ret;
2988
2989         /* When PSR is enabled, VSC SDP is handled by PSR routine */
2990         if (crtc_state->has_psr)
2991                 return;
2992
2993         if ((crtc_state->infoframes.enable &
2994              intel_hdmi_infoframe_enable(type)) == 0)
2995                 return;
2996
2997         dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
2998
2999         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
3000
3001         if (ret)
3002                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
3003 }
3004
3005 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
3006                                                      struct intel_crtc_state *crtc_state,
3007                                                      struct hdmi_drm_infoframe *drm_infoframe)
3008 {
3009         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3010         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3011         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
3012         struct dp_sdp sdp = {};
3013         int ret;
3014
3015         if ((crtc_state->infoframes.enable &
3016             intel_hdmi_infoframe_enable(type)) == 0)
3017                 return;
3018
3019         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
3020                                  sizeof(sdp));
3021
3022         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
3023                                                          sizeof(sdp));
3024
3025         if (ret)
3026                 drm_dbg_kms(&dev_priv->drm,
3027                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
3028 }
3029
3030 void intel_read_dp_sdp(struct intel_encoder *encoder,
3031                        struct intel_crtc_state *crtc_state,
3032                        unsigned int type)
3033 {
3034         if (encoder->type != INTEL_OUTPUT_DDI)
3035                 return;
3036
3037         switch (type) {
3038         case DP_SDP_VSC:
3039                 intel_read_dp_vsc_sdp(encoder, crtc_state,
3040                                       &crtc_state->infoframes.vsc);
3041                 break;
3042         case HDMI_PACKET_TYPE_GAMUT_METADATA:
3043                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
3044                                                          &crtc_state->infoframes.drm.drm);
3045                 break;
3046         default:
3047                 MISSING_CASE(type);
3048                 break;
3049         }
3050 }
3051
3052 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3053 {
3054         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3055         int status = 0;
3056         int test_link_rate;
3057         u8 test_lane_count, test_link_bw;
3058         /* (DP CTS 1.2)
3059          * 4.3.1.11
3060          */
3061         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3062         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3063                                    &test_lane_count);
3064
3065         if (status <= 0) {
3066                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
3067                 return DP_TEST_NAK;
3068         }
3069         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3070
3071         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3072                                    &test_link_bw);
3073         if (status <= 0) {
3074                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
3075                 return DP_TEST_NAK;
3076         }
3077         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3078
3079         /* Validate the requested link rate and lane count */
3080         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
3081                                         test_lane_count))
3082                 return DP_TEST_NAK;
3083
3084         intel_dp->compliance.test_lane_count = test_lane_count;
3085         intel_dp->compliance.test_link_rate = test_link_rate;
3086
3087         return DP_TEST_ACK;
3088 }
3089
3090 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3091 {
3092         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3093         u8 test_pattern;
3094         u8 test_misc;
3095         __be16 h_width, v_height;
3096         int status = 0;
3097
3098         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
3099         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
3100                                    &test_pattern);
3101         if (status <= 0) {
3102                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
3103                 return DP_TEST_NAK;
3104         }
3105         if (test_pattern != DP_COLOR_RAMP)
3106                 return DP_TEST_NAK;
3107
3108         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3109                                   &h_width, 2);
3110         if (status <= 0) {
3111                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
3112                 return DP_TEST_NAK;
3113         }
3114
3115         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3116                                   &v_height, 2);
3117         if (status <= 0) {
3118                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
3119                 return DP_TEST_NAK;
3120         }
3121
3122         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
3123                                    &test_misc);
3124         if (status <= 0) {
3125                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
3126                 return DP_TEST_NAK;
3127         }
3128         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
3129                 return DP_TEST_NAK;
3130         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
3131                 return DP_TEST_NAK;
3132         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
3133         case DP_TEST_BIT_DEPTH_6:
3134                 intel_dp->compliance.test_data.bpc = 6;
3135                 break;
3136         case DP_TEST_BIT_DEPTH_8:
3137                 intel_dp->compliance.test_data.bpc = 8;
3138                 break;
3139         default:
3140                 return DP_TEST_NAK;
3141         }
3142
3143         intel_dp->compliance.test_data.video_pattern = test_pattern;
3144         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
3145         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
3146         /* Set test active flag here so userspace doesn't interrupt things */
3147         intel_dp->compliance.test_active = true;
3148
3149         return DP_TEST_ACK;
3150 }
3151
3152 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
3153 {
3154         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3155         u8 test_result = DP_TEST_ACK;
3156         struct intel_connector *intel_connector = intel_dp->attached_connector;
3157         struct drm_connector *connector = &intel_connector->base;
3158
3159         if (intel_connector->detect_edid == NULL ||
3160             connector->edid_corrupt ||
3161             intel_dp->aux.i2c_defer_count > 6) {
3162                 /* Check EDID read for NACKs, DEFERs and corruption
3163                  * (DP CTS 1.2 Core r1.1)
3164                  *    4.2.2.4 : Failed EDID read, I2C_NAK
3165                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
3166                  *    4.2.2.6 : EDID corruption detected
3167                  * Use failsafe mode for all cases
3168                  */
3169                 if (intel_dp->aux.i2c_nack_count > 0 ||
3170                         intel_dp->aux.i2c_defer_count > 0)
3171                         drm_dbg_kms(&i915->drm,
3172                                     "EDID read had %d NACKs, %d DEFERs\n",
3173                                     intel_dp->aux.i2c_nack_count,
3174                                     intel_dp->aux.i2c_defer_count);
3175                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
3176         } else {
3177                 struct edid *block = intel_connector->detect_edid;
3178
3179                 /* We have to write the checksum
3180                  * of the last block read
3181                  */
3182                 block += intel_connector->detect_edid->extensions;
3183
3184                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
3185                                        block->checksum) <= 0)
3186                         drm_dbg_kms(&i915->drm,
3187                                     "Failed to write EDID checksum\n");
3188
3189                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3190                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
3191         }
3192
3193         /* Set test active flag here so userspace doesn't interrupt things */
3194         intel_dp->compliance.test_active = true;
3195
3196         return test_result;
3197 }
3198
3199 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
3200                                         const struct intel_crtc_state *crtc_state)
3201 {
3202         struct drm_i915_private *dev_priv =
3203                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3204         struct drm_dp_phy_test_params *data =
3205                         &intel_dp->compliance.test_data.phytest;
3206         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3207         enum pipe pipe = crtc->pipe;
3208         u32 pattern_val;
3209
3210         switch (data->phy_pattern) {
3211         case DP_PHY_TEST_PATTERN_NONE:
3212                 DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
3213                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
3214                 break;
3215         case DP_PHY_TEST_PATTERN_D10_2:
3216                 DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
3217                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3218                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
3219                 break;
3220         case DP_PHY_TEST_PATTERN_ERROR_COUNT:
3221                 DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
3222                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3223                                DDI_DP_COMP_CTL_ENABLE |
3224                                DDI_DP_COMP_CTL_SCRAMBLED_0);
3225                 break;
3226         case DP_PHY_TEST_PATTERN_PRBS7:
3227                 DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
3228                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3229                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
3230                 break;
3231         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
3232                 /*
3233                  * FIXME: Ideally pattern should come from DPCD 0x250. As
3234                  * current firmware of DPR-100 could not set it, so hardcoding
3235                  * now for complaince test.
3236                  */
3237                 DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
3238                 pattern_val = 0x3e0f83e0;
3239                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
3240                 pattern_val = 0x0f83e0f8;
3241                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
3242                 pattern_val = 0x0000f83e;
3243                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
3244                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3245                                DDI_DP_COMP_CTL_ENABLE |
3246                                DDI_DP_COMP_CTL_CUSTOM80);
3247                 break;
3248         case DP_PHY_TEST_PATTERN_CP2520:
3249                 /*
3250                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
3251                  * current firmware of DPR-100 could not set it, so hardcoding
3252                  * now for complaince test.
3253                  */
3254                 DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
3255                 pattern_val = 0xFB;
3256                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3257                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
3258                                pattern_val);
3259                 break;
3260         default:
3261                 WARN(1, "Invalid Phy Test Pattern\n");
3262         }
3263 }
3264
3265 static void
3266 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
3267                                   const struct intel_crtc_state *crtc_state)
3268 {
3269         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3270         struct drm_device *dev = dig_port->base.base.dev;
3271         struct drm_i915_private *dev_priv = to_i915(dev);
3272         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
3273         enum pipe pipe = crtc->pipe;
3274         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
3275
3276         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
3277                                                  TRANS_DDI_FUNC_CTL(pipe));
3278         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
3279         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
3280
3281         trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
3282                                       TGL_TRANS_DDI_PORT_MASK);
3283         trans_conf_value &= ~PIPECONF_ENABLE;
3284         dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
3285
3286         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
3287         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
3288                        trans_ddi_func_ctl_value);
3289         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
3290 }
3291
3292 static void
3293 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
3294                                  const struct intel_crtc_state *crtc_state)
3295 {
3296         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3297         struct drm_device *dev = dig_port->base.base.dev;
3298         struct drm_i915_private *dev_priv = to_i915(dev);
3299         enum port port = dig_port->base.port;
3300         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
3301         enum pipe pipe = crtc->pipe;
3302         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
3303
3304         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
3305                                                  TRANS_DDI_FUNC_CTL(pipe));
3306         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
3307         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
3308
3309         trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
3310                                     TGL_TRANS_DDI_SELECT_PORT(port);
3311         trans_conf_value |= PIPECONF_ENABLE;
3312         dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
3313
3314         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
3315         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
3316         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
3317                        trans_ddi_func_ctl_value);
3318 }
3319
3320 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
3321                                          const struct intel_crtc_state *crtc_state)
3322 {
3323         struct drm_dp_phy_test_params *data =
3324                 &intel_dp->compliance.test_data.phytest;
3325         u8 link_status[DP_LINK_STATUS_SIZE];
3326
3327         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3328                                              link_status) < 0) {
3329                 DRM_DEBUG_KMS("failed to get link status\n");
3330                 return;
3331         }
3332
3333         /* retrieve vswing & pre-emphasis setting */
3334         intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
3335                                   link_status);
3336
3337         intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
3338
3339         intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
3340
3341         intel_dp_phy_pattern_update(intel_dp, crtc_state);
3342
3343         intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
3344
3345         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
3346                                     link_status[DP_DPCD_REV]);
3347 }
3348
3349 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3350 {
3351         struct drm_dp_phy_test_params *data =
3352                 &intel_dp->compliance.test_data.phytest;
3353
3354         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
3355                 DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
3356                 return DP_TEST_NAK;
3357         }
3358
3359         /* Set test active flag here so userspace doesn't interrupt things */
3360         intel_dp->compliance.test_active = true;
3361
3362         return DP_TEST_ACK;
3363 }
3364
3365 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3366 {
3367         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3368         u8 response = DP_TEST_NAK;
3369         u8 request = 0;
3370         int status;
3371
3372         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
3373         if (status <= 0) {
3374                 drm_dbg_kms(&i915->drm,
3375                             "Could not read test request from sink\n");
3376                 goto update_status;
3377         }
3378
3379         switch (request) {
3380         case DP_TEST_LINK_TRAINING:
3381                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
3382                 response = intel_dp_autotest_link_training(intel_dp);
3383                 break;
3384         case DP_TEST_LINK_VIDEO_PATTERN:
3385                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
3386                 response = intel_dp_autotest_video_pattern(intel_dp);
3387                 break;
3388         case DP_TEST_LINK_EDID_READ:
3389                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
3390                 response = intel_dp_autotest_edid(intel_dp);
3391                 break;
3392         case DP_TEST_LINK_PHY_TEST_PATTERN:
3393                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
3394                 response = intel_dp_autotest_phy_pattern(intel_dp);
3395                 break;
3396         default:
3397                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
3398                             request);
3399                 break;
3400         }
3401
3402         if (response & DP_TEST_ACK)
3403                 intel_dp->compliance.test_type = request;
3404
3405 update_status:
3406         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
3407         if (status <= 0)
3408                 drm_dbg_kms(&i915->drm,
3409                             "Could not write test response to sink\n");
3410 }
3411
3412 static void
3413 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, bool *handled)
3414 {
3415                 drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, handled);
3416
3417                 if (esi[1] & DP_CP_IRQ) {
3418                         intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
3419                         *handled = true;
3420                 }
3421 }
3422
3423 /**
3424  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
3425  * @intel_dp: Intel DP struct
3426  *
3427  * Read any pending MST interrupts, call MST core to handle these and ack the
3428  * interrupts. Check if the main and AUX link state is ok.
3429  *
3430  * Returns:
3431  * - %true if pending interrupts were serviced (or no interrupts were
3432  *   pending) w/o detecting an error condition.
3433  * - %false if an error condition - like AUX failure or a loss of link - is
3434  *   detected, which needs servicing from the hotplug work.
3435  */
3436 static bool
3437 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3438 {
3439         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3440         bool link_ok = true;
3441
3442         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
3443
3444         for (;;) {
3445                 /*
3446                  * The +2 is because DP_DPRX_ESI_LEN is 14, but we then
3447                  * pass in "esi+10" to drm_dp_channel_eq_ok(), which
3448                  * takes a 6-byte array. So we actually need 16 bytes
3449                  * here.
3450                  *
3451                  * Somebody who knows what the limits actually are
3452                  * should check this, but for now this is at least
3453                  * harmless and avoids a valid compiler warning about
3454                  * using more of the array than we have allocated.
3455                  */
3456                 u8 esi[DP_DPRX_ESI_LEN+2] = {};
3457                 bool handled;
3458                 int retry;
3459
3460                 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
3461                         drm_dbg_kms(&i915->drm,
3462                                     "failed to get ESI - device may have failed\n");
3463                         link_ok = false;
3464
3465                         break;
3466                 }
3467
3468                 /* check link status - esi[10] = 0x200c */
3469                 if (intel_dp->active_mst_links > 0 && link_ok &&
3470                     !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3471                         drm_dbg_kms(&i915->drm,
3472                                     "channel EQ not ok, retraining\n");
3473                         link_ok = false;
3474                 }
3475
3476                 drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
3477
3478                 intel_dp_mst_hpd_irq(intel_dp, esi, &handled);
3479
3480                 if (!handled)
3481                         break;
3482
3483                 for (retry = 0; retry < 3; retry++) {
3484                         int wret;
3485
3486                         wret = drm_dp_dpcd_write(&intel_dp->aux,
3487                                                  DP_SINK_COUNT_ESI+1,
3488                                                  &esi[1], 3);
3489                         if (wret == 3)
3490                                 break;
3491                 }
3492         }
3493
3494         return link_ok;
3495 }
3496
3497 static void
3498 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
3499 {
3500         bool is_active;
3501         u8 buf = 0;
3502
3503         is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
3504         if (intel_dp->frl.is_trained && !is_active) {
3505                 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
3506                         return;
3507
3508                 buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
3509                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
3510                         return;
3511
3512                 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
3513
3514                 /* Restart FRL training or fall back to TMDS mode */
3515                 intel_dp_check_frl_training(intel_dp);
3516         }
3517 }
3518
3519 static bool
3520 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
3521 {
3522         u8 link_status[DP_LINK_STATUS_SIZE];
3523
3524         if (!intel_dp->link_trained)
3525                 return false;
3526
3527         /*
3528          * While PSR source HW is enabled, it will control main-link sending
3529          * frames, enabling and disabling it so trying to do a retrain will fail
3530          * as the link would or not be on or it could mix training patterns
3531          * and frame data at the same time causing retrain to fail.
3532          * Also when exiting PSR, HW will retrain the link anyways fixing
3533          * any link status error.
3534          */
3535         if (intel_psr_enabled(intel_dp))
3536                 return false;
3537
3538         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3539                                              link_status) < 0)
3540                 return false;
3541
3542         /*
3543          * Validate the cached values of intel_dp->link_rate and
3544          * intel_dp->lane_count before attempting to retrain.
3545          *
3546          * FIXME would be nice to user the crtc state here, but since
3547          * we need to call this from the short HPD handler that seems
3548          * a bit hard.
3549          */
3550         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
3551                                         intel_dp->lane_count))
3552                 return false;
3553
3554         /* Retrain if Channel EQ or CR not ok */
3555         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
3556 }
3557
3558 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
3559                                    const struct drm_connector_state *conn_state)
3560 {
3561         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3562         struct intel_encoder *encoder;
3563         enum pipe pipe;
3564
3565         if (!conn_state->best_encoder)
3566                 return false;
3567
3568         /* SST */
3569         encoder = &dp_to_dig_port(intel_dp)->base;
3570         if (conn_state->best_encoder == &encoder->base)
3571                 return true;
3572
3573         /* MST */
3574         for_each_pipe(i915, pipe) {
3575                 encoder = &intel_dp->mst_encoders[pipe]->base;
3576                 if (conn_state->best_encoder == &encoder->base)
3577                         return true;
3578         }
3579
3580         return false;
3581 }
3582
3583 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
3584                                       struct drm_modeset_acquire_ctx *ctx,
3585                                       u32 *crtc_mask)
3586 {
3587         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3588         struct drm_connector_list_iter conn_iter;
3589         struct intel_connector *connector;
3590         int ret = 0;
3591
3592         *crtc_mask = 0;
3593
3594         if (!intel_dp_needs_link_retrain(intel_dp))
3595                 return 0;
3596
3597         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
3598         for_each_intel_connector_iter(connector, &conn_iter) {
3599                 struct drm_connector_state *conn_state =
3600                         connector->base.state;
3601                 struct intel_crtc_state *crtc_state;
3602                 struct intel_crtc *crtc;
3603
3604                 if (!intel_dp_has_connector(intel_dp, conn_state))
3605                         continue;
3606
3607                 crtc = to_intel_crtc(conn_state->crtc);
3608                 if (!crtc)
3609                         continue;
3610
3611                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3612                 if (ret)
3613                         break;
3614
3615                 crtc_state = to_intel_crtc_state(crtc->base.state);
3616
3617                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
3618
3619                 if (!crtc_state->hw.active)
3620                         continue;
3621
3622                 if (conn_state->commit &&
3623                     !try_wait_for_completion(&conn_state->commit->hw_done))
3624                         continue;
3625
3626                 *crtc_mask |= drm_crtc_mask(&crtc->base);
3627         }
3628         drm_connector_list_iter_end(&conn_iter);
3629
3630         if (!intel_dp_needs_link_retrain(intel_dp))
3631                 *crtc_mask = 0;
3632
3633         return ret;
3634 }
3635
3636 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
3637 {
3638         struct intel_connector *connector = intel_dp->attached_connector;
3639
3640         return connector->base.status == connector_status_connected ||
3641                 intel_dp->is_mst;
3642 }
3643
3644 int intel_dp_retrain_link(struct intel_encoder *encoder,
3645                           struct drm_modeset_acquire_ctx *ctx)
3646 {
3647         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3648         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3649         struct intel_crtc *crtc;
3650         u32 crtc_mask;
3651         int ret;
3652
3653         if (!intel_dp_is_connected(intel_dp))
3654                 return 0;
3655
3656         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3657                                ctx);
3658         if (ret)
3659                 return ret;
3660
3661         ret = intel_dp_prep_link_retrain(intel_dp, ctx, &crtc_mask);
3662         if (ret)
3663                 return ret;
3664
3665         if (crtc_mask == 0)
3666                 return 0;
3667
3668         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
3669                     encoder->base.base.id, encoder->base.name);
3670
3671         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3672                 const struct intel_crtc_state *crtc_state =
3673                         to_intel_crtc_state(crtc->base.state);
3674
3675                 /* Suppress underruns caused by re-training */
3676                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3677                 if (crtc_state->has_pch_encoder)
3678                         intel_set_pch_fifo_underrun_reporting(dev_priv,
3679                                                               intel_crtc_pch_transcoder(crtc), false);
3680         }
3681
3682         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3683                 const struct intel_crtc_state *crtc_state =
3684                         to_intel_crtc_state(crtc->base.state);
3685
3686                 /* retrain on the MST master transcoder */
3687                 if (DISPLAY_VER(dev_priv) >= 12 &&
3688                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
3689                     !intel_dp_mst_is_master_trans(crtc_state))
3690                         continue;
3691
3692                 intel_dp_check_frl_training(intel_dp);
3693                 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
3694                 intel_dp_start_link_train(intel_dp, crtc_state);
3695                 intel_dp_stop_link_train(intel_dp, crtc_state);
3696                 break;
3697         }
3698
3699         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3700                 const struct intel_crtc_state *crtc_state =
3701                         to_intel_crtc_state(crtc->base.state);
3702
3703                 /* Keep underrun reporting disabled until things are stable */
3704                 intel_wait_for_vblank(dev_priv, crtc->pipe);
3705
3706                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
3707                 if (crtc_state->has_pch_encoder)
3708                         intel_set_pch_fifo_underrun_reporting(dev_priv,
3709                                                               intel_crtc_pch_transcoder(crtc), true);
3710         }
3711
3712         return 0;
3713 }
3714
3715 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
3716                                   struct drm_modeset_acquire_ctx *ctx,
3717                                   u32 *crtc_mask)
3718 {
3719         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3720         struct drm_connector_list_iter conn_iter;
3721         struct intel_connector *connector;
3722         int ret = 0;
3723
3724         *crtc_mask = 0;
3725
3726         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
3727         for_each_intel_connector_iter(connector, &conn_iter) {
3728                 struct drm_connector_state *conn_state =
3729                         connector->base.state;
3730                 struct intel_crtc_state *crtc_state;
3731                 struct intel_crtc *crtc;
3732
3733                 if (!intel_dp_has_connector(intel_dp, conn_state))
3734                         continue;
3735
3736                 crtc = to_intel_crtc(conn_state->crtc);
3737                 if (!crtc)
3738                         continue;
3739
3740                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3741                 if (ret)
3742                         break;
3743
3744                 crtc_state = to_intel_crtc_state(crtc->base.state);
3745
3746                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
3747
3748                 if (!crtc_state->hw.active)
3749                         continue;
3750
3751                 if (conn_state->commit &&
3752                     !try_wait_for_completion(&conn_state->commit->hw_done))
3753                         continue;
3754
3755                 *crtc_mask |= drm_crtc_mask(&crtc->base);
3756         }
3757         drm_connector_list_iter_end(&conn_iter);
3758
3759         return ret;
3760 }
3761
3762 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
3763                                 struct drm_modeset_acquire_ctx *ctx)
3764 {
3765         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3766         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3767         struct intel_crtc *crtc;
3768         u32 crtc_mask;
3769         int ret;
3770
3771         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3772                                ctx);
3773         if (ret)
3774                 return ret;
3775
3776         ret = intel_dp_prep_phy_test(intel_dp, ctx, &crtc_mask);
3777         if (ret)
3778                 return ret;
3779
3780         if (crtc_mask == 0)
3781                 return 0;
3782
3783         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
3784                     encoder->base.base.id, encoder->base.name);
3785
3786         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
3787                 const struct intel_crtc_state *crtc_state =
3788                         to_intel_crtc_state(crtc->base.state);
3789
3790                 /* test on the MST master transcoder */
3791                 if (DISPLAY_VER(dev_priv) >= 12 &&
3792                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
3793                     !intel_dp_mst_is_master_trans(crtc_state))
3794                         continue;
3795
3796                 intel_dp_process_phy_request(intel_dp, crtc_state);
3797                 break;
3798         }
3799
3800         return 0;
3801 }
3802
3803 void intel_dp_phy_test(struct intel_encoder *encoder)
3804 {
3805         struct drm_modeset_acquire_ctx ctx;
3806         int ret;
3807
3808         drm_modeset_acquire_init(&ctx, 0);
3809
3810         for (;;) {
3811                 ret = intel_dp_do_phy_test(encoder, &ctx);
3812
3813                 if (ret == -EDEADLK) {
3814                         drm_modeset_backoff(&ctx);
3815                         continue;
3816                 }
3817
3818                 break;
3819         }
3820
3821         drm_modeset_drop_locks(&ctx);
3822         drm_modeset_acquire_fini(&ctx);
3823         drm_WARN(encoder->base.dev, ret,
3824                  "Acquiring modeset locks failed with %i\n", ret);
3825 }
3826
3827 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
3828 {
3829         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3830         u8 val;
3831
3832         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3833                 return;
3834
3835         if (drm_dp_dpcd_readb(&intel_dp->aux,
3836                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
3837                 return;
3838
3839         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
3840
3841         if (val & DP_AUTOMATED_TEST_REQUEST)
3842                 intel_dp_handle_test_request(intel_dp);
3843
3844         if (val & DP_CP_IRQ)
3845                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
3846
3847         if (val & DP_SINK_SPECIFIC_IRQ)
3848                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
3849 }
3850
3851 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
3852 {
3853         u8 val;
3854
3855         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3856                 return;
3857
3858         if (drm_dp_dpcd_readb(&intel_dp->aux,
3859                               DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
3860                 return;
3861
3862         if (drm_dp_dpcd_writeb(&intel_dp->aux,
3863                                DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
3864                 return;
3865
3866         if (val & HDMI_LINK_STATUS_CHANGED)
3867                 intel_dp_handle_hdmi_link_status_change(intel_dp);
3868 }
3869
3870 /*
3871  * According to DP spec
3872  * 5.1.2:
3873  *  1. Read DPCD
3874  *  2. Configure link according to Receiver Capabilities
3875  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
3876  *  4. Check link status on receipt of hot-plug interrupt
3877  *
3878  * intel_dp_short_pulse -  handles short pulse interrupts
3879  * when full detection is not required.
3880  * Returns %true if short pulse is handled and full detection
3881  * is NOT required and %false otherwise.
3882  */
3883 static bool
3884 intel_dp_short_pulse(struct intel_dp *intel_dp)
3885 {
3886         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3887         u8 old_sink_count = intel_dp->sink_count;
3888         bool ret;
3889
3890         /*
3891          * Clearing compliance test variables to allow capturing
3892          * of values for next automated test request.
3893          */
3894         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
3895
3896         /*
3897          * Now read the DPCD to see if it's actually running
3898          * If the current value of sink count doesn't match with
3899          * the value that was stored earlier or dpcd read failed
3900          * we need to do full detection
3901          */
3902         ret = intel_dp_get_dpcd(intel_dp);
3903
3904         if ((old_sink_count != intel_dp->sink_count) || !ret) {
3905                 /* No need to proceed if we are going to do full detect */
3906                 return false;
3907         }
3908
3909         intel_dp_check_device_service_irq(intel_dp);
3910         intel_dp_check_link_service_irq(intel_dp);
3911
3912         /* Handle CEC interrupts, if any */
3913         drm_dp_cec_irq(&intel_dp->aux);
3914
3915         /* defer to the hotplug work for link retraining if needed */
3916         if (intel_dp_needs_link_retrain(intel_dp))
3917                 return false;
3918
3919         intel_psr_short_pulse(intel_dp);
3920
3921         switch (intel_dp->compliance.test_type) {
3922         case DP_TEST_LINK_TRAINING:
3923                 drm_dbg_kms(&dev_priv->drm,
3924                             "Link Training Compliance Test requested\n");
3925                 /* Send a Hotplug Uevent to userspace to start modeset */
3926                 drm_kms_helper_hotplug_event(&dev_priv->drm);
3927                 break;
3928         case DP_TEST_LINK_PHY_TEST_PATTERN:
3929                 drm_dbg_kms(&dev_priv->drm,
3930                             "PHY test pattern Compliance Test requested\n");
3931                 /*
3932                  * Schedule long hpd to do the test
3933                  *
3934                  * FIXME get rid of the ad-hoc phy test modeset code
3935                  * and properly incorporate it into the normal modeset.
3936                  */
3937                 return false;
3938         }
3939
3940         return true;
3941 }
3942
3943 /* XXX this is probably wrong for multiple downstream ports */
3944 static enum drm_connector_status
3945 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3946 {
3947         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3948         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3949         u8 *dpcd = intel_dp->dpcd;
3950         u8 type;
3951
3952         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
3953                 return connector_status_connected;
3954
3955         lspcon_resume(dig_port);
3956
3957         if (!intel_dp_get_dpcd(intel_dp))
3958                 return connector_status_disconnected;
3959
3960         /* if there's no downstream port, we're done */
3961         if (!drm_dp_is_branch(dpcd))
3962                 return connector_status_connected;
3963
3964         /* If we're HPD-aware, SINK_COUNT changes dynamically */
3965         if (intel_dp_has_sink_count(intel_dp) &&
3966             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3967                 return intel_dp->sink_count ?
3968                 connector_status_connected : connector_status_disconnected;
3969         }
3970
3971         if (intel_dp_can_mst(intel_dp))
3972                 return connector_status_connected;
3973
3974         /* If no HPD, poke DDC gently */
3975         if (drm_probe_ddc(&intel_dp->aux.ddc))
3976                 return connector_status_connected;
3977
3978         /* Well we tried, say unknown for unreliable port types */
3979         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3980                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3981                 if (type == DP_DS_PORT_TYPE_VGA ||
3982                     type == DP_DS_PORT_TYPE_NON_EDID)
3983                         return connector_status_unknown;
3984         } else {
3985                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3986                         DP_DWN_STRM_PORT_TYPE_MASK;
3987                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3988                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
3989                         return connector_status_unknown;
3990         }
3991
3992         /* Anything else is out of spec, warn and ignore */
3993         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
3994         return connector_status_disconnected;
3995 }
3996
3997 static enum drm_connector_status
3998 edp_detect(struct intel_dp *intel_dp)
3999 {
4000         return connector_status_connected;
4001 }
4002
4003 /*
4004  * intel_digital_port_connected - is the specified port connected?
4005  * @encoder: intel_encoder
4006  *
4007  * In cases where there's a connector physically connected but it can't be used
4008  * by our hardware we also return false, since the rest of the driver should
4009  * pretty much treat the port as disconnected. This is relevant for type-C
4010  * (starting on ICL) where there's ownership involved.
4011  *
4012  * Return %true if port is connected, %false otherwise.
4013  */
4014 bool intel_digital_port_connected(struct intel_encoder *encoder)
4015 {
4016         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4017         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4018         bool is_connected = false;
4019         intel_wakeref_t wakeref;
4020
4021         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
4022                 is_connected = dig_port->connected(encoder);
4023
4024         return is_connected;
4025 }
4026
4027 static struct edid *
4028 intel_dp_get_edid(struct intel_dp *intel_dp)
4029 {
4030         struct intel_connector *intel_connector = intel_dp->attached_connector;
4031
4032         /* use cached edid if we have one */
4033         if (intel_connector->edid) {
4034                 /* invalid edid */
4035                 if (IS_ERR(intel_connector->edid))
4036                         return NULL;
4037
4038                 return drm_edid_duplicate(intel_connector->edid);
4039         } else
4040                 return drm_get_edid(&intel_connector->base,
4041                                     &intel_dp->aux.ddc);
4042 }
4043
4044 static void
4045 intel_dp_update_dfp(struct intel_dp *intel_dp,
4046                     const struct edid *edid)
4047 {
4048         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4049         struct intel_connector *connector = intel_dp->attached_connector;
4050
4051         intel_dp->dfp.max_bpc =
4052                 drm_dp_downstream_max_bpc(intel_dp->dpcd,
4053                                           intel_dp->downstream_ports, edid);
4054
4055         intel_dp->dfp.max_dotclock =
4056                 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
4057                                                intel_dp->downstream_ports);
4058
4059         intel_dp->dfp.min_tmds_clock =
4060                 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
4061                                                  intel_dp->downstream_ports,
4062                                                  edid);
4063         intel_dp->dfp.max_tmds_clock =
4064                 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
4065                                                  intel_dp->downstream_ports,
4066                                                  edid);
4067
4068         intel_dp->dfp.pcon_max_frl_bw =
4069                 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
4070                                            intel_dp->downstream_ports);
4071
4072         drm_dbg_kms(&i915->drm,
4073                     "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
4074                     connector->base.base.id, connector->base.name,
4075                     intel_dp->dfp.max_bpc,
4076                     intel_dp->dfp.max_dotclock,
4077                     intel_dp->dfp.min_tmds_clock,
4078                     intel_dp->dfp.max_tmds_clock,
4079                     intel_dp->dfp.pcon_max_frl_bw);
4080
4081         intel_dp_get_pcon_dsc_cap(intel_dp);
4082 }
4083
4084 static void
4085 intel_dp_update_420(struct intel_dp *intel_dp)
4086 {
4087         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4088         struct intel_connector *connector = intel_dp->attached_connector;
4089         bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
4090
4091         /* No YCbCr output support on gmch platforms */
4092         if (HAS_GMCH(i915))
4093                 return;
4094
4095         /*
4096          * ILK doesn't seem capable of DP YCbCr output. The
4097          * displayed image is severly corrupted. SNB+ is fine.
4098          */
4099         if (IS_IRONLAKE(i915))
4100                 return;
4101
4102         is_branch = drm_dp_is_branch(intel_dp->dpcd);
4103         ycbcr_420_passthrough =
4104                 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
4105                                                   intel_dp->downstream_ports);
4106         /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
4107         ycbcr_444_to_420 =
4108                 dp_to_dig_port(intel_dp)->lspcon.active ||
4109                 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
4110                                                         intel_dp->downstream_ports);
4111         rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
4112                                                                  intel_dp->downstream_ports,
4113                                                                  DP_DS_HDMI_BT601_RGB_YCBCR_CONV |
4114                                                                  DP_DS_HDMI_BT709_RGB_YCBCR_CONV |
4115                                                                  DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
4116
4117         if (DISPLAY_VER(i915) >= 11) {
4118                 /* Let PCON convert from RGB->YCbCr if possible */
4119                 if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
4120                         intel_dp->dfp.rgb_to_ycbcr = true;
4121                         intel_dp->dfp.ycbcr_444_to_420 = true;
4122                         connector->base.ycbcr_420_allowed = true;
4123                 } else {
4124                 /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
4125                         intel_dp->dfp.ycbcr_444_to_420 =
4126                                 ycbcr_444_to_420 && !ycbcr_420_passthrough;
4127
4128                         connector->base.ycbcr_420_allowed =
4129                                 !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
4130                 }
4131         } else {
4132                 /* 4:4:4->4:2:0 conversion is the only way */
4133                 intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
4134
4135                 connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
4136         }
4137
4138         drm_dbg_kms(&i915->drm,
4139                     "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
4140                     connector->base.base.id, connector->base.name,
4141                     yesno(intel_dp->dfp.rgb_to_ycbcr),
4142                     yesno(connector->base.ycbcr_420_allowed),
4143                     yesno(intel_dp->dfp.ycbcr_444_to_420));
4144 }
4145
4146 static void
4147 intel_dp_set_edid(struct intel_dp *intel_dp)
4148 {
4149         struct intel_connector *connector = intel_dp->attached_connector;
4150         struct edid *edid;
4151
4152         intel_dp_unset_edid(intel_dp);
4153         edid = intel_dp_get_edid(intel_dp);
4154         connector->detect_edid = edid;
4155
4156         intel_dp_update_dfp(intel_dp, edid);
4157         intel_dp_update_420(intel_dp);
4158
4159         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
4160                 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
4161                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4162         }
4163
4164         drm_dp_cec_set_edid(&intel_dp->aux, edid);
4165 }
4166
4167 static void
4168 intel_dp_unset_edid(struct intel_dp *intel_dp)
4169 {
4170         struct intel_connector *connector = intel_dp->attached_connector;
4171
4172         drm_dp_cec_unset_edid(&intel_dp->aux);
4173         kfree(connector->detect_edid);
4174         connector->detect_edid = NULL;
4175
4176         intel_dp->has_hdmi_sink = false;
4177         intel_dp->has_audio = false;
4178
4179         intel_dp->dfp.max_bpc = 0;
4180         intel_dp->dfp.max_dotclock = 0;
4181         intel_dp->dfp.min_tmds_clock = 0;
4182         intel_dp->dfp.max_tmds_clock = 0;
4183
4184         intel_dp->dfp.pcon_max_frl_bw = 0;
4185
4186         intel_dp->dfp.ycbcr_444_to_420 = false;
4187         connector->base.ycbcr_420_allowed = false;
4188 }
4189
4190 static int
4191 intel_dp_detect(struct drm_connector *connector,
4192                 struct drm_modeset_acquire_ctx *ctx,
4193                 bool force)
4194 {
4195         struct drm_i915_private *dev_priv = to_i915(connector->dev);
4196         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4197         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4198         struct intel_encoder *encoder = &dig_port->base;
4199         enum drm_connector_status status;
4200
4201         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4202                     connector->base.id, connector->name);
4203         drm_WARN_ON(&dev_priv->drm,
4204                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4205
4206         if (!INTEL_DISPLAY_ENABLED(dev_priv))
4207                 return connector_status_disconnected;
4208
4209         /* Can't disconnect eDP */
4210         if (intel_dp_is_edp(intel_dp))
4211                 status = edp_detect(intel_dp);
4212         else if (intel_digital_port_connected(encoder))
4213                 status = intel_dp_detect_dpcd(intel_dp);
4214         else
4215                 status = connector_status_disconnected;
4216
4217         if (status == connector_status_disconnected) {
4218                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4219                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4220
4221                 if (intel_dp->is_mst) {
4222                         drm_dbg_kms(&dev_priv->drm,
4223                                     "MST device may have disappeared %d vs %d\n",
4224                                     intel_dp->is_mst,
4225                                     intel_dp->mst_mgr.mst_state);
4226                         intel_dp->is_mst = false;
4227                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4228                                                         intel_dp->is_mst);
4229                 }
4230
4231                 goto out;
4232         }
4233
4234         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4235         if (DISPLAY_VER(dev_priv) >= 11)
4236                 intel_dp_get_dsc_sink_cap(intel_dp);
4237
4238         intel_dp_configure_mst(intel_dp);
4239
4240         /*
4241          * TODO: Reset link params when switching to MST mode, until MST
4242          * supports link training fallback params.
4243          */
4244         if (intel_dp->reset_link_params || intel_dp->is_mst) {
4245                 /* Initial max link lane count */
4246                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4247
4248                 /* Initial max link rate */
4249                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4250
4251                 intel_dp->reset_link_params = false;
4252         }
4253
4254         intel_dp_print_rates(intel_dp);
4255
4256         if (intel_dp->is_mst) {
4257                 /*
4258                  * If we are in MST mode then this connector
4259                  * won't appear connected or have anything
4260                  * with EDID on it
4261                  */
4262                 status = connector_status_disconnected;
4263                 goto out;
4264         }
4265
4266         /*
4267          * Some external monitors do not signal loss of link synchronization
4268          * with an IRQ_HPD, so force a link status check.
4269          */
4270         if (!intel_dp_is_edp(intel_dp)) {
4271                 int ret;
4272
4273                 ret = intel_dp_retrain_link(encoder, ctx);
4274                 if (ret)
4275                         return ret;
4276         }
4277
4278         /*
4279          * Clearing NACK and defer counts to get their exact values
4280          * while reading EDID which are required by Compliance tests
4281          * 4.2.2.4 and 4.2.2.5
4282          */
4283         intel_dp->aux.i2c_nack_count = 0;
4284         intel_dp->aux.i2c_defer_count = 0;
4285
4286         intel_dp_set_edid(intel_dp);
4287         if (intel_dp_is_edp(intel_dp) ||
4288             to_intel_connector(connector)->detect_edid)
4289                 status = connector_status_connected;
4290
4291         intel_dp_check_device_service_irq(intel_dp);
4292
4293 out:
4294         if (status != connector_status_connected && !intel_dp->is_mst)
4295                 intel_dp_unset_edid(intel_dp);
4296
4297         /*
4298          * Make sure the refs for power wells enabled during detect are
4299          * dropped to avoid a new detect cycle triggered by HPD polling.
4300          */
4301         intel_display_power_flush_work(dev_priv);
4302
4303         if (!intel_dp_is_edp(intel_dp))
4304                 drm_dp_set_subconnector_property(connector,
4305                                                  status,
4306                                                  intel_dp->dpcd,
4307                                                  intel_dp->downstream_ports);
4308         return status;
4309 }
4310
4311 static void
4312 intel_dp_force(struct drm_connector *connector)
4313 {
4314         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4315         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4316         struct intel_encoder *intel_encoder = &dig_port->base;
4317         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4318         enum intel_display_power_domain aux_domain =
4319                 intel_aux_power_domain(dig_port);
4320         intel_wakeref_t wakeref;
4321
4322         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4323                     connector->base.id, connector->name);
4324         intel_dp_unset_edid(intel_dp);
4325
4326         if (connector->status != connector_status_connected)
4327                 return;
4328
4329         wakeref = intel_display_power_get(dev_priv, aux_domain);
4330
4331         intel_dp_set_edid(intel_dp);
4332
4333         intel_display_power_put(dev_priv, aux_domain, wakeref);
4334 }
4335
4336 static int intel_dp_get_modes(struct drm_connector *connector)
4337 {
4338         struct intel_connector *intel_connector = to_intel_connector(connector);
4339         struct edid *edid;
4340         int num_modes = 0;
4341
4342         edid = intel_connector->detect_edid;
4343         if (edid) {
4344                 num_modes = intel_connector_update_modes(connector, edid);
4345
4346                 if (intel_vrr_is_capable(connector))
4347                         drm_connector_set_vrr_capable_property(connector,
4348                                                                true);
4349         }
4350
4351         /* Also add fixed mode, which may or may not be present in EDID */
4352         if (intel_dp_is_edp(intel_attached_dp(intel_connector)) &&
4353             intel_connector->panel.fixed_mode) {
4354                 struct drm_display_mode *mode;
4355
4356                 mode = drm_mode_duplicate(connector->dev,
4357                                           intel_connector->panel.fixed_mode);
4358                 if (mode) {
4359                         drm_mode_probed_add(connector, mode);
4360                         num_modes++;
4361                 }
4362         }
4363
4364         if (num_modes)
4365                 return num_modes;
4366
4367         if (!edid) {
4368                 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
4369                 struct drm_display_mode *mode;
4370
4371                 mode = drm_dp_downstream_mode(connector->dev,
4372                                               intel_dp->dpcd,
4373                                               intel_dp->downstream_ports);
4374                 if (mode) {
4375                         drm_mode_probed_add(connector, mode);
4376                         num_modes++;
4377                 }
4378         }
4379
4380         return num_modes;
4381 }
4382
4383 static int
4384 intel_dp_connector_register(struct drm_connector *connector)
4385 {
4386         struct drm_i915_private *i915 = to_i915(connector->dev);
4387         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4388         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4389         struct intel_lspcon *lspcon = &dig_port->lspcon;
4390         int ret;
4391
4392         ret = intel_connector_register(connector);
4393         if (ret)
4394                 return ret;
4395
4396         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
4397                     intel_dp->aux.name, connector->kdev->kobj.name);
4398
4399         intel_dp->aux.dev = connector->kdev;
4400         ret = drm_dp_aux_register(&intel_dp->aux);
4401         if (!ret)
4402                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
4403
4404         if (!intel_bios_is_lspcon_present(i915, dig_port->base.port))
4405                 return ret;
4406
4407         /*
4408          * ToDo: Clean this up to handle lspcon init and resume more
4409          * efficiently and streamlined.
4410          */
4411         if (lspcon_init(dig_port)) {
4412                 lspcon_detect_hdr_capability(lspcon);
4413                 if (lspcon->hdr_supported)
4414                         drm_object_attach_property(&connector->base,
4415                                                    connector->dev->mode_config.hdr_output_metadata_property,
4416                                                    0);
4417         }
4418
4419         return ret;
4420 }
4421
4422 static void
4423 intel_dp_connector_unregister(struct drm_connector *connector)
4424 {
4425         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4426
4427         drm_dp_cec_unregister_connector(&intel_dp->aux);
4428         drm_dp_aux_unregister(&intel_dp->aux);
4429         intel_connector_unregister(connector);
4430 }
4431
4432 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
4433 {
4434         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4435         struct intel_dp *intel_dp = &dig_port->dp;
4436
4437         intel_dp_mst_encoder_cleanup(dig_port);
4438
4439         intel_pps_vdd_off_sync(intel_dp);
4440
4441         intel_dp_aux_fini(intel_dp);
4442 }
4443
4444 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4445 {
4446         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4447
4448         intel_pps_vdd_off_sync(intel_dp);
4449 }
4450
4451 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
4452 {
4453         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4454
4455         intel_pps_wait_power_cycle(intel_dp);
4456 }
4457
4458 static int intel_modeset_tile_group(struct intel_atomic_state *state,
4459                                     int tile_group_id)
4460 {
4461         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4462         struct drm_connector_list_iter conn_iter;
4463         struct drm_connector *connector;
4464         int ret = 0;
4465
4466         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
4467         drm_for_each_connector_iter(connector, &conn_iter) {
4468                 struct drm_connector_state *conn_state;
4469                 struct intel_crtc_state *crtc_state;
4470                 struct intel_crtc *crtc;
4471
4472                 if (!connector->has_tile ||
4473                     connector->tile_group->id != tile_group_id)
4474                         continue;
4475
4476                 conn_state = drm_atomic_get_connector_state(&state->base,
4477                                                             connector);
4478                 if (IS_ERR(conn_state)) {
4479                         ret = PTR_ERR(conn_state);
4480                         break;
4481                 }
4482
4483                 crtc = to_intel_crtc(conn_state->crtc);
4484
4485                 if (!crtc)
4486                         continue;
4487
4488                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
4489                 crtc_state->uapi.mode_changed = true;
4490
4491                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4492                 if (ret)
4493                         break;
4494         }
4495         drm_connector_list_iter_end(&conn_iter);
4496
4497         return ret;
4498 }
4499
4500 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
4501 {
4502         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4503         struct intel_crtc *crtc;
4504
4505         if (transcoders == 0)
4506                 return 0;
4507
4508         for_each_intel_crtc(&dev_priv->drm, crtc) {
4509                 struct intel_crtc_state *crtc_state;
4510                 int ret;
4511
4512                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
4513                 if (IS_ERR(crtc_state))
4514                         return PTR_ERR(crtc_state);
4515
4516                 if (!crtc_state->hw.enable)
4517                         continue;
4518
4519                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
4520                         continue;
4521
4522                 crtc_state->uapi.mode_changed = true;
4523
4524                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
4525                 if (ret)
4526                         return ret;
4527
4528                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4529                 if (ret)
4530                         return ret;
4531
4532                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
4533         }
4534
4535         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
4536
4537         return 0;
4538 }
4539
4540 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
4541                                       struct drm_connector *connector)
4542 {
4543         const struct drm_connector_state *old_conn_state =
4544                 drm_atomic_get_old_connector_state(&state->base, connector);
4545         const struct intel_crtc_state *old_crtc_state;
4546         struct intel_crtc *crtc;
4547         u8 transcoders;
4548
4549         crtc = to_intel_crtc(old_conn_state->crtc);
4550         if (!crtc)
4551                 return 0;
4552
4553         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
4554
4555         if (!old_crtc_state->hw.active)
4556                 return 0;
4557
4558         transcoders = old_crtc_state->sync_mode_slaves_mask;
4559         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
4560                 transcoders |= BIT(old_crtc_state->master_transcoder);
4561
4562         return intel_modeset_affected_transcoders(state,
4563                                                   transcoders);
4564 }
4565
4566 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
4567                                            struct drm_atomic_state *_state)
4568 {
4569         struct drm_i915_private *dev_priv = to_i915(conn->dev);
4570         struct intel_atomic_state *state = to_intel_atomic_state(_state);
4571         int ret;
4572
4573         ret = intel_digital_connector_atomic_check(conn, &state->base);
4574         if (ret)
4575                 return ret;
4576
4577         /*
4578          * We don't enable port sync on BDW due to missing w/as and
4579          * due to not having adjusted the modeset sequence appropriately.
4580          */
4581         if (DISPLAY_VER(dev_priv) < 9)
4582                 return 0;
4583
4584         if (!intel_connector_needs_modeset(state, conn))
4585                 return 0;
4586
4587         if (conn->has_tile) {
4588                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
4589                 if (ret)
4590                         return ret;
4591         }
4592
4593         return intel_modeset_synced_crtcs(state, conn);
4594 }
4595
4596 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4597         .force = intel_dp_force,
4598         .fill_modes = drm_helper_probe_single_connector_modes,
4599         .atomic_get_property = intel_digital_connector_atomic_get_property,
4600         .atomic_set_property = intel_digital_connector_atomic_set_property,
4601         .late_register = intel_dp_connector_register,
4602         .early_unregister = intel_dp_connector_unregister,
4603         .destroy = intel_connector_destroy,
4604         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4605         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
4606 };
4607
4608 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4609         .detect_ctx = intel_dp_detect,
4610         .get_modes = intel_dp_get_modes,
4611         .mode_valid = intel_dp_mode_valid,
4612         .atomic_check = intel_dp_connector_atomic_check,
4613 };
4614
4615 enum irqreturn
4616 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
4617 {
4618         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
4619         struct intel_dp *intel_dp = &dig_port->dp;
4620
4621         if (dig_port->base.type == INTEL_OUTPUT_EDP &&
4622             (long_hpd || !intel_pps_have_power(intel_dp))) {
4623                 /*
4624                  * vdd off can generate a long/short pulse on eDP which
4625                  * would require vdd on to handle it, and thus we
4626                  * would end up in an endless cycle of
4627                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
4628                  */
4629                 drm_dbg_kms(&i915->drm,
4630                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
4631                             long_hpd ? "long" : "short",
4632                             dig_port->base.base.base.id,
4633                             dig_port->base.base.name);
4634                 return IRQ_HANDLED;
4635         }
4636
4637         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
4638                     dig_port->base.base.base.id,
4639                     dig_port->base.base.name,
4640                     long_hpd ? "long" : "short");
4641
4642         if (long_hpd) {
4643                 intel_dp->reset_link_params = true;
4644                 return IRQ_NONE;
4645         }
4646
4647         if (intel_dp->is_mst) {
4648                 if (!intel_dp_check_mst_status(intel_dp))
4649                         return IRQ_NONE;
4650         } else if (!intel_dp_short_pulse(intel_dp)) {
4651                 return IRQ_NONE;
4652         }
4653
4654         return IRQ_HANDLED;
4655 }
4656
4657 /* check the VBT to see whether the eDP is on another port */
4658 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
4659 {
4660         /*
4661          * eDP not supported on g4x. so bail out early just
4662          * for a bit extra safety in case the VBT is bonkers.
4663          */
4664         if (DISPLAY_VER(dev_priv) < 5)
4665                 return false;
4666
4667         if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
4668                 return true;
4669
4670         return intel_bios_is_port_edp(dev_priv, port);
4671 }
4672
4673 static void
4674 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4675 {
4676         struct drm_i915_private *dev_priv = to_i915(connector->dev);
4677         enum port port = dp_to_dig_port(intel_dp)->base.port;
4678
4679         if (!intel_dp_is_edp(intel_dp))
4680                 drm_connector_attach_dp_subconnector_property(connector);
4681
4682         if (!IS_G4X(dev_priv) && port != PORT_A)
4683                 intel_attach_force_audio_property(connector);
4684
4685         intel_attach_broadcast_rgb_property(connector);
4686         if (HAS_GMCH(dev_priv))
4687                 drm_connector_attach_max_bpc_property(connector, 6, 10);
4688         else if (DISPLAY_VER(dev_priv) >= 5)
4689                 drm_connector_attach_max_bpc_property(connector, 6, 12);
4690
4691         /* Register HDMI colorspace for case of lspcon */
4692         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4693                 drm_connector_attach_content_type_property(connector);
4694                 intel_attach_hdmi_colorspace_property(connector);
4695         } else {
4696                 intel_attach_dp_colorspace_property(connector);
4697         }
4698
4699         if (IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 11)
4700                 drm_object_attach_property(&connector->base,
4701                                            connector->dev->mode_config.hdr_output_metadata_property,
4702                                            0);
4703
4704         if (intel_dp_is_edp(intel_dp)) {
4705                 u32 allowed_scalers;
4706
4707                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
4708                 if (!HAS_GMCH(dev_priv))
4709                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
4710
4711                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
4712
4713                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
4714
4715         }
4716
4717         if (HAS_VRR(dev_priv))
4718                 drm_connector_attach_vrr_capable_property(connector);
4719 }
4720
4721 /**
4722  * intel_dp_set_drrs_state - program registers for RR switch to take effect
4723  * @dev_priv: i915 device
4724  * @crtc_state: a pointer to the active intel_crtc_state
4725  * @refresh_rate: RR to be programmed
4726  *
4727  * This function gets called when refresh rate (RR) has to be changed from
4728  * one frequency to another. Switches can be between high and low RR
4729  * supported by the panel or to any other RR based on media playback (in
4730  * this case, RR value needs to be passed from user space).
4731  *
4732  * The caller of this function needs to take a lock on dev_priv->drrs.
4733  */
4734 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
4735                                     const struct intel_crtc_state *crtc_state,
4736                                     int refresh_rate)
4737 {
4738         struct intel_dp *intel_dp = dev_priv->drrs.dp;
4739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4740         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
4741
4742         if (refresh_rate <= 0) {
4743                 drm_dbg_kms(&dev_priv->drm,
4744                             "Refresh rate should be positive non-zero.\n");
4745                 return;
4746         }
4747
4748         if (intel_dp == NULL) {
4749                 drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
4750                 return;
4751         }
4752
4753         if (!intel_crtc) {
4754                 drm_dbg_kms(&dev_priv->drm,
4755                             "DRRS: intel_crtc not initialized\n");
4756                 return;
4757         }
4758
4759         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
4760                 drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
4761                 return;
4762         }
4763
4764         if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) ==
4765                         refresh_rate)
4766                 index = DRRS_LOW_RR;
4767
4768         if (index == dev_priv->drrs.refresh_rate_type) {
4769                 drm_dbg_kms(&dev_priv->drm,
4770                             "DRRS requested for previously set RR...ignoring\n");
4771                 return;
4772         }
4773
4774         if (!crtc_state->hw.active) {
4775                 drm_dbg_kms(&dev_priv->drm,
4776                             "eDP encoder disabled. CRTC not Active\n");
4777                 return;
4778         }
4779
4780         if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
4781                 switch (index) {
4782                 case DRRS_HIGH_RR:
4783                         intel_dp_set_m_n(crtc_state, M1_N1);
4784                         break;
4785                 case DRRS_LOW_RR:
4786                         intel_dp_set_m_n(crtc_state, M2_N2);
4787                         break;
4788                 case DRRS_MAX_RR:
4789                 default:
4790                         drm_err(&dev_priv->drm,
4791                                 "Unsupported refreshrate type\n");
4792                 }
4793         } else if (DISPLAY_VER(dev_priv) > 6) {
4794                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
4795                 u32 val;
4796
4797                 val = intel_de_read(dev_priv, reg);
4798                 if (index > DRRS_HIGH_RR) {
4799                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4800                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
4801                         else
4802                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4803                 } else {
4804                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4805                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
4806                         else
4807                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4808                 }
4809                 intel_de_write(dev_priv, reg, val);
4810         }
4811
4812         dev_priv->drrs.refresh_rate_type = index;
4813
4814         drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
4815                     refresh_rate);
4816 }
4817
4818 static void
4819 intel_edp_drrs_enable_locked(struct intel_dp *intel_dp)
4820 {
4821         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4822
4823         dev_priv->drrs.busy_frontbuffer_bits = 0;
4824         dev_priv->drrs.dp = intel_dp;
4825 }
4826
4827 /**
4828  * intel_edp_drrs_enable - init drrs struct if supported
4829  * @intel_dp: DP struct
4830  * @crtc_state: A pointer to the active crtc state.
4831  *
4832  * Initializes frontbuffer_bits and drrs.dp
4833  */
4834 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
4835                            const struct intel_crtc_state *crtc_state)
4836 {
4837         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4838
4839         if (!crtc_state->has_drrs)
4840                 return;
4841
4842         drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
4843
4844         mutex_lock(&dev_priv->drrs.mutex);
4845
4846         if (dev_priv->drrs.dp) {
4847                 drm_warn(&dev_priv->drm, "DRRS already enabled\n");
4848                 goto unlock;
4849         }
4850
4851         intel_edp_drrs_enable_locked(intel_dp);
4852
4853 unlock:
4854         mutex_unlock(&dev_priv->drrs.mutex);
4855 }
4856
4857 static void
4858 intel_edp_drrs_disable_locked(struct intel_dp *intel_dp,
4859                               const struct intel_crtc_state *crtc_state)
4860 {
4861         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4862
4863         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
4864                 int refresh;
4865
4866                 refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
4867                 intel_dp_set_drrs_state(dev_priv, crtc_state, refresh);
4868         }
4869
4870         dev_priv->drrs.dp = NULL;
4871 }
4872
4873 /**
4874  * intel_edp_drrs_disable - Disable DRRS
4875  * @intel_dp: DP struct
4876  * @old_crtc_state: Pointer to old crtc_state.
4877  *
4878  */
4879 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
4880                             const struct intel_crtc_state *old_crtc_state)
4881 {
4882         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4883
4884         if (!old_crtc_state->has_drrs)
4885                 return;
4886
4887         mutex_lock(&dev_priv->drrs.mutex);
4888         if (!dev_priv->drrs.dp) {
4889                 mutex_unlock(&dev_priv->drrs.mutex);
4890                 return;
4891         }
4892
4893         intel_edp_drrs_disable_locked(intel_dp, old_crtc_state);
4894         mutex_unlock(&dev_priv->drrs.mutex);
4895
4896         cancel_delayed_work_sync(&dev_priv->drrs.work);
4897 }
4898
4899 /**
4900  * intel_edp_drrs_update - Update DRRS state
4901  * @intel_dp: Intel DP
4902  * @crtc_state: new CRTC state
4903  *
4904  * This function will update DRRS states, disabling or enabling DRRS when
4905  * executing fastsets. For full modeset, intel_edp_drrs_disable() and
4906  * intel_edp_drrs_enable() should be called instead.
4907  */
4908 void
4909 intel_edp_drrs_update(struct intel_dp *intel_dp,
4910                       const struct intel_crtc_state *crtc_state)
4911 {
4912         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4913
4914         if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
4915                 return;
4916
4917         mutex_lock(&dev_priv->drrs.mutex);
4918
4919         /* New state matches current one? */
4920         if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
4921                 goto unlock;
4922
4923         if (crtc_state->has_drrs)
4924                 intel_edp_drrs_enable_locked(intel_dp);
4925         else
4926                 intel_edp_drrs_disable_locked(intel_dp, crtc_state);
4927
4928 unlock:
4929         mutex_unlock(&dev_priv->drrs.mutex);
4930 }
4931
4932 static void intel_edp_drrs_downclock_work(struct work_struct *work)
4933 {
4934         struct drm_i915_private *dev_priv =
4935                 container_of(work, typeof(*dev_priv), drrs.work.work);
4936         struct intel_dp *intel_dp;
4937
4938         mutex_lock(&dev_priv->drrs.mutex);
4939
4940         intel_dp = dev_priv->drrs.dp;
4941
4942         if (!intel_dp)
4943                 goto unlock;
4944
4945         /*
4946          * The delayed work can race with an invalidate hence we need to
4947          * recheck.
4948          */
4949
4950         if (dev_priv->drrs.busy_frontbuffer_bits)
4951                 goto unlock;
4952
4953         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
4954                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
4955
4956                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
4957                         drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode));
4958         }
4959
4960 unlock:
4961         mutex_unlock(&dev_priv->drrs.mutex);
4962 }
4963
4964 /**
4965  * intel_edp_drrs_invalidate - Disable Idleness DRRS
4966  * @dev_priv: i915 device
4967  * @frontbuffer_bits: frontbuffer plane tracking bits
4968  *
4969  * This function gets called everytime rendering on the given planes start.
4970  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
4971  *
4972  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
4973  */
4974 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
4975                                unsigned int frontbuffer_bits)
4976 {
4977         struct intel_dp *intel_dp;
4978         struct drm_crtc *crtc;
4979         enum pipe pipe;
4980
4981         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
4982                 return;
4983
4984         cancel_delayed_work(&dev_priv->drrs.work);
4985
4986         mutex_lock(&dev_priv->drrs.mutex);
4987
4988         intel_dp = dev_priv->drrs.dp;
4989         if (!intel_dp) {
4990                 mutex_unlock(&dev_priv->drrs.mutex);
4991                 return;
4992         }
4993
4994         crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
4995         pipe = to_intel_crtc(crtc)->pipe;
4996
4997         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
4998         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
4999
5000         /* invalidate means busy screen hence upclock */
5001         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5002                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5003                                         drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
5004
5005         mutex_unlock(&dev_priv->drrs.mutex);
5006 }
5007
5008 /**
5009  * intel_edp_drrs_flush - Restart Idleness DRRS
5010  * @dev_priv: i915 device
5011  * @frontbuffer_bits: frontbuffer plane tracking bits
5012  *
5013  * This function gets called every time rendering on the given planes has
5014  * completed or flip on a crtc is completed. So DRRS should be upclocked
5015  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5016  * if no other planes are dirty.
5017  *
5018  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5019  */
5020 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5021                           unsigned int frontbuffer_bits)
5022 {
5023         struct intel_dp *intel_dp;
5024         struct drm_crtc *crtc;
5025         enum pipe pipe;
5026
5027         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5028                 return;
5029
5030         cancel_delayed_work(&dev_priv->drrs.work);
5031
5032         mutex_lock(&dev_priv->drrs.mutex);
5033
5034         intel_dp = dev_priv->drrs.dp;
5035         if (!intel_dp) {
5036                 mutex_unlock(&dev_priv->drrs.mutex);
5037                 return;
5038         }
5039
5040         crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5041         pipe = to_intel_crtc(crtc)->pipe;
5042
5043         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5044         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5045
5046         /* flush means busy screen hence upclock */
5047         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5048                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5049                                         drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
5050
5051         /*
5052          * flush also means no more activity hence schedule downclock, if all
5053          * other fbs are quiescent too
5054          */
5055         if (!dev_priv->drrs.busy_frontbuffer_bits)
5056                 schedule_delayed_work(&dev_priv->drrs.work,
5057                                 msecs_to_jiffies(1000));
5058         mutex_unlock(&dev_priv->drrs.mutex);
5059 }
5060
5061 /**
5062  * DOC: Display Refresh Rate Switching (DRRS)
5063  *
5064  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5065  * which enables swtching between low and high refresh rates,
5066  * dynamically, based on the usage scenario. This feature is applicable
5067  * for internal panels.
5068  *
5069  * Indication that the panel supports DRRS is given by the panel EDID, which
5070  * would list multiple refresh rates for one resolution.
5071  *
5072  * DRRS is of 2 types - static and seamless.
5073  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5074  * (may appear as a blink on screen) and is used in dock-undock scenario.
5075  * Seamless DRRS involves changing RR without any visual effect to the user
5076  * and can be used during normal system usage. This is done by programming
5077  * certain registers.
5078  *
5079  * Support for static/seamless DRRS may be indicated in the VBT based on
5080  * inputs from the panel spec.
5081  *
5082  * DRRS saves power by switching to low RR based on usage scenarios.
5083  *
5084  * The implementation is based on frontbuffer tracking implementation.  When
5085  * there is a disturbance on the screen triggered by user activity or a periodic
5086  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
5087  * no movement on screen, after a timeout of 1 second, a switch to low RR is
5088  * made.
5089  *
5090  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5091  * and intel_edp_drrs_flush() are called.
5092  *
5093  * DRRS can be further extended to support other internal panels and also
5094  * the scenario of video playback wherein RR is set based on the rate
5095  * requested by userspace.
5096  */
5097
5098 /**
5099  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5100  * @connector: eDP connector
5101  * @fixed_mode: preferred mode of panel
5102  *
5103  * This function is  called only once at driver load to initialize basic
5104  * DRRS stuff.
5105  *
5106  * Returns:
5107  * Downclock mode if panel supports it, else return NULL.
5108  * DRRS support is determined by the presence of downclock mode (apart
5109  * from VBT setting).
5110  */
5111 static struct drm_display_mode *
5112 intel_dp_drrs_init(struct intel_connector *connector,
5113                    struct drm_display_mode *fixed_mode)
5114 {
5115         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
5116         struct drm_display_mode *downclock_mode = NULL;
5117
5118         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5119         mutex_init(&dev_priv->drrs.mutex);
5120
5121         if (DISPLAY_VER(dev_priv) <= 6) {
5122                 drm_dbg_kms(&dev_priv->drm,
5123                             "DRRS supported for Gen7 and above\n");
5124                 return NULL;
5125         }
5126
5127         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5128                 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
5129                 return NULL;
5130         }
5131
5132         downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
5133         if (!downclock_mode) {
5134                 drm_dbg_kms(&dev_priv->drm,
5135                             "Downclock mode is not found. DRRS not supported\n");
5136                 return NULL;
5137         }
5138
5139         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5140
5141         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5142         drm_dbg_kms(&dev_priv->drm,
5143                     "seamless DRRS supported for eDP panel.\n");
5144         return downclock_mode;
5145 }
5146
5147 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5148                                      struct intel_connector *intel_connector)
5149 {
5150         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5151         struct drm_device *dev = &dev_priv->drm;
5152         struct drm_connector *connector = &intel_connector->base;
5153         struct drm_display_mode *fixed_mode = NULL;
5154         struct drm_display_mode *downclock_mode = NULL;
5155         bool has_dpcd;
5156         enum pipe pipe = INVALID_PIPE;
5157         struct edid *edid;
5158
5159         if (!intel_dp_is_edp(intel_dp))
5160                 return true;
5161
5162         /*
5163          * On IBX/CPT we may get here with LVDS already registered. Since the
5164          * driver uses the only internal power sequencer available for both
5165          * eDP and LVDS bail out early in this case to prevent interfering
5166          * with an already powered-on LVDS power sequencer.
5167          */
5168         if (intel_get_lvds_encoder(dev_priv)) {
5169                 drm_WARN_ON(dev,
5170                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5171                 drm_info(&dev_priv->drm,
5172                          "LVDS was detected, not registering eDP\n");
5173
5174                 return false;
5175         }
5176
5177         intel_pps_init(intel_dp);
5178
5179         /* Cache DPCD and EDID for edp. */
5180         has_dpcd = intel_edp_init_dpcd(intel_dp);
5181
5182         if (!has_dpcd) {
5183                 /* if this fails, presume the device is a ghost */
5184                 drm_info(&dev_priv->drm,
5185                          "failed to retrieve link info, disabling eDP\n");
5186                 goto out_vdd_off;
5187         }
5188
5189         mutex_lock(&dev->mode_config.mutex);
5190         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5191         if (edid) {
5192                 if (drm_add_edid_modes(connector, edid)) {
5193                         drm_connector_update_edid_property(connector, edid);
5194                 } else {
5195                         kfree(edid);
5196                         edid = ERR_PTR(-EINVAL);
5197                 }
5198         } else {
5199                 edid = ERR_PTR(-ENOENT);
5200         }
5201         intel_connector->edid = edid;
5202
5203         fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
5204         if (fixed_mode)
5205                 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
5206
5207         /* multiply the mode clock and horizontal timings for MSO */
5208         intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
5209         intel_edp_mso_mode_fixup(intel_connector, downclock_mode);
5210
5211         /* fallback to VBT if available for eDP */
5212         if (!fixed_mode)
5213                 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
5214         mutex_unlock(&dev->mode_config.mutex);
5215
5216         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5217                 /*
5218                  * Figure out the current pipe for the initial backlight setup.
5219                  * If the current pipe isn't valid, try the PPS pipe, and if that
5220                  * fails just assume pipe A.
5221                  */
5222                 pipe = vlv_active_pipe(intel_dp);
5223
5224                 if (pipe != PIPE_A && pipe != PIPE_B)
5225                         pipe = intel_dp->pps.pps_pipe;
5226
5227                 if (pipe != PIPE_A && pipe != PIPE_B)
5228                         pipe = PIPE_A;
5229
5230                 drm_dbg_kms(&dev_priv->drm,
5231                             "using pipe %c for initial backlight setup\n",
5232                             pipe_name(pipe));
5233         }
5234
5235         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5236         intel_connector->panel.backlight.power = intel_pps_backlight_power;
5237         intel_panel_setup_backlight(connector, pipe);
5238
5239         if (fixed_mode) {
5240                 drm_connector_set_panel_orientation_with_quirk(connector,
5241                                 dev_priv->vbt.orientation,
5242                                 fixed_mode->hdisplay, fixed_mode->vdisplay);
5243         }
5244
5245         return true;
5246
5247 out_vdd_off:
5248         intel_pps_vdd_off_sync(intel_dp);
5249
5250         return false;
5251 }
5252
5253 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5254 {
5255         struct intel_connector *intel_connector;
5256         struct drm_connector *connector;
5257
5258         intel_connector = container_of(work, typeof(*intel_connector),
5259                                        modeset_retry_work);
5260         connector = &intel_connector->base;
5261         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
5262                       connector->name);
5263
5264         /* Grab the locks before changing connector property*/
5265         mutex_lock(&connector->dev->mode_config.mutex);
5266         /* Set connector link status to BAD and send a Uevent to notify
5267          * userspace to do a modeset.
5268          */
5269         drm_connector_set_link_status_property(connector,
5270                                                DRM_MODE_LINK_STATUS_BAD);
5271         mutex_unlock(&connector->dev->mode_config.mutex);
5272         /* Send Hotplug uevent so userspace can reprobe */
5273         drm_kms_helper_hotplug_event(connector->dev);
5274 }
5275
5276 bool
5277 intel_dp_init_connector(struct intel_digital_port *dig_port,
5278                         struct intel_connector *intel_connector)
5279 {
5280         struct drm_connector *connector = &intel_connector->base;
5281         struct intel_dp *intel_dp = &dig_port->dp;
5282         struct intel_encoder *intel_encoder = &dig_port->base;
5283         struct drm_device *dev = intel_encoder->base.dev;
5284         struct drm_i915_private *dev_priv = to_i915(dev);
5285         enum port port = intel_encoder->port;
5286         enum phy phy = intel_port_to_phy(dev_priv, port);
5287         int type;
5288
5289         /* Initialize the work for modeset in case of link train failure */
5290         INIT_WORK(&intel_connector->modeset_retry_work,
5291                   intel_dp_modeset_retry_work_fn);
5292
5293         if (drm_WARN(dev, dig_port->max_lanes < 1,
5294                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
5295                      dig_port->max_lanes, intel_encoder->base.base.id,
5296                      intel_encoder->base.name))
5297                 return false;
5298
5299         intel_dp_set_source_rates(intel_dp);
5300
5301         intel_dp->reset_link_params = true;
5302         intel_dp->pps.pps_pipe = INVALID_PIPE;
5303         intel_dp->pps.active_pipe = INVALID_PIPE;
5304
5305         /* Preserve the current hw state. */
5306         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
5307         intel_dp->attached_connector = intel_connector;
5308
5309         if (intel_dp_is_port_edp(dev_priv, port)) {
5310                 /*
5311                  * Currently we don't support eDP on TypeC ports, although in
5312                  * theory it could work on TypeC legacy ports.
5313                  */
5314                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
5315                 type = DRM_MODE_CONNECTOR_eDP;
5316         } else {
5317                 type = DRM_MODE_CONNECTOR_DisplayPort;
5318         }
5319
5320         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5321                 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
5322
5323         /*
5324          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5325          * for DP the encoder type can be set by the caller to
5326          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5327          */
5328         if (type == DRM_MODE_CONNECTOR_eDP)
5329                 intel_encoder->type = INTEL_OUTPUT_EDP;
5330
5331         /* eDP only on port B and/or C on vlv/chv */
5332         if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
5333                               IS_CHERRYVIEW(dev_priv)) &&
5334                         intel_dp_is_edp(intel_dp) &&
5335                         port != PORT_B && port != PORT_C))
5336                 return false;
5337
5338         drm_dbg_kms(&dev_priv->drm,
5339                     "Adding %s connector on [ENCODER:%d:%s]\n",
5340                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5341                     intel_encoder->base.base.id, intel_encoder->base.name);
5342
5343         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5344         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5345
5346         if (!HAS_GMCH(dev_priv))
5347                 connector->interlace_allowed = true;
5348         connector->doublescan_allowed = 0;
5349
5350         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
5351
5352         intel_dp_aux_init(intel_dp);
5353
5354         intel_connector_attach_encoder(intel_connector, intel_encoder);
5355
5356         if (HAS_DDI(dev_priv))
5357                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5358         else
5359                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5360
5361         /* init MST on ports that can support it */
5362         intel_dp_mst_encoder_init(dig_port,
5363                                   intel_connector->base.base.id);
5364
5365         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5366                 intel_dp_aux_fini(intel_dp);
5367                 intel_dp_mst_encoder_cleanup(dig_port);
5368                 goto fail;
5369         }
5370
5371         intel_dp_add_properties(intel_dp, connector);
5372
5373         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
5374                 int ret = intel_dp_hdcp_init(dig_port, intel_connector);
5375                 if (ret)
5376                         drm_dbg_kms(&dev_priv->drm,
5377                                     "HDCP init failed, skipping.\n");
5378         }
5379
5380         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5381          * 0xd.  Failure to do so will result in spurious interrupts being
5382          * generated on the port when a cable is not attached.
5383          */
5384         if (IS_G45(dev_priv)) {
5385                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
5386                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
5387                                (temp & ~0xf) | 0xd);
5388         }
5389
5390         intel_dp->frl.is_trained = false;
5391         intel_dp->frl.trained_rate_gbps = 0;
5392
5393         intel_psr_init(intel_dp);
5394
5395         return true;
5396
5397 fail:
5398         drm_connector_cleanup(connector);
5399
5400         return false;
5401 }
5402
5403 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
5404 {
5405         struct intel_encoder *encoder;
5406
5407         if (!HAS_DISPLAY(dev_priv))
5408                 return;
5409
5410         for_each_intel_encoder(&dev_priv->drm, encoder) {
5411                 struct intel_dp *intel_dp;
5412
5413                 if (encoder->type != INTEL_OUTPUT_DDI)
5414                         continue;
5415
5416                 intel_dp = enc_to_intel_dp(encoder);
5417
5418                 if (!intel_dp->can_mst)
5419                         continue;
5420
5421                 if (intel_dp->is_mst)
5422                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
5423         }
5424 }
5425
5426 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
5427 {
5428         struct intel_encoder *encoder;
5429
5430         if (!HAS_DISPLAY(dev_priv))
5431                 return;
5432
5433         for_each_intel_encoder(&dev_priv->drm, encoder) {
5434                 struct intel_dp *intel_dp;
5435                 int ret;
5436
5437                 if (encoder->type != INTEL_OUTPUT_DDI)
5438                         continue;
5439
5440                 intel_dp = enc_to_intel_dp(encoder);
5441
5442                 if (!intel_dp->can_mst)
5443                         continue;
5444
5445                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
5446                                                      true);
5447                 if (ret) {
5448                         intel_dp->is_mst = false;
5449                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5450                                                         false);
5451                 }
5452         }
5453 }