drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/slab.h>
  32 #include <linux/string_helpers.h>
  33 #include <linux/timekeeping.h>
  34 #include <linux/types.h>
  35
  36 #include <asm/byteorder.h>
  37
  38 #include <drm/display/drm_dp_helper.h>
  39 #include <drm/display/drm_dsc_helper.h>
  40 #include <drm/display/drm_hdmi_helper.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_crtc.h>
  43 #include <drm/drm_edid.h>
  44 #include <drm/drm_probe_helper.h>
  45
  46 #include "g4x_dp.h"
  47 #include "i915_drv.h"
  48 #include "i915_irq.h"
  49 #include "i915_reg.h"
  50 #include "intel_atomic.h"
  51 #include "intel_audio.h"
  52 #include "intel_backlight.h"
  53 #include "intel_combo_phy_regs.h"
  54 #include "intel_connector.h"
  55 #include "intel_crtc.h"
  56 #include "intel_cx0_phy.h"
  57 #include "intel_ddi.h"
  58 #include "intel_de.h"
  59 #include "intel_display_types.h"
  60 #include "intel_dp.h"
  61 #include "intel_dp_aux.h"
  62 #include "intel_dp_hdcp.h"
  63 #include "intel_dp_link_training.h"
  64 #include "intel_dp_mst.h"
  65 #include "intel_dpio_phy.h"
  66 #include "intel_dpll.h"
  67 #include "intel_fifo_underrun.h"
  68 #include "intel_hdcp.h"
  69 #include "intel_hdmi.h"
  70 #include "intel_hotplug.h"
  71 #include "intel_hotplug_irq.h"
  72 #include "intel_lspcon.h"
  73 #include "intel_lvds.h"
  74 #include "intel_panel.h"
  75 #include "intel_pch_display.h"
  76 #include "intel_pps.h"
  77 #include "intel_psr.h"
  78 #include "intel_tc.h"
  79 #include "intel_vdsc.h"
  80 #include "intel_vrr.h"
  81 #include "intel_crtc_state_dump.h"
  82
  83 /* DP DSC throughput values used for slice count calculations KPixels/s */
  84 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  85 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  86 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  87
  88 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  89 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  90
  91 /* Compliance test status bits  */
  92 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  93 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  94 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  95 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  96
  97
  98 /* Constants for DP DSC configurations */
  99 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 100
 101 /* With Single pipe configuration, HW is capable of supporting maximum
 102  * of 4 slices per line.
 103  */
 104 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 105
 106 /**
 107  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 108  * @intel_dp: DP struct
 109  *
 110  * If a CPU or PCH DP output is attached to an eDP panel, this function
 111  * will return true, and false otherwise.
 112  *
 113  * This function is not safe to use prior to encoder type being set.
 114  */
 115 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 116 {
 117         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 118
 119         return dig_port->base.type == INTEL_OUTPUT_EDP;
 120 }
 121
 122 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 123
 124 /* Is link rate UHBR and thus 128b/132b? */
 125 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
 126 {
 127         return crtc_state->port_clock >= 1000000;
 128 }
 129
 130 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
 131 {
 132         intel_dp->sink_rates[0] = 162000;
 133         intel_dp->num_sink_rates = 1;
 134 }
 135
 136 /* update sink rates from dpcd */
 137 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
 138 {
 139         static const int dp_rates[] = {
 140                 162000, 270000, 540000, 810000
 141         };
 142         int i, max_rate;
 143         int max_lttpr_rate;
 144
 145         if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 146                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 147                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 148
 149                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 150                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 151
 152                 return;
 153         }
 154
 155         /*
 156          * Sink rates for 8b/10b.
 157          */
 158         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 159         max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 160         if (max_lttpr_rate)
 161                 max_rate = min(max_rate, max_lttpr_rate);
 162
 163         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 164                 if (dp_rates[i] > max_rate)
 165                         break;
 166                 intel_dp->sink_rates[i] = dp_rates[i];
 167         }
 168
 169         /*
 170          * Sink rates for 128b/132b. If set, sink should support all 8b/10b
 171          * rates and 10 Gbps.
 172          */
 173         if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
 174                 u8 uhbr_rates = 0;
 175
 176                 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
 177
 178                 drm_dp_dpcd_readb(&intel_dp->aux,
 179                                   DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
 180
 181                 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
 182                         /* We have a repeater */
 183                         if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
 184                             intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
 185                                                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
 186                             DP_PHY_REPEATER_128B132B_SUPPORTED) {
 187                                 /* Repeater supports 128b/132b, valid UHBR rates */
 188                                 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
 189                                                                           DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
 190                         } else {
 191                                 /* Does not support 128b/132b */
 192                                 uhbr_rates = 0;
 193                         }
 194                 }
 195
 196                 if (uhbr_rates & DP_UHBR10)
 197                         intel_dp->sink_rates[i++] = 1000000;
 198                 if (uhbr_rates & DP_UHBR13_5)
 199                         intel_dp->sink_rates[i++] = 1350000;
 200                 if (uhbr_rates & DP_UHBR20)
 201                         intel_dp->sink_rates[i++] = 2000000;
 202         }
 203
 204         intel_dp->num_sink_rates = i;
 205 }
 206
 207 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 208 {
 209         struct intel_connector *connector = intel_dp->attached_connector;
 210         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 211         struct intel_encoder *encoder = &intel_dig_port->base;
 212
 213         intel_dp_set_dpcd_sink_rates(intel_dp);
 214
 215         if (intel_dp->num_sink_rates)
 216                 return;
 217
 218         drm_err(&dp_to_i915(intel_dp)->drm,
 219                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
 220                 connector->base.base.id, connector->base.name,
 221                 encoder->base.base.id, encoder->base.name);
 222
 223         intel_dp_set_default_sink_rates(intel_dp);
 224 }
 225
 226 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
 227 {
 228         intel_dp->max_sink_lane_count = 1;
 229 }
 230
 231 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
 232 {
 233         struct intel_connector *connector = intel_dp->attached_connector;
 234         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 235         struct intel_encoder *encoder = &intel_dig_port->base;
 236
 237         intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 238
 239         switch (intel_dp->max_sink_lane_count) {
 240         case 1:
 241         case 2:
 242         case 4:
 243                 return;
 244         }
 245
 246         drm_err(&dp_to_i915(intel_dp)->drm,
 247                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
 248                 connector->base.base.id, connector->base.name,
 249                 encoder->base.base.id, encoder->base.name,
 250                 intel_dp->max_sink_lane_count);
 251
 252         intel_dp_set_default_max_sink_lane_count(intel_dp);
 253 }
 254
 255 /* Get length of rates array potentially limited by max_rate. */
 256 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 257 {
 258         int i;
 259
 260         /* Limit results by potentially reduced max rate */
 261         for (i = 0; i < len; i++) {
 262                 if (rates[len - i - 1] <= max_rate)
 263                         return len - i;
 264         }
 265
 266         return 0;
 267 }
 268
 269 /* Get length of common rates array potentially limited by max_rate. */
 270 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 271                                           int max_rate)
 272 {
 273         return intel_dp_rate_limit_len(intel_dp->common_rates,
 274                                        intel_dp->num_common_rates, max_rate);
 275 }
 276
 277 static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
 278 {
 279         if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
 280                         index < 0 || index >= intel_dp->num_common_rates))
 281                 return 162000;
 282
 283         return intel_dp->common_rates[index];
 284 }
 285
 286 /* Theoretical max between source and sink */
 287 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 288 {
 289         return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
 290 }
 291
 292 static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
 293 {
 294         int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata);
 295         int max_lanes = dig_port->max_lanes;
 296
 297         if (vbt_max_lanes)
 298                 max_lanes = min(max_lanes, vbt_max_lanes);
 299
 300         return max_lanes;
 301 }
 302
 303 /* Theoretical max between source and sink */
 304 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 305 {
 306         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 307         int source_max = intel_dp_max_source_lane_count(dig_port);
 308         int sink_max = intel_dp->max_sink_lane_count;
 309         int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
 310         int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 311
 312         if (lttpr_max)
 313                 sink_max = min(sink_max, lttpr_max);
 314
 315         return min3(source_max, sink_max, fia_max);
 316 }
 317
 318 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 319 {
 320         switch (intel_dp->max_link_lane_count) {
 321         case 1:
 322         case 2:
 323         case 4:
 324                 return intel_dp->max_link_lane_count;
 325         default:
 326                 MISSING_CASE(intel_dp->max_link_lane_count);
 327                 return 1;
 328         }
 329 }
 330
 331 /*
 332  * The required data bandwidth for a mode with given pixel clock and bpp. This
 333  * is the required net bandwidth independent of the data bandwidth efficiency.
 334  */
 335 int
 336 intel_dp_link_required(int pixel_clock, int bpp)
 337 {
 338         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 339         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 340 }
 341
 342 /*
 343  * Given a link rate and lanes, get the data bandwidth.
 344  *
 345  * Data bandwidth is the actual payload rate, which depends on the data
 346  * bandwidth efficiency and the link rate.
 347  *
 348  * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth efficiency
 349  * is 80%. For example, for a 1.62 Gbps link, 1.62*10^9 bps * 0.80 * (1/8) =
 350  * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by
 351  * coincidence, the port clock in kHz matches the data bandwidth in kBps, and
 352  * they equal the link bit rate in Gbps multiplied by 100000. (Note that this no
 353  * longer holds for data bandwidth as soon as FEC or MST is taken into account!)
 354  *
 355  * For 128b/132b channel encoding, the data bandwidth efficiency is 96.71%. For
 356  * example, for a 10 Gbps link, 10*10^9 bps * 0.9671 * (1/8) = 1208875
 357  * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value 1000000
 358  * does not match the symbol clock, the port clock (not even if you think in
 359  * terms of a byte clock), nor the data bandwidth. It only matches the link bit
 360  * rate in units of 10000 bps.
 361  */
 362 int
 363 intel_dp_max_data_rate(int max_link_rate, int max_lanes)
 364 {
 365         if (max_link_rate >= 1000000) {
 366                 /*
 367                  * UHBR rates always use 128b/132b channel encoding, and have
 368                  * 97.71% data bandwidth efficiency. Consider max_link_rate the
 369                  * link bit rate in units of 10000 bps.
 370                  */
 371                 int max_link_rate_kbps = max_link_rate * 10;
 372
 373                 max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(max_link_rate_kbps, 9671), 10000);
 374                 max_link_rate = max_link_rate_kbps / 8;
 375         }
 376
 377         /*
 378          * Lower than UHBR rates always use 8b/10b channel encoding, and have
 379          * 80% data bandwidth efficiency for SST non-FEC. However, this turns
 380          * out to be a nop by coincidence, and can be skipped:
 381          *
 382          *      int max_link_rate_kbps = max_link_rate * 10;
 383          *      max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(max_link_rate_kbps * 8, 10);
 384          *      max_link_rate = max_link_rate_kbps / 8;
 385          */
 386
 387         return max_link_rate * max_lanes;
 388 }
 389
 390 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 391 {
 392         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 393         struct intel_encoder *encoder = &intel_dig_port->base;
 394         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 395
 396         return DISPLAY_VER(dev_priv) >= 12 ||
 397                 (DISPLAY_VER(dev_priv) == 11 &&
 398                  encoder->port != PORT_A);
 399 }
 400
 401 static int dg2_max_source_rate(struct intel_dp *intel_dp)
 402 {
 403         return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
 404 }
 405
 406 static int icl_max_source_rate(struct intel_dp *intel_dp)
 407 {
 408         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 409         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 410         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 411
 412         if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))
 413                 return 540000;
 414
 415         return 810000;
 416 }
 417
 418 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 419 {
 420         if (intel_dp_is_edp(intel_dp))
 421                 return 540000;
 422
 423         return 810000;
 424 }
 425
 426 static int mtl_max_source_rate(struct intel_dp *intel_dp)
 427 {
 428         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 429         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 430         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 431
 432         if (intel_is_c10phy(i915, phy))
 433                 return intel_dp_is_edp(intel_dp) ? 675000 : 810000;
 434
 435         return 2000000;
 436 }
 437
 438 static int vbt_max_link_rate(struct intel_dp *intel_dp)
 439 {
 440         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 441         int max_rate;
 442
 443         max_rate = intel_bios_dp_max_link_rate(encoder->devdata);
 444
 445         if (intel_dp_is_edp(intel_dp)) {
 446                 struct intel_connector *connector = intel_dp->attached_connector;
 447                 int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
 448
 449                 if (max_rate && edp_max_rate)
 450                         max_rate = min(max_rate, edp_max_rate);
 451                 else if (edp_max_rate)
 452                         max_rate = edp_max_rate;
 453         }
 454
 455         return max_rate;
 456 }
 457
 458 static void
 459 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 460 {
 461         /* The values must be in increasing order */
 462         static const int mtl_rates[] = {
 463                 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
 464                 810000, 1000000, 1350000, 2000000,
 465         };
 466         static const int icl_rates[] = {
 467                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
 468                 1000000, 1350000,
 469         };
 470         static const int bxt_rates[] = {
 471                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 472         };
 473         static const int skl_rates[] = {
 474                 162000, 216000, 270000, 324000, 432000, 540000
 475         };
 476         static const int hsw_rates[] = {
 477                 162000, 270000, 540000
 478         };
 479         static const int g4x_rates[] = {
 480                 162000, 270000
 481         };
 482         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 483         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 484         const int *source_rates;
 485         int size, max_rate = 0, vbt_max_rate;
 486
 487         /* This should only be done once */
 488         drm_WARN_ON(&dev_priv->drm,
 489                     intel_dp->source_rates || intel_dp->num_source_rates);
 490
 491         if (DISPLAY_VER(dev_priv) >= 14) {
 492                 source_rates = mtl_rates;
 493                 size = ARRAY_SIZE(mtl_rates);
 494                 max_rate = mtl_max_source_rate(intel_dp);
 495         } else if (DISPLAY_VER(dev_priv) >= 11) {
 496                 source_rates = icl_rates;
 497                 size = ARRAY_SIZE(icl_rates);
 498                 if (IS_DG2(dev_priv))
 499                         max_rate = dg2_max_source_rate(intel_dp);
 500                 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 501                          IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 502                         max_rate = 810000;
 503                 else if (IS_JSL_EHL(dev_priv))
 504                         max_rate = ehl_max_source_rate(intel_dp);
 505                 else
 506                         max_rate = icl_max_source_rate(intel_dp);
 507         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 508                 source_rates = bxt_rates;
 509                 size = ARRAY_SIZE(bxt_rates);
 510         } else if (DISPLAY_VER(dev_priv) == 9) {
 511                 source_rates = skl_rates;
 512                 size = ARRAY_SIZE(skl_rates);
 513         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 514                    IS_BROADWELL(dev_priv)) {
 515                 source_rates = hsw_rates;
 516                 size = ARRAY_SIZE(hsw_rates);
 517         } else {
 518                 source_rates = g4x_rates;
 519                 size = ARRAY_SIZE(g4x_rates);
 520         }
 521
 522         vbt_max_rate = vbt_max_link_rate(intel_dp);
 523         if (max_rate && vbt_max_rate)
 524                 max_rate = min(max_rate, vbt_max_rate);
 525         else if (vbt_max_rate)
 526                 max_rate = vbt_max_rate;
 527
 528         if (max_rate)
 529                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 530
 531         intel_dp->source_rates = source_rates;
 532         intel_dp->num_source_rates = size;
 533 }
 534
 535 static int intersect_rates(const int *source_rates, int source_len,
 536                            const int *sink_rates, int sink_len,
 537                            int *common_rates)
 538 {
 539         int i = 0, j = 0, k = 0;
 540
 541         while (i < source_len && j < sink_len) {
 542                 if (source_rates[i] == sink_rates[j]) {
 543                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 544                                 return k;
 545                         common_rates[k] = source_rates[i];
 546                         ++k;
 547                         ++i;
 548                         ++j;
 549                 } else if (source_rates[i] < sink_rates[j]) {
 550                         ++i;
 551                 } else {
 552                         ++j;
 553                 }
 554         }
 555         return k;
 556 }
 557
 558 /* return index of rate in rates array, or -1 if not found */
 559 static int intel_dp_rate_index(const int *rates, int len, int rate)
 560 {
 561         int i;
 562
 563         for (i = 0; i < len; i++)
 564                 if (rate == rates[i])
 565                         return i;
 566
 567         return -1;
 568 }
 569
 570 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 571 {
 572         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 573
 574         drm_WARN_ON(&i915->drm,
 575                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 576
 577         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 578                                                      intel_dp->num_source_rates,
 579                                                      intel_dp->sink_rates,
 580                                                      intel_dp->num_sink_rates,
 581                                                      intel_dp->common_rates);
 582
 583         /* Paranoia, there should always be something in common. */
 584         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 585                 intel_dp->common_rates[0] = 162000;
 586                 intel_dp->num_common_rates = 1;
 587         }
 588 }
 589
 590 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 591                                        u8 lane_count)
 592 {
 593         /*
 594          * FIXME: we need to synchronize the current link parameters with
 595          * hardware readout. Currently fast link training doesn't work on
 596          * boot-up.
 597          */
 598         if (link_rate == 0 ||
 599             link_rate > intel_dp->max_link_rate)
 600                 return false;
 601
 602         if (lane_count == 0 ||
 603             lane_count > intel_dp_max_lane_count(intel_dp))
 604                 return false;
 605
 606         return true;
 607 }
 608
 609 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 610                                                      int link_rate,
 611                                                      u8 lane_count)
 612 {
 613         /* FIXME figure out what we actually want here */
 614         const struct drm_display_mode *fixed_mode =
 615                 intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
 616         int mode_rate, max_rate;
 617
 618         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 619         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 620         if (mode_rate > max_rate)
 621                 return false;
 622
 623         return true;
 624 }
 625
 626 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 627                                             int link_rate, u8 lane_count)
 628 {
 629         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 630         int index;
 631
 632         /*
 633          * TODO: Enable fallback on MST links once MST link compute can handle
 634          * the fallback params.
 635          */
 636         if (intel_dp->is_mst) {
 637                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 638                 return -1;
 639         }
 640
 641         if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
 642                 drm_dbg_kms(&i915->drm,
 643                             "Retrying Link training for eDP with max parameters\n");
 644                 intel_dp->use_max_params = true;
 645                 return 0;
 646         }
 647
 648         index = intel_dp_rate_index(intel_dp->common_rates,
 649                                     intel_dp->num_common_rates,
 650                                     link_rate);
 651         if (index > 0) {
 652                 if (intel_dp_is_edp(intel_dp) &&
 653                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 654                                                               intel_dp_common_rate(intel_dp, index - 1),
 655                                                               lane_count)) {
 656                         drm_dbg_kms(&i915->drm,
 657                                     "Retrying Link training for eDP with same parameters\n");
 658                         return 0;
 659                 }
 660                 intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1);
 661                 intel_dp->max_link_lane_count = lane_count;
 662         } else if (lane_count > 1) {
 663                 if (intel_dp_is_edp(intel_dp) &&
 664                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 665                                                               intel_dp_max_common_rate(intel_dp),
 666                                                               lane_count >> 1)) {
 667                         drm_dbg_kms(&i915->drm,
 668                                     "Retrying Link training for eDP with same parameters\n");
 669                         return 0;
 670                 }
 671                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 672                 intel_dp->max_link_lane_count = lane_count >> 1;
 673         } else {
 674                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 675                 return -1;
 676         }
 677
 678         return 0;
 679 }
 680
 681 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 682 {
 683         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 684                        DP_DSC_FEC_OVERHEAD_FACTOR);
 685 }
 686
 687 static int
 688 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 689 {
 690         if (DISPLAY_VER(i915) >= 13)
 691                 return 17280 * 8;
 692         else if (DISPLAY_VER(i915) >= 11)
 693                 return 7680 * 8;
 694         else
 695                 return 6144 * 8;
 696 }
 697
 698 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp)
 699 {
 700         u32 bits_per_pixel = bpp;
 701         int i;
 702
 703         /* Error out if the max bpp is less than smallest allowed valid bpp */
 704         if (bits_per_pixel < valid_dsc_bpp[0]) {
 705                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 706                             bits_per_pixel, valid_dsc_bpp[0]);
 707                 return 0;
 708         }
 709
 710         /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
 711         if (DISPLAY_VER(i915) >= 13) {
 712                 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
 713
 714                 /*
 715                  * According to BSpec, 27 is the max DSC output bpp,
 716                  * 8 is the min DSC output bpp.
 717                  * While we can still clamp higher bpp values to 27, saving bandwidth,
 718                  * if it is required to oompress up to bpp < 8, means we can't do
 719                  * that and probably means we can't fit the required mode, even with
 720                  * DSC enabled.
 721                  */
 722                 if (bits_per_pixel < 8) {
 723                         drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min 8\n",
 724                                     bits_per_pixel);
 725                         return 0;
 726                 }
 727                 bits_per_pixel = min_t(u32, bits_per_pixel, 27);
 728         } else {
 729                 /* Find the nearest match in the array of known BPPs from VESA */
 730                 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 731                         if (bits_per_pixel < valid_dsc_bpp[i + 1])
 732                                 break;
 733                 }
 734                 drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n",
 735                             bits_per_pixel, valid_dsc_bpp[i]);
 736
 737                 bits_per_pixel = valid_dsc_bpp[i];
 738         }
 739
 740         return bits_per_pixel;
 741 }
 742
 743 u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 744                                 u32 link_clock, u32 lane_count,
 745                                 u32 mode_clock, u32 mode_hdisplay,
 746                                 bool bigjoiner,
 747                                 u32 pipe_bpp,
 748                                 u32 timeslots)
 749 {
 750         u32 bits_per_pixel, max_bpp_small_joiner_ram;
 751
 752         /*
 753          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 754          * (LinkSymbolClock)* 8 * (TimeSlots / 64)
 755          * for SST -> TimeSlots is 64(i.e all TimeSlots that are available)
 756          * for MST -> TimeSlots has to be calculated, based on mode requirements
 757          *
 758          * Due to FEC overhead, the available bw is reduced to 97.2261%.
 759          * To support the given mode:
 760          * Bandwidth required should be <= Available link Bandwidth * FEC Overhead
 761          * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead
 762          * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock
 763          * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) /
 764          *                     (ModeClock / FEC Overhead)
 765          * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) /
 766          *                     (ModeClock / FEC Overhead * 8)
 767          */
 768         bits_per_pixel = ((link_clock * lane_count) * timeslots) /
 769                          (intel_dp_mode_to_fec_clock(mode_clock) * 8);
 770
 771         drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
 772                                 "total bw %u pixel clock %u\n",
 773                                 bits_per_pixel, timeslots,
 774                                 (link_clock * lane_count * 8),
 775                                 intel_dp_mode_to_fec_clock(mode_clock));
 776
 777         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 778         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 779                 mode_hdisplay;
 780
 781         if (bigjoiner)
 782                 max_bpp_small_joiner_ram *= 2;
 783
 784         /*
 785          * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 786          * check, output bpp from small joiner RAM check)
 787          */
 788         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 789
 790         if (bigjoiner) {
 791                 u32 max_bpp_bigjoiner =
 792                         i915->display.cdclk.max_cdclk_freq * 48 /
 793                         intel_dp_mode_to_fec_clock(mode_clock);
 794
 795                 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
 796         }
 797
 798         bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
 799
 800         /*
 801          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 802          * fractional part is 0
 803          */
 804         return bits_per_pixel << 4;
 805 }
 806
 807 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 808                                 int mode_clock, int mode_hdisplay,
 809                                 bool bigjoiner)
 810 {
 811         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 812         u8 min_slice_count, i;
 813         int max_slice_width;
 814
 815         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 816                 min_slice_count = DIV_ROUND_UP(mode_clock,
 817                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 818         else
 819                 min_slice_count = DIV_ROUND_UP(mode_clock,
 820                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 821
 822         /*
 823          * Due to some DSC engine BW limitations, we need to enable second
 824          * slice and VDSC engine, whenever we approach close enough to max CDCLK
 825          */
 826         if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100))
 827                 min_slice_count = max_t(u8, min_slice_count, 2);
 828
 829         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 830         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 831                 drm_dbg_kms(&i915->drm,
 832                             "Unsupported slice width %d by DP DSC Sink device\n",
 833                             max_slice_width);
 834                 return 0;
 835         }
 836         /* Also take into account max slice width */
 837         min_slice_count = max_t(u8, min_slice_count,
 838                                 DIV_ROUND_UP(mode_hdisplay,
 839                                              max_slice_width));
 840
 841         /* Find the closest match to the valid slice count values */
 842         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 843                 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 844
 845                 if (test_slice_count >
 846                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
 847                         break;
 848
 849                 /* big joiner needs small joiner to be enabled */
 850                 if (bigjoiner && test_slice_count < 4)
 851                         continue;
 852
 853                 if (min_slice_count <= test_slice_count)
 854                         return test_slice_count;
 855         }
 856
 857         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 858                     min_slice_count);
 859         return 0;
 860 }
 861
 862 static bool source_can_output(struct intel_dp *intel_dp,
 863                               enum intel_output_format format)
 864 {
 865         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 866
 867         switch (format) {
 868         case INTEL_OUTPUT_FORMAT_RGB:
 869                 return true;
 870
 871         case INTEL_OUTPUT_FORMAT_YCBCR444:
 872                 /*
 873                  * No YCbCr output support on gmch platforms.
 874                  * Also, ILK doesn't seem capable of DP YCbCr output.
 875                  * The displayed image is severly corrupted. SNB+ is fine.
 876                  */
 877                 return !HAS_GMCH(i915) && !IS_IRONLAKE(i915);
 878
 879         case INTEL_OUTPUT_FORMAT_YCBCR420:
 880                 /* Platform < Gen 11 cannot output YCbCr420 format */
 881                 return DISPLAY_VER(i915) >= 11;
 882
 883         default:
 884                 MISSING_CASE(format);
 885                 return false;
 886         }
 887 }
 888
 889 static bool
 890 dfp_can_convert_from_rgb(struct intel_dp *intel_dp,
 891                          enum intel_output_format sink_format)
 892 {
 893         if (!drm_dp_is_branch(intel_dp->dpcd))
 894                 return false;
 895
 896         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 897                 return intel_dp->dfp.rgb_to_ycbcr;
 898
 899         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 900                 return intel_dp->dfp.rgb_to_ycbcr &&
 901                         intel_dp->dfp.ycbcr_444_to_420;
 902
 903         return false;
 904 }
 905
 906 static bool
 907 dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
 908                               enum intel_output_format sink_format)
 909 {
 910         if (!drm_dp_is_branch(intel_dp->dpcd))
 911                 return false;
 912
 913         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 914                 return intel_dp->dfp.ycbcr_444_to_420;
 915
 916         return false;
 917 }
 918
 919 static enum intel_output_format
 920 intel_dp_output_format(struct intel_connector *connector,
 921                        enum intel_output_format sink_format)
 922 {
 923         struct intel_dp *intel_dp = intel_attached_dp(connector);
 924         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 925         enum intel_output_format output_format;
 926
 927         if (intel_dp->force_dsc_output_format)
 928                 return intel_dp->force_dsc_output_format;
 929
 930         if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
 931             dfp_can_convert_from_rgb(intel_dp, sink_format))
 932                 output_format = INTEL_OUTPUT_FORMAT_RGB;
 933
 934         else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
 935                  dfp_can_convert_from_ycbcr444(intel_dp, sink_format))
 936                 output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
 937
 938         else
 939                 output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
 940
 941         drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format));
 942
 943         return output_format;
 944 }
 945
 946 int intel_dp_min_bpp(enum intel_output_format output_format)
 947 {
 948         if (output_format == INTEL_OUTPUT_FORMAT_RGB)
 949                 return 6 * 3;
 950         else
 951                 return 8 * 3;
 952 }
 953
 954 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
 955 {
 956         /*
 957          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
 958          * format of the number of bytes per pixel will be half the number
 959          * of bytes of RGB pixel.
 960          */
 961         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 962                 bpp /= 2;
 963
 964         return bpp;
 965 }
 966
 967 static enum intel_output_format
 968 intel_dp_sink_format(struct intel_connector *connector,
 969                      const struct drm_display_mode *mode)
 970 {
 971         const struct drm_display_info *info = &connector->base.display_info;
 972
 973         if (drm_mode_is_420_only(info, mode))
 974                 return INTEL_OUTPUT_FORMAT_YCBCR420;
 975
 976         return INTEL_OUTPUT_FORMAT_RGB;
 977 }
 978
 979 static int
 980 intel_dp_mode_min_output_bpp(struct intel_connector *connector,
 981                              const struct drm_display_mode *mode)
 982 {
 983         enum intel_output_format output_format, sink_format;
 984
 985         sink_format = intel_dp_sink_format(connector, mode);
 986
 987         output_format = intel_dp_output_format(connector, sink_format);
 988
 989         return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
 990 }
 991
 992 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 993                                   int hdisplay)
 994 {
 995         /*
 996          * Older platforms don't like hdisplay==4096 with DP.
 997          *
 998          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
 999          * and frame counter increment), but we don't get vblank interrupts,
1000          * and the pipe underruns immediately. The link also doesn't seem
1001          * to get trained properly.
1002          *
1003          * On CHV the vblank interrupts don't seem to disappear but
1004          * otherwise the symptoms are similar.
1005          *
1006          * TODO: confirm the behaviour on HSW+
1007          */
1008         return hdisplay == 4096 && !HAS_DDI(dev_priv);
1009 }
1010
1011 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
1012 {
1013         struct intel_connector *connector = intel_dp->attached_connector;
1014         const struct drm_display_info *info = &connector->base.display_info;
1015         int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
1016
1017         /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
1018         if (max_tmds_clock && info->max_tmds_clock)
1019                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1020
1021         return max_tmds_clock;
1022 }
1023
1024 static enum drm_mode_status
1025 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
1026                           int clock, int bpc,
1027                           enum intel_output_format sink_format,
1028                           bool respect_downstream_limits)
1029 {
1030         int tmds_clock, min_tmds_clock, max_tmds_clock;
1031
1032         if (!respect_downstream_limits)
1033                 return MODE_OK;
1034
1035         tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
1036
1037         min_tmds_clock = intel_dp->dfp.min_tmds_clock;
1038         max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
1039
1040         if (min_tmds_clock && tmds_clock < min_tmds_clock)
1041                 return MODE_CLOCK_LOW;
1042
1043         if (max_tmds_clock && tmds_clock > max_tmds_clock)
1044                 return MODE_CLOCK_HIGH;
1045
1046         return MODE_OK;
1047 }
1048
1049 static enum drm_mode_status
1050 intel_dp_mode_valid_downstream(struct intel_connector *connector,
1051                                const struct drm_display_mode *mode,
1052                                int target_clock)
1053 {
1054         struct intel_dp *intel_dp = intel_attached_dp(connector);
1055         const struct drm_display_info *info = &connector->base.display_info;
1056         enum drm_mode_status status;
1057         enum intel_output_format sink_format;
1058
1059         /* If PCON supports FRL MODE, check FRL bandwidth constraints */
1060         if (intel_dp->dfp.pcon_max_frl_bw) {
1061                 int target_bw;
1062                 int max_frl_bw;
1063                 int bpp = intel_dp_mode_min_output_bpp(connector, mode);
1064
1065                 target_bw = bpp * target_clock;
1066
1067                 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
1068
1069                 /* converting bw from Gbps to Kbps*/
1070                 max_frl_bw = max_frl_bw * 1000000;
1071
1072                 if (target_bw > max_frl_bw)
1073                         return MODE_CLOCK_HIGH;
1074
1075                 return MODE_OK;
1076         }
1077
1078         if (intel_dp->dfp.max_dotclock &&
1079             target_clock > intel_dp->dfp.max_dotclock)
1080                 return MODE_CLOCK_HIGH;
1081
1082         sink_format = intel_dp_sink_format(connector, mode);
1083
1084         /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
1085         status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1086                                            8, sink_format, true);
1087
1088         if (status != MODE_OK) {
1089                 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1090                     !connector->base.ycbcr_420_allowed ||
1091                     !drm_mode_is_420_also(info, mode))
1092                         return status;
1093                 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1094                 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1095                                                    8, sink_format, true);
1096                 if (status != MODE_OK)
1097                         return status;
1098         }
1099
1100         return MODE_OK;
1101 }
1102
1103 bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
1104                              int hdisplay, int clock)
1105 {
1106         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1107
1108         if (!intel_dp_can_bigjoiner(intel_dp))
1109                 return false;
1110
1111         return clock > i915->max_dotclk_freq || hdisplay > 5120;
1112 }
1113
1114 static enum drm_mode_status
1115 intel_dp_mode_valid(struct drm_connector *_connector,
1116                     struct drm_display_mode *mode)
1117 {
1118         struct intel_connector *connector = to_intel_connector(_connector);
1119         struct intel_dp *intel_dp = intel_attached_dp(connector);
1120         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1121         const struct drm_display_mode *fixed_mode;
1122         int target_clock = mode->clock;
1123         int max_rate, mode_rate, max_lanes, max_link_clock;
1124         int max_dotclk = dev_priv->max_dotclk_freq;
1125         u16 dsc_max_output_bpp = 0;
1126         u8 dsc_slice_count = 0;
1127         enum drm_mode_status status;
1128         bool dsc = false, bigjoiner = false;
1129
1130         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1131                 return MODE_H_ILLEGAL;
1132
1133         fixed_mode = intel_panel_fixed_mode(connector, mode);
1134         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
1135                 status = intel_panel_mode_valid(connector, mode);
1136                 if (status != MODE_OK)
1137                         return status;
1138
1139                 target_clock = fixed_mode->clock;
1140         }
1141
1142         if (mode->clock < 10000)
1143                 return MODE_CLOCK_LOW;
1144
1145         if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
1146                 bigjoiner = true;
1147                 max_dotclk *= 2;
1148         }
1149         if (target_clock > max_dotclk)
1150                 return MODE_CLOCK_HIGH;
1151
1152         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1153                 return MODE_H_ILLEGAL;
1154
1155         max_link_clock = intel_dp_max_link_rate(intel_dp);
1156         max_lanes = intel_dp_max_lane_count(intel_dp);
1157
1158         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
1159         mode_rate = intel_dp_link_required(target_clock,
1160                                            intel_dp_mode_min_output_bpp(connector, mode));
1161
1162         if (HAS_DSC(dev_priv) &&
1163             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
1164                 /*
1165                  * TBD pass the connector BPC,
1166                  * for now U8_MAX so that max BPC on that platform would be picked
1167                  */
1168                 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
1169
1170                 /*
1171                  * Output bpp is stored in 6.4 format so right shift by 4 to get the
1172                  * integer value since we support only integer values of bpp.
1173                  */
1174                 if (intel_dp_is_edp(intel_dp)) {
1175                         dsc_max_output_bpp =
1176                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
1177                         dsc_slice_count =
1178                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1179                                                                 true);
1180                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
1181                         dsc_max_output_bpp =
1182                                 intel_dp_dsc_get_output_bpp(dev_priv,
1183                                                             max_link_clock,
1184                                                             max_lanes,
1185                                                             target_clock,
1186                                                             mode->hdisplay,
1187                                                             bigjoiner,
1188                                                             pipe_bpp, 64) >> 4;
1189                         dsc_slice_count =
1190                                 intel_dp_dsc_get_slice_count(intel_dp,
1191                                                              target_clock,
1192                                                              mode->hdisplay,
1193                                                              bigjoiner);
1194                 }
1195
1196                 dsc = dsc_max_output_bpp && dsc_slice_count;
1197         }
1198
1199         /*
1200          * Big joiner configuration needs DSC for TGL which is not true for
1201          * XE_LPD where uncompressed joiner is supported.
1202          */
1203         if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
1204                 return MODE_CLOCK_HIGH;
1205
1206         if (mode_rate > max_rate && !dsc)
1207                 return MODE_CLOCK_HIGH;
1208
1209         status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1210         if (status != MODE_OK)
1211                 return status;
1212
1213         return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1214 }
1215
1216 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1217 {
1218         return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1219 }
1220
1221 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1222 {
1223         return DISPLAY_VER(i915) >= 10;
1224 }
1225
1226 static void snprintf_int_array(char *str, size_t len,
1227                                const int *array, int nelem)
1228 {
1229         int i;
1230
1231         str[0] = '\0';
1232
1233         for (i = 0; i < nelem; i++) {
1234                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1235                 if (r >= len)
1236                         return;
1237                 str += r;
1238                 len -= r;
1239         }
1240 }
1241
1242 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1243 {
1244         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1245         char str[128]; /* FIXME: too big for stack? */
1246
1247         if (!drm_debug_enabled(DRM_UT_KMS))
1248                 return;
1249
1250         snprintf_int_array(str, sizeof(str),
1251                            intel_dp->source_rates, intel_dp->num_source_rates);
1252         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1253
1254         snprintf_int_array(str, sizeof(str),
1255                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1256         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1257
1258         snprintf_int_array(str, sizeof(str),
1259                            intel_dp->common_rates, intel_dp->num_common_rates);
1260         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1261 }
1262
1263 int
1264 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1265 {
1266         int len;
1267
1268         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1269
1270         return intel_dp_common_rate(intel_dp, len - 1);
1271 }
1272
1273 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1274 {
1275         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1276         int i = intel_dp_rate_index(intel_dp->sink_rates,
1277                                     intel_dp->num_sink_rates, rate);
1278
1279         if (drm_WARN_ON(&i915->drm, i < 0))
1280                 i = 0;
1281
1282         return i;
1283 }
1284
1285 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1286                            u8 *link_bw, u8 *rate_select)
1287 {
1288         /* eDP 1.4 rate select method. */
1289         if (intel_dp->use_rate_select) {
1290                 *link_bw = 0;
1291                 *rate_select =
1292                         intel_dp_rate_select(intel_dp, port_clock);
1293         } else {
1294                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1295                 *rate_select = 0;
1296         }
1297 }
1298
1299 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp)
1300 {
1301         struct intel_connector *connector = intel_dp->attached_connector;
1302
1303         return connector->base.display_info.is_hdmi;
1304 }
1305
1306 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1307                                          const struct intel_crtc_state *pipe_config)
1308 {
1309         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1310
1311         /* On TGL, FEC is supported on all Pipes */
1312         if (DISPLAY_VER(dev_priv) >= 12)
1313                 return true;
1314
1315         if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A)
1316                 return true;
1317
1318         return false;
1319 }
1320
1321 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1322                                   const struct intel_crtc_state *pipe_config)
1323 {
1324         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1325                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1326 }
1327
1328 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1329                                   const struct intel_crtc_state *crtc_state)
1330 {
1331         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1332                 return false;
1333
1334         return intel_dsc_source_support(crtc_state) &&
1335                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1336 }
1337
1338 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1339                                      const struct intel_crtc_state *crtc_state,
1340                                      int bpc, bool respect_downstream_limits)
1341 {
1342         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1343
1344         /*
1345          * Current bpc could already be below 8bpc due to
1346          * FDI bandwidth constraints or other limits.
1347          * HDMI minimum is 8bpc however.
1348          */
1349         bpc = max(bpc, 8);
1350
1351         /*
1352          * We will never exceed downstream TMDS clock limits while
1353          * attempting deep color. If the user insists on forcing an
1354          * out of spec mode they will have to be satisfied with 8bpc.
1355          */
1356         if (!respect_downstream_limits)
1357                 bpc = 8;
1358
1359         for (; bpc >= 8; bpc -= 2) {
1360                 if (intel_hdmi_bpc_possible(crtc_state, bpc,
1361                                             intel_dp_has_hdmi_sink(intel_dp)) &&
1362                     intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
1363                                               respect_downstream_limits) == MODE_OK)
1364                         return bpc;
1365         }
1366
1367         return -EINVAL;
1368 }
1369
1370 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1371                             const struct intel_crtc_state *crtc_state,
1372                             bool respect_downstream_limits)
1373 {
1374         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1375         struct intel_connector *intel_connector = intel_dp->attached_connector;
1376         int bpp, bpc;
1377
1378         bpc = crtc_state->pipe_bpp / 3;
1379
1380         if (intel_dp->dfp.max_bpc)
1381                 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1382
1383         if (intel_dp->dfp.min_tmds_clock) {
1384                 int max_hdmi_bpc;
1385
1386                 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1387                                                          respect_downstream_limits);
1388                 if (max_hdmi_bpc < 0)
1389                         return 0;
1390
1391                 bpc = min(bpc, max_hdmi_bpc);
1392         }
1393
1394         bpp = bpc * 3;
1395         if (intel_dp_is_edp(intel_dp)) {
1396                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1397                 if (intel_connector->base.display_info.bpc == 0 &&
1398                     intel_connector->panel.vbt.edp.bpp &&
1399                     intel_connector->panel.vbt.edp.bpp < bpp) {
1400                         drm_dbg_kms(&dev_priv->drm,
1401                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
1402                                     intel_connector->panel.vbt.edp.bpp);
1403                         bpp = intel_connector->panel.vbt.edp.bpp;
1404                 }
1405         }
1406
1407         return bpp;
1408 }
1409
1410 /* Adjust link config limits based on compliance test requests. */
1411 void
1412 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1413                                   struct intel_crtc_state *pipe_config,
1414                                   struct link_config_limits *limits)
1415 {
1416         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1417
1418         /* For DP Compliance we override the computed bpp for the pipe */
1419         if (intel_dp->compliance.test_data.bpc != 0) {
1420                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1421
1422                 limits->min_bpp = limits->max_bpp = bpp;
1423                 pipe_config->dither_force_disable = bpp == 6 * 3;
1424
1425                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1426         }
1427
1428         /* Use values requested by Compliance Test Request */
1429         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1430                 int index;
1431
1432                 /* Validate the compliance test data since max values
1433                  * might have changed due to link train fallback.
1434                  */
1435                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1436                                                intel_dp->compliance.test_lane_count)) {
1437                         index = intel_dp_rate_index(intel_dp->common_rates,
1438                                                     intel_dp->num_common_rates,
1439                                                     intel_dp->compliance.test_link_rate);
1440                         if (index >= 0)
1441                                 limits->min_rate = limits->max_rate =
1442                                         intel_dp->compliance.test_link_rate;
1443                         limits->min_lane_count = limits->max_lane_count =
1444                                 intel_dp->compliance.test_lane_count;
1445                 }
1446         }
1447 }
1448
1449 static bool has_seamless_m_n(struct intel_connector *connector)
1450 {
1451         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1452
1453         /*
1454          * Seamless M/N reprogramming only implemented
1455          * for BDW+ double buffered M/N registers so far.
1456          */
1457         return HAS_DOUBLE_BUFFERED_M_N(i915) &&
1458                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1459 }
1460
1461 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
1462                                const struct drm_connector_state *conn_state)
1463 {
1464         struct intel_connector *connector = to_intel_connector(conn_state->connector);
1465         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1466
1467         /* FIXME a bit of a mess wrt clock vs. crtc_clock */
1468         if (has_seamless_m_n(connector))
1469                 return intel_panel_highest_mode(connector, adjusted_mode)->clock;
1470         else
1471                 return adjusted_mode->crtc_clock;
1472 }
1473
1474 /* Optimize link config in order: max bpp, min clock, min lanes */
1475 static int
1476 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1477                                   struct intel_crtc_state *pipe_config,
1478                                   const struct drm_connector_state *conn_state,
1479                                   const struct link_config_limits *limits)
1480 {
1481         int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
1482         int mode_rate, link_rate, link_avail;
1483
1484         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1485                 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1486
1487                 mode_rate = intel_dp_link_required(clock, output_bpp);
1488
1489                 for (i = 0; i < intel_dp->num_common_rates; i++) {
1490                         link_rate = intel_dp_common_rate(intel_dp, i);
1491                         if (link_rate < limits->min_rate ||
1492                             link_rate > limits->max_rate)
1493                                 continue;
1494
1495                         for (lane_count = limits->min_lane_count;
1496                              lane_count <= limits->max_lane_count;
1497                              lane_count <<= 1) {
1498                                 link_avail = intel_dp_max_data_rate(link_rate,
1499                                                                     lane_count);
1500
1501                                 if (mode_rate <= link_avail) {
1502                                         pipe_config->lane_count = lane_count;
1503                                         pipe_config->pipe_bpp = bpp;
1504                                         pipe_config->port_clock = link_rate;
1505
1506                                         return 0;
1507                                 }
1508                         }
1509                 }
1510         }
1511
1512         return -EINVAL;
1513 }
1514
1515 int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
1516 {
1517         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1518         int i, num_bpc;
1519         u8 dsc_bpc[3] = {0};
1520         u8 dsc_max_bpc;
1521
1522         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1523         if (DISPLAY_VER(i915) >= 12)
1524                 dsc_max_bpc = min_t(u8, 12, max_req_bpc);
1525         else
1526                 dsc_max_bpc = min_t(u8, 10, max_req_bpc);
1527
1528         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1529                                                        dsc_bpc);
1530         for (i = 0; i < num_bpc; i++) {
1531                 if (dsc_max_bpc >= dsc_bpc[i])
1532                         return dsc_bpc[i] * 3;
1533         }
1534
1535         return 0;
1536 }
1537
1538 static int intel_dp_source_dsc_version_minor(struct intel_dp *intel_dp)
1539 {
1540         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1541
1542         return DISPLAY_VER(i915) >= 14 ? 2 : 1;
1543 }
1544
1545 static int intel_dp_sink_dsc_version_minor(struct intel_dp *intel_dp)
1546 {
1547         return (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
1548                 DP_DSC_MINOR_SHIFT;
1549 }
1550
1551 static int intel_dp_get_slice_height(int vactive)
1552 {
1553         int slice_height;
1554
1555         /*
1556          * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108
1557          * lines is an optimal slice height, but any size can be used as long as
1558          * vertical active integer multiple and maximum vertical slice count
1559          * requirements are met.
1560          */
1561         for (slice_height = 108; slice_height <= vactive; slice_height += 2)
1562                 if (vactive % slice_height == 0)
1563                         return slice_height;
1564
1565         /*
1566          * Highly unlikely we reach here as most of the resolutions will end up
1567          * finding appropriate slice_height in above loop but returning
1568          * slice_height as 2 here as it should work with all resolutions.
1569          */
1570         return 2;
1571 }
1572
1573 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
1574                                        struct intel_crtc_state *crtc_state)
1575 {
1576         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1577         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1578         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1579         u8 line_buf_depth;
1580         int ret;
1581
1582         /*
1583          * RC_MODEL_SIZE is currently a constant across all configurations.
1584          *
1585          * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1586          * DP_DSC_RC_BUF_SIZE for this.
1587          */
1588         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1589         vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1590
1591         vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height);
1592
1593         ret = intel_dsc_compute_params(crtc_state);
1594         if (ret)
1595                 return ret;
1596
1597         vdsc_cfg->dsc_version_major =
1598                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1599                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1600         vdsc_cfg->dsc_version_minor =
1601                 min(intel_dp_source_dsc_version_minor(intel_dp),
1602                     intel_dp_sink_dsc_version_minor(intel_dp));
1603         if (vdsc_cfg->convert_rgb)
1604                 vdsc_cfg->convert_rgb =
1605                         intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1606                         DP_DSC_RGB;
1607
1608         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
1609         if (!line_buf_depth) {
1610                 drm_dbg_kms(&i915->drm,
1611                             "DSC Sink Line Buffer Depth invalid\n");
1612                 return -EINVAL;
1613         }
1614
1615         if (vdsc_cfg->dsc_version_minor == 2)
1616                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1617                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1618         else
1619                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1620                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1621
1622         vdsc_cfg->block_pred_enable =
1623                 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1624                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1625
1626         return drm_dsc_compute_rc_parameters(vdsc_cfg);
1627 }
1628
1629 static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
1630                                          enum intel_output_format output_format)
1631 {
1632         u8 sink_dsc_format;
1633
1634         switch (output_format) {
1635         case INTEL_OUTPUT_FORMAT_RGB:
1636                 sink_dsc_format = DP_DSC_RGB;
1637                 break;
1638         case INTEL_OUTPUT_FORMAT_YCBCR444:
1639                 sink_dsc_format = DP_DSC_YCbCr444;
1640                 break;
1641         case INTEL_OUTPUT_FORMAT_YCBCR420:
1642                 if (min(intel_dp_source_dsc_version_minor(intel_dp),
1643                         intel_dp_sink_dsc_version_minor(intel_dp)) < 2)
1644                         return false;
1645                 sink_dsc_format = DP_DSC_YCbCr420_Native;
1646                 break;
1647         default:
1648                 return false;
1649         }
1650
1651         return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
1652 }
1653
1654 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1655                                 struct intel_crtc_state *pipe_config,
1656                                 struct drm_connector_state *conn_state,
1657                                 struct link_config_limits *limits,
1658                                 int timeslots,
1659                                 bool compute_pipe_bpp)
1660 {
1661         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1662         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1663         const struct drm_display_mode *adjusted_mode =
1664                 &pipe_config->hw.adjusted_mode;
1665         int pipe_bpp;
1666         int ret;
1667
1668         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1669                 intel_dp_supports_fec(intel_dp, pipe_config);
1670
1671         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1672                 return -EINVAL;
1673
1674         if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
1675                 return -EINVAL;
1676
1677         if (compute_pipe_bpp)
1678                 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
1679         else
1680                 pipe_bpp = pipe_config->pipe_bpp;
1681
1682         if (intel_dp->force_dsc_bpc) {
1683                 pipe_bpp = intel_dp->force_dsc_bpc * 3;
1684                 drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);
1685         }
1686
1687         /* Min Input BPC for ICL+ is 8 */
1688         if (pipe_bpp < 8 * 3) {
1689                 drm_dbg_kms(&dev_priv->drm,
1690                             "No DSC support for less than 8bpc\n");
1691                 return -EINVAL;
1692         }
1693
1694         /*
1695          * For now enable DSC for max bpp, max link rate, max lane count.
1696          * Optimize this later for the minimum possible link rate/lane count
1697          * with DSC enabled for the requested mode.
1698          */
1699         pipe_config->pipe_bpp = pipe_bpp;
1700         pipe_config->port_clock = limits->max_rate;
1701         pipe_config->lane_count = limits->max_lane_count;
1702
1703         if (intel_dp_is_edp(intel_dp)) {
1704                 pipe_config->dsc.compressed_bpp =
1705                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1706                               pipe_config->pipe_bpp);
1707                 pipe_config->dsc.slice_count =
1708                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1709                                                         true);
1710                 if (!pipe_config->dsc.slice_count) {
1711                         drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n",
1712                                     pipe_config->dsc.slice_count);
1713                         return -EINVAL;
1714                 }
1715         } else {
1716                 u16 dsc_max_output_bpp = 0;
1717                 u8 dsc_dp_slice_count;
1718
1719                 if (compute_pipe_bpp) {
1720                         dsc_max_output_bpp =
1721                                 intel_dp_dsc_get_output_bpp(dev_priv,
1722                                                             pipe_config->port_clock,
1723                                                             pipe_config->lane_count,
1724                                                             adjusted_mode->crtc_clock,
1725                                                             adjusted_mode->crtc_hdisplay,
1726                                                             pipe_config->bigjoiner_pipes,
1727                                                             pipe_bpp,
1728                                                             timeslots);
1729                         /*
1730                          * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
1731                          * supported PPS value can be 63.9375 and with the further
1732                          * mention that bpp should be programmed double the target bpp
1733                          * restricting our target bpp to be 31.9375 at max
1734                          */
1735                         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1736                                 dsc_max_output_bpp = min_t(u16, dsc_max_output_bpp, 31 << 4);
1737
1738                         if (!dsc_max_output_bpp) {
1739                                 drm_dbg_kms(&dev_priv->drm,
1740                                             "Compressed BPP not supported\n");
1741                                 return -EINVAL;
1742                         }
1743                 }
1744                 dsc_dp_slice_count =
1745                         intel_dp_dsc_get_slice_count(intel_dp,
1746                                                      adjusted_mode->crtc_clock,
1747                                                      adjusted_mode->crtc_hdisplay,
1748                                                      pipe_config->bigjoiner_pipes);
1749                 if (!dsc_dp_slice_count) {
1750                         drm_dbg_kms(&dev_priv->drm,
1751                                     "Compressed Slice Count not supported\n");
1752                         return -EINVAL;
1753                 }
1754
1755                 /*
1756                  * compute pipe bpp is set to false for DP MST DSC case
1757                  * and compressed_bpp is calculated same time once
1758                  * vpci timeslots are allocated, because overall bpp
1759                  * calculation procedure is bit different for MST case.
1760                  */
1761                 if (compute_pipe_bpp) {
1762                         pipe_config->dsc.compressed_bpp = min_t(u16,
1763                                                                 dsc_max_output_bpp >> 4,
1764                                                                 pipe_config->pipe_bpp);
1765                 }
1766                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
1767                 drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n",
1768                             pipe_config->dsc.compressed_bpp,
1769                             pipe_config->dsc.slice_count);
1770         }
1771         /*
1772          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1773          * is greater than the maximum Cdclock and if slice count is even
1774          * then we need to use 2 VDSC instances.
1775          */
1776         if (pipe_config->bigjoiner_pipes || pipe_config->dsc.slice_count > 1)
1777                 pipe_config->dsc.dsc_split = true;
1778
1779         ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
1780         if (ret < 0) {
1781                 drm_dbg_kms(&dev_priv->drm,
1782                             "Cannot compute valid DSC parameters for Input Bpp = %d "
1783                             "Compressed BPP = %d\n",
1784                             pipe_config->pipe_bpp,
1785                             pipe_config->dsc.compressed_bpp);
1786                 return ret;
1787         }
1788
1789         pipe_config->dsc.compression_enable = true;
1790         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
1791                     "Compressed Bpp = %d Slice Count = %d\n",
1792                     pipe_config->pipe_bpp,
1793                     pipe_config->dsc.compressed_bpp,
1794                     pipe_config->dsc.slice_count);
1795
1796         return 0;
1797 }
1798
1799 static int
1800 intel_dp_compute_link_config(struct intel_encoder *encoder,
1801                              struct intel_crtc_state *pipe_config,
1802                              struct drm_connector_state *conn_state,
1803                              bool respect_downstream_limits)
1804 {
1805         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1806         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1807         const struct drm_display_mode *adjusted_mode =
1808                 &pipe_config->hw.adjusted_mode;
1809         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1810         struct link_config_limits limits;
1811         bool joiner_needs_dsc = false;
1812         int ret;
1813
1814         limits.min_rate = intel_dp_common_rate(intel_dp, 0);
1815         limits.max_rate = intel_dp_max_link_rate(intel_dp);
1816
1817         limits.min_lane_count = 1;
1818         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1819
1820         limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
1821         limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config, respect_downstream_limits);
1822
1823         if (intel_dp->use_max_params) {
1824                 /*
1825                  * Use the maximum clock and number of lanes the eDP panel
1826                  * advertizes being capable of in case the initial fast
1827                  * optimal params failed us. The panels are generally
1828                  * designed to support only a single clock and lane
1829                  * configuration, and typically on older panels these
1830                  * values correspond to the native resolution of the panel.
1831                  */
1832                 limits.min_lane_count = limits.max_lane_count;
1833                 limits.min_rate = limits.max_rate;
1834         }
1835
1836         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1837
1838         drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
1839                     "max rate %d max bpp %d pixel clock %iKHz\n",
1840                     limits.max_lane_count, limits.max_rate,
1841                     limits.max_bpp, adjusted_mode->crtc_clock);
1842
1843         if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
1844                                     adjusted_mode->crtc_clock))
1845                 pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
1846
1847         /*
1848          * Pipe joiner needs compression up to display 12 due to bandwidth
1849          * limitation. DG2 onwards pipe joiner can be enabled without
1850          * compression.
1851          */
1852         joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
1853
1854         /*
1855          * Optimize for slow and wide for everything, because there are some
1856          * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
1857          */
1858         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, conn_state, &limits);
1859
1860         if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
1861                 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
1862                             str_yes_no(ret), str_yes_no(joiner_needs_dsc),
1863                             str_yes_no(intel_dp->force_dsc_en));
1864                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
1865                                                   conn_state, &limits, 64, true);
1866                 if (ret < 0)
1867                         return ret;
1868         }
1869
1870         if (pipe_config->dsc.compression_enable) {
1871                 drm_dbg_kms(&i915->drm,
1872                             "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
1873                             pipe_config->lane_count, pipe_config->port_clock,
1874                             pipe_config->pipe_bpp,
1875                             pipe_config->dsc.compressed_bpp);
1876
1877                 drm_dbg_kms(&i915->drm,
1878                             "DP link rate required %i available %i\n",
1879                             intel_dp_link_required(adjusted_mode->crtc_clock,
1880                                                    pipe_config->dsc.compressed_bpp),
1881                             intel_dp_max_data_rate(pipe_config->port_clock,
1882                                                    pipe_config->lane_count));
1883         } else {
1884                 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
1885                             pipe_config->lane_count, pipe_config->port_clock,
1886                             pipe_config->pipe_bpp);
1887
1888                 drm_dbg_kms(&i915->drm,
1889                             "DP link rate required %i available %i\n",
1890                             intel_dp_link_required(adjusted_mode->crtc_clock,
1891                                                    pipe_config->pipe_bpp),
1892                             intel_dp_max_data_rate(pipe_config->port_clock,
1893                                                    pipe_config->lane_count));
1894         }
1895         return 0;
1896 }
1897
1898 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
1899                                   const struct drm_connector_state *conn_state)
1900 {
1901         const struct intel_digital_connector_state *intel_conn_state =
1902                 to_intel_digital_connector_state(conn_state);
1903         const struct drm_display_mode *adjusted_mode =
1904                 &crtc_state->hw.adjusted_mode;
1905
1906         /*
1907          * Our YCbCr output is always limited range.
1908          * crtc_state->limited_color_range only applies to RGB,
1909          * and it must never be set for YCbCr or we risk setting
1910          * some conflicting bits in TRANSCONF which will mess up
1911          * the colors on the monitor.
1912          */
1913         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1914                 return false;
1915
1916         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1917                 /*
1918                  * See:
1919                  * CEA-861-E - 5.1 Default Encoding Parameters
1920                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1921                  */
1922                 return crtc_state->pipe_bpp != 18 &&
1923                         drm_default_rgb_quant_range(adjusted_mode) ==
1924                         HDMI_QUANTIZATION_RANGE_LIMITED;
1925         } else {
1926                 return intel_conn_state->broadcast_rgb ==
1927                         INTEL_BROADCAST_RGB_LIMITED;
1928         }
1929 }
1930
1931 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
1932                                     enum port port)
1933 {
1934         if (IS_G4X(dev_priv))
1935                 return false;
1936         if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
1937                 return false;
1938
1939         return true;
1940 }
1941
1942 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
1943                                              const struct drm_connector_state *conn_state,
1944                                              struct drm_dp_vsc_sdp *vsc)
1945 {
1946         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1947         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1948
1949         /*
1950          * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1951          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
1952          * Colorimetry Format indication.
1953          */
1954         vsc->revision = 0x5;
1955         vsc->length = 0x13;
1956
1957         /* DP 1.4a spec, Table 2-120 */
1958         switch (crtc_state->output_format) {
1959         case INTEL_OUTPUT_FORMAT_YCBCR444:
1960                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
1961                 break;
1962         case INTEL_OUTPUT_FORMAT_YCBCR420:
1963                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
1964                 break;
1965         case INTEL_OUTPUT_FORMAT_RGB:
1966         default:
1967                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
1968         }
1969
1970         switch (conn_state->colorspace) {
1971         case DRM_MODE_COLORIMETRY_BT709_YCC:
1972                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1973                 break;
1974         case DRM_MODE_COLORIMETRY_XVYCC_601:
1975                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
1976                 break;
1977         case DRM_MODE_COLORIMETRY_XVYCC_709:
1978                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
1979                 break;
1980         case DRM_MODE_COLORIMETRY_SYCC_601:
1981                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
1982                 break;
1983         case DRM_MODE_COLORIMETRY_OPYCC_601:
1984                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
1985                 break;
1986         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1987                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
1988                 break;
1989         case DRM_MODE_COLORIMETRY_BT2020_RGB:
1990                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
1991                 break;
1992         case DRM_MODE_COLORIMETRY_BT2020_YCC:
1993                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
1994                 break;
1995         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1996         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1997                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
1998                 break;
1999         default:
2000                 /*
2001                  * RGB->YCBCR color conversion uses the BT.709
2002                  * color space.
2003                  */
2004                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2005                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2006                 else
2007                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2008                 break;
2009         }
2010
2011         vsc->bpc = crtc_state->pipe_bpp / 3;
2012
2013         /* only RGB pixelformat supports 6 bpc */
2014         drm_WARN_ON(&dev_priv->drm,
2015                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2016
2017         /* all YCbCr are always limited range */
2018         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2019         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2020 }
2021
2022 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2023                                      struct intel_crtc_state *crtc_state,
2024                                      const struct drm_connector_state *conn_state)
2025 {
2026         struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
2027
2028         /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
2029         if (crtc_state->has_psr)
2030                 return;
2031
2032         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
2033                 return;
2034
2035         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2036         vsc->sdp_type = DP_SDP_VSC;
2037         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2038                                          &crtc_state->infoframes.vsc);
2039 }
2040
2041 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
2042                                   const struct intel_crtc_state *crtc_state,
2043                                   const struct drm_connector_state *conn_state,
2044                                   struct drm_dp_vsc_sdp *vsc)
2045 {
2046         vsc->sdp_type = DP_SDP_VSC;
2047
2048         if (crtc_state->has_psr2) {
2049                 if (intel_dp->psr.colorimetry_support &&
2050                     intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2051                         /* [PSR2, +Colorimetry] */
2052                         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2053                                                          vsc);
2054                 } else {
2055                         /*
2056                          * [PSR2, -Colorimetry]
2057                          * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2058                          * 3D stereo + PSR/PSR2 + Y-coordinate.
2059                          */
2060                         vsc->revision = 0x4;
2061                         vsc->length = 0xe;
2062                 }
2063         } else {
2064                 /*
2065                  * [PSR1]
2066                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2067                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2068                  * higher).
2069                  */
2070                 vsc->revision = 0x2;
2071                 vsc->length = 0x8;
2072         }
2073 }
2074
2075 static void
2076 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2077                                             struct intel_crtc_state *crtc_state,
2078                                             const struct drm_connector_state *conn_state)
2079 {
2080         int ret;
2081         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2082         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2083
2084         if (!conn_state->hdr_output_metadata)
2085                 return;
2086
2087         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2088
2089         if (ret) {
2090                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2091                 return;
2092         }
2093
2094         crtc_state->infoframes.enable |=
2095                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2096 }
2097
2098 static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915,
2099                                     enum transcoder cpu_transcoder)
2100 {
2101         if (HAS_DOUBLE_BUFFERED_M_N(i915))
2102                 return true;
2103
2104         return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
2105 }
2106
2107 static bool can_enable_drrs(struct intel_connector *connector,
2108                             const struct intel_crtc_state *pipe_config,
2109                             const struct drm_display_mode *downclock_mode)
2110 {
2111         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2112
2113         if (pipe_config->vrr.enable)
2114                 return false;
2115
2116         /*
2117          * DRRS and PSR can't be enable together, so giving preference to PSR
2118          * as it allows more power-savings by complete shutting down display,
2119          * so to guarantee this, intel_drrs_compute_config() must be called
2120          * after intel_psr_compute_config().
2121          */
2122         if (pipe_config->has_psr)
2123                 return false;
2124
2125         /* FIXME missing FDI M2/N2 etc. */
2126         if (pipe_config->has_pch_encoder)
2127                 return false;
2128
2129         if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
2130                 return false;
2131
2132         return downclock_mode &&
2133                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
2134 }
2135
2136 static void
2137 intel_dp_drrs_compute_config(struct intel_connector *connector,
2138                              struct intel_crtc_state *pipe_config,
2139                              int output_bpp)
2140 {
2141         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2142         const struct drm_display_mode *downclock_mode =
2143                 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
2144         int pixel_clock;
2145
2146         if (has_seamless_m_n(connector))
2147                 pipe_config->seamless_m_n = true;
2148
2149         if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
2150                 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
2151                         intel_zero_m_n(&pipe_config->dp_m2_n2);
2152                 return;
2153         }
2154
2155         if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
2156                 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
2157
2158         pipe_config->has_drrs = true;
2159
2160         pixel_clock = downclock_mode->clock;
2161         if (pipe_config->splitter.enable)
2162                 pixel_clock /= pipe_config->splitter.link_count;
2163
2164         intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
2165                                pipe_config->port_clock, &pipe_config->dp_m2_n2,
2166                                pipe_config->fec_enable);
2167
2168         /* FIXME: abstract this better */
2169         if (pipe_config->splitter.enable)
2170                 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
2171 }
2172
2173 static bool intel_dp_has_audio(struct intel_encoder *encoder,
2174                                const struct drm_connector_state *conn_state)
2175 {
2176         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2177         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2178         struct intel_connector *connector = intel_dp->attached_connector;
2179         const struct intel_digital_connector_state *intel_conn_state =
2180                 to_intel_digital_connector_state(conn_state);
2181
2182         if (!intel_dp_port_has_audio(i915, encoder->port))
2183                 return false;
2184
2185         if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2186                 return connector->base.display_info.has_audio;
2187         else
2188                 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2189 }
2190
2191 static int
2192 intel_dp_compute_output_format(struct intel_encoder *encoder,
2193                                struct intel_crtc_state *crtc_state,
2194                                struct drm_connector_state *conn_state,
2195                                bool respect_downstream_limits)
2196 {
2197         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2198         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2199         struct intel_connector *connector = intel_dp->attached_connector;
2200         const struct drm_display_info *info = &connector->base.display_info;
2201         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2202         bool ycbcr_420_only;
2203         int ret;
2204
2205         ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2206
2207         if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
2208                 drm_dbg_kms(&i915->drm,
2209                             "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2210                 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
2211         } else {
2212                 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode);
2213         }
2214
2215         crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
2216
2217         ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2218                                            respect_downstream_limits);
2219         if (ret) {
2220                 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2221                     !connector->base.ycbcr_420_allowed ||
2222                     !drm_mode_is_420_also(info, adjusted_mode))
2223                         return ret;
2224
2225                 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2226                 crtc_state->output_format = intel_dp_output_format(connector,
2227                                                                    crtc_state->sink_format);
2228                 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2229                                                    respect_downstream_limits);
2230         }
2231
2232         return ret;
2233 }
2234
2235 static void
2236 intel_dp_audio_compute_config(struct intel_encoder *encoder,
2237                               struct intel_crtc_state *pipe_config,
2238                               struct drm_connector_state *conn_state)
2239 {
2240         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2241         struct drm_connector *connector = conn_state->connector;
2242
2243         pipe_config->sdp_split_enable =
2244                 intel_dp_has_audio(encoder, conn_state) &&
2245                 intel_dp_is_uhbr(pipe_config);
2246
2247         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] SDP split enable: %s\n",
2248                     connector->base.id, connector->name,
2249                     str_yes_no(pipe_config->sdp_split_enable));
2250 }
2251
2252 int
2253 intel_dp_compute_config(struct intel_encoder *encoder,
2254                         struct intel_crtc_state *pipe_config,
2255                         struct drm_connector_state *conn_state)
2256 {
2257         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2258         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2259         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2260         const struct drm_display_mode *fixed_mode;
2261         struct intel_connector *connector = intel_dp->attached_connector;
2262         int ret = 0, output_bpp;
2263
2264         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
2265                 pipe_config->has_pch_encoder = true;
2266
2267         pipe_config->has_audio =
2268                 intel_dp_has_audio(encoder, conn_state) &&
2269                 intel_audio_compute_config(encoder, pipe_config, conn_state);
2270
2271         fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
2272         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
2273                 ret = intel_panel_compute_config(connector, adjusted_mode);
2274                 if (ret)
2275                         return ret;
2276         }
2277
2278         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2279                 return -EINVAL;
2280
2281         if (!connector->base.interlace_allowed &&
2282             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2283                 return -EINVAL;
2284
2285         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2286                 return -EINVAL;
2287
2288         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2289                 return -EINVAL;
2290
2291         /*
2292          * Try to respect downstream TMDS clock limits first, if
2293          * that fails assume the user might know something we don't.
2294          */
2295         ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
2296         if (ret)
2297                 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
2298         if (ret)
2299                 return ret;
2300
2301         if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
2302             pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2303                 ret = intel_panel_fitting(pipe_config, conn_state);
2304                 if (ret)
2305                         return ret;
2306         }
2307
2308         pipe_config->limited_color_range =
2309                 intel_dp_limited_color_range(pipe_config, conn_state);
2310
2311         if (pipe_config->dsc.compression_enable)
2312                 output_bpp = pipe_config->dsc.compressed_bpp;
2313         else
2314                 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
2315                                                  pipe_config->pipe_bpp);
2316
2317         if (intel_dp->mso_link_count) {
2318                 int n = intel_dp->mso_link_count;
2319                 int overlap = intel_dp->mso_pixel_overlap;
2320
2321                 pipe_config->splitter.enable = true;
2322                 pipe_config->splitter.link_count = n;
2323                 pipe_config->splitter.pixel_overlap = overlap;
2324
2325                 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
2326                             n, overlap);
2327
2328                 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
2329                 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
2330                 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
2331                 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
2332                 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
2333                 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
2334                 adjusted_mode->crtc_clock /= n;
2335         }
2336
2337         intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
2338
2339         intel_link_compute_m_n(output_bpp,
2340                                pipe_config->lane_count,
2341                                adjusted_mode->crtc_clock,
2342                                pipe_config->port_clock,
2343                                &pipe_config->dp_m_n,
2344                                pipe_config->fec_enable);
2345
2346         /* FIXME: abstract this better */
2347         if (pipe_config->splitter.enable)
2348                 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
2349
2350         if (!HAS_DDI(dev_priv))
2351                 g4x_dp_set_clock(encoder, pipe_config);
2352
2353         intel_vrr_compute_config(pipe_config, conn_state);
2354         intel_psr_compute_config(intel_dp, pipe_config, conn_state);
2355         intel_dp_drrs_compute_config(connector, pipe_config, output_bpp);
2356         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2357         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2358
2359         return 0;
2360 }
2361
2362 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2363                               int link_rate, int lane_count)
2364 {
2365         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2366         intel_dp->link_trained = false;
2367         intel_dp->link_rate = link_rate;
2368         intel_dp->lane_count = lane_count;
2369 }
2370
2371 static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
2372 {
2373         intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
2374         intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
2375 }
2376
2377 /* Enable backlight PWM and backlight PP control. */
2378 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2379                             const struct drm_connector_state *conn_state)
2380 {
2381         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
2382         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2383
2384         if (!intel_dp_is_edp(intel_dp))
2385                 return;
2386
2387         drm_dbg_kms(&i915->drm, "\n");
2388
2389         intel_backlight_enable(crtc_state, conn_state);
2390         intel_pps_backlight_on(intel_dp);
2391 }
2392
2393 /* Disable backlight PP control and backlight PWM. */
2394 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2395 {
2396         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
2397         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2398
2399         if (!intel_dp_is_edp(intel_dp))
2400                 return;
2401
2402         drm_dbg_kms(&i915->drm, "\n");
2403
2404         intel_pps_backlight_off(intel_dp);
2405         intel_backlight_disable(old_conn_state);
2406 }
2407
2408 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2409 {
2410         /*
2411          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2412          * be capable of signalling downstream hpd with a long pulse.
2413          * Whether or not that means D3 is safe to use is not clear,
2414          * but let's assume so until proven otherwise.
2415          *
2416          * FIXME should really check all downstream ports...
2417          */
2418         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2419                 drm_dp_is_branch(intel_dp->dpcd) &&
2420                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2421 }
2422
2423 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2424                                            const struct intel_crtc_state *crtc_state,
2425                                            bool enable)
2426 {
2427         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2428         int ret;
2429
2430         if (!crtc_state->dsc.compression_enable)
2431                 return;
2432
2433         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2434                                  enable ? DP_DECOMPRESSION_EN : 0);
2435         if (ret < 0)
2436                 drm_dbg_kms(&i915->drm,
2437                             "Failed to %s sink decompression state\n",
2438                             str_enable_disable(enable));
2439 }
2440
2441 static void
2442 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
2443 {
2444         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2445         u8 oui[] = { 0x00, 0xaa, 0x01 };
2446         u8 buf[3] = { 0 };
2447
2448         /*
2449          * During driver init, we want to be careful and avoid changing the source OUI if it's
2450          * already set to what we want, so as to avoid clearing any state by accident
2451          */
2452         if (careful) {
2453                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
2454                         drm_err(&i915->drm, "Failed to read source OUI\n");
2455
2456                 if (memcmp(oui, buf, sizeof(oui)) == 0)
2457                         return;
2458         }
2459
2460         if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
2461                 drm_err(&i915->drm, "Failed to write source OUI\n");
2462
2463         intel_dp->last_oui_write = jiffies;
2464 }
2465
2466 void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
2467 {
2468         struct intel_connector *connector = intel_dp->attached_connector;
2469         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2470
2471         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
2472                     connector->base.base.id, connector->base.name,
2473                     connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
2474
2475         wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,
2476                                        connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
2477 }
2478
2479 /* If the device supports it, try to set the power state appropriately */
2480 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
2481 {
2482         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2483         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2484         int ret, i;
2485
2486         /* Should have a valid DPCD by this point */
2487         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2488                 return;
2489
2490         if (mode != DP_SET_POWER_D0) {
2491                 if (downstream_hpd_needs_d0(intel_dp))
2492                         return;
2493
2494                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2495         } else {
2496                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2497
2498                 lspcon_resume(dp_to_dig_port(intel_dp));
2499
2500                 /* Write the source OUI as early as possible */
2501                 if (intel_dp_is_edp(intel_dp))
2502                         intel_edp_init_source_oui(intel_dp, false);
2503
2504                 /*
2505                  * When turning on, we need to retry for 1ms to give the sink
2506                  * time to wake up.
2507                  */
2508                 for (i = 0; i < 3; i++) {
2509                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2510                         if (ret == 1)
2511                                 break;
2512                         msleep(1);
2513                 }
2514
2515                 if (ret == 1 && lspcon->active)
2516                         lspcon_wait_pcon_mode(lspcon);
2517         }
2518
2519         if (ret != 1)
2520                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
2521                             encoder->base.base.id, encoder->base.name,
2522                             mode == DP_SET_POWER_D0 ? "D0" : "D3");
2523 }
2524
2525 static bool
2526 intel_dp_get_dpcd(struct intel_dp *intel_dp);
2527
2528 /**
2529  * intel_dp_sync_state - sync the encoder state during init/resume
2530  * @encoder: intel encoder to sync
2531  * @crtc_state: state for the CRTC connected to the encoder
2532  *
2533  * Sync any state stored in the encoder wrt. HW state during driver init
2534  * and system resume.
2535  */
2536 void intel_dp_sync_state(struct intel_encoder *encoder,
2537                          const struct intel_crtc_state *crtc_state)
2538 {
2539         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2540
2541         if (!crtc_state)
2542                 return;
2543
2544         /*
2545          * Don't clobber DPCD if it's been already read out during output
2546          * setup (eDP) or detect.
2547          */
2548         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2549                 intel_dp_get_dpcd(intel_dp);
2550
2551         intel_dp_reset_max_link_params(intel_dp);
2552 }
2553
2554 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
2555                                     struct intel_crtc_state *crtc_state)
2556 {
2557         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2558         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2559         bool fastset = true;
2560
2561         /*
2562          * If BIOS has set an unsupported or non-standard link rate for some
2563          * reason force an encoder recompute and full modeset.
2564          */
2565         if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
2566                                 crtc_state->port_clock) < 0) {
2567                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
2568                             encoder->base.base.id, encoder->base.name);
2569                 crtc_state->uapi.connectors_changed = true;
2570                 fastset = false;
2571         }
2572
2573         /*
2574          * FIXME hack to force full modeset when DSC is being used.
2575          *
2576          * As long as we do not have full state readout and config comparison
2577          * of crtc_state->dsc, we have no way to ensure reliable fastset.
2578          * Remove once we have readout for DSC.
2579          */
2580         if (crtc_state->dsc.compression_enable) {
2581                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
2582                             encoder->base.base.id, encoder->base.name);
2583                 crtc_state->uapi.mode_changed = true;
2584                 fastset = false;
2585         }
2586
2587         if (CAN_PSR(intel_dp)) {
2588                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute PSR state\n",
2589                             encoder->base.base.id, encoder->base.name);
2590                 crtc_state->uapi.mode_changed = true;
2591                 fastset = false;
2592         }
2593
2594         return fastset;
2595 }
2596
2597 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
2598 {
2599         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2600
2601         /* Clear the cached register set to avoid using stale values */
2602
2603         memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
2604
2605         if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
2606                              intel_dp->pcon_dsc_dpcd,
2607                              sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
2608                 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
2609                         DP_PCON_DSC_ENCODER);
2610
2611         drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
2612                     (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
2613 }
2614
2615 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
2616 {
2617         int bw_gbps[] = {9, 18, 24, 32, 40, 48};
2618         int i;
2619
2620         for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
2621                 if (frl_bw_mask & (1 << i))
2622                         return bw_gbps[i];
2623         }
2624         return 0;
2625 }
2626
2627 static int intel_dp_pcon_set_frl_mask(int max_frl)
2628 {
2629         switch (max_frl) {
2630         case 48:
2631                 return DP_PCON_FRL_BW_MASK_48GBPS;
2632         case 40:
2633                 return DP_PCON_FRL_BW_MASK_40GBPS;
2634         case 32:
2635                 return DP_PCON_FRL_BW_MASK_32GBPS;
2636         case 24:
2637                 return DP_PCON_FRL_BW_MASK_24GBPS;
2638         case 18:
2639                 return DP_PCON_FRL_BW_MASK_18GBPS;
2640         case 9:
2641                 return DP_PCON_FRL_BW_MASK_9GBPS;
2642         }
2643
2644         return 0;
2645 }
2646
2647 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
2648 {
2649         struct intel_connector *intel_connector = intel_dp->attached_connector;
2650         struct drm_connector *connector = &intel_connector->base;
2651         int max_frl_rate;
2652         int max_lanes, rate_per_lane;
2653         int max_dsc_lanes, dsc_rate_per_lane;
2654
2655         max_lanes = connector->display_info.hdmi.max_lanes;
2656         rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
2657         max_frl_rate = max_lanes * rate_per_lane;
2658
2659         if (connector->display_info.hdmi.dsc_cap.v_1p2) {
2660                 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
2661                 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
2662                 if (max_dsc_lanes && dsc_rate_per_lane)
2663                         max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
2664         }
2665
2666         return max_frl_rate;
2667 }
2668
2669 static bool
2670 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
2671                              u8 max_frl_bw_mask, u8 *frl_trained_mask)
2672 {
2673         if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
2674             drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
2675             *frl_trained_mask >= max_frl_bw_mask)
2676                 return true;
2677
2678         return false;
2679 }
2680
2681 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
2682 {
2683 #define TIMEOUT_FRL_READY_MS 500
2684 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
2685
2686         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2687         int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
2688         u8 max_frl_bw_mask = 0, frl_trained_mask;
2689         bool is_active;
2690
2691         max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
2692         drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
2693
2694         max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
2695         drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
2696
2697         max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
2698
2699         if (max_frl_bw <= 0)
2700                 return -EINVAL;
2701
2702         max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
2703         drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
2704
2705         if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
2706                 goto frl_trained;
2707
2708         ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
2709         if (ret < 0)
2710                 return ret;
2711         /* Wait for PCON to be FRL Ready */
2712         wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
2713
2714         if (!is_active)
2715                 return -ETIMEDOUT;
2716
2717         ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
2718                                           DP_PCON_ENABLE_SEQUENTIAL_LINK);
2719         if (ret < 0)
2720                 return ret;
2721         ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
2722                                           DP_PCON_FRL_LINK_TRAIN_NORMAL);
2723         if (ret < 0)
2724                 return ret;
2725         ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
2726         if (ret < 0)
2727                 return ret;
2728         /*
2729          * Wait for FRL to be completed
2730          * Check if the HDMI Link is up and active.
2731          */
2732         wait_for(is_active =
2733                  intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
2734                  TIMEOUT_HDMI_LINK_ACTIVE_MS);
2735
2736         if (!is_active)
2737                 return -ETIMEDOUT;
2738
2739 frl_trained:
2740         drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
2741         intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
2742         intel_dp->frl.is_trained = true;
2743         drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
2744
2745         return 0;
2746 }
2747
2748 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
2749 {
2750         if (drm_dp_is_branch(intel_dp->dpcd) &&
2751             intel_dp_has_hdmi_sink(intel_dp) &&
2752             intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
2753                 return true;
2754
2755         return false;
2756 }
2757
2758 static
2759 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
2760 {
2761         int ret;
2762         u8 buf = 0;
2763
2764         /* Set PCON source control mode */
2765         buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
2766
2767         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2768         if (ret < 0)
2769                 return ret;
2770
2771         /* Set HDMI LINK ENABLE */
2772         buf |= DP_PCON_ENABLE_HDMI_LINK;
2773         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2774         if (ret < 0)
2775                 return ret;
2776
2777         return 0;
2778 }
2779
2780 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
2781 {
2782         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2783
2784         /*
2785          * Always go for FRL training if:
2786          * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
2787          * -sink is HDMI2.1
2788          */
2789         if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
2790             !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
2791             intel_dp->frl.is_trained)
2792                 return;
2793
2794         if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
2795                 int ret, mode;
2796
2797                 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
2798                 ret = intel_dp_pcon_set_tmds_mode(intel_dp);
2799                 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
2800
2801                 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
2802                         drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
2803         } else {
2804                 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
2805         }
2806 }
2807
2808 static int
2809 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
2810 {
2811         int vactive = crtc_state->hw.adjusted_mode.vdisplay;
2812
2813         return intel_hdmi_dsc_get_slice_height(vactive);
2814 }
2815
2816 static int
2817 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
2818                              const struct intel_crtc_state *crtc_state)
2819 {
2820         struct intel_connector *intel_connector = intel_dp->attached_connector;
2821         struct drm_connector *connector = &intel_connector->base;
2822         int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
2823         int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
2824         int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
2825         int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
2826
2827         return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
2828                                              pcon_max_slice_width,
2829                                              hdmi_max_slices, hdmi_throughput);
2830 }
2831
2832 static int
2833 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
2834                           const struct intel_crtc_state *crtc_state,
2835                           int num_slices, int slice_width)
2836 {
2837         struct intel_connector *intel_connector = intel_dp->attached_connector;
2838         struct drm_connector *connector = &intel_connector->base;
2839         int output_format = crtc_state->output_format;
2840         bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
2841         int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
2842         int hdmi_max_chunk_bytes =
2843                 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
2844
2845         return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
2846                                       num_slices, output_format, hdmi_all_bpp,
2847                                       hdmi_max_chunk_bytes);
2848 }
2849
2850 void
2851 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
2852                             const struct intel_crtc_state *crtc_state)
2853 {
2854         u8 pps_param[6];
2855         int slice_height;
2856         int slice_width;
2857         int num_slices;
2858         int bits_per_pixel;
2859         int ret;
2860         struct intel_connector *intel_connector = intel_dp->attached_connector;
2861         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2862         struct drm_connector *connector;
2863         bool hdmi_is_dsc_1_2;
2864
2865         if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
2866                 return;
2867
2868         if (!intel_connector)
2869                 return;
2870         connector = &intel_connector->base;
2871         hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
2872
2873         if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
2874             !hdmi_is_dsc_1_2)
2875                 return;
2876
2877         slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
2878         if (!slice_height)
2879                 return;
2880
2881         num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
2882         if (!num_slices)
2883                 return;
2884
2885         slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
2886                                    num_slices);
2887
2888         bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
2889                                                    num_slices, slice_width);
2890         if (!bits_per_pixel)
2891                 return;
2892
2893         pps_param[0] = slice_height & 0xFF;
2894         pps_param[1] = slice_height >> 8;
2895         pps_param[2] = slice_width & 0xFF;
2896         pps_param[3] = slice_width >> 8;
2897         pps_param[4] = bits_per_pixel & 0xFF;
2898         pps_param[5] = (bits_per_pixel >> 8) & 0x3;
2899
2900         ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
2901         if (ret < 0)
2902                 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
2903 }
2904
2905 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
2906                                            const struct intel_crtc_state *crtc_state)
2907 {
2908         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2909         bool ycbcr444_to_420 = false;
2910         bool rgb_to_ycbcr = false;
2911         u8 tmp;
2912
2913         if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
2914                 return;
2915
2916         if (!drm_dp_is_branch(intel_dp->dpcd))
2917                 return;
2918
2919         tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0;
2920
2921         if (drm_dp_dpcd_writeb(&intel_dp->aux,
2922                                DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
2923                 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
2924                             str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));
2925
2926         if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2927                 switch (crtc_state->output_format) {
2928                 case INTEL_OUTPUT_FORMAT_YCBCR420:
2929                         break;
2930                 case INTEL_OUTPUT_FORMAT_YCBCR444:
2931                         ycbcr444_to_420 = true;
2932                         break;
2933                 case INTEL_OUTPUT_FORMAT_RGB:
2934                         rgb_to_ycbcr = true;
2935                         ycbcr444_to_420 = true;
2936                         break;
2937                 default:
2938                         MISSING_CASE(crtc_state->output_format);
2939                         break;
2940                 }
2941         } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
2942                 switch (crtc_state->output_format) {
2943                 case INTEL_OUTPUT_FORMAT_YCBCR444:
2944                         break;
2945                 case INTEL_OUTPUT_FORMAT_RGB:
2946                         rgb_to_ycbcr = true;
2947                         break;
2948                 default:
2949                         MISSING_CASE(crtc_state->output_format);
2950                         break;
2951                 }
2952         }
2953
2954         tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
2955
2956         if (drm_dp_dpcd_writeb(&intel_dp->aux,
2957                                DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
2958                 drm_dbg_kms(&i915->drm,
2959                             "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
2960                             str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
2961
2962         tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
2963
2964         if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
2965                 drm_dbg_kms(&i915->drm,
2966                             "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
2967                             str_enable_disable(tmp));
2968 }
2969
2970 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
2971 {
2972         u8 dprx = 0;
2973
2974         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
2975                               &dprx) != 1)
2976                 return false;
2977         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
2978 }
2979
2980 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
2981 {
2982         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2983
2984         /*
2985          * Clear the cached register set to avoid using stale values
2986          * for the sinks that do not support DSC.
2987          */
2988         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
2989
2990         /* Clear fec_capable to avoid using stale values */
2991         intel_dp->fec_capable = 0;
2992
2993         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
2994         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
2995             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2996                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
2997                                      intel_dp->dsc_dpcd,
2998                                      sizeof(intel_dp->dsc_dpcd)) < 0)
2999                         drm_err(&i915->drm,
3000                                 "Failed to read DPCD register 0x%x\n",
3001                                 DP_DSC_SUPPORT);
3002
3003                 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
3004                             (int)sizeof(intel_dp->dsc_dpcd),
3005                             intel_dp->dsc_dpcd);
3006
3007                 /* FEC is supported only on DP 1.4 */
3008                 if (!intel_dp_is_edp(intel_dp) &&
3009                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
3010                                       &intel_dp->fec_capable) < 0)
3011                         drm_err(&i915->drm,
3012                                 "Failed to read FEC DPCD register\n");
3013
3014                 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
3015                             intel_dp->fec_capable);
3016         }
3017 }
3018
3019 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
3020                                      struct drm_display_mode *mode)
3021 {
3022         struct intel_dp *intel_dp = intel_attached_dp(connector);
3023         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3024         int n = intel_dp->mso_link_count;
3025         int overlap = intel_dp->mso_pixel_overlap;
3026
3027         if (!mode || !n)
3028                 return;
3029
3030         mode->hdisplay = (mode->hdisplay - overlap) * n;
3031         mode->hsync_start = (mode->hsync_start - overlap) * n;
3032         mode->hsync_end = (mode->hsync_end - overlap) * n;
3033         mode->htotal = (mode->htotal - overlap) * n;
3034         mode->clock *= n;
3035
3036         drm_mode_set_name(mode);
3037
3038         drm_dbg_kms(&i915->drm,
3039                     "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
3040                     connector->base.base.id, connector->base.name,
3041                     DRM_MODE_ARG(mode));
3042 }
3043
3044 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
3045 {
3046         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3047         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3048         struct intel_connector *connector = intel_dp->attached_connector;
3049
3050         if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
3051                 /*
3052                  * This is a big fat ugly hack.
3053                  *
3054                  * Some machines in UEFI boot mode provide us a VBT that has 18
3055                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3056                  * unknown we fail to light up. Yet the same BIOS boots up with
3057                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3058                  * max, not what it tells us to use.
3059                  *
3060                  * Note: This will still be broken if the eDP panel is not lit
3061                  * up by the BIOS, and thus we can't get the mode at module
3062                  * load.
3063                  */
3064                 drm_dbg_kms(&dev_priv->drm,
3065                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3066                             pipe_bpp, connector->panel.vbt.edp.bpp);
3067                 connector->panel.vbt.edp.bpp = pipe_bpp;
3068         }
3069 }
3070
3071 static void intel_edp_mso_init(struct intel_dp *intel_dp)
3072 {
3073         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3074         struct intel_connector *connector = intel_dp->attached_connector;
3075         struct drm_display_info *info = &connector->base.display_info;
3076         u8 mso;
3077
3078         if (intel_dp->edp_dpcd[0] < DP_EDP_14)
3079                 return;
3080
3081         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
3082                 drm_err(&i915->drm, "Failed to read MSO cap\n");
3083                 return;
3084         }
3085
3086         /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
3087         mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
3088         if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
3089                 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
3090                 mso = 0;
3091         }
3092
3093         if (mso) {
3094                 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
3095                             mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
3096                             info->mso_pixel_overlap);
3097                 if (!HAS_MSO(i915)) {
3098                         drm_err(&i915->drm, "No source MSO support, disabling\n");
3099                         mso = 0;
3100                 }
3101         }
3102
3103         intel_dp->mso_link_count = mso;
3104         intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
3105 }
3106
3107 static bool
3108 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3109 {
3110         struct drm_i915_private *dev_priv =
3111                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3112
3113         /* this function is meant to be called only once */
3114         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
3115
3116         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
3117                 return false;
3118
3119         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3120                          drm_dp_is_branch(intel_dp->dpcd));
3121
3122         /*
3123          * Read the eDP display control registers.
3124          *
3125          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3126          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3127          * set, but require eDP 1.4+ detection (e.g. for supported link rates
3128          * method). The display control registers should read zero if they're
3129          * not supported anyway.
3130          */
3131         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3132                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3133                              sizeof(intel_dp->edp_dpcd)) {
3134                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
3135                             (int)sizeof(intel_dp->edp_dpcd),
3136                             intel_dp->edp_dpcd);
3137
3138                 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
3139         }
3140
3141         /*
3142          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3143          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3144          */
3145         intel_psr_init_dpcd(intel_dp);
3146
3147         /* Clear the default sink rates */
3148         intel_dp->num_sink_rates = 0;
3149
3150         /* Read the eDP 1.4+ supported link rates. */
3151         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3152                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3153                 int i;
3154
3155                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3156                                 sink_rates, sizeof(sink_rates));
3157
3158                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3159                         int val = le16_to_cpu(sink_rates[i]);
3160
3161                         if (val == 0)
3162                                 break;
3163
3164                         /* Value read multiplied by 200kHz gives the per-lane
3165                          * link rate in kHz. The source rates are, however,
3166                          * stored in terms of LS_Clk kHz. The full conversion
3167                          * back to symbols is
3168                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3169                          */
3170                         intel_dp->sink_rates[i] = (val * 200) / 10;
3171                 }
3172                 intel_dp->num_sink_rates = i;
3173         }
3174
3175         /*
3176          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3177          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3178          */
3179         if (intel_dp->num_sink_rates)
3180                 intel_dp->use_rate_select = true;
3181         else
3182                 intel_dp_set_sink_rates(intel_dp);
3183         intel_dp_set_max_sink_lane_count(intel_dp);
3184
3185         /* Read the eDP DSC DPCD registers */
3186         if (HAS_DSC(dev_priv))
3187                 intel_dp_get_dsc_sink_cap(intel_dp);
3188
3189         /*
3190          * If needed, program our source OUI so we can make various Intel-specific AUX services
3191          * available (such as HDR backlight controls)
3192          */
3193         intel_edp_init_source_oui(intel_dp, true);
3194
3195         return true;
3196 }
3197
3198 static bool
3199 intel_dp_has_sink_count(struct intel_dp *intel_dp)
3200 {
3201         if (!intel_dp->attached_connector)
3202                 return false;
3203
3204         return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
3205                                           intel_dp->dpcd,
3206                                           &intel_dp->desc);
3207 }
3208
3209 static bool
3210 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3211 {
3212         int ret;
3213
3214         if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
3215                 return false;
3216
3217         /*
3218          * Don't clobber cached eDP rates. Also skip re-reading
3219          * the OUI/ID since we know it won't change.
3220          */
3221         if (!intel_dp_is_edp(intel_dp)) {
3222                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3223                                  drm_dp_is_branch(intel_dp->dpcd));
3224
3225                 intel_dp_set_sink_rates(intel_dp);
3226                 intel_dp_set_max_sink_lane_count(intel_dp);
3227                 intel_dp_set_common_rates(intel_dp);
3228         }
3229
3230         if (intel_dp_has_sink_count(intel_dp)) {
3231                 ret = drm_dp_read_sink_count(&intel_dp->aux);
3232                 if (ret < 0)
3233                         return false;
3234
3235                 /*
3236                  * Sink count can change between short pulse hpd hence
3237                  * a member variable in intel_dp will track any changes
3238                  * between short pulse interrupts.
3239                  */
3240                 intel_dp->sink_count = ret;
3241
3242                 /*
3243                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3244                  * a dongle is present but no display. Unless we require to know
3245                  * if a dongle is present or not, we don't need to update
3246                  * downstream port information. So, an early return here saves
3247                  * time from performing other operations which are not required.
3248                  */
3249                 if (!intel_dp->sink_count)
3250                         return false;
3251         }
3252
3253         return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
3254                                            intel_dp->downstream_ports) == 0;
3255 }
3256
3257 static bool
3258 intel_dp_can_mst(struct intel_dp *intel_dp)
3259 {
3260         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3261
3262         return i915->params.enable_dp_mst &&
3263                 intel_dp_mst_source_support(intel_dp) &&
3264                 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
3265 }
3266
3267 static void
3268 intel_dp_configure_mst(struct intel_dp *intel_dp)
3269 {
3270         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3271         struct intel_encoder *encoder =
3272                 &dp_to_dig_port(intel_dp)->base;
3273         bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
3274
3275         drm_dbg_kms(&i915->drm,
3276                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
3277                     encoder->base.base.id, encoder->base.name,
3278                     str_yes_no(intel_dp_mst_source_support(intel_dp)),
3279                     str_yes_no(sink_can_mst),
3280                     str_yes_no(i915->params.enable_dp_mst));
3281
3282         if (!intel_dp_mst_source_support(intel_dp))
3283                 return;
3284
3285         intel_dp->is_mst = sink_can_mst &&
3286                 i915->params.enable_dp_mst;
3287
3288         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3289                                         intel_dp->is_mst);
3290 }
3291
3292 static bool
3293 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
3294 {
3295         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
3296 }
3297
3298 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
3299 {
3300         int retry;
3301
3302         for (retry = 0; retry < 3; retry++) {
3303                 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
3304                                       &esi[1], 3) == 3)
3305                         return true;
3306         }
3307
3308         return false;
3309 }
3310
3311 bool
3312 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
3313                        const struct drm_connector_state *conn_state)
3314 {
3315         /*
3316          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
3317          * of Color Encoding Format and Content Color Gamut], in order to
3318          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
3319          */
3320         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3321                 return true;
3322
3323         switch (conn_state->colorspace) {
3324         case DRM_MODE_COLORIMETRY_SYCC_601:
3325         case DRM_MODE_COLORIMETRY_OPYCC_601:
3326         case DRM_MODE_COLORIMETRY_BT2020_YCC:
3327         case DRM_MODE_COLORIMETRY_BT2020_RGB:
3328         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
3329                 return true;
3330         default:
3331                 break;
3332         }
3333
3334         return false;
3335 }
3336
3337 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
3338                                      struct dp_sdp *sdp, size_t size)
3339 {
3340         size_t length = sizeof(struct dp_sdp);
3341
3342         if (size < length)
3343                 return -ENOSPC;
3344
3345         memset(sdp, 0, size);
3346
3347         /*
3348          * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
3349          * VSC SDP Header Bytes
3350          */
3351         sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
3352         sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
3353         sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
3354         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
3355
3356         /*
3357          * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
3358          * per DP 1.4a spec.
3359          */
3360         if (vsc->revision != 0x5)
3361                 goto out;
3362
3363         /* VSC SDP Payload for DB16 through DB18 */
3364         /* Pixel Encoding and Colorimetry Formats  */
3365         sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3366         sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3367
3368         switch (vsc->bpc) {
3369         case 6:
3370                 /* 6bpc: 0x0 */
3371                 break;
3372         case 8:
3373                 sdp->db[17] = 0x1; /* DB17[3:0] */
3374                 break;
3375         case 10:
3376                 sdp->db[17] = 0x2;
3377                 break;
3378         case 12:
3379                 sdp->db[17] = 0x3;
3380                 break;
3381         case 16:
3382                 sdp->db[17] = 0x4;
3383                 break;
3384         default:
3385                 MISSING_CASE(vsc->bpc);
3386                 break;
3387         }
3388         /* Dynamic Range and Component Bit Depth */
3389         if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3390                 sdp->db[17] |= 0x80;  /* DB17[7] */
3391
3392         /* Content Type */
3393         sdp->db[18] = vsc->content_type & 0x7;
3394
3395 out:
3396         return length;
3397 }
3398
3399 static ssize_t
3400 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
3401                                          const struct hdmi_drm_infoframe *drm_infoframe,
3402                                          struct dp_sdp *sdp,
3403                                          size_t size)
3404 {
3405         size_t length = sizeof(struct dp_sdp);
3406         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
3407         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
3408         ssize_t len;
3409
3410         if (size < length)
3411                 return -ENOSPC;
3412
3413         memset(sdp, 0, size);
3414
3415         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
3416         if (len < 0) {
3417                 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
3418                 return -ENOSPC;
3419         }
3420
3421         if (len != infoframe_size) {
3422                 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
3423                 return -ENOSPC;
3424         }
3425
3426         /*
3427          * Set up the infoframe sdp packet for HDR static metadata.
3428          * Prepare VSC Header for SU as per DP 1.4a spec,
3429          * Table 2-100 and Table 2-101
3430          */
3431
3432         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
3433         sdp->sdp_header.HB0 = 0;
3434         /*
3435          * Packet Type 80h + Non-audio INFOFRAME Type value
3436          * HDMI_INFOFRAME_TYPE_DRM: 0x87
3437          * - 80h + Non-audio INFOFRAME Type value
3438          * - InfoFrame Type: 0x07
3439          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
3440          */
3441         sdp->sdp_header.HB1 = drm_infoframe->type;
3442         /*
3443          * Least Significant Eight Bits of (Data Byte Count – 1)
3444          * infoframe_size - 1
3445          */
3446         sdp->sdp_header.HB2 = 0x1D;
3447         /* INFOFRAME SDP Version Number */
3448         sdp->sdp_header.HB3 = (0x13 << 2);
3449         /* CTA Header Byte 2 (INFOFRAME Version Number) */
3450         sdp->db[0] = drm_infoframe->version;
3451         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3452         sdp->db[1] = drm_infoframe->length;
3453         /*
3454          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
3455          * HDMI_INFOFRAME_HEADER_SIZE
3456          */
3457         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
3458         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
3459                HDMI_DRM_INFOFRAME_SIZE);
3460
3461         /*
3462          * Size of DP infoframe sdp packet for HDR static metadata consists of
3463          * - DP SDP Header(struct dp_sdp_header): 4 bytes
3464          * - Two Data Blocks: 2 bytes
3465          *    CTA Header Byte2 (INFOFRAME Version Number)
3466          *    CTA Header Byte3 (Length of INFOFRAME)
3467          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
3468          *
3469          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
3470          * infoframe size. But GEN11+ has larger than that size, write_infoframe
3471          * will pad rest of the size.
3472          */
3473         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
3474 }
3475
3476 static void intel_write_dp_sdp(struct intel_encoder *encoder,
3477                                const struct intel_crtc_state *crtc_state,
3478                                unsigned int type)
3479 {
3480         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3481         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3482         struct dp_sdp sdp = {};
3483         ssize_t len;
3484
3485         if ((crtc_state->infoframes.enable &
3486              intel_hdmi_infoframe_enable(type)) == 0)
3487                 return;
3488
3489         switch (type) {
3490         case DP_SDP_VSC:
3491                 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
3492                                             sizeof(sdp));
3493                 break;
3494         case HDMI_PACKET_TYPE_GAMUT_METADATA:
3495                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
3496                                                                &crtc_state->infoframes.drm.drm,
3497                                                                &sdp, sizeof(sdp));
3498                 break;
3499         default:
3500                 MISSING_CASE(type);
3501                 return;
3502         }
3503
3504         if (drm_WARN_ON(&dev_priv->drm, len < 0))
3505                 return;
3506
3507         dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
3508 }
3509
3510 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
3511                             const struct intel_crtc_state *crtc_state,
3512                             const struct drm_dp_vsc_sdp *vsc)
3513 {
3514         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3515         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3516         struct dp_sdp sdp = {};
3517         ssize_t len;
3518
3519         len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
3520
3521         if (drm_WARN_ON(&dev_priv->drm, len < 0))
3522                 return;
3523
3524         dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
3525                                         &sdp, len);
3526 }
3527
3528 void intel_dp_set_infoframes(struct intel_encoder *encoder,
3529                              bool enable,
3530                              const struct intel_crtc_state *crtc_state,
3531                              const struct drm_connector_state *conn_state)
3532 {
3533         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3534         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
3535         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
3536                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
3537                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
3538         u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
3539
3540         /* TODO: Add DSC case (DIP_ENABLE_PPS) */
3541         /* When PSR is enabled, this routine doesn't disable VSC DIP */
3542         if (!crtc_state->has_psr)
3543                 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
3544
3545         intel_de_write(dev_priv, reg, val);
3546         intel_de_posting_read(dev_priv, reg);
3547
3548         if (!enable)
3549                 return;
3550
3551         /* When PSR is enabled, VSC SDP is handled by PSR routine */
3552         if (!crtc_state->has_psr)
3553                 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
3554
3555         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
3556 }
3557
3558 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
3559                                    const void *buffer, size_t size)
3560 {
3561         const struct dp_sdp *sdp = buffer;
3562
3563         if (size < sizeof(struct dp_sdp))
3564                 return -EINVAL;
3565
3566         memset(vsc, 0, sizeof(*vsc));
3567
3568         if (sdp->sdp_header.HB0 != 0)
3569                 return -EINVAL;
3570
3571         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
3572                 return -EINVAL;
3573
3574         vsc->sdp_type = sdp->sdp_header.HB1;
3575         vsc->revision = sdp->sdp_header.HB2;
3576         vsc->length = sdp->sdp_header.HB3;
3577
3578         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
3579             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
3580                 /*
3581                  * - HB2 = 0x2, HB3 = 0x8
3582                  *   VSC SDP supporting 3D stereo + PSR
3583                  * - HB2 = 0x4, HB3 = 0xe
3584                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
3585                  *   first scan line of the SU region (applies to eDP v1.4b
3586                  *   and higher).
3587                  */
3588                 return 0;
3589         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
3590                 /*
3591                  * - HB2 = 0x5, HB3 = 0x13
3592                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
3593                  *   Format.
3594                  */
3595                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
3596                 vsc->colorimetry = sdp->db[16] & 0xf;
3597                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
3598
3599                 switch (sdp->db[17] & 0x7) {
3600                 case 0x0:
3601                         vsc->bpc = 6;
3602                         break;
3603                 case 0x1:
3604                         vsc->bpc = 8;
3605                         break;
3606                 case 0x2:
3607                         vsc->bpc = 10;
3608                         break;
3609                 case 0x3:
3610                         vsc->bpc = 12;
3611                         break;
3612                 case 0x4:
3613                         vsc->bpc = 16;
3614                         break;
3615                 default:
3616                         MISSING_CASE(sdp->db[17] & 0x7);
3617                         return -EINVAL;
3618                 }
3619
3620                 vsc->content_type = sdp->db[18] & 0x7;
3621         } else {
3622                 return -EINVAL;
3623         }
3624
3625         return 0;
3626 }
3627
3628 static int
3629 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
3630                                            const void *buffer, size_t size)
3631 {
3632         int ret;
3633
3634         const struct dp_sdp *sdp = buffer;
3635
3636         if (size < sizeof(struct dp_sdp))
3637                 return -EINVAL;
3638
3639         if (sdp->sdp_header.HB0 != 0)
3640                 return -EINVAL;
3641
3642         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
3643                 return -EINVAL;
3644
3645         /*
3646          * Least Significant Eight Bits of (Data Byte Count – 1)
3647          * 1Dh (i.e., Data Byte Count = 30 bytes).
3648          */
3649         if (sdp->sdp_header.HB2 != 0x1D)
3650                 return -EINVAL;
3651
3652         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
3653         if ((sdp->sdp_header.HB3 & 0x3) != 0)
3654                 return -EINVAL;
3655
3656         /* INFOFRAME SDP Version Number */
3657         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
3658                 return -EINVAL;
3659
3660         /* CTA Header Byte 2 (INFOFRAME Version Number) */
3661         if (sdp->db[0] != 1)
3662                 return -EINVAL;
3663
3664         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3665         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
3666                 return -EINVAL;
3667
3668         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
3669                                              HDMI_DRM_INFOFRAME_SIZE);
3670
3671         return ret;
3672 }
3673
3674 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
3675                                   struct intel_crtc_state *crtc_state,
3676                                   struct drm_dp_vsc_sdp *vsc)
3677 {
3678         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3679         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3680         unsigned int type = DP_SDP_VSC;
3681         struct dp_sdp sdp = {};
3682         int ret;
3683
3684         /* When PSR is enabled, VSC SDP is handled by PSR routine */
3685         if (crtc_state->has_psr)
3686                 return;
3687
3688         if ((crtc_state->infoframes.enable &
3689              intel_hdmi_infoframe_enable(type)) == 0)
3690                 return;
3691
3692         dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
3693
3694         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
3695
3696         if (ret)
3697                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
3698 }
3699
3700 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
3701                                                      struct intel_crtc_state *crtc_state,
3702                                                      struct hdmi_drm_infoframe *drm_infoframe)
3703 {
3704         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3705         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3706         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
3707         struct dp_sdp sdp = {};
3708         int ret;
3709
3710         if ((crtc_state->infoframes.enable &
3711             intel_hdmi_infoframe_enable(type)) == 0)
3712                 return;
3713
3714         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
3715                                  sizeof(sdp));
3716
3717         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
3718                                                          sizeof(sdp));
3719
3720         if (ret)
3721                 drm_dbg_kms(&dev_priv->drm,
3722                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
3723 }
3724
3725 void intel_read_dp_sdp(struct intel_encoder *encoder,
3726                        struct intel_crtc_state *crtc_state,
3727                        unsigned int type)
3728 {
3729         switch (type) {
3730         case DP_SDP_VSC:
3731                 intel_read_dp_vsc_sdp(encoder, crtc_state,
3732                                       &crtc_state->infoframes.vsc);
3733                 break;
3734         case HDMI_PACKET_TYPE_GAMUT_METADATA:
3735                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
3736                                                          &crtc_state->infoframes.drm.drm);
3737                 break;
3738         default:
3739                 MISSING_CASE(type);
3740                 break;
3741         }
3742 }
3743
3744 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3745 {
3746         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3747         int status = 0;
3748         int test_link_rate;
3749         u8 test_lane_count, test_link_bw;
3750         /* (DP CTS 1.2)
3751          * 4.3.1.11
3752          */
3753         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3754         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3755                                    &test_lane_count);
3756
3757         if (status <= 0) {
3758                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
3759                 return DP_TEST_NAK;
3760         }
3761         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3762
3763         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3764                                    &test_link_bw);
3765         if (status <= 0) {
3766                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
3767                 return DP_TEST_NAK;
3768         }
3769         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3770
3771         /* Validate the requested link rate and lane count */
3772         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
3773                                         test_lane_count))
3774                 return DP_TEST_NAK;
3775
3776         intel_dp->compliance.test_lane_count = test_lane_count;
3777         intel_dp->compliance.test_link_rate = test_link_rate;
3778
3779         return DP_TEST_ACK;
3780 }
3781
3782 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3783 {
3784         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3785         u8 test_pattern;
3786         u8 test_misc;
3787         __be16 h_width, v_height;
3788         int status = 0;
3789
3790         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
3791         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
3792                                    &test_pattern);
3793         if (status <= 0) {
3794                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
3795                 return DP_TEST_NAK;
3796         }
3797         if (test_pattern != DP_COLOR_RAMP)
3798                 return DP_TEST_NAK;
3799
3800         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3801                                   &h_width, 2);
3802         if (status <= 0) {
3803                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
3804                 return DP_TEST_NAK;
3805         }
3806
3807         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3808                                   &v_height, 2);
3809         if (status <= 0) {
3810                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
3811                 return DP_TEST_NAK;
3812         }
3813
3814         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
3815                                    &test_misc);
3816         if (status <= 0) {
3817                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
3818                 return DP_TEST_NAK;
3819         }
3820         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
3821                 return DP_TEST_NAK;
3822         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
3823                 return DP_TEST_NAK;
3824         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
3825         case DP_TEST_BIT_DEPTH_6:
3826                 intel_dp->compliance.test_data.bpc = 6;
3827                 break;
3828         case DP_TEST_BIT_DEPTH_8:
3829                 intel_dp->compliance.test_data.bpc = 8;
3830                 break;
3831         default:
3832                 return DP_TEST_NAK;
3833         }
3834
3835         intel_dp->compliance.test_data.video_pattern = test_pattern;
3836         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
3837         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
3838         /* Set test active flag here so userspace doesn't interrupt things */
3839         intel_dp->compliance.test_active = true;
3840
3841         return DP_TEST_ACK;
3842 }
3843
3844 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
3845 {
3846         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3847         u8 test_result = DP_TEST_ACK;
3848         struct intel_connector *intel_connector = intel_dp->attached_connector;
3849         struct drm_connector *connector = &intel_connector->base;
3850
3851         if (intel_connector->detect_edid == NULL ||
3852             connector->edid_corrupt ||
3853             intel_dp->aux.i2c_defer_count > 6) {
3854                 /* Check EDID read for NACKs, DEFERs and corruption
3855                  * (DP CTS 1.2 Core r1.1)
3856                  *    4.2.2.4 : Failed EDID read, I2C_NAK
3857                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
3858                  *    4.2.2.6 : EDID corruption detected
3859                  * Use failsafe mode for all cases
3860                  */
3861                 if (intel_dp->aux.i2c_nack_count > 0 ||
3862                         intel_dp->aux.i2c_defer_count > 0)
3863                         drm_dbg_kms(&i915->drm,
3864                                     "EDID read had %d NACKs, %d DEFERs\n",
3865                                     intel_dp->aux.i2c_nack_count,
3866                                     intel_dp->aux.i2c_defer_count);
3867                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
3868         } else {
3869                 /* FIXME: Get rid of drm_edid_raw() */
3870                 const struct edid *block = drm_edid_raw(intel_connector->detect_edid);
3871
3872                 /* We have to write the checksum of the last block read */
3873                 block += block->extensions;
3874
3875                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
3876                                        block->checksum) <= 0)
3877                         drm_dbg_kms(&i915->drm,
3878                                     "Failed to write EDID checksum\n");
3879
3880                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3881                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
3882         }
3883
3884         /* Set test active flag here so userspace doesn't interrupt things */
3885         intel_dp->compliance.test_active = true;
3886
3887         return test_result;
3888 }
3889
3890 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
3891                                         const struct intel_crtc_state *crtc_state)
3892 {
3893         struct drm_i915_private *dev_priv =
3894                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3895         struct drm_dp_phy_test_params *data =
3896                         &intel_dp->compliance.test_data.phytest;
3897         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3898         enum pipe pipe = crtc->pipe;
3899         u32 pattern_val;
3900
3901         switch (data->phy_pattern) {
3902         case DP_PHY_TEST_PATTERN_NONE:
3903                 drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
3904                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
3905                 break;
3906         case DP_PHY_TEST_PATTERN_D10_2:
3907                 drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
3908                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3909                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
3910                 break;
3911         case DP_PHY_TEST_PATTERN_ERROR_COUNT:
3912                 drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
3913                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3914                                DDI_DP_COMP_CTL_ENABLE |
3915                                DDI_DP_COMP_CTL_SCRAMBLED_0);
3916                 break;
3917         case DP_PHY_TEST_PATTERN_PRBS7:
3918                 drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
3919                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3920                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
3921                 break;
3922         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
3923                 /*
3924                  * FIXME: Ideally pattern should come from DPCD 0x250. As
3925                  * current firmware of DPR-100 could not set it, so hardcoding
3926                  * now for complaince test.
3927                  */
3928                 drm_dbg_kms(&dev_priv->drm,
3929                             "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
3930                 pattern_val = 0x3e0f83e0;
3931                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
3932                 pattern_val = 0x0f83e0f8;
3933                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
3934                 pattern_val = 0x0000f83e;
3935                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
3936                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3937                                DDI_DP_COMP_CTL_ENABLE |
3938                                DDI_DP_COMP_CTL_CUSTOM80);
3939                 break;
3940         case DP_PHY_TEST_PATTERN_CP2520:
3941                 /*
3942                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
3943                  * current firmware of DPR-100 could not set it, so hardcoding
3944                  * now for complaince test.
3945                  */
3946                 drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
3947                 pattern_val = 0xFB;
3948                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3949                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
3950                                pattern_val);
3951                 break;
3952         default:
3953                 WARN(1, "Invalid Phy Test Pattern\n");
3954         }
3955 }
3956
3957 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
3958                                          const struct intel_crtc_state *crtc_state)
3959 {
3960         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3961         struct drm_dp_phy_test_params *data =
3962                 &intel_dp->compliance.test_data.phytest;
3963         u8 link_status[DP_LINK_STATUS_SIZE];
3964
3965         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3966                                              link_status) < 0) {
3967                 drm_dbg_kms(&i915->drm, "failed to get link status\n");
3968                 return;
3969         }
3970
3971         /* retrieve vswing & pre-emphasis setting */
3972         intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
3973                                   link_status);
3974
3975         intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
3976
3977         intel_dp_phy_pattern_update(intel_dp, crtc_state);
3978
3979         drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3980                           intel_dp->train_set, crtc_state->lane_count);
3981
3982         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
3983                                     link_status[DP_DPCD_REV]);
3984 }
3985
3986 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3987 {
3988         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3989         struct drm_dp_phy_test_params *data =
3990                 &intel_dp->compliance.test_data.phytest;
3991
3992         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
3993                 drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");
3994                 return DP_TEST_NAK;
3995         }
3996
3997         /* Set test active flag here so userspace doesn't interrupt things */
3998         intel_dp->compliance.test_active = true;
3999
4000         return DP_TEST_ACK;
4001 }
4002
4003 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4004 {
4005         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4006         u8 response = DP_TEST_NAK;
4007         u8 request = 0;
4008         int status;
4009
4010         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4011         if (status <= 0) {
4012                 drm_dbg_kms(&i915->drm,
4013                             "Could not read test request from sink\n");
4014                 goto update_status;
4015         }
4016
4017         switch (request) {
4018         case DP_TEST_LINK_TRAINING:
4019                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
4020                 response = intel_dp_autotest_link_training(intel_dp);
4021                 break;
4022         case DP_TEST_LINK_VIDEO_PATTERN:
4023                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
4024                 response = intel_dp_autotest_video_pattern(intel_dp);
4025                 break;
4026         case DP_TEST_LINK_EDID_READ:
4027                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
4028                 response = intel_dp_autotest_edid(intel_dp);
4029                 break;
4030         case DP_TEST_LINK_PHY_TEST_PATTERN:
4031                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
4032                 response = intel_dp_autotest_phy_pattern(intel_dp);
4033                 break;
4034         default:
4035                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
4036                             request);
4037                 break;
4038         }
4039
4040         if (response & DP_TEST_ACK)
4041                 intel_dp->compliance.test_type = request;
4042
4043 update_status:
4044         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4045         if (status <= 0)
4046                 drm_dbg_kms(&i915->drm,
4047                             "Could not write test response to sink\n");
4048 }
4049
4050 static bool intel_dp_link_ok(struct intel_dp *intel_dp,
4051                              u8 link_status[DP_LINK_STATUS_SIZE])
4052 {
4053         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4054         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4055         bool uhbr = intel_dp->link_rate >= 1000000;
4056         bool ok;
4057
4058         if (uhbr)
4059                 ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
4060                                                           intel_dp->lane_count);
4061         else
4062                 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4063
4064         if (ok)
4065                 return true;
4066
4067         intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
4068         drm_dbg_kms(&i915->drm,
4069                     "[ENCODER:%d:%s] %s link not ok, retraining\n",
4070                     encoder->base.base.id, encoder->base.name,
4071                     uhbr ? "128b/132b" : "8b/10b");
4072
4073         return false;
4074 }
4075
4076 static void
4077 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
4078 {
4079         bool handled = false;
4080
4081         drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled);
4082
4083         if (esi[1] & DP_CP_IRQ) {
4084                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4085                 ack[1] |= DP_CP_IRQ;
4086         }
4087 }
4088
4089 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
4090 {
4091         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4092         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4093         u8 link_status[DP_LINK_STATUS_SIZE] = {};
4094         const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
4095
4096         if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
4097                              esi_link_status_size) != esi_link_status_size) {
4098                 drm_err(&i915->drm,
4099                         "[ENCODER:%d:%s] Failed to read link status\n",
4100                         encoder->base.base.id, encoder->base.name);
4101                 return false;
4102         }
4103
4104         return intel_dp_link_ok(intel_dp, link_status);
4105 }
4106
4107 /**
4108  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
4109  * @intel_dp: Intel DP struct
4110  *
4111  * Read any pending MST interrupts, call MST core to handle these and ack the
4112  * interrupts. Check if the main and AUX link state is ok.
4113  *
4114  * Returns:
4115  * - %true if pending interrupts were serviced (or no interrupts were
4116  *   pending) w/o detecting an error condition.
4117  * - %false if an error condition - like AUX failure or a loss of link - is
4118  *   detected, which needs servicing from the hotplug work.
4119  */
4120 static bool
4121 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4122 {
4123         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4124         bool link_ok = true;
4125
4126         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
4127
4128         for (;;) {
4129                 u8 esi[4] = {};
4130                 u8 ack[4] = {};
4131
4132                 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
4133                         drm_dbg_kms(&i915->drm,
4134                                     "failed to get ESI - device may have failed\n");
4135                         link_ok = false;
4136
4137                         break;
4138                 }
4139
4140                 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
4141
4142                 if (intel_dp->active_mst_links > 0 && link_ok &&
4143                     esi[3] & LINK_STATUS_CHANGED) {
4144                         if (!intel_dp_mst_link_status(intel_dp))
4145                                 link_ok = false;
4146                         ack[3] |= LINK_STATUS_CHANGED;
4147                 }
4148
4149                 intel_dp_mst_hpd_irq(intel_dp, esi, ack);
4150
4151                 if (!memchr_inv(ack, 0, sizeof(ack)))
4152                         break;
4153
4154                 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
4155                         drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
4156
4157                 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))
4158                         drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);
4159         }
4160
4161         return link_ok;
4162 }
4163
4164 static void
4165 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
4166 {
4167         bool is_active;
4168         u8 buf = 0;
4169
4170         is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
4171         if (intel_dp->frl.is_trained && !is_active) {
4172                 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
4173                         return;
4174
4175                 buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
4176                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
4177                         return;
4178
4179                 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
4180
4181                 intel_dp->frl.is_trained = false;
4182
4183                 /* Restart FRL training or fall back to TMDS mode */
4184                 intel_dp_check_frl_training(intel_dp);
4185         }
4186 }
4187
4188 static bool
4189 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4190 {
4191         u8 link_status[DP_LINK_STATUS_SIZE];
4192
4193         if (!intel_dp->link_trained)
4194                 return false;
4195
4196         /*
4197          * While PSR source HW is enabled, it will control main-link sending
4198          * frames, enabling and disabling it so trying to do a retrain will fail
4199          * as the link would or not be on or it could mix training patterns
4200          * and frame data at the same time causing retrain to fail.
4201          * Also when exiting PSR, HW will retrain the link anyways fixing
4202          * any link status error.
4203          */
4204         if (intel_psr_enabled(intel_dp))
4205                 return false;
4206
4207         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4208                                              link_status) < 0)
4209                 return false;
4210
4211         /*
4212          * Validate the cached values of intel_dp->link_rate and
4213          * intel_dp->lane_count before attempting to retrain.
4214          *
4215          * FIXME would be nice to user the crtc state here, but since
4216          * we need to call this from the short HPD handler that seems
4217          * a bit hard.
4218          */
4219         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4220                                         intel_dp->lane_count))
4221                 return false;
4222
4223         /* Retrain if link not ok */
4224         return !intel_dp_link_ok(intel_dp, link_status);
4225 }
4226
4227 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
4228                                    const struct drm_connector_state *conn_state)
4229 {
4230         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4231         struct intel_encoder *encoder;
4232         enum pipe pipe;
4233
4234         if (!conn_state->best_encoder)
4235                 return false;
4236
4237         /* SST */
4238         encoder = &dp_to_dig_port(intel_dp)->base;
4239         if (conn_state->best_encoder == &encoder->base)
4240                 return true;
4241
4242         /* MST */
4243         for_each_pipe(i915, pipe) {
4244                 encoder = &intel_dp->mst_encoders[pipe]->base;
4245                 if (conn_state->best_encoder == &encoder->base)
4246                         return true;
4247         }
4248
4249         return false;
4250 }
4251
4252 int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
4253                               struct drm_modeset_acquire_ctx *ctx,
4254                               u8 *pipe_mask)
4255 {
4256         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4257         struct drm_connector_list_iter conn_iter;
4258         struct intel_connector *connector;
4259         int ret = 0;
4260
4261         *pipe_mask = 0;
4262
4263         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4264         for_each_intel_connector_iter(connector, &conn_iter) {
4265                 struct drm_connector_state *conn_state =
4266                         connector->base.state;
4267                 struct intel_crtc_state *crtc_state;
4268                 struct intel_crtc *crtc;
4269
4270                 if (!intel_dp_has_connector(intel_dp, conn_state))
4271                         continue;
4272
4273                 crtc = to_intel_crtc(conn_state->crtc);
4274                 if (!crtc)
4275                         continue;
4276
4277                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4278                 if (ret)
4279                         break;
4280
4281                 crtc_state = to_intel_crtc_state(crtc->base.state);
4282
4283                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4284
4285                 if (!crtc_state->hw.active)
4286                         continue;
4287
4288                 if (conn_state->commit &&
4289                     !try_wait_for_completion(&conn_state->commit->hw_done))
4290                         continue;
4291
4292                 *pipe_mask |= BIT(crtc->pipe);
4293         }
4294         drm_connector_list_iter_end(&conn_iter);
4295
4296         return ret;
4297 }
4298
4299 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
4300 {
4301         struct intel_connector *connector = intel_dp->attached_connector;
4302
4303         return connector->base.status == connector_status_connected ||
4304                 intel_dp->is_mst;
4305 }
4306
4307 int intel_dp_retrain_link(struct intel_encoder *encoder,
4308                           struct drm_modeset_acquire_ctx *ctx)
4309 {
4310         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4311         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4312         struct intel_crtc *crtc;
4313         u8 pipe_mask;
4314         int ret;
4315
4316         if (!intel_dp_is_connected(intel_dp))
4317                 return 0;
4318
4319         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4320                                ctx);
4321         if (ret)
4322                 return ret;
4323
4324         if (!intel_dp_needs_link_retrain(intel_dp))
4325                 return 0;
4326
4327         ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);
4328         if (ret)
4329                 return ret;
4330
4331         if (pipe_mask == 0)
4332                 return 0;
4333
4334         if (!intel_dp_needs_link_retrain(intel_dp))
4335                 return 0;
4336
4337         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
4338                     encoder->base.base.id, encoder->base.name);
4339
4340         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4341                 const struct intel_crtc_state *crtc_state =
4342                         to_intel_crtc_state(crtc->base.state);
4343
4344                 /* Suppress underruns caused by re-training */
4345                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4346                 if (crtc_state->has_pch_encoder)
4347                         intel_set_pch_fifo_underrun_reporting(dev_priv,
4348                                                               intel_crtc_pch_transcoder(crtc), false);
4349         }
4350
4351         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4352                 const struct intel_crtc_state *crtc_state =
4353                         to_intel_crtc_state(crtc->base.state);
4354
4355                 /* retrain on the MST master transcoder */
4356                 if (DISPLAY_VER(dev_priv) >= 12 &&
4357                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4358                     !intel_dp_mst_is_master_trans(crtc_state))
4359                         continue;
4360
4361                 intel_dp_check_frl_training(intel_dp);
4362                 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
4363                 intel_dp_start_link_train(intel_dp, crtc_state);
4364                 intel_dp_stop_link_train(intel_dp, crtc_state);
4365                 break;
4366         }
4367
4368         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4369                 const struct intel_crtc_state *crtc_state =
4370                         to_intel_crtc_state(crtc->base.state);
4371
4372                 /* Keep underrun reporting disabled until things are stable */
4373                 intel_crtc_wait_for_next_vblank(crtc);
4374
4375                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4376                 if (crtc_state->has_pch_encoder)
4377                         intel_set_pch_fifo_underrun_reporting(dev_priv,
4378                                                               intel_crtc_pch_transcoder(crtc), true);
4379         }
4380
4381         return 0;
4382 }
4383
4384 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
4385                                   struct drm_modeset_acquire_ctx *ctx,
4386                                   u8 *pipe_mask)
4387 {
4388         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4389         struct drm_connector_list_iter conn_iter;
4390         struct intel_connector *connector;
4391         int ret = 0;
4392
4393         *pipe_mask = 0;
4394
4395         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4396         for_each_intel_connector_iter(connector, &conn_iter) {
4397                 struct drm_connector_state *conn_state =
4398                         connector->base.state;
4399                 struct intel_crtc_state *crtc_state;
4400                 struct intel_crtc *crtc;
4401
4402                 if (!intel_dp_has_connector(intel_dp, conn_state))
4403                         continue;
4404
4405                 crtc = to_intel_crtc(conn_state->crtc);
4406                 if (!crtc)
4407                         continue;
4408
4409                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4410                 if (ret)
4411                         break;
4412
4413                 crtc_state = to_intel_crtc_state(crtc->base.state);
4414
4415                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4416
4417                 if (!crtc_state->hw.active)
4418                         continue;
4419
4420                 if (conn_state->commit &&
4421                     !try_wait_for_completion(&conn_state->commit->hw_done))
4422                         continue;
4423
4424                 *pipe_mask |= BIT(crtc->pipe);
4425         }
4426         drm_connector_list_iter_end(&conn_iter);
4427
4428         return ret;
4429 }
4430
4431 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
4432                                 struct drm_modeset_acquire_ctx *ctx)
4433 {
4434         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4435         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4436         struct intel_crtc *crtc;
4437         u8 pipe_mask;
4438         int ret;
4439
4440         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4441                                ctx);
4442         if (ret)
4443                 return ret;
4444
4445         ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);
4446         if (ret)
4447                 return ret;
4448
4449         if (pipe_mask == 0)
4450                 return 0;
4451
4452         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
4453                     encoder->base.base.id, encoder->base.name);
4454
4455         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4456                 const struct intel_crtc_state *crtc_state =
4457                         to_intel_crtc_state(crtc->base.state);
4458
4459                 /* test on the MST master transcoder */
4460                 if (DISPLAY_VER(dev_priv) >= 12 &&
4461                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4462                     !intel_dp_mst_is_master_trans(crtc_state))
4463                         continue;
4464
4465                 intel_dp_process_phy_request(intel_dp, crtc_state);
4466                 break;
4467         }
4468
4469         return 0;
4470 }
4471
4472 void intel_dp_phy_test(struct intel_encoder *encoder)
4473 {
4474         struct drm_modeset_acquire_ctx ctx;
4475         int ret;
4476
4477         drm_modeset_acquire_init(&ctx, 0);
4478
4479         for (;;) {
4480                 ret = intel_dp_do_phy_test(encoder, &ctx);
4481
4482                 if (ret == -EDEADLK) {
4483                         drm_modeset_backoff(&ctx);
4484                         continue;
4485                 }
4486
4487                 break;
4488         }
4489
4490         drm_modeset_drop_locks(&ctx);
4491         drm_modeset_acquire_fini(&ctx);
4492         drm_WARN(encoder->base.dev, ret,
4493                  "Acquiring modeset locks failed with %i\n", ret);
4494 }
4495
4496 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
4497 {
4498         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4499         u8 val;
4500
4501         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4502                 return;
4503
4504         if (drm_dp_dpcd_readb(&intel_dp->aux,
4505                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4506                 return;
4507
4508         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4509
4510         if (val & DP_AUTOMATED_TEST_REQUEST)
4511                 intel_dp_handle_test_request(intel_dp);
4512
4513         if (val & DP_CP_IRQ)
4514                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4515
4516         if (val & DP_SINK_SPECIFIC_IRQ)
4517                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
4518 }
4519
4520 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
4521 {
4522         u8 val;
4523
4524         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4525                 return;
4526
4527         if (drm_dp_dpcd_readb(&intel_dp->aux,
4528                               DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
4529                 return;
4530
4531         if (drm_dp_dpcd_writeb(&intel_dp->aux,
4532                                DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
4533                 return;
4534
4535         if (val & HDMI_LINK_STATUS_CHANGED)
4536                 intel_dp_handle_hdmi_link_status_change(intel_dp);
4537 }
4538
4539 /*
4540  * According to DP spec
4541  * 5.1.2:
4542  *  1. Read DPCD
4543  *  2. Configure link according to Receiver Capabilities
4544  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4545  *  4. Check link status on receipt of hot-plug interrupt
4546  *
4547  * intel_dp_short_pulse -  handles short pulse interrupts
4548  * when full detection is not required.
4549  * Returns %true if short pulse is handled and full detection
4550  * is NOT required and %false otherwise.
4551  */
4552 static bool
4553 intel_dp_short_pulse(struct intel_dp *intel_dp)
4554 {
4555         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4556         u8 old_sink_count = intel_dp->sink_count;
4557         bool ret;
4558
4559         /*
4560          * Clearing compliance test variables to allow capturing
4561          * of values for next automated test request.
4562          */
4563         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4564
4565         /*
4566          * Now read the DPCD to see if it's actually running
4567          * If the current value of sink count doesn't match with
4568          * the value that was stored earlier or dpcd read failed
4569          * we need to do full detection
4570          */
4571         ret = intel_dp_get_dpcd(intel_dp);
4572
4573         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4574                 /* No need to proceed if we are going to do full detect */
4575                 return false;
4576         }
4577
4578         intel_dp_check_device_service_irq(intel_dp);
4579         intel_dp_check_link_service_irq(intel_dp);
4580
4581         /* Handle CEC interrupts, if any */
4582         drm_dp_cec_irq(&intel_dp->aux);
4583
4584         /* defer to the hotplug work for link retraining if needed */
4585         if (intel_dp_needs_link_retrain(intel_dp))
4586                 return false;
4587
4588         intel_psr_short_pulse(intel_dp);
4589
4590         switch (intel_dp->compliance.test_type) {
4591         case DP_TEST_LINK_TRAINING:
4592                 drm_dbg_kms(&dev_priv->drm,
4593                             "Link Training Compliance Test requested\n");
4594                 /* Send a Hotplug Uevent to userspace to start modeset */
4595                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4596                 break;
4597         case DP_TEST_LINK_PHY_TEST_PATTERN:
4598                 drm_dbg_kms(&dev_priv->drm,
4599                             "PHY test pattern Compliance Test requested\n");
4600                 /*
4601                  * Schedule long hpd to do the test
4602                  *
4603                  * FIXME get rid of the ad-hoc phy test modeset code
4604                  * and properly incorporate it into the normal modeset.
4605                  */
4606                 return false;
4607         }
4608
4609         return true;
4610 }
4611
4612 /* XXX this is probably wrong for multiple downstream ports */
4613 static enum drm_connector_status
4614 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4615 {
4616         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4617         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4618         u8 *dpcd = intel_dp->dpcd;
4619         u8 type;
4620
4621         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
4622                 return connector_status_connected;
4623
4624         lspcon_resume(dig_port);
4625
4626         if (!intel_dp_get_dpcd(intel_dp))
4627                 return connector_status_disconnected;
4628
4629         /* if there's no downstream port, we're done */
4630         if (!drm_dp_is_branch(dpcd))
4631                 return connector_status_connected;
4632
4633         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4634         if (intel_dp_has_sink_count(intel_dp) &&
4635             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4636                 return intel_dp->sink_count ?
4637                 connector_status_connected : connector_status_disconnected;
4638         }
4639
4640         if (intel_dp_can_mst(intel_dp))
4641                 return connector_status_connected;
4642
4643         /* If no HPD, poke DDC gently */
4644         if (drm_probe_ddc(&intel_dp->aux.ddc))
4645                 return connector_status_connected;
4646
4647         /* Well we tried, say unknown for unreliable port types */
4648         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4649                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4650                 if (type == DP_DS_PORT_TYPE_VGA ||
4651                     type == DP_DS_PORT_TYPE_NON_EDID)
4652                         return connector_status_unknown;
4653         } else {
4654                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4655                         DP_DWN_STRM_PORT_TYPE_MASK;
4656                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4657                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4658                         return connector_status_unknown;
4659         }
4660
4661         /* Anything else is out of spec, warn and ignore */
4662         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
4663         return connector_status_disconnected;
4664 }
4665
4666 static enum drm_connector_status
4667 edp_detect(struct intel_dp *intel_dp)
4668 {
4669         return connector_status_connected;
4670 }
4671
4672 /*
4673  * intel_digital_port_connected - is the specified port connected?
4674  * @encoder: intel_encoder
4675  *
4676  * In cases where there's a connector physically connected but it can't be used
4677  * by our hardware we also return false, since the rest of the driver should
4678  * pretty much treat the port as disconnected. This is relevant for type-C
4679  * (starting on ICL) where there's ownership involved.
4680  *
4681  * Return %true if port is connected, %false otherwise.
4682  */
4683 bool intel_digital_port_connected(struct intel_encoder *encoder)
4684 {
4685         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4686         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4687         bool is_connected = false;
4688         intel_wakeref_t wakeref;
4689
4690         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
4691                 is_connected = dig_port->connected(encoder);
4692
4693         return is_connected;
4694 }
4695
4696 static const struct drm_edid *
4697 intel_dp_get_edid(struct intel_dp *intel_dp)
4698 {
4699         struct intel_connector *connector = intel_dp->attached_connector;
4700         const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
4701
4702         /* Use panel fixed edid if we have one */
4703         if (fixed_edid) {
4704                 /* invalid edid */
4705                 if (IS_ERR(fixed_edid))
4706                         return NULL;
4707
4708                 return drm_edid_dup(fixed_edid);
4709         }
4710
4711         return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);
4712 }
4713
4714 static void
4715 intel_dp_update_dfp(struct intel_dp *intel_dp,
4716                     const struct drm_edid *drm_edid)
4717 {
4718         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4719         struct intel_connector *connector = intel_dp->attached_connector;
4720         const struct edid *edid;
4721
4722         /* FIXME: Get rid of drm_edid_raw() */
4723         edid = drm_edid_raw(drm_edid);
4724
4725         intel_dp->dfp.max_bpc =
4726                 drm_dp_downstream_max_bpc(intel_dp->dpcd,
4727                                           intel_dp->downstream_ports, edid);
4728
4729         intel_dp->dfp.max_dotclock =
4730                 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
4731                                                intel_dp->downstream_ports);
4732
4733         intel_dp->dfp.min_tmds_clock =
4734                 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
4735                                                  intel_dp->downstream_ports,
4736                                                  edid);
4737         intel_dp->dfp.max_tmds_clock =
4738                 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
4739                                                  intel_dp->downstream_ports,
4740                                                  edid);
4741
4742         intel_dp->dfp.pcon_max_frl_bw =
4743                 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
4744                                            intel_dp->downstream_ports);
4745
4746         drm_dbg_kms(&i915->drm,
4747                     "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
4748                     connector->base.base.id, connector->base.name,
4749                     intel_dp->dfp.max_bpc,
4750                     intel_dp->dfp.max_dotclock,
4751                     intel_dp->dfp.min_tmds_clock,
4752                     intel_dp->dfp.max_tmds_clock,
4753                     intel_dp->dfp.pcon_max_frl_bw);
4754
4755         intel_dp_get_pcon_dsc_cap(intel_dp);
4756 }
4757
4758 static bool
4759 intel_dp_can_ycbcr420(struct intel_dp *intel_dp)
4760 {
4761         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) &&
4762             (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))
4763                 return true;
4764
4765         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
4766             dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
4767                 return true;
4768
4769         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&
4770             dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
4771                 return true;
4772
4773         return false;
4774 }
4775
4776 static void
4777 intel_dp_update_420(struct intel_dp *intel_dp)
4778 {
4779         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4780         struct intel_connector *connector = intel_dp->attached_connector;
4781
4782         intel_dp->dfp.ycbcr420_passthrough =
4783                 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
4784                                                   intel_dp->downstream_ports);
4785         /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
4786         intel_dp->dfp.ycbcr_444_to_420 =
4787                 dp_to_dig_port(intel_dp)->lspcon.active ||
4788                 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
4789                                                         intel_dp->downstream_ports);
4790         intel_dp->dfp.rgb_to_ycbcr =
4791                 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
4792                                                           intel_dp->downstream_ports,
4793                                                           DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
4794
4795         connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);
4796
4797         drm_dbg_kms(&i915->drm,
4798                     "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
4799                     connector->base.base.id, connector->base.name,
4800                     str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
4801                     str_yes_no(connector->base.ycbcr_420_allowed),
4802                     str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
4803 }
4804
4805 static void
4806 intel_dp_set_edid(struct intel_dp *intel_dp)
4807 {
4808         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4809         struct intel_connector *connector = intel_dp->attached_connector;
4810         const struct drm_edid *drm_edid;
4811         const struct edid *edid;
4812         bool vrr_capable;
4813
4814         intel_dp_unset_edid(intel_dp);
4815         drm_edid = intel_dp_get_edid(intel_dp);
4816         connector->detect_edid = drm_edid;
4817
4818         /* Below we depend on display info having been updated */
4819         drm_edid_connector_update(&connector->base, drm_edid);
4820
4821         vrr_capable = intel_vrr_is_capable(connector);
4822         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
4823                     connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
4824         drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
4825
4826         intel_dp_update_dfp(intel_dp, drm_edid);
4827         intel_dp_update_420(intel_dp);
4828
4829         /* FIXME: Get rid of drm_edid_raw() */
4830         edid = drm_edid_raw(drm_edid);
4831
4832         drm_dp_cec_set_edid(&intel_dp->aux, edid);
4833 }
4834
4835 static void
4836 intel_dp_unset_edid(struct intel_dp *intel_dp)
4837 {
4838         struct intel_connector *connector = intel_dp->attached_connector;
4839
4840         drm_dp_cec_unset_edid(&intel_dp->aux);
4841         drm_edid_free(connector->detect_edid);
4842         connector->detect_edid = NULL;
4843
4844         intel_dp->dfp.max_bpc = 0;
4845         intel_dp->dfp.max_dotclock = 0;
4846         intel_dp->dfp.min_tmds_clock = 0;
4847         intel_dp->dfp.max_tmds_clock = 0;
4848
4849         intel_dp->dfp.pcon_max_frl_bw = 0;
4850
4851         intel_dp->dfp.ycbcr_444_to_420 = false;
4852         connector->base.ycbcr_420_allowed = false;
4853
4854         drm_connector_set_vrr_capable_property(&connector->base,
4855                                                false);
4856 }
4857
4858 static int
4859 intel_dp_detect(struct drm_connector *connector,
4860                 struct drm_modeset_acquire_ctx *ctx,
4861                 bool force)
4862 {
4863         struct drm_i915_private *dev_priv = to_i915(connector->dev);
4864         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4865         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4866         struct intel_encoder *encoder = &dig_port->base;
4867         enum drm_connector_status status;
4868
4869         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4870                     connector->base.id, connector->name);
4871         drm_WARN_ON(&dev_priv->drm,
4872                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4873
4874         if (!INTEL_DISPLAY_ENABLED(dev_priv))
4875                 return connector_status_disconnected;
4876
4877         /* Can't disconnect eDP */
4878         if (intel_dp_is_edp(intel_dp))
4879                 status = edp_detect(intel_dp);
4880         else if (intel_digital_port_connected(encoder))
4881                 status = intel_dp_detect_dpcd(intel_dp);
4882         else
4883                 status = connector_status_disconnected;
4884
4885         if (status == connector_status_disconnected) {
4886                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4887                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4888
4889                 if (intel_dp->is_mst) {
4890                         drm_dbg_kms(&dev_priv->drm,
4891                                     "MST device may have disappeared %d vs %d\n",
4892                                     intel_dp->is_mst,
4893                                     intel_dp->mst_mgr.mst_state);
4894                         intel_dp->is_mst = false;
4895                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4896                                                         intel_dp->is_mst);
4897                 }
4898
4899                 goto out;
4900         }
4901
4902         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4903         if (HAS_DSC(dev_priv))
4904                 intel_dp_get_dsc_sink_cap(intel_dp);
4905
4906         intel_dp_configure_mst(intel_dp);
4907
4908         /*
4909          * TODO: Reset link params when switching to MST mode, until MST
4910          * supports link training fallback params.
4911          */
4912         if (intel_dp->reset_link_params || intel_dp->is_mst) {
4913                 intel_dp_reset_max_link_params(intel_dp);
4914                 intel_dp->reset_link_params = false;
4915         }
4916
4917         intel_dp_print_rates(intel_dp);
4918
4919         if (intel_dp->is_mst) {
4920                 /*
4921                  * If we are in MST mode then this connector
4922                  * won't appear connected or have anything
4923                  * with EDID on it
4924                  */
4925                 status = connector_status_disconnected;
4926                 goto out;
4927         }
4928
4929         /*
4930          * Some external monitors do not signal loss of link synchronization
4931          * with an IRQ_HPD, so force a link status check.
4932          */
4933         if (!intel_dp_is_edp(intel_dp)) {
4934                 int ret;
4935
4936                 ret = intel_dp_retrain_link(encoder, ctx);
4937                 if (ret)
4938                         return ret;
4939         }
4940
4941         /*
4942          * Clearing NACK and defer counts to get their exact values
4943          * while reading EDID which are required by Compliance tests
4944          * 4.2.2.4 and 4.2.2.5
4945          */
4946         intel_dp->aux.i2c_nack_count = 0;
4947         intel_dp->aux.i2c_defer_count = 0;
4948
4949         intel_dp_set_edid(intel_dp);
4950         if (intel_dp_is_edp(intel_dp) ||
4951             to_intel_connector(connector)->detect_edid)
4952                 status = connector_status_connected;
4953
4954         intel_dp_check_device_service_irq(intel_dp);
4955
4956 out:
4957         if (status != connector_status_connected && !intel_dp->is_mst)
4958                 intel_dp_unset_edid(intel_dp);
4959
4960         /*
4961          * Make sure the refs for power wells enabled during detect are
4962          * dropped to avoid a new detect cycle triggered by HPD polling.
4963          */
4964         intel_display_power_flush_work(dev_priv);
4965
4966         if (!intel_dp_is_edp(intel_dp))
4967                 drm_dp_set_subconnector_property(connector,
4968                                                  status,
4969                                                  intel_dp->dpcd,
4970                                                  intel_dp->downstream_ports);
4971         return status;
4972 }
4973
4974 static void
4975 intel_dp_force(struct drm_connector *connector)
4976 {
4977         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4978         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4979         struct intel_encoder *intel_encoder = &dig_port->base;
4980         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4981         enum intel_display_power_domain aux_domain =
4982                 intel_aux_power_domain(dig_port);
4983         intel_wakeref_t wakeref;
4984
4985         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4986                     connector->base.id, connector->name);
4987         intel_dp_unset_edid(intel_dp);
4988
4989         if (connector->status != connector_status_connected)
4990                 return;
4991
4992         wakeref = intel_display_power_get(dev_priv, aux_domain);
4993
4994         intel_dp_set_edid(intel_dp);
4995
4996         intel_display_power_put(dev_priv, aux_domain, wakeref);
4997 }
4998
4999 static int intel_dp_get_modes(struct drm_connector *connector)
5000 {
5001         struct intel_connector *intel_connector = to_intel_connector(connector);
5002         int num_modes;
5003
5004         /* drm_edid_connector_update() done in ->detect() or ->force() */
5005         num_modes = drm_edid_connector_add_modes(connector);
5006
5007         /* Also add fixed mode, which may or may not be present in EDID */
5008         if (intel_dp_is_edp(intel_attached_dp(intel_connector)))
5009                 num_modes += intel_panel_get_modes(intel_connector);
5010
5011         if (num_modes)
5012                 return num_modes;
5013
5014         if (!intel_connector->detect_edid) {
5015                 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5016                 struct drm_display_mode *mode;
5017
5018                 mode = drm_dp_downstream_mode(connector->dev,
5019                                               intel_dp->dpcd,
5020                                               intel_dp->downstream_ports);
5021                 if (mode) {
5022                         drm_mode_probed_add(connector, mode);
5023                         num_modes++;
5024                 }
5025         }
5026
5027         return num_modes;
5028 }
5029
5030 static int
5031 intel_dp_connector_register(struct drm_connector *connector)
5032 {
5033         struct drm_i915_private *i915 = to_i915(connector->dev);
5034         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5035         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5036         struct intel_lspcon *lspcon = &dig_port->lspcon;
5037         int ret;
5038
5039         ret = intel_connector_register(connector);
5040         if (ret)
5041                 return ret;
5042
5043         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
5044                     intel_dp->aux.name, connector->kdev->kobj.name);
5045
5046         intel_dp->aux.dev = connector->kdev;
5047         ret = drm_dp_aux_register(&intel_dp->aux);
5048         if (!ret)
5049                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
5050
5051         if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))
5052                 return ret;
5053
5054         /*
5055          * ToDo: Clean this up to handle lspcon init and resume more
5056          * efficiently and streamlined.
5057          */
5058         if (lspcon_init(dig_port)) {
5059                 lspcon_detect_hdr_capability(lspcon);
5060                 if (lspcon->hdr_supported)
5061                         drm_connector_attach_hdr_output_metadata_property(connector);
5062         }
5063
5064         return ret;
5065 }
5066
5067 static void
5068 intel_dp_connector_unregister(struct drm_connector *connector)
5069 {
5070         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5071
5072         drm_dp_cec_unregister_connector(&intel_dp->aux);
5073         drm_dp_aux_unregister(&intel_dp->aux);
5074         intel_connector_unregister(connector);
5075 }
5076
5077 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5078 {
5079         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
5080         struct intel_dp *intel_dp = &dig_port->dp;
5081
5082         intel_dp_mst_encoder_cleanup(dig_port);
5083
5084         intel_pps_vdd_off_sync(intel_dp);
5085
5086         /*
5087          * Ensure power off delay is respected on module remove, so that we can
5088          * reduce delays at driver probe. See pps_init_timestamps().
5089          */
5090         intel_pps_wait_power_cycle(intel_dp);
5091
5092         intel_dp_aux_fini(intel_dp);
5093 }
5094
5095 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5096 {
5097         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5098
5099         intel_pps_vdd_off_sync(intel_dp);
5100 }
5101
5102 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
5103 {
5104         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5105
5106         intel_pps_wait_power_cycle(intel_dp);
5107 }
5108
5109 static int intel_modeset_tile_group(struct intel_atomic_state *state,
5110                                     int tile_group_id)
5111 {
5112         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5113         struct drm_connector_list_iter conn_iter;
5114         struct drm_connector *connector;
5115         int ret = 0;
5116
5117         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
5118         drm_for_each_connector_iter(connector, &conn_iter) {
5119                 struct drm_connector_state *conn_state;
5120                 struct intel_crtc_state *crtc_state;
5121                 struct intel_crtc *crtc;
5122
5123                 if (!connector->has_tile ||
5124                     connector->tile_group->id != tile_group_id)
5125                         continue;
5126
5127                 conn_state = drm_atomic_get_connector_state(&state->base,
5128                                                             connector);
5129                 if (IS_ERR(conn_state)) {
5130                         ret = PTR_ERR(conn_state);
5131                         break;
5132                 }
5133
5134                 crtc = to_intel_crtc(conn_state->crtc);
5135
5136                 if (!crtc)
5137                         continue;
5138
5139                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
5140                 crtc_state->uapi.mode_changed = true;
5141
5142                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5143                 if (ret)
5144                         break;
5145         }
5146         drm_connector_list_iter_end(&conn_iter);
5147
5148         return ret;
5149 }
5150
5151 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
5152 {
5153         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5154         struct intel_crtc *crtc;
5155
5156         if (transcoders == 0)
5157                 return 0;
5158
5159         for_each_intel_crtc(&dev_priv->drm, crtc) {
5160                 struct intel_crtc_state *crtc_state;
5161                 int ret;
5162
5163                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5164                 if (IS_ERR(crtc_state))
5165                         return PTR_ERR(crtc_state);
5166
5167                 if (!crtc_state->hw.enable)
5168                         continue;
5169
5170                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
5171                         continue;
5172
5173                 crtc_state->uapi.mode_changed = true;
5174
5175                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
5176                 if (ret)
5177                         return ret;
5178
5179                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5180                 if (ret)
5181                         return ret;
5182
5183                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
5184         }
5185
5186         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
5187
5188         return 0;
5189 }
5190
5191 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
5192                                       struct drm_connector *connector)
5193 {
5194         const struct drm_connector_state *old_conn_state =
5195                 drm_atomic_get_old_connector_state(&state->base, connector);
5196         const struct intel_crtc_state *old_crtc_state;
5197         struct intel_crtc *crtc;
5198         u8 transcoders;
5199
5200         crtc = to_intel_crtc(old_conn_state->crtc);
5201         if (!crtc)
5202                 return 0;
5203
5204         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
5205
5206         if (!old_crtc_state->hw.active)
5207                 return 0;
5208
5209         transcoders = old_crtc_state->sync_mode_slaves_mask;
5210         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
5211                 transcoders |= BIT(old_crtc_state->master_transcoder);
5212
5213         return intel_modeset_affected_transcoders(state,
5214                                                   transcoders);
5215 }
5216
5217 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
5218                                            struct drm_atomic_state *_state)
5219 {
5220         struct drm_i915_private *dev_priv = to_i915(conn->dev);
5221         struct intel_atomic_state *state = to_intel_atomic_state(_state);
5222         struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);
5223         struct intel_connector *intel_conn = to_intel_connector(conn);
5224         struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);
5225         int ret;
5226
5227         ret = intel_digital_connector_atomic_check(conn, &state->base);
5228         if (ret)
5229                 return ret;
5230
5231         if (intel_dp_mst_source_support(intel_dp)) {
5232                 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr);
5233                 if (ret)
5234                         return ret;
5235         }
5236
5237         /*
5238          * We don't enable port sync on BDW due to missing w/as and
5239          * due to not having adjusted the modeset sequence appropriately.
5240          */
5241         if (DISPLAY_VER(dev_priv) < 9)
5242                 return 0;
5243
5244         if (!intel_connector_needs_modeset(state, conn))
5245                 return 0;
5246
5247         if (conn->has_tile) {
5248                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
5249                 if (ret)
5250                         return ret;
5251         }
5252
5253         return intel_modeset_synced_crtcs(state, conn);
5254 }
5255
5256 static void intel_dp_oob_hotplug_event(struct drm_connector *connector)
5257 {
5258         struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
5259         struct drm_i915_private *i915 = to_i915(connector->dev);
5260
5261         spin_lock_irq(&i915->irq_lock);
5262         i915->display.hotplug.event_bits |= BIT(encoder->hpd_pin);
5263         spin_unlock_irq(&i915->irq_lock);
5264         queue_delayed_work(i915->unordered_wq, &i915->display.hotplug.hotplug_work, 0);
5265 }
5266
5267 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5268         .force = intel_dp_force,
5269         .fill_modes = drm_helper_probe_single_connector_modes,
5270         .atomic_get_property = intel_digital_connector_atomic_get_property,
5271         .atomic_set_property = intel_digital_connector_atomic_set_property,
5272         .late_register = intel_dp_connector_register,
5273         .early_unregister = intel_dp_connector_unregister,
5274         .destroy = intel_connector_destroy,
5275         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5276         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5277         .oob_hotplug_event = intel_dp_oob_hotplug_event,
5278 };
5279
5280 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5281         .detect_ctx = intel_dp_detect,
5282         .get_modes = intel_dp_get_modes,
5283         .mode_valid = intel_dp_mode_valid,
5284         .atomic_check = intel_dp_connector_atomic_check,
5285 };
5286
5287 enum irqreturn
5288 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
5289 {
5290         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
5291         struct intel_dp *intel_dp = &dig_port->dp;
5292
5293         if (dig_port->base.type == INTEL_OUTPUT_EDP &&
5294             (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {
5295                 /*
5296                  * vdd off can generate a long/short pulse on eDP which
5297                  * would require vdd on to handle it, and thus we
5298                  * would end up in an endless cycle of
5299                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
5300                  */
5301                 drm_dbg_kms(&i915->drm,
5302                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
5303                             long_hpd ? "long" : "short",
5304                             dig_port->base.base.base.id,
5305                             dig_port->base.base.name);
5306                 return IRQ_HANDLED;
5307         }
5308
5309         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
5310                     dig_port->base.base.base.id,
5311                     dig_port->base.base.name,
5312                     long_hpd ? "long" : "short");
5313
5314         if (long_hpd) {
5315                 intel_dp->reset_link_params = true;
5316                 return IRQ_NONE;
5317         }
5318
5319         if (intel_dp->is_mst) {
5320                 if (!intel_dp_check_mst_status(intel_dp))
5321                         return IRQ_NONE;
5322         } else if (!intel_dp_short_pulse(intel_dp)) {
5323                 return IRQ_NONE;
5324         }
5325
5326         return IRQ_HANDLED;
5327 }
5328
5329 static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv,
5330                                   const struct intel_bios_encoder_data *devdata,
5331                                   enum port port)
5332 {
5333         /*
5334          * eDP not supported on g4x. so bail out early just
5335          * for a bit extra safety in case the VBT is bonkers.
5336          */
5337         if (DISPLAY_VER(dev_priv) < 5)
5338                 return false;
5339
5340         if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
5341                 return true;
5342
5343         return devdata && intel_bios_encoder_supports_edp(devdata);
5344 }
5345
5346 bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port)
5347 {
5348         const struct intel_bios_encoder_data *devdata =
5349                 intel_bios_encoder_data_lookup(i915, port);
5350
5351         return _intel_dp_is_port_edp(i915, devdata, port);
5352 }
5353
5354 static bool
5355 has_gamut_metadata_dip(struct intel_encoder *encoder)
5356 {
5357         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
5358         enum port port = encoder->port;
5359
5360         if (intel_bios_encoder_is_lspcon(encoder->devdata))
5361                 return false;
5362
5363         if (DISPLAY_VER(i915) >= 11)
5364                 return true;
5365
5366         if (port == PORT_A)
5367                 return false;
5368
5369         if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
5370             DISPLAY_VER(i915) >= 9)
5371                 return true;
5372
5373         return false;
5374 }
5375
5376 static void
5377 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5378 {
5379         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5380         enum port port = dp_to_dig_port(intel_dp)->base.port;
5381
5382         if (!intel_dp_is_edp(intel_dp))
5383                 drm_connector_attach_dp_subconnector_property(connector);
5384
5385         if (!IS_G4X(dev_priv) && port != PORT_A)
5386                 intel_attach_force_audio_property(connector);
5387
5388         intel_attach_broadcast_rgb_property(connector);
5389         if (HAS_GMCH(dev_priv))
5390                 drm_connector_attach_max_bpc_property(connector, 6, 10);
5391         else if (DISPLAY_VER(dev_priv) >= 5)
5392                 drm_connector_attach_max_bpc_property(connector, 6, 12);
5393
5394         /* Register HDMI colorspace for case of lspcon */
5395         if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {
5396                 drm_connector_attach_content_type_property(connector);
5397                 intel_attach_hdmi_colorspace_property(connector);
5398         } else {
5399                 intel_attach_dp_colorspace_property(connector);
5400         }
5401
5402         if (has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
5403                 drm_connector_attach_hdr_output_metadata_property(connector);
5404
5405         if (HAS_VRR(dev_priv))
5406                 drm_connector_attach_vrr_capable_property(connector);
5407 }
5408
5409 static void
5410 intel_edp_add_properties(struct intel_dp *intel_dp)
5411 {
5412         struct intel_connector *connector = intel_dp->attached_connector;
5413         struct drm_i915_private *i915 = to_i915(connector->base.dev);
5414         const struct drm_display_mode *fixed_mode =
5415                 intel_panel_preferred_fixed_mode(connector);
5416
5417         intel_attach_scaling_mode_property(&connector->base);
5418
5419         drm_connector_set_panel_orientation_with_quirk(&connector->base,
5420                                                        i915->display.vbt.orientation,
5421                                                        fixed_mode->hdisplay,
5422                                                        fixed_mode->vdisplay);
5423 }
5424
5425 static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
5426                                       struct intel_connector *connector)
5427 {
5428         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5429         enum pipe pipe = INVALID_PIPE;
5430
5431         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
5432                 /*
5433                  * Figure out the current pipe for the initial backlight setup.
5434                  * If the current pipe isn't valid, try the PPS pipe, and if that
5435                  * fails just assume pipe A.
5436                  */
5437                 pipe = vlv_active_pipe(intel_dp);
5438
5439                 if (pipe != PIPE_A && pipe != PIPE_B)
5440                         pipe = intel_dp->pps.pps_pipe;
5441
5442                 if (pipe != PIPE_A && pipe != PIPE_B)
5443                         pipe = PIPE_A;
5444         }
5445
5446         intel_backlight_setup(connector, pipe);
5447 }
5448
5449 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5450                                      struct intel_connector *intel_connector)
5451 {
5452         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5453         struct drm_connector *connector = &intel_connector->base;
5454         struct drm_display_mode *fixed_mode;
5455         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5456         bool has_dpcd;
5457         const struct drm_edid *drm_edid;
5458
5459         if (!intel_dp_is_edp(intel_dp))
5460                 return true;
5461
5462         /*
5463          * On IBX/CPT we may get here with LVDS already registered. Since the
5464          * driver uses the only internal power sequencer available for both
5465          * eDP and LVDS bail out early in this case to prevent interfering
5466          * with an already powered-on LVDS power sequencer.
5467          */
5468         if (intel_get_lvds_encoder(dev_priv)) {
5469                 drm_WARN_ON(&dev_priv->drm,
5470                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5471                 drm_info(&dev_priv->drm,
5472                          "LVDS was detected, not registering eDP\n");
5473
5474                 return false;
5475         }
5476
5477         intel_bios_init_panel_early(dev_priv, &intel_connector->panel,
5478                                     encoder->devdata);
5479
5480         if (!intel_pps_init(intel_dp)) {
5481                 drm_info(&dev_priv->drm,
5482                          "[ENCODER:%d:%s] unusable PPS, disabling eDP\n",
5483                          encoder->base.base.id, encoder->base.name);
5484                 /*
5485                  * The BIOS may have still enabled VDD on the PPS even
5486                  * though it's unusable. Make sure we turn it back off
5487                  * and to release the power domain references/etc.
5488                  */
5489                 goto out_vdd_off;
5490         }
5491
5492         /*
5493          * Enable HPD sense for live status check.
5494          * intel_hpd_irq_setup() will turn it off again
5495          * if it's no longer needed later.
5496          *
5497          * The DPCD probe below will make sure VDD is on.
5498          */
5499         intel_hpd_enable_detection(encoder);
5500
5501         /* Cache DPCD and EDID for edp. */
5502         has_dpcd = intel_edp_init_dpcd(intel_dp);
5503
5504         if (!has_dpcd) {
5505                 /* if this fails, presume the device is a ghost */
5506                 drm_info(&dev_priv->drm,
5507                          "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",
5508                          encoder->base.base.id, encoder->base.name);
5509                 goto out_vdd_off;
5510         }
5511
5512         /*
5513          * VBT and straps are liars. Also check HPD as that seems
5514          * to be the most reliable piece of information available.
5515          */
5516         if (!intel_digital_port_connected(encoder)) {
5517                 /*
5518                  * If this fails, presume the DPCD answer came
5519                  * from some other port using the same AUX CH.
5520                  *
5521                  * FIXME maybe cleaner to check this before the
5522                  * DPCD read? Would need sort out the VDD handling...
5523                  */
5524                 drm_info(&dev_priv->drm,
5525                          "[ENCODER:%d:%s] HPD is down, disabling eDP\n",
5526                          encoder->base.base.id, encoder->base.name);
5527                 goto out_vdd_off;
5528         }
5529
5530         mutex_lock(&dev_priv->drm.mode_config.mutex);
5531         drm_edid = drm_edid_read_ddc(connector, &intel_dp->aux.ddc);
5532         if (!drm_edid) {
5533                 /* Fallback to EDID from ACPI OpRegion, if any */
5534                 drm_edid = intel_opregion_get_edid(intel_connector);
5535                 if (drm_edid)
5536                         drm_dbg_kms(&dev_priv->drm,
5537                                     "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
5538                                     connector->base.id, connector->name);
5539         }
5540         if (drm_edid) {
5541                 if (drm_edid_connector_update(connector, drm_edid) ||
5542                     !drm_edid_connector_add_modes(connector)) {
5543                         drm_edid_connector_update(connector, NULL);
5544                         drm_edid_free(drm_edid);
5545                         drm_edid = ERR_PTR(-EINVAL);
5546                 }
5547         } else {
5548                 drm_edid = ERR_PTR(-ENOENT);
5549         }
5550
5551         intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata,
5552                                    IS_ERR(drm_edid) ? NULL : drm_edid);
5553
5554         intel_panel_add_edid_fixed_modes(intel_connector, true);
5555
5556         /* MSO requires information from the EDID */
5557         intel_edp_mso_init(intel_dp);
5558
5559         /* multiply the mode clock and horizontal timings for MSO */
5560         list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)
5561                 intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
5562
5563         /* fallback to VBT if available for eDP */
5564         if (!intel_panel_preferred_fixed_mode(intel_connector))
5565                 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
5566
5567         mutex_unlock(&dev_priv->drm.mode_config.mutex);
5568
5569         if (!intel_panel_preferred_fixed_mode(intel_connector)) {
5570                 drm_info(&dev_priv->drm,
5571                          "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",
5572                          encoder->base.base.id, encoder->base.name);
5573                 goto out_vdd_off;
5574         }
5575
5576         intel_panel_init(intel_connector, drm_edid);
5577
5578         intel_edp_backlight_setup(intel_dp, intel_connector);
5579
5580         intel_edp_add_properties(intel_dp);
5581
5582         intel_pps_init_late(intel_dp);
5583
5584         return true;
5585
5586 out_vdd_off:
5587         intel_pps_vdd_off_sync(intel_dp);
5588
5589         return false;
5590 }
5591
5592 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5593 {
5594         struct intel_connector *intel_connector;
5595         struct drm_connector *connector;
5596
5597         intel_connector = container_of(work, typeof(*intel_connector),
5598                                        modeset_retry_work);
5599         connector = &intel_connector->base;
5600         drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
5601                     connector->name);
5602
5603         /* Grab the locks before changing connector property*/
5604         mutex_lock(&connector->dev->mode_config.mutex);
5605         /* Set connector link status to BAD and send a Uevent to notify
5606          * userspace to do a modeset.
5607          */
5608         drm_connector_set_link_status_property(connector,
5609                                                DRM_MODE_LINK_STATUS_BAD);
5610         mutex_unlock(&connector->dev->mode_config.mutex);
5611         /* Send Hotplug uevent so userspace can reprobe */
5612         drm_kms_helper_connector_hotplug_event(connector);
5613 }
5614
5615 bool
5616 intel_dp_init_connector(struct intel_digital_port *dig_port,
5617                         struct intel_connector *intel_connector)
5618 {
5619         struct drm_connector *connector = &intel_connector->base;
5620         struct intel_dp *intel_dp = &dig_port->dp;
5621         struct intel_encoder *intel_encoder = &dig_port->base;
5622         struct drm_device *dev = intel_encoder->base.dev;
5623         struct drm_i915_private *dev_priv = to_i915(dev);
5624         enum port port = intel_encoder->port;
5625         enum phy phy = intel_port_to_phy(dev_priv, port);
5626         int type;
5627
5628         /* Initialize the work for modeset in case of link train failure */
5629         INIT_WORK(&intel_connector->modeset_retry_work,
5630                   intel_dp_modeset_retry_work_fn);
5631
5632         if (drm_WARN(dev, dig_port->max_lanes < 1,
5633                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
5634                      dig_port->max_lanes, intel_encoder->base.base.id,
5635                      intel_encoder->base.name))
5636                 return false;
5637
5638         intel_dp->reset_link_params = true;
5639         intel_dp->pps.pps_pipe = INVALID_PIPE;
5640         intel_dp->pps.active_pipe = INVALID_PIPE;
5641
5642         /* Preserve the current hw state. */
5643         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
5644         intel_dp->attached_connector = intel_connector;
5645
5646         if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
5647                 /*
5648                  * Currently we don't support eDP on TypeC ports, although in
5649                  * theory it could work on TypeC legacy ports.
5650                  */
5651                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
5652                 type = DRM_MODE_CONNECTOR_eDP;
5653                 intel_encoder->type = INTEL_OUTPUT_EDP;
5654
5655                 /* eDP only on port B and/or C on vlv/chv */
5656                 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
5657                                       IS_CHERRYVIEW(dev_priv)) &&
5658                                 port != PORT_B && port != PORT_C))
5659                         return false;
5660         } else {
5661                 type = DRM_MODE_CONNECTOR_DisplayPort;
5662         }
5663
5664         intel_dp_set_default_sink_rates(intel_dp);
5665         intel_dp_set_default_max_sink_lane_count(intel_dp);
5666
5667         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5668                 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
5669
5670         drm_dbg_kms(&dev_priv->drm,
5671                     "Adding %s connector on [ENCODER:%d:%s]\n",
5672                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5673                     intel_encoder->base.base.id, intel_encoder->base.name);
5674
5675         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5676         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5677
5678         if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12)
5679                 connector->interlace_allowed = true;
5680
5681         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
5682
5683         intel_dp_aux_init(intel_dp);
5684
5685         intel_connector_attach_encoder(intel_connector, intel_encoder);
5686
5687         if (HAS_DDI(dev_priv))
5688                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5689         else
5690                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5691
5692         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5693                 intel_dp_aux_fini(intel_dp);
5694                 goto fail;
5695         }
5696
5697         intel_dp_set_source_rates(intel_dp);
5698         intel_dp_set_common_rates(intel_dp);
5699         intel_dp_reset_max_link_params(intel_dp);
5700
5701         /* init MST on ports that can support it */
5702         intel_dp_mst_encoder_init(dig_port,
5703                                   intel_connector->base.base.id);
5704
5705         intel_dp_add_properties(intel_dp, connector);
5706
5707         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
5708                 int ret = intel_dp_hdcp_init(dig_port, intel_connector);
5709                 if (ret)
5710                         drm_dbg_kms(&dev_priv->drm,
5711                                     "HDCP init failed, skipping.\n");
5712         }
5713
5714         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5715          * 0xd.  Failure to do so will result in spurious interrupts being
5716          * generated on the port when a cable is not attached.
5717          */
5718         if (IS_G45(dev_priv)) {
5719                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
5720                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
5721                                (temp & ~0xf) | 0xd);
5722         }
5723
5724         intel_dp->frl.is_trained = false;
5725         intel_dp->frl.trained_rate_gbps = 0;
5726
5727         intel_psr_init(intel_dp);
5728
5729         return true;
5730
5731 fail:
5732         intel_display_power_flush_work(dev_priv);
5733         drm_connector_cleanup(connector);
5734
5735         return false;
5736 }
5737
5738 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
5739 {
5740         struct intel_encoder *encoder;
5741
5742         if (!HAS_DISPLAY(dev_priv))
5743                 return;
5744
5745         for_each_intel_encoder(&dev_priv->drm, encoder) {
5746                 struct intel_dp *intel_dp;
5747
5748                 if (encoder->type != INTEL_OUTPUT_DDI)
5749                         continue;
5750
5751                 intel_dp = enc_to_intel_dp(encoder);
5752
5753                 if (!intel_dp_mst_source_support(intel_dp))
5754                         continue;
5755
5756                 if (intel_dp->is_mst)
5757                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
5758         }
5759 }
5760
5761 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
5762 {
5763         struct intel_encoder *encoder;
5764
5765         if (!HAS_DISPLAY(dev_priv))
5766                 return;
5767
5768         for_each_intel_encoder(&dev_priv->drm, encoder) {
5769                 struct intel_dp *intel_dp;
5770                 int ret;
5771
5772                 if (encoder->type != INTEL_OUTPUT_DDI)
5773                         continue;
5774
5775                 intel_dp = enc_to_intel_dp(encoder);
5776
5777                 if (!intel_dp_mst_source_support(intel_dp))
5778                         continue;
5779
5780                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
5781                                                      true);
5782                 if (ret) {
5783                         intel_dp->is_mst = false;
5784                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5785                                                         false);
5786                 }
5787         }
5788 }