drivers/gpu/drm/i915/display/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include <linux/input.h>
  29 #include <linux/intel-iommu.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/dma-resv.h>
  33 #include <linux/slab.h>
  34
  35 #include <drm/drm_atomic.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_atomic_uapi.h>
  38 #include <drm/drm_dp_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_fourcc.h>
  41 #include <drm/drm_plane_helper.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/drm_rect.h>
  44
  45 #include "display/intel_crt.h"
  46 #include "display/intel_ddi.h"
  47 #include "display/intel_dp.h"
  48 #include "display/intel_dp_mst.h"
  49 #include "display/intel_dsi.h"
  50 #include "display/intel_dvo.h"
  51 #include "display/intel_gmbus.h"
  52 #include "display/intel_hdmi.h"
  53 #include "display/intel_lvds.h"
  54 #include "display/intel_sdvo.h"
  55 #include "display/intel_tv.h"
  56 #include "display/intel_vdsc.h"
  57
  58 #include "gt/intel_rps.h"
  59
  60 #include "i915_drv.h"
  61 #include "i915_trace.h"
  62 #include "intel_acpi.h"
  63 #include "intel_atomic.h"
  64 #include "intel_atomic_plane.h"
  65 #include "intel_bw.h"
  66 #include "intel_cdclk.h"
  67 #include "intel_color.h"
  68 #include "intel_display_types.h"
  69 #include "intel_dp_link_training.h"
  70 #include "intel_fbc.h"
  71 #include "intel_fbdev.h"
  72 #include "intel_fifo_underrun.h"
  73 #include "intel_frontbuffer.h"
  74 #include "intel_hdcp.h"
  75 #include "intel_hotplug.h"
  76 #include "intel_overlay.h"
  77 #include "intel_pipe_crc.h"
  78 #include "intel_pm.h"
  79 #include "intel_psr.h"
  80 #include "intel_quirks.h"
  81 #include "intel_sideband.h"
  82 #include "intel_sprite.h"
  83 #include "intel_tc.h"
  84 #include "intel_vga.h"
  85
  86 /* Primary plane formats for gen <= 3 */
  87 static const u32 i8xx_primary_formats[] = {
  88         DRM_FORMAT_C8,
  89         DRM_FORMAT_XRGB1555,
  90         DRM_FORMAT_RGB565,
  91         DRM_FORMAT_XRGB8888,
  92 };
  93
  94 /* Primary plane formats for ivb (no fp16 due to hw issue) */
  95 static const u32 ivb_primary_formats[] = {
  96         DRM_FORMAT_C8,
  97         DRM_FORMAT_RGB565,
  98         DRM_FORMAT_XRGB8888,
  99         DRM_FORMAT_XBGR8888,
 100         DRM_FORMAT_XRGB2101010,
 101         DRM_FORMAT_XBGR2101010,
 102 };
 103
 104 /* Primary plane formats for gen >= 4, except ivb */
 105 static const u32 i965_primary_formats[] = {
 106         DRM_FORMAT_C8,
 107         DRM_FORMAT_RGB565,
 108         DRM_FORMAT_XRGB8888,
 109         DRM_FORMAT_XBGR8888,
 110         DRM_FORMAT_XRGB2101010,
 111         DRM_FORMAT_XBGR2101010,
 112         DRM_FORMAT_XBGR16161616F,
 113 };
 114
 115 /* Primary plane formats for vlv/chv */
 116 static const u32 vlv_primary_formats[] = {
 117         DRM_FORMAT_C8,
 118         DRM_FORMAT_RGB565,
 119         DRM_FORMAT_XRGB8888,
 120         DRM_FORMAT_XBGR8888,
 121         DRM_FORMAT_ARGB8888,
 122         DRM_FORMAT_ABGR8888,
 123         DRM_FORMAT_XRGB2101010,
 124         DRM_FORMAT_XBGR2101010,
 125         DRM_FORMAT_ARGB2101010,
 126         DRM_FORMAT_ABGR2101010,
 127         DRM_FORMAT_XBGR16161616F,
 128 };
 129
 130 static const u64 i9xx_format_modifiers[] = {
 131         I915_FORMAT_MOD_X_TILED,
 132         DRM_FORMAT_MOD_LINEAR,
 133         DRM_FORMAT_MOD_INVALID
 134 };
 135
 136 /* Cursor formats */
 137 static const u32 intel_cursor_formats[] = {
 138         DRM_FORMAT_ARGB8888,
 139 };
 140
 141 static const u64 cursor_format_modifiers[] = {
 142         DRM_FORMAT_MOD_LINEAR,
 143         DRM_FORMAT_MOD_INVALID
 144 };
 145
 146 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 147                                 struct intel_crtc_state *pipe_config);
 148 static void ilk_pch_clock_get(struct intel_crtc *crtc,
 149                               struct intel_crtc_state *pipe_config);
 150
 151 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 152                                   struct drm_i915_gem_object *obj,
 153                                   struct drm_mode_fb_cmd2 *mode_cmd);
 154 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
 155 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 156 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
 157                                          const struct intel_link_m_n *m_n,
 158                                          const struct intel_link_m_n *m2_n2);
 159 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
 160 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
 161 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
 162 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
 163 static void vlv_prepare_pll(struct intel_crtc *crtc,
 164                             const struct intel_crtc_state *pipe_config);
 165 static void chv_prepare_pll(struct intel_crtc *crtc,
 166                             const struct intel_crtc_state *pipe_config);
 167 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
 168 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
 169 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 170                                          struct drm_modeset_acquire_ctx *ctx);
 171 static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc);
 172
 173 struct intel_limit {
 174         struct {
 175                 int min, max;
 176         } dot, vco, n, m, m1, m2, p, p1;
 177
 178         struct {
 179                 int dot_limit;
 180                 int p2_slow, p2_fast;
 181         } p2;
 182 };
 183
 184 /* returns HPLL frequency in kHz */
 185 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 186 {
 187         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 188
 189         /* Obtain SKU information */
 190         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 191                 CCK_FUSE_HPLL_FREQ_MASK;
 192
 193         return vco_freq[hpll_freq] * 1000;
 194 }
 195
 196 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 197                       const char *name, u32 reg, int ref_freq)
 198 {
 199         u32 val;
 200         int divider;
 201
 202         val = vlv_cck_read(dev_priv, reg);
 203         divider = val & CCK_FREQUENCY_VALUES;
 204
 205         drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
 206                  (divider << CCK_FREQUENCY_STATUS_SHIFT),
 207                  "%s change in progress\n", name);
 208
 209         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 210 }
 211
 212 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 213                            const char *name, u32 reg)
 214 {
 215         int hpll;
 216
 217         vlv_cck_get(dev_priv);
 218
 219         if (dev_priv->hpll_freq == 0)
 220                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 221
 222         hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
 223
 224         vlv_cck_put(dev_priv);
 225
 226         return hpll;
 227 }
 228
 229 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 230 {
 231         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 232                 return;
 233
 234         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 235                                                       CCK_CZ_CLOCK_CONTROL);
 236
 237         drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
 238                 dev_priv->czclk_freq);
 239 }
 240
 241 static inline u32 /* units of 100MHz */
 242 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 243                     const struct intel_crtc_state *pipe_config)
 244 {
 245         if (HAS_DDI(dev_priv))
 246                 return pipe_config->port_clock; /* SPLL */
 247         else
 248                 return dev_priv->fdi_pll_freq;
 249 }
 250
 251 static const struct intel_limit intel_limits_i8xx_dac = {
 252         .dot = { .min = 25000, .max = 350000 },
 253         .vco = { .min = 908000, .max = 1512000 },
 254         .n = { .min = 2, .max = 16 },
 255         .m = { .min = 96, .max = 140 },
 256         .m1 = { .min = 18, .max = 26 },
 257         .m2 = { .min = 6, .max = 16 },
 258         .p = { .min = 4, .max = 128 },
 259         .p1 = { .min = 2, .max = 33 },
 260         .p2 = { .dot_limit = 165000,
 261                 .p2_slow = 4, .p2_fast = 2 },
 262 };
 263
 264 static const struct intel_limit intel_limits_i8xx_dvo = {
 265         .dot = { .min = 25000, .max = 350000 },
 266         .vco = { .min = 908000, .max = 1512000 },
 267         .n = { .min = 2, .max = 16 },
 268         .m = { .min = 96, .max = 140 },
 269         .m1 = { .min = 18, .max = 26 },
 270         .m2 = { .min = 6, .max = 16 },
 271         .p = { .min = 4, .max = 128 },
 272         .p1 = { .min = 2, .max = 33 },
 273         .p2 = { .dot_limit = 165000,
 274                 .p2_slow = 4, .p2_fast = 4 },
 275 };
 276
 277 static const struct intel_limit intel_limits_i8xx_lvds = {
 278         .dot = { .min = 25000, .max = 350000 },
 279         .vco = { .min = 908000, .max = 1512000 },
 280         .n = { .min = 2, .max = 16 },
 281         .m = { .min = 96, .max = 140 },
 282         .m1 = { .min = 18, .max = 26 },
 283         .m2 = { .min = 6, .max = 16 },
 284         .p = { .min = 4, .max = 128 },
 285         .p1 = { .min = 1, .max = 6 },
 286         .p2 = { .dot_limit = 165000,
 287                 .p2_slow = 14, .p2_fast = 7 },
 288 };
 289
 290 static const struct intel_limit intel_limits_i9xx_sdvo = {
 291         .dot = { .min = 20000, .max = 400000 },
 292         .vco = { .min = 1400000, .max = 2800000 },
 293         .n = { .min = 1, .max = 6 },
 294         .m = { .min = 70, .max = 120 },
 295         .m1 = { .min = 8, .max = 18 },
 296         .m2 = { .min = 3, .max = 7 },
 297         .p = { .min = 5, .max = 80 },
 298         .p1 = { .min = 1, .max = 8 },
 299         .p2 = { .dot_limit = 200000,
 300                 .p2_slow = 10, .p2_fast = 5 },
 301 };
 302
 303 static const struct intel_limit intel_limits_i9xx_lvds = {
 304         .dot = { .min = 20000, .max = 400000 },
 305         .vco = { .min = 1400000, .max = 2800000 },
 306         .n = { .min = 1, .max = 6 },
 307         .m = { .min = 70, .max = 120 },
 308         .m1 = { .min = 8, .max = 18 },
 309         .m2 = { .min = 3, .max = 7 },
 310         .p = { .min = 7, .max = 98 },
 311         .p1 = { .min = 1, .max = 8 },
 312         .p2 = { .dot_limit = 112000,
 313                 .p2_slow = 14, .p2_fast = 7 },
 314 };
 315
 316
 317 static const struct intel_limit intel_limits_g4x_sdvo = {
 318         .dot = { .min = 25000, .max = 270000 },
 319         .vco = { .min = 1750000, .max = 3500000},
 320         .n = { .min = 1, .max = 4 },
 321         .m = { .min = 104, .max = 138 },
 322         .m1 = { .min = 17, .max = 23 },
 323         .m2 = { .min = 5, .max = 11 },
 324         .p = { .min = 10, .max = 30 },
 325         .p1 = { .min = 1, .max = 3},
 326         .p2 = { .dot_limit = 270000,
 327                 .p2_slow = 10,
 328                 .p2_fast = 10
 329         },
 330 };
 331
 332 static const struct intel_limit intel_limits_g4x_hdmi = {
 333         .dot = { .min = 22000, .max = 400000 },
 334         .vco = { .min = 1750000, .max = 3500000},
 335         .n = { .min = 1, .max = 4 },
 336         .m = { .min = 104, .max = 138 },
 337         .m1 = { .min = 16, .max = 23 },
 338         .m2 = { .min = 5, .max = 11 },
 339         .p = { .min = 5, .max = 80 },
 340         .p1 = { .min = 1, .max = 8},
 341         .p2 = { .dot_limit = 165000,
 342                 .p2_slow = 10, .p2_fast = 5 },
 343 };
 344
 345 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 346         .dot = { .min = 20000, .max = 115000 },
 347         .vco = { .min = 1750000, .max = 3500000 },
 348         .n = { .min = 1, .max = 3 },
 349         .m = { .min = 104, .max = 138 },
 350         .m1 = { .min = 17, .max = 23 },
 351         .m2 = { .min = 5, .max = 11 },
 352         .p = { .min = 28, .max = 112 },
 353         .p1 = { .min = 2, .max = 8 },
 354         .p2 = { .dot_limit = 0,
 355                 .p2_slow = 14, .p2_fast = 14
 356         },
 357 };
 358
 359 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 360         .dot = { .min = 80000, .max = 224000 },
 361         .vco = { .min = 1750000, .max = 3500000 },
 362         .n = { .min = 1, .max = 3 },
 363         .m = { .min = 104, .max = 138 },
 364         .m1 = { .min = 17, .max = 23 },
 365         .m2 = { .min = 5, .max = 11 },
 366         .p = { .min = 14, .max = 42 },
 367         .p1 = { .min = 2, .max = 6 },
 368         .p2 = { .dot_limit = 0,
 369                 .p2_slow = 7, .p2_fast = 7
 370         },
 371 };
 372
 373 static const struct intel_limit pnv_limits_sdvo = {
 374         .dot = { .min = 20000, .max = 400000},
 375         .vco = { .min = 1700000, .max = 3500000 },
 376         /* Pineview's Ncounter is a ring counter */
 377         .n = { .min = 3, .max = 6 },
 378         .m = { .min = 2, .max = 256 },
 379         /* Pineview only has one combined m divider, which we treat as m2. */
 380         .m1 = { .min = 0, .max = 0 },
 381         .m2 = { .min = 0, .max = 254 },
 382         .p = { .min = 5, .max = 80 },
 383         .p1 = { .min = 1, .max = 8 },
 384         .p2 = { .dot_limit = 200000,
 385                 .p2_slow = 10, .p2_fast = 5 },
 386 };
 387
 388 static const struct intel_limit pnv_limits_lvds = {
 389         .dot = { .min = 20000, .max = 400000 },
 390         .vco = { .min = 1700000, .max = 3500000 },
 391         .n = { .min = 3, .max = 6 },
 392         .m = { .min = 2, .max = 256 },
 393         .m1 = { .min = 0, .max = 0 },
 394         .m2 = { .min = 0, .max = 254 },
 395         .p = { .min = 7, .max = 112 },
 396         .p1 = { .min = 1, .max = 8 },
 397         .p2 = { .dot_limit = 112000,
 398                 .p2_slow = 14, .p2_fast = 14 },
 399 };
 400
 401 /* Ironlake / Sandybridge
 402  *
 403  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 404  * the range value for them is (actual_value - 2).
 405  */
 406 static const struct intel_limit ilk_limits_dac = {
 407         .dot = { .min = 25000, .max = 350000 },
 408         .vco = { .min = 1760000, .max = 3510000 },
 409         .n = { .min = 1, .max = 5 },
 410         .m = { .min = 79, .max = 127 },
 411         .m1 = { .min = 12, .max = 22 },
 412         .m2 = { .min = 5, .max = 9 },
 413         .p = { .min = 5, .max = 80 },
 414         .p1 = { .min = 1, .max = 8 },
 415         .p2 = { .dot_limit = 225000,
 416                 .p2_slow = 10, .p2_fast = 5 },
 417 };
 418
 419 static const struct intel_limit ilk_limits_single_lvds = {
 420         .dot = { .min = 25000, .max = 350000 },
 421         .vco = { .min = 1760000, .max = 3510000 },
 422         .n = { .min = 1, .max = 3 },
 423         .m = { .min = 79, .max = 118 },
 424         .m1 = { .min = 12, .max = 22 },
 425         .m2 = { .min = 5, .max = 9 },
 426         .p = { .min = 28, .max = 112 },
 427         .p1 = { .min = 2, .max = 8 },
 428         .p2 = { .dot_limit = 225000,
 429                 .p2_slow = 14, .p2_fast = 14 },
 430 };
 431
 432 static const struct intel_limit ilk_limits_dual_lvds = {
 433         .dot = { .min = 25000, .max = 350000 },
 434         .vco = { .min = 1760000, .max = 3510000 },
 435         .n = { .min = 1, .max = 3 },
 436         .m = { .min = 79, .max = 127 },
 437         .m1 = { .min = 12, .max = 22 },
 438         .m2 = { .min = 5, .max = 9 },
 439         .p = { .min = 14, .max = 56 },
 440         .p1 = { .min = 2, .max = 8 },
 441         .p2 = { .dot_limit = 225000,
 442                 .p2_slow = 7, .p2_fast = 7 },
 443 };
 444
 445 /* LVDS 100mhz refclk limits. */
 446 static const struct intel_limit ilk_limits_single_lvds_100m = {
 447         .dot = { .min = 25000, .max = 350000 },
 448         .vco = { .min = 1760000, .max = 3510000 },
 449         .n = { .min = 1, .max = 2 },
 450         .m = { .min = 79, .max = 126 },
 451         .m1 = { .min = 12, .max = 22 },
 452         .m2 = { .min = 5, .max = 9 },
 453         .p = { .min = 28, .max = 112 },
 454         .p1 = { .min = 2, .max = 8 },
 455         .p2 = { .dot_limit = 225000,
 456                 .p2_slow = 14, .p2_fast = 14 },
 457 };
 458
 459 static const struct intel_limit ilk_limits_dual_lvds_100m = {
 460         .dot = { .min = 25000, .max = 350000 },
 461         .vco = { .min = 1760000, .max = 3510000 },
 462         .n = { .min = 1, .max = 3 },
 463         .m = { .min = 79, .max = 126 },
 464         .m1 = { .min = 12, .max = 22 },
 465         .m2 = { .min = 5, .max = 9 },
 466         .p = { .min = 14, .max = 42 },
 467         .p1 = { .min = 2, .max = 6 },
 468         .p2 = { .dot_limit = 225000,
 469                 .p2_slow = 7, .p2_fast = 7 },
 470 };
 471
 472 static const struct intel_limit intel_limits_vlv = {
 473          /*
 474           * These are the data rate limits (measured in fast clocks)
 475           * since those are the strictest limits we have. The fast
 476           * clock and actual rate limits are more relaxed, so checking
 477           * them would make no difference.
 478           */
 479         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 480         .vco = { .min = 4000000, .max = 6000000 },
 481         .n = { .min = 1, .max = 7 },
 482         .m1 = { .min = 2, .max = 3 },
 483         .m2 = { .min = 11, .max = 156 },
 484         .p1 = { .min = 2, .max = 3 },
 485         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 486 };
 487
 488 static const struct intel_limit intel_limits_chv = {
 489         /*
 490          * These are the data rate limits (measured in fast clocks)
 491          * since those are the strictest limits we have.  The fast
 492          * clock and actual rate limits are more relaxed, so checking
 493          * them would make no difference.
 494          */
 495         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 496         .vco = { .min = 4800000, .max = 6480000 },
 497         .n = { .min = 1, .max = 1 },
 498         .m1 = { .min = 2, .max = 2 },
 499         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 500         .p1 = { .min = 2, .max = 4 },
 501         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 502 };
 503
 504 static const struct intel_limit intel_limits_bxt = {
 505         /* FIXME: find real dot limits */
 506         .dot = { .min = 0, .max = INT_MAX },
 507         .vco = { .min = 4800000, .max = 6700000 },
 508         .n = { .min = 1, .max = 1 },
 509         .m1 = { .min = 2, .max = 2 },
 510         /* FIXME: find real m2 limits */
 511         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 512         .p1 = { .min = 2, .max = 4 },
 513         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 514 };
 515
 516 /* WA Display #0827: Gen9:all */
 517 static void
 518 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
 519 {
 520         if (enable)
 521                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 522                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 523         else
 524                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 525                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
 526 }
 527
 528 /* Wa_2006604312:icl */
 529 static void
 530 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 531                        bool enable)
 532 {
 533         if (enable)
 534                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 535                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
 536         else
 537                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 538                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
 539 }
 540
 541 static bool
 542 needs_modeset(const struct intel_crtc_state *state)
 543 {
 544         return drm_atomic_crtc_needs_modeset(&state->uapi);
 545 }
 546
 547 bool
 548 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 549 {
 550         return (crtc_state->master_transcoder != INVALID_TRANSCODER ||
 551                 crtc_state->sync_mode_slaves_mask);
 552 }
 553
 554 static bool
 555 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
 556 {
 557         return crtc_state->master_transcoder != INVALID_TRANSCODER;
 558 }
 559
 560 /*
 561  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 562  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 563  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 564  * The helpers' return value is the rate of the clock that is fed to the
 565  * display engine's pipe which can be the above fast dot clock rate or a
 566  * divided-down version of it.
 567  */
 568 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 569 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 570 {
 571         clock->m = clock->m2 + 2;
 572         clock->p = clock->p1 * clock->p2;
 573         if (WARN_ON(clock->n == 0 || clock->p == 0))
 574                 return 0;
 575         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 576         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 577
 578         return clock->dot;
 579 }
 580
 581 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
 582 {
 583         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 584 }
 585
 586 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 587 {
 588         clock->m = i9xx_dpll_compute_m(clock);
 589         clock->p = clock->p1 * clock->p2;
 590         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 591                 return 0;
 592         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 593         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 594
 595         return clock->dot;
 596 }
 597
 598 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 599 {
 600         clock->m = clock->m1 * clock->m2;
 601         clock->p = clock->p1 * clock->p2;
 602         if (WARN_ON(clock->n == 0 || clock->p == 0))
 603                 return 0;
 604         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 605         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 606
 607         return clock->dot / 5;
 608 }
 609
 610 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 611 {
 612         clock->m = clock->m1 * clock->m2;
 613         clock->p = clock->p1 * clock->p2;
 614         if (WARN_ON(clock->n == 0 || clock->p == 0))
 615                 return 0;
 616         clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
 617                                            clock->n << 22);
 618         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 619
 620         return clock->dot / 5;
 621 }
 622
 623 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 624
 625 /*
 626  * Returns whether the given set of divisors are valid for a given refclk with
 627  * the given connectors.
 628  */
 629 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 630                                const struct intel_limit *limit,
 631                                const struct dpll *clock)
 632 {
 633         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 634                 INTELPllInvalid("n out of range\n");
 635         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 636                 INTELPllInvalid("p1 out of range\n");
 637         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 638                 INTELPllInvalid("m2 out of range\n");
 639         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 640                 INTELPllInvalid("m1 out of range\n");
 641
 642         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 643             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 644                 if (clock->m1 <= clock->m2)
 645                         INTELPllInvalid("m1 <= m2\n");
 646
 647         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 648             !IS_GEN9_LP(dev_priv)) {
 649                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 650                         INTELPllInvalid("p out of range\n");
 651                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 652                         INTELPllInvalid("m out of range\n");
 653         }
 654
 655         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 656                 INTELPllInvalid("vco out of range\n");
 657         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 658          * connector, etc., rather than just a single range.
 659          */
 660         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 661                 INTELPllInvalid("dot out of range\n");
 662
 663         return true;
 664 }
 665
 666 static int
 667 i9xx_select_p2_div(const struct intel_limit *limit,
 668                    const struct intel_crtc_state *crtc_state,
 669                    int target)
 670 {
 671         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 672
 673         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 674                 /*
 675                  * For LVDS just rely on its current settings for dual-channel.
 676                  * We haven't figured out how to reliably set up different
 677                  * single/dual channel state, if we even can.
 678                  */
 679                 if (intel_is_dual_link_lvds(dev_priv))
 680                         return limit->p2.p2_fast;
 681                 else
 682                         return limit->p2.p2_slow;
 683         } else {
 684                 if (target < limit->p2.dot_limit)
 685                         return limit->p2.p2_slow;
 686                 else
 687                         return limit->p2.p2_fast;
 688         }
 689 }
 690
 691 /*
 692  * Returns a set of divisors for the desired target clock with the given
 693  * refclk, or FALSE.  The returned values represent the clock equation:
 694  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 695  *
 696  * Target and reference clocks are specified in kHz.
 697  *
 698  * If match_clock is provided, then best_clock P divider must match the P
 699  * divider from @match_clock used for LVDS downclocking.
 700  */
 701 static bool
 702 i9xx_find_best_dpll(const struct intel_limit *limit,
 703                     struct intel_crtc_state *crtc_state,
 704                     int target, int refclk, struct dpll *match_clock,
 705                     struct dpll *best_clock)
 706 {
 707         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 708         struct dpll clock;
 709         int err = target;
 710
 711         memset(best_clock, 0, sizeof(*best_clock));
 712
 713         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 714
 715         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 716              clock.m1++) {
 717                 for (clock.m2 = limit->m2.min;
 718                      clock.m2 <= limit->m2.max; clock.m2++) {
 719                         if (clock.m2 >= clock.m1)
 720                                 break;
 721                         for (clock.n = limit->n.min;
 722                              clock.n <= limit->n.max; clock.n++) {
 723                                 for (clock.p1 = limit->p1.min;
 724                                         clock.p1 <= limit->p1.max; clock.p1++) {
 725                                         int this_err;
 726
 727                                         i9xx_calc_dpll_params(refclk, &clock);
 728                                         if (!intel_PLL_is_valid(to_i915(dev),
 729                                                                 limit,
 730                                                                 &clock))
 731                                                 continue;
 732                                         if (match_clock &&
 733                                             clock.p != match_clock->p)
 734                                                 continue;
 735
 736                                         this_err = abs(clock.dot - target);
 737                                         if (this_err < err) {
 738                                                 *best_clock = clock;
 739                                                 err = this_err;
 740                                         }
 741                                 }
 742                         }
 743                 }
 744         }
 745
 746         return (err != target);
 747 }
 748
 749 /*
 750  * Returns a set of divisors for the desired target clock with the given
 751  * refclk, or FALSE.  The returned values represent the clock equation:
 752  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 753  *
 754  * Target and reference clocks are specified in kHz.
 755  *
 756  * If match_clock is provided, then best_clock P divider must match the P
 757  * divider from @match_clock used for LVDS downclocking.
 758  */
 759 static bool
 760 pnv_find_best_dpll(const struct intel_limit *limit,
 761                    struct intel_crtc_state *crtc_state,
 762                    int target, int refclk, struct dpll *match_clock,
 763                    struct dpll *best_clock)
 764 {
 765         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 766         struct dpll clock;
 767         int err = target;
 768
 769         memset(best_clock, 0, sizeof(*best_clock));
 770
 771         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 772
 773         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 774              clock.m1++) {
 775                 for (clock.m2 = limit->m2.min;
 776                      clock.m2 <= limit->m2.max; clock.m2++) {
 777                         for (clock.n = limit->n.min;
 778                              clock.n <= limit->n.max; clock.n++) {
 779                                 for (clock.p1 = limit->p1.min;
 780                                         clock.p1 <= limit->p1.max; clock.p1++) {
 781                                         int this_err;
 782
 783                                         pnv_calc_dpll_params(refclk, &clock);
 784                                         if (!intel_PLL_is_valid(to_i915(dev),
 785                                                                 limit,
 786                                                                 &clock))
 787                                                 continue;
 788                                         if (match_clock &&
 789                                             clock.p != match_clock->p)
 790                                                 continue;
 791
 792                                         this_err = abs(clock.dot - target);
 793                                         if (this_err < err) {
 794                                                 *best_clock = clock;
 795                                                 err = this_err;
 796                                         }
 797                                 }
 798                         }
 799                 }
 800         }
 801
 802         return (err != target);
 803 }
 804
 805 /*
 806  * Returns a set of divisors for the desired target clock with the given
 807  * refclk, or FALSE.  The returned values represent the clock equation:
 808  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 809  *
 810  * Target and reference clocks are specified in kHz.
 811  *
 812  * If match_clock is provided, then best_clock P divider must match the P
 813  * divider from @match_clock used for LVDS downclocking.
 814  */
 815 static bool
 816 g4x_find_best_dpll(const struct intel_limit *limit,
 817                    struct intel_crtc_state *crtc_state,
 818                    int target, int refclk, struct dpll *match_clock,
 819                    struct dpll *best_clock)
 820 {
 821         struct drm_device *dev = crtc_state->uapi.crtc->dev;
 822         struct dpll clock;
 823         int max_n;
 824         bool found = false;
 825         /* approximately equals target * 0.00585 */
 826         int err_most = (target >> 8) + (target >> 9);
 827
 828         memset(best_clock, 0, sizeof(*best_clock));
 829
 830         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 831
 832         max_n = limit->n.max;
 833         /* based on hardware requirement, prefer smaller n to precision */
 834         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 835                 /* based on hardware requirement, prefere larger m1,m2 */
 836                 for (clock.m1 = limit->m1.max;
 837                      clock.m1 >= limit->m1.min; clock.m1--) {
 838                         for (clock.m2 = limit->m2.max;
 839                              clock.m2 >= limit->m2.min; clock.m2--) {
 840                                 for (clock.p1 = limit->p1.max;
 841                                      clock.p1 >= limit->p1.min; clock.p1--) {
 842                                         int this_err;
 843
 844                                         i9xx_calc_dpll_params(refclk, &clock);
 845                                         if (!intel_PLL_is_valid(to_i915(dev),
 846                                                                 limit,
 847                                                                 &clock))
 848                                                 continue;
 849
 850                                         this_err = abs(clock.dot - target);
 851                                         if (this_err < err_most) {
 852                                                 *best_clock = clock;
 853                                                 err_most = this_err;
 854                                                 max_n = clock.n;
 855                                                 found = true;
 856                                         }
 857                                 }
 858                         }
 859                 }
 860         }
 861         return found;
 862 }
 863
 864 /*
 865  * Check if the calculated PLL configuration is more optimal compared to the
 866  * best configuration and error found so far. Return the calculated error.
 867  */
 868 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 869                                const struct dpll *calculated_clock,
 870                                const struct dpll *best_clock,
 871                                unsigned int best_error_ppm,
 872                                unsigned int *error_ppm)
 873 {
 874         /*
 875          * For CHV ignore the error and consider only the P value.
 876          * Prefer a bigger P value based on HW requirements.
 877          */
 878         if (IS_CHERRYVIEW(to_i915(dev))) {
 879                 *error_ppm = 0;
 880
 881                 return calculated_clock->p > best_clock->p;
 882         }
 883
 884         if (drm_WARN_ON_ONCE(dev, !target_freq))
 885                 return false;
 886
 887         *error_ppm = div_u64(1000000ULL *
 888                                 abs(target_freq - calculated_clock->dot),
 889                              target_freq);
 890         /*
 891          * Prefer a better P value over a better (smaller) error if the error
 892          * is small. Ensure this preference for future configurations too by
 893          * setting the error to 0.
 894          */
 895         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 896                 *error_ppm = 0;
 897
 898                 return true;
 899         }
 900
 901         return *error_ppm + 10 < best_error_ppm;
 902 }
 903
 904 /*
 905  * Returns a set of divisors for the desired target clock with the given
 906  * refclk, or FALSE.  The returned values represent the clock equation:
 907  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 908  */
 909 static bool
 910 vlv_find_best_dpll(const struct intel_limit *limit,
 911                    struct intel_crtc_state *crtc_state,
 912                    int target, int refclk, struct dpll *match_clock,
 913                    struct dpll *best_clock)
 914 {
 915         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 916         struct drm_device *dev = crtc->base.dev;
 917         struct dpll clock;
 918         unsigned int bestppm = 1000000;
 919         /* min update 19.2 MHz */
 920         int max_n = min(limit->n.max, refclk / 19200);
 921         bool found = false;
 922
 923         target *= 5; /* fast clock */
 924
 925         memset(best_clock, 0, sizeof(*best_clock));
 926
 927         /* based on hardware requirement, prefer smaller n to precision */
 928         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 929                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 930                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 931                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 932                                 clock.p = clock.p1 * clock.p2;
 933                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 934                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 935                                         unsigned int ppm;
 936
 937                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 938                                                                      refclk * clock.m1);
 939
 940                                         vlv_calc_dpll_params(refclk, &clock);
 941
 942                                         if (!intel_PLL_is_valid(to_i915(dev),
 943                                                                 limit,
 944                                                                 &clock))
 945                                                 continue;
 946
 947                                         if (!vlv_PLL_is_optimal(dev, target,
 948                                                                 &clock,
 949                                                                 best_clock,
 950                                                                 bestppm, &ppm))
 951                                                 continue;
 952
 953                                         *best_clock = clock;
 954                                         bestppm = ppm;
 955                                         found = true;
 956                                 }
 957                         }
 958                 }
 959         }
 960
 961         return found;
 962 }
 963
 964 /*
 965  * Returns a set of divisors for the desired target clock with the given
 966  * refclk, or FALSE.  The returned values represent the clock equation:
 967  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 968  */
 969 static bool
 970 chv_find_best_dpll(const struct intel_limit *limit,
 971                    struct intel_crtc_state *crtc_state,
 972                    int target, int refclk, struct dpll *match_clock,
 973                    struct dpll *best_clock)
 974 {
 975         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 976         struct drm_device *dev = crtc->base.dev;
 977         unsigned int best_error_ppm;
 978         struct dpll clock;
 979         u64 m2;
 980         int found = false;
 981
 982         memset(best_clock, 0, sizeof(*best_clock));
 983         best_error_ppm = 1000000;
 984
 985         /*
 986          * Based on hardware doc, the n always set to 1, and m1 always
 987          * set to 2.  If requires to support 200Mhz refclk, we need to
 988          * revisit this because n may not 1 anymore.
 989          */
 990         clock.n = 1, clock.m1 = 2;
 991         target *= 5;    /* fast clock */
 992
 993         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 994                 for (clock.p2 = limit->p2.p2_fast;
 995                                 clock.p2 >= limit->p2.p2_slow;
 996                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 997                         unsigned int error_ppm;
 998
 999                         clock.p = clock.p1 * clock.p2;
1000
1001                         m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
1002                                                    refclk * clock.m1);
1003
1004                         if (m2 > INT_MAX/clock.m1)
1005                                 continue;
1006
1007                         clock.m2 = m2;
1008
1009                         chv_calc_dpll_params(refclk, &clock);
1010
1011                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
1012                                 continue;
1013
1014                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1015                                                 best_error_ppm, &error_ppm))
1016                                 continue;
1017
1018                         *best_clock = clock;
1019                         best_error_ppm = error_ppm;
1020                         found = true;
1021                 }
1022         }
1023
1024         return found;
1025 }
1026
1027 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1028                         struct dpll *best_clock)
1029 {
1030         int refclk = 100000;
1031         const struct intel_limit *limit = &intel_limits_bxt;
1032
1033         return chv_find_best_dpll(limit, crtc_state,
1034                                   crtc_state->port_clock, refclk,
1035                                   NULL, best_clock);
1036 }
1037
1038 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
1039                                     enum pipe pipe)
1040 {
1041         i915_reg_t reg = PIPEDSL(pipe);
1042         u32 line1, line2;
1043         u32 line_mask;
1044
1045         if (IS_GEN(dev_priv, 2))
1046                 line_mask = DSL_LINEMASK_GEN2;
1047         else
1048                 line_mask = DSL_LINEMASK_GEN3;
1049
1050         line1 = intel_de_read(dev_priv, reg) & line_mask;
1051         msleep(5);
1052         line2 = intel_de_read(dev_priv, reg) & line_mask;
1053
1054         return line1 != line2;
1055 }
1056
1057 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
1058 {
1059         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1060         enum pipe pipe = crtc->pipe;
1061
1062         /* Wait for the display line to settle/start moving */
1063         if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
1064                 drm_err(&dev_priv->drm,
1065                         "pipe %c scanline %s wait timed out\n",
1066                         pipe_name(pipe), onoff(state));
1067 }
1068
1069 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1070 {
1071         wait_for_pipe_scanline_moving(crtc, false);
1072 }
1073
1074 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1075 {
1076         wait_for_pipe_scanline_moving(crtc, true);
1077 }
1078
1079 static void
1080 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1081 {
1082         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1083         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1084
1085         if (INTEL_GEN(dev_priv) >= 4) {
1086                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1087                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1088
1089                 /* Wait for the Pipe State to go off */
1090                 if (intel_de_wait_for_clear(dev_priv, reg,
1091                                             I965_PIPECONF_ACTIVE, 100))
1092                         drm_WARN(&dev_priv->drm, 1,
1093                                  "pipe_off wait timed out\n");
1094         } else {
1095                 intel_wait_for_pipe_scanline_stopped(crtc);
1096         }
1097 }
1098
1099 /* Only for pre-ILK configs */
1100 void assert_pll(struct drm_i915_private *dev_priv,
1101                 enum pipe pipe, bool state)
1102 {
1103         u32 val;
1104         bool cur_state;
1105
1106         val = intel_de_read(dev_priv, DPLL(pipe));
1107         cur_state = !!(val & DPLL_VCO_ENABLE);
1108         I915_STATE_WARN(cur_state != state,
1109              "PLL state assertion failure (expected %s, current %s)\n",
1110                         onoff(state), onoff(cur_state));
1111 }
1112
1113 /* XXX: the dsi pll is shared between MIPI DSI ports */
1114 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1115 {
1116         u32 val;
1117         bool cur_state;
1118
1119         vlv_cck_get(dev_priv);
1120         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1121         vlv_cck_put(dev_priv);
1122
1123         cur_state = val & DSI_PLL_VCO_EN;
1124         I915_STATE_WARN(cur_state != state,
1125              "DSI PLL state assertion failure (expected %s, current %s)\n",
1126                         onoff(state), onoff(cur_state));
1127 }
1128
1129 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1130                           enum pipe pipe, bool state)
1131 {
1132         bool cur_state;
1133
1134         if (HAS_DDI(dev_priv)) {
1135                 /*
1136                  * DDI does not have a specific FDI_TX register.
1137                  *
1138                  * FDI is never fed from EDP transcoder
1139                  * so pipe->transcoder cast is fine here.
1140                  */
1141                 enum transcoder cpu_transcoder = (enum transcoder)pipe;
1142                 u32 val = intel_de_read(dev_priv,
1143                                         TRANS_DDI_FUNC_CTL(cpu_transcoder));
1144                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1145         } else {
1146                 u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
1147                 cur_state = !!(val & FDI_TX_ENABLE);
1148         }
1149         I915_STATE_WARN(cur_state != state,
1150              "FDI TX state assertion failure (expected %s, current %s)\n",
1151                         onoff(state), onoff(cur_state));
1152 }
1153 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1154 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1155
1156 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1157                           enum pipe pipe, bool state)
1158 {
1159         u32 val;
1160         bool cur_state;
1161
1162         val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
1163         cur_state = !!(val & FDI_RX_ENABLE);
1164         I915_STATE_WARN(cur_state != state,
1165              "FDI RX state assertion failure (expected %s, current %s)\n",
1166                         onoff(state), onoff(cur_state));
1167 }
1168 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1169 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1170
1171 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1172                                       enum pipe pipe)
1173 {
1174         u32 val;
1175
1176         /* ILK FDI PLL is always enabled */
1177         if (IS_GEN(dev_priv, 5))
1178                 return;
1179
1180         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1181         if (HAS_DDI(dev_priv))
1182                 return;
1183
1184         val = intel_de_read(dev_priv, FDI_TX_CTL(pipe));
1185         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1189                        enum pipe pipe, bool state)
1190 {
1191         u32 val;
1192         bool cur_state;
1193
1194         val = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
1195         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1196         I915_STATE_WARN(cur_state != state,
1197              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1198                         onoff(state), onoff(cur_state));
1199 }
1200
1201 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1202 {
1203         i915_reg_t pp_reg;
1204         u32 val;
1205         enum pipe panel_pipe = INVALID_PIPE;
1206         bool locked = true;
1207
1208         if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv)))
1209                 return;
1210
1211         if (HAS_PCH_SPLIT(dev_priv)) {
1212                 u32 port_sel;
1213
1214                 pp_reg = PP_CONTROL(0);
1215                 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1216
1217                 switch (port_sel) {
1218                 case PANEL_PORT_SELECT_LVDS:
1219                         intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
1220                         break;
1221                 case PANEL_PORT_SELECT_DPA:
1222                         intel_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe);
1223                         break;
1224                 case PANEL_PORT_SELECT_DPC:
1225                         intel_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe);
1226                         break;
1227                 case PANEL_PORT_SELECT_DPD:
1228                         intel_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe);
1229                         break;
1230                 default:
1231                         MISSING_CASE(port_sel);
1232                         break;
1233                 }
1234         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1235                 /* presumably write lock depends on pipe, not port select */
1236                 pp_reg = PP_CONTROL(pipe);
1237                 panel_pipe = pipe;
1238         } else {
1239                 u32 port_sel;
1240
1241                 pp_reg = PP_CONTROL(0);
1242                 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1243
1244                 drm_WARN_ON(&dev_priv->drm,
1245                             port_sel != PANEL_PORT_SELECT_LVDS);
1246                 intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
1247         }
1248
1249         val = intel_de_read(dev_priv, pp_reg);
1250         if (!(val & PANEL_POWER_ON) ||
1251             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1252                 locked = false;
1253
1254         I915_STATE_WARN(panel_pipe == pipe && locked,
1255              "panel assertion failure, pipe %c regs locked\n",
1256              pipe_name(pipe));
1257 }
1258
1259 void assert_pipe(struct drm_i915_private *dev_priv,
1260                  enum transcoder cpu_transcoder, bool state)
1261 {
1262         bool cur_state;
1263         enum intel_display_power_domain power_domain;
1264         intel_wakeref_t wakeref;
1265
1266         /* we keep both pipes enabled on 830 */
1267         if (IS_I830(dev_priv))
1268                 state = true;
1269
1270         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1271         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1272         if (wakeref) {
1273                 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
1274                 cur_state = !!(val & PIPECONF_ENABLE);
1275
1276                 intel_display_power_put(dev_priv, power_domain, wakeref);
1277         } else {
1278                 cur_state = false;
1279         }
1280
1281         I915_STATE_WARN(cur_state != state,
1282                         "transcoder %s assertion failure (expected %s, current %s)\n",
1283                         transcoder_name(cpu_transcoder),
1284                         onoff(state), onoff(cur_state));
1285 }
1286
1287 static void assert_plane(struct intel_plane *plane, bool state)
1288 {
1289         enum pipe pipe;
1290         bool cur_state;
1291
1292         cur_state = plane->get_hw_state(plane, &pipe);
1293
1294         I915_STATE_WARN(cur_state != state,
1295                         "%s assertion failure (expected %s, current %s)\n",
1296                         plane->base.name, onoff(state), onoff(cur_state));
1297 }
1298
1299 #define assert_plane_enabled(p) assert_plane(p, true)
1300 #define assert_plane_disabled(p) assert_plane(p, false)
1301
1302 static void assert_planes_disabled(struct intel_crtc *crtc)
1303 {
1304         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1305         struct intel_plane *plane;
1306
1307         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
1308                 assert_plane_disabled(plane);
1309 }
1310
1311 static void assert_vblank_disabled(struct drm_crtc *crtc)
1312 {
1313         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1314                 drm_crtc_vblank_put(crtc);
1315 }
1316
1317 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1318                                     enum pipe pipe)
1319 {
1320         u32 val;
1321         bool enabled;
1322
1323         val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
1324         enabled = !!(val & TRANS_ENABLE);
1325         I915_STATE_WARN(enabled,
1326              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1327              pipe_name(pipe));
1328 }
1329
1330 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1331                                    enum pipe pipe, enum port port,
1332                                    i915_reg_t dp_reg)
1333 {
1334         enum pipe port_pipe;
1335         bool state;
1336
1337         state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1338
1339         I915_STATE_WARN(state && port_pipe == pipe,
1340                         "PCH DP %c enabled on transcoder %c, should be disabled\n",
1341                         port_name(port), pipe_name(pipe));
1342
1343         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1344                         "IBX PCH DP %c still using transcoder B\n",
1345                         port_name(port));
1346 }
1347
1348 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1349                                      enum pipe pipe, enum port port,
1350                                      i915_reg_t hdmi_reg)
1351 {
1352         enum pipe port_pipe;
1353         bool state;
1354
1355         state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1356
1357         I915_STATE_WARN(state && port_pipe == pipe,
1358                         "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
1359                         port_name(port), pipe_name(pipe));
1360
1361         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1362                         "IBX PCH HDMI %c still using transcoder B\n",
1363                         port_name(port));
1364 }
1365
1366 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1367                                       enum pipe pipe)
1368 {
1369         enum pipe port_pipe;
1370
1371         assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
1372         assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
1373         assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
1374
1375         I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
1376                         port_pipe == pipe,
1377                         "PCH VGA enabled on transcoder %c, should be disabled\n",
1378                         pipe_name(pipe));
1379
1380         I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
1381                         port_pipe == pipe,
1382                         "PCH LVDS enabled on transcoder %c, should be disabled\n",
1383                         pipe_name(pipe));
1384
1385         /* PCH SDVOB multiplex with HDMIB */
1386         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
1387         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
1388         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
1389 }
1390
1391 static void _vlv_enable_pll(struct intel_crtc *crtc,
1392                             const struct intel_crtc_state *pipe_config)
1393 {
1394         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1395         enum pipe pipe = crtc->pipe;
1396
1397         intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1398         intel_de_posting_read(dev_priv, DPLL(pipe));
1399         udelay(150);
1400
1401         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1402                 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
1403 }
1404
1405 static void vlv_enable_pll(struct intel_crtc *crtc,
1406                            const struct intel_crtc_state *pipe_config)
1407 {
1408         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1409         enum pipe pipe = crtc->pipe;
1410
1411         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1412
1413         /* PLL is protected by panel, make sure we can write it */
1414         assert_panel_unlocked(dev_priv, pipe);
1415
1416         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1417                 _vlv_enable_pll(crtc, pipe_config);
1418
1419         intel_de_write(dev_priv, DPLL_MD(pipe),
1420                        pipe_config->dpll_hw_state.dpll_md);
1421         intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1422 }
1423
1424
1425 static void _chv_enable_pll(struct intel_crtc *crtc,
1426                             const struct intel_crtc_state *pipe_config)
1427 {
1428         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1429         enum pipe pipe = crtc->pipe;
1430         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1431         u32 tmp;
1432
1433         vlv_dpio_get(dev_priv);
1434
1435         /* Enable back the 10bit clock to display controller */
1436         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1437         tmp |= DPIO_DCLKP_EN;
1438         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1439
1440         vlv_dpio_put(dev_priv);
1441
1442         /*
1443          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1444          */
1445         udelay(1);
1446
1447         /* Enable PLL */
1448         intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1449
1450         /* Check PLL is locked */
1451         if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1452                 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
1453 }
1454
1455 static void chv_enable_pll(struct intel_crtc *crtc,
1456                            const struct intel_crtc_state *pipe_config)
1457 {
1458         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1459         enum pipe pipe = crtc->pipe;
1460
1461         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
1462
1463         /* PLL is protected by panel, make sure we can write it */
1464         assert_panel_unlocked(dev_priv, pipe);
1465
1466         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1467                 _chv_enable_pll(crtc, pipe_config);
1468
1469         if (pipe != PIPE_A) {
1470                 /*
1471                  * WaPixelRepeatModeFixForC0:chv
1472                  *
1473                  * DPLLCMD is AWOL. Use chicken bits to propagate
1474                  * the value from DPLLBMD to either pipe B or C.
1475                  */
1476                 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
1477                 intel_de_write(dev_priv, DPLL_MD(PIPE_B),
1478                                pipe_config->dpll_hw_state.dpll_md);
1479                 intel_de_write(dev_priv, CBR4_VLV, 0);
1480                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1481
1482                 /*
1483                  * DPLLB VGA mode also seems to cause problems.
1484                  * We should always have it disabled.
1485                  */
1486                 drm_WARN_ON(&dev_priv->drm,
1487                             (intel_de_read(dev_priv, DPLL(PIPE_B)) &
1488                              DPLL_VGA_MODE_DIS) == 0);
1489         } else {
1490                 intel_de_write(dev_priv, DPLL_MD(pipe),
1491                                pipe_config->dpll_hw_state.dpll_md);
1492                 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1493         }
1494 }
1495
1496 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1497 {
1498         if (IS_I830(dev_priv))
1499                 return false;
1500
1501         return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1502 }
1503
1504 static void i9xx_enable_pll(struct intel_crtc *crtc,
1505                             const struct intel_crtc_state *crtc_state)
1506 {
1507         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1508         i915_reg_t reg = DPLL(crtc->pipe);
1509         u32 dpll = crtc_state->dpll_hw_state.dpll;
1510         int i;
1511
1512         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1513
1514         /* PLL is protected by panel, make sure we can write it */
1515         if (i9xx_has_pps(dev_priv))
1516                 assert_panel_unlocked(dev_priv, crtc->pipe);
1517
1518         /*
1519          * Apparently we need to have VGA mode enabled prior to changing
1520          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1521          * dividers, even though the register value does change.
1522          */
1523         intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS);
1524         intel_de_write(dev_priv, reg, dpll);
1525
1526         /* Wait for the clocks to stabilize. */
1527         intel_de_posting_read(dev_priv, reg);
1528         udelay(150);
1529
1530         if (INTEL_GEN(dev_priv) >= 4) {
1531                 intel_de_write(dev_priv, DPLL_MD(crtc->pipe),
1532                                crtc_state->dpll_hw_state.dpll_md);
1533         } else {
1534                 /* The pixel multiplier can only be updated once the
1535                  * DPLL is enabled and the clocks are stable.
1536                  *
1537                  * So write it again.
1538                  */
1539                 intel_de_write(dev_priv, reg, dpll);
1540         }
1541
1542         /* We do this three times for luck */
1543         for (i = 0; i < 3; i++) {
1544                 intel_de_write(dev_priv, reg, dpll);
1545                 intel_de_posting_read(dev_priv, reg);
1546                 udelay(150); /* wait for warmup */
1547         }
1548 }
1549
1550 static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1551 {
1552         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1553         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1554         enum pipe pipe = crtc->pipe;
1555
1556         /* Don't disable pipe or pipe PLLs if needed */
1557         if (IS_I830(dev_priv))
1558                 return;
1559
1560         /* Make sure the pipe isn't still relying on us */
1561         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
1562
1563         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
1564         intel_de_posting_read(dev_priv, DPLL(pipe));
1565 }
1566
1567 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1568 {
1569         u32 val;
1570
1571         /* Make sure the pipe isn't still relying on us */
1572         assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1573
1574         val = DPLL_INTEGRATED_REF_CLK_VLV |
1575                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1576         if (pipe != PIPE_A)
1577                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1578
1579         intel_de_write(dev_priv, DPLL(pipe), val);
1580         intel_de_posting_read(dev_priv, DPLL(pipe));
1581 }
1582
1583 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1584 {
1585         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1586         u32 val;
1587
1588         /* Make sure the pipe isn't still relying on us */
1589         assert_pipe_disabled(dev_priv, (enum transcoder)pipe);
1590
1591         val = DPLL_SSC_REF_CLK_CHV |
1592                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1593         if (pipe != PIPE_A)
1594                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1595
1596         intel_de_write(dev_priv, DPLL(pipe), val);
1597         intel_de_posting_read(dev_priv, DPLL(pipe));
1598
1599         vlv_dpio_get(dev_priv);
1600
1601         /* Disable 10bit clock to display controller */
1602         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1603         val &= ~DPIO_DCLKP_EN;
1604         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1605
1606         vlv_dpio_put(dev_priv);
1607 }
1608
1609 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1610                          struct intel_digital_port *dport,
1611                          unsigned int expected_mask)
1612 {
1613         u32 port_mask;
1614         i915_reg_t dpll_reg;
1615
1616         switch (dport->base.port) {
1617         case PORT_B:
1618                 port_mask = DPLL_PORTB_READY_MASK;
1619                 dpll_reg = DPLL(0);
1620                 break;
1621         case PORT_C:
1622                 port_mask = DPLL_PORTC_READY_MASK;
1623                 dpll_reg = DPLL(0);
1624                 expected_mask <<= 4;
1625                 break;
1626         case PORT_D:
1627                 port_mask = DPLL_PORTD_READY_MASK;
1628                 dpll_reg = DPIO_PHY_STATUS;
1629                 break;
1630         default:
1631                 BUG();
1632         }
1633
1634         if (intel_de_wait_for_register(dev_priv, dpll_reg,
1635                                        port_mask, expected_mask, 1000))
1636                 drm_WARN(&dev_priv->drm, 1,
1637                          "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
1638                          dport->base.base.base.id, dport->base.base.name,
1639                          intel_de_read(dev_priv, dpll_reg) & port_mask,
1640                          expected_mask);
1641 }
1642
1643 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1644 {
1645         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1646         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1647         enum pipe pipe = crtc->pipe;
1648         i915_reg_t reg;
1649         u32 val, pipeconf_val;
1650
1651         /* Make sure PCH DPLL is enabled */
1652         assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
1653
1654         /* FDI must be feeding us bits for PCH ports */
1655         assert_fdi_tx_enabled(dev_priv, pipe);
1656         assert_fdi_rx_enabled(dev_priv, pipe);
1657
1658         if (HAS_PCH_CPT(dev_priv)) {
1659                 reg = TRANS_CHICKEN2(pipe);
1660                 val = intel_de_read(dev_priv, reg);
1661                 /*
1662                  * Workaround: Set the timing override bit
1663                  * before enabling the pch transcoder.
1664                  */
1665                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1666                 /* Configure frame start delay to match the CPU */
1667                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1668                 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1669                 intel_de_write(dev_priv, reg, val);
1670         }
1671
1672         reg = PCH_TRANSCONF(pipe);
1673         val = intel_de_read(dev_priv, reg);
1674         pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
1675
1676         if (HAS_PCH_IBX(dev_priv)) {
1677                 /* Configure frame start delay to match the CPU */
1678                 val &= ~TRANS_FRAME_START_DELAY_MASK;
1679                 val |= TRANS_FRAME_START_DELAY(0);
1680
1681                 /*
1682                  * Make the BPC in transcoder be consistent with
1683                  * that in pipeconf reg. For HDMI we must use 8bpc
1684                  * here for both 8bpc and 12bpc.
1685                  */
1686                 val &= ~PIPECONF_BPC_MASK;
1687                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1688                         val |= PIPECONF_8BPC;
1689                 else
1690                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1691         }
1692
1693         val &= ~TRANS_INTERLACE_MASK;
1694         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
1695                 if (HAS_PCH_IBX(dev_priv) &&
1696                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1697                         val |= TRANS_LEGACY_INTERLACED_ILK;
1698                 else
1699                         val |= TRANS_INTERLACED;
1700         } else {
1701                 val |= TRANS_PROGRESSIVE;
1702         }
1703
1704         intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
1705         if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
1706                 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
1707                         pipe_name(pipe));
1708 }
1709
1710 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1711                                       enum transcoder cpu_transcoder)
1712 {
1713         u32 val, pipeconf_val;
1714
1715         /* FDI must be feeding us bits for PCH ports */
1716         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1717         assert_fdi_rx_enabled(dev_priv, PIPE_A);
1718
1719         val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
1720         /* Workaround: set timing override bit. */
1721         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1722         /* Configure frame start delay to match the CPU */
1723         val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
1724         val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
1725         intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
1726
1727         val = TRANS_ENABLE;
1728         pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
1729
1730         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1731             PIPECONF_INTERLACED_ILK)
1732                 val |= TRANS_INTERLACED;
1733         else
1734                 val |= TRANS_PROGRESSIVE;
1735
1736         intel_de_write(dev_priv, LPT_TRANSCONF, val);
1737         if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
1738                                   TRANS_STATE_ENABLE, 100))
1739                 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
1740 }
1741
1742 static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1743                                        enum pipe pipe)
1744 {
1745         i915_reg_t reg;
1746         u32 val;
1747
1748         /* FDI relies on the transcoder */
1749         assert_fdi_tx_disabled(dev_priv, pipe);
1750         assert_fdi_rx_disabled(dev_priv, pipe);
1751
1752         /* Ports must be off as well */
1753         assert_pch_ports_disabled(dev_priv, pipe);
1754
1755         reg = PCH_TRANSCONF(pipe);
1756         val = intel_de_read(dev_priv, reg);
1757         val &= ~TRANS_ENABLE;
1758         intel_de_write(dev_priv, reg, val);
1759         /* wait for PCH transcoder off, transcoder state */
1760         if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
1761                 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
1762                         pipe_name(pipe));
1763
1764         if (HAS_PCH_CPT(dev_priv)) {
1765                 /* Workaround: Clear the timing override chicken bit again. */
1766                 reg = TRANS_CHICKEN2(pipe);
1767                 val = intel_de_read(dev_priv, reg);
1768                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1769                 intel_de_write(dev_priv, reg, val);
1770         }
1771 }
1772
1773 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1774 {
1775         u32 val;
1776
1777         val = intel_de_read(dev_priv, LPT_TRANSCONF);
1778         val &= ~TRANS_ENABLE;
1779         intel_de_write(dev_priv, LPT_TRANSCONF, val);
1780         /* wait for PCH transcoder off, transcoder state */
1781         if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
1782                                     TRANS_STATE_ENABLE, 50))
1783                 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
1784
1785         /* Workaround: clear timing override bit. */
1786         val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
1787         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1788         intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
1789 }
1790
1791 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1792 {
1793         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1794
1795         if (HAS_PCH_LPT(dev_priv))
1796                 return PIPE_A;
1797         else
1798                 return crtc->pipe;
1799 }
1800
1801 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1802 {
1803         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1804
1805         /*
1806          * On i965gm the hardware frame counter reads
1807          * zero when the TV encoder is enabled :(
1808          */
1809         if (IS_I965GM(dev_priv) &&
1810             (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)))
1811                 return 0;
1812
1813         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1814                 return 0xffffffff; /* full 32 bit counter */
1815         else if (INTEL_GEN(dev_priv) >= 3)
1816                 return 0xffffff; /* only 24 bits of frame count */
1817         else
1818                 return 0; /* Gen2 doesn't have a hardware frame counter */
1819 }
1820
1821 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1822 {
1823         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1824
1825         assert_vblank_disabled(&crtc->base);
1826         drm_crtc_set_max_vblank_count(&crtc->base,
1827                                       intel_crtc_max_vblank_count(crtc_state));
1828         drm_crtc_vblank_on(&crtc->base);
1829 }
1830
1831 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
1832 {
1833         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1834
1835         drm_crtc_vblank_off(&crtc->base);
1836         assert_vblank_disabled(&crtc->base);
1837 }
1838
1839 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1840 {
1841         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1842         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1843         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1844         enum pipe pipe = crtc->pipe;
1845         i915_reg_t reg;
1846         u32 val;
1847
1848         drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
1849
1850         assert_planes_disabled(crtc);
1851
1852         /*
1853          * A pipe without a PLL won't actually be able to drive bits from
1854          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1855          * need the check.
1856          */
1857         if (HAS_GMCH(dev_priv)) {
1858                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1859                         assert_dsi_pll_enabled(dev_priv);
1860                 else
1861                         assert_pll_enabled(dev_priv, pipe);
1862         } else {
1863                 if (new_crtc_state->has_pch_encoder) {
1864                         /* if driving the PCH, we need FDI enabled */
1865                         assert_fdi_rx_pll_enabled(dev_priv,
1866                                                   intel_crtc_pch_transcoder(crtc));
1867                         assert_fdi_tx_pll_enabled(dev_priv,
1868                                                   (enum pipe) cpu_transcoder);
1869                 }
1870                 /* FIXME: assert CPU port conditions for SNB+ */
1871         }
1872
1873         trace_intel_pipe_enable(crtc);
1874
1875         reg = PIPECONF(cpu_transcoder);
1876         val = intel_de_read(dev_priv, reg);
1877         if (val & PIPECONF_ENABLE) {
1878                 /* we keep both pipes enabled on 830 */
1879                 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
1880                 return;
1881         }
1882
1883         intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
1884         intel_de_posting_read(dev_priv, reg);
1885
1886         /*
1887          * Until the pipe starts PIPEDSL reads will return a stale value,
1888          * which causes an apparent vblank timestamp jump when PIPEDSL
1889          * resets to its proper value. That also messes up the frame count
1890          * when it's derived from the timestamps. So let's wait for the
1891          * pipe to start properly before we call drm_crtc_vblank_on()
1892          */
1893         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1894                 intel_wait_for_pipe_scanline_moving(crtc);
1895 }
1896
1897 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1898 {
1899         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1900         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1901         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1902         enum pipe pipe = crtc->pipe;
1903         i915_reg_t reg;
1904         u32 val;
1905
1906         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
1907
1908         /*
1909          * Make sure planes won't keep trying to pump pixels to us,
1910          * or we might hang the display.
1911          */
1912         assert_planes_disabled(crtc);
1913
1914         trace_intel_pipe_disable(crtc);
1915
1916         reg = PIPECONF(cpu_transcoder);
1917         val = intel_de_read(dev_priv, reg);
1918         if ((val & PIPECONF_ENABLE) == 0)
1919                 return;
1920
1921         /*
1922          * Double wide has implications for planes
1923          * so best keep it disabled when not needed.
1924          */
1925         if (old_crtc_state->double_wide)
1926                 val &= ~PIPECONF_DOUBLE_WIDE;
1927
1928         /* Don't disable pipe or pipe PLLs if needed */
1929         if (!IS_I830(dev_priv))
1930                 val &= ~PIPECONF_ENABLE;
1931
1932         intel_de_write(dev_priv, reg, val);
1933         if ((val & PIPECONF_ENABLE) == 0)
1934                 intel_wait_for_pipe_off(old_crtc_state);
1935 }
1936
1937 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1938 {
1939         return IS_GEN(dev_priv, 2) ? 2048 : 4096;
1940 }
1941
1942 static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
1943 {
1944         if (!is_ccs_modifier(fb->modifier))
1945                 return false;
1946
1947         return plane >= fb->format->num_planes / 2;
1948 }
1949
1950 static bool is_gen12_ccs_modifier(u64 modifier)
1951 {
1952         return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
1953                modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
1954
1955 }
1956
1957 static bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
1958 {
1959         return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
1960 }
1961
1962 static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
1963 {
1964         if (is_ccs_modifier(fb->modifier))
1965                 return is_ccs_plane(fb, plane);
1966
1967         return plane == 1;
1968 }
1969
1970 static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
1971 {
1972         WARN_ON(!is_ccs_modifier(fb->modifier) ||
1973                 (main_plane && main_plane >= fb->format->num_planes / 2));
1974
1975         return fb->format->num_planes / 2 + main_plane;
1976 }
1977
1978 static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
1979 {
1980         WARN_ON(!is_ccs_modifier(fb->modifier) ||
1981                 ccs_plane < fb->format->num_planes / 2);
1982
1983         return ccs_plane - fb->format->num_planes / 2;
1984 }
1985
1986 /* Return either the main plane's CCS or - if not a CCS FB - UV plane */
1987 int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
1988 {
1989         if (is_ccs_modifier(fb->modifier))
1990                 return main_to_ccs_plane(fb, main_plane);
1991
1992         return 1;
1993 }
1994
1995 bool
1996 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
1997                                     uint64_t modifier)
1998 {
1999         return info->is_yuv &&
2000                info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
2001 }
2002
2003 static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb,
2004                                    int color_plane)
2005 {
2006         return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
2007                color_plane == 1;
2008 }
2009
2010 static unsigned int
2011 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
2012 {
2013         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2014         unsigned int cpp = fb->format->cpp[color_plane];
2015
2016         switch (fb->modifier) {
2017         case DRM_FORMAT_MOD_LINEAR:
2018                 return intel_tile_size(dev_priv);
2019         case I915_FORMAT_MOD_X_TILED:
2020                 if (IS_GEN(dev_priv, 2))
2021                         return 128;
2022                 else
2023                         return 512;
2024         case I915_FORMAT_MOD_Y_TILED_CCS:
2025                 if (is_ccs_plane(fb, color_plane))
2026                         return 128;
2027                 /* fall through */
2028         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2029         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2030                 if (is_ccs_plane(fb, color_plane))
2031                         return 64;
2032                 /* fall through */
2033         case I915_FORMAT_MOD_Y_TILED:
2034                 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
2035                         return 128;
2036                 else
2037                         return 512;
2038         case I915_FORMAT_MOD_Yf_TILED_CCS:
2039                 if (is_ccs_plane(fb, color_plane))
2040                         return 128;
2041                 /* fall through */
2042         case I915_FORMAT_MOD_Yf_TILED:
2043                 switch (cpp) {
2044                 case 1:
2045                         return 64;
2046                 case 2:
2047                 case 4:
2048                         return 128;
2049                 case 8:
2050                 case 16:
2051                         return 256;
2052                 default:
2053                         MISSING_CASE(cpp);
2054                         return cpp;
2055                 }
2056                 break;
2057         default:
2058                 MISSING_CASE(fb->modifier);
2059                 return cpp;
2060         }
2061 }
2062
2063 static unsigned int
2064 intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
2065 {
2066         if (is_gen12_ccs_plane(fb, color_plane))
2067                 return 1;
2068
2069         return intel_tile_size(to_i915(fb->dev)) /
2070                 intel_tile_width_bytes(fb, color_plane);
2071 }
2072
2073 /* Return the tile dimensions in pixel units */
2074 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
2075                             unsigned int *tile_width,
2076                             unsigned int *tile_height)
2077 {
2078         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
2079         unsigned int cpp = fb->format->cpp[color_plane];
2080
2081         *tile_width = tile_width_bytes / cpp;
2082         *tile_height = intel_tile_height(fb, color_plane);
2083 }
2084
2085 static unsigned int intel_tile_row_size(const struct drm_framebuffer *fb,
2086                                         int color_plane)
2087 {
2088         unsigned int tile_width, tile_height;
2089
2090         intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2091
2092         return fb->pitches[color_plane] * tile_height;
2093 }
2094
2095 unsigned int
2096 intel_fb_align_height(const struct drm_framebuffer *fb,
2097                       int color_plane, unsigned int height)
2098 {
2099         unsigned int tile_height = intel_tile_height(fb, color_plane);
2100
2101         return ALIGN(height, tile_height);
2102 }
2103
2104 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2105 {
2106         unsigned int size = 0;
2107         int i;
2108
2109         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2110                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2111
2112         return size;
2113 }
2114
2115 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
2116 {
2117         unsigned int size = 0;
2118         int i;
2119
2120         for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
2121                 size += rem_info->plane[i].width * rem_info->plane[i].height;
2122
2123         return size;
2124 }
2125
2126 static void
2127 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2128                         const struct drm_framebuffer *fb,
2129                         unsigned int rotation)
2130 {
2131         view->type = I915_GGTT_VIEW_NORMAL;
2132         if (drm_rotation_90_or_270(rotation)) {
2133                 view->type = I915_GGTT_VIEW_ROTATED;
2134                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2135         }
2136 }
2137
2138 static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv)
2139 {
2140         if (IS_I830(dev_priv))
2141                 return 16 * 1024;
2142         else if (IS_I85X(dev_priv))
2143                 return 256;
2144         else if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
2145                 return 32;
2146         else
2147                 return 4 * 1024;
2148 }
2149
2150 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2151 {
2152         if (INTEL_GEN(dev_priv) >= 9)
2153                 return 256 * 1024;
2154         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2155                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2156                 return 128 * 1024;
2157         else if (INTEL_GEN(dev_priv) >= 4)
2158                 return 4 * 1024;
2159         else
2160                 return 0;
2161 }
2162
2163 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2164                                          int color_plane)
2165 {
2166         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2167
2168         /* AUX_DIST needs only 4K alignment */
2169         if ((INTEL_GEN(dev_priv) < 12 && is_aux_plane(fb, color_plane)) ||
2170             is_ccs_plane(fb, color_plane))
2171                 return 4096;
2172
2173         switch (fb->modifier) {
2174         case DRM_FORMAT_MOD_LINEAR:
2175                 return intel_linear_alignment(dev_priv);
2176         case I915_FORMAT_MOD_X_TILED:
2177                 if (INTEL_GEN(dev_priv) >= 9)
2178                         return 256 * 1024;
2179                 return 0;
2180         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2181                 if (is_semiplanar_uv_plane(fb, color_plane))
2182                         return intel_tile_row_size(fb, color_plane);
2183                 /* Fall-through */
2184         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2185                 return 16 * 1024;
2186         case I915_FORMAT_MOD_Y_TILED_CCS:
2187         case I915_FORMAT_MOD_Yf_TILED_CCS:
2188         case I915_FORMAT_MOD_Y_TILED:
2189                 if (INTEL_GEN(dev_priv) >= 12 &&
2190                     is_semiplanar_uv_plane(fb, color_plane))
2191                         return intel_tile_row_size(fb, color_plane);
2192                 /* Fall-through */
2193         case I915_FORMAT_MOD_Yf_TILED:
2194                 return 1 * 1024 * 1024;
2195         default:
2196                 MISSING_CASE(fb->modifier);
2197                 return 0;
2198         }
2199 }
2200
2201 static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2202 {
2203         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2204         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2205
2206         return INTEL_GEN(dev_priv) < 4 ||
2207                 (plane->has_fbc &&
2208                  plane_state->view.type == I915_GGTT_VIEW_NORMAL);
2209 }
2210
2211 struct i915_vma *
2212 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2213                            const struct i915_ggtt_view *view,
2214                            bool uses_fence,
2215                            unsigned long *out_flags)
2216 {
2217         struct drm_device *dev = fb->dev;
2218         struct drm_i915_private *dev_priv = to_i915(dev);
2219         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2220         intel_wakeref_t wakeref;
2221         struct i915_vma *vma;
2222         unsigned int pinctl;
2223         u32 alignment;
2224
2225         if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
2226                 return ERR_PTR(-EINVAL);
2227
2228         alignment = intel_surf_alignment(fb, 0);
2229         if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
2230                 return ERR_PTR(-EINVAL);
2231
2232         /* Note that the w/a also requires 64 PTE of padding following the
2233          * bo. We currently fill all unused PTE with the shadow page and so
2234          * we should always have valid PTE following the scanout preventing
2235          * the VT-d warning.
2236          */
2237         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2238                 alignment = 256 * 1024;
2239
2240         /*
2241          * Global gtt pte registers are special registers which actually forward
2242          * writes to a chunk of system memory. Which means that there is no risk
2243          * that the register values disappear as soon as we call
2244          * intel_runtime_pm_put(), so it is correct to wrap only the
2245          * pin/unpin/fence and not more.
2246          */
2247         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
2248
2249         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
2250
2251         /*
2252          * Valleyview is definitely limited to scanning out the first
2253          * 512MiB. Lets presume this behaviour was inherited from the
2254          * g4x display engine and that all earlier gen are similarly
2255          * limited. Testing suggests that it is a little more
2256          * complicated than this. For example, Cherryview appears quite
2257          * happy to scanout from anywhere within its global aperture.
2258          */
2259         pinctl = 0;
2260         if (HAS_GMCH(dev_priv))
2261                 pinctl |= PIN_MAPPABLE;
2262
2263         vma = i915_gem_object_pin_to_display_plane(obj,
2264                                                    alignment, view, pinctl);
2265         if (IS_ERR(vma))
2266                 goto err;
2267
2268         if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2269                 int ret;
2270
2271                 /*
2272                  * Install a fence for tiled scan-out. Pre-i965 always needs a
2273                  * fence, whereas 965+ only requires a fence if using
2274                  * framebuffer compression.  For simplicity, we always, when
2275                  * possible, install a fence as the cost is not that onerous.
2276                  *
2277                  * If we fail to fence the tiled scanout, then either the
2278                  * modeset will reject the change (which is highly unlikely as
2279                  * the affected systems, all but one, do not have unmappable
2280                  * space) or we will not be able to enable full powersaving
2281                  * techniques (also likely not to apply due to various limits
2282                  * FBC and the like impose on the size of the buffer, which
2283                  * presumably we violated anyway with this unmappable buffer).
2284                  * Anyway, it is presumably better to stumble onwards with
2285                  * something and try to run the system in a "less than optimal"
2286                  * mode that matches the user configuration.
2287                  */
2288                 ret = i915_vma_pin_fence(vma);
2289                 if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
2290                         i915_gem_object_unpin_from_display_plane(vma);
2291                         vma = ERR_PTR(ret);
2292                         goto err;
2293                 }
2294
2295                 if (ret == 0 && vma->fence)
2296                         *out_flags |= PLANE_HAS_FENCE;
2297         }
2298
2299         i915_vma_get(vma);
2300 err:
2301         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
2302         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2303         return vma;
2304 }
2305
2306 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2307 {
2308         i915_gem_object_lock(vma->obj);
2309         if (flags & PLANE_HAS_FENCE)
2310                 i915_vma_unpin_fence(vma);
2311         i915_gem_object_unpin_from_display_plane(vma);
2312         i915_gem_object_unlock(vma->obj);
2313
2314         i915_vma_put(vma);
2315 }
2316
2317 static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2318                           unsigned int rotation)
2319 {
2320         if (drm_rotation_90_or_270(rotation))
2321                 return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
2322         else
2323                 return fb->pitches[color_plane];
2324 }
2325
2326 /*
2327  * Convert the x/y offsets into a linear offset.
2328  * Only valid with 0/180 degree rotation, which is fine since linear
2329  * offset is only used with linear buffers on pre-hsw and tiled buffers
2330  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2331  */
2332 u32 intel_fb_xy_to_linear(int x, int y,
2333                           const struct intel_plane_state *state,
2334                           int color_plane)
2335 {
2336         const struct drm_framebuffer *fb = state->hw.fb;
2337         unsigned int cpp = fb->format->cpp[color_plane];
2338         unsigned int pitch = state->color_plane[color_plane].stride;
2339
2340         return y * pitch + x * cpp;
2341 }
2342
2343 /*
2344  * Add the x/y offsets derived from fb->offsets[] to the user
2345  * specified plane src x/y offsets. The resulting x/y offsets
2346  * specify the start of scanout from the beginning of the gtt mapping.
2347  */
2348 void intel_add_fb_offsets(int *x, int *y,
2349                           const struct intel_plane_state *state,
2350                           int color_plane)
2351
2352 {
2353         *x += state->color_plane[color_plane].x;
2354         *y += state->color_plane[color_plane].y;
2355 }
2356
2357 static u32 intel_adjust_tile_offset(int *x, int *y,
2358                                     unsigned int tile_width,
2359                                     unsigned int tile_height,
2360                                     unsigned int tile_size,
2361                                     unsigned int pitch_tiles,
2362                                     u32 old_offset,
2363                                     u32 new_offset)
2364 {
2365         unsigned int pitch_pixels = pitch_tiles * tile_width;
2366         unsigned int tiles;
2367
2368         WARN_ON(old_offset & (tile_size - 1));
2369         WARN_ON(new_offset & (tile_size - 1));
2370         WARN_ON(new_offset > old_offset);
2371
2372         tiles = (old_offset - new_offset) / tile_size;
2373
2374         *y += tiles / pitch_tiles * tile_height;
2375         *x += tiles % pitch_tiles * tile_width;
2376
2377         /* minimize x in case it got needlessly big */
2378         *y += *x / pitch_pixels * tile_height;
2379         *x %= pitch_pixels;
2380
2381         return new_offset;
2382 }
2383
2384 static bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
2385 {
2386         return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
2387                is_gen12_ccs_plane(fb, color_plane);
2388 }
2389
2390 static u32 intel_adjust_aligned_offset(int *x, int *y,
2391                                        const struct drm_framebuffer *fb,
2392                                        int color_plane,
2393                                        unsigned int rotation,
2394                                        unsigned int pitch,
2395                                        u32 old_offset, u32 new_offset)
2396 {
2397         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2398         unsigned int cpp = fb->format->cpp[color_plane];
2399
2400         drm_WARN_ON(&dev_priv->drm, new_offset > old_offset);
2401
2402         if (!is_surface_linear(fb, color_plane)) {
2403                 unsigned int tile_size, tile_width, tile_height;
2404                 unsigned int pitch_tiles;
2405
2406                 tile_size = intel_tile_size(dev_priv);
2407                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2408
2409                 if (drm_rotation_90_or_270(rotation)) {
2410                         pitch_tiles = pitch / tile_height;
2411                         swap(tile_width, tile_height);
2412                 } else {
2413                         pitch_tiles = pitch / (tile_width * cpp);
2414                 }
2415
2416                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2417                                          tile_size, pitch_tiles,
2418                                          old_offset, new_offset);
2419         } else {
2420                 old_offset += *y * pitch + *x * cpp;
2421
2422                 *y = (old_offset - new_offset) / pitch;
2423                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2424         }
2425
2426         return new_offset;
2427 }
2428
2429 /*
2430  * Adjust the tile offset by moving the difference into
2431  * the x/y offsets.
2432  */
2433 static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2434                                              const struct intel_plane_state *state,
2435                                              int color_plane,
2436                                              u32 old_offset, u32 new_offset)
2437 {
2438         return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
2439                                            state->hw.rotation,
2440                                            state->color_plane[color_plane].stride,
2441                                            old_offset, new_offset);
2442 }
2443
2444 /*
2445  * Computes the aligned offset to the base tile and adjusts
2446  * x, y. bytes per pixel is assumed to be a power-of-two.
2447  *
2448  * In the 90/270 rotated case, x and y are assumed
2449  * to be already rotated to match the rotated GTT view, and
2450  * pitch is the tile_height aligned framebuffer height.
2451  *
2452  * This function is used when computing the derived information
2453  * under intel_framebuffer, so using any of that information
2454  * here is not allowed. Anything under drm_framebuffer can be
2455  * used. This is why the user has to pass in the pitch since it
2456  * is specified in the rotated orientation.
2457  */
2458 static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
2459                                         int *x, int *y,
2460                                         const struct drm_framebuffer *fb,
2461                                         int color_plane,
2462                                         unsigned int pitch,
2463                                         unsigned int rotation,
2464                                         u32 alignment)
2465 {
2466         unsigned int cpp = fb->format->cpp[color_plane];
2467         u32 offset, offset_aligned;
2468
2469         if (!is_surface_linear(fb, color_plane)) {
2470                 unsigned int tile_size, tile_width, tile_height;
2471                 unsigned int tile_rows, tiles, pitch_tiles;
2472
2473                 tile_size = intel_tile_size(dev_priv);
2474                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2475
2476                 if (drm_rotation_90_or_270(rotation)) {
2477                         pitch_tiles = pitch / tile_height;
2478                         swap(tile_width, tile_height);
2479                 } else {
2480                         pitch_tiles = pitch / (tile_width * cpp);
2481                 }
2482
2483                 tile_rows = *y / tile_height;
2484                 *y %= tile_height;
2485
2486                 tiles = *x / tile_width;
2487                 *x %= tile_width;
2488
2489                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2490
2491                 offset_aligned = offset;
2492                 if (alignment)
2493                         offset_aligned = rounddown(offset_aligned, alignment);
2494
2495                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2496                                          tile_size, pitch_tiles,
2497                                          offset, offset_aligned);
2498         } else {
2499                 offset = *y * pitch + *x * cpp;
2500                 offset_aligned = offset;
2501                 if (alignment) {
2502                         offset_aligned = rounddown(offset_aligned, alignment);
2503                         *y = (offset % alignment) / pitch;
2504                         *x = ((offset % alignment) - *y * pitch) / cpp;
2505                 } else {
2506                         *y = *x = 0;
2507                 }
2508         }
2509
2510         return offset_aligned;
2511 }
2512
2513 static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2514                                               const struct intel_plane_state *state,
2515                                               int color_plane)
2516 {
2517         struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
2518         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
2519         const struct drm_framebuffer *fb = state->hw.fb;
2520         unsigned int rotation = state->hw.rotation;
2521         int pitch = state->color_plane[color_plane].stride;
2522         u32 alignment;
2523
2524         if (intel_plane->id == PLANE_CURSOR)
2525                 alignment = intel_cursor_alignment(dev_priv);
2526         else
2527                 alignment = intel_surf_alignment(fb, color_plane);
2528
2529         return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2530                                             pitch, rotation, alignment);
2531 }
2532
2533 /* Convert the fb->offset[] into x/y offsets */
2534 static int intel_fb_offset_to_xy(int *x, int *y,
2535                                  const struct drm_framebuffer *fb,
2536                                  int color_plane)
2537 {
2538         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2539         unsigned int height;
2540         u32 alignment;
2541
2542         if (INTEL_GEN(dev_priv) >= 12 &&
2543             is_semiplanar_uv_plane(fb, color_plane))
2544                 alignment = intel_tile_row_size(fb, color_plane);
2545         else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
2546                 alignment = intel_tile_size(dev_priv);
2547         else
2548                 alignment = 0;
2549
2550         if (alignment != 0 && fb->offsets[color_plane] % alignment) {
2551                 drm_dbg_kms(&dev_priv->drm,
2552                             "Misaligned offset 0x%08x for color plane %d\n",
2553                             fb->offsets[color_plane], color_plane);
2554                 return -EINVAL;
2555         }
2556
2557         height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2558         height = ALIGN(height, intel_tile_height(fb, color_plane));
2559
2560         /* Catch potential overflows early */
2561         if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
2562                             fb->offsets[color_plane])) {
2563                 drm_dbg_kms(&dev_priv->drm,
2564                             "Bad offset 0x%08x or pitch %d for color plane %d\n",
2565                             fb->offsets[color_plane], fb->pitches[color_plane],
2566                             color_plane);
2567                 return -ERANGE;
2568         }
2569
2570         *x = 0;
2571         *y = 0;
2572
2573         intel_adjust_aligned_offset(x, y,
2574                                     fb, color_plane, DRM_MODE_ROTATE_0,
2575                                     fb->pitches[color_plane],
2576                                     fb->offsets[color_plane], 0);
2577
2578         return 0;
2579 }
2580
2581 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2582 {
2583         switch (fb_modifier) {
2584         case I915_FORMAT_MOD_X_TILED:
2585                 return I915_TILING_X;
2586         case I915_FORMAT_MOD_Y_TILED:
2587         case I915_FORMAT_MOD_Y_TILED_CCS:
2588         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2589         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2590                 return I915_TILING_Y;
2591         default:
2592                 return I915_TILING_NONE;
2593         }
2594 }
2595
2596 /*
2597  * From the Sky Lake PRM:
2598  * "The Color Control Surface (CCS) contains the compression status of
2599  *  the cache-line pairs. The compression state of the cache-line pair
2600  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
2601  *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2602  *  cache-line-pairs. CCS is always Y tiled."
2603  *
2604  * Since cache line pairs refers to horizontally adjacent cache lines,
2605  * each cache line in the CCS corresponds to an area of 32x16 cache
2606  * lines on the main surface. Since each pixel is 4 bytes, this gives
2607  * us a ratio of one byte in the CCS for each 8x16 pixels in the
2608  * main surface.
2609  */
2610 static const struct drm_format_info skl_ccs_formats[] = {
2611         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2612           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2613         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2614           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2615         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2616           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2617         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2618           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
2619 };
2620
2621 /*
2622  * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
2623  * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
2624  * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
2625  * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
2626  * the main surface.
2627  */
2628 static const struct drm_format_info gen12_ccs_formats[] = {
2629         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
2630           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2631           .hsub = 1, .vsub = 1, },
2632         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
2633           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2634           .hsub = 1, .vsub = 1, },
2635         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
2636           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2637           .hsub = 1, .vsub = 1, .has_alpha = true },
2638         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
2639           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2640           .hsub = 1, .vsub = 1, .has_alpha = true },
2641         { .format = DRM_FORMAT_YUYV, .num_planes = 2,
2642           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2643           .hsub = 2, .vsub = 1, .is_yuv = true },
2644         { .format = DRM_FORMAT_YVYU, .num_planes = 2,
2645           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2646           .hsub = 2, .vsub = 1, .is_yuv = true },
2647         { .format = DRM_FORMAT_UYVY, .num_planes = 2,
2648           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2649           .hsub = 2, .vsub = 1, .is_yuv = true },
2650         { .format = DRM_FORMAT_VYUY, .num_planes = 2,
2651           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2652           .hsub = 2, .vsub = 1, .is_yuv = true },
2653         { .format = DRM_FORMAT_NV12, .num_planes = 4,
2654           .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
2655           .hsub = 2, .vsub = 2, .is_yuv = true },
2656         { .format = DRM_FORMAT_P010, .num_planes = 4,
2657           .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2658           .hsub = 2, .vsub = 2, .is_yuv = true },
2659         { .format = DRM_FORMAT_P012, .num_planes = 4,
2660           .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2661           .hsub = 2, .vsub = 2, .is_yuv = true },
2662         { .format = DRM_FORMAT_P016, .num_planes = 4,
2663           .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2664           .hsub = 2, .vsub = 2, .is_yuv = true },
2665 };
2666
2667 static const struct drm_format_info *
2668 lookup_format_info(const struct drm_format_info formats[],
2669                    int num_formats, u32 format)
2670 {
2671         int i;
2672
2673         for (i = 0; i < num_formats; i++) {
2674                 if (formats[i].format == format)
2675                         return &formats[i];
2676         }
2677
2678         return NULL;
2679 }
2680
2681 static const struct drm_format_info *
2682 intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2683 {
2684         switch (cmd->modifier[0]) {
2685         case I915_FORMAT_MOD_Y_TILED_CCS:
2686         case I915_FORMAT_MOD_Yf_TILED_CCS:
2687                 return lookup_format_info(skl_ccs_formats,
2688                                           ARRAY_SIZE(skl_ccs_formats),
2689                                           cmd->pixel_format);
2690         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2691         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2692                 return lookup_format_info(gen12_ccs_formats,
2693                                           ARRAY_SIZE(gen12_ccs_formats),
2694                                           cmd->pixel_format);
2695         default:
2696                 return NULL;
2697         }
2698 }
2699
2700 bool is_ccs_modifier(u64 modifier)
2701 {
2702         return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
2703                modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
2704                modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2705                modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2706 }
2707
2708 static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
2709 {
2710         return DIV_ROUND_UP(fb->pitches[ccs_to_main_plane(fb, ccs_plane)],
2711                             512) * 64;
2712 }
2713
2714 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
2715                               u32 pixel_format, u64 modifier)
2716 {
2717         struct intel_crtc *crtc;
2718         struct intel_plane *plane;
2719
2720         /*
2721          * We assume the primary plane for pipe A has
2722          * the highest stride limits of them all,
2723          * if in case pipe A is disabled, use the first pipe from pipe_mask.
2724          */
2725         crtc = intel_get_first_crtc(dev_priv);
2726         if (!crtc)
2727                 return 0;
2728
2729         plane = to_intel_plane(crtc->base.primary);
2730
2731         return plane->max_stride(plane, pixel_format, modifier,
2732                                  DRM_MODE_ROTATE_0);
2733 }
2734
2735 static
2736 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
2737                         u32 pixel_format, u64 modifier)
2738 {
2739         /*
2740          * Arbitrary limit for gen4+ chosen to match the
2741          * render engine max stride.
2742          *
2743          * The new CCS hash mode makes remapping impossible
2744          */
2745         if (!is_ccs_modifier(modifier)) {
2746                 if (INTEL_GEN(dev_priv) >= 7)
2747                         return 256*1024;
2748                 else if (INTEL_GEN(dev_priv) >= 4)
2749                         return 128*1024;
2750         }
2751
2752         return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
2753 }
2754
2755 static u32
2756 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
2757 {
2758         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2759         u32 tile_width;
2760
2761         if (is_surface_linear(fb, color_plane)) {
2762                 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
2763                                                            fb->format->format,
2764                                                            fb->modifier);
2765
2766                 /*
2767                  * To make remapping with linear generally feasible
2768                  * we need the stride to be page aligned.
2769                  */
2770                 if (fb->pitches[color_plane] > max_stride &&
2771                     !is_ccs_modifier(fb->modifier))
2772                         return intel_tile_size(dev_priv);
2773                 else
2774                         return 64;
2775         }
2776
2777         tile_width = intel_tile_width_bytes(fb, color_plane);
2778         if (is_ccs_modifier(fb->modifier)) {
2779                 /*
2780                  * Display WA #0531: skl,bxt,kbl,glk
2781                  *
2782                  * Render decompression and plane width > 3840
2783                  * combined with horizontal panning requires the
2784                  * plane stride to be a multiple of 4. We'll just
2785                  * require the entire fb to accommodate that to avoid
2786                  * potential runtime errors at plane configuration time.
2787                  */
2788                 if (IS_GEN(dev_priv, 9) && color_plane == 0 && fb->width > 3840)
2789                         tile_width *= 4;
2790                 /*
2791                  * The main surface pitch must be padded to a multiple of four
2792                  * tile widths.
2793                  */
2794                 else if (INTEL_GEN(dev_priv) >= 12)
2795                         tile_width *= 4;
2796         }
2797         return tile_width;
2798 }
2799
2800 bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
2801 {
2802         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2803         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
2804         const struct drm_framebuffer *fb = plane_state->hw.fb;
2805         int i;
2806
2807         /* We don't want to deal with remapping with cursors */
2808         if (plane->id == PLANE_CURSOR)
2809                 return false;
2810
2811         /*
2812          * The display engine limits already match/exceed the
2813          * render engine limits, so not much point in remapping.
2814          * Would also need to deal with the fence POT alignment
2815          * and gen2 2KiB GTT tile size.
2816          */
2817         if (INTEL_GEN(dev_priv) < 4)
2818                 return false;
2819
2820         /*
2821          * The new CCS hash mode isn't compatible with remapping as
2822          * the virtual address of the pages affects the compressed data.
2823          */
2824         if (is_ccs_modifier(fb->modifier))
2825                 return false;
2826
2827         /* Linear needs a page aligned stride for remapping */
2828         if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
2829                 unsigned int alignment = intel_tile_size(dev_priv) - 1;
2830
2831                 for (i = 0; i < fb->format->num_planes; i++) {
2832                         if (fb->pitches[i] & alignment)
2833                                 return false;
2834                 }
2835         }
2836
2837         return true;
2838 }
2839
2840 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
2841 {
2842         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
2843         const struct drm_framebuffer *fb = plane_state->hw.fb;
2844         unsigned int rotation = plane_state->hw.rotation;
2845         u32 stride, max_stride;
2846
2847         /*
2848          * No remapping for invisible planes since we don't have
2849          * an actual source viewport to remap.
2850          */
2851         if (!plane_state->uapi.visible)
2852                 return false;
2853
2854         if (!intel_plane_can_remap(plane_state))
2855                 return false;
2856
2857         /*
2858          * FIXME: aux plane limits on gen9+ are
2859          * unclear in Bspec, for now no checking.
2860          */
2861         stride = intel_fb_pitch(fb, 0, rotation);
2862         max_stride = plane->max_stride(plane, fb->format->format,
2863                                        fb->modifier, rotation);
2864
2865         return stride > max_stride;
2866 }
2867
2868 static void
2869 intel_fb_plane_get_subsampling(int *hsub, int *vsub,
2870                                const struct drm_framebuffer *fb,
2871                                int color_plane)
2872 {
2873         int main_plane;
2874
2875         if (color_plane == 0) {
2876                 *hsub = 1;
2877                 *vsub = 1;
2878
2879                 return;
2880         }
2881
2882         /*
2883          * TODO: Deduct the subsampling from the char block for all CCS
2884          * formats and planes.
2885          */
2886         if (!is_gen12_ccs_plane(fb, color_plane)) {
2887                 *hsub = fb->format->hsub;
2888                 *vsub = fb->format->vsub;
2889
2890                 return;
2891         }
2892
2893         main_plane = ccs_to_main_plane(fb, color_plane);
2894         *hsub = drm_format_info_block_width(fb->format, color_plane) /
2895                 drm_format_info_block_width(fb->format, main_plane);
2896
2897         /*
2898          * The min stride check in the core framebuffer_check() function
2899          * assumes that format->hsub applies to every plane except for the
2900          * first plane. That's incorrect for the CCS AUX plane of the first
2901          * plane, but for the above check to pass we must define the block
2902          * width with that subsampling applied to it. Adjust the width here
2903          * accordingly, so we can calculate the actual subsampling factor.
2904          */
2905         if (main_plane == 0)
2906                 *hsub *= fb->format->hsub;
2907
2908         *vsub = 32;
2909 }
2910 static int
2911 intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
2912 {
2913         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2914         int main_plane;
2915         int hsub, vsub;
2916         int tile_width, tile_height;
2917         int ccs_x, ccs_y;
2918         int main_x, main_y;
2919
2920         if (!is_ccs_plane(fb, ccs_plane))
2921                 return 0;
2922
2923         intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
2924         intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
2925
2926         tile_width *= hsub;
2927         tile_height *= vsub;
2928
2929         ccs_x = (x * hsub) % tile_width;
2930         ccs_y = (y * vsub) % tile_height;
2931
2932         main_plane = ccs_to_main_plane(fb, ccs_plane);
2933         main_x = intel_fb->normal[main_plane].x % tile_width;
2934         main_y = intel_fb->normal[main_plane].y % tile_height;
2935
2936         /*
2937          * CCS doesn't have its own x/y offset register, so the intra CCS tile
2938          * x/y offsets must match between CCS and the main surface.
2939          */
2940         if (main_x != ccs_x || main_y != ccs_y) {
2941                 DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
2942                               main_x, main_y,
2943                               ccs_x, ccs_y,
2944                               intel_fb->normal[main_plane].x,
2945                               intel_fb->normal[main_plane].y,
2946                               x, y);
2947                 return -EINVAL;
2948         }
2949
2950         return 0;
2951 }
2952
2953 static void
2954 intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
2955 {
2956         int main_plane = is_ccs_plane(fb, color_plane) ?
2957                          ccs_to_main_plane(fb, color_plane) : 0;
2958         int main_hsub, main_vsub;
2959         int hsub, vsub;
2960
2961         intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, main_plane);
2962         intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
2963         *w = fb->width / main_hsub / hsub;
2964         *h = fb->height / main_vsub / vsub;
2965 }
2966
2967 /*
2968  * Setup the rotated view for an FB plane and return the size the GTT mapping
2969  * requires for this view.
2970  */
2971 static u32
2972 setup_fb_rotation(int plane, const struct intel_remapped_plane_info *plane_info,
2973                   u32 gtt_offset_rotated, int x, int y,
2974                   unsigned int width, unsigned int height,
2975                   unsigned int tile_size,
2976                   unsigned int tile_width, unsigned int tile_height,
2977                   struct drm_framebuffer *fb)
2978 {
2979         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2980         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2981         unsigned int pitch_tiles;
2982         struct drm_rect r;
2983
2984         /* Y or Yf modifiers required for 90/270 rotation */
2985         if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
2986             fb->modifier != I915_FORMAT_MOD_Yf_TILED)
2987                 return 0;
2988
2989         if (WARN_ON(plane >= ARRAY_SIZE(rot_info->plane)))
2990                 return 0;
2991
2992         rot_info->plane[plane] = *plane_info;
2993
2994         intel_fb->rotated[plane].pitch = plane_info->height * tile_height;
2995
2996         /* rotate the x/y offsets to match the GTT view */
2997         drm_rect_init(&r, x, y, width, height);
2998         drm_rect_rotate(&r,
2999                         plane_info->width * tile_width,
3000                         plane_info->height * tile_height,
3001                         DRM_MODE_ROTATE_270);
3002         x = r.x1;
3003         y = r.y1;
3004
3005         /* rotate the tile dimensions to match the GTT view */
3006         pitch_tiles = intel_fb->rotated[plane].pitch / tile_height;
3007         swap(tile_width, tile_height);
3008
3009         /*
3010          * We only keep the x/y offsets, so push all of the
3011          * gtt offset into the x/y offsets.
3012          */
3013         intel_adjust_tile_offset(&x, &y,
3014                                  tile_width, tile_height,
3015                                  tile_size, pitch_tiles,
3016                                  gtt_offset_rotated * tile_size, 0);
3017
3018         /*
3019          * First pixel of the framebuffer from
3020          * the start of the rotated gtt mapping.
3021          */
3022         intel_fb->rotated[plane].x = x;
3023         intel_fb->rotated[plane].y = y;
3024
3025         return plane_info->width * plane_info->height;
3026 }
3027
3028 static int
3029 intel_fill_fb_info(struct drm_i915_private *dev_priv,
3030                    struct drm_framebuffer *fb)
3031 {
3032         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3033         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3034         u32 gtt_offset_rotated = 0;
3035         unsigned int max_size = 0;
3036         int i, num_planes = fb->format->num_planes;
3037         unsigned int tile_size = intel_tile_size(dev_priv);
3038
3039         for (i = 0; i < num_planes; i++) {
3040                 unsigned int width, height;
3041                 unsigned int cpp, size;
3042                 u32 offset;
3043                 int x, y;
3044                 int ret;
3045
3046                 cpp = fb->format->cpp[i];
3047                 intel_fb_plane_dims(&width, &height, fb, i);
3048
3049                 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
3050                 if (ret) {
3051                         drm_dbg_kms(&dev_priv->drm,
3052                                     "bad fb plane %d offset: 0x%x\n",
3053                                     i, fb->offsets[i]);
3054                         return ret;
3055                 }
3056
3057                 ret = intel_fb_check_ccs_xy(fb, i, x, y);
3058                 if (ret)
3059                         return ret;
3060
3061                 /*
3062                  * The fence (if used) is aligned to the start of the object
3063                  * so having the framebuffer wrap around across the edge of the
3064                  * fenced region doesn't really work. We have no API to configure
3065                  * the fence start offset within the object (nor could we probably
3066                  * on gen2/3). So it's just easier if we just require that the
3067                  * fb layout agrees with the fence layout. We already check that the
3068                  * fb stride matches the fence stride elsewhere.
3069                  */
3070                 if (i == 0 && i915_gem_object_is_tiled(obj) &&
3071                     (x + width) * cpp > fb->pitches[i]) {
3072                         drm_dbg_kms(&dev_priv->drm,
3073                                     "bad fb plane %d offset: 0x%x\n",
3074                                      i, fb->offsets[i]);
3075                         return -EINVAL;
3076                 }
3077
3078                 /*
3079                  * First pixel of the framebuffer from
3080                  * the start of the normal gtt mapping.
3081                  */
3082                 intel_fb->normal[i].x = x;
3083                 intel_fb->normal[i].y = y;
3084
3085                 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
3086                                                       fb->pitches[i],
3087                                                       DRM_MODE_ROTATE_0,
3088                                                       tile_size);
3089                 offset /= tile_size;
3090
3091                 if (!is_surface_linear(fb, i)) {
3092                         struct intel_remapped_plane_info plane_info;
3093                         unsigned int tile_width, tile_height;
3094
3095                         intel_tile_dims(fb, i, &tile_width, &tile_height);
3096
3097                         plane_info.offset = offset;
3098                         plane_info.stride = DIV_ROUND_UP(fb->pitches[i],
3099                                                          tile_width * cpp);
3100                         plane_info.width = DIV_ROUND_UP(x + width, tile_width);
3101                         plane_info.height = DIV_ROUND_UP(y + height,
3102                                                          tile_height);
3103
3104                         /* how many tiles does this plane need */
3105                         size = plane_info.stride * plane_info.height;
3106                         /*
3107                          * If the plane isn't horizontally tile aligned,
3108                          * we need one more tile.
3109                          */
3110                         if (x != 0)
3111                                 size++;
3112
3113                         gtt_offset_rotated +=
3114                                 setup_fb_rotation(i, &plane_info,
3115                                                   gtt_offset_rotated,
3116                                                   x, y, width, height,
3117                                                   tile_size,
3118                                                   tile_width, tile_height,
3119                                                   fb);
3120                 } else {
3121                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
3122                                             x * cpp, tile_size);
3123                 }
3124
3125                 /* how many tiles in total needed in the bo */
3126                 max_size = max(max_size, offset + size);
3127         }
3128
3129         if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
3130                 drm_dbg_kms(&dev_priv->drm,
3131                             "fb too big for bo (need %llu bytes, have %zu bytes)\n",
3132                             mul_u32_u32(max_size, tile_size), obj->base.size);
3133                 return -EINVAL;
3134         }
3135
3136         return 0;
3137 }
3138
3139 static void
3140 intel_plane_remap_gtt(struct intel_plane_state *plane_state)
3141 {
3142         struct drm_i915_private *dev_priv =
3143                 to_i915(plane_state->uapi.plane->dev);
3144         struct drm_framebuffer *fb = plane_state->hw.fb;
3145         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3146         struct intel_rotation_info *info = &plane_state->view.rotated;
3147         unsigned int rotation = plane_state->hw.rotation;
3148         int i, num_planes = fb->format->num_planes;
3149         unsigned int tile_size = intel_tile_size(dev_priv);
3150         unsigned int src_x, src_y;
3151         unsigned int src_w, src_h;
3152         u32 gtt_offset = 0;
3153
3154         memset(&plane_state->view, 0, sizeof(plane_state->view));
3155         plane_state->view.type = drm_rotation_90_or_270(rotation) ?
3156                 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
3157
3158         src_x = plane_state->uapi.src.x1 >> 16;
3159         src_y = plane_state->uapi.src.y1 >> 16;
3160         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3161         src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
3162
3163         drm_WARN_ON(&dev_priv->drm, is_ccs_modifier(fb->modifier));
3164
3165         /* Make src coordinates relative to the viewport */
3166         drm_rect_translate(&plane_state->uapi.src,
3167                            -(src_x << 16), -(src_y << 16));
3168
3169         /* Rotate src coordinates to match rotated GTT view */
3170         if (drm_rotation_90_or_270(rotation))
3171                 drm_rect_rotate(&plane_state->uapi.src,
3172                                 src_w << 16, src_h << 16,
3173                                 DRM_MODE_ROTATE_270);
3174
3175         for (i = 0; i < num_planes; i++) {
3176                 unsigned int hsub = i ? fb->format->hsub : 1;
3177                 unsigned int vsub = i ? fb->format->vsub : 1;
3178                 unsigned int cpp = fb->format->cpp[i];
3179                 unsigned int tile_width, tile_height;
3180                 unsigned int width, height;
3181                 unsigned int pitch_tiles;
3182                 unsigned int x, y;
3183                 u32 offset;
3184
3185                 intel_tile_dims(fb, i, &tile_width, &tile_height);
3186
3187                 x = src_x / hsub;
3188                 y = src_y / vsub;
3189                 width = src_w / hsub;
3190                 height = src_h / vsub;
3191
3192                 /*
3193                  * First pixel of the src viewport from the
3194                  * start of the normal gtt mapping.
3195                  */
3196                 x += intel_fb->normal[i].x;
3197                 y += intel_fb->normal[i].y;
3198
3199                 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
3200                                                       fb, i, fb->pitches[i],
3201                                                       DRM_MODE_ROTATE_0, tile_size);
3202                 offset /= tile_size;
3203
3204                 drm_WARN_ON(&dev_priv->drm, i >= ARRAY_SIZE(info->plane));
3205                 info->plane[i].offset = offset;
3206                 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
3207                                                      tile_width * cpp);
3208                 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
3209                 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
3210
3211                 if (drm_rotation_90_or_270(rotation)) {
3212                         struct drm_rect r;
3213
3214                         /* rotate the x/y offsets to match the GTT view */
3215                         drm_rect_init(&r, x, y, width, height);
3216                         drm_rect_rotate(&r,
3217                                         info->plane[i].width * tile_width,
3218                                         info->plane[i].height * tile_height,
3219                                         DRM_MODE_ROTATE_270);
3220                         x = r.x1;
3221                         y = r.y1;
3222
3223                         pitch_tiles = info->plane[i].height;
3224                         plane_state->color_plane[i].stride = pitch_tiles * tile_height;
3225
3226                         /* rotate the tile dimensions to match the GTT view */
3227                         swap(tile_width, tile_height);
3228                 } else {
3229                         pitch_tiles = info->plane[i].width;
3230                         plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
3231                 }
3232
3233                 /*
3234                  * We only keep the x/y offsets, so push all of the
3235                  * gtt offset into the x/y offsets.
3236                  */
3237                 intel_adjust_tile_offset(&x, &y,
3238                                          tile_width, tile_height,
3239                                          tile_size, pitch_tiles,
3240                                          gtt_offset * tile_size, 0);
3241
3242                 gtt_offset += info->plane[i].width * info->plane[i].height;
3243
3244                 plane_state->color_plane[i].offset = 0;
3245                 plane_state->color_plane[i].x = x;
3246                 plane_state->color_plane[i].y = y;
3247         }
3248 }
3249
3250 static int
3251 intel_plane_compute_gtt(struct intel_plane_state *plane_state)
3252 {
3253         const struct intel_framebuffer *fb =
3254                 to_intel_framebuffer(plane_state->hw.fb);
3255         unsigned int rotation = plane_state->hw.rotation;
3256         int i, num_planes;
3257
3258         if (!fb)
3259                 return 0;
3260
3261         num_planes = fb->base.format->num_planes;
3262
3263         if (intel_plane_needs_remap(plane_state)) {
3264                 intel_plane_remap_gtt(plane_state);
3265
3266                 /*
3267                  * Sometimes even remapping can't overcome
3268                  * the stride limitations :( Can happen with
3269                  * big plane sizes and suitably misaligned
3270                  * offsets.
3271                  */
3272                 return intel_plane_check_stride(plane_state);
3273         }
3274
3275         intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
3276
3277         for (i = 0; i < num_planes; i++) {
3278                 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
3279                 plane_state->color_plane[i].offset = 0;
3280
3281                 if (drm_rotation_90_or_270(rotation)) {
3282                         plane_state->color_plane[i].x = fb->rotated[i].x;
3283                         plane_state->color_plane[i].y = fb->rotated[i].y;
3284                 } else {
3285                         plane_state->color_plane[i].x = fb->normal[i].x;
3286                         plane_state->color_plane[i].y = fb->normal[i].y;
3287                 }
3288         }
3289
3290         /* Rotate src coordinates to match rotated GTT view */
3291         if (drm_rotation_90_or_270(rotation))
3292                 drm_rect_rotate(&plane_state->uapi.src,
3293                                 fb->base.width << 16, fb->base.height << 16,
3294                                 DRM_MODE_ROTATE_270);
3295
3296         return intel_plane_check_stride(plane_state);
3297 }
3298
3299 static int i9xx_format_to_fourcc(int format)
3300 {
3301         switch (format) {
3302         case DISPPLANE_8BPP:
3303                 return DRM_FORMAT_C8;
3304         case DISPPLANE_BGRA555:
3305                 return DRM_FORMAT_ARGB1555;
3306         case DISPPLANE_BGRX555:
3307                 return DRM_FORMAT_XRGB1555;
3308         case DISPPLANE_BGRX565:
3309                 return DRM_FORMAT_RGB565;
3310         default:
3311         case DISPPLANE_BGRX888:
3312                 return DRM_FORMAT_XRGB8888;
3313         case DISPPLANE_RGBX888:
3314                 return DRM_FORMAT_XBGR8888;
3315         case DISPPLANE_BGRA888:
3316                 return DRM_FORMAT_ARGB8888;
3317         case DISPPLANE_RGBA888:
3318                 return DRM_FORMAT_ABGR8888;
3319         case DISPPLANE_BGRX101010:
3320                 return DRM_FORMAT_XRGB2101010;
3321         case DISPPLANE_RGBX101010:
3322                 return DRM_FORMAT_XBGR2101010;
3323         case DISPPLANE_BGRA101010:
3324                 return DRM_FORMAT_ARGB2101010;
3325         case DISPPLANE_RGBA101010:
3326                 return DRM_FORMAT_ABGR2101010;
3327         case DISPPLANE_RGBX161616:
3328                 return DRM_FORMAT_XBGR16161616F;
3329         }
3330 }
3331
3332 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
3333 {
3334         switch (format) {
3335         case PLANE_CTL_FORMAT_RGB_565:
3336                 return DRM_FORMAT_RGB565;
3337         case PLANE_CTL_FORMAT_NV12:
3338                 return DRM_FORMAT_NV12;
3339         case PLANE_CTL_FORMAT_P010:
3340                 return DRM_FORMAT_P010;
3341         case PLANE_CTL_FORMAT_P012:
3342                 return DRM_FORMAT_P012;
3343         case PLANE_CTL_FORMAT_P016:
3344                 return DRM_FORMAT_P016;
3345         case PLANE_CTL_FORMAT_Y210:
3346                 return DRM_FORMAT_Y210;
3347         case PLANE_CTL_FORMAT_Y212:
3348                 return DRM_FORMAT_Y212;
3349         case PLANE_CTL_FORMAT_Y216:
3350                 return DRM_FORMAT_Y216;
3351         case PLANE_CTL_FORMAT_Y410:
3352                 return DRM_FORMAT_XVYU2101010;
3353         case PLANE_CTL_FORMAT_Y412:
3354                 return DRM_FORMAT_XVYU12_16161616;
3355         case PLANE_CTL_FORMAT_Y416:
3356                 return DRM_FORMAT_XVYU16161616;
3357         default:
3358         case PLANE_CTL_FORMAT_XRGB_8888:
3359                 if (rgb_order) {
3360                         if (alpha)
3361                                 return DRM_FORMAT_ABGR8888;
3362                         else
3363                                 return DRM_FORMAT_XBGR8888;
3364                 } else {
3365                         if (alpha)
3366                                 return DRM_FORMAT_ARGB8888;
3367                         else
3368                                 return DRM_FORMAT_XRGB8888;
3369                 }
3370         case PLANE_CTL_FORMAT_XRGB_2101010:
3371                 if (rgb_order) {
3372                         if (alpha)
3373                                 return DRM_FORMAT_ABGR2101010;
3374                         else
3375                                 return DRM_FORMAT_XBGR2101010;
3376                 } else {
3377                         if (alpha)
3378                                 return DRM_FORMAT_ARGB2101010;
3379                         else
3380                                 return DRM_FORMAT_XRGB2101010;
3381                 }
3382         case PLANE_CTL_FORMAT_XRGB_16161616F:
3383                 if (rgb_order) {
3384                         if (alpha)
3385                                 return DRM_FORMAT_ABGR16161616F;
3386                         else
3387                                 return DRM_FORMAT_XBGR16161616F;
3388                 } else {
3389                         if (alpha)
3390                                 return DRM_FORMAT_ARGB16161616F;
3391                         else
3392                                 return DRM_FORMAT_XRGB16161616F;
3393                 }
3394         }
3395 }
3396
3397 static struct i915_vma *
3398 initial_plane_vma(struct drm_i915_private *i915,
3399                   struct intel_initial_plane_config *plane_config)
3400 {
3401         struct drm_i915_gem_object *obj;
3402         struct i915_vma *vma;
3403         u32 base, size;
3404
3405         if (plane_config->size == 0)
3406                 return NULL;
3407
3408         base = round_down(plane_config->base,
3409                           I915_GTT_MIN_ALIGNMENT);
3410         size = round_up(plane_config->base + plane_config->size,
3411                         I915_GTT_MIN_ALIGNMENT);
3412         size -= base;
3413
3414         /*
3415          * If the FB is too big, just don't use it since fbdev is not very
3416          * important and we should probably use that space with FBC or other
3417          * features.
3418          */
3419         if (size * 2 > i915->stolen_usable_size)
3420                 return NULL;
3421
3422         obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size);
3423         if (IS_ERR(obj))
3424                 return NULL;
3425
3426         switch (plane_config->tiling) {
3427         case I915_TILING_NONE:
3428                 break;
3429         case I915_TILING_X:
3430         case I915_TILING_Y:
3431                 obj->tiling_and_stride =
3432                         plane_config->fb->base.pitches[0] |
3433                         plane_config->tiling;
3434                 break;
3435         default:
3436                 MISSING_CASE(plane_config->tiling);
3437                 goto err_obj;
3438         }
3439
3440         vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
3441         if (IS_ERR(vma))
3442                 goto err_obj;
3443
3444         if (i915_ggtt_pin(vma, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
3445                 goto err_obj;
3446
3447         if (i915_gem_object_is_tiled(obj) &&
3448             !i915_vma_is_map_and_fenceable(vma))
3449                 goto err_obj;
3450
3451         return vma;
3452
3453 err_obj:
3454         i915_gem_object_put(obj);
3455         return NULL;
3456 }
3457
3458 static bool
3459 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
3460                               struct intel_initial_plane_config *plane_config)
3461 {
3462         struct drm_device *dev = crtc->base.dev;
3463         struct drm_i915_private *dev_priv = to_i915(dev);
3464         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
3465         struct drm_framebuffer *fb = &plane_config->fb->base;
3466         struct i915_vma *vma;
3467
3468         switch (fb->modifier) {
3469         case DRM_FORMAT_MOD_LINEAR:
3470         case I915_FORMAT_MOD_X_TILED:
3471         case I915_FORMAT_MOD_Y_TILED:
3472                 break;
3473         default:
3474                 drm_dbg(&dev_priv->drm,
3475                         "Unsupported modifier for initial FB: 0x%llx\n",
3476                         fb->modifier);
3477                 return false;
3478         }
3479
3480         vma = initial_plane_vma(dev_priv, plane_config);
3481         if (!vma)
3482                 return false;
3483
3484         mode_cmd.pixel_format = fb->format->format;
3485         mode_cmd.width = fb->width;
3486         mode_cmd.height = fb->height;
3487         mode_cmd.pitches[0] = fb->pitches[0];
3488         mode_cmd.modifier[0] = fb->modifier;
3489         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
3490
3491         if (intel_framebuffer_init(to_intel_framebuffer(fb),
3492                                    vma->obj, &mode_cmd)) {
3493                 drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n");
3494                 goto err_vma;
3495         }
3496
3497         plane_config->vma = vma;
3498         return true;
3499
3500 err_vma:
3501         i915_vma_put(vma);
3502         return false;
3503 }
3504
3505 static void
3506 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
3507                         struct intel_plane_state *plane_state,
3508                         bool visible)
3509 {
3510         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
3511
3512         plane_state->uapi.visible = visible;
3513
3514         if (visible)
3515                 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
3516         else
3517                 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
3518 }
3519
3520 static void fixup_active_planes(struct intel_crtc_state *crtc_state)
3521 {
3522         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3523         struct drm_plane *plane;
3524
3525         /*
3526          * Active_planes aliases if multiple "primary" or cursor planes
3527          * have been used on the same (or wrong) pipe. plane_mask uses
3528          * unique ids, hence we can use that to reconstruct active_planes.
3529          */
3530         crtc_state->active_planes = 0;
3531
3532         drm_for_each_plane_mask(plane, &dev_priv->drm,
3533                                 crtc_state->uapi.plane_mask)
3534                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
3535 }
3536
3537 static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
3538                                          struct intel_plane *plane)
3539 {
3540         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3541         struct intel_crtc_state *crtc_state =
3542                 to_intel_crtc_state(crtc->base.state);
3543         struct intel_plane_state *plane_state =
3544                 to_intel_plane_state(plane->base.state);
3545
3546         drm_dbg_kms(&dev_priv->drm,
3547                     "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
3548                     plane->base.base.id, plane->base.name,
3549                     crtc->base.base.id, crtc->base.name);
3550
3551         intel_set_plane_visible(crtc_state, plane_state, false);
3552         fixup_active_planes(crtc_state);
3553         crtc_state->data_rate[plane->id] = 0;
3554         crtc_state->min_cdclk[plane->id] = 0;
3555
3556         if (plane->id == PLANE_PRIMARY)
3557                 hsw_disable_ips(crtc_state);
3558
3559         /*
3560          * Vblank time updates from the shadow to live plane control register
3561          * are blocked if the memory self-refresh mode is active at that
3562          * moment. So to make sure the plane gets truly disabled, disable
3563          * first the self-refresh mode. The self-refresh enable bit in turn
3564          * will be checked/applied by the HW only at the next frame start
3565          * event which is after the vblank start event, so we need to have a
3566          * wait-for-vblank between disabling the plane and the pipe.
3567          */
3568         if (HAS_GMCH(dev_priv) &&
3569             intel_set_memory_cxsr(dev_priv, false))
3570                 intel_wait_for_vblank(dev_priv, crtc->pipe);
3571
3572         /*
3573          * Gen2 reports pipe underruns whenever all planes are disabled.
3574          * So disable underrun reporting before all the planes get disabled.
3575          */
3576         if (IS_GEN(dev_priv, 2) && !crtc_state->active_planes)
3577                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3578
3579         intel_disable_plane(plane, crtc_state);
3580 }
3581
3582 static struct intel_frontbuffer *
3583 to_intel_frontbuffer(struct drm_framebuffer *fb)
3584 {
3585         return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
3586 }
3587
3588 static void
3589 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
3590                              struct intel_initial_plane_config *plane_config)
3591 {
3592         struct drm_device *dev = intel_crtc->base.dev;
3593         struct drm_i915_private *dev_priv = to_i915(dev);
3594         struct drm_crtc *c;
3595         struct drm_plane *primary = intel_crtc->base.primary;
3596         struct drm_plane_state *plane_state = primary->state;
3597         struct intel_plane *intel_plane = to_intel_plane(primary);
3598         struct intel_plane_state *intel_state =
3599                 to_intel_plane_state(plane_state);
3600         struct drm_framebuffer *fb;
3601         struct i915_vma *vma;
3602
3603         if (!plane_config->fb)
3604                 return;
3605
3606         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
3607                 fb = &plane_config->fb->base;
3608                 vma = plane_config->vma;
3609                 goto valid_fb;
3610         }
3611
3612         /*
3613          * Failed to alloc the obj, check to see if we should share
3614          * an fb with another CRTC instead
3615          */
3616         for_each_crtc(dev, c) {
3617                 struct intel_plane_state *state;
3618
3619                 if (c == &intel_crtc->base)
3620                         continue;
3621
3622                 if (!to_intel_crtc(c)->active)
3623                         continue;
3624
3625                 state = to_intel_plane_state(c->primary->state);
3626                 if (!state->vma)
3627                         continue;
3628
3629                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
3630                         fb = state->hw.fb;
3631                         vma = state->vma;
3632                         goto valid_fb;
3633                 }
3634         }
3635
3636         /*
3637          * We've failed to reconstruct the BIOS FB.  Current display state
3638          * indicates that the primary plane is visible, but has a NULL FB,
3639          * which will lead to problems later if we don't fix it up.  The
3640          * simplest solution is to just disable the primary plane now and
3641          * pretend the BIOS never had it enabled.
3642          */
3643         intel_plane_disable_noatomic(intel_crtc, intel_plane);
3644
3645         return;
3646
3647 valid_fb:
3648         intel_state->hw.rotation = plane_config->rotation;
3649         intel_fill_fb_ggtt_view(&intel_state->view, fb,
3650                                 intel_state->hw.rotation);
3651         intel_state->color_plane[0].stride =
3652                 intel_fb_pitch(fb, 0, intel_state->hw.rotation);
3653
3654         __i915_vma_pin(vma);
3655         intel_state->vma = i915_vma_get(vma);
3656         if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0)
3657                 if (vma->fence)
3658                         intel_state->flags |= PLANE_HAS_FENCE;
3659
3660         plane_state->src_x = 0;
3661         plane_state->src_y = 0;
3662         plane_state->src_w = fb->width << 16;
3663         plane_state->src_h = fb->height << 16;
3664
3665         plane_state->crtc_x = 0;
3666         plane_state->crtc_y = 0;
3667         plane_state->crtc_w = fb->width;
3668         plane_state->crtc_h = fb->height;
3669
3670         intel_state->uapi.src = drm_plane_state_src(plane_state);
3671         intel_state->uapi.dst = drm_plane_state_dest(plane_state);
3672
3673         if (plane_config->tiling)
3674                 dev_priv->preserve_bios_swizzle = true;
3675
3676         plane_state->fb = fb;
3677         drm_framebuffer_get(fb);
3678
3679         plane_state->crtc = &intel_crtc->base;
3680         intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
3681
3682         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
3683
3684         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
3685                   &to_intel_frontbuffer(fb)->bits);
3686 }
3687
3688 static int skl_max_plane_width(const struct drm_framebuffer *fb,
3689                                int color_plane,
3690                                unsigned int rotation)
3691 {
3692         int cpp = fb->format->cpp[color_plane];
3693
3694         switch (fb->modifier) {
3695         case DRM_FORMAT_MOD_LINEAR:
3696         case I915_FORMAT_MOD_X_TILED:
3697                 /*
3698                  * Validated limit is 4k, but has 5k should
3699                  * work apart from the following features:
3700                  * - Ytile (already limited to 4k)
3701                  * - FP16 (already limited to 4k)
3702                  * - render compression (already limited to 4k)
3703                  * - KVMR sprite and cursor (don't care)
3704                  * - horizontal panning (TODO verify this)
3705                  * - pipe and plane scaling (TODO verify this)
3706                  */
3707                 if (cpp == 8)
3708                         return 4096;
3709                 else
3710                         return 5120;
3711         case I915_FORMAT_MOD_Y_TILED_CCS:
3712         case I915_FORMAT_MOD_Yf_TILED_CCS:
3713         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
3714                 /* FIXME AUX plane? */
3715         case I915_FORMAT_MOD_Y_TILED:
3716         case I915_FORMAT_MOD_Yf_TILED:
3717                 if (cpp == 8)
3718                         return 2048;
3719                 else
3720                         return 4096;
3721         default:
3722                 MISSING_CASE(fb->modifier);
3723                 return 2048;
3724         }
3725 }
3726
3727 static int glk_max_plane_width(const struct drm_framebuffer *fb,
3728                                int color_plane,
3729                                unsigned int rotation)
3730 {
3731         int cpp = fb->format->cpp[color_plane];
3732
3733         switch (fb->modifier) {
3734         case DRM_FORMAT_MOD_LINEAR:
3735         case I915_FORMAT_MOD_X_TILED:
3736                 if (cpp == 8)
3737                         return 4096;
3738                 else
3739                         return 5120;
3740         case I915_FORMAT_MOD_Y_TILED_CCS:
3741         case I915_FORMAT_MOD_Yf_TILED_CCS:
3742                 /* FIXME AUX plane? */
3743         case I915_FORMAT_MOD_Y_TILED:
3744         case I915_FORMAT_MOD_Yf_TILED:
3745                 if (cpp == 8)
3746                         return 2048;
3747                 else
3748                         return 5120;
3749         default:
3750                 MISSING_CASE(fb->modifier);
3751                 return 2048;
3752         }
3753 }
3754
3755 static int icl_max_plane_width(const struct drm_framebuffer *fb,
3756                                int color_plane,
3757                                unsigned int rotation)
3758 {
3759         return 5120;
3760 }
3761
3762 static int skl_max_plane_height(void)
3763 {
3764         return 4096;
3765 }
3766
3767 static int icl_max_plane_height(void)
3768 {
3769         return 4320;
3770 }
3771
3772 static bool
3773 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3774                                int main_x, int main_y, u32 main_offset,
3775                                int ccs_plane)
3776 {
3777         const struct drm_framebuffer *fb = plane_state->hw.fb;
3778         int aux_x = plane_state->color_plane[ccs_plane].x;
3779         int aux_y = plane_state->color_plane[ccs_plane].y;
3780         u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
3781         u32 alignment = intel_surf_alignment(fb, ccs_plane);
3782         int hsub;
3783         int vsub;
3784
3785         intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
3786         while (aux_offset >= main_offset && aux_y <= main_y) {
3787                 int x, y;
3788
3789                 if (aux_x == main_x && aux_y == main_y)
3790                         break;
3791
3792                 if (aux_offset == 0)
3793                         break;
3794
3795                 x = aux_x / hsub;
3796                 y = aux_y / vsub;
3797                 aux_offset = intel_plane_adjust_aligned_offset(&x, &y,
3798                                                                plane_state,
3799                                                                ccs_plane,
3800                                                                aux_offset,
3801                                                                aux_offset -
3802                                                                 alignment);
3803                 aux_x = x * hsub + aux_x % hsub;
3804                 aux_y = y * vsub + aux_y % vsub;
3805         }
3806
3807         if (aux_x != main_x || aux_y != main_y)
3808                 return false;
3809
3810         plane_state->color_plane[ccs_plane].offset = aux_offset;
3811         plane_state->color_plane[ccs_plane].x = aux_x;
3812         plane_state->color_plane[ccs_plane].y = aux_y;
3813
3814         return true;
3815 }
3816
3817 static int skl_check_main_surface(struct intel_plane_state *plane_state)
3818 {
3819         struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
3820         const struct drm_framebuffer *fb = plane_state->hw.fb;
3821         unsigned int rotation = plane_state->hw.rotation;
3822         int x = plane_state->uapi.src.x1 >> 16;
3823         int y = plane_state->uapi.src.y1 >> 16;
3824         int w = drm_rect_width(&plane_state->uapi.src) >> 16;
3825         int h = drm_rect_height(&plane_state->uapi.src) >> 16;
3826         int max_width;
3827         int max_height;
3828         u32 alignment;
3829         u32 offset;
3830         int aux_plane = intel_main_to_aux_plane(fb, 0);
3831         u32 aux_offset = plane_state->color_plane[aux_plane].offset;
3832
3833         if (INTEL_GEN(dev_priv) >= 11)
3834                 max_width = icl_max_plane_width(fb, 0, rotation);
3835         else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3836                 max_width = glk_max_plane_width(fb, 0, rotation);
3837         else
3838                 max_width = skl_max_plane_width(fb, 0, rotation);
3839
3840         if (INTEL_GEN(dev_priv) >= 11)
3841                 max_height = icl_max_plane_height();
3842         else
3843                 max_height = skl_max_plane_height();
3844
3845         if (w > max_width || h > max_height) {
3846                 drm_dbg_kms(&dev_priv->drm,
3847                             "requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
3848                             w, h, max_width, max_height);
3849                 return -EINVAL;
3850         }
3851
3852         intel_add_fb_offsets(&x, &y, plane_state, 0);
3853         offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3854         alignment = intel_surf_alignment(fb, 0);
3855         if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment)))
3856                 return -EINVAL;
3857
3858         /*
3859          * AUX surface offset is specified as the distance from the
3860          * main surface offset, and it must be non-negative. Make
3861          * sure that is what we will get.
3862          */
3863         if (offset > aux_offset)
3864                 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3865                                                            offset, aux_offset & ~(alignment - 1));
3866
3867         /*
3868          * When using an X-tiled surface, the plane blows up
3869          * if the x offset + width exceed the stride.
3870          *
3871          * TODO: linear and Y-tiled seem fine, Yf untested,
3872          */
3873         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
3874                 int cpp = fb->format->cpp[0];
3875
3876                 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3877                         if (offset == 0) {
3878                                 drm_dbg_kms(&dev_priv->drm,
3879                                             "Unable to find suitable display surface offset due to X-tiling\n");
3880                                 return -EINVAL;
3881                         }
3882
3883                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3884                                                                    offset, offset - alignment);
3885                 }
3886         }
3887
3888         /*
3889          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3890          * they match with the main surface x/y offsets.
3891          */
3892         if (is_ccs_modifier(fb->modifier)) {
3893                 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
3894                                                        offset, aux_plane)) {
3895                         if (offset == 0)
3896                                 break;
3897
3898                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3899                                                                    offset, offset - alignment);
3900                 }
3901
3902                 if (x != plane_state->color_plane[aux_plane].x ||
3903                     y != plane_state->color_plane[aux_plane].y) {
3904                         drm_dbg_kms(&dev_priv->drm,
3905                                     "Unable to find suitable display surface offset due to CCS\n");
3906                         return -EINVAL;
3907                 }
3908         }
3909
3910         plane_state->color_plane[0].offset = offset;
3911         plane_state->color_plane[0].x = x;
3912         plane_state->color_plane[0].y = y;
3913
3914         /*
3915          * Put the final coordinates back so that the src
3916          * coordinate checks will see the right values.
3917          */
3918         drm_rect_translate_to(&plane_state->uapi.src,
3919                               x << 16, y << 16);
3920
3921         return 0;
3922 }
3923
3924 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3925 {
3926         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
3927         const struct drm_framebuffer *fb = plane_state->hw.fb;
3928         unsigned int rotation = plane_state->hw.rotation;
3929         int uv_plane = 1;
3930         int max_width = skl_max_plane_width(fb, uv_plane, rotation);
3931         int max_height = 4096;
3932         int x = plane_state->uapi.src.x1 >> 17;
3933         int y = plane_state->uapi.src.y1 >> 17;
3934         int w = drm_rect_width(&plane_state->uapi.src) >> 17;
3935         int h = drm_rect_height(&plane_state->uapi.src) >> 17;
3936         u32 offset;
3937
3938         intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
3939         offset = intel_plane_compute_aligned_offset(&x, &y,
3940                                                     plane_state, uv_plane);
3941
3942         /* FIXME not quite sure how/if these apply to the chroma plane */
3943         if (w > max_width || h > max_height) {
3944                 drm_dbg_kms(&i915->drm,
3945                             "CbCr source size %dx%d too big (limit %dx%d)\n",
3946                             w, h, max_width, max_height);
3947                 return -EINVAL;
3948         }
3949
3950         if (is_ccs_modifier(fb->modifier)) {
3951                 int ccs_plane = main_to_ccs_plane(fb, uv_plane);
3952                 int aux_offset = plane_state->color_plane[ccs_plane].offset;
3953                 int alignment = intel_surf_alignment(fb, uv_plane);
3954
3955                 if (offset > aux_offset)
3956                         offset = intel_plane_adjust_aligned_offset(&x, &y,
3957                                                                    plane_state,
3958                                                                    uv_plane,
3959                                                                    offset,
3960                                                                    aux_offset & ~(alignment - 1));
3961
3962                 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
3963                                                        offset, ccs_plane)) {
3964                         if (offset == 0)
3965                                 break;
3966
3967                         offset = intel_plane_adjust_aligned_offset(&x, &y,
3968                                                                    plane_state,
3969                                                                    uv_plane,
3970                                                                    offset, offset - alignment);
3971                 }
3972
3973                 if (x != plane_state->color_plane[ccs_plane].x ||
3974                     y != plane_state->color_plane[ccs_plane].y) {
3975                         drm_dbg_kms(&i915->drm,
3976                                     "Unable to find suitable display surface offset due to CCS\n");
3977                         return -EINVAL;
3978                 }
3979         }
3980
3981         plane_state->color_plane[uv_plane].offset = offset;
3982         plane_state->color_plane[uv_plane].x = x;
3983         plane_state->color_plane[uv_plane].y = y;
3984
3985         return 0;
3986 }
3987
3988 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
3989 {
3990         const struct drm_framebuffer *fb = plane_state->hw.fb;
3991         int src_x = plane_state->uapi.src.x1 >> 16;
3992         int src_y = plane_state->uapi.src.y1 >> 16;
3993         u32 offset;
3994         int ccs_plane;
3995
3996         for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) {
3997                 int main_hsub, main_vsub;
3998                 int hsub, vsub;
3999                 int x, y;
4000
4001                 if (!is_ccs_plane(fb, ccs_plane))
4002                         continue;
4003
4004                 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
4005                                                ccs_to_main_plane(fb, ccs_plane));
4006                 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
4007
4008                 hsub *= main_hsub;
4009                 vsub *= main_vsub;
4010                 x = src_x / hsub;
4011                 y = src_y / vsub;
4012
4013                 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
4014
4015                 offset = intel_plane_compute_aligned_offset(&x, &y,
4016                                                             plane_state,
4017                                                             ccs_plane);
4018
4019                 plane_state->color_plane[ccs_plane].offset = offset;
4020                 plane_state->color_plane[ccs_plane].x = (x * hsub +
4021                                                          src_x % hsub) /
4022                                                         main_hsub;
4023                 plane_state->color_plane[ccs_plane].y = (y * vsub +
4024                                                          src_y % vsub) /
4025                                                         main_vsub;
4026         }
4027
4028         return 0;
4029 }
4030
4031 int skl_check_plane_surface(struct intel_plane_state *plane_state)
4032 {
4033         const struct drm_framebuffer *fb = plane_state->hw.fb;
4034         int ret;
4035         bool needs_aux = false;
4036
4037         ret = intel_plane_compute_gtt(plane_state);
4038         if (ret)
4039                 return ret;
4040
4041         if (!plane_state->uapi.visible)
4042                 return 0;
4043
4044         /*
4045          * Handle the AUX surface first since the main surface setup depends on
4046          * it.
4047          */
4048         if (is_ccs_modifier(fb->modifier)) {
4049                 needs_aux = true;
4050                 ret = skl_check_ccs_aux_surface(plane_state);
4051                 if (ret)
4052                         return ret;
4053         }
4054
4055         if (intel_format_info_is_yuv_semiplanar(fb->format,
4056                                                 fb->modifier)) {
4057                 needs_aux = true;
4058                 ret = skl_check_nv12_aux_surface(plane_state);
4059                 if (ret)
4060                         return ret;
4061         }
4062
4063         if (!needs_aux) {
4064                 int i;
4065
4066                 for (i = 1; i < fb->format->num_planes; i++) {
4067                         plane_state->color_plane[i].offset = ~0xfff;
4068                         plane_state->color_plane[i].x = 0;
4069                         plane_state->color_plane[i].y = 0;
4070                 }
4071         }
4072
4073         ret = skl_check_main_surface(plane_state);
4074         if (ret)
4075                 return ret;
4076
4077         return 0;
4078 }
4079
4080 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
4081                              const struct intel_plane_state *plane_state,
4082                              unsigned int *num, unsigned int *den)
4083 {
4084         const struct drm_framebuffer *fb = plane_state->hw.fb;
4085         unsigned int cpp = fb->format->cpp[0];
4086
4087         /*
4088          * g4x bspec says 64bpp pixel rate can't exceed 80%
4089          * of cdclk when the sprite plane is enabled on the
4090          * same pipe. ilk/snb bspec says 64bpp pixel rate is
4091          * never allowed to exceed 80% of cdclk. Let's just go
4092          * with the ilk/snb limit always.
4093          */
4094         if (cpp == 8) {
4095                 *num = 10;
4096                 *den = 8;
4097         } else {
4098                 *num = 1;
4099                 *den = 1;
4100         }
4101 }
4102
4103 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
4104                                 const struct intel_plane_state *plane_state)
4105 {
4106         unsigned int pixel_rate;
4107         unsigned int num, den;
4108
4109         /*
4110          * Note that crtc_state->pixel_rate accounts for both
4111          * horizontal and vertical panel fitter downscaling factors.
4112          * Pre-HSW bspec tells us to only consider the horizontal
4113          * downscaling factor here. We ignore that and just consider
4114          * both for simplicity.
4115          */
4116         pixel_rate = crtc_state->pixel_rate;
4117
4118         i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
4119
4120         /* two pixels per clock with double wide pipe */
4121         if (crtc_state->double_wide)
4122                 den *= 2;
4123
4124         return DIV_ROUND_UP(pixel_rate * num, den);
4125 }
4126
4127 unsigned int
4128 i9xx_plane_max_stride(struct intel_plane *plane,
4129                       u32 pixel_format, u64 modifier,
4130                       unsigned int rotation)
4131 {
4132         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4133
4134         if (!HAS_GMCH(dev_priv)) {
4135                 return 32*1024;
4136         } else if (INTEL_GEN(dev_priv) >= 4) {
4137                 if (modifier == I915_FORMAT_MOD_X_TILED)
4138                         return 16*1024;
4139                 else
4140                         return 32*1024;
4141         } else if (INTEL_GEN(dev_priv) >= 3) {
4142                 if (modifier == I915_FORMAT_MOD_X_TILED)
4143                         return 8*1024;
4144                 else
4145                         return 16*1024;
4146         } else {
4147                 if (plane->i9xx_plane == PLANE_C)
4148                         return 4*1024;
4149                 else
4150                         return 8*1024;
4151         }
4152 }
4153
4154 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4155 {
4156         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4157         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4158         u32 dspcntr = 0;
4159
4160         if (crtc_state->gamma_enable)
4161                 dspcntr |= DISPPLANE_GAMMA_ENABLE;
4162
4163         if (crtc_state->csc_enable)
4164                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
4165
4166         if (INTEL_GEN(dev_priv) < 5)
4167                 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
4168
4169         return dspcntr;
4170 }
4171
4172 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
4173                           const struct intel_plane_state *plane_state)
4174 {
4175         struct drm_i915_private *dev_priv =
4176                 to_i915(plane_state->uapi.plane->dev);
4177         const struct drm_framebuffer *fb = plane_state->hw.fb;
4178         unsigned int rotation = plane_state->hw.rotation;
4179         u32 dspcntr;
4180
4181         dspcntr = DISPLAY_PLANE_ENABLE;
4182
4183         if (IS_G4X(dev_priv) || IS_GEN(dev_priv, 5) ||
4184             IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
4185                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
4186
4187         switch (fb->format->format) {
4188         case DRM_FORMAT_C8:
4189                 dspcntr |= DISPPLANE_8BPP;
4190                 break;
4191         case DRM_FORMAT_XRGB1555:
4192                 dspcntr |= DISPPLANE_BGRX555;
4193                 break;
4194         case DRM_FORMAT_ARGB1555:
4195                 dspcntr |= DISPPLANE_BGRA555;
4196                 break;
4197         case DRM_FORMAT_RGB565:
4198                 dspcntr |= DISPPLANE_BGRX565;
4199                 break;
4200         case DRM_FORMAT_XRGB8888:
4201                 dspcntr |= DISPPLANE_BGRX888;
4202                 break;
4203         case DRM_FORMAT_XBGR8888:
4204                 dspcntr |= DISPPLANE_RGBX888;
4205                 break;
4206         case DRM_FORMAT_ARGB8888:
4207                 dspcntr |= DISPPLANE_BGRA888;
4208                 break;
4209         case DRM_FORMAT_ABGR8888:
4210                 dspcntr |= DISPPLANE_RGBA888;
4211                 break;
4212         case DRM_FORMAT_XRGB2101010:
4213                 dspcntr |= DISPPLANE_BGRX101010;
4214                 break;
4215         case DRM_FORMAT_XBGR2101010:
4216                 dspcntr |= DISPPLANE_RGBX101010;
4217                 break;
4218         case DRM_FORMAT_ARGB2101010:
4219                 dspcntr |= DISPPLANE_BGRA101010;
4220                 break;
4221         case DRM_FORMAT_ABGR2101010:
4222                 dspcntr |= DISPPLANE_RGBA101010;
4223                 break;
4224         case DRM_FORMAT_XBGR16161616F:
4225                 dspcntr |= DISPPLANE_RGBX161616;
4226                 break;
4227         default:
4228                 MISSING_CASE(fb->format->format);
4229                 return 0;
4230         }
4231
4232         if (INTEL_GEN(dev_priv) >= 4 &&
4233             fb->modifier == I915_FORMAT_MOD_X_TILED)
4234                 dspcntr |= DISPPLANE_TILED;
4235
4236         if (rotation & DRM_MODE_ROTATE_180)
4237                 dspcntr |= DISPPLANE_ROTATE_180;
4238
4239         if (rotation & DRM_MODE_REFLECT_X)
4240                 dspcntr |= DISPPLANE_MIRROR;
4241
4242         return dspcntr;
4243 }
4244
4245 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
4246 {
4247         struct drm_i915_private *dev_priv =
4248                 to_i915(plane_state->uapi.plane->dev);
4249         const struct drm_framebuffer *fb = plane_state->hw.fb;
4250         int src_x, src_y, src_w;
4251         u32 offset;
4252         int ret;
4253
4254         ret = intel_plane_compute_gtt(plane_state);
4255         if (ret)
4256                 return ret;
4257
4258         if (!plane_state->uapi.visible)
4259                 return 0;
4260
4261         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4262         src_x = plane_state->uapi.src.x1 >> 16;
4263         src_y = plane_state->uapi.src.y1 >> 16;
4264
4265         /* Undocumented hardware limit on i965/g4x/vlv/chv */
4266         if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
4267                 return -EINVAL;
4268
4269         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
4270
4271         if (INTEL_GEN(dev_priv) >= 4)
4272                 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
4273                                                             plane_state, 0);
4274         else
4275                 offset = 0;
4276
4277         /*
4278          * Put the final coordinates back so that the src
4279          * coordinate checks will see the right values.
4280          */
4281         drm_rect_translate_to(&plane_state->uapi.src,
4282                               src_x << 16, src_y << 16);
4283
4284         /* HSW/BDW do this automagically in hardware */
4285         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
4286                 unsigned int rotation = plane_state->hw.rotation;
4287                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4288                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
4289
4290                 if (rotation & DRM_MODE_ROTATE_180) {
4291                         src_x += src_w - 1;
4292                         src_y += src_h - 1;
4293                 } else if (rotation & DRM_MODE_REFLECT_X) {
4294                         src_x += src_w - 1;
4295                 }
4296         }
4297
4298         plane_state->color_plane[0].offset = offset;
4299         plane_state->color_plane[0].x = src_x;
4300         plane_state->color_plane[0].y = src_y;
4301
4302         return 0;
4303 }
4304
4305 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
4306 {
4307         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4308         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4309
4310         if (IS_CHERRYVIEW(dev_priv))
4311                 return i9xx_plane == PLANE_B;
4312         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
4313                 return false;
4314         else if (IS_GEN(dev_priv, 4))
4315                 return i9xx_plane == PLANE_C;
4316         else
4317                 return i9xx_plane == PLANE_B ||
4318                         i9xx_plane == PLANE_C;
4319 }
4320
4321 static int
4322 i9xx_plane_check(struct intel_crtc_state *crtc_state,
4323                  struct intel_plane_state *plane_state)
4324 {
4325         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4326         int ret;
4327
4328         ret = chv_plane_check_rotation(plane_state);
4329         if (ret)
4330                 return ret;
4331
4332         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
4333                                                   &crtc_state->uapi,
4334                                                   DRM_PLANE_HELPER_NO_SCALING,
4335                                                   DRM_PLANE_HELPER_NO_SCALING,
4336                                                   i9xx_plane_has_windowing(plane),
4337                                                   true);
4338         if (ret)
4339                 return ret;
4340
4341         ret = i9xx_check_plane_surface(plane_state);
4342         if (ret)
4343                 return ret;
4344
4345         if (!plane_state->uapi.visible)
4346                 return 0;
4347
4348         ret = intel_plane_check_src_coordinates(plane_state);
4349         if (ret)
4350                 return ret;
4351
4352         plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
4353
4354         return 0;
4355 }
4356
4357 static void i9xx_update_plane(struct intel_plane *plane,
4358                               const struct intel_crtc_state *crtc_state,
4359                               const struct intel_plane_state *plane_state)
4360 {
4361         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4362         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4363         u32 linear_offset;
4364         int x = plane_state->color_plane[0].x;
4365         int y = plane_state->color_plane[0].y;
4366         int crtc_x = plane_state->uapi.dst.x1;
4367         int crtc_y = plane_state->uapi.dst.y1;
4368         int crtc_w = drm_rect_width(&plane_state->uapi.dst);
4369         int crtc_h = drm_rect_height(&plane_state->uapi.dst);
4370         unsigned long irqflags;
4371         u32 dspaddr_offset;
4372         u32 dspcntr;
4373
4374         dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
4375
4376         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
4377
4378         if (INTEL_GEN(dev_priv) >= 4)
4379                 dspaddr_offset = plane_state->color_plane[0].offset;
4380         else
4381                 dspaddr_offset = linear_offset;
4382
4383         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4384
4385         intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
4386                           plane_state->color_plane[0].stride);
4387
4388         if (INTEL_GEN(dev_priv) < 4) {
4389                 /*
4390                  * PLANE_A doesn't actually have a full window
4391                  * generator but let's assume we still need to
4392                  * program whatever is there.
4393                  */
4394                 intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
4395                                   (crtc_y << 16) | crtc_x);
4396                 intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
4397                                   ((crtc_h - 1) << 16) | (crtc_w - 1));
4398         } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
4399                 intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
4400                                   (crtc_y << 16) | crtc_x);
4401                 intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
4402                                   ((crtc_h - 1) << 16) | (crtc_w - 1));
4403                 intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
4404         }
4405
4406         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
4407                 intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
4408                                   (y << 16) | x);
4409         } else if (INTEL_GEN(dev_priv) >= 4) {
4410                 intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
4411                                   linear_offset);
4412                 intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
4413                                   (y << 16) | x);
4414         }
4415
4416         /*
4417          * The control register self-arms if the plane was previously
4418          * disabled. Try to make the plane enable atomic by writing
4419          * the control register just before the surface register.
4420          */
4421         intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
4422         if (INTEL_GEN(dev_priv) >= 4)
4423                 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
4424                                   intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4425         else
4426                 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
4427                                   intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4428
4429         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4430 }
4431
4432 static void i9xx_disable_plane(struct intel_plane *plane,
4433                                const struct intel_crtc_state *crtc_state)
4434 {
4435         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4436         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4437         unsigned long irqflags;
4438         u32 dspcntr;
4439
4440         /*
4441          * DSPCNTR pipe gamma enable on g4x+ and pipe csc
4442          * enable on ilk+ affect the pipe bottom color as
4443          * well, so we must configure them even if the plane
4444          * is disabled.
4445          *
4446          * On pre-g4x there is no way to gamma correct the
4447          * pipe bottom color but we'll keep on doing this
4448          * anyway so that the crtc state readout works correctly.
4449          */
4450         dspcntr = i9xx_plane_ctl_crtc(crtc_state);
4451
4452         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4453
4454         intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
4455         if (INTEL_GEN(dev_priv) >= 4)
4456                 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
4457         else
4458                 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0);
4459
4460         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4461 }
4462
4463 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
4464                                     enum pipe *pipe)
4465 {
4466         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
4467         enum intel_display_power_domain power_domain;
4468         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4469         intel_wakeref_t wakeref;
4470         bool ret;
4471         u32 val;
4472
4473         /*
4474          * Not 100% correct for planes that can move between pipes,
4475          * but that's only the case for gen2-4 which don't have any
4476          * display power wells.
4477          */
4478         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
4479         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4480         if (!wakeref)
4481                 return false;
4482
4483         val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
4484
4485         ret = val & DISPLAY_PLANE_ENABLE;
4486
4487         if (INTEL_GEN(dev_priv) >= 5)
4488                 *pipe = plane->pipe;
4489         else
4490                 *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
4491                         DISPPLANE_SEL_PIPE_SHIFT;
4492
4493         intel_display_power_put(dev_priv, power_domain, wakeref);
4494
4495         return ret;
4496 }
4497
4498 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
4499 {
4500         struct drm_device *dev = intel_crtc->base.dev;
4501         struct drm_i915_private *dev_priv = to_i915(dev);
4502         unsigned long irqflags;
4503
4504         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
4505
4506         intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0);
4507         intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
4508         intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
4509
4510         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
4511 }
4512
4513 /*
4514  * This function detaches (aka. unbinds) unused scalers in hardware
4515  */
4516 static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
4517 {
4518         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
4519         const struct intel_crtc_scaler_state *scaler_state =
4520                 &crtc_state->scaler_state;
4521         int i;
4522
4523         /* loop through and disable scalers that aren't in use */
4524         for (i = 0; i < intel_crtc->num_scalers; i++) {
4525                 if (!scaler_state->scalers[i].in_use)
4526                         skl_detach_scaler(intel_crtc, i);
4527         }
4528 }
4529
4530 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
4531                                           int color_plane, unsigned int rotation)
4532 {
4533         /*
4534          * The stride is either expressed as a multiple of 64 bytes chunks for
4535          * linear buffers or in number of tiles for tiled buffers.
4536          */
4537         if (is_surface_linear(fb, color_plane))
4538                 return 64;
4539         else if (drm_rotation_90_or_270(rotation))
4540                 return intel_tile_height(fb, color_plane);
4541         else
4542                 return intel_tile_width_bytes(fb, color_plane);
4543 }
4544
4545 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
4546                      int color_plane)
4547 {
4548         const struct drm_framebuffer *fb = plane_state->hw.fb;
4549         unsigned int rotation = plane_state->hw.rotation;
4550         u32 stride = plane_state->color_plane[color_plane].stride;
4551
4552         if (color_plane >= fb->format->num_planes)
4553                 return 0;
4554
4555         return stride / skl_plane_stride_mult(fb, color_plane, rotation);
4556 }
4557
4558 static u32 skl_plane_ctl_format(u32 pixel_format)
4559 {
4560         switch (pixel_format) {
4561         case DRM_FORMAT_C8:
4562                 return PLANE_CTL_FORMAT_INDEXED;
4563         case DRM_FORMAT_RGB565:
4564                 return PLANE_CTL_FORMAT_RGB_565;
4565         case DRM_FORMAT_XBGR8888:
4566         case DRM_FORMAT_ABGR8888:
4567                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
4568         case DRM_FORMAT_XRGB8888:
4569         case DRM_FORMAT_ARGB8888:
4570                 return PLANE_CTL_FORMAT_XRGB_8888;
4571         case DRM_FORMAT_XBGR2101010:
4572         case DRM_FORMAT_ABGR2101010:
4573                 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
4574         case DRM_FORMAT_XRGB2101010:
4575         case DRM_FORMAT_ARGB2101010:
4576                 return PLANE_CTL_FORMAT_XRGB_2101010;
4577         case DRM_FORMAT_XBGR16161616F:
4578         case DRM_FORMAT_ABGR16161616F:
4579                 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
4580         case DRM_FORMAT_XRGB16161616F:
4581         case DRM_FORMAT_ARGB16161616F:
4582                 return PLANE_CTL_FORMAT_XRGB_16161616F;
4583         case DRM_FORMAT_YUYV:
4584                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
4585         case DRM_FORMAT_YVYU:
4586                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
4587         case DRM_FORMAT_UYVY:
4588                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
4589         case DRM_FORMAT_VYUY:
4590                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
4591         case DRM_FORMAT_NV12:
4592                 return PLANE_CTL_FORMAT_NV12;
4593         case DRM_FORMAT_P010:
4594                 return PLANE_CTL_FORMAT_P010;
4595         case DRM_FORMAT_P012:
4596                 return PLANE_CTL_FORMAT_P012;
4597         case DRM_FORMAT_P016:
4598                 return PLANE_CTL_FORMAT_P016;
4599         case DRM_FORMAT_Y210:
4600                 return PLANE_CTL_FORMAT_Y210;
4601         case DRM_FORMAT_Y212:
4602                 return PLANE_CTL_FORMAT_Y212;
4603         case DRM_FORMAT_Y216:
4604                 return PLANE_CTL_FORMAT_Y216;
4605         case DRM_FORMAT_XVYU2101010:
4606                 return PLANE_CTL_FORMAT_Y410;
4607         case DRM_FORMAT_XVYU12_16161616:
4608                 return PLANE_CTL_FORMAT_Y412;
4609         case DRM_FORMAT_XVYU16161616:
4610                 return PLANE_CTL_FORMAT_Y416;
4611         default:
4612                 MISSING_CASE(pixel_format);
4613         }
4614
4615         return 0;
4616 }
4617
4618 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
4619 {
4620         if (!plane_state->hw.fb->format->has_alpha)
4621                 return PLANE_CTL_ALPHA_DISABLE;
4622
4623         switch (plane_state->hw.pixel_blend_mode) {
4624         case DRM_MODE_BLEND_PIXEL_NONE:
4625                 return PLANE_CTL_ALPHA_DISABLE;
4626         case DRM_MODE_BLEND_PREMULTI:
4627                 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
4628         case DRM_MODE_BLEND_COVERAGE:
4629                 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
4630         default:
4631                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4632                 return PLANE_CTL_ALPHA_DISABLE;
4633         }
4634 }
4635
4636 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
4637 {
4638         if (!plane_state->hw.fb->format->has_alpha)
4639                 return PLANE_COLOR_ALPHA_DISABLE;
4640
4641         switch (plane_state->hw.pixel_blend_mode) {
4642         case DRM_MODE_BLEND_PIXEL_NONE:
4643                 return PLANE_COLOR_ALPHA_DISABLE;
4644         case DRM_MODE_BLEND_PREMULTI:
4645                 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
4646         case DRM_MODE_BLEND_COVERAGE:
4647                 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
4648         default:
4649                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
4650                 return PLANE_COLOR_ALPHA_DISABLE;
4651         }
4652 }
4653
4654 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
4655 {
4656         switch (fb_modifier) {
4657         case DRM_FORMAT_MOD_LINEAR:
4658                 break;
4659         case I915_FORMAT_MOD_X_TILED:
4660                 return PLANE_CTL_TILED_X;
4661         case I915_FORMAT_MOD_Y_TILED:
4662                 return PLANE_CTL_TILED_Y;
4663         case I915_FORMAT_MOD_Y_TILED_CCS:
4664                 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4665         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
4666                 return PLANE_CTL_TILED_Y |
4667                        PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
4668                        PLANE_CTL_CLEAR_COLOR_DISABLE;
4669         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
4670                 return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
4671         case I915_FORMAT_MOD_Yf_TILED:
4672                 return PLANE_CTL_TILED_YF;
4673         case I915_FORMAT_MOD_Yf_TILED_CCS:
4674                 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
4675         default:
4676                 MISSING_CASE(fb_modifier);
4677         }
4678
4679         return 0;
4680 }
4681
4682 static u32 skl_plane_ctl_rotate(unsigned int rotate)
4683 {
4684         switch (rotate) {
4685         case DRM_MODE_ROTATE_0:
4686                 break;
4687         /*
4688          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4689          * while i915 HW rotation is clockwise, thats why this swapping.
4690          */
4691         case DRM_MODE_ROTATE_90:
4692                 return PLANE_CTL_ROTATE_270;
4693         case DRM_MODE_ROTATE_180:
4694                 return PLANE_CTL_ROTATE_180;
4695         case DRM_MODE_ROTATE_270:
4696                 return PLANE_CTL_ROTATE_90;
4697         default:
4698                 MISSING_CASE(rotate);
4699         }
4700
4701         return 0;
4702 }
4703
4704 static u32 cnl_plane_ctl_flip(unsigned int reflect)
4705 {
4706         switch (reflect) {
4707         case 0:
4708                 break;
4709         case DRM_MODE_REFLECT_X:
4710                 return PLANE_CTL_FLIP_HORIZONTAL;
4711         case DRM_MODE_REFLECT_Y:
4712         default:
4713                 MISSING_CASE(reflect);
4714         }
4715
4716         return 0;
4717 }
4718
4719 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4720 {
4721         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4722         u32 plane_ctl = 0;
4723
4724         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4725                 return plane_ctl;
4726
4727         if (crtc_state->gamma_enable)
4728                 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
4729
4730         if (crtc_state->csc_enable)
4731                 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
4732
4733         return plane_ctl;
4734 }
4735
4736 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
4737                   const struct intel_plane_state *plane_state)
4738 {
4739         struct drm_i915_private *dev_priv =
4740                 to_i915(plane_state->uapi.plane->dev);
4741         const struct drm_framebuffer *fb = plane_state->hw.fb;
4742         unsigned int rotation = plane_state->hw.rotation;
4743         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
4744         u32 plane_ctl;
4745
4746         plane_ctl = PLANE_CTL_ENABLE;
4747
4748         if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
4749                 plane_ctl |= skl_plane_ctl_alpha(plane_state);
4750                 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
4751
4752                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4753                         plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
4754
4755                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4756                         plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
4757         }
4758
4759         plane_ctl |= skl_plane_ctl_format(fb->format->format);
4760         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
4761         plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
4762
4763         if (INTEL_GEN(dev_priv) >= 10)
4764                 plane_ctl |= cnl_plane_ctl_flip(rotation &
4765                                                 DRM_MODE_REFLECT_MASK);
4766
4767         if (key->flags & I915_SET_COLORKEY_DESTINATION)
4768                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
4769         else if (key->flags & I915_SET_COLORKEY_SOURCE)
4770                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
4771
4772         return plane_ctl;
4773 }
4774
4775 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
4776 {
4777         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4778         u32 plane_color_ctl = 0;
4779
4780         if (INTEL_GEN(dev_priv) >= 11)
4781                 return plane_color_ctl;
4782
4783         if (crtc_state->gamma_enable)
4784                 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
4785
4786         if (crtc_state->csc_enable)
4787                 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
4788
4789         return plane_color_ctl;
4790 }
4791
4792 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
4793                         const struct intel_plane_state *plane_state)
4794 {
4795         struct drm_i915_private *dev_priv =
4796                 to_i915(plane_state->uapi.plane->dev);
4797         const struct drm_framebuffer *fb = plane_state->hw.fb;
4798         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4799         u32 plane_color_ctl = 0;
4800
4801         plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
4802         plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
4803
4804         if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
4805                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4806                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
4807                 else
4808                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
4809
4810                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4811                         plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
4812         } else if (fb->format->is_yuv) {
4813                 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
4814         }
4815
4816         return plane_color_ctl;
4817 }
4818
4819 static int
4820 __intel_display_resume(struct drm_device *dev,
4821                        struct drm_atomic_state *state,
4822                        struct drm_modeset_acquire_ctx *ctx)
4823 {
4824         struct drm_crtc_state *crtc_state;
4825         struct drm_crtc *crtc;
4826         int i, ret;
4827
4828         intel_modeset_setup_hw_state(dev, ctx);
4829         intel_vga_redisable(to_i915(dev));
4830
4831         if (!state)
4832                 return 0;
4833
4834         /*
4835          * We've duplicated the state, pointers to the old state are invalid.
4836          *
4837          * Don't attempt to use the old state until we commit the duplicated state.
4838          */
4839         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
4840                 /*
4841                  * Force recalculation even if we restore
4842                  * current state. With fast modeset this may not result
4843                  * in a modeset when the state is compatible.
4844                  */
4845                 crtc_state->mode_changed = true;
4846         }
4847
4848         /* ignore any reset values/BIOS leftovers in the WM registers */
4849         if (!HAS_GMCH(to_i915(dev)))
4850                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
4851
4852         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4853
4854         drm_WARN_ON(dev, ret == -EDEADLK);
4855         return ret;
4856 }
4857
4858 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
4859 {
4860         return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
4861                 intel_has_gpu_reset(&dev_priv->gt));
4862 }
4863
4864 void intel_prepare_reset(struct drm_i915_private *dev_priv)
4865 {
4866         struct drm_device *dev = &dev_priv->drm;
4867         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4868         struct drm_atomic_state *state;
4869         int ret;
4870
4871         /* reset doesn't touch the display */
4872         if (!i915_modparams.force_reset_modeset_test &&
4873             !gpu_reset_clobbers_display(dev_priv))
4874                 return;
4875
4876         /* We have a modeset vs reset deadlock, defensively unbreak it. */
4877         set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4878         smp_mb__after_atomic();
4879         wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
4880
4881         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
4882                 drm_dbg_kms(&dev_priv->drm,
4883                             "Modeset potentially stuck, unbreaking through wedging\n");
4884                 intel_gt_set_wedged(&dev_priv->gt);
4885         }
4886
4887         /*
4888          * Need mode_config.mutex so that we don't
4889          * trample ongoing ->detect() and whatnot.
4890          */
4891         mutex_lock(&dev->mode_config.mutex);
4892         drm_modeset_acquire_init(ctx, 0);
4893         while (1) {
4894                 ret = drm_modeset_lock_all_ctx(dev, ctx);
4895                 if (ret != -EDEADLK)
4896                         break;
4897
4898                 drm_modeset_backoff(ctx);
4899         }
4900         /*
4901          * Disabling the crtcs gracefully seems nicer. Also the
4902          * g33 docs say we should at least disable all the planes.
4903          */
4904         state = drm_atomic_helper_duplicate_state(dev, ctx);
4905         if (IS_ERR(state)) {
4906                 ret = PTR_ERR(state);
4907                 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
4908                         ret);
4909                 return;
4910         }
4911
4912         ret = drm_atomic_helper_disable_all(dev, ctx);
4913         if (ret) {
4914                 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
4915                         ret);
4916                 drm_atomic_state_put(state);
4917                 return;
4918         }
4919
4920         dev_priv->modeset_restore_state = state;
4921         state->acquire_ctx = ctx;
4922 }
4923
4924 void intel_finish_reset(struct drm_i915_private *dev_priv)
4925 {
4926         struct drm_device *dev = &dev_priv->drm;
4927         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4928         struct drm_atomic_state *state;
4929         int ret;
4930
4931         /* reset doesn't touch the display */
4932         if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
4933                 return;
4934
4935         state = fetch_and_zero(&dev_priv->modeset_restore_state);
4936         if (!state)
4937                 goto unlock;
4938
4939         /* reset doesn't touch the display */
4940         if (!gpu_reset_clobbers_display(dev_priv)) {
4941                 /* for testing only restore the display */
4942                 ret = __intel_display_resume(dev, state, ctx);
4943                 if (ret)
4944                         drm_err(&dev_priv->drm,
4945                                 "Restoring old state failed with %i\n", ret);
4946         } else {
4947                 /*
4948                  * The display has been reset as well,
4949                  * so need a full re-initialization.
4950                  */
4951                 intel_pps_unlock_regs_wa(dev_priv);
4952                 intel_modeset_init_hw(dev_priv);
4953                 intel_init_clock_gating(dev_priv);
4954
4955                 spin_lock_irq(&dev_priv->irq_lock);
4956                 if (dev_priv->display.hpd_irq_setup)
4957                         dev_priv->display.hpd_irq_setup(dev_priv);
4958                 spin_unlock_irq(&dev_priv->irq_lock);
4959
4960                 ret = __intel_display_resume(dev, state, ctx);
4961                 if (ret)
4962                         drm_err(&dev_priv->drm,
4963                                 "Restoring old state failed with %i\n", ret);
4964
4965                 intel_hpd_init(dev_priv);
4966         }
4967
4968         drm_atomic_state_put(state);
4969 unlock:
4970         drm_modeset_drop_locks(ctx);
4971         drm_modeset_acquire_fini(ctx);
4972         mutex_unlock(&dev->mode_config.mutex);
4973
4974         clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4975 }
4976
4977 static void icl_set_pipe_chicken(struct intel_crtc *crtc)
4978 {
4979         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4980         enum pipe pipe = crtc->pipe;
4981         u32 tmp;
4982
4983         tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
4984
4985         /*
4986          * Display WA #1153: icl
4987          * enable hardware to bypass the alpha math
4988          * and rounding for per-pixel values 00 and 0xff
4989          */
4990         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
4991         /*
4992          * Display WA # 1605353570: icl
4993          * Set the pixel rounding bit to 1 for allowing
4994          * passthrough of Frame buffer pixels unmodified
4995          * across pipe
4996          */
4997         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
4998         intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
4999 }
5000
5001 static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state)
5002 {
5003         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5004         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5005         u32 trans_ddi_func_ctl2_val;
5006         u8 master_select;
5007
5008         /*
5009          * Configure the master select and enable Transcoder Port Sync for
5010          * Slave CRTCs transcoder.
5011          */
5012         if (crtc_state->master_transcoder == INVALID_TRANSCODER)
5013                 return;
5014
5015         if (crtc_state->master_transcoder == TRANSCODER_EDP)
5016                 master_select = 0;
5017         else
5018                 master_select = crtc_state->master_transcoder + 1;
5019
5020         /* Set the master select bits for Tranascoder Port Sync */
5021         trans_ddi_func_ctl2_val = (PORT_SYNC_MODE_MASTER_SELECT(master_select) &
5022                                    PORT_SYNC_MODE_MASTER_SELECT_MASK) <<
5023                 PORT_SYNC_MODE_MASTER_SELECT_SHIFT;
5024         /* Enable Transcoder Port Sync */
5025         trans_ddi_func_ctl2_val |= PORT_SYNC_MODE_ENABLE;
5026
5027         intel_de_write(dev_priv,
5028                        TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder),
5029                        trans_ddi_func_ctl2_val);
5030 }
5031
5032 static void intel_fdi_normal_train(struct intel_crtc *crtc)
5033 {
5034         struct drm_device *dev = crtc->base.dev;
5035         struct drm_i915_private *dev_priv = to_i915(dev);
5036         enum pipe pipe = crtc->pipe;
5037         i915_reg_t reg;
5038         u32 temp;
5039
5040         /* enable normal train */
5041         reg = FDI_TX_CTL(pipe);
5042         temp = intel_de_read(dev_priv, reg);
5043         if (IS_IVYBRIDGE(dev_priv)) {
5044                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
5045                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
5046         } else {
5047                 temp &= ~FDI_LINK_TRAIN_NONE;
5048                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
5049         }
5050         intel_de_write(dev_priv, reg, temp);
5051
5052         reg = FDI_RX_CTL(pipe);
5053         temp = intel_de_read(dev_priv, reg);
5054         if (HAS_PCH_CPT(dev_priv)) {
5055                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5056                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
5057         } else {
5058                 temp &= ~FDI_LINK_TRAIN_NONE;
5059                 temp |= FDI_LINK_TRAIN_NONE;
5060         }
5061         intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
5062
5063         /* wait one idle pattern time */
5064         intel_de_posting_read(dev_priv, reg);
5065         udelay(1000);
5066
5067         /* IVB wants error correction enabled */
5068         if (IS_IVYBRIDGE(dev_priv))
5069                 intel_de_write(dev_priv, reg,
5070                                intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
5071 }
5072
5073 /* The FDI link training functions for ILK/Ibexpeak. */
5074 static void ilk_fdi_link_train(struct intel_crtc *crtc,
5075                                const struct intel_crtc_state *crtc_state)
5076 {
5077         struct drm_device *dev = crtc->base.dev;
5078         struct drm_i915_private *dev_priv = to_i915(dev);
5079         enum pipe pipe = crtc->pipe;
5080         i915_reg_t reg;
5081         u32 temp, tries;
5082
5083         /* FDI needs bits from pipe first */
5084         assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder);
5085
5086         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5087            for train result */
5088         reg = FDI_RX_IMR(pipe);
5089         temp = intel_de_read(dev_priv, reg);
5090         temp &= ~FDI_RX_SYMBOL_LOCK;
5091         temp &= ~FDI_RX_BIT_LOCK;
5092         intel_de_write(dev_priv, reg, temp);
5093         intel_de_read(dev_priv, reg);
5094         udelay(150);
5095
5096         /* enable CPU FDI TX and PCH FDI RX */
5097         reg = FDI_TX_CTL(pipe);
5098         temp = intel_de_read(dev_priv, reg);
5099         temp &= ~FDI_DP_PORT_WIDTH_MASK;
5100         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5101         temp &= ~FDI_LINK_TRAIN_NONE;
5102         temp |= FDI_LINK_TRAIN_PATTERN_1;
5103         intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5104
5105         reg = FDI_RX_CTL(pipe);
5106         temp = intel_de_read(dev_priv, reg);
5107         temp &= ~FDI_LINK_TRAIN_NONE;
5108         temp |= FDI_LINK_TRAIN_PATTERN_1;
5109         intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5110
5111         intel_de_posting_read(dev_priv, reg);
5112         udelay(150);
5113
5114         /* Ironlake workaround, enable clock pointer after FDI enable*/
5115         intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5116                        FDI_RX_PHASE_SYNC_POINTER_OVR);
5117         intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5118                        FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN);
5119
5120         reg = FDI_RX_IIR(pipe);
5121         for (tries = 0; tries < 5; tries++) {
5122                 temp = intel_de_read(dev_priv, reg);
5123                 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5124
5125                 if ((temp & FDI_RX_BIT_LOCK)) {
5126                         drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n");
5127                         intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK);
5128                         break;
5129                 }
5130         }
5131         if (tries == 5)
5132                 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
5133
5134         /* Train 2 */
5135         reg = FDI_TX_CTL(pipe);
5136         temp = intel_de_read(dev_priv, reg);
5137         temp &= ~FDI_LINK_TRAIN_NONE;
5138         temp |= FDI_LINK_TRAIN_PATTERN_2;
5139         intel_de_write(dev_priv, reg, temp);
5140
5141         reg = FDI_RX_CTL(pipe);
5142         temp = intel_de_read(dev_priv, reg);
5143         temp &= ~FDI_LINK_TRAIN_NONE;
5144         temp |= FDI_LINK_TRAIN_PATTERN_2;
5145         intel_de_write(dev_priv, reg, temp);
5146
5147         intel_de_posting_read(dev_priv, reg);
5148         udelay(150);
5149
5150         reg = FDI_RX_IIR(pipe);
5151         for (tries = 0; tries < 5; tries++) {
5152                 temp = intel_de_read(dev_priv, reg);
5153                 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5154
5155                 if (temp & FDI_RX_SYMBOL_LOCK) {
5156                         intel_de_write(dev_priv, reg,
5157                                        temp | FDI_RX_SYMBOL_LOCK);
5158                         drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n");
5159                         break;
5160                 }
5161         }
5162         if (tries == 5)
5163                 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
5164
5165         drm_dbg_kms(&dev_priv->drm, "FDI train done\n");
5166
5167 }
5168
5169 static const int snb_b_fdi_train_param[] = {
5170         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
5171         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
5172         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
5173         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
5174 };
5175
5176 /* The FDI link training functions for SNB/Cougarpoint. */
5177 static void gen6_fdi_link_train(struct intel_crtc *crtc,
5178                                 const struct intel_crtc_state *crtc_state)
5179 {
5180         struct drm_device *dev = crtc->base.dev;
5181         struct drm_i915_private *dev_priv = to_i915(dev);
5182         enum pipe pipe = crtc->pipe;
5183         i915_reg_t reg;
5184         u32 temp, i, retry;
5185
5186         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5187            for train result */
5188         reg = FDI_RX_IMR(pipe);
5189         temp = intel_de_read(dev_priv, reg);
5190         temp &= ~FDI_RX_SYMBOL_LOCK;
5191         temp &= ~FDI_RX_BIT_LOCK;
5192         intel_de_write(dev_priv, reg, temp);
5193
5194         intel_de_posting_read(dev_priv, reg);
5195         udelay(150);
5196
5197         /* enable CPU FDI TX and PCH FDI RX */
5198         reg = FDI_TX_CTL(pipe);
5199         temp = intel_de_read(dev_priv, reg);
5200         temp &= ~FDI_DP_PORT_WIDTH_MASK;
5201         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5202         temp &= ~FDI_LINK_TRAIN_NONE;
5203         temp |= FDI_LINK_TRAIN_PATTERN_1;
5204         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5205         /* SNB-B */
5206         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5207         intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5208
5209         intel_de_write(dev_priv, FDI_RX_MISC(pipe),
5210                        FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
5211
5212         reg = FDI_RX_CTL(pipe);
5213         temp = intel_de_read(dev_priv, reg);
5214         if (HAS_PCH_CPT(dev_priv)) {
5215                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5216                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5217         } else {
5218                 temp &= ~FDI_LINK_TRAIN_NONE;
5219                 temp |= FDI_LINK_TRAIN_PATTERN_1;
5220         }
5221         intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5222
5223         intel_de_posting_read(dev_priv, reg);
5224         udelay(150);
5225
5226         for (i = 0; i < 4; i++) {
5227                 reg = FDI_TX_CTL(pipe);
5228                 temp = intel_de_read(dev_priv, reg);
5229                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5230                 temp |= snb_b_fdi_train_param[i];
5231                 intel_de_write(dev_priv, reg, temp);
5232
5233                 intel_de_posting_read(dev_priv, reg);
5234                 udelay(500);
5235
5236                 for (retry = 0; retry < 5; retry++) {
5237                         reg = FDI_RX_IIR(pipe);
5238                         temp = intel_de_read(dev_priv, reg);
5239                         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5240                         if (temp & FDI_RX_BIT_LOCK) {
5241                                 intel_de_write(dev_priv, reg,
5242                                                temp | FDI_RX_BIT_LOCK);
5243                                 drm_dbg_kms(&dev_priv->drm,
5244                                             "FDI train 1 done.\n");
5245                                 break;
5246                         }
5247                         udelay(50);
5248                 }
5249                 if (retry < 5)
5250                         break;
5251         }
5252         if (i == 4)
5253                 drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
5254
5255         /* Train 2 */
5256         reg = FDI_TX_CTL(pipe);
5257         temp = intel_de_read(dev_priv, reg);
5258         temp &= ~FDI_LINK_TRAIN_NONE;
5259         temp |= FDI_LINK_TRAIN_PATTERN_2;
5260         if (IS_GEN(dev_priv, 6)) {
5261                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5262                 /* SNB-B */
5263                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5264         }
5265         intel_de_write(dev_priv, reg, temp);
5266
5267         reg = FDI_RX_CTL(pipe);
5268         temp = intel_de_read(dev_priv, reg);
5269         if (HAS_PCH_CPT(dev_priv)) {
5270                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5271                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
5272         } else {
5273                 temp &= ~FDI_LINK_TRAIN_NONE;
5274                 temp |= FDI_LINK_TRAIN_PATTERN_2;
5275         }
5276         intel_de_write(dev_priv, reg, temp);
5277
5278         intel_de_posting_read(dev_priv, reg);
5279         udelay(150);
5280
5281         for (i = 0; i < 4; i++) {
5282                 reg = FDI_TX_CTL(pipe);
5283                 temp = intel_de_read(dev_priv, reg);
5284                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5285                 temp |= snb_b_fdi_train_param[i];
5286                 intel_de_write(dev_priv, reg, temp);
5287
5288                 intel_de_posting_read(dev_priv, reg);
5289                 udelay(500);
5290
5291                 for (retry = 0; retry < 5; retry++) {
5292                         reg = FDI_RX_IIR(pipe);
5293                         temp = intel_de_read(dev_priv, reg);
5294                         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5295                         if (temp & FDI_RX_SYMBOL_LOCK) {
5296                                 intel_de_write(dev_priv, reg,
5297                                                temp | FDI_RX_SYMBOL_LOCK);
5298                                 drm_dbg_kms(&dev_priv->drm,
5299                                             "FDI train 2 done.\n");
5300                                 break;
5301                         }
5302                         udelay(50);
5303                 }
5304                 if (retry < 5)
5305                         break;
5306         }
5307         if (i == 4)
5308                 drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
5309
5310         drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
5311 }
5312
5313 /* Manual link training for Ivy Bridge A0 parts */
5314 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
5315                                       const struct intel_crtc_state *crtc_state)
5316 {
5317         struct drm_device *dev = crtc->base.dev;
5318         struct drm_i915_private *dev_priv = to_i915(dev);
5319         enum pipe pipe = crtc->pipe;
5320         i915_reg_t reg;
5321         u32 temp, i, j;
5322
5323         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5324            for train result */
5325         reg = FDI_RX_IMR(pipe);
5326         temp = intel_de_read(dev_priv, reg);
5327         temp &= ~FDI_RX_SYMBOL_LOCK;
5328         temp &= ~FDI_RX_BIT_LOCK;
5329         intel_de_write(dev_priv, reg, temp);
5330
5331         intel_de_posting_read(dev_priv, reg);
5332         udelay(150);
5333
5334         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n",
5335                     intel_de_read(dev_priv, FDI_RX_IIR(pipe)));
5336
5337         /* Try each vswing and preemphasis setting twice before moving on */
5338         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
5339                 /* disable first in case we need to retry */
5340                 reg = FDI_TX_CTL(pipe);
5341                 temp = intel_de_read(dev_priv, reg);
5342                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
5343                 temp &= ~FDI_TX_ENABLE;
5344                 intel_de_write(dev_priv, reg, temp);
5345
5346                 reg = FDI_RX_CTL(pipe);
5347                 temp = intel_de_read(dev_priv, reg);
5348                 temp &= ~FDI_LINK_TRAIN_AUTO;
5349                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5350                 temp &= ~FDI_RX_ENABLE;
5351                 intel_de_write(dev_priv, reg, temp);
5352
5353                 /* enable CPU FDI TX and PCH FDI RX */
5354                 reg = FDI_TX_CTL(pipe);
5355                 temp = intel_de_read(dev_priv, reg);
5356                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
5357                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5358                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
5359                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
5360                 temp |= snb_b_fdi_train_param[j/2];
5361                 temp |= FDI_COMPOSITE_SYNC;
5362                 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
5363
5364                 intel_de_write(dev_priv, FDI_RX_MISC(pipe),
5365                                FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
5366
5367                 reg = FDI_RX_CTL(pipe);
5368                 temp = intel_de_read(dev_priv, reg);
5369                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5370                 temp |= FDI_COMPOSITE_SYNC;
5371                 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
5372
5373                 intel_de_posting_read(dev_priv, reg);
5374                 udelay(1); /* should be 0.5us */
5375
5376                 for (i = 0; i < 4; i++) {
5377                         reg = FDI_RX_IIR(pipe);
5378                         temp = intel_de_read(dev_priv, reg);
5379                         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5380
5381                         if (temp & FDI_RX_BIT_LOCK ||
5382                             (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) {
5383                                 intel_de_write(dev_priv, reg,
5384                                                temp | FDI_RX_BIT_LOCK);
5385                                 drm_dbg_kms(&dev_priv->drm,
5386                                             "FDI train 1 done, level %i.\n",
5387                                             i);
5388                                 break;
5389                         }
5390                         udelay(1); /* should be 0.5us */
5391                 }
5392                 if (i == 4) {
5393                         drm_dbg_kms(&dev_priv->drm,
5394                                     "FDI train 1 fail on vswing %d\n", j / 2);
5395                         continue;
5396                 }
5397
5398                 /* Train 2 */
5399                 reg = FDI_TX_CTL(pipe);
5400                 temp = intel_de_read(dev_priv, reg);
5401                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
5402                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
5403                 intel_de_write(dev_priv, reg, temp);
5404
5405                 reg = FDI_RX_CTL(pipe);
5406                 temp = intel_de_read(dev_priv, reg);
5407                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5408                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
5409                 intel_de_write(dev_priv, reg, temp);
5410
5411                 intel_de_posting_read(dev_priv, reg);
5412                 udelay(2); /* should be 1.5us */
5413
5414                 for (i = 0; i < 4; i++) {
5415                         reg = FDI_RX_IIR(pipe);
5416                         temp = intel_de_read(dev_priv, reg);
5417                         drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
5418
5419                         if (temp & FDI_RX_SYMBOL_LOCK ||
5420                             (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) {
5421                                 intel_de_write(dev_priv, reg,
5422                                                temp | FDI_RX_SYMBOL_LOCK);
5423                                 drm_dbg_kms(&dev_priv->drm,
5424                                             "FDI train 2 done, level %i.\n",
5425                                             i);
5426                                 goto train_done;
5427                         }
5428                         udelay(2); /* should be 1.5us */
5429                 }
5430                 if (i == 4)
5431                         drm_dbg_kms(&dev_priv->drm,
5432                                     "FDI train 2 fail on vswing %d\n", j / 2);
5433         }
5434
5435 train_done:
5436         drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
5437 }
5438
5439 static void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
5440 {
5441         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
5442         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5443         enum pipe pipe = intel_crtc->pipe;
5444         i915_reg_t reg;
5445         u32 temp;
5446
5447         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5448         reg = FDI_RX_CTL(pipe);
5449         temp = intel_de_read(dev_priv, reg);
5450         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
5451         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
5452         temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5453         intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE);
5454
5455         intel_de_posting_read(dev_priv, reg);
5456         udelay(200);
5457
5458         /* Switch from Rawclk to PCDclk */
5459         temp = intel_de_read(dev_priv, reg);
5460         intel_de_write(dev_priv, reg, temp | FDI_PCDCLK);
5461
5462         intel_de_posting_read(dev_priv, reg);
5463         udelay(200);
5464
5465         /* Enable CPU FDI TX PLL, always on for Ironlake */
5466         reg = FDI_TX_CTL(pipe);
5467         temp = intel_de_read(dev_priv, reg);
5468         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5469                 intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE);
5470
5471                 intel_de_posting_read(dev_priv, reg);
5472                 udelay(100);
5473         }
5474 }
5475
5476 static void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc)
5477 {
5478         struct drm_device *dev = intel_crtc->base.dev;
5479         struct drm_i915_private *dev_priv = to_i915(dev);
5480         enum pipe pipe = intel_crtc->pipe;
5481         i915_reg_t reg;
5482         u32 temp;
5483
5484         /* Switch from PCDclk to Rawclk */
5485         reg = FDI_RX_CTL(pipe);
5486         temp = intel_de_read(dev_priv, reg);
5487         intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK);
5488
5489         /* Disable CPU FDI TX PLL */
5490         reg = FDI_TX_CTL(pipe);
5491         temp = intel_de_read(dev_priv, reg);
5492         intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE);
5493
5494         intel_de_posting_read(dev_priv, reg);
5495         udelay(100);
5496
5497         reg = FDI_RX_CTL(pipe);
5498         temp = intel_de_read(dev_priv, reg);
5499         intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE);
5500
5501         /* Wait for the clocks to turn off. */
5502         intel_de_posting_read(dev_priv, reg);
5503         udelay(100);
5504 }
5505
5506 static void ilk_fdi_disable(struct intel_crtc *crtc)
5507 {
5508         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5509         enum pipe pipe = crtc->pipe;
5510         i915_reg_t reg;
5511         u32 temp;
5512
5513         /* disable CPU FDI tx and PCH FDI rx */
5514         reg = FDI_TX_CTL(pipe);
5515         temp = intel_de_read(dev_priv, reg);
5516         intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE);
5517         intel_de_posting_read(dev_priv, reg);
5518
5519         reg = FDI_RX_CTL(pipe);
5520         temp = intel_de_read(dev_priv, reg);
5521         temp &= ~(0x7 << 16);
5522         temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5523         intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE);
5524
5525         intel_de_posting_read(dev_priv, reg);
5526         udelay(100);
5527
5528         /* Ironlake workaround, disable clock pointer after downing FDI */
5529         if (HAS_PCH_IBX(dev_priv))
5530                 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
5531                                FDI_RX_PHASE_SYNC_POINTER_OVR);
5532
5533         /* still set train pattern 1 */
5534         reg = FDI_TX_CTL(pipe);
5535         temp = intel_de_read(dev_priv, reg);
5536         temp &= ~FDI_LINK_TRAIN_NONE;
5537         temp |= FDI_LINK_TRAIN_PATTERN_1;
5538         intel_de_write(dev_priv, reg, temp);
5539
5540         reg = FDI_RX_CTL(pipe);
5541         temp = intel_de_read(dev_priv, reg);
5542         if (HAS_PCH_CPT(dev_priv)) {
5543                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
5544                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
5545         } else {
5546                 temp &= ~FDI_LINK_TRAIN_NONE;
5547                 temp |= FDI_LINK_TRAIN_PATTERN_1;
5548         }
5549         /* BPC in FDI rx is consistent with that in PIPECONF */
5550         temp &= ~(0x07 << 16);
5551         temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5552         intel_de_write(dev_priv, reg, temp);
5553
5554         intel_de_posting_read(dev_priv, reg);
5555         udelay(100);
5556 }
5557
5558 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
5559 {
5560         struct drm_crtc *crtc;
5561         bool cleanup_done;
5562
5563         drm_for_each_crtc(crtc, &dev_priv->drm) {
5564                 struct drm_crtc_commit *commit;
5565                 spin_lock(&crtc->commit_lock);
5566                 commit = list_first_entry_or_null(&crtc->commit_list,
5567                                                   struct drm_crtc_commit, commit_entry);
5568                 cleanup_done = commit ?
5569                         try_wait_for_completion(&commit->cleanup_done) : true;
5570                 spin_unlock(&crtc->commit_lock);
5571
5572                 if (cleanup_done)
5573                         continue;
5574
5575                 drm_crtc_wait_one_vblank(crtc);
5576
5577                 return true;
5578         }
5579
5580         return false;
5581 }
5582
5583 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
5584 {
5585         u32 temp;
5586
5587         intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
5588
5589         mutex_lock(&dev_priv->sb_lock);
5590
5591         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5592         temp |= SBI_SSCCTL_DISABLE;
5593         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5594
5595         mutex_unlock(&dev_priv->sb_lock);
5596 }
5597
5598 /* Program iCLKIP clock to the desired frequency */
5599 static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
5600 {
5601         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5602         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5603         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
5604         u32 divsel, phaseinc, auxdiv, phasedir = 0;
5605         u32 temp;
5606
5607         lpt_disable_iclkip(dev_priv);
5608
5609         /* The iCLK virtual clock root frequency is in MHz,
5610          * but the adjusted_mode->crtc_clock in in KHz. To get the
5611          * divisors, it is necessary to divide one by another, so we
5612          * convert the virtual clock precision to KHz here for higher
5613          * precision.
5614          */
5615         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
5616                 u32 iclk_virtual_root_freq = 172800 * 1000;
5617                 u32 iclk_pi_range = 64;
5618                 u32 desired_divisor;
5619
5620                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5621                                                     clock << auxdiv);
5622                 divsel = (desired_divisor / iclk_pi_range) - 2;
5623                 phaseinc = desired_divisor % iclk_pi_range;
5624
5625                 /*
5626                  * Near 20MHz is a corner case which is
5627                  * out of range for the 7-bit divisor
5628                  */
5629                 if (divsel <= 0x7f)
5630                         break;
5631         }
5632
5633         /* This should not happen with any sane values */
5634         drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
5635                     ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
5636         drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
5637                     ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
5638
5639         drm_dbg_kms(&dev_priv->drm,
5640                     "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
5641                     clock, auxdiv, divsel, phasedir, phaseinc);
5642
5643         mutex_lock(&dev_priv->sb_lock);
5644
5645         /* Program SSCDIVINTPHASE6 */
5646         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5647         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
5648         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
5649         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
5650         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
5651         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
5652         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
5653         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
5654
5655         /* Program SSCAUXDIV */
5656         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5657         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
5658         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
5659         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
5660
5661         /* Enable modulator and associated divider */
5662         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5663         temp &= ~SBI_SSCCTL_DISABLE;
5664         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
5665
5666         mutex_unlock(&dev_priv->sb_lock);
5667
5668         /* Wait for initialization time */
5669         udelay(24);
5670
5671         intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
5672 }
5673
5674 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
5675 {
5676         u32 divsel, phaseinc, auxdiv;
5677         u32 iclk_virtual_root_freq = 172800 * 1000;
5678         u32 iclk_pi_range = 64;
5679         u32 desired_divisor;
5680         u32 temp;
5681
5682         if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
5683                 return 0;
5684
5685         mutex_lock(&dev_priv->sb_lock);
5686
5687         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
5688         if (temp & SBI_SSCCTL_DISABLE) {
5689                 mutex_unlock(&dev_priv->sb_lock);
5690                 return 0;
5691         }
5692
5693         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
5694         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
5695                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
5696         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
5697                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
5698
5699         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
5700         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
5701                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
5702
5703         mutex_unlock(&dev_priv->sb_lock);
5704
5705         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
5706
5707         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
5708                                  desired_divisor << auxdiv);
5709 }
5710
5711 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
5712                                            enum pipe pch_transcoder)
5713 {
5714         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5715         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5716         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5717
5718         intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
5719                        intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
5720         intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
5721                        intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
5722         intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
5723                        intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
5724
5725         intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
5726                        intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
5727         intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
5728                        intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
5729         intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
5730                        intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
5731         intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
5732                        intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
5733 }
5734
5735 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
5736 {
5737         u32 temp;
5738
5739         temp = intel_de_read(dev_priv, SOUTH_CHICKEN1);
5740         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
5741                 return;
5742
5743         drm_WARN_ON(&dev_priv->drm,
5744                     intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) &
5745                     FDI_RX_ENABLE);
5746         drm_WARN_ON(&dev_priv->drm,
5747                     intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) &
5748                     FDI_RX_ENABLE);
5749
5750         temp &= ~FDI_BC_BIFURCATION_SELECT;
5751         if (enable)
5752                 temp |= FDI_BC_BIFURCATION_SELECT;
5753
5754         drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n",
5755                     enable ? "en" : "dis");
5756         intel_de_write(dev_priv, SOUTH_CHICKEN1, temp);
5757         intel_de_posting_read(dev_priv, SOUTH_CHICKEN1);
5758 }
5759
5760 static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state)
5761 {
5762         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5763         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5764
5765         switch (crtc->pipe) {
5766         case PIPE_A:
5767                 break;
5768         case PIPE_B:
5769                 if (crtc_state->fdi_lanes > 2)
5770                         cpt_set_fdi_bc_bifurcation(dev_priv, false);
5771                 else
5772                         cpt_set_fdi_bc_bifurcation(dev_priv, true);
5773
5774                 break;
5775         case PIPE_C:
5776                 cpt_set_fdi_bc_bifurcation(dev_priv, true);
5777
5778                 break;
5779         default:
5780                 BUG();
5781         }
5782 }
5783
5784 /*
5785  * Finds the encoder associated with the given CRTC. This can only be
5786  * used when we know that the CRTC isn't feeding multiple encoders!
5787  */
5788 static struct intel_encoder *
5789 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
5790                            const struct intel_crtc_state *crtc_state)
5791 {
5792         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5793         const struct drm_connector_state *connector_state;
5794         const struct drm_connector *connector;
5795         struct intel_encoder *encoder = NULL;
5796         int num_encoders = 0;
5797         int i;
5798
5799         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5800                 if (connector_state->crtc != &crtc->base)
5801                         continue;
5802
5803                 encoder = to_intel_encoder(connector_state->best_encoder);
5804                 num_encoders++;
5805         }
5806
5807         drm_WARN(encoder->base.dev, num_encoders != 1,
5808                  "%d encoders for pipe %c\n",
5809                  num_encoders, pipe_name(crtc->pipe));
5810
5811         return encoder;
5812 }
5813
5814 /*
5815  * Enable PCH resources required for PCH ports:
5816  *   - PCH PLLs
5817  *   - FDI training & RX/TX
5818  *   - update transcoder timings
5819  *   - DP transcoding bits
5820  *   - transcoder
5821  */
5822 static void ilk_pch_enable(const struct intel_atomic_state *state,
5823                            const struct intel_crtc_state *crtc_state)
5824 {
5825         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5826         struct drm_device *dev = crtc->base.dev;
5827         struct drm_i915_private *dev_priv = to_i915(dev);
5828         enum pipe pipe = crtc->pipe;
5829         u32 temp;
5830
5831         assert_pch_transcoder_disabled(dev_priv, pipe);
5832
5833         if (IS_IVYBRIDGE(dev_priv))
5834                 ivb_update_fdi_bc_bifurcation(crtc_state);
5835
5836         /* Write the TU size bits before fdi link training, so that error
5837          * detection works. */
5838         intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
5839                        intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
5840
5841         /* For PCH output, training FDI link */
5842         dev_priv->display.fdi_link_train(crtc, crtc_state);
5843
5844         /* We need to program the right clock selection before writing the pixel
5845          * mutliplier into the DPLL. */
5846         if (HAS_PCH_CPT(dev_priv)) {
5847                 u32 sel;
5848
5849                 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
5850                 temp |= TRANS_DPLL_ENABLE(pipe);
5851                 sel = TRANS_DPLLB_SEL(pipe);
5852                 if (crtc_state->shared_dpll ==
5853                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
5854                         temp |= sel;
5855                 else
5856                         temp &= ~sel;
5857                 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
5858         }
5859
5860         /* XXX: pch pll's can be enabled any time before we enable the PCH
5861          * transcoder, and we actually should do this to not upset any PCH
5862          * transcoder that already use the clock when we share it.
5863          *
5864          * Note that enable_shared_dpll tries to do the right thing, but
5865          * get_shared_dpll unconditionally resets the pll - we need that to have
5866          * the right LVDS enable sequence. */
5867         intel_enable_shared_dpll(crtc_state);
5868
5869         /* set transcoder timing, panel must allow it */
5870         assert_panel_unlocked(dev_priv, pipe);
5871         ilk_pch_transcoder_set_timings(crtc_state, pipe);
5872
5873         intel_fdi_normal_train(crtc);
5874
5875         /* For PCH DP, enable TRANS_DP_CTL */
5876         if (HAS_PCH_CPT(dev_priv) &&
5877             intel_crtc_has_dp_encoder(crtc_state)) {
5878                 const struct drm_display_mode *adjusted_mode =
5879                         &crtc_state->hw.adjusted_mode;
5880                 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5881                 i915_reg_t reg = TRANS_DP_CTL(pipe);
5882                 enum port port;
5883
5884                 temp = intel_de_read(dev_priv, reg);
5885                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
5886                           TRANS_DP_SYNC_MASK |
5887                           TRANS_DP_BPC_MASK);
5888                 temp |= TRANS_DP_OUTPUT_ENABLE;
5889                 temp |= bpc << 9; /* same format but at 11:9 */
5890
5891                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5892                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
5893                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5894                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
5895
5896                 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
5897                 drm_WARN_ON(dev, port < PORT_B || port > PORT_D);
5898                 temp |= TRANS_DP_PORT_SEL(port);
5899
5900                 intel_de_write(dev_priv, reg, temp);
5901         }
5902
5903         ilk_enable_pch_transcoder(crtc_state);
5904 }
5905
5906 void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
5907 {
5908         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5909         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5910         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
5911
5912         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
5913
5914         lpt_program_iclkip(crtc_state);
5915
5916         /* Set transcoder timing. */
5917         ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
5918
5919         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
5920 }
5921
5922 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
5923                                enum pipe pipe)
5924 {
5925         i915_reg_t dslreg = PIPEDSL(pipe);
5926         u32 temp;
5927
5928         temp = intel_de_read(dev_priv, dslreg);
5929         udelay(500);
5930         if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
5931                 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
5932                         drm_err(&dev_priv->drm,
5933                                 "mode set failed: pipe %c stuck\n",
5934                                 pipe_name(pipe));
5935         }
5936 }
5937
5938 /*
5939  * The hardware phase 0.0 refers to the center of the pixel.
5940  * We want to start from the top/left edge which is phase
5941  * -0.5. That matches how the hardware calculates the scaling
5942  * factors (from top-left of the first pixel to bottom-right
5943  * of the last pixel, as opposed to the pixel centers).
5944  *
5945  * For 4:2:0 subsampled chroma planes we obviously have to
5946  * adjust that so that the chroma sample position lands in
5947  * the right spot.
5948  *
5949  * Note that for packed YCbCr 4:2:2 formats there is no way to
5950  * control chroma siting. The hardware simply replicates the
5951  * chroma samples for both of the luma samples, and thus we don't
5952  * actually get the expected MPEG2 chroma siting convention :(
5953  * The same behaviour is observed on pre-SKL platforms as well.
5954  *
5955  * Theory behind the formula (note that we ignore sub-pixel
5956  * source coordinates):
5957  * s = source sample position
5958  * d = destination sample position
5959  *
5960  * Downscaling 4:1:
5961  * -0.5
5962  * | 0.0
5963  * | |     1.5 (initial phase)
5964  * | |     |
5965  * v v     v
5966  * | s | s | s | s |
5967  * |       d       |
5968  *
5969  * Upscaling 1:4:
5970  * -0.5
5971  * | -0.375 (initial phase)
5972  * | |     0.0
5973  * | |     |
5974  * v v     v
5975  * |       s       |
5976  * | d | d | d | d |
5977  */
5978 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
5979 {
5980         int phase = -0x8000;
5981         u16 trip = 0;
5982
5983         if (chroma_cosited)
5984                 phase += (sub - 1) * 0x8000 / sub;
5985
5986         phase += scale / (2 * sub);
5987
5988         /*
5989          * Hardware initial phase limited to [-0.5:1.5].
5990          * Since the max hardware scale factor is 3.0, we
5991          * should never actually excdeed 1.0 here.
5992          */
5993         WARN_ON(phase < -0x8000 || phase > 0x18000);
5994
5995         if (phase < 0)
5996                 phase = 0x10000 + phase;
5997         else
5998                 trip = PS_PHASE_TRIP;
5999
6000         return ((phase >> 2) & PS_PHASE_MASK) | trip;
6001 }
6002
6003 #define SKL_MIN_SRC_W 8
6004 #define SKL_MAX_SRC_W 4096
6005 #define SKL_MIN_SRC_H 8
6006 #define SKL_MAX_SRC_H 4096
6007 #define SKL_MIN_DST_W 8
6008 #define SKL_MAX_DST_W 4096
6009 #define SKL_MIN_DST_H 8
6010 #define SKL_MAX_DST_H 4096
6011 #define ICL_MAX_SRC_W 5120
6012 #define ICL_MAX_SRC_H 4096
6013 #define ICL_MAX_DST_W 5120
6014 #define ICL_MAX_DST_H 4096
6015 #define SKL_MIN_YUV_420_SRC_W 16
6016 #define SKL_MIN_YUV_420_SRC_H 16
6017
6018 static int
6019 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
6020                   unsigned int scaler_user, int *scaler_id,
6021                   int src_w, int src_h, int dst_w, int dst_h,
6022                   const struct drm_format_info *format,
6023                   u64 modifier, bool need_scaler)
6024 {
6025         struct intel_crtc_scaler_state *scaler_state =
6026                 &crtc_state->scaler_state;
6027         struct intel_crtc *intel_crtc =
6028                 to_intel_crtc(crtc_state->uapi.crtc);
6029         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6030         const struct drm_display_mode *adjusted_mode =
6031                 &crtc_state->hw.adjusted_mode;
6032
6033         /*
6034          * Src coordinates are already rotated by 270 degrees for
6035          * the 90/270 degree plane rotation cases (to match the
6036          * GTT mapping), hence no need to account for rotation here.
6037          */
6038         if (src_w != dst_w || src_h != dst_h)
6039                 need_scaler = true;
6040
6041         /*
6042          * Scaling/fitting not supported in IF-ID mode in GEN9+
6043          * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
6044          * Once NV12 is enabled, handle it here while allocating scaler
6045          * for NV12.
6046          */
6047         if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable &&
6048             need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6049                 drm_dbg_kms(&dev_priv->drm,
6050                             "Pipe/Plane scaling not supported with IF-ID mode\n");
6051                 return -EINVAL;
6052         }
6053
6054         /*
6055          * if plane is being disabled or scaler is no more required or force detach
6056          *  - free scaler binded to this plane/crtc
6057          *  - in order to do this, update crtc->scaler_usage
6058          *
6059          * Here scaler state in crtc_state is set free so that
6060          * scaler can be assigned to other user. Actual register
6061          * update to free the scaler is done in plane/panel-fit programming.
6062          * For this purpose crtc/plane_state->scaler_id isn't reset here.
6063          */
6064         if (force_detach || !need_scaler) {
6065                 if (*scaler_id >= 0) {
6066                         scaler_state->scaler_users &= ~(1 << scaler_user);
6067                         scaler_state->scalers[*scaler_id].in_use = 0;
6068
6069                         drm_dbg_kms(&dev_priv->drm,
6070                                     "scaler_user index %u.%u: "
6071                                     "Staged freeing scaler id %d scaler_users = 0x%x\n",
6072                                     intel_crtc->pipe, scaler_user, *scaler_id,
6073                                     scaler_state->scaler_users);
6074                         *scaler_id = -1;
6075                 }
6076                 return 0;
6077         }
6078
6079         if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
6080             (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
6081                 drm_dbg_kms(&dev_priv->drm,
6082                             "Planar YUV: src dimensions not met\n");
6083                 return -EINVAL;
6084         }
6085
6086         /* range checks */
6087         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
6088             dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
6089             (INTEL_GEN(dev_priv) >= 11 &&
6090              (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
6091               dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
6092             (INTEL_GEN(dev_priv) < 11 &&
6093              (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
6094               dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
6095                 drm_dbg_kms(&dev_priv->drm,
6096                             "scaler_user index %u.%u: src %ux%u dst %ux%u "
6097                             "size is out of scaler range\n",
6098                             intel_crtc->pipe, scaler_user, src_w, src_h,
6099                             dst_w, dst_h);
6100                 return -EINVAL;
6101         }
6102
6103         /* mark this plane as a scaler user in crtc_state */
6104         scaler_state->scaler_users |= (1 << scaler_user);
6105         drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
6106                     "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
6107                     intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
6108                     scaler_state->scaler_users);
6109
6110         return 0;
6111 }
6112
6113 /**
6114  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
6115  *
6116  * @state: crtc's scaler state
6117  *
6118  * Return
6119  *     0 - scaler_usage updated successfully
6120  *    error - requested scaling cannot be supported or other error condition
6121  */
6122 int skl_update_scaler_crtc(struct intel_crtc_state *state)
6123 {
6124         const struct drm_display_mode *adjusted_mode = &state->hw.adjusted_mode;
6125         bool need_scaler = false;
6126
6127         if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
6128             state->pch_pfit.enabled)
6129                 need_scaler = true;
6130
6131         return skl_update_scaler(state, !state->hw.active, SKL_CRTC_INDEX,
6132                                  &state->scaler_state.scaler_id,
6133                                  state->pipe_src_w, state->pipe_src_h,
6134                                  adjusted_mode->crtc_hdisplay,
6135                                  adjusted_mode->crtc_vdisplay, NULL, 0,
6136                                  need_scaler);
6137 }
6138
6139 /**
6140  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
6141  * @crtc_state: crtc's scaler state
6142  * @plane_state: atomic plane state to update
6143  *
6144  * Return
6145  *     0 - scaler_usage updated successfully
6146  *    error - requested scaling cannot be supported or other error condition
6147  */
6148 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
6149                                    struct intel_plane_state *plane_state)
6150 {
6151         struct intel_plane *intel_plane =
6152                 to_intel_plane(plane_state->uapi.plane);
6153         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
6154         struct drm_framebuffer *fb = plane_state->hw.fb;
6155         int ret;
6156         bool force_detach = !fb || !plane_state->uapi.visible;
6157         bool need_scaler = false;
6158
6159         /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
6160         if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
6161             fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
6162                 need_scaler = true;
6163
6164         ret = skl_update_scaler(crtc_state, force_detach,
6165                                 drm_plane_index(&intel_plane->base),
6166                                 &plane_state->scaler_id,
6167                                 drm_rect_width(&plane_state->uapi.src) >> 16,
6168                                 drm_rect_height(&plane_state->uapi.src) >> 16,
6169                                 drm_rect_width(&plane_state->uapi.dst),
6170                                 drm_rect_height(&plane_state->uapi.dst),
6171                                 fb ? fb->format : NULL,
6172                                 fb ? fb->modifier : 0,
6173                                 need_scaler);
6174
6175         if (ret || plane_state->scaler_id < 0)
6176                 return ret;
6177
6178         /* check colorkey */
6179         if (plane_state->ckey.flags) {
6180                 drm_dbg_kms(&dev_priv->drm,
6181                             "[PLANE:%d:%s] scaling with color key not allowed",
6182                             intel_plane->base.base.id,
6183                             intel_plane->base.name);
6184                 return -EINVAL;
6185         }
6186
6187         /* Check src format */
6188         switch (fb->format->format) {
6189         case DRM_FORMAT_RGB565:
6190         case DRM_FORMAT_XBGR8888:
6191         case DRM_FORMAT_XRGB8888:
6192         case DRM_FORMAT_ABGR8888:
6193         case DRM_FORMAT_ARGB8888:
6194         case DRM_FORMAT_XRGB2101010:
6195         case DRM_FORMAT_XBGR2101010:
6196         case DRM_FORMAT_ARGB2101010:
6197         case DRM_FORMAT_ABGR2101010:
6198         case DRM_FORMAT_YUYV:
6199         case DRM_FORMAT_YVYU:
6200         case DRM_FORMAT_UYVY:
6201         case DRM_FORMAT_VYUY:
6202         case DRM_FORMAT_NV12:
6203         case DRM_FORMAT_P010:
6204         case DRM_FORMAT_P012:
6205         case DRM_FORMAT_P016:
6206         case DRM_FORMAT_Y210:
6207         case DRM_FORMAT_Y212:
6208         case DRM_FORMAT_Y216:
6209         case DRM_FORMAT_XVYU2101010:
6210         case DRM_FORMAT_XVYU12_16161616:
6211         case DRM_FORMAT_XVYU16161616:
6212                 break;
6213         case DRM_FORMAT_XBGR16161616F:
6214         case DRM_FORMAT_ABGR16161616F:
6215         case DRM_FORMAT_XRGB16161616F:
6216         case DRM_FORMAT_ARGB16161616F:
6217                 if (INTEL_GEN(dev_priv) >= 11)
6218                         break;
6219                 /* fall through */
6220         default:
6221                 drm_dbg_kms(&dev_priv->drm,
6222                             "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
6223                             intel_plane->base.base.id, intel_plane->base.name,
6224                             fb->base.id, fb->format->format);
6225                 return -EINVAL;
6226         }
6227
6228         return 0;
6229 }
6230
6231 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
6232 {
6233         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
6234         int i;
6235
6236         for (i = 0; i < crtc->num_scalers; i++)
6237                 skl_detach_scaler(crtc, i);
6238 }
6239
6240 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
6241 {
6242         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6243         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6244         enum pipe pipe = crtc->pipe;
6245         const struct intel_crtc_scaler_state *scaler_state =
6246                 &crtc_state->scaler_state;
6247
6248         if (crtc_state->pch_pfit.enabled) {
6249                 u16 uv_rgb_hphase, uv_rgb_vphase;
6250                 int pfit_w, pfit_h, hscale, vscale;
6251                 unsigned long irqflags;
6252                 int id;
6253
6254                 if (drm_WARN_ON(&dev_priv->drm,
6255                                 crtc_state->scaler_state.scaler_id < 0))
6256                         return;
6257
6258                 pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
6259                 pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
6260
6261                 hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
6262                 vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
6263
6264                 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
6265                 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
6266
6267                 id = scaler_state->scaler_id;
6268
6269                 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6270
6271                 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
6272                                   PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
6273                 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
6274                                   PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
6275                 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
6276                                   PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
6277                 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
6278                                   crtc_state->pch_pfit.pos);
6279                 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
6280                                   crtc_state->pch_pfit.size);
6281
6282                 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6283         }
6284 }
6285
6286 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
6287 {
6288         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6289         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6290         enum pipe pipe = crtc->pipe;
6291
6292         if (crtc_state->pch_pfit.enabled) {
6293                 /* Force use of hard-coded filter coefficients
6294                  * as some pre-programmed values are broken,
6295                  * e.g. x201.
6296                  */
6297                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
6298                         intel_de_write(dev_priv, PF_CTL(pipe),
6299                                        PF_ENABLE | PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
6300                 else
6301                         intel_de_write(dev_priv, PF_CTL(pipe),
6302                                        PF_ENABLE | PF_FILTER_MED_3x3);
6303                 intel_de_write(dev_priv, PF_WIN_POS(pipe),
6304                                crtc_state->pch_pfit.pos);
6305                 intel_de_write(dev_priv, PF_WIN_SZ(pipe),
6306                                crtc_state->pch_pfit.size);
6307         }
6308 }
6309
6310 void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
6311 {
6312         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6313         struct drm_device *dev = crtc->base.dev;
6314         struct drm_i915_private *dev_priv = to_i915(dev);
6315
6316         if (!crtc_state->ips_enabled)
6317                 return;
6318
6319         /*
6320          * We can only enable IPS after we enable a plane and wait for a vblank
6321          * This function is called from post_plane_update, which is run after
6322          * a vblank wait.
6323          */
6324         drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
6325
6326         if (IS_BROADWELL(dev_priv)) {
6327                 drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
6328                                                          IPS_ENABLE | IPS_PCODE_CONTROL));
6329                 /* Quoting Art Runyan: "its not safe to expect any particular
6330                  * value in IPS_CTL bit 31 after enabling IPS through the
6331                  * mailbox." Moreover, the mailbox may return a bogus state,
6332                  * so we need to just enable it and continue on.
6333                  */
6334         } else {
6335                 intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE);
6336                 /* The bit only becomes 1 in the next vblank, so this wait here
6337                  * is essentially intel_wait_for_vblank. If we don't have this
6338                  * and don't wait for vblanks until the end of crtc_enable, then
6339                  * the HW state readout code will complain that the expected
6340                  * IPS_CTL value is not the one we read. */
6341                 if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
6342                         drm_err(&dev_priv->drm,
6343                                 "Timed out waiting for IPS enable\n");
6344         }
6345 }
6346
6347 void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
6348 {
6349         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6350         struct drm_device *dev = crtc->base.dev;
6351         struct drm_i915_private *dev_priv = to_i915(dev);
6352
6353         if (!crtc_state->ips_enabled)
6354                 return;
6355
6356         if (IS_BROADWELL(dev_priv)) {
6357                 drm_WARN_ON(dev,
6358                             sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
6359                 /*
6360                  * Wait for PCODE to finish disabling IPS. The BSpec specified
6361                  * 42ms timeout value leads to occasional timeouts so use 100ms
6362                  * instead.
6363                  */
6364                 if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
6365                         drm_err(&dev_priv->drm,
6366                                 "Timed out waiting for IPS disable\n");
6367         } else {
6368                 intel_de_write(dev_priv, IPS_CTL, 0);
6369                 intel_de_posting_read(dev_priv, IPS_CTL);
6370         }
6371
6372         /* We need to wait for a vblank before we can disable the plane. */
6373         intel_wait_for_vblank(dev_priv, crtc->pipe);
6374 }
6375
6376 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
6377 {
6378         if (intel_crtc->overlay)
6379                 (void) intel_overlay_switch_off(intel_crtc->overlay);
6380
6381         /* Let userspace switch the overlay on again. In most cases userspace
6382          * has to recompute where to put it anyway.
6383          */
6384 }
6385
6386 static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state,
6387                                        const struct intel_crtc_state *new_crtc_state)
6388 {
6389         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6390         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6391
6392         if (!old_crtc_state->ips_enabled)
6393                 return false;
6394
6395         if (needs_modeset(new_crtc_state))
6396                 return true;
6397
6398         /*
6399          * Workaround : Do not read or write the pipe palette/gamma data while
6400          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6401          *
6402          * Disable IPS before we program the LUT.
6403          */
6404         if (IS_HASWELL(dev_priv) &&
6405             (new_crtc_state->uapi.color_mgmt_changed ||
6406              new_crtc_state->update_pipe) &&
6407             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6408                 return true;
6409
6410         return !new_crtc_state->ips_enabled;
6411 }
6412
6413 static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state,
6414                                        const struct intel_crtc_state *new_crtc_state)
6415 {
6416         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6417         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6418
6419         if (!new_crtc_state->ips_enabled)
6420                 return false;
6421
6422         if (needs_modeset(new_crtc_state))
6423                 return true;
6424
6425         /*
6426          * Workaround : Do not read or write the pipe palette/gamma data while
6427          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6428          *
6429          * Re-enable IPS after the LUT has been programmed.
6430          */
6431         if (IS_HASWELL(dev_priv) &&
6432             (new_crtc_state->uapi.color_mgmt_changed ||
6433              new_crtc_state->update_pipe) &&
6434             new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
6435                 return true;
6436
6437         /*
6438          * We can't read out IPS on broadwell, assume the worst and
6439          * forcibly enable IPS on the first fastset.
6440          */
6441         if (new_crtc_state->update_pipe &&
6442             old_crtc_state->hw.adjusted_mode.private_flags & I915_MODE_FLAG_INHERITED)
6443                 return true;
6444
6445         return !old_crtc_state->ips_enabled;
6446 }
6447
6448 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
6449 {
6450         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6451
6452         if (!crtc_state->nv12_planes)
6453                 return false;
6454
6455         /* WA Display #0827: Gen9:all */
6456         if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
6457                 return true;
6458
6459         return false;
6460 }
6461
6462 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
6463 {
6464         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
6465
6466         /* Wa_2006604312:icl */
6467         if (crtc_state->scaler_state.scaler_users > 0 && IS_ICELAKE(dev_priv))
6468                 return true;
6469
6470         return false;
6471 }
6472
6473 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
6474                             const struct intel_crtc_state *new_crtc_state)
6475 {
6476         return (!old_crtc_state->active_planes || needs_modeset(new_crtc_state)) &&
6477                 new_crtc_state->active_planes;
6478 }
6479
6480 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
6481                              const struct intel_crtc_state *new_crtc_state)
6482 {
6483         return old_crtc_state->active_planes &&
6484                 (!new_crtc_state->active_planes || needs_modeset(new_crtc_state));
6485 }
6486
6487 static void intel_post_plane_update(struct intel_atomic_state *state,
6488                                     struct intel_crtc *crtc)
6489 {
6490         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6491         const struct intel_crtc_state *old_crtc_state =
6492                 intel_atomic_get_old_crtc_state(state, crtc);
6493         const struct intel_crtc_state *new_crtc_state =
6494                 intel_atomic_get_new_crtc_state(state, crtc);
6495         enum pipe pipe = crtc->pipe;
6496
6497         intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
6498
6499         if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
6500                 intel_update_watermarks(crtc);
6501
6502         if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
6503                 hsw_enable_ips(new_crtc_state);
6504
6505         intel_fbc_post_update(state, crtc);
6506
6507         if (needs_nv12_wa(old_crtc_state) &&
6508             !needs_nv12_wa(new_crtc_state))
6509                 skl_wa_827(dev_priv, pipe, false);
6510
6511         if (needs_scalerclk_wa(old_crtc_state) &&
6512             !needs_scalerclk_wa(new_crtc_state))
6513                 icl_wa_scalerclkgating(dev_priv, pipe, false);
6514 }
6515
6516 static void intel_pre_plane_update(struct intel_atomic_state *state,
6517                                    struct intel_crtc *crtc)
6518 {
6519         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6520         const struct intel_crtc_state *old_crtc_state =
6521                 intel_atomic_get_old_crtc_state(state, crtc);
6522         const struct intel_crtc_state *new_crtc_state =
6523                 intel_atomic_get_new_crtc_state(state, crtc);
6524         enum pipe pipe = crtc->pipe;
6525
6526         if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state))
6527                 hsw_disable_ips(old_crtc_state);
6528
6529         if (intel_fbc_pre_update(state, crtc))
6530                 intel_wait_for_vblank(dev_priv, pipe);
6531
6532         /* Display WA 827 */
6533         if (!needs_nv12_wa(old_crtc_state) &&
6534             needs_nv12_wa(new_crtc_state))
6535                 skl_wa_827(dev_priv, pipe, true);
6536
6537         /* Wa_2006604312:icl */
6538         if (!needs_scalerclk_wa(old_crtc_state) &&
6539             needs_scalerclk_wa(new_crtc_state))
6540                 icl_wa_scalerclkgating(dev_priv, pipe, true);
6541
6542         /*
6543          * Vblank time updates from the shadow to live plane control register
6544          * are blocked if the memory self-refresh mode is active at that
6545          * moment. So to make sure the plane gets truly disabled, disable
6546          * first the self-refresh mode. The self-refresh enable bit in turn
6547          * will be checked/applied by the HW only at the next frame start
6548          * event which is after the vblank start event, so we need to have a
6549          * wait-for-vblank between disabling the plane and the pipe.
6550          */
6551         if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
6552             new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
6553                 intel_wait_for_vblank(dev_priv, pipe);
6554
6555         /*
6556          * IVB workaround: must disable low power watermarks for at least
6557          * one frame before enabling scaling.  LP watermarks can be re-enabled
6558          * when scaling is disabled.
6559          *
6560          * WaCxSRDisabledForSpriteScaling:ivb
6561          */
6562         if (old_crtc_state->hw.active &&
6563             new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
6564                 intel_wait_for_vblank(dev_priv, pipe);
6565
6566         /*
6567          * If we're doing a modeset we don't need to do any
6568          * pre-vblank watermark programming here.
6569          */
6570         if (!needs_modeset(new_crtc_state)) {
6571                 /*
6572                  * For platforms that support atomic watermarks, program the
6573                  * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
6574                  * will be the intermediate values that are safe for both pre- and
6575                  * post- vblank; when vblank happens, the 'active' values will be set
6576                  * to the final 'target' values and we'll do this again to get the
6577                  * optimal watermarks.  For gen9+ platforms, the values we program here
6578                  * will be the final target values which will get automatically latched
6579                  * at vblank time; no further programming will be necessary.
6580                  *
6581                  * If a platform hasn't been transitioned to atomic watermarks yet,
6582                  * we'll continue to update watermarks the old way, if flags tell
6583                  * us to.
6584                  */
6585                 if (dev_priv->display.initial_watermarks)
6586                         dev_priv->display.initial_watermarks(state, crtc);
6587                 else if (new_crtc_state->update_wm_pre)
6588                         intel_update_watermarks(crtc);
6589         }
6590
6591         /*
6592          * Gen2 reports pipe underruns whenever all planes are disabled.
6593          * So disable underrun reporting before all the planes get disabled.
6594          *
6595          * We do this after .initial_watermarks() so that we have a
6596          * chance of catching underruns with the intermediate watermarks
6597          * vs. the old plane configuration.
6598          */
6599         if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state))
6600                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6601 }
6602
6603 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
6604                                       struct intel_crtc *crtc)
6605 {
6606         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6607         const struct intel_crtc_state *new_crtc_state =
6608                 intel_atomic_get_new_crtc_state(state, crtc);
6609         unsigned int update_mask = new_crtc_state->update_planes;
6610         const struct intel_plane_state *old_plane_state;
6611         struct intel_plane *plane;
6612         unsigned fb_bits = 0;
6613         int i;
6614
6615         intel_crtc_dpms_overlay_disable(crtc);
6616
6617         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
6618                 if (crtc->pipe != plane->pipe ||
6619                     !(update_mask & BIT(plane->id)))
6620                         continue;
6621
6622                 intel_disable_plane(plane, new_crtc_state);
6623
6624                 if (old_plane_state->uapi.visible)
6625                         fb_bits |= plane->frontbuffer_bit;
6626         }
6627
6628         intel_frontbuffer_flip(dev_priv, fb_bits);
6629 }
6630
6631 /*
6632  * intel_connector_primary_encoder - get the primary encoder for a connector
6633  * @connector: connector for which to return the encoder
6634  *
6635  * Returns the primary encoder for a connector. There is a 1:1 mapping from
6636  * all connectors to their encoder, except for DP-MST connectors which have
6637  * both a virtual and a primary encoder. These DP-MST primary encoders can be
6638  * pointed to by as many DP-MST connectors as there are pipes.
6639  */
6640 static struct intel_encoder *
6641 intel_connector_primary_encoder(struct intel_connector *connector)
6642 {
6643         struct intel_encoder *encoder;
6644
6645         if (connector->mst_port)
6646                 return &dp_to_dig_port(connector->mst_port)->base;
6647
6648         encoder = intel_attached_encoder(connector);
6649         WARN_ON(!encoder);
6650
6651         return encoder;
6652 }
6653
6654 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
6655 {
6656         struct drm_connector_state *new_conn_state;
6657         struct drm_connector *connector;
6658         int i;
6659
6660         for_each_new_connector_in_state(&state->base, connector, new_conn_state,
6661                                         i) {
6662                 struct intel_connector *intel_connector;
6663                 struct intel_encoder *encoder;
6664                 struct intel_crtc *crtc;
6665
6666                 if (!intel_connector_needs_modeset(state, connector))
6667                         continue;
6668
6669                 intel_connector = to_intel_connector(connector);
6670                 encoder = intel_connector_primary_encoder(intel_connector);
6671                 if (!encoder->update_prepare)
6672                         continue;
6673
6674                 crtc = new_conn_state->crtc ?
6675                         to_intel_crtc(new_conn_state->crtc) : NULL;
6676                 encoder->update_prepare(state, encoder, crtc);
6677         }
6678 }
6679
6680 static void intel_encoders_update_complete(struct intel_atomic_state *state)
6681 {
6682         struct drm_connector_state *new_conn_state;
6683         struct drm_connector *connector;
6684         int i;
6685
6686         for_each_new_connector_in_state(&state->base, connector, new_conn_state,
6687                                         i) {
6688                 struct intel_connector *intel_connector;
6689                 struct intel_encoder *encoder;
6690                 struct intel_crtc *crtc;
6691
6692                 if (!intel_connector_needs_modeset(state, connector))
6693                         continue;
6694
6695                 intel_connector = to_intel_connector(connector);
6696                 encoder = intel_connector_primary_encoder(intel_connector);
6697                 if (!encoder->update_complete)
6698                         continue;
6699
6700                 crtc = new_conn_state->crtc ?
6701                         to_intel_crtc(new_conn_state->crtc) : NULL;
6702                 encoder->update_complete(state, encoder, crtc);
6703         }
6704 }
6705
6706 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
6707                                           struct intel_crtc *crtc)
6708 {
6709         const struct intel_crtc_state *crtc_state =
6710                 intel_atomic_get_new_crtc_state(state, crtc);
6711         const struct drm_connector_state *conn_state;
6712         struct drm_connector *conn;
6713         int i;
6714
6715         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6716                 struct intel_encoder *encoder =
6717                         to_intel_encoder(conn_state->best_encoder);
6718
6719                 if (conn_state->crtc != &crtc->base)
6720                         continue;
6721
6722                 if (encoder->pre_pll_enable)
6723                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
6724         }
6725 }
6726
6727 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
6728                                       struct intel_crtc *crtc)
6729 {
6730         const struct intel_crtc_state *crtc_state =
6731                 intel_atomic_get_new_crtc_state(state, crtc);
6732         const struct drm_connector_state *conn_state;
6733         struct drm_connector *conn;
6734         int i;
6735
6736         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6737                 struct intel_encoder *encoder =
6738                         to_intel_encoder(conn_state->best_encoder);
6739
6740                 if (conn_state->crtc != &crtc->base)
6741                         continue;
6742
6743                 if (encoder->pre_enable)
6744                         encoder->pre_enable(encoder, crtc_state, conn_state);
6745         }
6746 }
6747
6748 static void intel_encoders_enable(struct intel_atomic_state *state,
6749                                   struct intel_crtc *crtc)
6750 {
6751         const struct intel_crtc_state *crtc_state =
6752                 intel_atomic_get_new_crtc_state(state, crtc);
6753         const struct drm_connector_state *conn_state;
6754         struct drm_connector *conn;
6755         int i;
6756
6757         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6758                 struct intel_encoder *encoder =
6759                         to_intel_encoder(conn_state->best_encoder);
6760
6761                 if (conn_state->crtc != &crtc->base)
6762                         continue;
6763
6764                 if (encoder->enable)
6765                         encoder->enable(encoder, crtc_state, conn_state);
6766                 intel_opregion_notify_encoder(encoder, true);
6767         }
6768 }
6769
6770 static void intel_encoders_disable(struct intel_atomic_state *state,
6771                                    struct intel_crtc *crtc)
6772 {
6773         const struct intel_crtc_state *old_crtc_state =
6774                 intel_atomic_get_old_crtc_state(state, crtc);
6775         const struct drm_connector_state *old_conn_state;
6776         struct drm_connector *conn;
6777         int i;
6778
6779         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6780                 struct intel_encoder *encoder =
6781                         to_intel_encoder(old_conn_state->best_encoder);
6782
6783                 if (old_conn_state->crtc != &crtc->base)
6784                         continue;
6785
6786                 intel_opregion_notify_encoder(encoder, false);
6787                 if (encoder->disable)
6788                         encoder->disable(encoder, old_crtc_state, old_conn_state);
6789         }
6790 }
6791
6792 static void intel_encoders_post_disable(struct intel_atomic_state *state,
6793                                         struct intel_crtc *crtc)
6794 {
6795         const struct intel_crtc_state *old_crtc_state =
6796                 intel_atomic_get_old_crtc_state(state, crtc);
6797         const struct drm_connector_state *old_conn_state;
6798         struct drm_connector *conn;
6799         int i;
6800
6801         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6802                 struct intel_encoder *encoder =
6803                         to_intel_encoder(old_conn_state->best_encoder);
6804
6805                 if (old_conn_state->crtc != &crtc->base)
6806                         continue;
6807
6808                 if (encoder->post_disable)
6809                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
6810         }
6811 }
6812
6813 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
6814                                             struct intel_crtc *crtc)
6815 {
6816         const struct intel_crtc_state *old_crtc_state =
6817                 intel_atomic_get_old_crtc_state(state, crtc);
6818         const struct drm_connector_state *old_conn_state;
6819         struct drm_connector *conn;
6820         int i;
6821
6822         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6823                 struct intel_encoder *encoder =
6824                         to_intel_encoder(old_conn_state->best_encoder);
6825
6826                 if (old_conn_state->crtc != &crtc->base)
6827                         continue;
6828
6829                 if (encoder->post_pll_disable)
6830                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
6831         }
6832 }
6833
6834 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
6835                                        struct intel_crtc *crtc)
6836 {
6837         const struct intel_crtc_state *crtc_state =
6838                 intel_atomic_get_new_crtc_state(state, crtc);
6839         const struct drm_connector_state *conn_state;
6840         struct drm_connector *conn;
6841         int i;
6842
6843         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6844                 struct intel_encoder *encoder =
6845                         to_intel_encoder(conn_state->best_encoder);
6846
6847                 if (conn_state->crtc != &crtc->base)
6848                         continue;
6849
6850                 if (encoder->update_pipe)
6851                         encoder->update_pipe(encoder, crtc_state, conn_state);
6852         }
6853 }
6854
6855 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
6856 {
6857         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6858         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
6859
6860         plane->disable_plane(plane, crtc_state);
6861 }
6862
6863 static void ilk_crtc_enable(struct intel_atomic_state *state,
6864                             struct intel_crtc *crtc)
6865 {
6866         const struct intel_crtc_state *new_crtc_state =
6867                 intel_atomic_get_new_crtc_state(state, crtc);
6868         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6869         enum pipe pipe = crtc->pipe;
6870
6871         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
6872                 return;
6873
6874         /*
6875          * Sometimes spurious CPU pipe underruns happen during FDI
6876          * training, at least with VGA+HDMI cloning. Suppress them.
6877          *
6878          * On ILK we get an occasional spurious CPU pipe underruns
6879          * between eDP port A enable and vdd enable. Also PCH port
6880          * enable seems to result in the occasional CPU pipe underrun.
6881          *
6882          * Spurious PCH underruns also occur during PCH enabling.
6883          */
6884         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6885         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6886
6887         if (new_crtc_state->has_pch_encoder)
6888                 intel_prepare_shared_dpll(new_crtc_state);
6889
6890         if (intel_crtc_has_dp_encoder(new_crtc_state))
6891                 intel_dp_set_m_n(new_crtc_state, M1_N1);
6892
6893         intel_set_pipe_timings(new_crtc_state);
6894         intel_set_pipe_src_size(new_crtc_state);
6895
6896         if (new_crtc_state->has_pch_encoder)
6897                 intel_cpu_transcoder_set_m_n(new_crtc_state,
6898                                              &new_crtc_state->fdi_m_n, NULL);
6899
6900         ilk_set_pipeconf(new_crtc_state);
6901
6902         crtc->active = true;
6903
6904         intel_encoders_pre_enable(state, crtc);
6905
6906         if (new_crtc_state->has_pch_encoder) {
6907                 /* Note: FDI PLL enabling _must_ be done before we enable the
6908                  * cpu pipes, hence this is separate from all the other fdi/pch
6909                  * enabling. */
6910                 ilk_fdi_pll_enable(new_crtc_state);
6911         } else {
6912                 assert_fdi_tx_disabled(dev_priv, pipe);
6913                 assert_fdi_rx_disabled(dev_priv, pipe);
6914         }
6915
6916         ilk_pfit_enable(new_crtc_state);
6917
6918         /*
6919          * On ILK+ LUT must be loaded before the pipe is running but with
6920          * clocks enabled
6921          */
6922         intel_color_load_luts(new_crtc_state);
6923         intel_color_commit(new_crtc_state);
6924         /* update DSPCNTR to configure gamma for pipe bottom color */
6925         intel_disable_primary_plane(new_crtc_state);
6926
6927         if (dev_priv->display.initial_watermarks)
6928                 dev_priv->display.initial_watermarks(state, crtc);
6929         intel_enable_pipe(new_crtc_state);
6930
6931         if (new_crtc_state->has_pch_encoder)
6932                 ilk_pch_enable(state, new_crtc_state);
6933
6934         intel_crtc_vblank_on(new_crtc_state);
6935
6936         intel_encoders_enable(state, crtc);
6937
6938         if (HAS_PCH_CPT(dev_priv))
6939                 cpt_verify_modeset(dev_priv, pipe);
6940
6941         /*
6942          * Must wait for vblank to avoid spurious PCH FIFO underruns.
6943          * And a second vblank wait is needed at least on ILK with
6944          * some interlaced HDMI modes. Let's do the double wait always
6945          * in case there are more corner cases we don't know about.
6946          */
6947         if (new_crtc_state->has_pch_encoder) {
6948                 intel_wait_for_vblank(dev_priv, pipe);
6949                 intel_wait_for_vblank(dev_priv, pipe);
6950         }
6951         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6952         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6953 }
6954
6955 /* IPS only exists on ULT machines and is tied to pipe A. */
6956 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
6957 {
6958         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
6959 }
6960
6961 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
6962                                             enum pipe pipe, bool apply)
6963 {
6964         u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
6965         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
6966
6967         if (apply)
6968                 val |= mask;
6969         else
6970                 val &= ~mask;
6971
6972         intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
6973 }
6974
6975 static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
6976 {
6977         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6978         enum pipe pipe = crtc->pipe;
6979         u32 val;
6980
6981         val = MBUS_DBOX_A_CREDIT(2);
6982
6983         if (INTEL_GEN(dev_priv) >= 12) {
6984                 val |= MBUS_DBOX_BW_CREDIT(2);
6985                 val |= MBUS_DBOX_B_CREDIT(12);
6986         } else {
6987                 val |= MBUS_DBOX_BW_CREDIT(1);
6988                 val |= MBUS_DBOX_B_CREDIT(8);
6989         }
6990
6991         intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val);
6992 }
6993
6994 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
6995 {
6996         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
6997         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6998
6999         intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
7000                        HSW_LINETIME(crtc_state->linetime) |
7001                        HSW_IPS_LINETIME(crtc_state->ips_linetime));
7002 }
7003
7004 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
7005 {
7006         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7007         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7008         i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
7009         u32 val;
7010
7011         val = intel_de_read(dev_priv, reg);
7012         val &= ~HSW_FRAME_START_DELAY_MASK;
7013         val |= HSW_FRAME_START_DELAY(0);
7014         intel_de_write(dev_priv, reg, val);
7015 }
7016
7017 static void hsw_crtc_enable(struct intel_atomic_state *state,
7018                             struct intel_crtc *crtc)
7019 {
7020         const struct intel_crtc_state *new_crtc_state =
7021                 intel_atomic_get_new_crtc_state(state, crtc);
7022         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7023         enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
7024         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
7025         bool psl_clkgate_wa;
7026
7027         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7028                 return;
7029
7030         intel_encoders_pre_pll_enable(state, crtc);
7031
7032         if (new_crtc_state->shared_dpll)
7033                 intel_enable_shared_dpll(new_crtc_state);
7034
7035         intel_encoders_pre_enable(state, crtc);
7036
7037         if (!transcoder_is_dsi(cpu_transcoder))
7038                 intel_set_pipe_timings(new_crtc_state);
7039
7040         if (INTEL_GEN(dev_priv) >= 11)
7041                 icl_enable_trans_port_sync(new_crtc_state);
7042
7043         intel_set_pipe_src_size(new_crtc_state);
7044
7045         if (cpu_transcoder != TRANSCODER_EDP &&
7046             !transcoder_is_dsi(cpu_transcoder))
7047                 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
7048                                new_crtc_state->pixel_multiplier - 1);
7049
7050         if (new_crtc_state->has_pch_encoder)
7051                 intel_cpu_transcoder_set_m_n(new_crtc_state,
7052                                              &new_crtc_state->fdi_m_n, NULL);
7053
7054         if (!transcoder_is_dsi(cpu_transcoder)) {
7055                 hsw_set_frame_start_delay(new_crtc_state);
7056                 hsw_set_pipeconf(new_crtc_state);
7057         }
7058
7059         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
7060                 bdw_set_pipemisc(new_crtc_state);
7061
7062         crtc->active = true;
7063
7064         /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
7065         psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
7066                 new_crtc_state->pch_pfit.enabled;
7067         if (psl_clkgate_wa)
7068                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
7069
7070         if (INTEL_GEN(dev_priv) >= 9)
7071                 skl_pfit_enable(new_crtc_state);
7072         else
7073                 ilk_pfit_enable(new_crtc_state);
7074
7075         /*
7076          * On ILK+ LUT must be loaded before the pipe is running but with
7077          * clocks enabled
7078          */
7079         intel_color_load_luts(new_crtc_state);
7080         intel_color_commit(new_crtc_state);
7081         /* update DSPCNTR to configure gamma/csc for pipe bottom color */
7082         if (INTEL_GEN(dev_priv) < 9)
7083                 intel_disable_primary_plane(new_crtc_state);
7084
7085         hsw_set_linetime_wm(new_crtc_state);
7086
7087         if (INTEL_GEN(dev_priv) >= 11)
7088                 icl_set_pipe_chicken(crtc);
7089
7090         if (!transcoder_is_dsi(cpu_transcoder))
7091                 intel_ddi_enable_transcoder_func(new_crtc_state);
7092
7093         if (dev_priv->display.initial_watermarks)
7094                 dev_priv->display.initial_watermarks(state, crtc);
7095
7096         if (INTEL_GEN(dev_priv) >= 11)
7097                 icl_pipe_mbus_enable(crtc);
7098
7099         intel_encoders_enable(state, crtc);
7100
7101         if (psl_clkgate_wa) {
7102                 intel_wait_for_vblank(dev_priv, pipe);
7103                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
7104         }
7105
7106         /* If we change the relative order between pipe/planes enabling, we need
7107          * to change the workaround. */
7108         hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
7109         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
7110                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
7111                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
7112         }
7113 }
7114
7115 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7116 {
7117         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7118         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7119         enum pipe pipe = crtc->pipe;
7120
7121         /* To avoid upsetting the power well on haswell only disable the pfit if
7122          * it's in use. The hw state code will make sure we get this right. */
7123         if (old_crtc_state->pch_pfit.enabled) {
7124                 intel_de_write(dev_priv, PF_CTL(pipe), 0);
7125                 intel_de_write(dev_priv, PF_WIN_POS(pipe), 0);
7126                 intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0);
7127         }
7128 }
7129
7130 static void ilk_crtc_disable(struct intel_atomic_state *state,
7131                              struct intel_crtc *crtc)
7132 {
7133         const struct intel_crtc_state *old_crtc_state =
7134                 intel_atomic_get_old_crtc_state(state, crtc);
7135         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7136         enum pipe pipe = crtc->pipe;
7137
7138         /*
7139          * Sometimes spurious CPU pipe underruns happen when the
7140          * pipe is already disabled, but FDI RX/TX is still enabled.
7141          * Happens at least with VGA+HDMI cloning. Suppress them.
7142          */
7143         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7144         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
7145
7146         intel_encoders_disable(state, crtc);
7147
7148         intel_crtc_vblank_off(old_crtc_state);
7149
7150         intel_disable_pipe(old_crtc_state);
7151
7152         ilk_pfit_disable(old_crtc_state);
7153
7154         if (old_crtc_state->has_pch_encoder)
7155                 ilk_fdi_disable(crtc);
7156
7157         intel_encoders_post_disable(state, crtc);
7158
7159         if (old_crtc_state->has_pch_encoder) {
7160                 ilk_disable_pch_transcoder(dev_priv, pipe);
7161
7162                 if (HAS_PCH_CPT(dev_priv)) {
7163                         i915_reg_t reg;
7164                         u32 temp;
7165
7166                         /* disable TRANS_DP_CTL */
7167                         reg = TRANS_DP_CTL(pipe);
7168                         temp = intel_de_read(dev_priv, reg);
7169                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
7170                                   TRANS_DP_PORT_SEL_MASK);
7171                         temp |= TRANS_DP_PORT_SEL_NONE;
7172                         intel_de_write(dev_priv, reg, temp);
7173
7174                         /* disable DPLL_SEL */
7175                         temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
7176                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
7177                         intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
7178                 }
7179
7180                 ilk_fdi_pll_disable(crtc);
7181         }
7182
7183         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7184         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
7185 }
7186
7187 static void hsw_crtc_disable(struct intel_atomic_state *state,
7188                              struct intel_crtc *crtc)
7189 {
7190         /*
7191          * FIXME collapse everything to one hook.
7192          * Need care with mst->ddi interactions.
7193          */
7194         intel_encoders_disable(state, crtc);
7195         intel_encoders_post_disable(state, crtc);
7196 }
7197
7198 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
7199 {
7200         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7201         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7202
7203         if (!crtc_state->gmch_pfit.control)
7204                 return;
7205
7206         /*
7207          * The panel fitter should only be adjusted whilst the pipe is disabled,
7208          * according to register description and PRM.
7209          */
7210         drm_WARN_ON(&dev_priv->drm,
7211                     intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
7212         assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder);
7213
7214         intel_de_write(dev_priv, PFIT_PGM_RATIOS,
7215                        crtc_state->gmch_pfit.pgm_ratios);
7216         intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
7217
7218         /* Border color in case we don't scale up to the full screen. Black by
7219          * default, change to something else for debugging. */
7220         intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
7221 }
7222
7223 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
7224 {
7225         if (phy == PHY_NONE)
7226                 return false;
7227
7228         if (IS_ELKHARTLAKE(dev_priv))
7229                 return phy <= PHY_C;
7230
7231         if (INTEL_GEN(dev_priv) >= 11)
7232                 return phy <= PHY_B;
7233
7234         return false;
7235 }
7236
7237 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
7238 {
7239         if (INTEL_GEN(dev_priv) >= 12)
7240                 return phy >= PHY_D && phy <= PHY_I;
7241
7242         if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
7243                 return phy >= PHY_C && phy <= PHY_F;
7244
7245         return false;
7246 }
7247
7248 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
7249 {
7250         if (IS_ELKHARTLAKE(i915) && port == PORT_D)
7251                 return PHY_A;
7252
7253         return (enum phy)port;
7254 }
7255
7256 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
7257 {
7258         if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
7259                 return PORT_TC_NONE;
7260
7261         if (INTEL_GEN(dev_priv) >= 12)
7262                 return port - PORT_D;
7263
7264         return port - PORT_C;
7265 }
7266
7267 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
7268 {
7269         switch (port) {
7270         case PORT_A:
7271                 return POWER_DOMAIN_PORT_DDI_A_LANES;
7272         case PORT_B:
7273                 return POWER_DOMAIN_PORT_DDI_B_LANES;
7274         case PORT_C:
7275                 return POWER_DOMAIN_PORT_DDI_C_LANES;
7276         case PORT_D:
7277                 return POWER_DOMAIN_PORT_DDI_D_LANES;
7278         case PORT_E:
7279                 return POWER_DOMAIN_PORT_DDI_E_LANES;
7280         case PORT_F:
7281                 return POWER_DOMAIN_PORT_DDI_F_LANES;
7282         case PORT_G:
7283                 return POWER_DOMAIN_PORT_DDI_G_LANES;
7284         default:
7285                 MISSING_CASE(port);
7286                 return POWER_DOMAIN_PORT_OTHER;
7287         }
7288 }
7289
7290 enum intel_display_power_domain
7291 intel_aux_power_domain(struct intel_digital_port *dig_port)
7292 {
7293         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
7294         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
7295
7296         if (intel_phy_is_tc(dev_priv, phy) &&
7297             dig_port->tc_mode == TC_PORT_TBT_ALT) {
7298                 switch (dig_port->aux_ch) {
7299                 case AUX_CH_C:
7300                         return POWER_DOMAIN_AUX_C_TBT;
7301                 case AUX_CH_D:
7302                         return POWER_DOMAIN_AUX_D_TBT;
7303                 case AUX_CH_E:
7304                         return POWER_DOMAIN_AUX_E_TBT;
7305                 case AUX_CH_F:
7306                         return POWER_DOMAIN_AUX_F_TBT;
7307                 case AUX_CH_G:
7308                         return POWER_DOMAIN_AUX_G_TBT;
7309                 default:
7310                         MISSING_CASE(dig_port->aux_ch);
7311                         return POWER_DOMAIN_AUX_C_TBT;
7312                 }
7313         }
7314
7315         switch (dig_port->aux_ch) {
7316         case AUX_CH_A:
7317                 return POWER_DOMAIN_AUX_A;
7318         case AUX_CH_B:
7319                 return POWER_DOMAIN_AUX_B;
7320         case AUX_CH_C:
7321                 return POWER_DOMAIN_AUX_C;
7322         case AUX_CH_D:
7323                 return POWER_DOMAIN_AUX_D;
7324         case AUX_CH_E:
7325                 return POWER_DOMAIN_AUX_E;
7326         case AUX_CH_F:
7327                 return POWER_DOMAIN_AUX_F;
7328         case AUX_CH_G:
7329                 return POWER_DOMAIN_AUX_G;
7330         default:
7331                 MISSING_CASE(dig_port->aux_ch);
7332                 return POWER_DOMAIN_AUX_A;
7333         }
7334 }
7335
7336 static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7337 {
7338         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7339         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7340         struct drm_encoder *encoder;
7341         enum pipe pipe = crtc->pipe;
7342         u64 mask;
7343         enum transcoder transcoder = crtc_state->cpu_transcoder;
7344
7345         if (!crtc_state->hw.active)
7346                 return 0;
7347
7348         mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
7349         mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));
7350         if (crtc_state->pch_pfit.enabled ||
7351             crtc_state->pch_pfit.force_thru)
7352                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
7353
7354         drm_for_each_encoder_mask(encoder, &dev_priv->drm,
7355                                   crtc_state->uapi.encoder_mask) {
7356                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7357
7358                 mask |= BIT_ULL(intel_encoder->power_domain);
7359         }
7360
7361         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
7362                 mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
7363
7364         if (crtc_state->shared_dpll)
7365                 mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
7366
7367         return mask;
7368 }
7369
7370 static u64
7371 modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
7372 {
7373         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7374         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7375         enum intel_display_power_domain domain;
7376         u64 domains, new_domains, old_domains;
7377
7378         old_domains = crtc->enabled_power_domains;
7379         crtc->enabled_power_domains = new_domains =
7380                 get_crtc_power_domains(crtc_state);
7381
7382         domains = new_domains & ~old_domains;
7383
7384         for_each_power_domain(domain, domains)
7385                 intel_display_power_get(dev_priv, domain);
7386
7387         return old_domains & ~new_domains;
7388 }
7389
7390 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
7391                                       u64 domains)
7392 {
7393         enum intel_display_power_domain domain;
7394
7395         for_each_power_domain(domain, domains)
7396                 intel_display_power_put_unchecked(dev_priv, domain);
7397 }
7398
7399 static void valleyview_crtc_enable(struct intel_atomic_state *state,
7400                                    struct intel_crtc *crtc)
7401 {
7402         const struct intel_crtc_state *new_crtc_state =
7403                 intel_atomic_get_new_crtc_state(state, crtc);
7404         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7405         enum pipe pipe = crtc->pipe;
7406
7407         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7408                 return;
7409
7410         if (intel_crtc_has_dp_encoder(new_crtc_state))
7411                 intel_dp_set_m_n(new_crtc_state, M1_N1);
7412
7413         intel_set_pipe_timings(new_crtc_state);
7414         intel_set_pipe_src_size(new_crtc_state);
7415
7416         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
7417                 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
7418                 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
7419         }
7420
7421         i9xx_set_pipeconf(new_crtc_state);
7422
7423         crtc->active = true;
7424
7425         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7426
7427         intel_encoders_pre_pll_enable(state, crtc);
7428
7429         if (IS_CHERRYVIEW(dev_priv)) {
7430                 chv_prepare_pll(crtc, new_crtc_state);
7431                 chv_enable_pll(crtc, new_crtc_state);
7432         } else {
7433                 vlv_prepare_pll(crtc, new_crtc_state);
7434                 vlv_enable_pll(crtc, new_crtc_state);
7435         }
7436
7437         intel_encoders_pre_enable(state, crtc);
7438
7439         i9xx_pfit_enable(new_crtc_state);
7440
7441         intel_color_load_luts(new_crtc_state);
7442         intel_color_commit(new_crtc_state);
7443         /* update DSPCNTR to configure gamma for pipe bottom color */
7444         intel_disable_primary_plane(new_crtc_state);
7445
7446         dev_priv->display.initial_watermarks(state, crtc);
7447         intel_enable_pipe(new_crtc_state);
7448
7449         intel_crtc_vblank_on(new_crtc_state);
7450
7451         intel_encoders_enable(state, crtc);
7452 }
7453
7454 static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
7455 {
7456         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7457         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7458
7459         intel_de_write(dev_priv, FP0(crtc->pipe),
7460                        crtc_state->dpll_hw_state.fp0);
7461         intel_de_write(dev_priv, FP1(crtc->pipe),
7462                        crtc_state->dpll_hw_state.fp1);
7463 }
7464
7465 static void i9xx_crtc_enable(struct intel_atomic_state *state,
7466                              struct intel_crtc *crtc)
7467 {
7468         const struct intel_crtc_state *new_crtc_state =
7469                 intel_atomic_get_new_crtc_state(state, crtc);
7470         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7471         enum pipe pipe = crtc->pipe;
7472
7473         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
7474                 return;
7475
7476         i9xx_set_pll_dividers(new_crtc_state);
7477
7478         if (intel_crtc_has_dp_encoder(new_crtc_state))
7479                 intel_dp_set_m_n(new_crtc_state, M1_N1);
7480
7481         intel_set_pipe_timings(new_crtc_state);
7482         intel_set_pipe_src_size(new_crtc_state);
7483
7484         i9xx_set_pipeconf(new_crtc_state);
7485
7486         crtc->active = true;
7487
7488         if (!IS_GEN(dev_priv, 2))
7489                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7490
7491         intel_encoders_pre_enable(state, crtc);
7492
7493         i9xx_enable_pll(crtc, new_crtc_state);
7494
7495         i9xx_pfit_enable(new_crtc_state);
7496
7497         intel_color_load_luts(new_crtc_state);
7498         intel_color_commit(new_crtc_state);
7499         /* update DSPCNTR to configure gamma for pipe bottom color */
7500         intel_disable_primary_plane(new_crtc_state);
7501
7502         if (dev_priv->display.initial_watermarks)
7503                 dev_priv->display.initial_watermarks(state, crtc);
7504         else
7505                 intel_update_watermarks(crtc);
7506         intel_enable_pipe(new_crtc_state);
7507
7508         intel_crtc_vblank_on(new_crtc_state);
7509
7510         intel_encoders_enable(state, crtc);
7511 }
7512
7513 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
7514 {
7515         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
7516         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7517
7518         if (!old_crtc_state->gmch_pfit.control)
7519                 return;
7520
7521         assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
7522
7523         drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
7524                     intel_de_read(dev_priv, PFIT_CONTROL));
7525         intel_de_write(dev_priv, PFIT_CONTROL, 0);
7526 }
7527
7528 static void i9xx_crtc_disable(struct intel_atomic_state *state,
7529                               struct intel_crtc *crtc)
7530 {
7531         struct intel_crtc_state *old_crtc_state =
7532                 intel_atomic_get_old_crtc_state(state, crtc);
7533         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7534         enum pipe pipe = crtc->pipe;
7535
7536         /*
7537          * On gen2 planes are double buffered but the pipe isn't, so we must
7538          * wait for planes to fully turn off before disabling the pipe.
7539          */
7540         if (IS_GEN(dev_priv, 2))
7541                 intel_wait_for_vblank(dev_priv, pipe);
7542
7543         intel_encoders_disable(state, crtc);
7544
7545         intel_crtc_vblank_off(old_crtc_state);
7546
7547         intel_disable_pipe(old_crtc_state);
7548
7549         i9xx_pfit_disable(old_crtc_state);
7550
7551         intel_encoders_post_disable(state, crtc);
7552
7553         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
7554                 if (IS_CHERRYVIEW(dev_priv))
7555                         chv_disable_pll(dev_priv, pipe);
7556                 else if (IS_VALLEYVIEW(dev_priv))
7557                         vlv_disable_pll(dev_priv, pipe);
7558                 else
7559                         i9xx_disable_pll(old_crtc_state);
7560         }
7561
7562         intel_encoders_post_pll_disable(state, crtc);
7563
7564         if (!IS_GEN(dev_priv, 2))
7565                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
7566
7567         if (!dev_priv->display.initial_watermarks)
7568                 intel_update_watermarks(crtc);
7569
7570         /* clock the pipe down to 640x480@60 to potentially save power */
7571         if (IS_I830(dev_priv))
7572                 i830_enable_pipe(dev_priv, pipe);
7573 }
7574
7575 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
7576                                         struct drm_modeset_acquire_ctx *ctx)
7577 {
7578         struct intel_encoder *encoder;
7579         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7580         struct intel_bw_state *bw_state =
7581                 to_intel_bw_state(dev_priv->bw_obj.state);
7582         struct intel_cdclk_state *cdclk_state =
7583                 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
7584         struct intel_crtc_state *crtc_state =
7585                 to_intel_crtc_state(crtc->base.state);
7586         enum intel_display_power_domain domain;
7587         struct intel_plane *plane;
7588         struct drm_atomic_state *state;
7589         struct intel_crtc_state *temp_crtc_state;
7590         enum pipe pipe = crtc->pipe;
7591         u64 domains;
7592         int ret;
7593
7594         if (!crtc_state->hw.active)
7595                 return;
7596
7597         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
7598                 const struct intel_plane_state *plane_state =
7599                         to_intel_plane_state(plane->base.state);
7600
7601                 if (plane_state->uapi.visible)
7602                         intel_plane_disable_noatomic(crtc, plane);
7603         }
7604
7605         state = drm_atomic_state_alloc(&dev_priv->drm);
7606         if (!state) {
7607                 drm_dbg_kms(&dev_priv->drm,
7608                             "failed to disable [CRTC:%d:%s], out of memory",
7609                             crtc->base.base.id, crtc->base.name);
7610                 return;
7611         }
7612
7613         state->acquire_ctx = ctx;
7614
7615         /* Everything's already locked, -EDEADLK can't happen. */
7616         temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
7617         ret = drm_atomic_add_affected_connectors(state, &crtc->base);
7618
7619         drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
7620
7621         dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
7622
7623         drm_atomic_state_put(state);
7624
7625         drm_dbg_kms(&dev_priv->drm,
7626                     "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
7627                     crtc->base.base.id, crtc->base.name);
7628
7629         crtc->active = false;
7630         crtc->base.enabled = false;
7631
7632         drm_WARN_ON(&dev_priv->drm,
7633                     drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
7634         crtc_state->uapi.active = false;
7635         crtc_state->uapi.connector_mask = 0;
7636         crtc_state->uapi.encoder_mask = 0;
7637         intel_crtc_free_hw_state(crtc_state);
7638         memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
7639
7640         for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
7641                 encoder->base.crtc = NULL;
7642
7643         intel_fbc_disable(crtc);
7644         intel_update_watermarks(crtc);
7645         intel_disable_shared_dpll(crtc_state);
7646
7647         domains = crtc->enabled_power_domains;
7648         for_each_power_domain(domain, domains)
7649                 intel_display_power_put_unchecked(dev_priv, domain);
7650         crtc->enabled_power_domains = 0;
7651
7652         dev_priv->active_pipes &= ~BIT(pipe);
7653         cdclk_state->min_cdclk[pipe] = 0;
7654         cdclk_state->min_voltage_level[pipe] = 0;
7655         cdclk_state->active_pipes &= ~BIT(pipe);
7656
7657         bw_state->data_rate[pipe] = 0;
7658         bw_state->num_active_planes[pipe] = 0;
7659 }
7660
7661 /*
7662  * turn all crtc's off, but do not adjust state
7663  * This has to be paired with a call to intel_modeset_setup_hw_state.
7664  */
7665 int intel_display_suspend(struct drm_device *dev)
7666 {
7667         struct drm_i915_private *dev_priv = to_i915(dev);
7668         struct drm_atomic_state *state;
7669         int ret;
7670
7671         state = drm_atomic_helper_suspend(dev);
7672         ret = PTR_ERR_OR_ZERO(state);
7673         if (ret)
7674                 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
7675                         ret);
7676         else
7677                 dev_priv->modeset_restore_state = state;
7678         return ret;
7679 }
7680
7681 void intel_encoder_destroy(struct drm_encoder *encoder)
7682 {
7683         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
7684
7685         drm_encoder_cleanup(encoder);
7686         kfree(intel_encoder);
7687 }
7688
7689 /* Cross check the actual hw state with our own modeset state tracking (and it's
7690  * internal consistency). */
7691 static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
7692                                          struct drm_connector_state *conn_state)
7693 {
7694         struct intel_connector *connector = to_intel_connector(conn_state->connector);
7695         struct drm_i915_private *i915 = to_i915(connector->base.dev);
7696
7697         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
7698                     connector->base.base.id, connector->base.name);
7699
7700         if (connector->get_hw_state(connector)) {
7701                 struct intel_encoder *encoder = intel_attached_encoder(connector);
7702
7703                 I915_STATE_WARN(!crtc_state,
7704                          "connector enabled without attached crtc\n");
7705
7706                 if (!crtc_state)
7707                         return;
7708
7709                 I915_STATE_WARN(!crtc_state->hw.active,
7710                                 "connector is active, but attached crtc isn't\n");
7711
7712                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
7713                         return;
7714
7715                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
7716                         "atomic encoder doesn't match attached encoder\n");
7717
7718                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
7719                         "attached encoder crtc differs from connector crtc\n");
7720         } else {
7721                 I915_STATE_WARN(crtc_state && crtc_state->hw.active,
7722                                 "attached crtc is active, but connector isn't\n");
7723                 I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
7724                         "best encoder set without crtc!\n");
7725         }
7726 }
7727
7728 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7729 {
7730         if (crtc_state->hw.enable && crtc_state->has_pch_encoder)
7731                 return crtc_state->fdi_lanes;
7732
7733         return 0;
7734 }
7735
7736 static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7737                                struct intel_crtc_state *pipe_config)
7738 {
7739         struct drm_i915_private *dev_priv = to_i915(dev);
7740         struct drm_atomic_state *state = pipe_config->uapi.state;
7741         struct intel_crtc *other_crtc;
7742         struct intel_crtc_state *other_crtc_state;
7743
7744         drm_dbg_kms(&dev_priv->drm,
7745                     "checking fdi config on pipe %c, lanes %i\n",
7746                     pipe_name(pipe), pipe_config->fdi_lanes);
7747         if (pipe_config->fdi_lanes > 4) {
7748                 drm_dbg_kms(&dev_priv->drm,
7749                             "invalid fdi lane config on pipe %c: %i lanes\n",
7750                             pipe_name(pipe), pipe_config->fdi_lanes);
7751                 return -EINVAL;
7752         }
7753
7754         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
7755                 if (pipe_config->fdi_lanes > 2) {
7756                         drm_dbg_kms(&dev_priv->drm,
7757                                     "only 2 lanes on haswell, required: %i lanes\n",
7758                                     pipe_config->fdi_lanes);
7759                         return -EINVAL;
7760                 } else {
7761                         return 0;
7762                 }
7763         }
7764
7765         if (INTEL_NUM_PIPES(dev_priv) == 2)
7766                 return 0;
7767
7768         /* Ivybridge 3 pipe is really complicated */
7769         switch (pipe) {
7770         case PIPE_A:
7771                 return 0;
7772         case PIPE_B:
7773                 if (pipe_config->fdi_lanes <= 2)
7774                         return 0;
7775
7776                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
7777                 other_crtc_state =
7778                         intel_atomic_get_crtc_state(state, other_crtc);
7779                 if (IS_ERR(other_crtc_state))
7780                         return PTR_ERR(other_crtc_state);
7781
7782                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7783                         drm_dbg_kms(&dev_priv->drm,
7784                                     "invalid shared fdi lane config on pipe %c: %i lanes\n",
7785                                     pipe_name(pipe), pipe_config->fdi_lanes);
7786                         return -EINVAL;
7787                 }
7788                 return 0;
7789         case PIPE_C:
7790                 if (pipe_config->fdi_lanes > 2) {
7791                         drm_dbg_kms(&dev_priv->drm,
7792                                     "only 2 lanes on pipe %c: required %i lanes\n",
7793                                     pipe_name(pipe), pipe_config->fdi_lanes);
7794                         return -EINVAL;
7795                 }
7796
7797                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
7798                 other_crtc_state =
7799                         intel_atomic_get_crtc_state(state, other_crtc);
7800                 if (IS_ERR(other_crtc_state))
7801                         return PTR_ERR(other_crtc_state);
7802
7803                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7804                         drm_dbg_kms(&dev_priv->drm,
7805                                     "fdi link B uses too many lanes to enable link C\n");
7806                         return -EINVAL;
7807                 }
7808                 return 0;
7809         default:
7810                 BUG();
7811         }
7812 }
7813
7814 #define RETRY 1
7815 static int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
7816                                   struct intel_crtc_state *pipe_config)
7817 {
7818         struct drm_device *dev = intel_crtc->base.dev;
7819         struct drm_i915_private *i915 = to_i915(dev);
7820         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7821         int lane, link_bw, fdi_dotclock, ret;
7822         bool needs_recompute = false;
7823
7824 retry:
7825         /* FDI is a binary signal running at ~2.7GHz, encoding
7826          * each output octet as 10 bits. The actual frequency
7827          * is stored as a divider into a 100MHz clock, and the
7828          * mode pixel clock is stored in units of 1KHz.
7829          * Hence the bw of each lane in terms of the mode signal
7830          * is:
7831          */
7832         link_bw = intel_fdi_link_freq(i915, pipe_config);
7833
7834         fdi_dotclock = adjusted_mode->crtc_clock;
7835
7836         lane = ilk_get_lanes_required(fdi_dotclock, link_bw,
7837                                       pipe_config->pipe_bpp);
7838
7839         pipe_config->fdi_lanes = lane;
7840
7841         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7842                                link_bw, &pipe_config->fdi_m_n, false, false);
7843
7844         ret = ilk_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7845         if (ret == -EDEADLK)
7846                 return ret;
7847
7848         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7849                 pipe_config->pipe_bpp -= 2*3;
7850                 drm_dbg_kms(&i915->drm,
7851                             "fdi link bw constraint, reducing pipe bpp to %i\n",
7852                             pipe_config->pipe_bpp);
7853                 needs_recompute = true;
7854                 pipe_config->bw_constrained = true;
7855
7856                 goto retry;
7857         }
7858
7859         if (needs_recompute)
7860                 return RETRY;
7861
7862         return ret;
7863 }
7864
7865 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
7866 {
7867         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
7868         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7869
7870         /* IPS only exists on ULT machines and is tied to pipe A. */
7871         if (!hsw_crtc_supports_ips(crtc))
7872                 return false;
7873
7874         if (!i915_modparams.enable_ips)
7875                 return false;
7876
7877         if (crtc_state->pipe_bpp > 24)
7878                 return false;
7879
7880         /*
7881          * We compare against max which means we must take
7882          * the increased cdclk requirement into account when
7883          * calculating the new cdclk.
7884          *
7885          * Should measure whether using a lower cdclk w/o IPS
7886          */
7887         if (IS_BROADWELL(dev_priv) &&
7888             crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
7889                 return false;
7890
7891         return true;
7892 }
7893
7894 static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
7895 {
7896         struct drm_i915_private *dev_priv =
7897                 to_i915(crtc_state->uapi.crtc->dev);
7898         struct intel_atomic_state *state =
7899                 to_intel_atomic_state(crtc_state->uapi.state);
7900
7901         crtc_state->ips_enabled = false;
7902
7903         if (!hsw_crtc_state_ips_capable(crtc_state))
7904                 return 0;
7905
7906         /*
7907          * When IPS gets enabled, the pipe CRC changes. Since IPS gets
7908          * enabled and disabled dynamically based on package C states,
7909          * user space can't make reliable use of the CRCs, so let's just
7910          * completely disable it.
7911          */
7912         if (crtc_state->crc_enabled)
7913                 return 0;
7914
7915         /* IPS should be fine as long as at least one plane is enabled. */
7916         if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
7917                 return 0;
7918
7919         if (IS_BROADWELL(dev_priv)) {
7920                 const struct intel_cdclk_state *cdclk_state;
7921
7922                 cdclk_state = intel_atomic_get_cdclk_state(state);
7923                 if (IS_ERR(cdclk_state))
7924                         return PTR_ERR(cdclk_state);
7925
7926                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
7927                 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
7928                         return 0;
7929         }
7930
7931         crtc_state->ips_enabled = true;
7932
7933         return 0;
7934 }
7935
7936 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7937 {
7938         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7939
7940         /* GDG double wide on either pipe, otherwise pipe A only */
7941         return INTEL_GEN(dev_priv) < 4 &&
7942                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7943 }
7944
7945 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
7946 {
7947         u32 pixel_rate;
7948
7949         pixel_rate = pipe_config->hw.adjusted_mode.crtc_clock;
7950
7951         /*
7952          * We only use IF-ID interlacing. If we ever use
7953          * PF-ID we'll need to adjust the pixel_rate here.
7954          */
7955
7956         if (pipe_config->pch_pfit.enabled) {
7957                 u64 pipe_w, pipe_h, pfit_w, pfit_h;
7958                 u32 pfit_size = pipe_config->pch_pfit.size;
7959
7960                 pipe_w = pipe_config->pipe_src_w;
7961                 pipe_h = pipe_config->pipe_src_h;
7962
7963                 pfit_w = (pfit_size >> 16) & 0xFFFF;
7964                 pfit_h = pfit_size & 0xFFFF;
7965                 if (pipe_w < pfit_w)
7966                         pipe_w = pfit_w;
7967                 if (pipe_h < pfit_h)
7968                         pipe_h = pfit_h;
7969
7970                 if (WARN_ON(!pfit_w || !pfit_h))
7971                         return pixel_rate;
7972
7973                 pixel_rate = div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
7974                                      pfit_w * pfit_h);
7975         }
7976
7977         return pixel_rate;
7978 }
7979
7980 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
7981 {
7982         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
7983
7984         if (HAS_GMCH(dev_priv))
7985                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
7986                 crtc_state->pixel_rate =
7987                         crtc_state->hw.adjusted_mode.crtc_clock;
7988         else
7989                 crtc_state->pixel_rate =
7990                         ilk_pipe_pixel_rate(crtc_state);
7991 }
7992
7993 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7994                                      struct intel_crtc_state *pipe_config)
7995 {
7996         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7997         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
7998         int clock_limit = dev_priv->max_dotclk_freq;
7999
8000         if (INTEL_GEN(dev_priv) < 4) {
8001                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
8002
8003                 /*
8004                  * Enable double wide mode when the dot clock
8005                  * is > 90% of the (display) core speed.
8006                  */
8007                 if (intel_crtc_supports_double_wide(crtc) &&
8008                     adjusted_mode->crtc_clock > clock_limit) {
8009                         clock_limit = dev_priv->max_dotclk_freq;
8010                         pipe_config->double_wide = true;
8011                 }
8012         }
8013
8014         if (adjusted_mode->crtc_clock > clock_limit) {
8015                 drm_dbg_kms(&dev_priv->drm,
8016                             "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
8017                             adjusted_mode->crtc_clock, clock_limit,
8018                             yesno(pipe_config->double_wide));
8019                 return -EINVAL;
8020         }
8021
8022         if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
8023              pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) &&
8024              pipe_config->hw.ctm) {
8025                 /*
8026                  * There is only one pipe CSC unit per pipe, and we need that
8027                  * for output conversion from RGB->YCBCR. So if CTM is already
8028                  * applied we can't support YCBCR420 output.
8029                  */
8030                 drm_dbg_kms(&dev_priv->drm,
8031                             "YCBCR420 and CTM together are not possible\n");
8032                 return -EINVAL;
8033         }
8034
8035         /*
8036          * Pipe horizontal size must be even in:
8037          * - DVO ganged mode
8038          * - LVDS dual channel mode
8039          * - Double wide pipe
8040          */
8041         if (pipe_config->pipe_src_w & 1) {
8042                 if (pipe_config->double_wide) {
8043                         drm_dbg_kms(&dev_priv->drm,
8044                                     "Odd pipe source width not supported with double wide pipe\n");
8045                         return -EINVAL;
8046                 }
8047
8048                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
8049                     intel_is_dual_link_lvds(dev_priv)) {
8050                         drm_dbg_kms(&dev_priv->drm,
8051                                     "Odd pipe source width not supported with dual link LVDS\n");
8052                         return -EINVAL;
8053                 }
8054         }
8055
8056         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
8057          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
8058          */
8059         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
8060                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
8061                 return -EINVAL;
8062
8063         intel_crtc_compute_pixel_rate(pipe_config);
8064
8065         if (pipe_config->has_pch_encoder)
8066                 return ilk_fdi_compute_config(crtc, pipe_config);
8067
8068         return 0;
8069 }
8070
8071 static void
8072 intel_reduce_m_n_ratio(u32 *num, u32 *den)
8073 {
8074         while (*num > DATA_LINK_M_N_MASK ||
8075                *den > DATA_LINK_M_N_MASK) {
8076                 *num >>= 1;
8077                 *den >>= 1;
8078         }
8079 }
8080
8081 static void compute_m_n(unsigned int m, unsigned int n,
8082                         u32 *ret_m, u32 *ret_n,
8083                         bool constant_n)
8084 {
8085         /*
8086          * Several DP dongles in particular seem to be fussy about
8087          * too large link M/N values. Give N value as 0x8000 that
8088          * should be acceptable by specific devices. 0x8000 is the
8089          * specified fixed N value for asynchronous clock mode,
8090          * which the devices expect also in synchronous clock mode.
8091          */
8092         if (constant_n)
8093                 *ret_n = 0x8000;
8094         else
8095                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
8096
8097         *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
8098         intel_reduce_m_n_ratio(ret_m, ret_n);
8099 }
8100
8101 void
8102 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
8103                        int pixel_clock, int link_clock,
8104                        struct intel_link_m_n *m_n,
8105                        bool constant_n, bool fec_enable)
8106 {
8107         u32 data_clock = bits_per_pixel * pixel_clock;
8108
8109         if (fec_enable)
8110                 data_clock = intel_dp_mode_to_fec_clock(data_clock);
8111
8112         m_n->tu = 64;
8113         compute_m_n(data_clock,
8114                     link_clock * nlanes * 8,
8115                     &m_n->gmch_m, &m_n->gmch_n,
8116                     constant_n);
8117
8118         compute_m_n(pixel_clock, link_clock,
8119                     &m_n->link_m, &m_n->link_n,
8120                     constant_n);
8121 }
8122
8123 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
8124 {
8125         /*
8126          * There may be no VBT; and if the BIOS enabled SSC we can
8127          * just keep using it to avoid unnecessary flicker.  Whereas if the
8128          * BIOS isn't using it, don't assume it will work even if the VBT
8129          * indicates as much.
8130          */
8131         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
8132                 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
8133                                                        PCH_DREF_CONTROL) &
8134                         DREF_SSC1_ENABLE;
8135
8136                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
8137                         drm_dbg_kms(&dev_priv->drm,
8138                                     "SSC %s by BIOS, overriding VBT which says %s\n",
8139                                     enableddisabled(bios_lvds_use_ssc),
8140                                     enableddisabled(dev_priv->vbt.lvds_use_ssc));
8141                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
8142                 }
8143         }
8144 }
8145
8146 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
8147 {
8148         if (i915_modparams.panel_use_ssc >= 0)
8149                 return i915_modparams.panel_use_ssc != 0;
8150         return dev_priv->vbt.lvds_use_ssc
8151                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
8152 }
8153
8154 static u32 pnv_dpll_compute_fp(struct dpll *dpll)
8155 {
8156         return (1 << dpll->n) << 16 | dpll->m2;
8157 }
8158
8159 static u32 i9xx_dpll_compute_fp(struct dpll *dpll)
8160 {
8161         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
8162 }
8163
8164 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
8165                                      struct intel_crtc_state *crtc_state,
8166                                      struct dpll *reduced_clock)
8167 {
8168         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8169         u32 fp, fp2 = 0;
8170
8171         if (IS_PINEVIEW(dev_priv)) {
8172                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
8173                 if (reduced_clock)
8174                         fp2 = pnv_dpll_compute_fp(reduced_clock);
8175         } else {
8176                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8177                 if (reduced_clock)
8178                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
8179         }
8180
8181         crtc_state->dpll_hw_state.fp0 = fp;
8182
8183         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8184             reduced_clock) {
8185                 crtc_state->dpll_hw_state.fp1 = fp2;
8186         } else {
8187                 crtc_state->dpll_hw_state.fp1 = fp;
8188         }
8189 }
8190
8191 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
8192                 pipe)
8193 {
8194         u32 reg_val;
8195
8196         /*
8197          * PLLB opamp always calibrates to max value of 0x3f, force enable it
8198          * and set it to a reasonable value instead.
8199          */
8200         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8201         reg_val &= 0xffffff00;
8202         reg_val |= 0x00000030;
8203         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8204
8205         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8206         reg_val &= 0x00ffffff;
8207         reg_val |= 0x8c000000;
8208         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8209
8210         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
8211         reg_val &= 0xffffff00;
8212         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
8213
8214         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
8215         reg_val &= 0x00ffffff;
8216         reg_val |= 0xb0000000;
8217         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
8218 }
8219
8220 static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
8221                                          const struct intel_link_m_n *m_n)
8222 {
8223         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8224         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8225         enum pipe pipe = crtc->pipe;
8226
8227         intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe),
8228                        TU_SIZE(m_n->tu) | m_n->gmch_m);
8229         intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
8230         intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);
8231         intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);
8232 }
8233
8234 static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
8235                                  enum transcoder transcoder)
8236 {
8237         if (IS_HASWELL(dev_priv))
8238                 return transcoder == TRANSCODER_EDP;
8239
8240         /*
8241          * Strictly speaking some registers are available before
8242          * gen7, but we only support DRRS on gen7+
8243          */
8244         return IS_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv);
8245 }
8246
8247 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
8248                                          const struct intel_link_m_n *m_n,
8249                                          const struct intel_link_m_n *m2_n2)
8250 {
8251         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8252         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8253         enum pipe pipe = crtc->pipe;
8254         enum transcoder transcoder = crtc_state->cpu_transcoder;
8255
8256         if (INTEL_GEN(dev_priv) >= 5) {
8257                 intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
8258                                TU_SIZE(m_n->tu) | m_n->gmch_m);
8259                 intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
8260                                m_n->gmch_n);
8261                 intel_de_write(dev_priv, PIPE_LINK_M1(transcoder),
8262                                m_n->link_m);
8263                 intel_de_write(dev_priv, PIPE_LINK_N1(transcoder),
8264                                m_n->link_n);
8265                 /*
8266                  *  M2_N2 registers are set only if DRRS is supported
8267                  * (to make sure the registers are not unnecessarily accessed).
8268                  */
8269                 if (m2_n2 && crtc_state->has_drrs &&
8270                     transcoder_has_m2_n2(dev_priv, transcoder)) {
8271                         intel_de_write(dev_priv, PIPE_DATA_M2(transcoder),
8272                                        TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
8273                         intel_de_write(dev_priv, PIPE_DATA_N2(transcoder),
8274                                        m2_n2->gmch_n);
8275                         intel_de_write(dev_priv, PIPE_LINK_M2(transcoder),
8276                                        m2_n2->link_m);
8277                         intel_de_write(dev_priv, PIPE_LINK_N2(transcoder),
8278                                        m2_n2->link_n);
8279                 }
8280         } else {
8281                 intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe),
8282                                TU_SIZE(m_n->tu) | m_n->gmch_m);
8283                 intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
8284                 intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);
8285                 intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);
8286         }
8287 }
8288
8289 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)
8290 {
8291         const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
8292         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
8293
8294         if (m_n == M1_N1) {
8295                 dp_m_n = &crtc_state->dp_m_n;
8296                 dp_m2_n2 = &crtc_state->dp_m2_n2;
8297         } else if (m_n == M2_N2) {
8298
8299                 /*
8300                  * M2_N2 registers are not supported. Hence m2_n2 divider value
8301                  * needs to be programmed into M1_N1.
8302                  */
8303                 dp_m_n = &crtc_state->dp_m2_n2;
8304         } else {
8305                 drm_err(&i915->drm, "Unsupported divider value\n");
8306                 return;
8307         }
8308
8309         if (crtc_state->has_pch_encoder)
8310                 intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);
8311         else
8312                 intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);
8313 }
8314
8315 static void vlv_compute_dpll(struct intel_crtc *crtc,
8316                              struct intel_crtc_state *pipe_config)
8317 {
8318         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
8319                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
8320         if (crtc->pipe != PIPE_A)
8321                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
8322
8323         /* DPLL not used with DSI, but still need the rest set up */
8324         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
8325                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
8326                         DPLL_EXT_BUFFER_ENABLE_VLV;
8327
8328         pipe_config->dpll_hw_state.dpll_md =
8329                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8330 }
8331
8332 static void chv_compute_dpll(struct intel_crtc *crtc,
8333                              struct intel_crtc_state *pipe_config)
8334 {
8335         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
8336                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
8337         if (crtc->pipe != PIPE_A)
8338                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
8339
8340         /* DPLL not used with DSI, but still need the rest set up */
8341         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
8342                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
8343
8344         pipe_config->dpll_hw_state.dpll_md =
8345                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8346 }
8347
8348 static void vlv_prepare_pll(struct intel_crtc *crtc,
8349                             const struct intel_crtc_state *pipe_config)
8350 {
8351         struct drm_device *dev = crtc->base.dev;
8352         struct drm_i915_private *dev_priv = to_i915(dev);
8353         enum pipe pipe = crtc->pipe;
8354         u32 mdiv;
8355         u32 bestn, bestm1, bestm2, bestp1, bestp2;
8356         u32 coreclk, reg_val;
8357
8358         /* Enable Refclk */
8359         intel_de_write(dev_priv, DPLL(pipe),
8360                        pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
8361
8362         /* No need to actually set up the DPLL with DSI */
8363         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8364                 return;
8365
8366         vlv_dpio_get(dev_priv);
8367
8368         bestn = pipe_config->dpll.n;
8369         bestm1 = pipe_config->dpll.m1;
8370         bestm2 = pipe_config->dpll.m2;
8371         bestp1 = pipe_config->dpll.p1;
8372         bestp2 = pipe_config->dpll.p2;
8373
8374         /* See eDP HDMI DPIO driver vbios notes doc */
8375
8376         /* PLL B needs special handling */
8377         if (pipe == PIPE_B)
8378                 vlv_pllb_recal_opamp(dev_priv, pipe);
8379
8380         /* Set up Tx target for periodic Rcomp update */
8381         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
8382
8383         /* Disable target IRef on PLL */
8384         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
8385         reg_val &= 0x00ffffff;
8386         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
8387
8388         /* Disable fast lock */
8389         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
8390
8391         /* Set idtafcrecal before PLL is enabled */
8392         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
8393         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
8394         mdiv |= ((bestn << DPIO_N_SHIFT));
8395         mdiv |= (1 << DPIO_K_SHIFT);
8396
8397         /*
8398          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
8399          * but we don't support that).
8400          * Note: don't use the DAC post divider as it seems unstable.
8401          */
8402         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
8403         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8404
8405         mdiv |= DPIO_ENABLE_CALIBRATION;
8406         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
8407
8408         /* Set HBR and RBR LPF coefficients */
8409         if (pipe_config->port_clock == 162000 ||
8410             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) ||
8411             intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
8412                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8413                                  0x009f0003);
8414         else
8415                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
8416                                  0x00d0000f);
8417
8418         if (intel_crtc_has_dp_encoder(pipe_config)) {
8419                 /* Use SSC source */
8420                 if (pipe == PIPE_A)
8421                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8422                                          0x0df40000);
8423                 else
8424                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8425                                          0x0df70000);
8426         } else { /* HDMI or VGA */
8427                 /* Use bend source */
8428                 if (pipe == PIPE_A)
8429                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8430                                          0x0df70000);
8431                 else
8432                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
8433                                          0x0df40000);
8434         }
8435
8436         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
8437         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
8438         if (intel_crtc_has_dp_encoder(pipe_config))
8439                 coreclk |= 0x01000000;
8440         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
8441
8442         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
8443
8444         vlv_dpio_put(dev_priv);
8445 }
8446
8447 static void chv_prepare_pll(struct intel_crtc *crtc,
8448                             const struct intel_crtc_state *pipe_config)
8449 {
8450         struct drm_device *dev = crtc->base.dev;
8451         struct drm_i915_private *dev_priv = to_i915(dev);
8452         enum pipe pipe = crtc->pipe;
8453         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8454         u32 loopfilter, tribuf_calcntr;
8455         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
8456         u32 dpio_val;
8457         int vco;
8458
8459         /* Enable Refclk and SSC */
8460         intel_de_write(dev_priv, DPLL(pipe),
8461                        pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
8462
8463         /* No need to actually set up the DPLL with DSI */
8464         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8465                 return;
8466
8467         bestn = pipe_config->dpll.n;
8468         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
8469         bestm1 = pipe_config->dpll.m1;
8470         bestm2 = pipe_config->dpll.m2 >> 22;
8471         bestp1 = pipe_config->dpll.p1;
8472         bestp2 = pipe_config->dpll.p2;
8473         vco = pipe_config->dpll.vco;
8474         dpio_val = 0;
8475         loopfilter = 0;
8476
8477         vlv_dpio_get(dev_priv);
8478
8479         /* p1 and p2 divider */
8480         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8481                         5 << DPIO_CHV_S1_DIV_SHIFT |
8482                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8483                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8484                         1 << DPIO_CHV_K_DIV_SHIFT);
8485
8486         /* Feedback post-divider - m2 */
8487         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8488
8489         /* Feedback refclk divider - n and m1 */
8490         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8491                         DPIO_CHV_M1_DIV_BY_2 |
8492                         1 << DPIO_CHV_N_DIV_SHIFT);
8493
8494         /* M2 fraction division */
8495         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8496
8497         /* M2 fraction division enable */
8498         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8499         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8500         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8501         if (bestm2_frac)
8502                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8503         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8504
8505         /* Program digital lock detect threshold */
8506         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8507         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8508                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8509         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8510         if (!bestm2_frac)
8511                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8512         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8513
8514         /* Loop filter */
8515         if (vco == 5400000) {
8516                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8517                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8518                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8519                 tribuf_calcntr = 0x9;
8520         } else if (vco <= 6200000) {
8521                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8522                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8523                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8524                 tribuf_calcntr = 0x9;
8525         } else if (vco <= 6480000) {
8526                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8527                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8528                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8529                 tribuf_calcntr = 0x8;
8530         } else {
8531                 /* Not supported. Apply the same limits as in the max case */
8532                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8533                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8534                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8535                 tribuf_calcntr = 0;
8536         }
8537         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8538
8539         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8540         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8541         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8542         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8543
8544         /* AFC Recal */
8545         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8546                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8547                         DPIO_AFC_RECAL);
8548
8549         vlv_dpio_put(dev_priv);
8550 }
8551
8552 /**
8553  * vlv_force_pll_on - forcibly enable just the PLL
8554  * @dev_priv: i915 private structure
8555  * @pipe: pipe PLL to enable
8556  * @dpll: PLL configuration
8557  *
8558  * Enable the PLL for @pipe using the supplied @dpll config. To be used
8559  * in cases where we need the PLL enabled even when @pipe is not going to
8560  * be enabled.
8561  */
8562 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
8563                      const struct dpll *dpll)
8564 {
8565         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
8566         struct intel_crtc_state *pipe_config;
8567
8568         pipe_config = intel_crtc_state_alloc(crtc);
8569         if (!pipe_config)
8570                 return -ENOMEM;
8571
8572         pipe_config->cpu_transcoder = (enum transcoder)pipe;
8573         pipe_config->pixel_multiplier = 1;
8574         pipe_config->dpll = *dpll;
8575
8576         if (IS_CHERRYVIEW(dev_priv)) {
8577                 chv_compute_dpll(crtc, pipe_config);
8578                 chv_prepare_pll(crtc, pipe_config);
8579                 chv_enable_pll(crtc, pipe_config);
8580         } else {
8581                 vlv_compute_dpll(crtc, pipe_config);
8582                 vlv_prepare_pll(crtc, pipe_config);
8583                 vlv_enable_pll(crtc, pipe_config);
8584         }
8585
8586         kfree(pipe_config);
8587
8588         return 0;
8589 }
8590
8591 /**
8592  * vlv_force_pll_off - forcibly disable just the PLL
8593  * @dev_priv: i915 private structure
8594  * @pipe: pipe PLL to disable
8595  *
8596  * Disable the PLL for @pipe. To be used in cases where we need
8597  * the PLL enabled even when @pipe is not going to be enabled.
8598  */
8599 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
8600 {
8601         if (IS_CHERRYVIEW(dev_priv))
8602                 chv_disable_pll(dev_priv, pipe);
8603         else
8604                 vlv_disable_pll(dev_priv, pipe);
8605 }
8606
8607 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8608                               struct intel_crtc_state *crtc_state,
8609                               struct dpll *reduced_clock)
8610 {
8611         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8612         u32 dpll;
8613         struct dpll *clock = &crtc_state->dpll;
8614
8615         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8616
8617         dpll = DPLL_VGA_MODE_DIS;
8618
8619         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8620                 dpll |= DPLLB_MODE_LVDS;
8621         else
8622                 dpll |= DPLLB_MODE_DAC_SERIAL;
8623
8624         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
8625             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
8626                 dpll |= (crtc_state->pixel_multiplier - 1)
8627                         << SDVO_MULTIPLIER_SHIFT_HIRES;
8628         }
8629
8630         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8631             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8632                 dpll |= DPLL_SDVO_HIGH_SPEED;
8633
8634         if (intel_crtc_has_dp_encoder(crtc_state))
8635                 dpll |= DPLL_SDVO_HIGH_SPEED;
8636
8637         /* compute bitmask from p1 value */
8638         if (IS_PINEVIEW(dev_priv))
8639                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8640         else {
8641                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8642                 if (IS_G4X(dev_priv) && reduced_clock)
8643                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8644         }
8645         switch (clock->p2) {
8646         case 5:
8647                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8648                 break;
8649         case 7:
8650                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8651                 break;
8652         case 10:
8653                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8654                 break;
8655         case 14:
8656                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8657                 break;
8658         }
8659         if (INTEL_GEN(dev_priv) >= 4)
8660                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8661
8662         if (crtc_state->sdvo_tv_clock)
8663                 dpll |= PLL_REF_INPUT_TVCLKINBC;
8664         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8665                  intel_panel_use_ssc(dev_priv))
8666                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8667         else
8668                 dpll |= PLL_REF_INPUT_DREFCLK;
8669
8670         dpll |= DPLL_VCO_ENABLE;
8671         crtc_state->dpll_hw_state.dpll = dpll;
8672
8673         if (INTEL_GEN(dev_priv) >= 4) {
8674                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8675                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8676                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8677         }
8678 }
8679
8680 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8681                               struct intel_crtc_state *crtc_state,
8682                               struct dpll *reduced_clock)
8683 {
8684         struct drm_device *dev = crtc->base.dev;
8685         struct drm_i915_private *dev_priv = to_i915(dev);
8686         u32 dpll;
8687         struct dpll *clock = &crtc_state->dpll;
8688
8689         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8690
8691         dpll = DPLL_VGA_MODE_DIS;
8692
8693         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8694                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8695         } else {
8696                 if (clock->p1 == 2)
8697                         dpll |= PLL_P1_DIVIDE_BY_TWO;
8698                 else
8699                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8700                 if (clock->p2 == 4)
8701                         dpll |= PLL_P2_DIVIDE_BY_4;
8702         }
8703
8704         /*
8705          * Bspec:
8706          * "[Almador Errata}: For the correct operation of the muxed DVO pins
8707          *  (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
8708          *  GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
8709          *  Enable) must be set to “1” in both the DPLL A Control Register
8710          *  (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
8711          *
8712          * For simplicity We simply keep both bits always enabled in
8713          * both DPLLS. The spec says we should disable the DVO 2X clock
8714          * when not needed, but this seems to work fine in practice.
8715          */
8716         if (IS_I830(dev_priv) ||
8717             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8718                 dpll |= DPLL_DVO_2X_MODE;
8719
8720         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8721             intel_panel_use_ssc(dev_priv))
8722                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8723         else
8724                 dpll |= PLL_REF_INPUT_DREFCLK;
8725
8726         dpll |= DPLL_VCO_ENABLE;
8727         crtc_state->dpll_hw_state.dpll = dpll;
8728 }
8729
8730 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
8731 {
8732         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8733         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8734         enum pipe pipe = crtc->pipe;
8735         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8736         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
8737         u32 crtc_vtotal, crtc_vblank_end;
8738         int vsyncshift = 0;
8739
8740         /* We need to be careful not to changed the adjusted mode, for otherwise
8741          * the hw state checker will get angry at the mismatch. */
8742         crtc_vtotal = adjusted_mode->crtc_vtotal;
8743         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8744
8745         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8746                 /* the chip adds 2 halflines automatically */
8747                 crtc_vtotal -= 1;
8748                 crtc_vblank_end -= 1;
8749
8750                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8751                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8752                 else
8753                         vsyncshift = adjusted_mode->crtc_hsync_start -
8754                                 adjusted_mode->crtc_htotal / 2;
8755                 if (vsyncshift < 0)
8756                         vsyncshift += adjusted_mode->crtc_htotal;
8757         }
8758
8759         if (INTEL_GEN(dev_priv) > 3)
8760                 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
8761                                vsyncshift);
8762
8763         intel_de_write(dev_priv, HTOTAL(cpu_transcoder),
8764                        (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
8765         intel_de_write(dev_priv, HBLANK(cpu_transcoder),
8766                        (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
8767         intel_de_write(dev_priv, HSYNC(cpu_transcoder),
8768                        (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
8769
8770         intel_de_write(dev_priv, VTOTAL(cpu_transcoder),
8771                        (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
8772         intel_de_write(dev_priv, VBLANK(cpu_transcoder),
8773                        (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
8774         intel_de_write(dev_priv, VSYNC(cpu_transcoder),
8775                        (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
8776
8777         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8778          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8779          * documented on the DDI_FUNC_CTL register description, EDP Input Select
8780          * bits. */
8781         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
8782             (pipe == PIPE_B || pipe == PIPE_C))
8783                 intel_de_write(dev_priv, VTOTAL(pipe),
8784                                intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
8785
8786 }
8787
8788 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
8789 {
8790         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8791         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8792         enum pipe pipe = crtc->pipe;
8793
8794         /* pipesrc controls the size that is scaled from, which should
8795          * always be the user's requested size.
8796          */
8797         intel_de_write(dev_priv, PIPESRC(pipe),
8798                        ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1));
8799 }
8800
8801 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
8802 {
8803         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
8804         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
8805
8806         if (IS_GEN(dev_priv, 2))
8807                 return false;
8808
8809         if (INTEL_GEN(dev_priv) >= 9 ||
8810             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
8811                 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
8812         else
8813                 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
8814 }
8815
8816 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8817                                    struct intel_crtc_state *pipe_config)
8818 {
8819         struct drm_device *dev = crtc->base.dev;
8820         struct drm_i915_private *dev_priv = to_i915(dev);
8821         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8822         u32 tmp;
8823
8824         tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));
8825         pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8826         pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8827
8828         if (!transcoder_is_dsi(cpu_transcoder)) {
8829                 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));
8830                 pipe_config->hw.adjusted_mode.crtc_hblank_start =
8831                                                         (tmp & 0xffff) + 1;
8832                 pipe_config->hw.adjusted_mode.crtc_hblank_end =
8833                                                 ((tmp >> 16) & 0xffff) + 1;
8834         }
8835         tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));
8836         pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8837         pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8838
8839         tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));
8840         pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8841         pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8842
8843         if (!transcoder_is_dsi(cpu_transcoder)) {
8844                 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));
8845                 pipe_config->hw.adjusted_mode.crtc_vblank_start =
8846                                                         (tmp & 0xffff) + 1;
8847                 pipe_config->hw.adjusted_mode.crtc_vblank_end =
8848                                                 ((tmp >> 16) & 0xffff) + 1;
8849         }
8850         tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));
8851         pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8852         pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8853
8854         if (intel_pipe_is_interlaced(pipe_config)) {
8855                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8856                 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
8857                 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
8858         }
8859 }
8860
8861 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8862                                     struct intel_crtc_state *pipe_config)
8863 {
8864         struct drm_device *dev = crtc->base.dev;
8865         struct drm_i915_private *dev_priv = to_i915(dev);
8866         u32 tmp;
8867
8868         tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
8869         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8870         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8871
8872         pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h;
8873         pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w;
8874 }
8875
8876 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8877                                  struct intel_crtc_state *pipe_config)
8878 {
8879         mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay;
8880         mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal;
8881         mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start;
8882         mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end;
8883
8884         mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay;
8885         mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal;
8886         mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start;
8887         mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end;
8888
8889         mode->flags = pipe_config->hw.adjusted_mode.flags;
8890         mode->type = DRM_MODE_TYPE_DRIVER;
8891
8892         mode->clock = pipe_config->hw.adjusted_mode.crtc_clock;
8893
8894         mode->hsync = drm_mode_hsync(mode);
8895         mode->vrefresh = drm_mode_vrefresh(mode);
8896         drm_mode_set_name(mode);
8897 }
8898
8899 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
8900 {
8901         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
8902         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8903         u32 pipeconf;
8904
8905         pipeconf = 0;
8906
8907         /* we keep both pipes enabled on 830 */
8908         if (IS_I830(dev_priv))
8909                 pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE;
8910
8911         if (crtc_state->double_wide)
8912                 pipeconf |= PIPECONF_DOUBLE_WIDE;
8913
8914         /* only g4x and later have fancy bpc/dither controls */
8915         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
8916             IS_CHERRYVIEW(dev_priv)) {
8917                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8918                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
8919                         pipeconf |= PIPECONF_DITHER_EN |
8920                                     PIPECONF_DITHER_TYPE_SP;
8921
8922                 switch (crtc_state->pipe_bpp) {
8923                 case 18:
8924                         pipeconf |= PIPECONF_6BPC;
8925                         break;
8926                 case 24:
8927                         pipeconf |= PIPECONF_8BPC;
8928                         break;
8929                 case 30:
8930                         pipeconf |= PIPECONF_10BPC;
8931                         break;
8932                 default:
8933                         /* Case prevented by intel_choose_pipe_bpp_dither. */
8934                         BUG();
8935                 }
8936         }
8937
8938         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8939                 if (INTEL_GEN(dev_priv) < 4 ||
8940                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
8941                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8942                 else
8943                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8944         } else {
8945                 pipeconf |= PIPECONF_PROGRESSIVE;
8946         }
8947
8948         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
8949              crtc_state->limited_color_range)
8950                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8951
8952         pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
8953
8954         pipeconf |= PIPECONF_FRAME_START_DELAY(0);
8955
8956         intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
8957         intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
8958 }
8959
8960 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8961                                    struct intel_crtc_state *crtc_state)
8962 {
8963         struct drm_device *dev = crtc->base.dev;
8964         struct drm_i915_private *dev_priv = to_i915(dev);
8965         const struct intel_limit *limit;
8966         int refclk = 48000;
8967
8968         memset(&crtc_state->dpll_hw_state, 0,
8969                sizeof(crtc_state->dpll_hw_state));
8970
8971         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8972                 if (intel_panel_use_ssc(dev_priv)) {
8973                         refclk = dev_priv->vbt.lvds_ssc_freq;
8974                         drm_dbg_kms(&dev_priv->drm,
8975                                     "using SSC reference clock of %d kHz\n",
8976                                     refclk);
8977                 }
8978
8979                 limit = &intel_limits_i8xx_lvds;
8980         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8981                 limit = &intel_limits_i8xx_dvo;
8982         } else {
8983                 limit = &intel_limits_i8xx_dac;
8984         }
8985
8986         if (!crtc_state->clock_set &&
8987             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8988                                  refclk, NULL, &crtc_state->dpll)) {
8989                 drm_err(&dev_priv->drm,
8990                         "Couldn't find PLL settings for mode!\n");
8991                 return -EINVAL;
8992         }
8993
8994         i8xx_compute_dpll(crtc, crtc_state, NULL);
8995
8996         return 0;
8997 }
8998
8999 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
9000                                   struct intel_crtc_state *crtc_state)
9001 {
9002         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9003         const struct intel_limit *limit;
9004         int refclk = 96000;
9005
9006         memset(&crtc_state->dpll_hw_state, 0,
9007                sizeof(crtc_state->dpll_hw_state));
9008
9009         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9010                 if (intel_panel_use_ssc(dev_priv)) {
9011                         refclk = dev_priv->vbt.lvds_ssc_freq;
9012                         drm_dbg_kms(&dev_priv->drm,
9013                                     "using SSC reference clock of %d kHz\n",
9014                                     refclk);
9015                 }
9016
9017                 if (intel_is_dual_link_lvds(dev_priv))
9018                         limit = &intel_limits_g4x_dual_channel_lvds;
9019                 else
9020                         limit = &intel_limits_g4x_single_channel_lvds;
9021         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
9022                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
9023                 limit = &intel_limits_g4x_hdmi;
9024         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
9025                 limit = &intel_limits_g4x_sdvo;
9026         } else {
9027                 /* The option is for other outputs */
9028                 limit = &intel_limits_i9xx_sdvo;
9029         }
9030
9031         if (!crtc_state->clock_set &&
9032             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9033                                 refclk, NULL, &crtc_state->dpll)) {
9034                 drm_err(&dev_priv->drm,
9035                         "Couldn't find PLL settings for mode!\n");
9036                 return -EINVAL;
9037         }
9038
9039         i9xx_compute_dpll(crtc, crtc_state, NULL);
9040
9041         return 0;
9042 }
9043
9044 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
9045                                   struct intel_crtc_state *crtc_state)
9046 {
9047         struct drm_device *dev = crtc->base.dev;
9048         struct drm_i915_private *dev_priv = to_i915(dev);
9049         const struct intel_limit *limit;
9050         int refclk = 96000;
9051
9052         memset(&crtc_state->dpll_hw_state, 0,
9053                sizeof(crtc_state->dpll_hw_state));
9054
9055         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9056                 if (intel_panel_use_ssc(dev_priv)) {
9057                         refclk = dev_priv->vbt.lvds_ssc_freq;
9058                         drm_dbg_kms(&dev_priv->drm,
9059                                     "using SSC reference clock of %d kHz\n",
9060                                     refclk);
9061                 }
9062
9063                 limit = &pnv_limits_lvds;
9064         } else {
9065                 limit = &pnv_limits_sdvo;
9066         }
9067
9068         if (!crtc_state->clock_set &&
9069             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9070                                 refclk, NULL, &crtc_state->dpll)) {
9071                 drm_err(&dev_priv->drm,
9072                         "Couldn't find PLL settings for mode!\n");
9073                 return -EINVAL;
9074         }
9075
9076         i9xx_compute_dpll(crtc, crtc_state, NULL);
9077
9078         return 0;
9079 }
9080
9081 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
9082                                    struct intel_crtc_state *crtc_state)
9083 {
9084         struct drm_device *dev = crtc->base.dev;
9085         struct drm_i915_private *dev_priv = to_i915(dev);
9086         const struct intel_limit *limit;
9087         int refclk = 96000;
9088
9089         memset(&crtc_state->dpll_hw_state, 0,
9090                sizeof(crtc_state->dpll_hw_state));
9091
9092         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9093                 if (intel_panel_use_ssc(dev_priv)) {
9094                         refclk = dev_priv->vbt.lvds_ssc_freq;
9095                         drm_dbg_kms(&dev_priv->drm,
9096                                     "using SSC reference clock of %d kHz\n",
9097                                     refclk);
9098                 }
9099
9100                 limit = &intel_limits_i9xx_lvds;
9101         } else {
9102                 limit = &intel_limits_i9xx_sdvo;
9103         }
9104
9105         if (!crtc_state->clock_set &&
9106             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9107                                  refclk, NULL, &crtc_state->dpll)) {
9108                 drm_err(&dev_priv->drm,
9109                         "Couldn't find PLL settings for mode!\n");
9110                 return -EINVAL;
9111         }
9112
9113         i9xx_compute_dpll(crtc, crtc_state, NULL);
9114
9115         return 0;
9116 }
9117
9118 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
9119                                   struct intel_crtc_state *crtc_state)
9120 {
9121         int refclk = 100000;
9122         const struct intel_limit *limit = &intel_limits_chv;
9123         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
9124
9125         memset(&crtc_state->dpll_hw_state, 0,
9126                sizeof(crtc_state->dpll_hw_state));
9127
9128         if (!crtc_state->clock_set &&
9129             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9130                                 refclk, NULL, &crtc_state->dpll)) {
9131                 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
9132                 return -EINVAL;
9133         }
9134
9135         chv_compute_dpll(crtc, crtc_state);
9136
9137         return 0;
9138 }
9139
9140 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
9141                                   struct intel_crtc_state *crtc_state)
9142 {
9143         int refclk = 100000;
9144         const struct intel_limit *limit = &intel_limits_vlv;
9145         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
9146
9147         memset(&crtc_state->dpll_hw_state, 0,
9148                sizeof(crtc_state->dpll_hw_state));
9149
9150         if (!crtc_state->clock_set &&
9151             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9152                                 refclk, NULL, &crtc_state->dpll)) {
9153                 drm_err(&i915->drm,  "Couldn't find PLL settings for mode!\n");
9154                 return -EINVAL;
9155         }
9156
9157         vlv_compute_dpll(crtc, crtc_state);
9158
9159         return 0;
9160 }
9161
9162 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
9163 {
9164         if (IS_I830(dev_priv))
9165                 return false;
9166
9167         return INTEL_GEN(dev_priv) >= 4 ||
9168                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
9169 }
9170
9171 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
9172                                  struct intel_crtc_state *pipe_config)
9173 {
9174         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9175         u32 tmp;
9176
9177         if (!i9xx_has_pfit(dev_priv))
9178                 return;
9179
9180         tmp = intel_de_read(dev_priv, PFIT_CONTROL);
9181         if (!(tmp & PFIT_ENABLE))
9182                 return;
9183
9184         /* Check whether the pfit is attached to our pipe. */
9185         if (INTEL_GEN(dev_priv) < 4) {
9186                 if (crtc->pipe != PIPE_B)
9187                         return;
9188         } else {
9189                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
9190                         return;
9191         }
9192
9193         pipe_config->gmch_pfit.control = tmp;
9194         pipe_config->gmch_pfit.pgm_ratios = intel_de_read(dev_priv,
9195                                                           PFIT_PGM_RATIOS);
9196 }
9197
9198 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
9199                                struct intel_crtc_state *pipe_config)
9200 {
9201         struct drm_device *dev = crtc->base.dev;
9202         struct drm_i915_private *dev_priv = to_i915(dev);
9203         enum pipe pipe = crtc->pipe;
9204         struct dpll clock;
9205         u32 mdiv;
9206         int refclk = 100000;
9207
9208         /* In case of DSI, DPLL will not be used */
9209         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
9210                 return;
9211
9212         vlv_dpio_get(dev_priv);
9213         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
9214         vlv_dpio_put(dev_priv);
9215
9216         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
9217         clock.m2 = mdiv & DPIO_M2DIV_MASK;
9218         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
9219         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
9220         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
9221
9222         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
9223 }
9224
9225 static void
9226 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
9227                               struct intel_initial_plane_config *plane_config)
9228 {
9229         struct drm_device *dev = crtc->base.dev;
9230         struct drm_i915_private *dev_priv = to_i915(dev);
9231         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9232         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
9233         enum pipe pipe;
9234         u32 val, base, offset;
9235         int fourcc, pixel_format;
9236         unsigned int aligned_height;
9237         struct drm_framebuffer *fb;
9238         struct intel_framebuffer *intel_fb;
9239
9240         if (!plane->get_hw_state(plane, &pipe))
9241                 return;
9242
9243         drm_WARN_ON(dev, pipe != crtc->pipe);
9244
9245         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9246         if (!intel_fb) {
9247                 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
9248                 return;
9249         }
9250
9251         fb = &intel_fb->base;
9252
9253         fb->dev = dev;
9254
9255         val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
9256
9257         if (INTEL_GEN(dev_priv) >= 4) {
9258                 if (val & DISPPLANE_TILED) {
9259                         plane_config->tiling = I915_TILING_X;
9260                         fb->modifier = I915_FORMAT_MOD_X_TILED;
9261                 }
9262
9263                 if (val & DISPPLANE_ROTATE_180)
9264                         plane_config->rotation = DRM_MODE_ROTATE_180;
9265         }
9266
9267         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
9268             val & DISPPLANE_MIRROR)
9269                 plane_config->rotation |= DRM_MODE_REFLECT_X;
9270
9271         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9272         fourcc = i9xx_format_to_fourcc(pixel_format);
9273         fb->format = drm_format_info(fourcc);
9274
9275         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
9276                 offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
9277                 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
9278         } else if (INTEL_GEN(dev_priv) >= 4) {
9279                 if (plane_config->tiling)
9280                         offset = intel_de_read(dev_priv,
9281                                                DSPTILEOFF(i9xx_plane));
9282                 else
9283                         offset = intel_de_read(dev_priv,
9284                                                DSPLINOFF(i9xx_plane));
9285                 base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
9286         } else {
9287                 base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
9288         }
9289         plane_config->base = base;
9290
9291         val = intel_de_read(dev_priv, PIPESRC(pipe));
9292         fb->width = ((val >> 16) & 0xfff) + 1;
9293         fb->height = ((val >> 0) & 0xfff) + 1;
9294
9295         val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
9296         fb->pitches[0] = val & 0xffffffc0;
9297
9298         aligned_height = intel_fb_align_height(fb, 0, fb->height);
9299
9300         plane_config->size = fb->pitches[0] * aligned_height;
9301
9302         drm_dbg_kms(&dev_priv->drm,
9303                     "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9304                     crtc->base.name, plane->base.name, fb->width, fb->height,
9305                     fb->format->cpp[0] * 8, base, fb->pitches[0],
9306                     plane_config->size);
9307
9308         plane_config->fb = intel_fb;
9309 }
9310
9311 static void chv_crtc_clock_get(struct intel_crtc *crtc,
9312                                struct intel_crtc_state *pipe_config)
9313 {
9314         struct drm_device *dev = crtc->base.dev;
9315         struct drm_i915_private *dev_priv = to_i915(dev);
9316         enum pipe pipe = crtc->pipe;
9317         enum dpio_channel port = vlv_pipe_to_channel(pipe);
9318         struct dpll clock;
9319         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
9320         int refclk = 100000;
9321
9322         /* In case of DSI, DPLL will not be used */
9323         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
9324                 return;
9325
9326         vlv_dpio_get(dev_priv);
9327         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
9328         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
9329         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
9330         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
9331         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
9332         vlv_dpio_put(dev_priv);
9333
9334         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
9335         clock.m2 = (pll_dw0 & 0xff) << 22;
9336         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
9337                 clock.m2 |= pll_dw2 & 0x3fffff;
9338         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
9339         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
9340         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
9341
9342         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
9343 }
9344
9345 static enum intel_output_format
9346 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
9347 {
9348         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9349         u32 tmp;
9350
9351         tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
9352
9353         if (tmp & PIPEMISC_YUV420_ENABLE) {
9354                 /* We support 4:2:0 in full blend mode only */
9355                 drm_WARN_ON(&dev_priv->drm,
9356                             (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
9357
9358                 return INTEL_OUTPUT_FORMAT_YCBCR420;
9359         } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
9360                 return INTEL_OUTPUT_FORMAT_YCBCR444;
9361         } else {
9362                 return INTEL_OUTPUT_FORMAT_RGB;
9363         }
9364 }
9365
9366 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
9367 {
9368         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9369         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
9370         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9371         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
9372         u32 tmp;
9373
9374         tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
9375
9376         if (tmp & DISPPLANE_GAMMA_ENABLE)
9377                 crtc_state->gamma_enable = true;
9378
9379         if (!HAS_GMCH(dev_priv) &&
9380             tmp & DISPPLANE_PIPE_CSC_ENABLE)
9381                 crtc_state->csc_enable = true;
9382 }
9383
9384 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
9385                                  struct intel_crtc_state *pipe_config)
9386 {
9387         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9388         enum intel_display_power_domain power_domain;
9389         intel_wakeref_t wakeref;
9390         u32 tmp;
9391         bool ret;
9392
9393         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9394         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
9395         if (!wakeref)
9396                 return false;
9397
9398         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
9399         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9400         pipe_config->shared_dpll = NULL;
9401         pipe_config->master_transcoder = INVALID_TRANSCODER;
9402
9403         ret = false;
9404
9405         tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
9406         if (!(tmp & PIPECONF_ENABLE))
9407                 goto out;
9408
9409         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
9410             IS_CHERRYVIEW(dev_priv)) {
9411                 switch (tmp & PIPECONF_BPC_MASK) {
9412                 case PIPECONF_6BPC:
9413                         pipe_config->pipe_bpp = 18;
9414                         break;
9415                 case PIPECONF_8BPC:
9416                         pipe_config->pipe_bpp = 24;
9417                         break;
9418                 case PIPECONF_10BPC:
9419                         pipe_config->pipe_bpp = 30;
9420                         break;
9421                 default:
9422                         break;
9423                 }
9424         }
9425
9426         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9427             (tmp & PIPECONF_COLOR_RANGE_SELECT))
9428                 pipe_config->limited_color_range = true;
9429
9430         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
9431                 PIPECONF_GAMMA_MODE_SHIFT;
9432
9433         if (IS_CHERRYVIEW(dev_priv))
9434                 pipe_config->cgm_mode = intel_de_read(dev_priv,
9435                                                       CGM_PIPE_MODE(crtc->pipe));
9436
9437         i9xx_get_pipe_color_config(pipe_config);
9438         intel_color_get_config(pipe_config);
9439
9440         if (INTEL_GEN(dev_priv) < 4)
9441                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
9442
9443         intel_get_pipe_timings(crtc, pipe_config);
9444         intel_get_pipe_src_size(crtc, pipe_config);
9445
9446         i9xx_get_pfit_config(crtc, pipe_config);
9447
9448         if (INTEL_GEN(dev_priv) >= 4) {
9449                 /* No way to read it out on pipes B and C */
9450                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
9451                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
9452                 else
9453                         tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
9454                 pipe_config->pixel_multiplier =
9455                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
9456                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
9457                 pipe_config->dpll_hw_state.dpll_md = tmp;
9458         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
9459                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
9460                 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
9461                 pipe_config->pixel_multiplier =
9462                         ((tmp & SDVO_MULTIPLIER_MASK)
9463                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
9464         } else {
9465                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
9466                  * port and will be fixed up in the encoder->get_config
9467                  * function. */
9468                 pipe_config->pixel_multiplier = 1;
9469         }
9470         pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
9471                                                         DPLL(crtc->pipe));
9472         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
9473                 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
9474                                                                FP0(crtc->pipe));
9475                 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
9476                                                                FP1(crtc->pipe));
9477         } else {
9478                 /* Mask out read-only status bits. */
9479                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
9480                                                      DPLL_PORTC_READY_MASK |
9481                                                      DPLL_PORTB_READY_MASK);
9482         }
9483
9484         if (IS_CHERRYVIEW(dev_priv))
9485                 chv_crtc_clock_get(crtc, pipe_config);
9486         else if (IS_VALLEYVIEW(dev_priv))
9487                 vlv_crtc_clock_get(crtc, pipe_config);
9488         else
9489                 i9xx_crtc_clock_get(crtc, pipe_config);
9490
9491         /*
9492          * Normally the dotclock is filled in by the encoder .get_config()
9493          * but in case the pipe is enabled w/o any ports we need a sane
9494          * default.
9495          */
9496         pipe_config->hw.adjusted_mode.crtc_clock =
9497                 pipe_config->port_clock / pipe_config->pixel_multiplier;
9498
9499         ret = true;
9500
9501 out:
9502         intel_display_power_put(dev_priv, power_domain, wakeref);
9503
9504         return ret;
9505 }
9506
9507 static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
9508 {
9509         struct intel_encoder *encoder;
9510         int i;
9511         u32 val, final;
9512         bool has_lvds = false;
9513         bool has_cpu_edp = false;
9514         bool has_panel = false;
9515         bool has_ck505 = false;
9516         bool can_ssc = false;
9517         bool using_ssc_source = false;
9518
9519         /* We need to take the global config into account */
9520         for_each_intel_encoder(&dev_priv->drm, encoder) {
9521                 switch (encoder->type) {
9522                 case INTEL_OUTPUT_LVDS:
9523                         has_panel = true;
9524                         has_lvds = true;
9525                         break;
9526                 case INTEL_OUTPUT_EDP:
9527                         has_panel = true;
9528                         if (encoder->port == PORT_A)
9529                                 has_cpu_edp = true;
9530                         break;
9531                 default:
9532                         break;
9533                 }
9534         }
9535
9536         if (HAS_PCH_IBX(dev_priv)) {
9537                 has_ck505 = dev_priv->vbt.display_clock_mode;
9538                 can_ssc = has_ck505;
9539         } else {
9540                 has_ck505 = false;
9541                 can_ssc = true;
9542         }
9543
9544         /* Check if any DPLLs are using the SSC source */
9545         for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
9546                 u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
9547
9548                 if (!(temp & DPLL_VCO_ENABLE))
9549                         continue;
9550
9551                 if ((temp & PLL_REF_INPUT_MASK) ==
9552                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
9553                         using_ssc_source = true;
9554                         break;
9555                 }
9556         }
9557
9558         drm_dbg_kms(&dev_priv->drm,
9559                     "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
9560                     has_panel, has_lvds, has_ck505, using_ssc_source);
9561
9562         /* Ironlake: try to setup display ref clock before DPLL
9563          * enabling. This is only under driver's control after
9564          * PCH B stepping, previous chipset stepping should be
9565          * ignoring this setting.
9566          */
9567         val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
9568
9569         /* As we must carefully and slowly disable/enable each source in turn,
9570          * compute the final state we want first and check if we need to
9571          * make any changes at all.
9572          */
9573         final = val;
9574         final &= ~DREF_NONSPREAD_SOURCE_MASK;
9575         if (has_ck505)
9576                 final |= DREF_NONSPREAD_CK505_ENABLE;
9577         else
9578                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
9579
9580         final &= ~DREF_SSC_SOURCE_MASK;
9581         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9582         final &= ~DREF_SSC1_ENABLE;
9583
9584         if (has_panel) {
9585                 final |= DREF_SSC_SOURCE_ENABLE;
9586
9587                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9588                         final |= DREF_SSC1_ENABLE;
9589
9590                 if (has_cpu_edp) {
9591                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
9592                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9593                         else
9594                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9595                 } else
9596                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9597         } else if (using_ssc_source) {
9598                 final |= DREF_SSC_SOURCE_ENABLE;
9599                 final |= DREF_SSC1_ENABLE;
9600         }
9601
9602         if (final == val)
9603                 return;
9604
9605         /* Always enable nonspread source */
9606         val &= ~DREF_NONSPREAD_SOURCE_MASK;
9607
9608         if (has_ck505)
9609                 val |= DREF_NONSPREAD_CK505_ENABLE;
9610         else
9611                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9612
9613         if (has_panel) {
9614                 val &= ~DREF_SSC_SOURCE_MASK;
9615                 val |= DREF_SSC_SOURCE_ENABLE;
9616
9617                 /* SSC must be turned on before enabling the CPU output  */
9618                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9619                         drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
9620                         val |= DREF_SSC1_ENABLE;
9621                 } else
9622                         val &= ~DREF_SSC1_ENABLE;
9623
9624                 /* Get SSC going before enabling the outputs */
9625                 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9626                 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9627                 udelay(200);
9628
9629                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9630
9631                 /* Enable CPU source on CPU attached eDP */
9632                 if (has_cpu_edp) {
9633                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9634                                 drm_dbg_kms(&dev_priv->drm,
9635                                             "Using SSC on eDP\n");
9636                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9637                         } else
9638                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9639                 } else
9640                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9641
9642                 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9643                 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9644                 udelay(200);
9645         } else {
9646                 drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
9647
9648                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9649
9650                 /* Turn off CPU output */
9651                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9652
9653                 intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9654                 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9655                 udelay(200);
9656
9657                 if (!using_ssc_source) {
9658                         drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
9659
9660                         /* Turn off the SSC source */
9661                         val &= ~DREF_SSC_SOURCE_MASK;
9662                         val |= DREF_SSC_SOURCE_DISABLE;
9663
9664                         /* Turn off SSC1 */
9665                         val &= ~DREF_SSC1_ENABLE;
9666
9667                         intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
9668                         intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
9669                         udelay(200);
9670                 }
9671         }
9672
9673         BUG_ON(val != final);
9674 }
9675
9676 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9677 {
9678         u32 tmp;
9679
9680         tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
9681         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9682         intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
9683
9684         if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
9685                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9686                 drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
9687
9688         tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
9689         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9690         intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
9691
9692         if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
9693                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9694                 drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
9695 }
9696
9697 /* WaMPhyProgramming:hsw */
9698 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9699 {
9700         u32 tmp;
9701
9702         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9703         tmp &= ~(0xFF << 24);
9704         tmp |= (0x12 << 24);
9705         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9706
9707         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9708         tmp |= (1 << 11);
9709         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9710
9711         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9712         tmp |= (1 << 11);
9713         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9714
9715         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9716         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9717         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9718
9719         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9720         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9721         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9722
9723         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9724         tmp &= ~(7 << 13);
9725         tmp |= (5 << 13);
9726         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9727
9728         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9729         tmp &= ~(7 << 13);
9730         tmp |= (5 << 13);
9731         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9732
9733         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9734         tmp &= ~0xFF;
9735         tmp |= 0x1C;
9736         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9737
9738         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9739         tmp &= ~0xFF;
9740         tmp |= 0x1C;
9741         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9742
9743         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9744         tmp &= ~(0xFF << 16);
9745         tmp |= (0x1C << 16);
9746         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9747
9748         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9749         tmp &= ~(0xFF << 16);
9750         tmp |= (0x1C << 16);
9751         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9752
9753         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9754         tmp |= (1 << 27);
9755         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9756
9757         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9758         tmp |= (1 << 27);
9759         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9760
9761         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9762         tmp &= ~(0xF << 28);
9763         tmp |= (4 << 28);
9764         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9765
9766         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9767         tmp &= ~(0xF << 28);
9768         tmp |= (4 << 28);
9769         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9770 }
9771
9772 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9773  * Programming" based on the parameters passed:
9774  * - Sequence to enable CLKOUT_DP
9775  * - Sequence to enable CLKOUT_DP without spread
9776  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9777  */
9778 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
9779                                  bool with_spread, bool with_fdi)
9780 {
9781         u32 reg, tmp;
9782
9783         if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
9784                      "FDI requires downspread\n"))
9785                 with_spread = true;
9786         if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
9787                      with_fdi, "LP PCH doesn't have FDI\n"))
9788                 with_fdi = false;
9789
9790         mutex_lock(&dev_priv->sb_lock);
9791
9792         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9793         tmp &= ~SBI_SSCCTL_DISABLE;
9794         tmp |= SBI_SSCCTL_PATHALT;
9795         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9796
9797         udelay(24);
9798
9799         if (with_spread) {
9800                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9801                 tmp &= ~SBI_SSCCTL_PATHALT;
9802                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9803
9804                 if (with_fdi) {
9805                         lpt_reset_fdi_mphy(dev_priv);
9806                         lpt_program_fdi_mphy(dev_priv);
9807                 }
9808         }
9809
9810         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9811         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9812         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9813         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9814
9815         mutex_unlock(&dev_priv->sb_lock);
9816 }
9817
9818 /* Sequence to disable CLKOUT_DP */
9819 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
9820 {
9821         u32 reg, tmp;
9822
9823         mutex_lock(&dev_priv->sb_lock);
9824
9825         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
9826         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9827         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9828         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9829
9830         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9831         if (!(tmp & SBI_SSCCTL_DISABLE)) {
9832                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9833                         tmp |= SBI_SSCCTL_PATHALT;
9834                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9835                         udelay(32);
9836                 }
9837                 tmp |= SBI_SSCCTL_DISABLE;
9838                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9839         }
9840
9841         mutex_unlock(&dev_priv->sb_lock);
9842 }
9843
9844 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9845
9846 static const u16 sscdivintphase[] = {
9847         [BEND_IDX( 50)] = 0x3B23,
9848         [BEND_IDX( 45)] = 0x3B23,
9849         [BEND_IDX( 40)] = 0x3C23,
9850         [BEND_IDX( 35)] = 0x3C23,
9851         [BEND_IDX( 30)] = 0x3D23,
9852         [BEND_IDX( 25)] = 0x3D23,
9853         [BEND_IDX( 20)] = 0x3E23,
9854         [BEND_IDX( 15)] = 0x3E23,
9855         [BEND_IDX( 10)] = 0x3F23,
9856         [BEND_IDX(  5)] = 0x3F23,
9857         [BEND_IDX(  0)] = 0x0025,
9858         [BEND_IDX( -5)] = 0x0025,
9859         [BEND_IDX(-10)] = 0x0125,
9860         [BEND_IDX(-15)] = 0x0125,
9861         [BEND_IDX(-20)] = 0x0225,
9862         [BEND_IDX(-25)] = 0x0225,
9863         [BEND_IDX(-30)] = 0x0325,
9864         [BEND_IDX(-35)] = 0x0325,
9865         [BEND_IDX(-40)] = 0x0425,
9866         [BEND_IDX(-45)] = 0x0425,
9867         [BEND_IDX(-50)] = 0x0525,
9868 };
9869
9870 /*
9871  * Bend CLKOUT_DP
9872  * steps -50 to 50 inclusive, in steps of 5
9873  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9874  * change in clock period = -(steps / 10) * 5.787 ps
9875  */
9876 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9877 {
9878         u32 tmp;
9879         int idx = BEND_IDX(steps);
9880
9881         if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
9882                 return;
9883
9884         if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
9885                 return;
9886
9887         mutex_lock(&dev_priv->sb_lock);
9888
9889         if (steps % 10 != 0)
9890                 tmp = 0xAAAAAAAB;
9891         else
9892                 tmp = 0x00000000;
9893         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9894
9895         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9896         tmp &= 0xffff0000;
9897         tmp |= sscdivintphase[idx];
9898         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9899
9900         mutex_unlock(&dev_priv->sb_lock);
9901 }
9902
9903 #undef BEND_IDX
9904
9905 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
9906 {
9907         u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
9908         u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
9909
9910         if ((ctl & SPLL_PLL_ENABLE) == 0)
9911                 return false;
9912
9913         if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
9914             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9915                 return true;
9916
9917         if (IS_BROADWELL(dev_priv) &&
9918             (ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
9919                 return true;
9920
9921         return false;
9922 }
9923
9924 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
9925                                enum intel_dpll_id id)
9926 {
9927         u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
9928         u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
9929
9930         if ((ctl & WRPLL_PLL_ENABLE) == 0)
9931                 return false;
9932
9933         if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
9934                 return true;
9935
9936         if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
9937             (ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
9938             (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
9939                 return true;
9940
9941         return false;
9942 }
9943
9944 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
9945 {
9946         struct intel_encoder *encoder;
9947         bool has_fdi = false;
9948
9949         for_each_intel_encoder(&dev_priv->drm, encoder) {
9950                 switch (encoder->type) {
9951                 case INTEL_OUTPUT_ANALOG:
9952                         has_fdi = true;
9953                         break;
9954                 default:
9955                         break;
9956                 }
9957         }
9958
9959         /*
9960          * The BIOS may have decided to use the PCH SSC
9961          * reference so we must not disable it until the
9962          * relevant PLLs have stopped relying on it. We'll
9963          * just leave the PCH SSC reference enabled in case
9964          * any active PLL is using it. It will get disabled
9965          * after runtime suspend if we don't have FDI.
9966          *
9967          * TODO: Move the whole reference clock handling
9968          * to the modeset sequence proper so that we can
9969          * actually enable/disable/reconfigure these things
9970          * safely. To do that we need to introduce a real
9971          * clock hierarchy. That would also allow us to do
9972          * clock bending finally.
9973          */
9974         dev_priv->pch_ssc_use = 0;
9975
9976         if (spll_uses_pch_ssc(dev_priv)) {
9977                 drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
9978                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
9979         }
9980
9981         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
9982                 drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
9983                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
9984         }
9985
9986         if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
9987                 drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
9988                 dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
9989         }
9990
9991         if (dev_priv->pch_ssc_use)
9992                 return;
9993
9994         if (has_fdi) {
9995                 lpt_bend_clkout_dp(dev_priv, 0);
9996                 lpt_enable_clkout_dp(dev_priv, true, true);
9997         } else {
9998                 lpt_disable_clkout_dp(dev_priv);
9999         }
10000 }
10001
10002 /*
10003  * Initialize reference clocks when the driver loads
10004  */
10005 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
10006 {
10007         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
10008                 ilk_init_pch_refclk(dev_priv);
10009         else if (HAS_PCH_LPT(dev_priv))
10010                 lpt_init_pch_refclk(dev_priv);
10011 }
10012
10013 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
10014 {
10015         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10016         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10017         enum pipe pipe = crtc->pipe;
10018         u32 val;
10019
10020         val = 0;
10021
10022         switch (crtc_state->pipe_bpp) {
10023         case 18:
10024                 val |= PIPECONF_6BPC;
10025                 break;
10026         case 24:
10027                 val |= PIPECONF_8BPC;
10028                 break;
10029         case 30:
10030                 val |= PIPECONF_10BPC;
10031                 break;
10032         case 36:
10033                 val |= PIPECONF_12BPC;
10034                 break;
10035         default:
10036                 /* Case prevented by intel_choose_pipe_bpp_dither. */
10037                 BUG();
10038         }
10039
10040         if (crtc_state->dither)
10041                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
10042
10043         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
10044                 val |= PIPECONF_INTERLACED_ILK;
10045         else
10046                 val |= PIPECONF_PROGRESSIVE;
10047
10048         /*
10049          * This would end up with an odd purple hue over
10050          * the entire display. Make sure we don't do it.
10051          */
10052         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
10053                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
10054
10055         if (crtc_state->limited_color_range)
10056                 val |= PIPECONF_COLOR_RANGE_SELECT;
10057
10058         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
10059                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
10060
10061         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
10062
10063         val |= PIPECONF_FRAME_START_DELAY(0);
10064
10065         intel_de_write(dev_priv, PIPECONF(pipe), val);
10066         intel_de_posting_read(dev_priv, PIPECONF(pipe));
10067 }
10068
10069 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state)
10070 {
10071         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10072         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10073         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
10074         u32 val = 0;
10075
10076         if (IS_HASWELL(dev_priv) && crtc_state->dither)
10077                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
10078
10079         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
10080                 val |= PIPECONF_INTERLACED_ILK;
10081         else
10082                 val |= PIPECONF_PROGRESSIVE;
10083
10084         if (IS_HASWELL(dev_priv) &&
10085             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
10086                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
10087
10088         intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
10089         intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
10090 }
10091
10092 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
10093 {
10094         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10095         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10096         u32 val = 0;
10097
10098         switch (crtc_state->pipe_bpp) {
10099         case 18:
10100                 val |= PIPEMISC_DITHER_6_BPC;
10101                 break;
10102         case 24:
10103                 val |= PIPEMISC_DITHER_8_BPC;
10104                 break;
10105         case 30:
10106                 val |= PIPEMISC_DITHER_10_BPC;
10107                 break;
10108         case 36:
10109                 val |= PIPEMISC_DITHER_12_BPC;
10110                 break;
10111         default:
10112                 MISSING_CASE(crtc_state->pipe_bpp);
10113                 break;
10114         }
10115
10116         if (crtc_state->dither)
10117                 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
10118
10119         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
10120             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
10121                 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
10122
10123         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
10124                 val |= PIPEMISC_YUV420_ENABLE |
10125                         PIPEMISC_YUV420_MODE_FULL_BLEND;
10126
10127         if (INTEL_GEN(dev_priv) >= 11 &&
10128             (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
10129                                            BIT(PLANE_CURSOR))) == 0)
10130                 val |= PIPEMISC_HDR_MODE_PRECISION;
10131
10132         if (INTEL_GEN(dev_priv) >= 12)
10133                 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
10134
10135         intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
10136 }
10137
10138 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
10139 {
10140         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10141         u32 tmp;
10142
10143         tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
10144
10145         switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
10146         case PIPEMISC_DITHER_6_BPC:
10147                 return 18;
10148         case PIPEMISC_DITHER_8_BPC:
10149                 return 24;
10150         case PIPEMISC_DITHER_10_BPC:
10151                 return 30;
10152         case PIPEMISC_DITHER_12_BPC:
10153                 return 36;
10154         default:
10155                 MISSING_CASE(tmp);
10156                 return 0;
10157         }
10158 }
10159
10160 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
10161 {
10162         /*
10163          * Account for spread spectrum to avoid
10164          * oversubscribing the link. Max center spread
10165          * is 2.5%; use 5% for safety's sake.
10166          */
10167         u32 bps = target_clock * bpp * 21 / 20;
10168         return DIV_ROUND_UP(bps, link_bw * 8);
10169 }
10170
10171 static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor)
10172 {
10173         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
10174 }
10175
10176 static void ilk_compute_dpll(struct intel_crtc *crtc,
10177                              struct intel_crtc_state *crtc_state,
10178                              struct dpll *reduced_clock)
10179 {
10180         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10181         u32 dpll, fp, fp2;
10182         int factor;
10183
10184         /* Enable autotuning of the PLL clock (if permissible) */
10185         factor = 21;
10186         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
10187                 if ((intel_panel_use_ssc(dev_priv) &&
10188                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
10189                     (HAS_PCH_IBX(dev_priv) &&
10190                      intel_is_dual_link_lvds(dev_priv)))
10191                         factor = 25;
10192         } else if (crtc_state->sdvo_tv_clock) {
10193                 factor = 20;
10194         }
10195
10196         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
10197
10198         if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor))
10199                 fp |= FP_CB_TUNE;
10200
10201         if (reduced_clock) {
10202                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
10203
10204                 if (reduced_clock->m < factor * reduced_clock->n)
10205                         fp2 |= FP_CB_TUNE;
10206         } else {
10207                 fp2 = fp;
10208         }
10209
10210         dpll = 0;
10211
10212         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
10213                 dpll |= DPLLB_MODE_LVDS;
10214         else
10215                 dpll |= DPLLB_MODE_DAC_SERIAL;
10216
10217         dpll |= (crtc_state->pixel_multiplier - 1)
10218                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
10219
10220         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
10221             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
10222                 dpll |= DPLL_SDVO_HIGH_SPEED;
10223
10224         if (intel_crtc_has_dp_encoder(crtc_state))
10225                 dpll |= DPLL_SDVO_HIGH_SPEED;
10226
10227         /*
10228          * The high speed IO clock is only really required for
10229          * SDVO/HDMI/DP, but we also enable it for CRT to make it
10230          * possible to share the DPLL between CRT and HDMI. Enabling
10231          * the clock needlessly does no real harm, except use up a
10232          * bit of power potentially.
10233          *
10234          * We'll limit this to IVB with 3 pipes, since it has only two
10235          * DPLLs and so DPLL sharing is the only way to get three pipes
10236          * driving PCH ports at the same time. On SNB we could do this,
10237          * and potentially avoid enabling the second DPLL, but it's not
10238          * clear if it''s a win or loss power wise. No point in doing
10239          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
10240          */
10241         if (INTEL_NUM_PIPES(dev_priv) == 3 &&
10242             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
10243                 dpll |= DPLL_SDVO_HIGH_SPEED;
10244
10245         /* compute bitmask from p1 value */
10246         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
10247         /* also FPA1 */
10248         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
10249
10250         switch (crtc_state->dpll.p2) {
10251         case 5:
10252                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
10253                 break;
10254         case 7:
10255                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
10256                 break;
10257         case 10:
10258                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
10259                 break;
10260         case 14:
10261                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
10262                 break;
10263         }
10264
10265         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
10266             intel_panel_use_ssc(dev_priv))
10267                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
10268         else
10269                 dpll |= PLL_REF_INPUT_DREFCLK;
10270
10271         dpll |= DPLL_VCO_ENABLE;
10272
10273         crtc_state->dpll_hw_state.dpll = dpll;
10274         crtc_state->dpll_hw_state.fp0 = fp;
10275         crtc_state->dpll_hw_state.fp1 = fp2;
10276 }
10277
10278 static int ilk_crtc_compute_clock(struct intel_crtc *crtc,
10279                                   struct intel_crtc_state *crtc_state)
10280 {
10281         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10282         struct intel_atomic_state *state =
10283                 to_intel_atomic_state(crtc_state->uapi.state);
10284         const struct intel_limit *limit;
10285         int refclk = 120000;
10286
10287         memset(&crtc_state->dpll_hw_state, 0,
10288                sizeof(crtc_state->dpll_hw_state));
10289
10290         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
10291         if (!crtc_state->has_pch_encoder)
10292                 return 0;
10293
10294         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
10295                 if (intel_panel_use_ssc(dev_priv)) {
10296                         drm_dbg_kms(&dev_priv->drm,
10297                                     "using SSC reference clock of %d kHz\n",
10298                                     dev_priv->vbt.lvds_ssc_freq);
10299                         refclk = dev_priv->vbt.lvds_ssc_freq;
10300                 }
10301
10302                 if (intel_is_dual_link_lvds(dev_priv)) {
10303                         if (refclk == 100000)
10304                                 limit = &ilk_limits_dual_lvds_100m;
10305                         else
10306                                 limit = &ilk_limits_dual_lvds;
10307                 } else {
10308                         if (refclk == 100000)
10309                                 limit = &ilk_limits_single_lvds_100m;
10310                         else
10311                                 limit = &ilk_limits_single_lvds;
10312                 }
10313         } else {
10314                 limit = &ilk_limits_dac;
10315         }
10316
10317         if (!crtc_state->clock_set &&
10318             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
10319                                 refclk, NULL, &crtc_state->dpll)) {
10320                 drm_err(&dev_priv->drm,
10321                         "Couldn't find PLL settings for mode!\n");
10322                 return -EINVAL;
10323         }
10324
10325         ilk_compute_dpll(crtc, crtc_state, NULL);
10326
10327         if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
10328                 drm_dbg_kms(&dev_priv->drm,
10329                             "failed to find PLL for pipe %c\n",
10330                             pipe_name(crtc->pipe));
10331                 return -EINVAL;
10332         }
10333
10334         return 0;
10335 }
10336
10337 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
10338                                          struct intel_link_m_n *m_n)
10339 {
10340         struct drm_device *dev = crtc->base.dev;
10341         struct drm_i915_private *dev_priv = to_i915(dev);
10342         enum pipe pipe = crtc->pipe;
10343
10344         m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));
10345         m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));
10346         m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
10347                 & ~TU_SIZE_MASK;
10348         m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));
10349         m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
10350                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10351 }
10352
10353 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
10354                                          enum transcoder transcoder,
10355                                          struct intel_link_m_n *m_n,
10356                                          struct intel_link_m_n *m2_n2)
10357 {
10358         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10359         enum pipe pipe = crtc->pipe;
10360
10361         if (INTEL_GEN(dev_priv) >= 5) {
10362                 m_n->link_m = intel_de_read(dev_priv,
10363                                             PIPE_LINK_M1(transcoder));
10364                 m_n->link_n = intel_de_read(dev_priv,
10365                                             PIPE_LINK_N1(transcoder));
10366                 m_n->gmch_m = intel_de_read(dev_priv,
10367                                             PIPE_DATA_M1(transcoder))
10368                         & ~TU_SIZE_MASK;
10369                 m_n->gmch_n = intel_de_read(dev_priv,
10370                                             PIPE_DATA_N1(transcoder));
10371                 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))
10372                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10373
10374                 if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
10375                         m2_n2->link_m = intel_de_read(dev_priv,
10376                                                       PIPE_LINK_M2(transcoder));
10377                         m2_n2->link_n = intel_de_read(dev_priv,
10378                                                              PIPE_LINK_N2(transcoder));
10379                         m2_n2->gmch_m = intel_de_read(dev_priv,
10380                                                              PIPE_DATA_M2(transcoder))
10381                                         & ~TU_SIZE_MASK;
10382                         m2_n2->gmch_n = intel_de_read(dev_priv,
10383                                                              PIPE_DATA_N2(transcoder));
10384                         m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))
10385                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10386                 }
10387         } else {
10388                 m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));
10389                 m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));
10390                 m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
10391                         & ~TU_SIZE_MASK;
10392                 m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));
10393                 m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
10394                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
10395         }
10396 }
10397
10398 void intel_dp_get_m_n(struct intel_crtc *crtc,
10399                       struct intel_crtc_state *pipe_config)
10400 {
10401         if (pipe_config->has_pch_encoder)
10402                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
10403         else
10404                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
10405                                              &pipe_config->dp_m_n,
10406                                              &pipe_config->dp_m2_n2);
10407 }
10408
10409 static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,
10410                                    struct intel_crtc_state *pipe_config)
10411 {
10412         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
10413                                      &pipe_config->fdi_m_n, NULL);
10414 }
10415
10416 static void skl_get_pfit_config(struct intel_crtc *crtc,
10417                                 struct intel_crtc_state *pipe_config)
10418 {
10419         struct drm_device *dev = crtc->base.dev;
10420         struct drm_i915_private *dev_priv = to_i915(dev);
10421         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
10422         u32 ps_ctrl = 0;
10423         int id = -1;
10424         int i;
10425
10426         /* find scaler attached to this pipe */
10427         for (i = 0; i < crtc->num_scalers; i++) {
10428                 ps_ctrl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
10429                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
10430                         id = i;
10431                         pipe_config->pch_pfit.enabled = true;
10432                         pipe_config->pch_pfit.pos = intel_de_read(dev_priv,
10433                                                                   SKL_PS_WIN_POS(crtc->pipe, i));
10434                         pipe_config->pch_pfit.size = intel_de_read(dev_priv,
10435                                                                    SKL_PS_WIN_SZ(crtc->pipe, i));
10436                         scaler_state->scalers[i].in_use = true;
10437                         break;
10438                 }
10439         }
10440
10441         scaler_state->scaler_id = id;
10442         if (id >= 0) {
10443                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
10444         } else {
10445                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
10446         }
10447 }
10448
10449 static void
10450 skl_get_initial_plane_config(struct intel_crtc *crtc,
10451                              struct intel_initial_plane_config *plane_config)
10452 {
10453         struct drm_device *dev = crtc->base.dev;
10454         struct drm_i915_private *dev_priv = to_i915(dev);
10455         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
10456         enum plane_id plane_id = plane->id;
10457         enum pipe pipe;
10458         u32 val, base, offset, stride_mult, tiling, alpha;
10459         int fourcc, pixel_format;
10460         unsigned int aligned_height;
10461         struct drm_framebuffer *fb;
10462         struct intel_framebuffer *intel_fb;
10463
10464         if (!plane->get_hw_state(plane, &pipe))
10465                 return;
10466
10467         drm_WARN_ON(dev, pipe != crtc->pipe);
10468
10469         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10470         if (!intel_fb) {
10471                 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
10472                 return;
10473         }
10474
10475         fb = &intel_fb->base;
10476
10477         fb->dev = dev;
10478
10479         val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
10480
10481         if (INTEL_GEN(dev_priv) >= 11)
10482                 pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
10483         else
10484                 pixel_format = val & PLANE_CTL_FORMAT_MASK;
10485
10486         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
10487                 alpha = intel_de_read(dev_priv,
10488                                       PLANE_COLOR_CTL(pipe, plane_id));
10489                 alpha &= PLANE_COLOR_ALPHA_MASK;
10490         } else {
10491                 alpha = val & PLANE_CTL_ALPHA_MASK;
10492         }
10493
10494         fourcc = skl_format_to_fourcc(pixel_format,
10495                                       val & PLANE_CTL_ORDER_RGBX, alpha);
10496         fb->format = drm_format_info(fourcc);
10497
10498         tiling = val & PLANE_CTL_TILED_MASK;
10499         switch (tiling) {
10500         case PLANE_CTL_TILED_LINEAR:
10501                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
10502                 break;
10503         case PLANE_CTL_TILED_X:
10504                 plane_config->tiling = I915_TILING_X;
10505                 fb->modifier = I915_FORMAT_MOD_X_TILED;
10506                 break;
10507         case PLANE_CTL_TILED_Y:
10508                 plane_config->tiling = I915_TILING_Y;
10509                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10510                         fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
10511                                 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
10512                                 I915_FORMAT_MOD_Y_TILED_CCS;
10513                 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
10514                         fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
10515                 else
10516                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
10517                 break;
10518         case PLANE_CTL_TILED_YF:
10519                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
10520                         fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
10521                 else
10522                         fb->modifier = I915_FORMAT_MOD_Yf_TILED;
10523                 break;
10524         default:
10525                 MISSING_CASE(tiling);
10526                 goto error;
10527         }
10528
10529         /*
10530          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
10531          * while i915 HW rotation is clockwise, thats why this swapping.
10532          */
10533         switch (val & PLANE_CTL_ROTATE_MASK) {
10534         case PLANE_CTL_ROTATE_0:
10535                 plane_config->rotation = DRM_MODE_ROTATE_0;
10536                 break;
10537         case PLANE_CTL_ROTATE_90:
10538                 plane_config->rotation = DRM_MODE_ROTATE_270;
10539                 break;
10540         case PLANE_CTL_ROTATE_180:
10541                 plane_config->rotation = DRM_MODE_ROTATE_180;
10542                 break;
10543         case PLANE_CTL_ROTATE_270:
10544                 plane_config->rotation = DRM_MODE_ROTATE_90;
10545                 break;
10546         }
10547
10548         if (INTEL_GEN(dev_priv) >= 10 &&
10549             val & PLANE_CTL_FLIP_HORIZONTAL)
10550                 plane_config->rotation |= DRM_MODE_REFLECT_X;
10551
10552         base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000;
10553         plane_config->base = base;
10554
10555         offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
10556
10557         val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
10558         fb->height = ((val >> 16) & 0xffff) + 1;
10559         fb->width = ((val >> 0) & 0xffff) + 1;
10560
10561         val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
10562         stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
10563         fb->pitches[0] = (val & 0x3ff) * stride_mult;
10564
10565         aligned_height = intel_fb_align_height(fb, 0, fb->height);
10566
10567         plane_config->size = fb->pitches[0] * aligned_height;
10568
10569         drm_dbg_kms(&dev_priv->drm,
10570                     "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
10571                     crtc->base.name, plane->base.name, fb->width, fb->height,
10572                     fb->format->cpp[0] * 8, base, fb->pitches[0],
10573                     plane_config->size);
10574
10575         plane_config->fb = intel_fb;
10576         return;
10577
10578 error:
10579         kfree(intel_fb);
10580 }
10581
10582 static void ilk_get_pfit_config(struct intel_crtc *crtc,
10583                                 struct intel_crtc_state *pipe_config)
10584 {
10585         struct drm_device *dev = crtc->base.dev;
10586         struct drm_i915_private *dev_priv = to_i915(dev);
10587         u32 tmp;
10588
10589         tmp = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
10590
10591         if (tmp & PF_ENABLE) {
10592                 pipe_config->pch_pfit.enabled = true;
10593                 pipe_config->pch_pfit.pos = intel_de_read(dev_priv,
10594                                                           PF_WIN_POS(crtc->pipe));
10595                 pipe_config->pch_pfit.size = intel_de_read(dev_priv,
10596                                                            PF_WIN_SZ(crtc->pipe));
10597
10598                 /* We currently do not free assignements of panel fitters on
10599                  * ivb/hsw (since we don't use the higher upscaling modes which
10600                  * differentiates them) so just WARN about this case for now. */
10601                 if (IS_GEN(dev_priv, 7)) {
10602                         drm_WARN_ON(dev, (tmp & PF_PIPE_SEL_MASK_IVB) !=
10603                                     PF_PIPE_SEL_IVB(crtc->pipe));
10604                 }
10605         }
10606 }
10607
10608 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
10609                                 struct intel_crtc_state *pipe_config)
10610 {
10611         struct drm_device *dev = crtc->base.dev;
10612         struct drm_i915_private *dev_priv = to_i915(dev);
10613         enum intel_display_power_domain power_domain;
10614         intel_wakeref_t wakeref;
10615         u32 tmp;
10616         bool ret;
10617
10618         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10619         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
10620         if (!wakeref)
10621                 return false;
10622
10623         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10624         pipe_config->shared_dpll = NULL;
10625         pipe_config->master_transcoder = INVALID_TRANSCODER;
10626
10627         ret = false;
10628         tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
10629         if (!(tmp & PIPECONF_ENABLE))
10630                 goto out;
10631
10632         switch (tmp & PIPECONF_BPC_MASK) {
10633         case PIPECONF_6BPC:
10634                 pipe_config->pipe_bpp = 18;
10635                 break;
10636         case PIPECONF_8BPC:
10637                 pipe_config->pipe_bpp = 24;
10638                 break;
10639         case PIPECONF_10BPC:
10640                 pipe_config->pipe_bpp = 30;
10641                 break;
10642         case PIPECONF_12BPC:
10643                 pipe_config->pipe_bpp = 36;
10644                 break;
10645         default:
10646                 break;
10647         }
10648
10649         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
10650                 pipe_config->limited_color_range = true;
10651
10652         switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
10653         case PIPECONF_OUTPUT_COLORSPACE_YUV601:
10654         case PIPECONF_OUTPUT_COLORSPACE_YUV709:
10655                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
10656                 break;
10657         default:
10658                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
10659                 break;
10660         }
10661
10662         pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
10663                 PIPECONF_GAMMA_MODE_SHIFT;
10664
10665         pipe_config->csc_mode = intel_de_read(dev_priv,
10666                                               PIPE_CSC_MODE(crtc->pipe));
10667
10668         i9xx_get_pipe_color_config(pipe_config);
10669         intel_color_get_config(pipe_config);
10670
10671         if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
10672                 struct intel_shared_dpll *pll;
10673                 enum intel_dpll_id pll_id;
10674
10675                 pipe_config->has_pch_encoder = true;
10676
10677                 tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe));
10678                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10679                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10680
10681                 ilk_get_fdi_m_n_config(crtc, pipe_config);
10682
10683                 if (HAS_PCH_IBX(dev_priv)) {
10684                         /*
10685                          * The pipe->pch transcoder and pch transcoder->pll
10686                          * mapping is fixed.
10687                          */
10688                         pll_id = (enum intel_dpll_id) crtc->pipe;
10689                 } else {
10690                         tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
10691                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
10692                                 pll_id = DPLL_ID_PCH_PLL_B;
10693                         else
10694                                 pll_id= DPLL_ID_PCH_PLL_A;
10695                 }
10696
10697                 pipe_config->shared_dpll =
10698                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
10699                 pll = pipe_config->shared_dpll;
10700
10701                 drm_WARN_ON(dev, !pll->info->funcs->get_hw_state(dev_priv, pll,
10702                                                  &pipe_config->dpll_hw_state));
10703
10704                 tmp = pipe_config->dpll_hw_state.dpll;
10705                 pipe_config->pixel_multiplier =
10706                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
10707                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
10708
10709                 ilk_pch_clock_get(crtc, pipe_config);
10710         } else {
10711                 pipe_config->pixel_multiplier = 1;
10712         }
10713
10714         intel_get_pipe_timings(crtc, pipe_config);
10715         intel_get_pipe_src_size(crtc, pipe_config);
10716
10717         ilk_get_pfit_config(crtc, pipe_config);
10718
10719         ret = true;
10720
10721 out:
10722         intel_display_power_put(dev_priv, power_domain, wakeref);
10723
10724         return ret;
10725 }
10726
10727 static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
10728                                   struct intel_crtc_state *crtc_state)
10729 {
10730         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10731         struct intel_atomic_state *state =
10732                 to_intel_atomic_state(crtc_state->uapi.state);
10733
10734         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
10735             INTEL_GEN(dev_priv) >= 11) {
10736                 struct intel_encoder *encoder =
10737                         intel_get_crtc_new_encoder(state, crtc_state);
10738
10739                 if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
10740                         drm_dbg_kms(&dev_priv->drm,
10741                                     "failed to find PLL for pipe %c\n",
10742                                     pipe_name(crtc->pipe));
10743                         return -EINVAL;
10744                 }
10745         }
10746
10747         return 0;
10748 }
10749
10750 static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10751                             struct intel_crtc_state *pipe_config)
10752 {
10753         enum intel_dpll_id id;
10754         u32 temp;
10755
10756         temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
10757         id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
10758
10759         if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2))
10760                 return;
10761
10762         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10763 }
10764
10765 static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10766                             struct intel_crtc_state *pipe_config)
10767 {
10768         enum phy phy = intel_port_to_phy(dev_priv, port);
10769         enum icl_port_dpll_id port_dpll_id;
10770         enum intel_dpll_id id;
10771         u32 temp;
10772
10773         if (intel_phy_is_combo(dev_priv, phy)) {
10774                 temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) &
10775                         ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
10776                 id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
10777                 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10778         } else if (intel_phy_is_tc(dev_priv, phy)) {
10779                 u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
10780
10781                 if (clk_sel == DDI_CLK_SEL_MG) {
10782                         id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
10783                                                                     port));
10784                         port_dpll_id = ICL_PORT_DPLL_MG_PHY;
10785                 } else {
10786                         drm_WARN_ON(&dev_priv->drm,
10787                                     clk_sel < DDI_CLK_SEL_TBT_162);
10788                         id = DPLL_ID_ICL_TBTPLL;
10789                         port_dpll_id = ICL_PORT_DPLL_DEFAULT;
10790                 }
10791         } else {
10792                 drm_WARN(&dev_priv->drm, 1, "Invalid port %x\n", port);
10793                 return;
10794         }
10795
10796         pipe_config->icl_port_dplls[port_dpll_id].pll =
10797                 intel_get_shared_dpll_by_id(dev_priv, id);
10798
10799         icl_set_active_port_dpll(pipe_config, port_dpll_id);
10800 }
10801
10802 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10803                                 enum port port,
10804                                 struct intel_crtc_state *pipe_config)
10805 {
10806         enum intel_dpll_id id;
10807
10808         switch (port) {
10809         case PORT_A:
10810                 id = DPLL_ID_SKL_DPLL0;
10811                 break;
10812         case PORT_B:
10813                 id = DPLL_ID_SKL_DPLL1;
10814                 break;
10815         case PORT_C:
10816                 id = DPLL_ID_SKL_DPLL2;
10817                 break;
10818         default:
10819                 drm_err(&dev_priv->drm, "Incorrect port type\n");
10820                 return;
10821         }
10822
10823         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10824 }
10825
10826 static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10827                             struct intel_crtc_state *pipe_config)
10828 {
10829         enum intel_dpll_id id;
10830         u32 temp;
10831
10832         temp = intel_de_read(dev_priv, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10833         id = temp >> (port * 3 + 1);
10834
10835         if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL3))
10836                 return;
10837
10838         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10839 }
10840
10841 static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
10842                             struct intel_crtc_state *pipe_config)
10843 {
10844         enum intel_dpll_id id;
10845         u32 ddi_pll_sel = intel_de_read(dev_priv, PORT_CLK_SEL(port));
10846
10847         switch (ddi_pll_sel) {
10848         case PORT_CLK_SEL_WRPLL1:
10849                 id = DPLL_ID_WRPLL1;
10850                 break;
10851         case PORT_CLK_SEL_WRPLL2:
10852                 id = DPLL_ID_WRPLL2;
10853                 break;
10854         case PORT_CLK_SEL_SPLL:
10855                 id = DPLL_ID_SPLL;
10856                 break;
10857         case PORT_CLK_SEL_LCPLL_810:
10858                 id = DPLL_ID_LCPLL_810;
10859                 break;
10860         case PORT_CLK_SEL_LCPLL_1350:
10861                 id = DPLL_ID_LCPLL_1350;
10862                 break;
10863         case PORT_CLK_SEL_LCPLL_2700:
10864                 id = DPLL_ID_LCPLL_2700;
10865                 break;
10866         default:
10867                 MISSING_CASE(ddi_pll_sel);
10868                 /* fall through */
10869         case PORT_CLK_SEL_NONE:
10870                 return;
10871         }
10872
10873         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10874 }
10875
10876 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10877                                      struct intel_crtc_state *pipe_config,
10878                                      u64 *power_domain_mask,
10879                                      intel_wakeref_t *wakerefs)
10880 {
10881         struct drm_device *dev = crtc->base.dev;
10882         struct drm_i915_private *dev_priv = to_i915(dev);
10883         enum intel_display_power_domain power_domain;
10884         unsigned long panel_transcoder_mask = 0;
10885         unsigned long enabled_panel_transcoders = 0;
10886         enum transcoder panel_transcoder;
10887         intel_wakeref_t wf;
10888         u32 tmp;
10889
10890         if (INTEL_GEN(dev_priv) >= 11)
10891                 panel_transcoder_mask |=
10892                         BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
10893
10894         if (HAS_TRANSCODER_EDP(dev_priv))
10895                 panel_transcoder_mask |= BIT(TRANSCODER_EDP);
10896
10897         /*
10898          * The pipe->transcoder mapping is fixed with the exception of the eDP
10899          * and DSI transcoders handled below.
10900          */
10901         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10902
10903         /*
10904          * XXX: Do intel_display_power_get_if_enabled before reading this (for
10905          * consistency and less surprising code; it's in always on power).
10906          */
10907         for_each_set_bit(panel_transcoder,
10908                          &panel_transcoder_mask,
10909                          ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) {
10910                 bool force_thru = false;
10911                 enum pipe trans_pipe;
10912
10913                 tmp = intel_de_read(dev_priv,
10914                                     TRANS_DDI_FUNC_CTL(panel_transcoder));
10915                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
10916                         continue;
10917
10918                 /*
10919                  * Log all enabled ones, only use the first one.
10920                  *
10921                  * FIXME: This won't work for two separate DSI displays.
10922                  */
10923                 enabled_panel_transcoders |= BIT(panel_transcoder);
10924                 if (enabled_panel_transcoders != BIT(panel_transcoder))
10925                         continue;
10926
10927                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10928                 default:
10929                         drm_WARN(dev, 1,
10930                                  "unknown pipe linked to transcoder %s\n",
10931                                  transcoder_name(panel_transcoder));
10932                         /* fall through */
10933                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10934                         force_thru = true;
10935                         /* fall through */
10936                 case TRANS_DDI_EDP_INPUT_A_ON:
10937                         trans_pipe = PIPE_A;
10938                         break;
10939                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10940                         trans_pipe = PIPE_B;
10941                         break;
10942                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10943                         trans_pipe = PIPE_C;
10944                         break;
10945                 case TRANS_DDI_EDP_INPUT_D_ONOFF:
10946                         trans_pipe = PIPE_D;
10947                         break;
10948                 }
10949
10950                 if (trans_pipe == crtc->pipe) {
10951                         pipe_config->cpu_transcoder = panel_transcoder;
10952                         pipe_config->pch_pfit.force_thru = force_thru;
10953                 }
10954         }
10955
10956         /*
10957          * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1
10958          */
10959         drm_WARN_ON(dev, (enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&
10960                     enabled_panel_transcoders != BIT(TRANSCODER_EDP));
10961
10962         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10963         drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
10964
10965         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
10966         if (!wf)
10967                 return false;
10968
10969         wakerefs[power_domain] = wf;
10970         *power_domain_mask |= BIT_ULL(power_domain);
10971
10972         tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
10973
10974         return tmp & PIPECONF_ENABLE;
10975 }
10976
10977 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10978                                          struct intel_crtc_state *pipe_config,
10979                                          u64 *power_domain_mask,
10980                                          intel_wakeref_t *wakerefs)
10981 {
10982         struct drm_device *dev = crtc->base.dev;
10983         struct drm_i915_private *dev_priv = to_i915(dev);
10984         enum intel_display_power_domain power_domain;
10985         enum transcoder cpu_transcoder;
10986         intel_wakeref_t wf;
10987         enum port port;
10988         u32 tmp;
10989
10990         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10991                 if (port == PORT_A)
10992                         cpu_transcoder = TRANSCODER_DSI_A;
10993                 else
10994                         cpu_transcoder = TRANSCODER_DSI_C;
10995
10996                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10997                 drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain));
10998
10999                 wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11000                 if (!wf)
11001                         continue;
11002
11003                 wakerefs[power_domain] = wf;
11004                 *power_domain_mask |= BIT_ULL(power_domain);
11005
11006                 /*
11007                  * The PLL needs to be enabled with a valid divider
11008                  * configuration, otherwise accessing DSI registers will hang
11009                  * the machine. See BSpec North Display Engine
11010                  * registers/MIPI[BXT]. We can break out here early, since we
11011                  * need the same DSI PLL to be enabled for both DSI ports.
11012                  */
11013                 if (!bxt_dsi_pll_is_enabled(dev_priv))
11014                         break;
11015
11016                 /* XXX: this works for video mode only */
11017                 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
11018                 if (!(tmp & DPI_ENABLE))
11019                         continue;
11020
11021                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
11022                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
11023                         continue;
11024
11025                 pipe_config->cpu_transcoder = cpu_transcoder;
11026                 break;
11027         }
11028
11029         return transcoder_is_dsi(pipe_config->cpu_transcoder);
11030 }
11031
11032 static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
11033                                    struct intel_crtc_state *pipe_config)
11034 {
11035         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11036         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
11037         struct intel_shared_dpll *pll;
11038         enum port port;
11039         u32 tmp;
11040
11041         if (transcoder_is_dsi(cpu_transcoder)) {
11042                 port = (cpu_transcoder == TRANSCODER_DSI_A) ?
11043                                                 PORT_A : PORT_B;
11044         } else {
11045                 tmp = intel_de_read(dev_priv,
11046                                     TRANS_DDI_FUNC_CTL(cpu_transcoder));
11047                 if (INTEL_GEN(dev_priv) >= 12)
11048                         port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
11049                 else
11050                         port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
11051         }
11052
11053         if (INTEL_GEN(dev_priv) >= 11)
11054                 icl_get_ddi_pll(dev_priv, port, pipe_config);
11055         else if (IS_CANNONLAKE(dev_priv))
11056                 cnl_get_ddi_pll(dev_priv, port, pipe_config);
11057         else if (IS_GEN9_BC(dev_priv))
11058                 skl_get_ddi_pll(dev_priv, port, pipe_config);
11059         else if (IS_GEN9_LP(dev_priv))
11060                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
11061         else
11062                 hsw_get_ddi_pll(dev_priv, port, pipe_config);
11063
11064         pll = pipe_config->shared_dpll;
11065         if (pll) {
11066                 drm_WARN_ON(&dev_priv->drm,
11067                             !pll->info->funcs->get_hw_state(dev_priv, pll,
11068                                                 &pipe_config->dpll_hw_state));
11069         }
11070
11071         /*
11072          * Haswell has only FDI/PCH transcoder A. It is which is connected to
11073          * DDI E. So just check whether this pipe is wired to DDI E and whether
11074          * the PCH transcoder is on.
11075          */
11076         if (INTEL_GEN(dev_priv) < 9 &&
11077             (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) {
11078                 pipe_config->has_pch_encoder = true;
11079
11080                 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
11081                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
11082                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
11083
11084                 ilk_get_fdi_m_n_config(crtc, pipe_config);
11085         }
11086 }
11087
11088 static enum transcoder transcoder_master_readout(struct drm_i915_private *dev_priv,
11089                                                  enum transcoder cpu_transcoder)
11090 {
11091         u32 trans_port_sync, master_select;
11092
11093         trans_port_sync = intel_de_read(dev_priv,
11094                                         TRANS_DDI_FUNC_CTL2(cpu_transcoder));
11095
11096         if ((trans_port_sync & PORT_SYNC_MODE_ENABLE) == 0)
11097                 return INVALID_TRANSCODER;
11098
11099         master_select = trans_port_sync &
11100                         PORT_SYNC_MODE_MASTER_SELECT_MASK;
11101         if (master_select == 0)
11102                 return TRANSCODER_EDP;
11103         else
11104                 return master_select - 1;
11105 }
11106
11107 static void icl_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
11108 {
11109         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
11110         u32 transcoders;
11111         enum transcoder cpu_transcoder;
11112
11113         crtc_state->master_transcoder = transcoder_master_readout(dev_priv,
11114                                                                   crtc_state->cpu_transcoder);
11115
11116         transcoders = BIT(TRANSCODER_A) |
11117                 BIT(TRANSCODER_B) |
11118                 BIT(TRANSCODER_C) |
11119                 BIT(TRANSCODER_D);
11120         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
11121                 enum intel_display_power_domain power_domain;
11122                 intel_wakeref_t trans_wakeref;
11123
11124                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
11125                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
11126                                                                    power_domain);
11127
11128                 if (!trans_wakeref)
11129                         continue;
11130
11131                 if (transcoder_master_readout(dev_priv, cpu_transcoder) ==
11132                     crtc_state->cpu_transcoder)
11133                         crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
11134
11135                 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
11136         }
11137
11138         drm_WARN_ON(&dev_priv->drm,
11139                     crtc_state->master_transcoder != INVALID_TRANSCODER &&
11140                     crtc_state->sync_mode_slaves_mask);
11141 }
11142
11143 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
11144                                 struct intel_crtc_state *pipe_config)
11145 {
11146         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11147         intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf;
11148         enum intel_display_power_domain power_domain;
11149         u64 power_domain_mask;
11150         bool active;
11151         u32 tmp;
11152
11153         pipe_config->master_transcoder = INVALID_TRANSCODER;
11154
11155         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
11156         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11157         if (!wf)
11158                 return false;
11159
11160         wakerefs[power_domain] = wf;
11161         power_domain_mask = BIT_ULL(power_domain);
11162
11163         pipe_config->shared_dpll = NULL;
11164
11165         active = hsw_get_transcoder_state(crtc, pipe_config,
11166                                           &power_domain_mask, wakerefs);
11167
11168         if (IS_GEN9_LP(dev_priv) &&
11169             bxt_get_dsi_transcoder_state(crtc, pipe_config,
11170                                          &power_domain_mask, wakerefs)) {
11171                 drm_WARN_ON(&dev_priv->drm, active);
11172                 active = true;
11173         }
11174
11175         if (!active)
11176                 goto out;
11177
11178         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
11179             INTEL_GEN(dev_priv) >= 11) {
11180                 hsw_get_ddi_port_state(crtc, pipe_config);
11181                 intel_get_pipe_timings(crtc, pipe_config);
11182         }
11183
11184         intel_get_pipe_src_size(crtc, pipe_config);
11185
11186         if (IS_HASWELL(dev_priv)) {
11187                 u32 tmp = intel_de_read(dev_priv,
11188                                         PIPECONF(pipe_config->cpu_transcoder));
11189
11190                 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
11191                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
11192                 else
11193                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
11194         } else {
11195                 pipe_config->output_format =
11196                         bdw_get_pipemisc_output_format(crtc);
11197
11198                 /*
11199                  * Currently there is no interface defined to
11200                  * check user preference between RGB/YCBCR444
11201                  * or YCBCR420. So the only possible case for
11202                  * YCBCR444 usage is driving YCBCR420 output
11203                  * with LSPCON, when pipe is configured for
11204                  * YCBCR444 output and LSPCON takes care of
11205                  * downsampling it.
11206                  */
11207                 pipe_config->lspcon_downsampling =
11208                         pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444;
11209         }
11210
11211         pipe_config->gamma_mode = intel_de_read(dev_priv,
11212                                                 GAMMA_MODE(crtc->pipe));
11213
11214         pipe_config->csc_mode = intel_de_read(dev_priv,
11215                                               PIPE_CSC_MODE(crtc->pipe));
11216
11217         if (INTEL_GEN(dev_priv) >= 9) {
11218                 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
11219
11220                 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
11221                         pipe_config->gamma_enable = true;
11222
11223                 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
11224                         pipe_config->csc_enable = true;
11225         } else {
11226                 i9xx_get_pipe_color_config(pipe_config);
11227         }
11228
11229         intel_color_get_config(pipe_config);
11230
11231         tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
11232         pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
11233         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
11234                 pipe_config->ips_linetime =
11235                         REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
11236
11237         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
11238         drm_WARN_ON(&dev_priv->drm, power_domain_mask & BIT_ULL(power_domain));
11239
11240         wf = intel_display_power_get_if_enabled(dev_priv, power_domain);
11241         if (wf) {
11242                 wakerefs[power_domain] = wf;
11243                 power_domain_mask |= BIT_ULL(power_domain);
11244
11245                 if (INTEL_GEN(dev_priv) >= 9)
11246                         skl_get_pfit_config(crtc, pipe_config);
11247                 else
11248                         ilk_get_pfit_config(crtc, pipe_config);
11249         }
11250
11251         if (hsw_crtc_supports_ips(crtc)) {
11252                 if (IS_HASWELL(dev_priv))
11253                         pipe_config->ips_enabled = intel_de_read(dev_priv,
11254                                                                  IPS_CTL) & IPS_ENABLE;
11255                 else {
11256                         /*
11257                          * We cannot readout IPS state on broadwell, set to
11258                          * true so we can set it to a defined state on first
11259                          * commit.
11260                          */
11261                         pipe_config->ips_enabled = true;
11262                 }
11263         }
11264
11265         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
11266             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
11267                 pipe_config->pixel_multiplier =
11268                         intel_de_read(dev_priv,
11269                                       PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
11270         } else {
11271                 pipe_config->pixel_multiplier = 1;
11272         }
11273
11274         if (INTEL_GEN(dev_priv) >= 11 &&
11275             !transcoder_is_dsi(pipe_config->cpu_transcoder))
11276                 icl_get_trans_port_sync_config(pipe_config);
11277
11278 out:
11279         for_each_power_domain(power_domain, power_domain_mask)
11280                 intel_display_power_put(dev_priv,
11281                                         power_domain, wakerefs[power_domain]);
11282
11283         return active;
11284 }
11285
11286 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
11287 {
11288         struct drm_i915_private *dev_priv =
11289                 to_i915(plane_state->uapi.plane->dev);
11290         const struct drm_framebuffer *fb = plane_state->hw.fb;
11291         const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11292         u32 base;
11293
11294         if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
11295                 base = sg_dma_address(obj->mm.pages->sgl);
11296         else
11297                 base = intel_plane_ggtt_offset(plane_state);
11298
11299         return base + plane_state->color_plane[0].offset;
11300 }
11301
11302 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
11303 {
11304         int x = plane_state->uapi.dst.x1;
11305         int y = plane_state->uapi.dst.y1;
11306         u32 pos = 0;
11307
11308         if (x < 0) {
11309                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
11310                 x = -x;
11311         }
11312         pos |= x << CURSOR_X_SHIFT;
11313
11314         if (y < 0) {
11315                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
11316                 y = -y;
11317         }
11318         pos |= y << CURSOR_Y_SHIFT;
11319
11320         return pos;
11321 }
11322
11323 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
11324 {
11325         const struct drm_mode_config *config =
11326                 &plane_state->uapi.plane->dev->mode_config;
11327         int width = drm_rect_width(&plane_state->uapi.dst);
11328         int height = drm_rect_height(&plane_state->uapi.dst);
11329
11330         return width > 0 && width <= config->cursor_width &&
11331                 height > 0 && height <= config->cursor_height;
11332 }
11333
11334 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
11335 {
11336         struct drm_i915_private *dev_priv =
11337                 to_i915(plane_state->uapi.plane->dev);
11338         unsigned int rotation = plane_state->hw.rotation;
11339         int src_x, src_y;
11340         u32 offset;
11341         int ret;
11342
11343         ret = intel_plane_compute_gtt(plane_state);
11344         if (ret)
11345                 return ret;
11346
11347         if (!plane_state->uapi.visible)
11348                 return 0;
11349
11350         src_x = plane_state->uapi.src.x1 >> 16;
11351         src_y = plane_state->uapi.src.y1 >> 16;
11352
11353         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
11354         offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
11355                                                     plane_state, 0);
11356
11357         if (src_x != 0 || src_y != 0) {
11358                 drm_dbg_kms(&dev_priv->drm,
11359                             "Arbitrary cursor panning not supported\n");
11360                 return -EINVAL;
11361         }
11362
11363         /*
11364          * Put the final coordinates back so that the src
11365          * coordinate checks will see the right values.
11366          */
11367         drm_rect_translate_to(&plane_state->uapi.src,
11368                               src_x << 16, src_y << 16);
11369
11370         /* ILK+ do this automagically in hardware */
11371         if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
11372                 const struct drm_framebuffer *fb = plane_state->hw.fb;
11373                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
11374                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
11375
11376                 offset += (src_h * src_w - 1) * fb->format->cpp[0];
11377         }
11378
11379         plane_state->color_plane[0].offset = offset;
11380         plane_state->color_plane[0].x = src_x;
11381         plane_state->color_plane[0].y = src_y;
11382
11383         return 0;
11384 }
11385
11386 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
11387                               struct intel_plane_state *plane_state)
11388 {
11389         const struct drm_framebuffer *fb = plane_state->hw.fb;
11390         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
11391         int ret;
11392
11393         if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
11394                 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n");
11395                 return -EINVAL;
11396         }
11397
11398         ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
11399                                                   &crtc_state->uapi,
11400                                                   DRM_PLANE_HELPER_NO_SCALING,
11401                                                   DRM_PLANE_HELPER_NO_SCALING,
11402                                                   true, true);
11403         if (ret)
11404                 return ret;
11405
11406         /* Use the unclipped src/dst rectangles, which we program to hw */
11407         plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi);
11408         plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi);
11409
11410         ret = intel_cursor_check_surface(plane_state);
11411         if (ret)
11412                 return ret;
11413
11414         if (!plane_state->uapi.visible)
11415                 return 0;
11416
11417         ret = intel_plane_check_src_coordinates(plane_state);
11418         if (ret)
11419                 return ret;
11420
11421         return 0;
11422 }
11423
11424 static unsigned int
11425 i845_cursor_max_stride(struct intel_plane *plane,
11426                        u32 pixel_format, u64 modifier,
11427                        unsigned int rotation)
11428 {
11429         return 2048;
11430 }
11431
11432 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11433 {
11434         u32 cntl = 0;
11435
11436         if (crtc_state->gamma_enable)
11437                 cntl |= CURSOR_GAMMA_ENABLE;
11438
11439         return cntl;
11440 }
11441
11442 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
11443                            const struct intel_plane_state *plane_state)
11444 {
11445         return CURSOR_ENABLE |
11446                 CURSOR_FORMAT_ARGB |
11447                 CURSOR_STRIDE(plane_state->color_plane[0].stride);
11448 }
11449
11450 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
11451 {
11452         int width = drm_rect_width(&plane_state->uapi.dst);
11453
11454         /*
11455          * 845g/865g are only limited by the width of their cursors,
11456          * the height is arbitrary up to the precision of the register.
11457          */
11458         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
11459 }
11460
11461 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
11462                              struct intel_plane_state *plane_state)
11463 {
11464         const struct drm_framebuffer *fb = plane_state->hw.fb;
11465         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
11466         int ret;
11467
11468         ret = intel_check_cursor(crtc_state, plane_state);
11469         if (ret)
11470                 return ret;
11471
11472         /* if we want to turn off the cursor ignore width and height */
11473         if (!fb)
11474                 return 0;
11475
11476         /* Check for which cursor types we support */
11477         if (!i845_cursor_size_ok(plane_state)) {
11478                 drm_dbg_kms(&i915->drm,
11479                             "Cursor dimension %dx%d not supported\n",
11480                             drm_rect_width(&plane_state->uapi.dst),
11481                             drm_rect_height(&plane_state->uapi.dst));
11482                 return -EINVAL;
11483         }
11484
11485         drm_WARN_ON(&i915->drm, plane_state->uapi.visible &&
11486                     plane_state->color_plane[0].stride != fb->pitches[0]);
11487
11488         switch (fb->pitches[0]) {
11489         case 256:
11490         case 512:
11491         case 1024:
11492         case 2048:
11493                 break;
11494         default:
11495                  drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n",
11496                              fb->pitches[0]);
11497                 return -EINVAL;
11498         }
11499
11500         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
11501
11502         return 0;
11503 }
11504
11505 static void i845_update_cursor(struct intel_plane *plane,
11506                                const struct intel_crtc_state *crtc_state,
11507                                const struct intel_plane_state *plane_state)
11508 {
11509         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11510         u32 cntl = 0, base = 0, pos = 0, size = 0;
11511         unsigned long irqflags;
11512
11513         if (plane_state && plane_state->uapi.visible) {
11514                 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
11515                 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
11516
11517                 cntl = plane_state->ctl |
11518                         i845_cursor_ctl_crtc(crtc_state);
11519
11520                 size = (height << 12) | width;
11521
11522                 base = intel_cursor_base(plane_state);
11523                 pos = intel_cursor_position(plane_state);
11524         }
11525
11526         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11527
11528         /* On these chipsets we can only modify the base/size/stride
11529          * whilst the cursor is disabled.
11530          */
11531         if (plane->cursor.base != base ||
11532             plane->cursor.size != size ||
11533             plane->cursor.cntl != cntl) {
11534                 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
11535                 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
11536                 intel_de_write_fw(dev_priv, CURSIZE, size);
11537                 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
11538                 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
11539
11540                 plane->cursor.base = base;
11541                 plane->cursor.size = size;
11542                 plane->cursor.cntl = cntl;
11543         } else {
11544                 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
11545         }
11546
11547         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11548 }
11549
11550 static void i845_disable_cursor(struct intel_plane *plane,
11551                                 const struct intel_crtc_state *crtc_state)
11552 {
11553         i845_update_cursor(plane, crtc_state, NULL);
11554 }
11555
11556 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
11557                                      enum pipe *pipe)
11558 {
11559         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11560         enum intel_display_power_domain power_domain;
11561         intel_wakeref_t wakeref;
11562         bool ret;
11563
11564         power_domain = POWER_DOMAIN_PIPE(PIPE_A);
11565         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11566         if (!wakeref)
11567                 return false;
11568
11569         ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
11570
11571         *pipe = PIPE_A;
11572
11573         intel_display_power_put(dev_priv, power_domain, wakeref);
11574
11575         return ret;
11576 }
11577
11578 static unsigned int
11579 i9xx_cursor_max_stride(struct intel_plane *plane,
11580                        u32 pixel_format, u64 modifier,
11581                        unsigned int rotation)
11582 {
11583         return plane->base.dev->mode_config.cursor_width * 4;
11584 }
11585
11586 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
11587 {
11588         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
11589         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11590         u32 cntl = 0;
11591
11592         if (INTEL_GEN(dev_priv) >= 11)
11593                 return cntl;
11594
11595         if (crtc_state->gamma_enable)
11596                 cntl = MCURSOR_GAMMA_ENABLE;
11597
11598         if (crtc_state->csc_enable)
11599                 cntl |= MCURSOR_PIPE_CSC_ENABLE;
11600
11601         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11602                 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
11603
11604         return cntl;
11605 }
11606
11607 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
11608                            const struct intel_plane_state *plane_state)
11609 {
11610         struct drm_i915_private *dev_priv =
11611                 to_i915(plane_state->uapi.plane->dev);
11612         u32 cntl = 0;
11613
11614         if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
11615                 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
11616
11617         switch (drm_rect_width(&plane_state->uapi.dst)) {
11618         case 64:
11619                 cntl |= MCURSOR_MODE_64_ARGB_AX;
11620                 break;
11621         case 128:
11622                 cntl |= MCURSOR_MODE_128_ARGB_AX;
11623                 break;
11624         case 256:
11625                 cntl |= MCURSOR_MODE_256_ARGB_AX;
11626                 break;
11627         default:
11628                 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
11629                 return 0;
11630         }
11631
11632         if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
11633                 cntl |= MCURSOR_ROTATE_180;
11634
11635         return cntl;
11636 }
11637
11638 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
11639 {
11640         struct drm_i915_private *dev_priv =
11641                 to_i915(plane_state->uapi.plane->dev);
11642         int width = drm_rect_width(&plane_state->uapi.dst);
11643         int height = drm_rect_height(&plane_state->uapi.dst);
11644
11645         if (!intel_cursor_size_ok(plane_state))
11646                 return false;
11647
11648         /* Cursor width is limited to a few power-of-two sizes */
11649         switch (width) {
11650         case 256:
11651         case 128:
11652         case 64:
11653                 break;
11654         default:
11655                 return false;
11656         }
11657
11658         /*
11659          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
11660          * height from 8 lines up to the cursor width, when the
11661          * cursor is not rotated. Everything else requires square
11662          * cursors.
11663          */
11664         if (HAS_CUR_FBC(dev_priv) &&
11665             plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
11666                 if (height < 8 || height > width)
11667                         return false;
11668         } else {
11669                 if (height != width)
11670                         return false;
11671         }
11672
11673         return true;
11674 }
11675
11676 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
11677                              struct intel_plane_state *plane_state)
11678 {
11679         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
11680         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11681         const struct drm_framebuffer *fb = plane_state->hw.fb;
11682         enum pipe pipe = plane->pipe;
11683         int ret;
11684
11685         ret = intel_check_cursor(crtc_state, plane_state);
11686         if (ret)
11687                 return ret;
11688
11689         /* if we want to turn off the cursor ignore width and height */
11690         if (!fb)
11691                 return 0;
11692
11693         /* Check for which cursor types we support */
11694         if (!i9xx_cursor_size_ok(plane_state)) {
11695                 drm_dbg(&dev_priv->drm,
11696                         "Cursor dimension %dx%d not supported\n",
11697                         drm_rect_width(&plane_state->uapi.dst),
11698                         drm_rect_height(&plane_state->uapi.dst));
11699                 return -EINVAL;
11700         }
11701
11702         drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&
11703                     plane_state->color_plane[0].stride != fb->pitches[0]);
11704
11705         if (fb->pitches[0] !=
11706             drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
11707                 drm_dbg_kms(&dev_priv->drm,
11708                             "Invalid cursor stride (%u) (cursor width %d)\n",
11709                             fb->pitches[0],
11710                             drm_rect_width(&plane_state->uapi.dst));
11711                 return -EINVAL;
11712         }
11713
11714         /*
11715          * There's something wrong with the cursor on CHV pipe C.
11716          * If it straddles the left edge of the screen then
11717          * moving it away from the edge or disabling it often
11718          * results in a pipe underrun, and often that can lead to
11719          * dead pipe (constant underrun reported, and it scans
11720          * out just a solid color). To recover from that, the
11721          * display power well must be turned off and on again.
11722          * Refuse the put the cursor into that compromised position.
11723          */
11724         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
11725             plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
11726                 drm_dbg_kms(&dev_priv->drm,
11727                             "CHV cursor C not allowed to straddle the left screen edge\n");
11728                 return -EINVAL;
11729         }
11730
11731         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
11732
11733         return 0;
11734 }
11735
11736 static void i9xx_update_cursor(struct intel_plane *plane,
11737                                const struct intel_crtc_state *crtc_state,
11738                                const struct intel_plane_state *plane_state)
11739 {
11740         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11741         enum pipe pipe = plane->pipe;
11742         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
11743         unsigned long irqflags;
11744
11745         if (plane_state && plane_state->uapi.visible) {
11746                 unsigned width = drm_rect_width(&plane_state->uapi.dst);
11747                 unsigned height = drm_rect_height(&plane_state->uapi.dst);
11748
11749                 cntl = plane_state->ctl |
11750                         i9xx_cursor_ctl_crtc(crtc_state);
11751
11752                 if (width != height)
11753                         fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
11754
11755                 base = intel_cursor_base(plane_state);
11756                 pos = intel_cursor_position(plane_state);
11757         }
11758
11759         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
11760
11761         /*
11762          * On some platforms writing CURCNTR first will also
11763          * cause CURPOS to be armed by the CURBASE write.
11764          * Without the CURCNTR write the CURPOS write would
11765          * arm itself. Thus we always update CURCNTR before
11766          * CURPOS.
11767          *
11768          * On other platforms CURPOS always requires the
11769          * CURBASE write to arm the update. Additonally
11770          * a write to any of the cursor register will cancel
11771          * an already armed cursor update. Thus leaving out
11772          * the CURBASE write after CURPOS could lead to a
11773          * cursor that doesn't appear to move, or even change
11774          * shape. Thus we always write CURBASE.
11775          *
11776          * The other registers are armed by by the CURBASE write
11777          * except when the plane is getting enabled at which time
11778          * the CURCNTR write arms the update.
11779          */
11780
11781         if (INTEL_GEN(dev_priv) >= 9)
11782                 skl_write_cursor_wm(plane, crtc_state);
11783
11784         if (plane->cursor.base != base ||
11785             plane->cursor.size != fbc_ctl ||
11786             plane->cursor.cntl != cntl) {
11787                 if (HAS_CUR_FBC(dev_priv))
11788                         intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
11789                                           fbc_ctl);
11790                 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
11791                 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
11792                 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
11793
11794                 plane->cursor.base = base;
11795                 plane->cursor.size = fbc_ctl;
11796                 plane->cursor.cntl = cntl;
11797         } else {
11798                 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
11799                 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
11800         }
11801
11802         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
11803 }
11804
11805 static void i9xx_disable_cursor(struct intel_plane *plane,
11806                                 const struct intel_crtc_state *crtc_state)
11807 {
11808         i9xx_update_cursor(plane, crtc_state, NULL);
11809 }
11810
11811 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
11812                                      enum pipe *pipe)
11813 {
11814         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
11815         enum intel_display_power_domain power_domain;
11816         intel_wakeref_t wakeref;
11817         bool ret;
11818         u32 val;
11819
11820         /*
11821          * Not 100% correct for planes that can move between pipes,
11822          * but that's only the case for gen2-3 which don't have any
11823          * display power wells.
11824          */
11825         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
11826         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
11827         if (!wakeref)
11828                 return false;
11829
11830         val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
11831
11832         ret = val & MCURSOR_MODE;
11833
11834         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
11835                 *pipe = plane->pipe;
11836         else
11837                 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
11838                         MCURSOR_PIPE_SELECT_SHIFT;
11839
11840         intel_display_power_put(dev_priv, power_domain, wakeref);
11841
11842         return ret;
11843 }
11844
11845 /* VESA 640x480x72Hz mode to set on the pipe */
11846 static const struct drm_display_mode load_detect_mode = {
11847         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
11848                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
11849 };
11850
11851 struct drm_framebuffer *
11852 intel_framebuffer_create(struct drm_i915_gem_object *obj,
11853                          struct drm_mode_fb_cmd2 *mode_cmd)
11854 {
11855         struct intel_framebuffer *intel_fb;
11856         int ret;
11857
11858         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
11859         if (!intel_fb)
11860                 return ERR_PTR(-ENOMEM);
11861
11862         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
11863         if (ret)
11864                 goto err;
11865
11866         return &intel_fb->base;
11867
11868 err:
11869         kfree(intel_fb);
11870         return ERR_PTR(ret);
11871 }
11872
11873 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
11874                                         struct drm_crtc *crtc)
11875 {
11876         struct drm_plane *plane;
11877         struct drm_plane_state *plane_state;
11878         int ret, i;
11879
11880         ret = drm_atomic_add_affected_planes(state, crtc);
11881         if (ret)
11882                 return ret;
11883
11884         for_each_new_plane_in_state(state, plane, plane_state, i) {
11885                 if (plane_state->crtc != crtc)
11886                         continue;
11887
11888                 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
11889                 if (ret)
11890                         return ret;
11891
11892                 drm_atomic_set_fb_for_plane(plane_state, NULL);
11893         }
11894
11895         return 0;
11896 }
11897
11898 int intel_get_load_detect_pipe(struct drm_connector *connector,
11899                                struct intel_load_detect_pipe *old,
11900                                struct drm_modeset_acquire_ctx *ctx)
11901 {
11902         struct intel_crtc *intel_crtc;
11903         struct intel_encoder *intel_encoder =
11904                 intel_attached_encoder(to_intel_connector(connector));
11905         struct drm_crtc *possible_crtc;
11906         struct drm_encoder *encoder = &intel_encoder->base;
11907         struct drm_crtc *crtc = NULL;
11908         struct drm_device *dev = encoder->dev;
11909         struct drm_i915_private *dev_priv = to_i915(dev);
11910         struct drm_mode_config *config = &dev->mode_config;
11911         struct drm_atomic_state *state = NULL, *restore_state = NULL;
11912         struct drm_connector_state *connector_state;
11913         struct intel_crtc_state *crtc_state;
11914         int ret, i = -1;
11915
11916         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11917                     connector->base.id, connector->name,
11918                     encoder->base.id, encoder->name);
11919
11920         old->restore_state = NULL;
11921
11922         drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
11923
11924         /*
11925          * Algorithm gets a little messy:
11926          *
11927          *   - if the connector already has an assigned crtc, use it (but make
11928          *     sure it's on first)
11929          *
11930          *   - try to find the first unused crtc that can drive this connector,
11931          *     and use that if we find one
11932          */
11933
11934         /* See if we already have a CRTC for this connector */
11935         if (connector->state->crtc) {
11936                 crtc = connector->state->crtc;
11937
11938                 ret = drm_modeset_lock(&crtc->mutex, ctx);
11939                 if (ret)
11940                         goto fail;
11941
11942                 /* Make sure the crtc and connector are running */
11943                 goto found;
11944         }
11945
11946         /* Find an unused one (if possible) */
11947         for_each_crtc(dev, possible_crtc) {
11948                 i++;
11949                 if (!(encoder->possible_crtcs & (1 << i)))
11950                         continue;
11951
11952                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11953                 if (ret)
11954                         goto fail;
11955
11956                 if (possible_crtc->state->enable) {
11957                         drm_modeset_unlock(&possible_crtc->mutex);
11958                         continue;
11959                 }
11960
11961                 crtc = possible_crtc;
11962                 break;
11963         }
11964
11965         /*
11966          * If we didn't find an unused CRTC, don't use any.
11967          */
11968         if (!crtc) {
11969                 drm_dbg_kms(&dev_priv->drm,
11970                             "no pipe available for load-detect\n");
11971                 ret = -ENODEV;
11972                 goto fail;
11973         }
11974
11975 found:
11976         intel_crtc = to_intel_crtc(crtc);
11977
11978         state = drm_atomic_state_alloc(dev);
11979         restore_state = drm_atomic_state_alloc(dev);
11980         if (!state || !restore_state) {
11981                 ret = -ENOMEM;
11982                 goto fail;
11983         }
11984
11985         state->acquire_ctx = ctx;
11986         restore_state->acquire_ctx = ctx;
11987
11988         connector_state = drm_atomic_get_connector_state(state, connector);
11989         if (IS_ERR(connector_state)) {
11990                 ret = PTR_ERR(connector_state);
11991                 goto fail;
11992         }
11993
11994         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11995         if (ret)
11996                 goto fail;
11997
11998         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11999         if (IS_ERR(crtc_state)) {
12000                 ret = PTR_ERR(crtc_state);
12001                 goto fail;
12002         }
12003
12004         crtc_state->uapi.active = true;
12005
12006         ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
12007                                            &load_detect_mode);
12008         if (ret)
12009                 goto fail;
12010
12011         ret = intel_modeset_disable_planes(state, crtc);
12012         if (ret)
12013                 goto fail;
12014
12015         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
12016         if (!ret)
12017                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
12018         if (!ret)
12019                 ret = drm_atomic_add_affected_planes(restore_state, crtc);
12020         if (ret) {
12021                 drm_dbg_kms(&dev_priv->drm,
12022                             "Failed to create a copy of old state to restore: %i\n",
12023                             ret);
12024                 goto fail;
12025         }
12026
12027         ret = drm_atomic_commit(state);
12028         if (ret) {
12029                 drm_dbg_kms(&dev_priv->drm,
12030                             "failed to set mode on load-detect pipe\n");
12031                 goto fail;
12032         }
12033
12034         old->restore_state = restore_state;
12035         drm_atomic_state_put(state);
12036
12037         /* let the connector get through one full cycle before testing */
12038         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
12039         return true;
12040
12041 fail:
12042         if (state) {
12043                 drm_atomic_state_put(state);
12044                 state = NULL;
12045         }
12046         if (restore_state) {
12047                 drm_atomic_state_put(restore_state);
12048                 restore_state = NULL;
12049         }
12050
12051         if (ret == -EDEADLK)
12052                 return ret;
12053
12054         return false;
12055 }
12056
12057 void intel_release_load_detect_pipe(struct drm_connector *connector,
12058                                     struct intel_load_detect_pipe *old,
12059                                     struct drm_modeset_acquire_ctx *ctx)
12060 {
12061         struct intel_encoder *intel_encoder =
12062                 intel_attached_encoder(to_intel_connector(connector));
12063         struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
12064         struct drm_encoder *encoder = &intel_encoder->base;
12065         struct drm_atomic_state *state = old->restore_state;
12066         int ret;
12067
12068         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
12069                     connector->base.id, connector->name,
12070                     encoder->base.id, encoder->name);
12071
12072         if (!state)
12073                 return;
12074
12075         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
12076         if (ret)
12077                 drm_dbg_kms(&i915->drm,
12078                             "Couldn't release load detect pipe: %i\n", ret);
12079         drm_atomic_state_put(state);
12080 }
12081
12082 static int i9xx_pll_refclk(struct drm_device *dev,
12083                            const struct intel_crtc_state *pipe_config)
12084 {
12085         struct drm_i915_private *dev_priv = to_i915(dev);
12086         u32 dpll = pipe_config->dpll_hw_state.dpll;
12087
12088         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
12089                 return dev_priv->vbt.lvds_ssc_freq;
12090         else if (HAS_PCH_SPLIT(dev_priv))
12091                 return 120000;
12092         else if (!IS_GEN(dev_priv, 2))
12093                 return 96000;
12094         else
12095                 return 48000;
12096 }
12097
12098 /* Returns the clock of the currently programmed mode of the given pipe. */
12099 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
12100                                 struct intel_crtc_state *pipe_config)
12101 {
12102         struct drm_device *dev = crtc->base.dev;
12103         struct drm_i915_private *dev_priv = to_i915(dev);
12104         enum pipe pipe = crtc->pipe;
12105         u32 dpll = pipe_config->dpll_hw_state.dpll;
12106         u32 fp;
12107         struct dpll clock;
12108         int port_clock;
12109         int refclk = i9xx_pll_refclk(dev, pipe_config);
12110
12111         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
12112                 fp = pipe_config->dpll_hw_state.fp0;
12113         else
12114                 fp = pipe_config->dpll_hw_state.fp1;
12115
12116         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
12117         if (IS_PINEVIEW(dev_priv)) {
12118                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
12119                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
12120         } else {
12121                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
12122                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
12123         }
12124
12125         if (!IS_GEN(dev_priv, 2)) {
12126                 if (IS_PINEVIEW(dev_priv))
12127                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
12128                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
12129                 else
12130                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
12131                                DPLL_FPA01_P1_POST_DIV_SHIFT);
12132
12133                 switch (dpll & DPLL_MODE_MASK) {
12134                 case DPLLB_MODE_DAC_SERIAL:
12135                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
12136                                 5 : 10;
12137                         break;
12138                 case DPLLB_MODE_LVDS:
12139                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
12140                                 7 : 14;
12141                         break;
12142                 default:
12143                         drm_dbg_kms(&dev_priv->drm,
12144                                     "Unknown DPLL mode %08x in programmed "
12145                                     "mode\n", (int)(dpll & DPLL_MODE_MASK));
12146                         return;
12147                 }
12148
12149                 if (IS_PINEVIEW(dev_priv))
12150                         port_clock = pnv_calc_dpll_params(refclk, &clock);
12151                 else
12152                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
12153         } else {
12154                 u32 lvds = IS_I830(dev_priv) ? 0 : intel_de_read(dev_priv,
12155                                                                  LVDS);
12156                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
12157
12158                 if (is_lvds) {
12159                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
12160                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
12161
12162                         if (lvds & LVDS_CLKB_POWER_UP)
12163                                 clock.p2 = 7;
12164                         else
12165                                 clock.p2 = 14;
12166                 } else {
12167                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
12168                                 clock.p1 = 2;
12169                         else {
12170                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
12171                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
12172                         }
12173                         if (dpll & PLL_P2_DIVIDE_BY_4)
12174                                 clock.p2 = 4;
12175                         else
12176                                 clock.p2 = 2;
12177                 }
12178
12179                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
12180         }
12181
12182         /*
12183          * This value includes pixel_multiplier. We will use
12184          * port_clock to compute adjusted_mode.crtc_clock in the
12185          * encoder's get_config() function.
12186          */
12187         pipe_config->port_clock = port_clock;
12188 }
12189
12190 int intel_dotclock_calculate(int link_freq,
12191                              const struct intel_link_m_n *m_n)
12192 {
12193         /*
12194          * The calculation for the data clock is:
12195          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
12196          * But we want to avoid losing precison if possible, so:
12197          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
12198          *
12199          * and the link clock is simpler:
12200          * link_clock = (m * link_clock) / n
12201          */
12202
12203         if (!m_n->link_n)
12204                 return 0;
12205
12206         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
12207 }
12208
12209 static void ilk_pch_clock_get(struct intel_crtc *crtc,
12210                               struct intel_crtc_state *pipe_config)
12211 {
12212         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12213
12214         /* read out port_clock from the DPLL */
12215         i9xx_crtc_clock_get(crtc, pipe_config);
12216
12217         /*
12218          * In case there is an active pipe without active ports,
12219          * we may need some idea for the dotclock anyway.
12220          * Calculate one based on the FDI configuration.
12221          */
12222         pipe_config->hw.adjusted_mode.crtc_clock =
12223                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12224                                          &pipe_config->fdi_m_n);
12225 }
12226
12227 static void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
12228                                    struct intel_crtc *crtc)
12229 {
12230         memset(crtc_state, 0, sizeof(*crtc_state));
12231
12232         __drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base);
12233
12234         crtc_state->cpu_transcoder = INVALID_TRANSCODER;
12235         crtc_state->master_transcoder = INVALID_TRANSCODER;
12236         crtc_state->hsw_workaround_pipe = INVALID_PIPE;
12237         crtc_state->output_format = INTEL_OUTPUT_FORMAT_INVALID;
12238         crtc_state->scaler_state.scaler_id = -1;
12239         crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
12240 }
12241
12242 static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc)
12243 {
12244         struct intel_crtc_state *crtc_state;
12245
12246         crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL);
12247
12248         if (crtc_state)
12249                 intel_crtc_state_reset(crtc_state, crtc);
12250
12251         return crtc_state;
12252 }
12253
12254 /* Returns the currently programmed mode of the given encoder. */
12255 struct drm_display_mode *
12256 intel_encoder_current_mode(struct intel_encoder *encoder)
12257 {
12258         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
12259         struct intel_crtc_state *crtc_state;
12260         struct drm_display_mode *mode;
12261         struct intel_crtc *crtc;
12262         enum pipe pipe;
12263
12264         if (!encoder->get_hw_state(encoder, &pipe))
12265                 return NULL;
12266
12267         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
12268
12269         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
12270         if (!mode)
12271                 return NULL;
12272
12273         crtc_state = intel_crtc_state_alloc(crtc);
12274         if (!crtc_state) {
12275                 kfree(mode);
12276                 return NULL;
12277         }
12278
12279         if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {
12280                 kfree(crtc_state);
12281                 kfree(mode);
12282                 return NULL;
12283         }
12284
12285         encoder->get_config(encoder, crtc_state);
12286
12287         intel_mode_from_pipe_config(mode, crtc_state);
12288
12289         kfree(crtc_state);
12290
12291         return mode;
12292 }
12293
12294 static void intel_crtc_destroy(struct drm_crtc *crtc)
12295 {
12296         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12297
12298         drm_crtc_cleanup(crtc);
12299         kfree(intel_crtc);
12300 }
12301
12302 /**
12303  * intel_wm_need_update - Check whether watermarks need updating
12304  * @cur: current plane state
12305  * @new: new plane state
12306  *
12307  * Check current plane state versus the new one to determine whether
12308  * watermarks need to be recalculated.
12309  *
12310  * Returns true or false.
12311  */
12312 static bool intel_wm_need_update(const struct intel_plane_state *cur,
12313                                  struct intel_plane_state *new)
12314 {
12315         /* Update watermarks on tiling or size changes. */
12316         if (new->uapi.visible != cur->uapi.visible)
12317                 return true;
12318
12319         if (!cur->hw.fb || !new->hw.fb)
12320                 return false;
12321
12322         if (cur->hw.fb->modifier != new->hw.fb->modifier ||
12323             cur->hw.rotation != new->hw.rotation ||
12324             drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
12325             drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
12326             drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
12327             drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
12328                 return true;
12329
12330         return false;
12331 }
12332
12333 static bool needs_scaling(const struct intel_plane_state *state)
12334 {
12335         int src_w = drm_rect_width(&state->uapi.src) >> 16;
12336         int src_h = drm_rect_height(&state->uapi.src) >> 16;
12337         int dst_w = drm_rect_width(&state->uapi.dst);
12338         int dst_h = drm_rect_height(&state->uapi.dst);
12339
12340         return (src_w != dst_w || src_h != dst_h);
12341 }
12342
12343 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
12344                                     struct intel_crtc_state *crtc_state,
12345                                     const struct intel_plane_state *old_plane_state,
12346                                     struct intel_plane_state *plane_state)
12347 {
12348         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12349         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
12350         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12351         bool mode_changed = needs_modeset(crtc_state);
12352         bool was_crtc_enabled = old_crtc_state->hw.active;
12353         bool is_crtc_enabled = crtc_state->hw.active;
12354         bool turn_off, turn_on, visible, was_visible;
12355         int ret;
12356
12357         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
12358                 ret = skl_update_scaler_plane(crtc_state, plane_state);
12359                 if (ret)
12360                         return ret;
12361         }
12362
12363         was_visible = old_plane_state->uapi.visible;
12364         visible = plane_state->uapi.visible;
12365
12366         if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
12367                 was_visible = false;
12368
12369         /*
12370          * Visibility is calculated as if the crtc was on, but
12371          * after scaler setup everything depends on it being off
12372          * when the crtc isn't active.
12373          *
12374          * FIXME this is wrong for watermarks. Watermarks should also
12375          * be computed as if the pipe would be active. Perhaps move
12376          * per-plane wm computation to the .check_plane() hook, and
12377          * only combine the results from all planes in the current place?
12378          */
12379         if (!is_crtc_enabled) {
12380                 plane_state->uapi.visible = visible = false;
12381                 crtc_state->active_planes &= ~BIT(plane->id);
12382                 crtc_state->data_rate[plane->id] = 0;
12383                 crtc_state->min_cdclk[plane->id] = 0;
12384         }
12385
12386         if (!was_visible && !visible)
12387                 return 0;
12388
12389         turn_off = was_visible && (!visible || mode_changed);
12390         turn_on = visible && (!was_visible || mode_changed);
12391
12392         drm_dbg_atomic(&dev_priv->drm,
12393                        "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12394                        crtc->base.base.id, crtc->base.name,
12395                        plane->base.base.id, plane->base.name,
12396                        was_visible, visible,
12397                        turn_off, turn_on, mode_changed);
12398
12399         if (turn_on) {
12400                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
12401                         crtc_state->update_wm_pre = true;
12402
12403                 /* must disable cxsr around plane enable/disable */
12404                 if (plane->id != PLANE_CURSOR)
12405                         crtc_state->disable_cxsr = true;
12406         } else if (turn_off) {
12407                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
12408                         crtc_state->update_wm_post = true;
12409
12410                 /* must disable cxsr around plane enable/disable */
12411                 if (plane->id != PLANE_CURSOR)
12412                         crtc_state->disable_cxsr = true;
12413         } else if (intel_wm_need_update(old_plane_state, plane_state)) {
12414                 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
12415                         /* FIXME bollocks */
12416                         crtc_state->update_wm_pre = true;
12417                         crtc_state->update_wm_post = true;
12418                 }
12419         }
12420
12421         if (visible || was_visible)
12422                 crtc_state->fb_bits |= plane->frontbuffer_bit;
12423
12424         /*
12425          * ILK/SNB DVSACNTR/Sprite Enable
12426          * IVB SPR_CTL/Sprite Enable
12427          * "When in Self Refresh Big FIFO mode, a write to enable the
12428          *  plane will be internally buffered and delayed while Big FIFO
12429          *  mode is exiting."
12430          *
12431          * Which means that enabling the sprite can take an extra frame
12432          * when we start in big FIFO mode (LP1+). Thus we need to drop
12433          * down to LP0 and wait for vblank in order to make sure the
12434          * sprite gets enabled on the next vblank after the register write.
12435          * Doing otherwise would risk enabling the sprite one frame after
12436          * we've already signalled flip completion. We can resume LP1+
12437          * once the sprite has been enabled.
12438          *
12439          *
12440          * WaCxSRDisabledForSpriteScaling:ivb
12441          * IVB SPR_SCALE/Scaling Enable
12442          * "Low Power watermarks must be disabled for at least one
12443          *  frame before enabling sprite scaling, and kept disabled
12444          *  until sprite scaling is disabled."
12445          *
12446          * ILK/SNB DVSASCALE/Scaling Enable
12447          * "When in Self Refresh Big FIFO mode, scaling enable will be
12448          *  masked off while Big FIFO mode is exiting."
12449          *
12450          * Despite the w/a only being listed for IVB we assume that
12451          * the ILK/SNB note has similar ramifications, hence we apply
12452          * the w/a on all three platforms.
12453          *
12454          * With experimental results seems this is needed also for primary
12455          * plane, not only sprite plane.
12456          */
12457         if (plane->id != PLANE_CURSOR &&
12458             (IS_GEN_RANGE(dev_priv, 5, 6) ||
12459              IS_IVYBRIDGE(dev_priv)) &&
12460             (turn_on || (!needs_scaling(old_plane_state) &&
12461                          needs_scaling(plane_state))))
12462                 crtc_state->disable_lp_wm = true;
12463
12464         return 0;
12465 }
12466
12467 static bool encoders_cloneable(const struct intel_encoder *a,
12468                                const struct intel_encoder *b)
12469 {
12470         /* masks could be asymmetric, so check both ways */
12471         return a == b || (a->cloneable & (1 << b->type) &&
12472                           b->cloneable & (1 << a->type));
12473 }
12474
12475 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12476                                          struct intel_crtc *crtc,
12477                                          struct intel_encoder *encoder)
12478 {
12479         struct intel_encoder *source_encoder;
12480         struct drm_connector *connector;
12481         struct drm_connector_state *connector_state;
12482         int i;
12483
12484         for_each_new_connector_in_state(state, connector, connector_state, i) {
12485                 if (connector_state->crtc != &crtc->base)
12486                         continue;
12487
12488                 source_encoder =
12489                         to_intel_encoder(connector_state->best_encoder);
12490                 if (!encoders_cloneable(encoder, source_encoder))
12491                         return false;
12492         }
12493
12494         return true;
12495 }
12496
12497 static int icl_add_linked_planes(struct intel_atomic_state *state)
12498 {
12499         struct intel_plane *plane, *linked;
12500         struct intel_plane_state *plane_state, *linked_plane_state;
12501         int i;
12502
12503         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12504                 linked = plane_state->planar_linked_plane;
12505
12506                 if (!linked)
12507                         continue;
12508
12509                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
12510                 if (IS_ERR(linked_plane_state))
12511                         return PTR_ERR(linked_plane_state);
12512
12513                 WARN_ON(linked_plane_state->planar_linked_plane != plane);
12514                 WARN_ON(linked_plane_state->planar_slave == plane_state->planar_slave);
12515         }
12516
12517         return 0;
12518 }
12519
12520 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
12521 {
12522         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12523         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12524         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
12525         struct intel_plane *plane, *linked;
12526         struct intel_plane_state *plane_state;
12527         int i;
12528
12529         if (INTEL_GEN(dev_priv) < 11)
12530                 return 0;
12531
12532         /*
12533          * Destroy all old plane links and make the slave plane invisible
12534          * in the crtc_state->active_planes mask.
12535          */
12536         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12537                 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
12538                         continue;
12539
12540                 plane_state->planar_linked_plane = NULL;
12541                 if (plane_state->planar_slave && !plane_state->uapi.visible) {
12542                         crtc_state->active_planes &= ~BIT(plane->id);
12543                         crtc_state->update_planes |= BIT(plane->id);
12544                 }
12545
12546                 plane_state->planar_slave = false;
12547         }
12548
12549         if (!crtc_state->nv12_planes)
12550                 return 0;
12551
12552         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
12553                 struct intel_plane_state *linked_state = NULL;
12554
12555                 if (plane->pipe != crtc->pipe ||
12556                     !(crtc_state->nv12_planes & BIT(plane->id)))
12557                         continue;
12558
12559                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
12560                         if (!icl_is_nv12_y_plane(linked->id))
12561                                 continue;
12562
12563                         if (crtc_state->active_planes & BIT(linked->id))
12564                                 continue;
12565
12566                         linked_state = intel_atomic_get_plane_state(state, linked);
12567                         if (IS_ERR(linked_state))
12568                                 return PTR_ERR(linked_state);
12569
12570                         break;
12571                 }
12572
12573                 if (!linked_state) {
12574                         drm_dbg_kms(&dev_priv->drm,
12575                                     "Need %d free Y planes for planar YUV\n",
12576                                     hweight8(crtc_state->nv12_planes));
12577
12578                         return -EINVAL;
12579                 }
12580
12581                 plane_state->planar_linked_plane = linked;
12582
12583                 linked_state->planar_slave = true;
12584                 linked_state->planar_linked_plane = plane;
12585                 crtc_state->active_planes |= BIT(linked->id);
12586                 crtc_state->update_planes |= BIT(linked->id);
12587                 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
12588                             linked->base.name, plane->base.name);
12589
12590                 /* Copy parameters to slave plane */
12591                 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
12592                 linked_state->color_ctl = plane_state->color_ctl;
12593                 linked_state->view = plane_state->view;
12594                 memcpy(linked_state->color_plane, plane_state->color_plane,
12595                        sizeof(linked_state->color_plane));
12596
12597                 intel_plane_copy_uapi_to_hw_state(linked_state, plane_state);
12598                 linked_state->uapi.src = plane_state->uapi.src;
12599                 linked_state->uapi.dst = plane_state->uapi.dst;
12600
12601                 if (icl_is_hdr_plane(dev_priv, plane->id)) {
12602                         if (linked->id == PLANE_SPRITE5)
12603                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
12604                         else if (linked->id == PLANE_SPRITE4)
12605                                 plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
12606                         else
12607                                 MISSING_CASE(linked->id);
12608                 }
12609         }
12610
12611         return 0;
12612 }
12613
12614 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
12615 {
12616         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
12617         struct intel_atomic_state *state =
12618                 to_intel_atomic_state(new_crtc_state->uapi.state);
12619         const struct intel_crtc_state *old_crtc_state =
12620                 intel_atomic_get_old_crtc_state(state, crtc);
12621
12622         return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
12623 }
12624
12625 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
12626 {
12627         const struct drm_display_mode *adjusted_mode =
12628                 &crtc_state->hw.adjusted_mode;
12629
12630         if (!crtc_state->hw.enable)
12631                 return 0;
12632
12633         return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
12634                                  adjusted_mode->crtc_clock);
12635 }
12636
12637 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
12638                                const struct intel_cdclk_state *cdclk_state)
12639 {
12640         const struct drm_display_mode *adjusted_mode =
12641                 &crtc_state->hw.adjusted_mode;
12642
12643         if (!crtc_state->hw.enable)
12644                 return 0;
12645
12646         return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
12647                                  cdclk_state->logical.cdclk);
12648 }
12649
12650 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
12651 {
12652         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
12653         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12654         const struct drm_display_mode *adjusted_mode =
12655                 &crtc_state->hw.adjusted_mode;
12656         u16 linetime_wm;
12657
12658         if (!crtc_state->hw.enable)
12659                 return 0;
12660
12661         linetime_wm = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000 * 8,
12662                                    crtc_state->pixel_rate);
12663
12664         /* Display WA #1135: BXT:ALL GLK:ALL */
12665         if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled)
12666                 linetime_wm /= 2;
12667
12668         return linetime_wm;
12669 }
12670
12671 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
12672                                    struct intel_crtc *crtc)
12673 {
12674         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12675         struct intel_crtc_state *crtc_state =
12676                 intel_atomic_get_new_crtc_state(state, crtc);
12677         const struct intel_cdclk_state *cdclk_state;
12678
12679         if (INTEL_GEN(dev_priv) >= 9)
12680                 crtc_state->linetime = skl_linetime_wm(crtc_state);
12681         else
12682                 crtc_state->linetime = hsw_linetime_wm(crtc_state);
12683
12684         if (!hsw_crtc_supports_ips(crtc))
12685                 return 0;
12686
12687         cdclk_state = intel_atomic_get_cdclk_state(state);
12688         if (IS_ERR(cdclk_state))
12689                 return PTR_ERR(cdclk_state);
12690
12691         crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
12692                                                        cdclk_state);
12693
12694         return 0;
12695 }
12696
12697 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
12698                                    struct intel_crtc *crtc)
12699 {
12700         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12701         struct intel_crtc_state *crtc_state =
12702                 intel_atomic_get_new_crtc_state(state, crtc);
12703         bool mode_changed = needs_modeset(crtc_state);
12704         int ret;
12705
12706         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
12707             mode_changed && !crtc_state->hw.active)
12708                 crtc_state->update_wm_post = true;
12709
12710         if (mode_changed && crtc_state->hw.enable &&
12711             dev_priv->display.crtc_compute_clock &&
12712             !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
12713                 ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
12714                 if (ret)
12715                         return ret;
12716         }
12717
12718         /*
12719          * May need to update pipe gamma enable bits
12720          * when C8 planes are getting enabled/disabled.
12721          */
12722         if (c8_planes_changed(crtc_state))
12723                 crtc_state->uapi.color_mgmt_changed = true;
12724
12725         if (mode_changed || crtc_state->update_pipe ||
12726             crtc_state->uapi.color_mgmt_changed) {
12727                 ret = intel_color_check(crtc_state);
12728                 if (ret)
12729                         return ret;
12730         }
12731
12732         if (dev_priv->display.compute_pipe_wm) {
12733                 ret = dev_priv->display.compute_pipe_wm(crtc_state);
12734                 if (ret) {
12735                         drm_dbg_kms(&dev_priv->drm,
12736                                     "Target pipe watermarks are invalid\n");
12737                         return ret;
12738                 }
12739         }
12740
12741         if (dev_priv->display.compute_intermediate_wm) {
12742                 if (drm_WARN_ON(&dev_priv->drm,
12743                                 !dev_priv->display.compute_pipe_wm))
12744                         return 0;
12745
12746                 /*
12747                  * Calculate 'intermediate' watermarks that satisfy both the
12748                  * old state and the new state.  We can program these
12749                  * immediately.
12750                  */
12751                 ret = dev_priv->display.compute_intermediate_wm(crtc_state);
12752                 if (ret) {
12753                         drm_dbg_kms(&dev_priv->drm,
12754                                     "No valid intermediate pipe watermarks are possible\n");
12755                         return ret;
12756                 }
12757         }
12758
12759         if (INTEL_GEN(dev_priv) >= 9) {
12760                 if (mode_changed || crtc_state->update_pipe) {
12761                         ret = skl_update_scaler_crtc(crtc_state);
12762                         if (ret)
12763                                 return ret;
12764                 }
12765
12766                 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
12767                 if (ret)
12768                         return ret;
12769         }
12770
12771         if (HAS_IPS(dev_priv)) {
12772                 ret = hsw_compute_ips_config(crtc_state);
12773                 if (ret)
12774                         return ret;
12775         }
12776
12777         if (INTEL_GEN(dev_priv) >= 9 ||
12778             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
12779                 ret = hsw_compute_linetime_wm(state, crtc);
12780                 if (ret)
12781                         return ret;
12782
12783         }
12784
12785         return 0;
12786 }
12787
12788 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12789 {
12790         struct intel_connector *connector;
12791         struct drm_connector_list_iter conn_iter;
12792
12793         drm_connector_list_iter_begin(dev, &conn_iter);
12794         for_each_intel_connector_iter(connector, &conn_iter) {
12795                 if (connector->base.state->crtc)
12796                         drm_connector_put(&connector->base);
12797
12798                 if (connector->base.encoder) {
12799                         connector->base.state->best_encoder =
12800                                 connector->base.encoder;
12801                         connector->base.state->crtc =
12802                                 connector->base.encoder->crtc;
12803
12804                         drm_connector_get(&connector->base);
12805                 } else {
12806                         connector->base.state->best_encoder = NULL;
12807                         connector->base.state->crtc = NULL;
12808                 }
12809         }
12810         drm_connector_list_iter_end(&conn_iter);
12811 }
12812
12813 static int
12814 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
12815                       struct intel_crtc_state *pipe_config)
12816 {
12817         struct drm_connector *connector = conn_state->connector;
12818         struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
12819         const struct drm_display_info *info = &connector->display_info;
12820         int bpp;
12821
12822         switch (conn_state->max_bpc) {
12823         case 6 ... 7:
12824                 bpp = 6 * 3;
12825                 break;
12826         case 8 ... 9:
12827                 bpp = 8 * 3;
12828                 break;
12829         case 10 ... 11:
12830                 bpp = 10 * 3;
12831                 break;
12832         case 12:
12833                 bpp = 12 * 3;
12834                 break;
12835         default:
12836                 return -EINVAL;
12837         }
12838
12839         if (bpp < pipe_config->pipe_bpp) {
12840                 drm_dbg_kms(&i915->drm,
12841                             "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
12842                             "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
12843                             connector->base.id, connector->name,
12844                             bpp, 3 * info->bpc,
12845                             3 * conn_state->max_requested_bpc,
12846                             pipe_config->pipe_bpp);
12847
12848                 pipe_config->pipe_bpp = bpp;
12849         }
12850
12851         return 0;
12852 }
12853
12854 static int
12855 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12856                           struct intel_crtc_state *pipe_config)
12857 {
12858         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12859         struct drm_atomic_state *state = pipe_config->uapi.state;
12860         struct drm_connector *connector;
12861         struct drm_connector_state *connector_state;
12862         int bpp, i;
12863
12864         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
12865             IS_CHERRYVIEW(dev_priv)))
12866                 bpp = 10*3;
12867         else if (INTEL_GEN(dev_priv) >= 5)
12868                 bpp = 12*3;
12869         else
12870                 bpp = 8*3;
12871
12872         pipe_config->pipe_bpp = bpp;
12873
12874         /* Clamp display bpp to connector max bpp */
12875         for_each_new_connector_in_state(state, connector, connector_state, i) {
12876                 int ret;
12877
12878                 if (connector_state->crtc != &crtc->base)
12879                         continue;
12880
12881                 ret = compute_sink_pipe_bpp(connector_state, pipe_config);
12882                 if (ret)
12883                         return ret;
12884         }
12885
12886         return 0;
12887 }
12888
12889 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12890 {
12891         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12892                       "type: 0x%x flags: 0x%x\n",
12893                       mode->crtc_clock,
12894                       mode->crtc_hdisplay, mode->crtc_hsync_start,
12895                       mode->crtc_hsync_end, mode->crtc_htotal,
12896                       mode->crtc_vdisplay, mode->crtc_vsync_start,
12897                       mode->crtc_vsync_end, mode->crtc_vtotal,
12898                       mode->type, mode->flags);
12899 }
12900
12901 static inline void
12902 intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
12903                       const char *id, unsigned int lane_count,
12904                       const struct intel_link_m_n *m_n)
12905 {
12906         struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
12907
12908         drm_dbg_kms(&i915->drm,
12909                     "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12910                     id, lane_count,
12911                     m_n->gmch_m, m_n->gmch_n,
12912                     m_n->link_m, m_n->link_n, m_n->tu);
12913 }
12914
12915 static void
12916 intel_dump_infoframe(struct drm_i915_private *dev_priv,
12917                      const union hdmi_infoframe *frame)
12918 {
12919         if (!drm_debug_enabled(DRM_UT_KMS))
12920                 return;
12921
12922         hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
12923 }
12924
12925 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
12926
12927 static const char * const output_type_str[] = {
12928         OUTPUT_TYPE(UNUSED),
12929         OUTPUT_TYPE(ANALOG),
12930         OUTPUT_TYPE(DVO),
12931         OUTPUT_TYPE(SDVO),
12932         OUTPUT_TYPE(LVDS),
12933         OUTPUT_TYPE(TVOUT),
12934         OUTPUT_TYPE(HDMI),
12935         OUTPUT_TYPE(DP),
12936         OUTPUT_TYPE(EDP),
12937         OUTPUT_TYPE(DSI),
12938         OUTPUT_TYPE(DDI),
12939         OUTPUT_TYPE(DP_MST),
12940 };
12941
12942 #undef OUTPUT_TYPE
12943
12944 static void snprintf_output_types(char *buf, size_t len,
12945                                   unsigned int output_types)
12946 {
12947         char *str = buf;
12948         int i;
12949
12950         str[0] = '\0';
12951
12952         for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
12953                 int r;
12954
12955                 if ((output_types & BIT(i)) == 0)
12956                         continue;
12957
12958                 r = snprintf(str, len, "%s%s",
12959                              str != buf ? "," : "", output_type_str[i]);
12960                 if (r >= len)
12961                         break;
12962                 str += r;
12963                 len -= r;
12964
12965                 output_types &= ~BIT(i);
12966         }
12967
12968         WARN_ON_ONCE(output_types != 0);
12969 }
12970
12971 static const char * const output_format_str[] = {
12972         [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid",
12973         [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
12974         [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
12975         [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
12976 };
12977
12978 static const char *output_formats(enum intel_output_format format)
12979 {
12980         if (format >= ARRAY_SIZE(output_format_str))
12981                 format = INTEL_OUTPUT_FORMAT_INVALID;
12982         return output_format_str[format];
12983 }
12984
12985 static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
12986 {
12987         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
12988         struct drm_i915_private *i915 = to_i915(plane->base.dev);
12989         const struct drm_framebuffer *fb = plane_state->hw.fb;
12990         struct drm_format_name_buf format_name;
12991
12992         if (!fb) {
12993                 drm_dbg_kms(&i915->drm,
12994                             "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
12995                             plane->base.base.id, plane->base.name,
12996                             yesno(plane_state->uapi.visible));
12997                 return;
12998         }
12999
13000         drm_dbg_kms(&i915->drm,
13001                     "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n",
13002                     plane->base.base.id, plane->base.name,
13003                     fb->base.id, fb->width, fb->height,
13004                     drm_get_format_name(fb->format->format, &format_name),
13005                     yesno(plane_state->uapi.visible));
13006         drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
13007                     plane_state->hw.rotation, plane_state->scaler_id);
13008         if (plane_state->uapi.visible)
13009                 drm_dbg_kms(&i915->drm,
13010                             "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
13011                             DRM_RECT_FP_ARG(&plane_state->uapi.src),
13012                             DRM_RECT_ARG(&plane_state->uapi.dst));
13013 }
13014
13015 static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
13016                                    struct intel_atomic_state *state,
13017                                    const char *context)
13018 {
13019         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13020         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13021         const struct intel_plane_state *plane_state;
13022         struct intel_plane *plane;
13023         char buf[64];
13024         int i;
13025
13026         drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
13027                     crtc->base.base.id, crtc->base.name,
13028                     yesno(pipe_config->hw.enable), context);
13029
13030         if (!pipe_config->hw.enable)
13031                 goto dump_planes;
13032
13033         snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
13034         drm_dbg_kms(&dev_priv->drm,
13035                     "active: %s, output_types: %s (0x%x), output format: %s\n",
13036                     yesno(pipe_config->hw.active),
13037                     buf, pipe_config->output_types,
13038                     output_formats(pipe_config->output_format));
13039
13040         drm_dbg_kms(&dev_priv->drm,
13041                     "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
13042                     transcoder_name(pipe_config->cpu_transcoder),
13043                     pipe_config->pipe_bpp, pipe_config->dither);
13044
13045         if (pipe_config->has_pch_encoder)
13046                 intel_dump_m_n_config(pipe_config, "fdi",
13047                                       pipe_config->fdi_lanes,
13048                                       &pipe_config->fdi_m_n);
13049
13050         if (intel_crtc_has_dp_encoder(pipe_config)) {
13051                 intel_dump_m_n_config(pipe_config, "dp m_n",
13052                                 pipe_config->lane_count, &pipe_config->dp_m_n);
13053                 if (pipe_config->has_drrs)
13054                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
13055                                               pipe_config->lane_count,
13056                                               &pipe_config->dp_m2_n2);
13057         }
13058
13059         drm_dbg_kms(&dev_priv->drm,
13060                     "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
13061                     pipe_config->has_audio, pipe_config->has_infoframe,
13062                     pipe_config->infoframes.enable);
13063
13064         if (pipe_config->infoframes.enable &
13065             intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
13066                 drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
13067                             pipe_config->infoframes.gcp);
13068         if (pipe_config->infoframes.enable &
13069             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
13070                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
13071         if (pipe_config->infoframes.enable &
13072             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
13073                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
13074         if (pipe_config->infoframes.enable &
13075             intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
13076                 intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
13077
13078         drm_dbg_kms(&dev_priv->drm, "requested mode:\n");
13079         drm_mode_debug_printmodeline(&pipe_config->hw.mode);
13080         drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n");
13081         drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode);
13082         intel_dump_crtc_timings(&pipe_config->hw.adjusted_mode);
13083         drm_dbg_kms(&dev_priv->drm,
13084                     "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
13085                     pipe_config->port_clock,
13086                     pipe_config->pipe_src_w, pipe_config->pipe_src_h,
13087                     pipe_config->pixel_rate);
13088
13089         drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
13090                     pipe_config->linetime, pipe_config->ips_linetime);
13091
13092         if (INTEL_GEN(dev_priv) >= 9)
13093                 drm_dbg_kms(&dev_priv->drm,
13094                             "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
13095                             crtc->num_scalers,
13096                             pipe_config->scaler_state.scaler_users,
13097                             pipe_config->scaler_state.scaler_id);
13098
13099         if (HAS_GMCH(dev_priv))
13100                 drm_dbg_kms(&dev_priv->drm,
13101                             "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
13102                             pipe_config->gmch_pfit.control,
13103                             pipe_config->gmch_pfit.pgm_ratios,
13104                             pipe_config->gmch_pfit.lvds_border_bits);
13105         else
13106                 drm_dbg_kms(&dev_priv->drm,
13107                             "pch pfit: pos: 0x%08x, size: 0x%08x, %s, force thru: %s\n",
13108                             pipe_config->pch_pfit.pos,
13109                             pipe_config->pch_pfit.size,
13110                             enableddisabled(pipe_config->pch_pfit.enabled),
13111                             yesno(pipe_config->pch_pfit.force_thru));
13112
13113         drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n",
13114                     pipe_config->ips_enabled, pipe_config->double_wide);
13115
13116         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
13117
13118         if (IS_CHERRYVIEW(dev_priv))
13119                 drm_dbg_kms(&dev_priv->drm,
13120                             "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
13121                             pipe_config->cgm_mode, pipe_config->gamma_mode,
13122                             pipe_config->gamma_enable, pipe_config->csc_enable);
13123         else
13124                 drm_dbg_kms(&dev_priv->drm,
13125                             "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
13126                             pipe_config->csc_mode, pipe_config->gamma_mode,
13127                             pipe_config->gamma_enable, pipe_config->csc_enable);
13128
13129         drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
13130                     transcoder_name(pipe_config->mst_master_transcoder));
13131
13132 dump_planes:
13133         if (!state)
13134                 return;
13135
13136         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
13137                 if (plane->pipe == crtc->pipe)
13138                         intel_dump_plane_state(plane_state);
13139         }
13140 }
13141
13142 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
13143 {
13144         struct drm_device *dev = state->base.dev;
13145         struct drm_connector *connector;
13146         struct drm_connector_list_iter conn_iter;
13147         unsigned int used_ports = 0;
13148         unsigned int used_mst_ports = 0;
13149         bool ret = true;
13150
13151         /*
13152          * We're going to peek into connector->state,
13153          * hence connection_mutex must be held.
13154          */
13155         drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
13156
13157         /*
13158          * Walk the connector list instead of the encoder
13159          * list to detect the problem on ddi platforms
13160          * where there's just one encoder per digital port.
13161          */
13162         drm_connector_list_iter_begin(dev, &conn_iter);
13163         drm_for_each_connector_iter(connector, &conn_iter) {
13164                 struct drm_connector_state *connector_state;
13165                 struct intel_encoder *encoder;
13166
13167                 connector_state =
13168                         drm_atomic_get_new_connector_state(&state->base,
13169                                                            connector);
13170                 if (!connector_state)
13171                         connector_state = connector->state;
13172
13173                 if (!connector_state->best_encoder)
13174                         continue;
13175
13176                 encoder = to_intel_encoder(connector_state->best_encoder);
13177
13178                 drm_WARN_ON(dev, !connector_state->crtc);
13179
13180                 switch (encoder->type) {
13181                 case INTEL_OUTPUT_DDI:
13182                         if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
13183                                 break;
13184                         /* else, fall through */
13185                 case INTEL_OUTPUT_DP:
13186                 case INTEL_OUTPUT_HDMI:
13187                 case INTEL_OUTPUT_EDP:
13188                         /* the same port mustn't appear more than once */
13189                         if (used_ports & BIT(encoder->port))
13190                                 ret = false;
13191
13192                         used_ports |= BIT(encoder->port);
13193                         break;
13194                 case INTEL_OUTPUT_DP_MST:
13195                         used_mst_ports |=
13196                                 1 << encoder->port;
13197                         break;
13198                 default:
13199                         break;
13200                 }
13201         }
13202         drm_connector_list_iter_end(&conn_iter);
13203
13204         /* can't mix MST and SST/HDMI on the same port */
13205         if (used_ports & used_mst_ports)
13206                 return false;
13207
13208         return ret;
13209 }
13210
13211 static void
13212 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state)
13213 {
13214         intel_crtc_copy_color_blobs(crtc_state);
13215 }
13216
13217 static void
13218 intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
13219 {
13220         crtc_state->hw.enable = crtc_state->uapi.enable;
13221         crtc_state->hw.active = crtc_state->uapi.active;
13222         crtc_state->hw.mode = crtc_state->uapi.mode;
13223         crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
13224         intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
13225 }
13226
13227 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
13228 {
13229         crtc_state->uapi.enable = crtc_state->hw.enable;
13230         crtc_state->uapi.active = crtc_state->hw.active;
13231         WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
13232
13233         crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
13234
13235         /* copy color blobs to uapi */
13236         drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
13237                                   crtc_state->hw.degamma_lut);
13238         drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
13239                                   crtc_state->hw.gamma_lut);
13240         drm_property_replace_blob(&crtc_state->uapi.ctm,
13241                                   crtc_state->hw.ctm);
13242 }
13243
13244 static int
13245 intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state)
13246 {
13247         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13248         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13249         struct intel_crtc_state *saved_state;
13250
13251         saved_state = intel_crtc_state_alloc(crtc);
13252         if (!saved_state)
13253                 return -ENOMEM;
13254
13255         /* free the old crtc_state->hw members */
13256         intel_crtc_free_hw_state(crtc_state);
13257
13258         /* FIXME: before the switch to atomic started, a new pipe_config was
13259          * kzalloc'd. Code that depends on any field being zero should be
13260          * fixed, so that the crtc_state can be safely duplicated. For now,
13261          * only fields that are know to not cause problems are preserved. */
13262
13263         saved_state->uapi = crtc_state->uapi;
13264         saved_state->scaler_state = crtc_state->scaler_state;
13265         saved_state->shared_dpll = crtc_state->shared_dpll;
13266         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
13267         memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
13268                sizeof(saved_state->icl_port_dplls));
13269         saved_state->crc_enabled = crtc_state->crc_enabled;
13270         if (IS_G4X(dev_priv) ||
13271             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13272                 saved_state->wm = crtc_state->wm;
13273
13274         memcpy(crtc_state, saved_state, sizeof(*crtc_state));
13275         kfree(saved_state);
13276
13277         intel_crtc_copy_uapi_to_hw_state(crtc_state);
13278
13279         return 0;
13280 }
13281
13282 static int
13283 intel_modeset_pipe_config(struct intel_crtc_state *pipe_config)
13284 {
13285         struct drm_crtc *crtc = pipe_config->uapi.crtc;
13286         struct drm_atomic_state *state = pipe_config->uapi.state;
13287         struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
13288         struct drm_connector *connector;
13289         struct drm_connector_state *connector_state;
13290         int base_bpp, ret, i;
13291         bool retry = true;
13292
13293         pipe_config->cpu_transcoder =
13294                 (enum transcoder) to_intel_crtc(crtc)->pipe;
13295
13296         /*
13297          * Sanitize sync polarity flags based on requested ones. If neither
13298          * positive or negative polarity is requested, treat this as meaning
13299          * negative polarity.
13300          */
13301         if (!(pipe_config->hw.adjusted_mode.flags &
13302               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
13303                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
13304
13305         if (!(pipe_config->hw.adjusted_mode.flags &
13306               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
13307                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
13308
13309         ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
13310                                         pipe_config);
13311         if (ret)
13312                 return ret;
13313
13314         base_bpp = pipe_config->pipe_bpp;
13315
13316         /*
13317          * Determine the real pipe dimensions. Note that stereo modes can
13318          * increase the actual pipe size due to the frame doubling and
13319          * insertion of additional space for blanks between the frame. This
13320          * is stored in the crtc timings. We use the requested mode to do this
13321          * computation to clearly distinguish it from the adjusted mode, which
13322          * can be changed by the connectors in the below retry loop.
13323          */
13324         drm_mode_get_hv_timing(&pipe_config->hw.mode,
13325                                &pipe_config->pipe_src_w,
13326                                &pipe_config->pipe_src_h);
13327
13328         for_each_new_connector_in_state(state, connector, connector_state, i) {
13329                 struct intel_encoder *encoder =
13330                         to_intel_encoder(connector_state->best_encoder);
13331
13332                 if (connector_state->crtc != crtc)
13333                         continue;
13334
13335                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13336                         drm_dbg_kms(&i915->drm,
13337                                     "rejecting invalid cloning configuration\n");
13338                         return -EINVAL;
13339                 }
13340
13341                 /*
13342                  * Determine output_types before calling the .compute_config()
13343                  * hooks so that the hooks can use this information safely.
13344                  */
13345                 if (encoder->compute_output_type)
13346                         pipe_config->output_types |=
13347                                 BIT(encoder->compute_output_type(encoder, pipe_config,
13348                                                                  connector_state));
13349                 else
13350                         pipe_config->output_types |= BIT(encoder->type);
13351         }
13352
13353 encoder_retry:
13354         /* Ensure the port clock defaults are reset when retrying. */
13355         pipe_config->port_clock = 0;
13356         pipe_config->pixel_multiplier = 1;
13357
13358         /* Fill in default crtc timings, allow encoders to overwrite them. */
13359         drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
13360                               CRTC_STEREO_DOUBLE);
13361
13362         /* Pass our mode to the connectors and the CRTC to give them a chance to
13363          * adjust it according to limitations or connector properties, and also
13364          * a chance to reject the mode entirely.
13365          */
13366         for_each_new_connector_in_state(state, connector, connector_state, i) {
13367                 struct intel_encoder *encoder =
13368                         to_intel_encoder(connector_state->best_encoder);
13369
13370                 if (connector_state->crtc != crtc)
13371                         continue;
13372
13373                 ret = encoder->compute_config(encoder, pipe_config,
13374                                               connector_state);
13375                 if (ret < 0) {
13376                         if (ret != -EDEADLK)
13377                                 drm_dbg_kms(&i915->drm,
13378                                             "Encoder config failure: %d\n",
13379                                             ret);
13380                         return ret;
13381                 }
13382         }
13383
13384         /* Set default port clock if not overwritten by the encoder. Needs to be
13385          * done afterwards in case the encoder adjusts the mode. */
13386         if (!pipe_config->port_clock)
13387                 pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
13388                         * pipe_config->pixel_multiplier;
13389
13390         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13391         if (ret == -EDEADLK)
13392                 return ret;
13393         if (ret < 0) {
13394                 drm_dbg_kms(&i915->drm, "CRTC fixup failed\n");
13395                 return ret;
13396         }
13397
13398         if (ret == RETRY) {
13399                 if (drm_WARN(&i915->drm, !retry,
13400                              "loop in pipe configuration computation\n"))
13401                         return -EINVAL;
13402
13403                 drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n");
13404                 retry = false;
13405                 goto encoder_retry;
13406         }
13407
13408         /* Dithering seems to not pass-through bits correctly when it should, so
13409          * only enable it on 6bpc panels and when its not a compliance
13410          * test requesting 6bpc video pattern.
13411          */
13412         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
13413                 !pipe_config->dither_force_disable;
13414         drm_dbg_kms(&i915->drm,
13415                     "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13416                     base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13417
13418         /*
13419          * Make drm_calc_timestamping_constants in
13420          * drm_atomic_helper_update_legacy_modeset_state() happy
13421          */
13422         pipe_config->uapi.adjusted_mode = pipe_config->hw.adjusted_mode;
13423
13424         return 0;
13425 }
13426
13427 static int
13428 intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state)
13429 {
13430         struct intel_atomic_state *state =
13431                 to_intel_atomic_state(crtc_state->uapi.state);
13432         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
13433         struct drm_connector_state *conn_state;
13434         struct drm_connector *connector;
13435         int i;
13436
13437         for_each_new_connector_in_state(&state->base, connector,
13438                                         conn_state, i) {
13439                 struct intel_encoder *encoder =
13440                         to_intel_encoder(conn_state->best_encoder);
13441                 int ret;
13442
13443                 if (conn_state->crtc != &crtc->base ||
13444                     !encoder->compute_config_late)
13445                         continue;
13446
13447                 ret = encoder->compute_config_late(encoder, crtc_state,
13448                                                    conn_state);
13449                 if (ret)
13450                         return ret;
13451         }
13452
13453         return 0;
13454 }
13455
13456 bool intel_fuzzy_clock_check(int clock1, int clock2)
13457 {
13458         int diff;
13459
13460         if (clock1 == clock2)
13461                 return true;
13462
13463         if (!clock1 || !clock2)
13464                 return false;
13465
13466         diff = abs(clock1 - clock2);
13467
13468         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13469                 return true;
13470
13471         return false;
13472 }
13473
13474 static bool
13475 intel_compare_m_n(unsigned int m, unsigned int n,
13476                   unsigned int m2, unsigned int n2,
13477                   bool exact)
13478 {
13479         if (m == m2 && n == n2)
13480                 return true;
13481
13482         if (exact || !m || !n || !m2 || !n2)
13483                 return false;
13484
13485         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13486
13487         if (n > n2) {
13488                 while (n > n2) {
13489                         m2 <<= 1;
13490                         n2 <<= 1;
13491                 }
13492         } else if (n < n2) {
13493                 while (n < n2) {
13494                         m <<= 1;
13495                         n <<= 1;
13496                 }
13497         }
13498
13499         if (n != n2)
13500                 return false;
13501
13502         return intel_fuzzy_clock_check(m, m2);
13503 }
13504
13505 static bool
13506 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13507                        const struct intel_link_m_n *m2_n2,
13508                        bool exact)
13509 {
13510         return m_n->tu == m2_n2->tu &&
13511                 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13512                                   m2_n2->gmch_m, m2_n2->gmch_n, exact) &&
13513                 intel_compare_m_n(m_n->link_m, m_n->link_n,
13514                                   m2_n2->link_m, m2_n2->link_n, exact);
13515 }
13516
13517 static bool
13518 intel_compare_infoframe(const union hdmi_infoframe *a,
13519                         const union hdmi_infoframe *b)
13520 {
13521         return memcmp(a, b, sizeof(*a)) == 0;
13522 }
13523
13524 static void
13525 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
13526                                bool fastset, const char *name,
13527                                const union hdmi_infoframe *a,
13528                                const union hdmi_infoframe *b)
13529 {
13530         if (fastset) {
13531                 if (!drm_debug_enabled(DRM_UT_KMS))
13532                         return;
13533
13534                 drm_dbg_kms(&dev_priv->drm,
13535                             "fastset mismatch in %s infoframe\n", name);
13536                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
13537                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
13538                 drm_dbg_kms(&dev_priv->drm, "found:\n");
13539                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
13540         } else {
13541                 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
13542                 drm_err(&dev_priv->drm, "expected:\n");
13543                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
13544                 drm_err(&dev_priv->drm, "found:\n");
13545                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
13546         }
13547 }
13548
13549 static void __printf(4, 5)
13550 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
13551                      const char *name, const char *format, ...)
13552 {
13553         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
13554         struct va_format vaf;
13555         va_list args;
13556
13557         va_start(args, format);
13558         vaf.fmt = format;
13559         vaf.va = &args;
13560
13561         if (fastset)
13562                 drm_dbg_kms(&i915->drm,
13563                             "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
13564                             crtc->base.base.id, crtc->base.name, name, &vaf);
13565         else
13566                 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
13567                         crtc->base.base.id, crtc->base.name, name, &vaf);
13568
13569         va_end(args);
13570 }
13571
13572 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
13573 {
13574         if (i915_modparams.fastboot != -1)
13575                 return i915_modparams.fastboot;
13576
13577         /* Enable fastboot by default on Skylake and newer */
13578         if (INTEL_GEN(dev_priv) >= 9)
13579                 return true;
13580
13581         /* Enable fastboot by default on VLV and CHV */
13582         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13583                 return true;
13584
13585         /* Disabled by default on all others */
13586         return false;
13587 }
13588
13589 static bool
13590 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
13591                           const struct intel_crtc_state *pipe_config,
13592                           bool fastset)
13593 {
13594         struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
13595         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
13596         bool ret = true;
13597         u32 bp_gamma = 0;
13598         bool fixup_inherited = fastset &&
13599                 (current_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED) &&
13600                 !(pipe_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED);
13601
13602         if (fixup_inherited && !fastboot_enabled(dev_priv)) {
13603                 drm_dbg_kms(&dev_priv->drm,
13604                             "initial modeset and fastboot not set\n");
13605                 ret = false;
13606         }
13607
13608 #define PIPE_CONF_CHECK_X(name) do { \
13609         if (current_config->name != pipe_config->name) { \
13610                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13611                                      "(expected 0x%08x, found 0x%08x)", \
13612                                      current_config->name, \
13613                                      pipe_config->name); \
13614                 ret = false; \
13615         } \
13616 } while (0)
13617
13618 #define PIPE_CONF_CHECK_I(name) do { \
13619         if (current_config->name != pipe_config->name) { \
13620                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13621                                      "(expected %i, found %i)", \
13622                                      current_config->name, \
13623                                      pipe_config->name); \
13624                 ret = false; \
13625         } \
13626 } while (0)
13627
13628 #define PIPE_CONF_CHECK_BOOL(name) do { \
13629         if (current_config->name != pipe_config->name) { \
13630                 pipe_config_mismatch(fastset, crtc,  __stringify(name), \
13631                                      "(expected %s, found %s)", \
13632                                      yesno(current_config->name), \
13633                                      yesno(pipe_config->name)); \
13634                 ret = false; \
13635         } \
13636 } while (0)
13637
13638 /*
13639  * Checks state where we only read out the enabling, but not the entire
13640  * state itself (like full infoframes or ELD for audio). These states
13641  * require a full modeset on bootup to fix up.
13642  */
13643 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
13644         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
13645                 PIPE_CONF_CHECK_BOOL(name); \
13646         } else { \
13647                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13648                                      "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
13649                                      yesno(current_config->name), \
13650                                      yesno(pipe_config->name)); \
13651                 ret = false; \
13652         } \
13653 } while (0)
13654
13655 #define PIPE_CONF_CHECK_P(name) do { \
13656         if (current_config->name != pipe_config->name) { \
13657                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13658                                      "(expected %p, found %p)", \
13659                                      current_config->name, \
13660                                      pipe_config->name); \
13661                 ret = false; \
13662         } \
13663 } while (0)
13664
13665 #define PIPE_CONF_CHECK_M_N(name) do { \
13666         if (!intel_compare_link_m_n(&current_config->name, \
13667                                     &pipe_config->name,\
13668                                     !fastset)) { \
13669                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13670                                      "(expected tu %i gmch %i/%i link %i/%i, " \
13671                                      "found tu %i, gmch %i/%i link %i/%i)", \
13672                                      current_config->name.tu, \
13673                                      current_config->name.gmch_m, \
13674                                      current_config->name.gmch_n, \
13675                                      current_config->name.link_m, \
13676                                      current_config->name.link_n, \
13677                                      pipe_config->name.tu, \
13678                                      pipe_config->name.gmch_m, \
13679                                      pipe_config->name.gmch_n, \
13680                                      pipe_config->name.link_m, \
13681                                      pipe_config->name.link_n); \
13682                 ret = false; \
13683         } \
13684 } while (0)
13685
13686 /* This is required for BDW+ where there is only one set of registers for
13687  * switching between high and low RR.
13688  * This macro can be used whenever a comparison has to be made between one
13689  * hw state and multiple sw state variables.
13690  */
13691 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
13692         if (!intel_compare_link_m_n(&current_config->name, \
13693                                     &pipe_config->name, !fastset) && \
13694             !intel_compare_link_m_n(&current_config->alt_name, \
13695                                     &pipe_config->name, !fastset)) { \
13696                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13697                                      "(expected tu %i gmch %i/%i link %i/%i, " \
13698                                      "or tu %i gmch %i/%i link %i/%i, " \
13699                                      "found tu %i, gmch %i/%i link %i/%i)", \
13700                                      current_config->name.tu, \
13701                                      current_config->name.gmch_m, \
13702                                      current_config->name.gmch_n, \
13703                                      current_config->name.link_m, \
13704                                      current_config->name.link_n, \
13705                                      current_config->alt_name.tu, \
13706                                      current_config->alt_name.gmch_m, \
13707                                      current_config->alt_name.gmch_n, \
13708                                      current_config->alt_name.link_m, \
13709                                      current_config->alt_name.link_n, \
13710                                      pipe_config->name.tu, \
13711                                      pipe_config->name.gmch_m, \
13712                                      pipe_config->name.gmch_n, \
13713                                      pipe_config->name.link_m, \
13714                                      pipe_config->name.link_n); \
13715                 ret = false; \
13716         } \
13717 } while (0)
13718
13719 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
13720         if ((current_config->name ^ pipe_config->name) & (mask)) { \
13721                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13722                                      "(%x) (expected %i, found %i)", \
13723                                      (mask), \
13724                                      current_config->name & (mask), \
13725                                      pipe_config->name & (mask)); \
13726                 ret = false; \
13727         } \
13728 } while (0)
13729
13730 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
13731         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13732                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
13733                                      "(expected %i, found %i)", \
13734                                      current_config->name, \
13735                                      pipe_config->name); \
13736                 ret = false; \
13737         } \
13738 } while (0)
13739
13740 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
13741         if (!intel_compare_infoframe(&current_config->infoframes.name, \
13742                                      &pipe_config->infoframes.name)) { \
13743                 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
13744                                                &current_config->infoframes.name, \
13745                                                &pipe_config->infoframes.name); \
13746                 ret = false; \
13747         } \
13748 } while (0)
13749
13750 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
13751         if (current_config->name1 != pipe_config->name1) { \
13752                 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
13753                                 "(expected %i, found %i, won't compare lut values)", \
13754                                 current_config->name1, \
13755                                 pipe_config->name1); \
13756                 ret = false;\
13757         } else { \
13758                 if (!intel_color_lut_equal(current_config->name2, \
13759                                         pipe_config->name2, pipe_config->name1, \
13760                                         bit_precision)) { \
13761                         pipe_config_mismatch(fastset, crtc, __stringify(name2), \
13762                                         "hw_state doesn't match sw_state"); \
13763                         ret = false; \
13764                 } \
13765         } \
13766 } while (0)
13767
13768 #define PIPE_CONF_QUIRK(quirk) \
13769         ((current_config->quirks | pipe_config->quirks) & (quirk))
13770
13771         PIPE_CONF_CHECK_I(cpu_transcoder);
13772
13773         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
13774         PIPE_CONF_CHECK_I(fdi_lanes);
13775         PIPE_CONF_CHECK_M_N(fdi_m_n);
13776
13777         PIPE_CONF_CHECK_I(lane_count);
13778         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13779
13780         if (INTEL_GEN(dev_priv) < 8) {
13781                 PIPE_CONF_CHECK_M_N(dp_m_n);
13782
13783                 if (current_config->has_drrs)
13784                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
13785         } else
13786                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13787
13788         PIPE_CONF_CHECK_X(output_types);
13789
13790         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
13791         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
13792         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
13793         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
13794         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
13795         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
13796
13797         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
13798         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
13799         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
13800         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
13801         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
13802         PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
13803
13804         PIPE_CONF_CHECK_I(pixel_multiplier);
13805         PIPE_CONF_CHECK_I(output_format);
13806         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
13807         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
13808             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
13809                 PIPE_CONF_CHECK_BOOL(limited_color_range);
13810
13811         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
13812         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
13813         PIPE_CONF_CHECK_BOOL(has_infoframe);
13814         PIPE_CONF_CHECK_BOOL(fec_enable);
13815
13816         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
13817
13818         PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13819                               DRM_MODE_FLAG_INTERLACE);
13820
13821         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13822                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13823                                       DRM_MODE_FLAG_PHSYNC);
13824                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13825                                       DRM_MODE_FLAG_NHSYNC);
13826                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13827                                       DRM_MODE_FLAG_PVSYNC);
13828                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
13829                                       DRM_MODE_FLAG_NVSYNC);
13830         }
13831
13832         PIPE_CONF_CHECK_X(gmch_pfit.control);
13833         /* pfit ratios are autocomputed by the hw on gen4+ */
13834         if (INTEL_GEN(dev_priv) < 4)
13835                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13836         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13837
13838         /*
13839          * Changing the EDP transcoder input mux
13840          * (A_ONOFF vs. A_ON) requires a full modeset.
13841          */
13842         PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
13843
13844         if (!fastset) {
13845                 PIPE_CONF_CHECK_I(pipe_src_w);
13846                 PIPE_CONF_CHECK_I(pipe_src_h);
13847
13848                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
13849                 if (current_config->pch_pfit.enabled) {
13850                         PIPE_CONF_CHECK_X(pch_pfit.pos);
13851                         PIPE_CONF_CHECK_X(pch_pfit.size);
13852                 }
13853
13854                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13855                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
13856
13857                 PIPE_CONF_CHECK_X(gamma_mode);
13858                 if (IS_CHERRYVIEW(dev_priv))
13859                         PIPE_CONF_CHECK_X(cgm_mode);
13860                 else
13861                         PIPE_CONF_CHECK_X(csc_mode);
13862                 PIPE_CONF_CHECK_BOOL(gamma_enable);
13863                 PIPE_CONF_CHECK_BOOL(csc_enable);
13864
13865                 PIPE_CONF_CHECK_I(linetime);
13866                 PIPE_CONF_CHECK_I(ips_linetime);
13867
13868                 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
13869                 if (bp_gamma)
13870                         PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
13871         }
13872
13873         PIPE_CONF_CHECK_BOOL(double_wide);
13874
13875         PIPE_CONF_CHECK_P(shared_dpll);
13876         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13877         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13878         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13879         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13880         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13881         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13882         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13883         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13884         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13885         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
13886         PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
13887         PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
13888         PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
13889         PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
13890         PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
13891         PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
13892         PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
13893         PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
13894         PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
13895         PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
13896         PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
13897         PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
13898         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
13899         PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
13900         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
13901         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
13902         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
13903         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
13904         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
13905         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
13906         PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
13907
13908         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13909         PIPE_CONF_CHECK_X(dsi_pll.div);
13910
13911         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
13912                 PIPE_CONF_CHECK_I(pipe_bpp);
13913
13914         PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
13915         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13916
13917         PIPE_CONF_CHECK_I(min_voltage_level);
13918
13919         PIPE_CONF_CHECK_X(infoframes.enable);
13920         PIPE_CONF_CHECK_X(infoframes.gcp);
13921         PIPE_CONF_CHECK_INFOFRAME(avi);
13922         PIPE_CONF_CHECK_INFOFRAME(spd);
13923         PIPE_CONF_CHECK_INFOFRAME(hdmi);
13924         PIPE_CONF_CHECK_INFOFRAME(drm);
13925
13926         PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
13927         PIPE_CONF_CHECK_I(master_transcoder);
13928
13929         PIPE_CONF_CHECK_I(dsc.compression_enable);
13930         PIPE_CONF_CHECK_I(dsc.dsc_split);
13931         PIPE_CONF_CHECK_I(dsc.compressed_bpp);
13932
13933         PIPE_CONF_CHECK_I(mst_master_transcoder);
13934
13935 #undef PIPE_CONF_CHECK_X
13936 #undef PIPE_CONF_CHECK_I
13937 #undef PIPE_CONF_CHECK_BOOL
13938 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
13939 #undef PIPE_CONF_CHECK_P
13940 #undef PIPE_CONF_CHECK_FLAGS
13941 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13942 #undef PIPE_CONF_CHECK_COLOR_LUT
13943 #undef PIPE_CONF_QUIRK
13944
13945         return ret;
13946 }
13947
13948 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13949                                            const struct intel_crtc_state *pipe_config)
13950 {
13951         if (pipe_config->has_pch_encoder) {
13952                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13953                                                             &pipe_config->fdi_m_n);
13954                 int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
13955
13956                 /*
13957                  * FDI already provided one idea for the dotclock.
13958                  * Yell if the encoder disagrees.
13959                  */
13960                 drm_WARN(&dev_priv->drm,
13961                          !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13962                          "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13963                          fdi_dotclock, dotclock);
13964         }
13965 }
13966
13967 static void verify_wm_state(struct intel_crtc *crtc,
13968                             struct intel_crtc_state *new_crtc_state)
13969 {
13970         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13971         struct skl_hw_state {
13972                 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
13973                 struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
13974                 struct skl_pipe_wm wm;
13975         } *hw;
13976         struct skl_pipe_wm *sw_wm;
13977         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
13978         u8 hw_enabled_slices;
13979         const enum pipe pipe = crtc->pipe;
13980         int plane, level, max_level = ilk_wm_max_level(dev_priv);
13981
13982         if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
13983                 return;
13984
13985         hw = kzalloc(sizeof(*hw), GFP_KERNEL);
13986         if (!hw)
13987                 return;
13988
13989         skl_pipe_wm_get_hw_state(crtc, &hw->wm);
13990         sw_wm = &new_crtc_state->wm.skl.optimal;
13991
13992         skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
13993
13994         hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
13995
13996         if (INTEL_GEN(dev_priv) >= 11 &&
13997             hw_enabled_slices != dev_priv->enabled_dbuf_slices_mask)
13998                 drm_err(&dev_priv->drm,
13999                         "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
14000                         dev_priv->enabled_dbuf_slices_mask,
14001                         hw_enabled_slices);
14002
14003         /* planes */
14004         for_each_universal_plane(dev_priv, pipe, plane) {
14005                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
14006
14007                 hw_plane_wm = &hw->wm.planes[plane];
14008                 sw_plane_wm = &sw_wm->planes[plane];
14009
14010                 /* Watermarks */
14011                 for (level = 0; level <= max_level; level++) {
14012                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14013                                                 &sw_plane_wm->wm[level]))
14014                                 continue;
14015
14016                         drm_err(&dev_priv->drm,
14017                                 "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14018                                 pipe_name(pipe), plane + 1, level,
14019                                 sw_plane_wm->wm[level].plane_en,
14020                                 sw_plane_wm->wm[level].plane_res_b,
14021                                 sw_plane_wm->wm[level].plane_res_l,
14022                                 hw_plane_wm->wm[level].plane_en,
14023                                 hw_plane_wm->wm[level].plane_res_b,
14024                                 hw_plane_wm->wm[level].plane_res_l);
14025                 }
14026
14027                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
14028                                          &sw_plane_wm->trans_wm)) {
14029                         drm_err(&dev_priv->drm,
14030                                 "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14031                                 pipe_name(pipe), plane + 1,
14032                                 sw_plane_wm->trans_wm.plane_en,
14033                                 sw_plane_wm->trans_wm.plane_res_b,
14034                                 sw_plane_wm->trans_wm.plane_res_l,
14035                                 hw_plane_wm->trans_wm.plane_en,
14036                                 hw_plane_wm->trans_wm.plane_res_b,
14037                                 hw_plane_wm->trans_wm.plane_res_l);
14038                 }
14039
14040                 /* DDB */
14041                 hw_ddb_entry = &hw->ddb_y[plane];
14042                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
14043
14044                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
14045                         drm_err(&dev_priv->drm,
14046                                 "mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
14047                                 pipe_name(pipe), plane + 1,
14048                                 sw_ddb_entry->start, sw_ddb_entry->end,
14049                                 hw_ddb_entry->start, hw_ddb_entry->end);
14050                 }
14051         }
14052
14053         /*
14054          * cursor
14055          * If the cursor plane isn't active, we may not have updated it's ddb
14056          * allocation. In that case since the ddb allocation will be updated
14057          * once the plane becomes visible, we can skip this check
14058          */
14059         if (1) {
14060                 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
14061
14062                 hw_plane_wm = &hw->wm.planes[PLANE_CURSOR];
14063                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
14064
14065                 /* Watermarks */
14066                 for (level = 0; level <= max_level; level++) {
14067                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
14068                                                 &sw_plane_wm->wm[level]))
14069                                 continue;
14070
14071                         drm_err(&dev_priv->drm,
14072                                 "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14073                                 pipe_name(pipe), level,
14074                                 sw_plane_wm->wm[level].plane_en,
14075                                 sw_plane_wm->wm[level].plane_res_b,
14076                                 sw_plane_wm->wm[level].plane_res_l,
14077                                 hw_plane_wm->wm[level].plane_en,
14078                                 hw_plane_wm->wm[level].plane_res_b,
14079                                 hw_plane_wm->wm[level].plane_res_l);
14080                 }
14081
14082                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
14083                                          &sw_plane_wm->trans_wm)) {
14084                         drm_err(&dev_priv->drm,
14085                                 "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
14086                                 pipe_name(pipe),
14087                                 sw_plane_wm->trans_wm.plane_en,
14088                                 sw_plane_wm->trans_wm.plane_res_b,
14089                                 sw_plane_wm->trans_wm.plane_res_l,
14090                                 hw_plane_wm->trans_wm.plane_en,
14091                                 hw_plane_wm->trans_wm.plane_res_b,
14092                                 hw_plane_wm->trans_wm.plane_res_l);
14093                 }
14094
14095                 /* DDB */
14096                 hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
14097                 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
14098
14099                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
14100                         drm_err(&dev_priv->drm,
14101                                 "mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
14102                                 pipe_name(pipe),
14103                                 sw_ddb_entry->start, sw_ddb_entry->end,
14104                                 hw_ddb_entry->start, hw_ddb_entry->end);
14105                 }
14106         }
14107
14108         kfree(hw);
14109 }
14110
14111 static void
14112 verify_connector_state(struct intel_atomic_state *state,
14113                        struct intel_crtc *crtc)
14114 {
14115         struct drm_connector *connector;
14116         struct drm_connector_state *new_conn_state;
14117         int i;
14118
14119         for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
14120                 struct drm_encoder *encoder = connector->encoder;
14121                 struct intel_crtc_state *crtc_state = NULL;
14122
14123                 if (new_conn_state->crtc != &crtc->base)
14124                         continue;
14125
14126                 if (crtc)
14127                         crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
14128
14129                 intel_connector_verify_state(crtc_state, new_conn_state);
14130
14131                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
14132                      "connector's atomic encoder doesn't match legacy encoder\n");
14133         }
14134 }
14135
14136 static void
14137 verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
14138 {
14139         struct intel_encoder *encoder;
14140         struct drm_connector *connector;
14141         struct drm_connector_state *old_conn_state, *new_conn_state;
14142         int i;
14143
14144         for_each_intel_encoder(&dev_priv->drm, encoder) {
14145                 bool enabled = false, found = false;
14146                 enum pipe pipe;
14147
14148                 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",
14149                             encoder->base.base.id,
14150                             encoder->base.name);
14151
14152                 for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
14153                                                    new_conn_state, i) {
14154                         if (old_conn_state->best_encoder == &encoder->base)
14155                                 found = true;
14156
14157                         if (new_conn_state->best_encoder != &encoder->base)
14158                                 continue;
14159                         found = enabled = true;
14160
14161                         I915_STATE_WARN(new_conn_state->crtc !=
14162                                         encoder->base.crtc,
14163                              "connector's crtc doesn't match encoder crtc\n");
14164                 }
14165
14166                 if (!found)
14167                         continue;
14168
14169                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
14170                      "encoder's enabled state mismatch "
14171                      "(expected %i, found %i)\n",
14172                      !!encoder->base.crtc, enabled);
14173
14174                 if (!encoder->base.crtc) {
14175                         bool active;
14176
14177                         active = encoder->get_hw_state(encoder, &pipe);
14178                         I915_STATE_WARN(active,
14179                              "encoder detached but still enabled on pipe %c.\n",
14180                              pipe_name(pipe));
14181                 }
14182         }
14183 }
14184
14185 static void
14186 verify_crtc_state(struct intel_crtc *crtc,
14187                   struct intel_crtc_state *old_crtc_state,
14188                   struct intel_crtc_state *new_crtc_state)
14189 {
14190         struct drm_device *dev = crtc->base.dev;
14191         struct drm_i915_private *dev_priv = to_i915(dev);
14192         struct intel_encoder *encoder;
14193         struct intel_crtc_state *pipe_config = old_crtc_state;
14194         struct drm_atomic_state *state = old_crtc_state->uapi.state;
14195         bool active;
14196
14197         __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
14198         intel_crtc_free_hw_state(old_crtc_state);
14199         intel_crtc_state_reset(old_crtc_state, crtc);
14200         old_crtc_state->uapi.state = state;
14201
14202         drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
14203                     crtc->base.name);
14204
14205         active = dev_priv->display.get_pipe_config(crtc, pipe_config);
14206
14207         /* we keep both pipes enabled on 830 */
14208         if (IS_I830(dev_priv))
14209                 active = new_crtc_state->hw.active;
14210
14211         I915_STATE_WARN(new_crtc_state->hw.active != active,
14212                         "crtc active state doesn't match with hw state "
14213                         "(expected %i, found %i)\n",
14214                         new_crtc_state->hw.active, active);
14215
14216         I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
14217                         "transitional active state does not match atomic hw state "
14218                         "(expected %i, found %i)\n",
14219                         new_crtc_state->hw.active, crtc->active);
14220
14221         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14222                 enum pipe pipe;
14223
14224                 active = encoder->get_hw_state(encoder, &pipe);
14225                 I915_STATE_WARN(active != new_crtc_state->hw.active,
14226                                 "[ENCODER:%i] active %i with crtc active %i\n",
14227                                 encoder->base.base.id, active,
14228                                 new_crtc_state->hw.active);
14229
14230                 I915_STATE_WARN(active && crtc->pipe != pipe,
14231                                 "Encoder connected to wrong pipe %c\n",
14232                                 pipe_name(pipe));
14233
14234                 if (active)
14235                         encoder->get_config(encoder, pipe_config);
14236         }
14237
14238         intel_crtc_compute_pixel_rate(pipe_config);
14239
14240         if (!new_crtc_state->hw.active)
14241                 return;
14242
14243         intel_pipe_config_sanity_check(dev_priv, pipe_config);
14244
14245         if (!intel_pipe_config_compare(new_crtc_state,
14246                                        pipe_config, false)) {
14247                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
14248                 intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
14249                 intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
14250         }
14251 }
14252
14253 static void
14254 intel_verify_planes(struct intel_atomic_state *state)
14255 {
14256         struct intel_plane *plane;
14257         const struct intel_plane_state *plane_state;
14258         int i;
14259
14260         for_each_new_intel_plane_in_state(state, plane,
14261                                           plane_state, i)
14262                 assert_plane(plane, plane_state->planar_slave ||
14263                              plane_state->uapi.visible);
14264 }
14265
14266 static void
14267 verify_single_dpll_state(struct drm_i915_private *dev_priv,
14268                          struct intel_shared_dpll *pll,
14269                          struct intel_crtc *crtc,
14270                          struct intel_crtc_state *new_crtc_state)
14271 {
14272         struct intel_dpll_hw_state dpll_hw_state;
14273         unsigned int crtc_mask;
14274         bool active;
14275
14276         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
14277
14278         drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
14279
14280         active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
14281
14282         if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
14283                 I915_STATE_WARN(!pll->on && pll->active_mask,
14284                      "pll in active use but not on in sw tracking\n");
14285                 I915_STATE_WARN(pll->on && !pll->active_mask,
14286                      "pll is on but not used by any active crtc\n");
14287                 I915_STATE_WARN(pll->on != active,
14288                      "pll on state mismatch (expected %i, found %i)\n",
14289                      pll->on, active);
14290         }
14291
14292         if (!crtc) {
14293                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
14294                                 "more active pll users than references: %x vs %x\n",
14295                                 pll->active_mask, pll->state.crtc_mask);
14296
14297                 return;
14298         }
14299
14300         crtc_mask = drm_crtc_mask(&crtc->base);
14301
14302         if (new_crtc_state->hw.active)
14303                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
14304                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
14305                                 pipe_name(crtc->pipe), pll->active_mask);
14306         else
14307                 I915_STATE_WARN(pll->active_mask & crtc_mask,
14308                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
14309                                 pipe_name(crtc->pipe), pll->active_mask);
14310
14311         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
14312                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
14313                         crtc_mask, pll->state.crtc_mask);
14314
14315         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
14316                                           &dpll_hw_state,
14317                                           sizeof(dpll_hw_state)),
14318                         "pll hw state mismatch\n");
14319 }
14320
14321 static void
14322 verify_shared_dpll_state(struct intel_crtc *crtc,
14323                          struct intel_crtc_state *old_crtc_state,
14324                          struct intel_crtc_state *new_crtc_state)
14325 {
14326         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14327
14328         if (new_crtc_state->shared_dpll)
14329                 verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
14330
14331         if (old_crtc_state->shared_dpll &&
14332             old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
14333                 unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
14334                 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
14335
14336                 I915_STATE_WARN(pll->active_mask & crtc_mask,
14337                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
14338                                 pipe_name(crtc->pipe));
14339                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
14340                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
14341                                 pipe_name(crtc->pipe));
14342         }
14343 }
14344
14345 static void
14346 intel_modeset_verify_crtc(struct intel_crtc *crtc,
14347                           struct intel_atomic_state *state,
14348                           struct intel_crtc_state *old_crtc_state,
14349                           struct intel_crtc_state *new_crtc_state)
14350 {
14351         if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
14352                 return;
14353
14354         verify_wm_state(crtc, new_crtc_state);
14355         verify_connector_state(state, crtc);
14356         verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
14357         verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
14358 }
14359
14360 static void
14361 verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
14362 {
14363         int i;
14364
14365         for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++)
14366                 verify_single_dpll_state(dev_priv,
14367                                          &dev_priv->dpll.shared_dplls[i],
14368                                          NULL, NULL);
14369 }
14370
14371 static void
14372 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
14373                               struct intel_atomic_state *state)
14374 {
14375         verify_encoder_state(dev_priv, state);
14376         verify_connector_state(state, NULL);
14377         verify_disabled_dpll_state(dev_priv);
14378 }
14379
14380 static void
14381 intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
14382 {
14383         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
14384         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14385         const struct drm_display_mode *adjusted_mode =
14386                 &crtc_state->hw.adjusted_mode;
14387
14388         drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
14389
14390         /*
14391          * The scanline counter increments at the leading edge of hsync.
14392          *
14393          * On most platforms it starts counting from vtotal-1 on the
14394          * first active line. That means the scanline counter value is
14395          * always one less than what we would expect. Ie. just after
14396          * start of vblank, which also occurs at start of hsync (on the
14397          * last active line), the scanline counter will read vblank_start-1.
14398          *
14399          * On gen2 the scanline counter starts counting from 1 instead
14400          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
14401          * to keep the value positive), instead of adding one.
14402          *
14403          * On HSW+ the behaviour of the scanline counter depends on the output
14404          * type. For DP ports it behaves like most other platforms, but on HDMI
14405          * there's an extra 1 line difference. So we need to add two instead of
14406          * one to the value.
14407          *
14408          * On VLV/CHV DSI the scanline counter would appear to increment
14409          * approx. 1/3 of a scanline before start of vblank. Unfortunately
14410          * that means we can't tell whether we're in vblank or not while
14411          * we're on that particular line. We must still set scanline_offset
14412          * to 1 so that the vblank timestamps come out correct when we query
14413          * the scanline counter from within the vblank interrupt handler.
14414          * However if queried just before the start of vblank we'll get an
14415          * answer that's slightly in the future.
14416          */
14417         if (IS_GEN(dev_priv, 2)) {
14418                 int vtotal;
14419
14420                 vtotal = adjusted_mode->crtc_vtotal;
14421                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
14422                         vtotal /= 2;
14423
14424                 crtc->scanline_offset = vtotal - 1;
14425         } else if (HAS_DDI(dev_priv) &&
14426                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
14427                 crtc->scanline_offset = 2;
14428         } else {
14429                 crtc->scanline_offset = 1;
14430         }
14431 }
14432
14433 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
14434 {
14435         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14436         struct intel_crtc_state *new_crtc_state;
14437         struct intel_crtc *crtc;
14438         int i;
14439
14440         if (!dev_priv->display.crtc_compute_clock)
14441                 return;
14442
14443         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14444                 if (!needs_modeset(new_crtc_state))
14445                         continue;
14446
14447                 intel_release_shared_dplls(state, crtc);
14448         }
14449 }
14450
14451 /*
14452  * This implements the workaround described in the "notes" section of the mode
14453  * set sequence documentation. When going from no pipes or single pipe to
14454  * multiple pipes, and planes are enabled after the pipe, we need to wait at
14455  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
14456  */
14457 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
14458 {
14459         struct intel_crtc_state *crtc_state;
14460         struct intel_crtc *crtc;
14461         struct intel_crtc_state *first_crtc_state = NULL;
14462         struct intel_crtc_state *other_crtc_state = NULL;
14463         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
14464         int i;
14465
14466         /* look at all crtc's that are going to be enabled in during modeset */
14467         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14468                 if (!crtc_state->hw.active ||
14469                     !needs_modeset(crtc_state))
14470                         continue;
14471
14472                 if (first_crtc_state) {
14473                         other_crtc_state = crtc_state;
14474                         break;
14475                 } else {
14476                         first_crtc_state = crtc_state;
14477                         first_pipe = crtc->pipe;
14478                 }
14479         }
14480
14481         /* No workaround needed? */
14482         if (!first_crtc_state)
14483                 return 0;
14484
14485         /* w/a possibly needed, check how many crtc's are already enabled. */
14486         for_each_intel_crtc(state->base.dev, crtc) {
14487                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
14488                 if (IS_ERR(crtc_state))
14489                         return PTR_ERR(crtc_state);
14490
14491                 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
14492
14493                 if (!crtc_state->hw.active ||
14494                     needs_modeset(crtc_state))
14495                         continue;
14496
14497                 /* 2 or more enabled crtcs means no need for w/a */
14498                 if (enabled_pipe != INVALID_PIPE)
14499                         return 0;
14500
14501                 enabled_pipe = crtc->pipe;
14502         }
14503
14504         if (enabled_pipe != INVALID_PIPE)
14505                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
14506         else if (other_crtc_state)
14507                 other_crtc_state->hsw_workaround_pipe = first_pipe;
14508
14509         return 0;
14510 }
14511
14512 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
14513                            u8 active_pipes)
14514 {
14515         const struct intel_crtc_state *crtc_state;
14516         struct intel_crtc *crtc;
14517         int i;
14518
14519         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14520                 if (crtc_state->hw.active)
14521                         active_pipes |= BIT(crtc->pipe);
14522                 else
14523                         active_pipes &= ~BIT(crtc->pipe);
14524         }
14525
14526         return active_pipes;
14527 }
14528
14529 static int intel_modeset_checks(struct intel_atomic_state *state)
14530 {
14531         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14532         int ret;
14533
14534         state->modeset = true;
14535         state->active_pipes = intel_calc_active_pipes(state, dev_priv->active_pipes);
14536
14537         state->active_pipe_changes = state->active_pipes ^ dev_priv->active_pipes;
14538
14539         if (state->active_pipe_changes) {
14540                 ret = _intel_atomic_lock_global_state(state);
14541                 if (ret)
14542                         return ret;
14543         }
14544
14545         ret = intel_modeset_calc_cdclk(state);
14546         if (ret)
14547                 return ret;
14548
14549         intel_modeset_clear_plls(state);
14550
14551         if (IS_HASWELL(dev_priv))
14552                 return hsw_mode_set_planes_workaround(state);
14553
14554         return 0;
14555 }
14556
14557 /*
14558  * Handle calculation of various watermark data at the end of the atomic check
14559  * phase.  The code here should be run after the per-crtc and per-plane 'check'
14560  * handlers to ensure that all derived state has been updated.
14561  */
14562 static int calc_watermark_data(struct intel_atomic_state *state)
14563 {
14564         struct drm_device *dev = state->base.dev;
14565         struct drm_i915_private *dev_priv = to_i915(dev);
14566
14567         /* Is there platform-specific watermark information to calculate? */
14568         if (dev_priv->display.compute_global_watermarks)
14569                 return dev_priv->display.compute_global_watermarks(state);
14570
14571         return 0;
14572 }
14573
14574 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
14575                                      struct intel_crtc_state *new_crtc_state)
14576 {
14577         if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
14578                 return;
14579
14580         new_crtc_state->uapi.mode_changed = false;
14581         new_crtc_state->update_pipe = true;
14582 }
14583
14584 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
14585                                     struct intel_crtc_state *new_crtc_state)
14586 {
14587         /*
14588          * If we're not doing the full modeset we want to
14589          * keep the current M/N values as they may be
14590          * sufficiently different to the computed values
14591          * to cause problems.
14592          *
14593          * FIXME: should really copy more fuzzy state here
14594          */
14595         new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
14596         new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
14597         new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
14598         new_crtc_state->has_drrs = old_crtc_state->has_drrs;
14599 }
14600
14601 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
14602                                           struct intel_crtc *crtc,
14603                                           u8 plane_ids_mask)
14604 {
14605         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14606         struct intel_plane *plane;
14607
14608         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
14609                 struct intel_plane_state *plane_state;
14610
14611                 if ((plane_ids_mask & BIT(plane->id)) == 0)
14612                         continue;
14613
14614                 plane_state = intel_atomic_get_plane_state(state, plane);
14615                 if (IS_ERR(plane_state))
14616                         return PTR_ERR(plane_state);
14617         }
14618
14619         return 0;
14620 }
14621
14622 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
14623 {
14624         /* See {hsw,vlv,ivb}_plane_ratio() */
14625         return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
14626                 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
14627                 IS_IVYBRIDGE(dev_priv);
14628 }
14629
14630 static int intel_atomic_check_planes(struct intel_atomic_state *state,
14631                                      bool *need_cdclk_calc)
14632 {
14633         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
14634         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14635         struct intel_plane_state *plane_state;
14636         struct intel_plane *plane;
14637         struct intel_crtc *crtc;
14638         int i, ret;
14639
14640         ret = icl_add_linked_planes(state);
14641         if (ret)
14642                 return ret;
14643
14644         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14645                 ret = intel_plane_atomic_check(state, plane);
14646                 if (ret) {
14647                         drm_dbg_atomic(&dev_priv->drm,
14648                                        "[PLANE:%d:%s] atomic driver check failed\n",
14649                                        plane->base.base.id, plane->base.name);
14650                         return ret;
14651                 }
14652         }
14653
14654         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14655                                             new_crtc_state, i) {
14656                 u8 old_active_planes, new_active_planes;
14657
14658                 ret = icl_check_nv12_planes(new_crtc_state);
14659                 if (ret)
14660                         return ret;
14661
14662                 /*
14663                  * On some platforms the number of active planes affects
14664                  * the planes' minimum cdclk calculation. Add such planes
14665                  * to the state before we compute the minimum cdclk.
14666                  */
14667                 if (!active_planes_affects_min_cdclk(dev_priv))
14668                         continue;
14669
14670                 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14671                 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
14672
14673                 if (hweight8(old_active_planes) == hweight8(new_active_planes))
14674                         continue;
14675
14676                 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
14677                 if (ret)
14678                         return ret;
14679         }
14680
14681         /*
14682          * active_planes bitmask has been updated, and potentially
14683          * affected planes are part of the state. We can now
14684          * compute the minimum cdclk for each plane.
14685          */
14686         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
14687                 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
14688                 if (ret)
14689                         return ret;
14690         }
14691
14692         return 0;
14693 }
14694
14695 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
14696 {
14697         struct intel_crtc_state *crtc_state;
14698         struct intel_crtc *crtc;
14699         int i;
14700
14701         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
14702                 int ret = intel_crtc_atomic_check(state, crtc);
14703                 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
14704                 if (ret) {
14705                         drm_dbg_atomic(&i915->drm,
14706                                        "[CRTC:%d:%s] atomic driver check failed\n",
14707                                        crtc->base.base.id, crtc->base.name);
14708                         return ret;
14709                 }
14710         }
14711
14712         return 0;
14713 }
14714
14715 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
14716                                                u8 transcoders)
14717 {
14718         const struct intel_crtc_state *new_crtc_state;
14719         struct intel_crtc *crtc;
14720         int i;
14721
14722         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14723                 if (new_crtc_state->hw.enable &&
14724                     transcoders & BIT(new_crtc_state->cpu_transcoder) &&
14725                     needs_modeset(new_crtc_state))
14726                         return true;
14727         }
14728
14729         return false;
14730 }
14731
14732 /**
14733  * intel_atomic_check - validate state object
14734  * @dev: drm device
14735  * @_state: state to validate
14736  */
14737 static int intel_atomic_check(struct drm_device *dev,
14738                               struct drm_atomic_state *_state)
14739 {
14740         struct drm_i915_private *dev_priv = to_i915(dev);
14741         struct intel_atomic_state *state = to_intel_atomic_state(_state);
14742         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
14743         struct intel_cdclk_state *new_cdclk_state;
14744         struct intel_crtc *crtc;
14745         int ret, i;
14746         bool any_ms = false;
14747
14748         /* Catch I915_MODE_FLAG_INHERITED */
14749         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14750                                             new_crtc_state, i) {
14751                 if (new_crtc_state->uapi.mode.private_flags !=
14752                     old_crtc_state->uapi.mode.private_flags)
14753                         new_crtc_state->uapi.mode_changed = true;
14754         }
14755
14756         ret = drm_atomic_helper_check_modeset(dev, &state->base);
14757         if (ret)
14758                 goto fail;
14759
14760         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14761                                             new_crtc_state, i) {
14762                 if (!needs_modeset(new_crtc_state)) {
14763                         /* Light copy */
14764                         intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state);
14765
14766                         continue;
14767                 }
14768
14769                 ret = intel_crtc_prepare_cleared_state(new_crtc_state);
14770                 if (ret)
14771                         goto fail;
14772
14773                 if (!new_crtc_state->hw.enable)
14774                         continue;
14775
14776                 ret = intel_modeset_pipe_config(new_crtc_state);
14777                 if (ret)
14778                         goto fail;
14779         }
14780
14781         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14782                                             new_crtc_state, i) {
14783                 if (!needs_modeset(new_crtc_state))
14784                         continue;
14785
14786                 ret = intel_modeset_pipe_config_late(new_crtc_state);
14787                 if (ret)
14788                         goto fail;
14789
14790                 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
14791         }
14792
14793         /**
14794          * Check if fastset is allowed by external dependencies like other
14795          * pipes and transcoders.
14796          *
14797          * Right now it only forces a fullmodeset when the MST master
14798          * transcoder did not changed but the pipe of the master transcoder
14799          * needs a fullmodeset so all slaves also needs to do a fullmodeset or
14800          * in case of port synced crtcs, if one of the synced crtcs
14801          * needs a full modeset, all other synced crtcs should be
14802          * forced a full modeset.
14803          */
14804         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
14805                 if (!new_crtc_state->hw.enable || needs_modeset(new_crtc_state))
14806                         continue;
14807
14808                 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
14809                         enum transcoder master = new_crtc_state->mst_master_transcoder;
14810
14811                         if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
14812                                 new_crtc_state->uapi.mode_changed = true;
14813                                 new_crtc_state->update_pipe = false;
14814                         }
14815                 }
14816
14817                 if (is_trans_port_sync_mode(new_crtc_state)) {
14818                         u8 trans = new_crtc_state->sync_mode_slaves_mask;
14819
14820                         if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
14821                                 trans |= BIT(new_crtc_state->master_transcoder);
14822
14823                         if (intel_cpu_transcoders_need_modeset(state, trans)) {
14824                                 new_crtc_state->uapi.mode_changed = true;
14825                                 new_crtc_state->update_pipe = false;
14826                         }
14827                 }
14828         }
14829
14830         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14831                                             new_crtc_state, i) {
14832                 if (needs_modeset(new_crtc_state)) {
14833                         any_ms = true;
14834                         continue;
14835                 }
14836
14837                 if (!new_crtc_state->update_pipe)
14838                         continue;
14839
14840                 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
14841         }
14842
14843         if (any_ms && !check_digital_port_conflicts(state)) {
14844                 drm_dbg_kms(&dev_priv->drm,
14845                             "rejecting conflicting digital port configuration\n");
14846                 ret = EINVAL;
14847                 goto fail;
14848         }
14849
14850         ret = drm_dp_mst_atomic_check(&state->base);
14851         if (ret)
14852                 goto fail;
14853
14854         ret = intel_atomic_check_planes(state, &any_ms);
14855         if (ret)
14856                 goto fail;
14857
14858         new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
14859         if (new_cdclk_state && new_cdclk_state->force_min_cdclk_changed)
14860                 any_ms = true;
14861
14862         /*
14863          * distrust_bios_wm will force a full dbuf recomputation
14864          * but the hardware state will only get updated accordingly
14865          * if state->modeset==true. Hence distrust_bios_wm==true &&
14866          * state->modeset==false is an invalid combination which
14867          * would cause the hardware and software dbuf state to get
14868          * out of sync. We must prevent that.
14869          *
14870          * FIXME clean up this mess and introduce better
14871          * state tracking for dbuf.
14872          */
14873         if (dev_priv->wm.distrust_bios_wm)
14874                 any_ms = true;
14875
14876         if (any_ms) {
14877                 ret = intel_modeset_checks(state);
14878                 if (ret)
14879                         goto fail;
14880         }
14881
14882         ret = intel_atomic_check_crtcs(state);
14883         if (ret)
14884                 goto fail;
14885
14886         intel_fbc_choose_crtc(dev_priv, state);
14887         ret = calc_watermark_data(state);
14888         if (ret)
14889                 goto fail;
14890
14891         ret = intel_bw_atomic_check(state);
14892         if (ret)
14893                 goto fail;
14894
14895         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14896                                             new_crtc_state, i) {
14897                 if (!needs_modeset(new_crtc_state) &&
14898                     !new_crtc_state->update_pipe)
14899                         continue;
14900
14901                 intel_dump_pipe_config(new_crtc_state, state,
14902                                        needs_modeset(new_crtc_state) ?
14903                                        "[modeset]" : "[fastset]");
14904         }
14905
14906         return 0;
14907
14908  fail:
14909         if (ret == -EDEADLK)
14910                 return ret;
14911
14912         /*
14913          * FIXME would probably be nice to know which crtc specifically
14914          * caused the failure, in cases where we can pinpoint it.
14915          */
14916         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
14917                                             new_crtc_state, i)
14918                 intel_dump_pipe_config(new_crtc_state, state, "[failed]");
14919
14920         return ret;
14921 }
14922
14923 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
14924 {
14925         return drm_atomic_helper_prepare_planes(state->base.dev,
14926                                                 &state->base);
14927 }
14928
14929 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14930 {
14931         struct drm_device *dev = crtc->base.dev;
14932         struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)];
14933
14934         if (!vblank->max_vblank_count)
14935                 return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
14936
14937         return crtc->base.funcs->get_vblank_counter(&crtc->base);
14938 }
14939
14940 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
14941                                   struct intel_crtc_state *crtc_state)
14942 {
14943         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14944
14945         if (!IS_GEN(dev_priv, 2) || crtc_state->active_planes)
14946                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
14947
14948         if (crtc_state->has_pch_encoder) {
14949                 enum pipe pch_transcoder =
14950                         intel_crtc_pch_transcoder(crtc);
14951
14952                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
14953         }
14954 }
14955
14956 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
14957                                const struct intel_crtc_state *new_crtc_state)
14958 {
14959         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
14960         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
14961
14962         /*
14963          * Update pipe size and adjust fitter if needed: the reason for this is
14964          * that in compute_mode_changes we check the native mode (not the pfit
14965          * mode) to see if we can flip rather than do a full mode set. In the
14966          * fastboot case, we'll flip, but if we don't update the pipesrc and
14967          * pfit state, we'll end up with a big fb scanned out into the wrong
14968          * sized surface.
14969          */
14970         intel_set_pipe_src_size(new_crtc_state);
14971
14972         /* on skylake this is done by detaching scalers */
14973         if (INTEL_GEN(dev_priv) >= 9) {
14974                 skl_detach_scalers(new_crtc_state);
14975
14976                 if (new_crtc_state->pch_pfit.enabled)
14977                         skl_pfit_enable(new_crtc_state);
14978         } else if (HAS_PCH_SPLIT(dev_priv)) {
14979                 if (new_crtc_state->pch_pfit.enabled)
14980                         ilk_pfit_enable(new_crtc_state);
14981                 else if (old_crtc_state->pch_pfit.enabled)
14982                         ilk_pfit_disable(old_crtc_state);
14983         }
14984
14985         /*
14986          * The register is supposedly single buffered so perhaps
14987          * not 100% correct to do this here. But SKL+ calculate
14988          * this based on the adjust pixel rate so pfit changes do
14989          * affect it and so it must be updated for fastsets.
14990          * HSW/BDW only really need this here for fastboot, after
14991          * that the value should not change without a full modeset.
14992          */
14993         if (INTEL_GEN(dev_priv) >= 9 ||
14994             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
14995                 hsw_set_linetime_wm(new_crtc_state);
14996
14997         if (INTEL_GEN(dev_priv) >= 11)
14998                 icl_set_pipe_chicken(crtc);
14999 }
15000
15001 static void commit_pipe_config(struct intel_atomic_state *state,
15002                                struct intel_crtc_state *old_crtc_state,
15003                                struct intel_crtc_state *new_crtc_state)
15004 {
15005         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
15006         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15007         bool modeset = needs_modeset(new_crtc_state);
15008
15009         /*
15010          * During modesets pipe configuration was programmed as the
15011          * CRTC was enabled.
15012          */
15013         if (!modeset) {
15014                 if (new_crtc_state->uapi.color_mgmt_changed ||
15015                     new_crtc_state->update_pipe)
15016                         intel_color_commit(new_crtc_state);
15017
15018                 if (INTEL_GEN(dev_priv) >= 9)
15019                         skl_detach_scalers(new_crtc_state);
15020
15021                 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
15022                         bdw_set_pipemisc(new_crtc_state);
15023
15024                 if (new_crtc_state->update_pipe)
15025                         intel_pipe_fastset(old_crtc_state, new_crtc_state);
15026         }
15027
15028         if (dev_priv->display.atomic_update_watermarks)
15029                 dev_priv->display.atomic_update_watermarks(state, crtc);
15030 }
15031
15032 static void intel_update_crtc(struct intel_crtc *crtc,
15033                               struct intel_atomic_state *state,
15034                               struct intel_crtc_state *old_crtc_state,
15035                               struct intel_crtc_state *new_crtc_state)
15036 {
15037         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15038         bool modeset = needs_modeset(new_crtc_state);
15039
15040         if (modeset) {
15041                 intel_crtc_update_active_timings(new_crtc_state);
15042
15043                 dev_priv->display.crtc_enable(state, crtc);
15044
15045                 /* vblanks work again, re-enable pipe CRC. */
15046                 intel_crtc_enable_pipe_crc(crtc);
15047         } else {
15048                 if (new_crtc_state->preload_luts &&
15049                     (new_crtc_state->uapi.color_mgmt_changed ||
15050                      new_crtc_state->update_pipe))
15051                         intel_color_load_luts(new_crtc_state);
15052
15053                 intel_pre_plane_update(state, crtc);
15054
15055                 if (new_crtc_state->update_pipe)
15056                         intel_encoders_update_pipe(state, crtc);
15057         }
15058
15059         if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
15060                 intel_fbc_disable(crtc);
15061         else
15062                 intel_fbc_enable(state, crtc);
15063
15064         /* Perform vblank evasion around commit operation */
15065         intel_pipe_update_start(new_crtc_state);
15066
15067         commit_pipe_config(state, old_crtc_state, new_crtc_state);
15068
15069         if (INTEL_GEN(dev_priv) >= 9)
15070                 skl_update_planes_on_crtc(state, crtc);
15071         else
15072                 i9xx_update_planes_on_crtc(state, crtc);
15073
15074         intel_pipe_update_end(new_crtc_state);
15075
15076         /*
15077          * We usually enable FIFO underrun interrupts as part of the
15078          * CRTC enable sequence during modesets.  But when we inherit a
15079          * valid pipe configuration from the BIOS we need to take care
15080          * of enabling them on the CRTC's first fastset.
15081          */
15082         if (new_crtc_state->update_pipe && !modeset &&
15083             old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
15084                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
15085 }
15086
15087 static struct intel_crtc *intel_get_slave_crtc(const struct intel_crtc_state *new_crtc_state)
15088 {
15089         struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev);
15090         enum transcoder slave_transcoder;
15091
15092         drm_WARN_ON(&dev_priv->drm,
15093                     !is_power_of_2(new_crtc_state->sync_mode_slaves_mask));
15094
15095         slave_transcoder = ffs(new_crtc_state->sync_mode_slaves_mask) - 1;
15096         return intel_get_crtc_for_pipe(dev_priv,
15097                                        (enum pipe)slave_transcoder);
15098 }
15099
15100 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
15101                                           struct intel_crtc_state *old_crtc_state,
15102                                           struct intel_crtc_state *new_crtc_state,
15103                                           struct intel_crtc *crtc)
15104 {
15105         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15106
15107         intel_crtc_disable_planes(state, crtc);
15108
15109         /*
15110          * We need to disable pipe CRC before disabling the pipe,
15111          * or we race against vblank off.
15112          */
15113         intel_crtc_disable_pipe_crc(crtc);
15114
15115         dev_priv->display.crtc_disable(state, crtc);
15116         crtc->active = false;
15117         intel_fbc_disable(crtc);
15118         intel_disable_shared_dpll(old_crtc_state);
15119
15120         /* FIXME unify this for all platforms */
15121         if (!new_crtc_state->hw.active &&
15122             !HAS_GMCH(dev_priv) &&
15123             dev_priv->display.initial_watermarks)
15124                 dev_priv->display.initial_watermarks(state, crtc);
15125 }
15126
15127 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
15128 {
15129         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
15130         struct intel_crtc *crtc;
15131         u32 handled = 0;
15132         int i;
15133
15134         /* Only disable port sync and MST slaves */
15135         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15136                                             new_crtc_state, i) {
15137                 if (!needs_modeset(new_crtc_state))
15138                         continue;
15139
15140                 if (!old_crtc_state->hw.active)
15141                         continue;
15142
15143                 /* In case of Transcoder port Sync master slave CRTCs can be
15144                  * assigned in any order and we need to make sure that
15145                  * slave CRTCs are disabled first and then master CRTC since
15146                  * Slave vblanks are masked till Master Vblanks.
15147                  */
15148                 if (!is_trans_port_sync_slave(old_crtc_state) &&
15149                     !intel_dp_mst_is_slave_trans(old_crtc_state))
15150                         continue;
15151
15152                 intel_pre_plane_update(state, crtc);
15153                 intel_old_crtc_state_disables(state, old_crtc_state,
15154                                               new_crtc_state, crtc);
15155                 handled |= BIT(crtc->pipe);
15156         }
15157
15158         /* Disable everything else left on */
15159         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15160                                             new_crtc_state, i) {
15161                 if (!needs_modeset(new_crtc_state) ||
15162                     (handled & BIT(crtc->pipe)))
15163                         continue;
15164
15165                 intel_pre_plane_update(state, crtc);
15166                 if (old_crtc_state->hw.active)
15167                         intel_old_crtc_state_disables(state, old_crtc_state,
15168                                                       new_crtc_state, crtc);
15169         }
15170 }
15171
15172 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
15173 {
15174         struct intel_crtc *crtc;
15175         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15176         int i;
15177
15178         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15179                 if (!new_crtc_state->hw.active)
15180                         continue;
15181
15182                 intel_update_crtc(crtc, state, old_crtc_state,
15183                                   new_crtc_state);
15184         }
15185 }
15186
15187 static void intel_crtc_enable_trans_port_sync(struct intel_crtc *crtc,
15188                                               struct intel_atomic_state *state,
15189                                               struct intel_crtc_state *new_crtc_state)
15190 {
15191         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15192
15193         intel_crtc_update_active_timings(new_crtc_state);
15194         dev_priv->display.crtc_enable(state, crtc);
15195         intel_crtc_enable_pipe_crc(crtc);
15196 }
15197
15198 static void intel_set_dp_tp_ctl_normal(struct intel_crtc *crtc,
15199                                        struct intel_atomic_state *state)
15200 {
15201         struct drm_connector *uninitialized_var(conn);
15202         struct drm_connector_state *conn_state;
15203         struct intel_dp *intel_dp;
15204         int i;
15205
15206         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
15207                 if (conn_state->crtc == &crtc->base)
15208                         break;
15209         }
15210         intel_dp = intel_attached_dp(to_intel_connector(conn));
15211         intel_dp_stop_link_train(intel_dp);
15212 }
15213
15214 /*
15215  * TODO: This is only called from port sync and it is identical to what will be
15216  * executed again in intel_update_crtc() over port sync pipes
15217  */
15218 static void intel_post_crtc_enable_updates(struct intel_crtc *crtc,
15219                                            struct intel_atomic_state *state)
15220 {
15221         struct intel_crtc_state *new_crtc_state =
15222                 intel_atomic_get_new_crtc_state(state, crtc);
15223         struct intel_crtc_state *old_crtc_state =
15224                 intel_atomic_get_old_crtc_state(state, crtc);
15225         bool modeset = needs_modeset(new_crtc_state);
15226
15227         if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
15228                 intel_fbc_disable(crtc);
15229         else
15230                 intel_fbc_enable(state, crtc);
15231
15232         /* Perform vblank evasion around commit operation */
15233         intel_pipe_update_start(new_crtc_state);
15234         commit_pipe_config(state, old_crtc_state, new_crtc_state);
15235         skl_update_planes_on_crtc(state, crtc);
15236         intel_pipe_update_end(new_crtc_state);
15237
15238         /*
15239          * We usually enable FIFO underrun interrupts as part of the
15240          * CRTC enable sequence during modesets.  But when we inherit a
15241          * valid pipe configuration from the BIOS we need to take care
15242          * of enabling them on the CRTC's first fastset.
15243          */
15244         if (new_crtc_state->update_pipe && !modeset &&
15245             old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
15246                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
15247 }
15248
15249 static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
15250                                                struct intel_atomic_state *state,
15251                                                struct intel_crtc_state *old_crtc_state,
15252                                                struct intel_crtc_state *new_crtc_state)
15253 {
15254         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
15255         struct intel_crtc *slave_crtc = intel_get_slave_crtc(new_crtc_state);
15256         struct intel_crtc_state *new_slave_crtc_state =
15257                 intel_atomic_get_new_crtc_state(state, slave_crtc);
15258         struct intel_crtc_state *old_slave_crtc_state =
15259                 intel_atomic_get_old_crtc_state(state, slave_crtc);
15260
15261         drm_WARN_ON(&i915->drm, !slave_crtc || !new_slave_crtc_state ||
15262                     !old_slave_crtc_state);
15263
15264         drm_dbg_kms(&i915->drm,
15265                     "Updating Transcoder Port Sync Master CRTC = %d %s and Slave CRTC %d %s\n",
15266                     crtc->base.base.id, crtc->base.name,
15267                     slave_crtc->base.base.id, slave_crtc->base.name);
15268
15269         /* Enable seq for slave with with DP_TP_CTL left Idle until the
15270          * master is ready
15271          */
15272         intel_crtc_enable_trans_port_sync(slave_crtc,
15273                                           state,
15274                                           new_slave_crtc_state);
15275
15276         /* Enable seq for master with with DP_TP_CTL left Idle */
15277         intel_crtc_enable_trans_port_sync(crtc,
15278                                           state,
15279                                           new_crtc_state);
15280
15281         /* Set Slave's DP_TP_CTL to Normal */
15282         intel_set_dp_tp_ctl_normal(slave_crtc,
15283                                    state);
15284
15285         /* Set Master's DP_TP_CTL To Normal */
15286         usleep_range(200, 400);
15287         intel_set_dp_tp_ctl_normal(crtc,
15288                                    state);
15289
15290         /* Now do the post crtc enable for all master and slaves */
15291         intel_post_crtc_enable_updates(slave_crtc,
15292                                        state);
15293         intel_post_crtc_enable_updates(crtc,
15294                                        state);
15295 }
15296
15297 static void icl_dbuf_slice_pre_update(struct intel_atomic_state *state)
15298 {
15299         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15300         u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_mask;
15301         u8 required_slices = state->enabled_dbuf_slices_mask;
15302         u8 slices_union = hw_enabled_slices | required_slices;
15303
15304         /* If 2nd DBuf slice required, enable it here */
15305         if (INTEL_GEN(dev_priv) >= 11 && slices_union != hw_enabled_slices)
15306                 icl_dbuf_slices_update(dev_priv, slices_union);
15307 }
15308
15309 static void icl_dbuf_slice_post_update(struct intel_atomic_state *state)
15310 {
15311         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15312         u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_mask;
15313         u8 required_slices = state->enabled_dbuf_slices_mask;
15314
15315         /* If 2nd DBuf slice is no more required disable it */
15316         if (INTEL_GEN(dev_priv) >= 11 && required_slices != hw_enabled_slices)
15317                 icl_dbuf_slices_update(dev_priv, required_slices);
15318 }
15319
15320 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
15321 {
15322         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
15323         struct intel_crtc *crtc;
15324         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
15325         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
15326         u8 update_pipes = 0, modeset_pipes = 0;
15327         int i;
15328
15329         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15330                 enum pipe pipe = crtc->pipe;
15331
15332                 if (!new_crtc_state->hw.active)
15333                         continue;
15334
15335                 /* ignore allocations for crtc's that have been turned off. */
15336                 if (!needs_modeset(new_crtc_state)) {
15337                         entries[pipe] = old_crtc_state->wm.skl.ddb;
15338                         update_pipes |= BIT(pipe);
15339                 } else {
15340                         modeset_pipes |= BIT(pipe);
15341                 }
15342         }
15343
15344         /*
15345          * Whenever the number of active pipes changes, we need to make sure we
15346          * update the pipes in the right order so that their ddb allocations
15347          * never overlap with each other between CRTC updates. Otherwise we'll
15348          * cause pipe underruns and other bad stuff.
15349          *
15350          * So first lets enable all pipes that do not need a fullmodeset as
15351          * those don't have any external dependency.
15352          */
15353         while (update_pipes) {
15354                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15355                                                     new_crtc_state, i) {
15356                         enum pipe pipe = crtc->pipe;
15357
15358                         if ((update_pipes & BIT(pipe)) == 0)
15359                                 continue;
15360
15361                         if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15362                                                         entries, I915_MAX_PIPES, pipe))
15363                                 continue;
15364
15365                         entries[pipe] = new_crtc_state->wm.skl.ddb;
15366                         update_pipes &= ~BIT(pipe);
15367
15368                         intel_update_crtc(crtc, state, old_crtc_state,
15369                                           new_crtc_state);
15370
15371                         /*
15372                          * If this is an already active pipe, it's DDB changed,
15373                          * and this isn't the last pipe that needs updating
15374                          * then we need to wait for a vblank to pass for the
15375                          * new ddb allocation to take effect.
15376                          */
15377                         if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
15378                                                  &old_crtc_state->wm.skl.ddb) &&
15379                             (update_pipes | modeset_pipes))
15380                                 intel_wait_for_vblank(dev_priv, pipe);
15381                 }
15382         }
15383
15384         /*
15385          * Enable all pipes that needs a modeset and do not depends on other
15386          * pipes
15387          */
15388         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15389                                             new_crtc_state, i) {
15390                 enum pipe pipe = crtc->pipe;
15391
15392                 if ((modeset_pipes & BIT(pipe)) == 0)
15393                         continue;
15394
15395                 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
15396                     is_trans_port_sync_slave(new_crtc_state))
15397                         continue;
15398
15399                 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15400                                                                         entries, I915_MAX_PIPES, pipe));
15401
15402                 entries[pipe] = new_crtc_state->wm.skl.ddb;
15403                 modeset_pipes &= ~BIT(pipe);
15404
15405                 if (is_trans_port_sync_mode(new_crtc_state)) {
15406                         struct intel_crtc *slave_crtc;
15407
15408                         intel_update_trans_port_sync_crtcs(crtc, state,
15409                                                            old_crtc_state,
15410                                                            new_crtc_state);
15411
15412                         slave_crtc = intel_get_slave_crtc(new_crtc_state);
15413                         /* TODO: update entries[] of slave */
15414                         modeset_pipes &= ~BIT(slave_crtc->pipe);
15415
15416                 } else {
15417                         intel_update_crtc(crtc, state, old_crtc_state,
15418                                           new_crtc_state);
15419                 }
15420         }
15421
15422         /*
15423          * Finally enable all pipes that needs a modeset and depends on
15424          * other pipes, right now it is only MST slaves as both port sync slave
15425          * and master are enabled together
15426          */
15427         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15428                                             new_crtc_state, i) {
15429                 enum pipe pipe = crtc->pipe;
15430
15431                 if ((modeset_pipes & BIT(pipe)) == 0)
15432                         continue;
15433
15434                 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
15435                                                                         entries, I915_MAX_PIPES, pipe));
15436
15437                 entries[pipe] = new_crtc_state->wm.skl.ddb;
15438                 modeset_pipes &= ~BIT(pipe);
15439
15440                 intel_update_crtc(crtc, state, old_crtc_state, new_crtc_state);
15441         }
15442
15443         drm_WARN_ON(&dev_priv->drm, modeset_pipes);
15444
15445 }
15446
15447 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
15448 {
15449         struct intel_atomic_state *state, *next;
15450         struct llist_node *freed;
15451
15452         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
15453         llist_for_each_entry_safe(state, next, freed, freed)
15454                 drm_atomic_state_put(&state->base);
15455 }
15456
15457 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
15458 {
15459         struct drm_i915_private *dev_priv =
15460                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
15461
15462         intel_atomic_helper_free_state(dev_priv);
15463 }
15464
15465 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
15466 {
15467         struct wait_queue_entry wait_fence, wait_reset;
15468         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
15469
15470         init_wait_entry(&wait_fence, 0);
15471         init_wait_entry(&wait_reset, 0);
15472         for (;;) {
15473                 prepare_to_wait(&intel_state->commit_ready.wait,
15474                                 &wait_fence, TASK_UNINTERRUPTIBLE);
15475                 prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
15476                                               I915_RESET_MODESET),
15477                                 &wait_reset, TASK_UNINTERRUPTIBLE);
15478
15479
15480                 if (i915_sw_fence_done(&intel_state->commit_ready) ||
15481                     test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
15482                         break;
15483
15484                 schedule();
15485         }
15486         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
15487         finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
15488                                   I915_RESET_MODESET),
15489                     &wait_reset);
15490 }
15491
15492 static void intel_atomic_cleanup_work(struct work_struct *work)
15493 {
15494         struct drm_atomic_state *state =
15495                 container_of(work, struct drm_atomic_state, commit_work);
15496         struct drm_i915_private *i915 = to_i915(state->dev);
15497
15498         drm_atomic_helper_cleanup_planes(&i915->drm, state);
15499         drm_atomic_helper_commit_cleanup_done(state);
15500         drm_atomic_state_put(state);
15501
15502         intel_atomic_helper_free_state(i915);
15503 }
15504
15505 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
15506 {
15507         struct drm_device *dev = state->base.dev;
15508         struct drm_i915_private *dev_priv = to_i915(dev);
15509         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
15510         struct intel_crtc *crtc;
15511         u64 put_domains[I915_MAX_PIPES] = {};
15512         intel_wakeref_t wakeref = 0;
15513         int i;
15514
15515         intel_atomic_commit_fence_wait(state);
15516
15517         drm_atomic_helper_wait_for_dependencies(&state->base);
15518
15519         if (state->modeset)
15520                 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
15521
15522         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15523                                             new_crtc_state, i) {
15524                 if (needs_modeset(new_crtc_state) ||
15525                     new_crtc_state->update_pipe) {
15526
15527                         put_domains[crtc->pipe] =
15528                                 modeset_get_crtc_power_domains(new_crtc_state);
15529                 }
15530         }
15531
15532         intel_commit_modeset_disables(state);
15533
15534         /* FIXME: Eventually get rid of our crtc->config pointer */
15535         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15536                 crtc->config = new_crtc_state;
15537
15538         if (state->modeset) {
15539                 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
15540
15541                 intel_set_cdclk_pre_plane_update(state);
15542
15543                 /*
15544                  * SKL workaround: bspec recommends we disable the SAGV when we
15545                  * have more then one pipe enabled
15546                  */
15547                 if (!intel_can_enable_sagv(state))
15548                         intel_disable_sagv(dev_priv);
15549
15550                 intel_modeset_verify_disabled(dev_priv, state);
15551         }
15552
15553         /* Complete the events for pipes that have now been disabled */
15554         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15555                 bool modeset = needs_modeset(new_crtc_state);
15556
15557                 /* Complete events for now disable pipes here. */
15558                 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
15559                         spin_lock_irq(&dev->event_lock);
15560                         drm_crtc_send_vblank_event(&crtc->base,
15561                                                    new_crtc_state->uapi.event);
15562                         spin_unlock_irq(&dev->event_lock);
15563
15564                         new_crtc_state->uapi.event = NULL;
15565                 }
15566         }
15567
15568         if (state->modeset)
15569                 intel_encoders_update_prepare(state);
15570
15571         /* Enable all new slices, we might need */
15572         if (state->modeset)
15573                 icl_dbuf_slice_pre_update(state);
15574
15575         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
15576         dev_priv->display.commit_modeset_enables(state);
15577
15578         if (state->modeset) {
15579                 intel_encoders_update_complete(state);
15580
15581                 intel_set_cdclk_post_plane_update(state);
15582         }
15583
15584         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
15585          * already, but still need the state for the delayed optimization. To
15586          * fix this:
15587          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
15588          * - schedule that vblank worker _before_ calling hw_done
15589          * - at the start of commit_tail, cancel it _synchrously
15590          * - switch over to the vblank wait helper in the core after that since
15591          *   we don't need out special handling any more.
15592          */
15593         drm_atomic_helper_wait_for_flip_done(dev, &state->base);
15594
15595         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
15596                 if (new_crtc_state->hw.active &&
15597                     !needs_modeset(new_crtc_state) &&
15598                     !new_crtc_state->preload_luts &&
15599                     (new_crtc_state->uapi.color_mgmt_changed ||
15600                      new_crtc_state->update_pipe))
15601                         intel_color_load_luts(new_crtc_state);
15602         }
15603
15604         /*
15605          * Now that the vblank has passed, we can go ahead and program the
15606          * optimal watermarks on platforms that need two-step watermark
15607          * programming.
15608          *
15609          * TODO: Move this (and other cleanup) to an async worker eventually.
15610          */
15611         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
15612                                             new_crtc_state, i) {
15613                 /*
15614                  * Gen2 reports pipe underruns whenever all planes are disabled.
15615                  * So re-enable underrun reporting after some planes get enabled.
15616                  *
15617                  * We do this before .optimize_watermarks() so that we have a
15618                  * chance of catching underruns with the intermediate watermarks
15619                  * vs. the new plane configuration.
15620                  */
15621                 if (IS_GEN(dev_priv, 2) && planes_enabling(old_crtc_state, new_crtc_state))
15622                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
15623
15624                 if (dev_priv->display.optimize_watermarks)
15625                         dev_priv->display.optimize_watermarks(state, crtc);
15626         }
15627
15628         /* Disable all slices, we don't need */
15629         if (state->modeset)
15630                 icl_dbuf_slice_post_update(state);
15631
15632         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
15633                 intel_post_plane_update(state, crtc);
15634
15635                 if (put_domains[i])
15636                         modeset_put_power_domains(dev_priv, put_domains[i]);
15637
15638                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
15639         }
15640
15641         /* Underruns don't always raise interrupts, so check manually */
15642         intel_check_cpu_fifo_underruns(dev_priv);
15643         intel_check_pch_fifo_underruns(dev_priv);
15644
15645         if (state->modeset)
15646                 intel_verify_planes(state);
15647
15648         if (state->modeset && intel_can_enable_sagv(state))
15649                 intel_enable_sagv(dev_priv);
15650
15651         drm_atomic_helper_commit_hw_done(&state->base);
15652
15653         if (state->modeset) {
15654                 /* As one of the primary mmio accessors, KMS has a high
15655                  * likelihood of triggering bugs in unclaimed access. After we
15656                  * finish modesetting, see if an error has been flagged, and if
15657                  * so enable debugging for the next modeset - and hope we catch
15658                  * the culprit.
15659                  */
15660                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
15661                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
15662         }
15663         intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15664
15665         /*
15666          * Defer the cleanup of the old state to a separate worker to not
15667          * impede the current task (userspace for blocking modesets) that
15668          * are executed inline. For out-of-line asynchronous modesets/flips,
15669          * deferring to a new worker seems overkill, but we would place a
15670          * schedule point (cond_resched()) here anyway to keep latencies
15671          * down.
15672          */
15673         INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
15674         queue_work(system_highpri_wq, &state->base.commit_work);
15675 }
15676
15677 static void intel_atomic_commit_work(struct work_struct *work)
15678 {
15679         struct intel_atomic_state *state =
15680                 container_of(work, struct intel_atomic_state, base.commit_work);
15681
15682         intel_atomic_commit_tail(state);
15683 }
15684
15685 static int __i915_sw_fence_call
15686 intel_atomic_commit_ready(struct i915_sw_fence *fence,
15687                           enum i915_sw_fence_notify notify)
15688 {
15689         struct intel_atomic_state *state =
15690                 container_of(fence, struct intel_atomic_state, commit_ready);
15691
15692         switch (notify) {
15693         case FENCE_COMPLETE:
15694                 /* we do blocking waits in the worker, nothing to do here */
15695                 break;
15696         case FENCE_FREE:
15697                 {
15698                         struct intel_atomic_helper *helper =
15699                                 &to_i915(state->base.dev)->atomic_helper;
15700
15701                         if (llist_add(&state->freed, &helper->free_list))
15702                                 schedule_work(&helper->free_work);
15703                         break;
15704                 }
15705         }
15706
15707         return NOTIFY_DONE;
15708 }
15709
15710 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
15711 {
15712         struct intel_plane_state *old_plane_state, *new_plane_state;
15713         struct intel_plane *plane;
15714         int i;
15715
15716         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
15717                                              new_plane_state, i)
15718                 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
15719                                         to_intel_frontbuffer(new_plane_state->hw.fb),
15720                                         plane->frontbuffer_bit);
15721 }
15722
15723 static void assert_global_state_locked(struct drm_i915_private *dev_priv)
15724 {
15725         struct intel_crtc *crtc;
15726
15727         for_each_intel_crtc(&dev_priv->drm, crtc)
15728                 drm_modeset_lock_assert_held(&crtc->base.mutex);
15729 }
15730
15731 static int intel_atomic_commit(struct drm_device *dev,
15732                                struct drm_atomic_state *_state,
15733                                bool nonblock)
15734 {
15735         struct intel_atomic_state *state = to_intel_atomic_state(_state);
15736         struct drm_i915_private *dev_priv = to_i915(dev);
15737         int ret = 0;
15738
15739         state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
15740
15741         drm_atomic_state_get(&state->base);
15742         i915_sw_fence_init(&state->commit_ready,
15743                            intel_atomic_commit_ready);
15744
15745         /*
15746          * The intel_legacy_cursor_update() fast path takes care
15747          * of avoiding the vblank waits for simple cursor
15748          * movement and flips. For cursor on/off and size changes,
15749          * we want to perform the vblank waits so that watermark
15750          * updates happen during the correct frames. Gen9+ have
15751          * double buffered watermarks and so shouldn't need this.
15752          *
15753          * Unset state->legacy_cursor_update before the call to
15754          * drm_atomic_helper_setup_commit() because otherwise
15755          * drm_atomic_helper_wait_for_flip_done() is a noop and
15756          * we get FIFO underruns because we didn't wait
15757          * for vblank.
15758          *
15759          * FIXME doing watermarks and fb cleanup from a vblank worker
15760          * (assuming we had any) would solve these problems.
15761          */
15762         if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
15763                 struct intel_crtc_state *new_crtc_state;
15764                 struct intel_crtc *crtc;
15765                 int i;
15766
15767                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
15768                         if (new_crtc_state->wm.need_postvbl_update ||
15769                             new_crtc_state->update_wm_post)
15770                                 state->base.legacy_cursor_update = false;
15771         }
15772
15773         ret = intel_atomic_prepare_commit(state);
15774         if (ret) {
15775                 drm_dbg_atomic(&dev_priv->drm,
15776                                "Preparing state failed with %i\n", ret);
15777                 i915_sw_fence_commit(&state->commit_ready);
15778                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15779                 return ret;
15780         }
15781
15782         ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
15783         if (!ret)
15784                 ret = drm_atomic_helper_swap_state(&state->base, true);
15785         if (!ret)
15786                 intel_atomic_swap_global_state(state);
15787
15788         if (ret) {
15789                 i915_sw_fence_commit(&state->commit_ready);
15790
15791                 drm_atomic_helper_cleanup_planes(dev, &state->base);
15792                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
15793                 return ret;
15794         }
15795         dev_priv->wm.distrust_bios_wm = false;
15796         intel_shared_dpll_swap_state(state);
15797         intel_atomic_track_fbs(state);
15798
15799         if (state->global_state_changed) {
15800                 assert_global_state_locked(dev_priv);
15801
15802                 dev_priv->active_pipes = state->active_pipes;
15803         }
15804
15805         drm_atomic_state_get(&state->base);
15806         INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
15807
15808         i915_sw_fence_commit(&state->commit_ready);
15809         if (nonblock && state->modeset) {
15810                 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
15811         } else if (nonblock) {
15812                 queue_work(dev_priv->flip_wq, &state->base.commit_work);
15813         } else {
15814                 if (state->modeset)
15815                         flush_workqueue(dev_priv->modeset_wq);
15816                 intel_atomic_commit_tail(state);
15817         }
15818
15819         return 0;
15820 }
15821
15822 struct wait_rps_boost {
15823         struct wait_queue_entry wait;
15824
15825         struct drm_crtc *crtc;
15826         struct i915_request *request;
15827 };
15828
15829 static int do_rps_boost(struct wait_queue_entry *_wait,
15830                         unsigned mode, int sync, void *key)
15831 {
15832         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
15833         struct i915_request *rq = wait->request;
15834
15835         /*
15836          * If we missed the vblank, but the request is already running it
15837          * is reasonable to assume that it will complete before the next
15838          * vblank without our intervention, so leave RPS alone.
15839          */
15840         if (!i915_request_started(rq))
15841                 intel_rps_boost(rq);
15842         i915_request_put(rq);
15843
15844         drm_crtc_vblank_put(wait->crtc);
15845
15846         list_del(&wait->wait.entry);
15847         kfree(wait);
15848         return 1;
15849 }
15850
15851 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
15852                                        struct dma_fence *fence)
15853 {
15854         struct wait_rps_boost *wait;
15855
15856         if (!dma_fence_is_i915(fence))
15857                 return;
15858
15859         if (INTEL_GEN(to_i915(crtc->dev)) < 6)
15860                 return;
15861
15862         if (drm_crtc_vblank_get(crtc))
15863                 return;
15864
15865         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
15866         if (!wait) {
15867                 drm_crtc_vblank_put(crtc);
15868                 return;
15869         }
15870
15871         wait->request = to_request(dma_fence_get(fence));
15872         wait->crtc = crtc;
15873
15874         wait->wait.func = do_rps_boost;
15875         wait->wait.flags = 0;
15876
15877         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
15878 }
15879
15880 static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
15881 {
15882         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
15883         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15884         struct drm_framebuffer *fb = plane_state->hw.fb;
15885         struct i915_vma *vma;
15886
15887         if (plane->id == PLANE_CURSOR &&
15888             INTEL_INFO(dev_priv)->display.cursor_needs_physical) {
15889                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15890                 const int align = intel_cursor_alignment(dev_priv);
15891                 int err;
15892
15893                 err = i915_gem_object_attach_phys(obj, align);
15894                 if (err)
15895                         return err;
15896         }
15897
15898         vma = intel_pin_and_fence_fb_obj(fb,
15899                                          &plane_state->view,
15900                                          intel_plane_uses_fence(plane_state),
15901                                          &plane_state->flags);
15902         if (IS_ERR(vma))
15903                 return PTR_ERR(vma);
15904
15905         plane_state->vma = vma;
15906
15907         return 0;
15908 }
15909
15910 static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
15911 {
15912         struct i915_vma *vma;
15913
15914         vma = fetch_and_zero(&old_plane_state->vma);
15915         if (vma)
15916                 intel_unpin_fb_vma(vma, old_plane_state->flags);
15917 }
15918
15919 static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj)
15920 {
15921         struct i915_sched_attr attr = {
15922                 .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY),
15923         };
15924
15925         i915_gem_object_wait_priority(obj, 0, &attr);
15926 }
15927
15928 /**
15929  * intel_prepare_plane_fb - Prepare fb for usage on plane
15930  * @_plane: drm plane to prepare for
15931  * @_new_plane_state: the plane state being prepared
15932  *
15933  * Prepares a framebuffer for usage on a display plane.  Generally this
15934  * involves pinning the underlying object and updating the frontbuffer tracking
15935  * bits.  Some older platforms need special physical address handling for
15936  * cursor planes.
15937  *
15938  * Returns 0 on success, negative error code on failure.
15939  */
15940 int
15941 intel_prepare_plane_fb(struct drm_plane *_plane,
15942                        struct drm_plane_state *_new_plane_state)
15943 {
15944         struct intel_plane *plane = to_intel_plane(_plane);
15945         struct intel_plane_state *new_plane_state =
15946                 to_intel_plane_state(_new_plane_state);
15947         struct intel_atomic_state *state =
15948                 to_intel_atomic_state(new_plane_state->uapi.state);
15949         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15950         const struct intel_plane_state *old_plane_state =
15951                 intel_atomic_get_old_plane_state(state, plane);
15952         struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
15953         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
15954         int ret;
15955
15956         if (old_obj) {
15957                 const struct intel_crtc_state *crtc_state =
15958                         intel_atomic_get_new_crtc_state(state,
15959                                                         to_intel_crtc(old_plane_state->hw.crtc));
15960
15961                 /* Big Hammer, we also need to ensure that any pending
15962                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
15963                  * current scanout is retired before unpinning the old
15964                  * framebuffer. Note that we rely on userspace rendering
15965                  * into the buffer attached to the pipe they are waiting
15966                  * on. If not, userspace generates a GPU hang with IPEHR
15967                  * point to the MI_WAIT_FOR_EVENT.
15968                  *
15969                  * This should only fail upon a hung GPU, in which case we
15970                  * can safely continue.
15971                  */
15972                 if (needs_modeset(crtc_state)) {
15973                         ret = i915_sw_fence_await_reservation(&state->commit_ready,
15974                                                               old_obj->base.resv, NULL,
15975                                                               false, 0,
15976                                                               GFP_KERNEL);
15977                         if (ret < 0)
15978                                 return ret;
15979                 }
15980         }
15981
15982         if (new_plane_state->uapi.fence) { /* explicit fencing */
15983                 ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
15984                                                     new_plane_state->uapi.fence,
15985                                                     I915_FENCE_TIMEOUT,
15986                                                     GFP_KERNEL);
15987                 if (ret < 0)
15988                         return ret;
15989         }
15990
15991         if (!obj)
15992                 return 0;
15993
15994         ret = i915_gem_object_pin_pages(obj);
15995         if (ret)
15996                 return ret;
15997
15998         ret = intel_plane_pin_fb(new_plane_state);
15999
16000         i915_gem_object_unpin_pages(obj);
16001         if (ret)
16002                 return ret;
16003
16004         fb_obj_bump_render_priority(obj);
16005         i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB);
16006
16007         if (!new_plane_state->uapi.fence) { /* implicit fencing */
16008                 struct dma_fence *fence;
16009
16010                 ret = i915_sw_fence_await_reservation(&state->commit_ready,
16011                                                       obj->base.resv, NULL,
16012                                                       false, I915_FENCE_TIMEOUT,
16013                                                       GFP_KERNEL);
16014                 if (ret < 0)
16015                         goto unpin_fb;
16016
16017                 fence = dma_resv_get_excl_rcu(obj->base.resv);
16018                 if (fence) {
16019                         add_rps_boost_after_vblank(new_plane_state->hw.crtc,
16020                                                    fence);
16021                         dma_fence_put(fence);
16022                 }
16023         } else {
16024                 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
16025                                            new_plane_state->uapi.fence);
16026         }
16027
16028         /*
16029          * We declare pageflips to be interactive and so merit a small bias
16030          * towards upclocking to deliver the frame on time. By only changing
16031          * the RPS thresholds to sample more regularly and aim for higher
16032          * clocks we can hopefully deliver low power workloads (like kodi)
16033          * that are not quite steady state without resorting to forcing
16034          * maximum clocks following a vblank miss (see do_rps_boost()).
16035          */
16036         if (!state->rps_interactive) {
16037                 intel_rps_mark_interactive(&dev_priv->gt.rps, true);
16038                 state->rps_interactive = true;
16039         }
16040
16041         return 0;
16042
16043 unpin_fb:
16044         intel_plane_unpin_fb(new_plane_state);
16045
16046         return ret;
16047 }
16048
16049 /**
16050  * intel_cleanup_plane_fb - Cleans up an fb after plane use
16051  * @plane: drm plane to clean up for
16052  * @_old_plane_state: the state from the previous modeset
16053  *
16054  * Cleans up a framebuffer that has just been removed from a plane.
16055  */
16056 void
16057 intel_cleanup_plane_fb(struct drm_plane *plane,
16058                        struct drm_plane_state *_old_plane_state)
16059 {
16060         struct intel_plane_state *old_plane_state =
16061                 to_intel_plane_state(_old_plane_state);
16062         struct intel_atomic_state *state =
16063                 to_intel_atomic_state(old_plane_state->uapi.state);
16064         struct drm_i915_private *dev_priv = to_i915(plane->dev);
16065         struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
16066
16067         if (!obj)
16068                 return;
16069
16070         if (state->rps_interactive) {
16071                 intel_rps_mark_interactive(&dev_priv->gt.rps, false);
16072                 state->rps_interactive = false;
16073         }
16074
16075         /* Should only be called after a successful intel_prepare_plane_fb()! */
16076         intel_plane_unpin_fb(old_plane_state);
16077 }
16078
16079 /**
16080  * intel_plane_destroy - destroy a plane
16081  * @plane: plane to destroy
16082  *
16083  * Common destruction function for all types of planes (primary, cursor,
16084  * sprite).
16085  */
16086 void intel_plane_destroy(struct drm_plane *plane)
16087 {
16088         drm_plane_cleanup(plane);
16089         kfree(to_intel_plane(plane));
16090 }
16091
16092 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
16093                                             u32 format, u64 modifier)
16094 {
16095         switch (modifier) {
16096         case DRM_FORMAT_MOD_LINEAR:
16097         case I915_FORMAT_MOD_X_TILED:
16098                 break;
16099         default:
16100                 return false;
16101         }
16102
16103         switch (format) {
16104         case DRM_FORMAT_C8:
16105         case DRM_FORMAT_RGB565:
16106         case DRM_FORMAT_XRGB1555:
16107         case DRM_FORMAT_XRGB8888:
16108                 return modifier == DRM_FORMAT_MOD_LINEAR ||
16109                         modifier == I915_FORMAT_MOD_X_TILED;
16110         default:
16111                 return false;
16112         }
16113 }
16114
16115 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
16116                                             u32 format, u64 modifier)
16117 {
16118         switch (modifier) {
16119         case DRM_FORMAT_MOD_LINEAR:
16120         case I915_FORMAT_MOD_X_TILED:
16121                 break;
16122         default:
16123                 return false;
16124         }
16125
16126         switch (format) {
16127         case DRM_FORMAT_C8:
16128         case DRM_FORMAT_RGB565:
16129         case DRM_FORMAT_XRGB8888:
16130         case DRM_FORMAT_XBGR8888:
16131         case DRM_FORMAT_ARGB8888:
16132         case DRM_FORMAT_ABGR8888:
16133         case DRM_FORMAT_XRGB2101010:
16134         case DRM_FORMAT_XBGR2101010:
16135         case DRM_FORMAT_ARGB2101010:
16136         case DRM_FORMAT_ABGR2101010:
16137         case DRM_FORMAT_XBGR16161616F:
16138                 return modifier == DRM_FORMAT_MOD_LINEAR ||
16139                         modifier == I915_FORMAT_MOD_X_TILED;
16140         default:
16141                 return false;
16142         }
16143 }
16144
16145 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
16146                                               u32 format, u64 modifier)
16147 {
16148         return modifier == DRM_FORMAT_MOD_LINEAR &&
16149                 format == DRM_FORMAT_ARGB8888;
16150 }
16151
16152 static const struct drm_plane_funcs i965_plane_funcs = {
16153         .update_plane = drm_atomic_helper_update_plane,
16154         .disable_plane = drm_atomic_helper_disable_plane,
16155         .destroy = intel_plane_destroy,
16156         .atomic_duplicate_state = intel_plane_duplicate_state,
16157         .atomic_destroy_state = intel_plane_destroy_state,
16158         .format_mod_supported = i965_plane_format_mod_supported,
16159 };
16160
16161 static const struct drm_plane_funcs i8xx_plane_funcs = {
16162         .update_plane = drm_atomic_helper_update_plane,
16163         .disable_plane = drm_atomic_helper_disable_plane,
16164         .destroy = intel_plane_destroy,
16165         .atomic_duplicate_state = intel_plane_duplicate_state,
16166         .atomic_destroy_state = intel_plane_destroy_state,
16167         .format_mod_supported = i8xx_plane_format_mod_supported,
16168 };
16169
16170 static int
16171 intel_legacy_cursor_update(struct drm_plane *_plane,
16172                            struct drm_crtc *_crtc,
16173                            struct drm_framebuffer *fb,
16174                            int crtc_x, int crtc_y,
16175                            unsigned int crtc_w, unsigned int crtc_h,
16176                            u32 src_x, u32 src_y,
16177                            u32 src_w, u32 src_h,
16178                            struct drm_modeset_acquire_ctx *ctx)
16179 {
16180         struct intel_plane *plane = to_intel_plane(_plane);
16181         struct intel_crtc *crtc = to_intel_crtc(_crtc);
16182         struct intel_plane_state *old_plane_state =
16183                 to_intel_plane_state(plane->base.state);
16184         struct intel_plane_state *new_plane_state;
16185         struct intel_crtc_state *crtc_state =
16186                 to_intel_crtc_state(crtc->base.state);
16187         struct intel_crtc_state *new_crtc_state;
16188         int ret;
16189
16190         /*
16191          * When crtc is inactive or there is a modeset pending,
16192          * wait for it to complete in the slowpath
16193          */
16194         if (!crtc_state->hw.active || needs_modeset(crtc_state) ||
16195             crtc_state->update_pipe)
16196                 goto slow;
16197
16198         /*
16199          * Don't do an async update if there is an outstanding commit modifying
16200          * the plane.  This prevents our async update's changes from getting
16201          * overridden by a previous synchronous update's state.
16202          */
16203         if (old_plane_state->uapi.commit &&
16204             !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
16205                 goto slow;
16206
16207         /*
16208          * If any parameters change that may affect watermarks,
16209          * take the slowpath. Only changing fb or position should be
16210          * in the fastpath.
16211          */
16212         if (old_plane_state->uapi.crtc != &crtc->base ||
16213             old_plane_state->uapi.src_w != src_w ||
16214             old_plane_state->uapi.src_h != src_h ||
16215             old_plane_state->uapi.crtc_w != crtc_w ||
16216             old_plane_state->uapi.crtc_h != crtc_h ||
16217             !old_plane_state->uapi.fb != !fb)
16218                 goto slow;
16219
16220         new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
16221         if (!new_plane_state)
16222                 return -ENOMEM;
16223
16224         new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
16225         if (!new_crtc_state) {
16226                 ret = -ENOMEM;
16227                 goto out_free;
16228         }
16229
16230         drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
16231
16232         new_plane_state->uapi.src_x = src_x;
16233         new_plane_state->uapi.src_y = src_y;
16234         new_plane_state->uapi.src_w = src_w;
16235         new_plane_state->uapi.src_h = src_h;
16236         new_plane_state->uapi.crtc_x = crtc_x;
16237         new_plane_state->uapi.crtc_y = crtc_y;
16238         new_plane_state->uapi.crtc_w = crtc_w;
16239         new_plane_state->uapi.crtc_h = crtc_h;
16240
16241         intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
16242
16243         ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
16244                                                   old_plane_state, new_plane_state);
16245         if (ret)
16246                 goto out_free;
16247
16248         ret = intel_plane_pin_fb(new_plane_state);
16249         if (ret)
16250                 goto out_free;
16251
16252         intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
16253                                 ORIGIN_FLIP);
16254         intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
16255                                 to_intel_frontbuffer(new_plane_state->hw.fb),
16256                                 plane->frontbuffer_bit);
16257
16258         /* Swap plane state */
16259         plane->base.state = &new_plane_state->uapi;
16260
16261         /*
16262          * We cannot swap crtc_state as it may be in use by an atomic commit or
16263          * page flip that's running simultaneously. If we swap crtc_state and
16264          * destroy the old state, we will cause a use-after-free there.
16265          *
16266          * Only update active_planes, which is needed for our internal
16267          * bookkeeping. Either value will do the right thing when updating
16268          * planes atomically. If the cursor was part of the atomic update then
16269          * we would have taken the slowpath.
16270          */
16271         crtc_state->active_planes = new_crtc_state->active_planes;
16272
16273         if (new_plane_state->uapi.visible)
16274                 intel_update_plane(plane, crtc_state, new_plane_state);
16275         else
16276                 intel_disable_plane(plane, crtc_state);
16277
16278         intel_plane_unpin_fb(old_plane_state);
16279
16280 out_free:
16281         if (new_crtc_state)
16282                 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
16283         if (ret)
16284                 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
16285         else
16286                 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
16287         return ret;
16288
16289 slow:
16290         return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
16291                                               crtc_x, crtc_y, crtc_w, crtc_h,
16292                                               src_x, src_y, src_w, src_h, ctx);
16293 }
16294
16295 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
16296         .update_plane = intel_legacy_cursor_update,
16297         .disable_plane = drm_atomic_helper_disable_plane,
16298         .destroy = intel_plane_destroy,
16299         .atomic_duplicate_state = intel_plane_duplicate_state,
16300         .atomic_destroy_state = intel_plane_destroy_state,
16301         .format_mod_supported = intel_cursor_format_mod_supported,
16302 };
16303
16304 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
16305                                enum i9xx_plane_id i9xx_plane)
16306 {
16307         if (!HAS_FBC(dev_priv))
16308                 return false;
16309
16310         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
16311                 return i9xx_plane == PLANE_A; /* tied to pipe A */
16312         else if (IS_IVYBRIDGE(dev_priv))
16313                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
16314                         i9xx_plane == PLANE_C;
16315         else if (INTEL_GEN(dev_priv) >= 4)
16316                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
16317         else
16318                 return i9xx_plane == PLANE_A;
16319 }
16320
16321 static struct intel_plane *
16322 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
16323 {
16324         struct intel_plane *plane;
16325         const struct drm_plane_funcs *plane_funcs;
16326         unsigned int supported_rotations;
16327         const u32 *formats;
16328         int num_formats;
16329         int ret, zpos;
16330
16331         if (INTEL_GEN(dev_priv) >= 9)
16332                 return skl_universal_plane_create(dev_priv, pipe,
16333                                                   PLANE_PRIMARY);
16334
16335         plane = intel_plane_alloc();
16336         if (IS_ERR(plane))
16337                 return plane;
16338
16339         plane->pipe = pipe;
16340         /*
16341          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
16342          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
16343          */
16344         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
16345                 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
16346         else
16347                 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
16348         plane->id = PLANE_PRIMARY;
16349         plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
16350
16351         plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
16352         if (plane->has_fbc) {
16353                 struct intel_fbc *fbc = &dev_priv->fbc;
16354
16355                 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
16356         }
16357
16358         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16359                 formats = vlv_primary_formats;
16360                 num_formats = ARRAY_SIZE(vlv_primary_formats);
16361         } else if (INTEL_GEN(dev_priv) >= 4) {
16362                 /*
16363                  * WaFP16GammaEnabling:ivb
16364                  * "Workaround : When using the 64-bit format, the plane
16365                  *  output on each color channel has one quarter amplitude.
16366                  *  It can be brought up to full amplitude by using pipe
16367                  *  gamma correction or pipe color space conversion to
16368                  *  multiply the plane output by four."
16369                  *
16370                  * There is no dedicated plane gamma for the primary plane,
16371                  * and using the pipe gamma/csc could conflict with other
16372                  * planes, so we choose not to expose fp16 on IVB primary
16373                  * planes. HSW primary planes no longer have this problem.
16374                  */
16375                 if (IS_IVYBRIDGE(dev_priv)) {
16376                         formats = ivb_primary_formats;
16377                         num_formats = ARRAY_SIZE(ivb_primary_formats);
16378                 } else {
16379                         formats = i965_primary_formats;
16380                         num_formats = ARRAY_SIZE(i965_primary_formats);
16381                 }
16382         } else {
16383                 formats = i8xx_primary_formats;
16384                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
16385         }
16386
16387         if (INTEL_GEN(dev_priv) >= 4)
16388                 plane_funcs = &i965_plane_funcs;
16389         else
16390                 plane_funcs = &i8xx_plane_funcs;
16391
16392         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16393                 plane->min_cdclk = vlv_plane_min_cdclk;
16394         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
16395                 plane->min_cdclk = hsw_plane_min_cdclk;
16396         else if (IS_IVYBRIDGE(dev_priv))
16397                 plane->min_cdclk = ivb_plane_min_cdclk;
16398         else
16399                 plane->min_cdclk = i9xx_plane_min_cdclk;
16400
16401         plane->max_stride = i9xx_plane_max_stride;
16402         plane->update_plane = i9xx_update_plane;
16403         plane->disable_plane = i9xx_disable_plane;
16404         plane->get_hw_state = i9xx_plane_get_hw_state;
16405         plane->check_plane = i9xx_plane_check;
16406
16407         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
16408                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
16409                                                0, plane_funcs,
16410                                                formats, num_formats,
16411                                                i9xx_format_modifiers,
16412                                                DRM_PLANE_TYPE_PRIMARY,
16413                                                "primary %c", pipe_name(pipe));
16414         else
16415                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
16416                                                0, plane_funcs,
16417                                                formats, num_formats,
16418                                                i9xx_format_modifiers,
16419                                                DRM_PLANE_TYPE_PRIMARY,
16420                                                "plane %c",
16421                                                plane_name(plane->i9xx_plane));
16422         if (ret)
16423                 goto fail;
16424
16425         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
16426                 supported_rotations =
16427                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
16428                         DRM_MODE_REFLECT_X;
16429         } else if (INTEL_GEN(dev_priv) >= 4) {
16430                 supported_rotations =
16431                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
16432         } else {
16433                 supported_rotations = DRM_MODE_ROTATE_0;
16434         }
16435
16436         if (INTEL_GEN(dev_priv) >= 4)
16437                 drm_plane_create_rotation_property(&plane->base,
16438                                                    DRM_MODE_ROTATE_0,
16439                                                    supported_rotations);
16440
16441         zpos = 0;
16442         drm_plane_create_zpos_immutable_property(&plane->base, zpos);
16443
16444         drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
16445
16446         return plane;
16447
16448 fail:
16449         intel_plane_free(plane);
16450
16451         return ERR_PTR(ret);
16452 }
16453
16454 static struct intel_plane *
16455 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
16456                           enum pipe pipe)
16457 {
16458         struct intel_plane *cursor;
16459         int ret, zpos;
16460
16461         cursor = intel_plane_alloc();
16462         if (IS_ERR(cursor))
16463                 return cursor;
16464
16465         cursor->pipe = pipe;
16466         cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
16467         cursor->id = PLANE_CURSOR;
16468         cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
16469
16470         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
16471                 cursor->max_stride = i845_cursor_max_stride;
16472                 cursor->update_plane = i845_update_cursor;
16473                 cursor->disable_plane = i845_disable_cursor;
16474                 cursor->get_hw_state = i845_cursor_get_hw_state;
16475                 cursor->check_plane = i845_check_cursor;
16476         } else {
16477                 cursor->max_stride = i9xx_cursor_max_stride;
16478                 cursor->update_plane = i9xx_update_cursor;
16479                 cursor->disable_plane = i9xx_disable_cursor;
16480                 cursor->get_hw_state = i9xx_cursor_get_hw_state;
16481                 cursor->check_plane = i9xx_check_cursor;
16482         }
16483
16484         cursor->cursor.base = ~0;
16485         cursor->cursor.cntl = ~0;
16486
16487         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
16488                 cursor->cursor.size = ~0;
16489
16490         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
16491                                        0, &intel_cursor_plane_funcs,
16492                                        intel_cursor_formats,
16493                                        ARRAY_SIZE(intel_cursor_formats),
16494                                        cursor_format_modifiers,
16495                                        DRM_PLANE_TYPE_CURSOR,
16496                                        "cursor %c", pipe_name(pipe));
16497         if (ret)
16498                 goto fail;
16499
16500         if (INTEL_GEN(dev_priv) >= 4)
16501                 drm_plane_create_rotation_property(&cursor->base,
16502                                                    DRM_MODE_ROTATE_0,
16503                                                    DRM_MODE_ROTATE_0 |
16504                                                    DRM_MODE_ROTATE_180);
16505
16506         zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
16507         drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
16508
16509         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
16510
16511         return cursor;
16512
16513 fail:
16514         intel_plane_free(cursor);
16515
16516         return ERR_PTR(ret);
16517 }
16518
16519 #define INTEL_CRTC_FUNCS \
16520         .gamma_set = drm_atomic_helper_legacy_gamma_set, \
16521         .set_config = drm_atomic_helper_set_config, \
16522         .destroy = intel_crtc_destroy, \
16523         .page_flip = drm_atomic_helper_page_flip, \
16524         .atomic_duplicate_state = intel_crtc_duplicate_state, \
16525         .atomic_destroy_state = intel_crtc_destroy_state, \
16526         .set_crc_source = intel_crtc_set_crc_source, \
16527         .verify_crc_source = intel_crtc_verify_crc_source, \
16528         .get_crc_sources = intel_crtc_get_crc_sources
16529
16530 static const struct drm_crtc_funcs bdw_crtc_funcs = {
16531         INTEL_CRTC_FUNCS,
16532
16533         .get_vblank_counter = g4x_get_vblank_counter,
16534         .enable_vblank = bdw_enable_vblank,
16535         .disable_vblank = bdw_disable_vblank,
16536         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16537 };
16538
16539 static const struct drm_crtc_funcs ilk_crtc_funcs = {
16540         INTEL_CRTC_FUNCS,
16541
16542         .get_vblank_counter = g4x_get_vblank_counter,
16543         .enable_vblank = ilk_enable_vblank,
16544         .disable_vblank = ilk_disable_vblank,
16545         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16546 };
16547
16548 static const struct drm_crtc_funcs g4x_crtc_funcs = {
16549         INTEL_CRTC_FUNCS,
16550
16551         .get_vblank_counter = g4x_get_vblank_counter,
16552         .enable_vblank = i965_enable_vblank,
16553         .disable_vblank = i965_disable_vblank,
16554         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16555 };
16556
16557 static const struct drm_crtc_funcs i965_crtc_funcs = {
16558         INTEL_CRTC_FUNCS,
16559
16560         .get_vblank_counter = i915_get_vblank_counter,
16561         .enable_vblank = i965_enable_vblank,
16562         .disable_vblank = i965_disable_vblank,
16563         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16564 };
16565
16566 static const struct drm_crtc_funcs i915gm_crtc_funcs = {
16567         INTEL_CRTC_FUNCS,
16568
16569         .get_vblank_counter = i915_get_vblank_counter,
16570         .enable_vblank = i915gm_enable_vblank,
16571         .disable_vblank = i915gm_disable_vblank,
16572         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16573 };
16574
16575 static const struct drm_crtc_funcs i915_crtc_funcs = {
16576         INTEL_CRTC_FUNCS,
16577
16578         .get_vblank_counter = i915_get_vblank_counter,
16579         .enable_vblank = i8xx_enable_vblank,
16580         .disable_vblank = i8xx_disable_vblank,
16581         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16582 };
16583
16584 static const struct drm_crtc_funcs i8xx_crtc_funcs = {
16585         INTEL_CRTC_FUNCS,
16586
16587         /* no hw vblank counter */
16588         .enable_vblank = i8xx_enable_vblank,
16589         .disable_vblank = i8xx_disable_vblank,
16590         .get_vblank_timestamp = intel_crtc_get_vblank_timestamp,
16591 };
16592
16593 static struct intel_crtc *intel_crtc_alloc(void)
16594 {
16595         struct intel_crtc_state *crtc_state;
16596         struct intel_crtc *crtc;
16597
16598         crtc = kzalloc(sizeof(*crtc), GFP_KERNEL);
16599         if (!crtc)
16600                 return ERR_PTR(-ENOMEM);
16601
16602         crtc_state = intel_crtc_state_alloc(crtc);
16603         if (!crtc_state) {
16604                 kfree(crtc);
16605                 return ERR_PTR(-ENOMEM);
16606         }
16607
16608         crtc->base.state = &crtc_state->uapi;
16609         crtc->config = crtc_state;
16610
16611         return crtc;
16612 }
16613
16614 static void intel_crtc_free(struct intel_crtc *crtc)
16615 {
16616         intel_crtc_destroy_state(&crtc->base, crtc->base.state);
16617         kfree(crtc);
16618 }
16619
16620 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
16621 {
16622         struct intel_plane *plane;
16623
16624         for_each_intel_plane(&dev_priv->drm, plane) {
16625                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
16626                                                                   plane->pipe);
16627
16628                 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
16629         }
16630 }
16631
16632 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
16633 {
16634         struct intel_plane *primary, *cursor;
16635         const struct drm_crtc_funcs *funcs;
16636         struct intel_crtc *crtc;
16637         int sprite, ret;
16638
16639         crtc = intel_crtc_alloc();
16640         if (IS_ERR(crtc))
16641                 return PTR_ERR(crtc);
16642
16643         crtc->pipe = pipe;
16644         crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[pipe];
16645
16646         primary = intel_primary_plane_create(dev_priv, pipe);
16647         if (IS_ERR(primary)) {
16648                 ret = PTR_ERR(primary);
16649                 goto fail;
16650         }
16651         crtc->plane_ids_mask |= BIT(primary->id);
16652
16653         for_each_sprite(dev_priv, pipe, sprite) {
16654                 struct intel_plane *plane;
16655
16656                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
16657                 if (IS_ERR(plane)) {
16658                         ret = PTR_ERR(plane);
16659                         goto fail;
16660                 }
16661                 crtc->plane_ids_mask |= BIT(plane->id);
16662         }
16663
16664         cursor = intel_cursor_plane_create(dev_priv, pipe);
16665         if (IS_ERR(cursor)) {
16666                 ret = PTR_ERR(cursor);
16667                 goto fail;
16668         }
16669         crtc->plane_ids_mask |= BIT(cursor->id);
16670
16671         if (HAS_GMCH(dev_priv)) {
16672                 if (IS_CHERRYVIEW(dev_priv) ||
16673                     IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
16674                         funcs = &g4x_crtc_funcs;
16675                 else if (IS_GEN(dev_priv, 4))
16676                         funcs = &i965_crtc_funcs;
16677                 else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv))
16678                         funcs = &i915gm_crtc_funcs;
16679                 else if (IS_GEN(dev_priv, 3))
16680                         funcs = &i915_crtc_funcs;
16681                 else
16682                         funcs = &i8xx_crtc_funcs;
16683         } else {
16684                 if (INTEL_GEN(dev_priv) >= 8)
16685                         funcs = &bdw_crtc_funcs;
16686                 else
16687                         funcs = &ilk_crtc_funcs;
16688         }
16689
16690         ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base,
16691                                         &primary->base, &cursor->base,
16692                                         funcs, "pipe %c", pipe_name(pipe));
16693         if (ret)
16694                 goto fail;
16695
16696         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
16697                dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
16698         dev_priv->pipe_to_crtc_mapping[pipe] = crtc;
16699
16700         if (INTEL_GEN(dev_priv) < 9) {
16701                 enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
16702
16703                 BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
16704                        dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
16705                 dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc;
16706         }
16707
16708         intel_color_init(crtc);
16709
16710         intel_crtc_crc_init(crtc);
16711
16712         drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
16713
16714         return 0;
16715
16716 fail:
16717         intel_crtc_free(crtc);
16718
16719         return ret;
16720 }
16721
16722 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
16723                                       struct drm_file *file)
16724 {
16725         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
16726         struct drm_crtc *drmmode_crtc;
16727         struct intel_crtc *crtc;
16728
16729         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
16730         if (!drmmode_crtc)
16731                 return -ENOENT;
16732
16733         crtc = to_intel_crtc(drmmode_crtc);
16734         pipe_from_crtc_id->pipe = crtc->pipe;
16735
16736         return 0;
16737 }
16738
16739 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
16740 {
16741         struct drm_device *dev = encoder->base.dev;
16742         struct intel_encoder *source_encoder;
16743         u32 possible_clones = 0;
16744
16745         for_each_intel_encoder(dev, source_encoder) {
16746                 if (encoders_cloneable(encoder, source_encoder))
16747                         possible_clones |= drm_encoder_mask(&source_encoder->base);
16748         }
16749
16750         return possible_clones;
16751 }
16752
16753 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
16754 {
16755         struct drm_device *dev = encoder->base.dev;
16756         struct intel_crtc *crtc;
16757         u32 possible_crtcs = 0;
16758
16759         for_each_intel_crtc(dev, crtc) {
16760                 if (encoder->pipe_mask & BIT(crtc->pipe))
16761                         possible_crtcs |= drm_crtc_mask(&crtc->base);
16762         }
16763
16764         return possible_crtcs;
16765 }
16766
16767 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
16768 {
16769         if (!IS_MOBILE(dev_priv))
16770                 return false;
16771
16772         if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
16773                 return false;
16774
16775         if (IS_GEN(dev_priv, 5) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
16776                 return false;
16777
16778         return true;
16779 }
16780
16781 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
16782 {
16783         if (INTEL_GEN(dev_priv) >= 9)
16784                 return false;
16785
16786         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
16787                 return false;
16788
16789         if (HAS_PCH_LPT_H(dev_priv) &&
16790             intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
16791                 return false;
16792
16793         /* DDI E can't be used if DDI A requires 4 lanes */
16794         if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
16795                 return false;
16796
16797         if (!dev_priv->vbt.int_crt_support)
16798                 return false;
16799
16800         return true;
16801 }
16802
16803 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
16804 {
16805         int pps_num;
16806         int pps_idx;
16807
16808         if (HAS_DDI(dev_priv))
16809                 return;
16810         /*
16811          * This w/a is needed at least on CPT/PPT, but to be sure apply it
16812          * everywhere where registers can be write protected.
16813          */
16814         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16815                 pps_num = 2;
16816         else
16817                 pps_num = 1;
16818
16819         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
16820                 u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
16821
16822                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
16823                 intel_de_write(dev_priv, PP_CONTROL(pps_idx), val);
16824         }
16825 }
16826
16827 static void intel_pps_init(struct drm_i915_private *dev_priv)
16828 {
16829         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
16830                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
16831         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16832                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
16833         else
16834                 dev_priv->pps_mmio_base = PPS_BASE;
16835
16836         intel_pps_unlock_regs_wa(dev_priv);
16837 }
16838
16839 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
16840 {
16841         struct intel_encoder *encoder;
16842         bool dpd_is_edp = false;
16843
16844         intel_pps_init(dev_priv);
16845
16846         if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
16847                 return;
16848
16849         if (INTEL_GEN(dev_priv) >= 12) {
16850                 intel_ddi_init(dev_priv, PORT_A);
16851                 intel_ddi_init(dev_priv, PORT_B);
16852                 intel_ddi_init(dev_priv, PORT_D);
16853                 intel_ddi_init(dev_priv, PORT_E);
16854                 intel_ddi_init(dev_priv, PORT_F);
16855                 intel_ddi_init(dev_priv, PORT_G);
16856                 intel_ddi_init(dev_priv, PORT_H);
16857                 intel_ddi_init(dev_priv, PORT_I);
16858                 icl_dsi_init(dev_priv);
16859         } else if (IS_ELKHARTLAKE(dev_priv)) {
16860                 intel_ddi_init(dev_priv, PORT_A);
16861                 intel_ddi_init(dev_priv, PORT_B);
16862                 intel_ddi_init(dev_priv, PORT_C);
16863                 intel_ddi_init(dev_priv, PORT_D);
16864                 icl_dsi_init(dev_priv);
16865         } else if (IS_GEN(dev_priv, 11)) {
16866                 intel_ddi_init(dev_priv, PORT_A);
16867                 intel_ddi_init(dev_priv, PORT_B);
16868                 intel_ddi_init(dev_priv, PORT_C);
16869                 intel_ddi_init(dev_priv, PORT_D);
16870                 intel_ddi_init(dev_priv, PORT_E);
16871                 /*
16872                  * On some ICL SKUs port F is not present. No strap bits for
16873                  * this, so rely on VBT.
16874                  * Work around broken VBTs on SKUs known to have no port F.
16875                  */
16876                 if (IS_ICL_WITH_PORT_F(dev_priv) &&
16877                     intel_bios_is_port_present(dev_priv, PORT_F))
16878                         intel_ddi_init(dev_priv, PORT_F);
16879
16880                 icl_dsi_init(dev_priv);
16881         } else if (IS_GEN9_LP(dev_priv)) {
16882                 /*
16883                  * FIXME: Broxton doesn't support port detection via the
16884                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
16885                  * detect the ports.
16886                  */
16887                 intel_ddi_init(dev_priv, PORT_A);
16888                 intel_ddi_init(dev_priv, PORT_B);
16889                 intel_ddi_init(dev_priv, PORT_C);
16890
16891                 vlv_dsi_init(dev_priv);
16892         } else if (HAS_DDI(dev_priv)) {
16893                 int found;
16894
16895                 if (intel_ddi_crt_present(dev_priv))
16896                         intel_crt_init(dev_priv);
16897
16898                 /*
16899                  * Haswell uses DDI functions to detect digital outputs.
16900                  * On SKL pre-D0 the strap isn't connected, so we assume
16901                  * it's there.
16902                  */
16903                 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
16904                 /* WaIgnoreDDIAStrap: skl */
16905                 if (found || IS_GEN9_BC(dev_priv))
16906                         intel_ddi_init(dev_priv, PORT_A);
16907
16908                 /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
16909                  * register */
16910                 found = intel_de_read(dev_priv, SFUSE_STRAP);
16911
16912                 if (found & SFUSE_STRAP_DDIB_DETECTED)
16913                         intel_ddi_init(dev_priv, PORT_B);
16914                 if (found & SFUSE_STRAP_DDIC_DETECTED)
16915                         intel_ddi_init(dev_priv, PORT_C);
16916                 if (found & SFUSE_STRAP_DDID_DETECTED)
16917                         intel_ddi_init(dev_priv, PORT_D);
16918                 if (found & SFUSE_STRAP_DDIF_DETECTED)
16919                         intel_ddi_init(dev_priv, PORT_F);
16920                 /*
16921                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
16922                  */
16923                 if (IS_GEN9_BC(dev_priv) &&
16924                     intel_bios_is_port_present(dev_priv, PORT_E))
16925                         intel_ddi_init(dev_priv, PORT_E);
16926
16927         } else if (HAS_PCH_SPLIT(dev_priv)) {
16928                 int found;
16929
16930                 /*
16931                  * intel_edp_init_connector() depends on this completing first,
16932                  * to prevent the registration of both eDP and LVDS and the
16933                  * incorrect sharing of the PPS.
16934                  */
16935                 intel_lvds_init(dev_priv);
16936                 intel_crt_init(dev_priv);
16937
16938                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
16939
16940                 if (ilk_has_edp_a(dev_priv))
16941                         intel_dp_init(dev_priv, DP_A, PORT_A);
16942
16943                 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
16944                         /* PCH SDVOB multiplex with HDMIB */
16945                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
16946                         if (!found)
16947                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
16948                         if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
16949                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
16950                 }
16951
16952                 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
16953                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
16954
16955                 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
16956                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
16957
16958                 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
16959                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
16960
16961                 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
16962                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
16963         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16964                 bool has_edp, has_port;
16965
16966                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
16967                         intel_crt_init(dev_priv);
16968
16969                 /*
16970                  * The DP_DETECTED bit is the latched state of the DDC
16971                  * SDA pin at boot. However since eDP doesn't require DDC
16972                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
16973                  * eDP ports may have been muxed to an alternate function.
16974                  * Thus we can't rely on the DP_DETECTED bit alone to detect
16975                  * eDP ports. Consult the VBT as well as DP_DETECTED to
16976                  * detect eDP ports.
16977                  *
16978                  * Sadly the straps seem to be missing sometimes even for HDMI
16979                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
16980                  * and VBT for the presence of the port. Additionally we can't
16981                  * trust the port type the VBT declares as we've seen at least
16982                  * HDMI ports that the VBT claim are DP or eDP.
16983                  */
16984                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
16985                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
16986                 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
16987                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
16988                 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
16989                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
16990
16991                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
16992                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
16993                 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
16994                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
16995                 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
16996                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
16997
16998                 if (IS_CHERRYVIEW(dev_priv)) {
16999                         /*
17000                          * eDP not supported on port D,
17001                          * so no need to worry about it
17002                          */
17003                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
17004                         if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
17005                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
17006                         if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
17007                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
17008                 }
17009
17010                 vlv_dsi_init(dev_priv);
17011         } else if (IS_PINEVIEW(dev_priv)) {
17012                 intel_lvds_init(dev_priv);
17013                 intel_crt_init(dev_priv);
17014         } else if (IS_GEN_RANGE(dev_priv, 3, 4)) {
17015                 bool found = false;
17016
17017                 if (IS_MOBILE(dev_priv))
17018                         intel_lvds_init(dev_priv);
17019
17020                 intel_crt_init(dev_priv);
17021
17022                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
17023                         drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
17024                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
17025                         if (!found && IS_G4X(dev_priv)) {
17026                                 drm_dbg_kms(&dev_priv->drm,
17027                                             "probing HDMI on SDVOB\n");
17028                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
17029                         }
17030
17031                         if (!found && IS_G4X(dev_priv))
17032                                 intel_dp_init(dev_priv, DP_B, PORT_B);
17033                 }
17034
17035                 /* Before G4X SDVOC doesn't have its own detect register */
17036
17037                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
17038                         drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
17039                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
17040                 }
17041
17042                 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
17043
17044                         if (IS_G4X(dev_priv)) {
17045                                 drm_dbg_kms(&dev_priv->drm,
17046                                             "probing HDMI on SDVOC\n");
17047                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
17048                         }
17049                         if (IS_G4X(dev_priv))
17050                                 intel_dp_init(dev_priv, DP_C, PORT_C);
17051                 }
17052
17053                 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
17054                         intel_dp_init(dev_priv, DP_D, PORT_D);
17055
17056                 if (SUPPORTS_TV(dev_priv))
17057                         intel_tv_init(dev_priv);
17058         } else if (IS_GEN(dev_priv, 2)) {
17059                 if (IS_I85X(dev_priv))
17060                         intel_lvds_init(dev_priv);
17061
17062                 intel_crt_init(dev_priv);
17063                 intel_dvo_init(dev_priv);
17064         }
17065
17066         intel_psr_init(dev_priv);
17067
17068         for_each_intel_encoder(&dev_priv->drm, encoder) {
17069                 encoder->base.possible_crtcs =
17070                         intel_encoder_possible_crtcs(encoder);
17071                 encoder->base.possible_clones =
17072                         intel_encoder_possible_clones(encoder);
17073         }
17074
17075         intel_init_pch_refclk(dev_priv);
17076
17077         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
17078 }
17079
17080 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
17081 {
17082         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
17083
17084         drm_framebuffer_cleanup(fb);
17085         intel_frontbuffer_put(intel_fb->frontbuffer);
17086
17087         kfree(intel_fb);
17088 }
17089
17090 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
17091                                                 struct drm_file *file,
17092                                                 unsigned int *handle)
17093 {
17094         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
17095         struct drm_i915_private *i915 = to_i915(obj->base.dev);
17096
17097         if (obj->userptr.mm) {
17098                 drm_dbg(&i915->drm,
17099                         "attempting to use a userptr for a framebuffer, denied\n");
17100                 return -EINVAL;
17101         }
17102
17103         return drm_gem_handle_create(file, &obj->base, handle);
17104 }
17105
17106 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
17107                                         struct drm_file *file,
17108                                         unsigned flags, unsigned color,
17109                                         struct drm_clip_rect *clips,
17110                                         unsigned num_clips)
17111 {
17112         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
17113
17114         i915_gem_object_flush_if_display(obj);
17115         intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
17116
17117         return 0;
17118 }
17119
17120 static const struct drm_framebuffer_funcs intel_fb_funcs = {
17121         .destroy = intel_user_framebuffer_destroy,
17122         .create_handle = intel_user_framebuffer_create_handle,
17123         .dirty = intel_user_framebuffer_dirty,
17124 };
17125
17126 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
17127                                   struct drm_i915_gem_object *obj,
17128                                   struct drm_mode_fb_cmd2 *mode_cmd)
17129 {
17130         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
17131         struct drm_framebuffer *fb = &intel_fb->base;
17132         u32 max_stride;
17133         unsigned int tiling, stride;
17134         int ret = -EINVAL;
17135         int i;
17136
17137         intel_fb->frontbuffer = intel_frontbuffer_get(obj);
17138         if (!intel_fb->frontbuffer)
17139                 return -ENOMEM;
17140
17141         i915_gem_object_lock(obj);
17142         tiling = i915_gem_object_get_tiling(obj);
17143         stride = i915_gem_object_get_stride(obj);
17144         i915_gem_object_unlock(obj);
17145
17146         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
17147                 /*
17148                  * If there's a fence, enforce that
17149                  * the fb modifier and tiling mode match.
17150                  */
17151                 if (tiling != I915_TILING_NONE &&
17152                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
17153                         drm_dbg_kms(&dev_priv->drm,
17154                                     "tiling_mode doesn't match fb modifier\n");
17155                         goto err;
17156                 }
17157         } else {
17158                 if (tiling == I915_TILING_X) {
17159                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
17160                 } else if (tiling == I915_TILING_Y) {
17161                         drm_dbg_kms(&dev_priv->drm,
17162                                     "No Y tiling for legacy addfb\n");
17163                         goto err;
17164                 }
17165         }
17166
17167         if (!drm_any_plane_has_format(&dev_priv->drm,
17168                                       mode_cmd->pixel_format,
17169                                       mode_cmd->modifier[0])) {
17170                 struct drm_format_name_buf format_name;
17171
17172                 drm_dbg_kms(&dev_priv->drm,
17173                             "unsupported pixel format %s / modifier 0x%llx\n",
17174                             drm_get_format_name(mode_cmd->pixel_format,
17175                                                 &format_name),
17176                             mode_cmd->modifier[0]);
17177                 goto err;
17178         }
17179
17180         /*
17181          * gen2/3 display engine uses the fence if present,
17182          * so the tiling mode must match the fb modifier exactly.
17183          */
17184         if (INTEL_GEN(dev_priv) < 4 &&
17185             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
17186                 drm_dbg_kms(&dev_priv->drm,
17187                             "tiling_mode must match fb modifier exactly on gen2/3\n");
17188                 goto err;
17189         }
17190
17191         max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
17192                                          mode_cmd->modifier[0]);
17193         if (mode_cmd->pitches[0] > max_stride) {
17194                 drm_dbg_kms(&dev_priv->drm,
17195                             "%s pitch (%u) must be at most %d\n",
17196                             mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
17197                             "tiled" : "linear",
17198                             mode_cmd->pitches[0], max_stride);
17199                 goto err;
17200         }
17201
17202         /*
17203          * If there's a fence, enforce that
17204          * the fb pitch and fence stride match.
17205          */
17206         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
17207                 drm_dbg_kms(&dev_priv->drm,
17208                             "pitch (%d) must match tiling stride (%d)\n",
17209                             mode_cmd->pitches[0], stride);
17210                 goto err;
17211         }
17212
17213         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
17214         if (mode_cmd->offsets[0] != 0) {
17215                 drm_dbg_kms(&dev_priv->drm,
17216                             "plane 0 offset (0x%08x) must be 0\n",
17217                             mode_cmd->offsets[0]);
17218                 goto err;
17219         }
17220
17221         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
17222
17223         for (i = 0; i < fb->format->num_planes; i++) {
17224                 u32 stride_alignment;
17225
17226                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
17227                         drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
17228                                     i);
17229                         goto err;
17230                 }
17231
17232                 stride_alignment = intel_fb_stride_alignment(fb, i);
17233                 if (fb->pitches[i] & (stride_alignment - 1)) {
17234                         drm_dbg_kms(&dev_priv->drm,
17235                                     "plane %d pitch (%d) must be at least %u byte aligned\n",
17236                                     i, fb->pitches[i], stride_alignment);
17237                         goto err;
17238                 }
17239
17240                 if (is_gen12_ccs_plane(fb, i)) {
17241                         int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
17242
17243                         if (fb->pitches[i] != ccs_aux_stride) {
17244                                 drm_dbg_kms(&dev_priv->drm,
17245                                             "ccs aux plane %d pitch (%d) must be %d\n",
17246                                             i,
17247                                             fb->pitches[i], ccs_aux_stride);
17248                                 goto err;
17249                         }
17250                 }
17251
17252                 fb->obj[i] = &obj->base;
17253         }
17254
17255         ret = intel_fill_fb_info(dev_priv, fb);
17256         if (ret)
17257                 goto err;
17258
17259         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
17260         if (ret) {
17261                 drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
17262                 goto err;
17263         }
17264
17265         return 0;
17266
17267 err:
17268         intel_frontbuffer_put(intel_fb->frontbuffer);
17269         return ret;
17270 }
17271
17272 static struct drm_framebuffer *
17273 intel_user_framebuffer_create(struct drm_device *dev,
17274                               struct drm_file *filp,
17275                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
17276 {
17277         struct drm_framebuffer *fb;
17278         struct drm_i915_gem_object *obj;
17279         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
17280
17281         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
17282         if (!obj)
17283                 return ERR_PTR(-ENOENT);
17284
17285         fb = intel_framebuffer_create(obj, &mode_cmd);
17286         i915_gem_object_put(obj);
17287
17288         return fb;
17289 }
17290
17291 static enum drm_mode_status
17292 intel_mode_valid(struct drm_device *dev,
17293                  const struct drm_display_mode *mode)
17294 {
17295         struct drm_i915_private *dev_priv = to_i915(dev);
17296         int hdisplay_max, htotal_max;
17297         int vdisplay_max, vtotal_max;
17298
17299         /*
17300          * Can't reject DBLSCAN here because Xorg ddxen can add piles
17301          * of DBLSCAN modes to the output's mode list when they detect
17302          * the scaling mode property on the connector. And they don't
17303          * ask the kernel to validate those modes in any way until
17304          * modeset time at which point the client gets a protocol error.
17305          * So in order to not upset those clients we silently ignore the
17306          * DBLSCAN flag on such connectors. For other connectors we will
17307          * reject modes with the DBLSCAN flag in encoder->compute_config().
17308          * And we always reject DBLSCAN modes in connector->mode_valid()
17309          * as we never want such modes on the connector's mode list.
17310          */
17311
17312         if (mode->vscan > 1)
17313                 return MODE_NO_VSCAN;
17314
17315         if (mode->flags & DRM_MODE_FLAG_HSKEW)
17316                 return MODE_H_ILLEGAL;
17317
17318         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
17319                            DRM_MODE_FLAG_NCSYNC |
17320                            DRM_MODE_FLAG_PCSYNC))
17321                 return MODE_HSYNC;
17322
17323         if (mode->flags & (DRM_MODE_FLAG_BCAST |
17324                            DRM_MODE_FLAG_PIXMUX |
17325                            DRM_MODE_FLAG_CLKDIV2))
17326                 return MODE_BAD;
17327
17328         /* Transcoder timing limits */
17329         if (INTEL_GEN(dev_priv) >= 11) {
17330                 hdisplay_max = 16384;
17331                 vdisplay_max = 8192;
17332                 htotal_max = 16384;
17333                 vtotal_max = 8192;
17334         } else if (INTEL_GEN(dev_priv) >= 9 ||
17335                    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
17336                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
17337                 vdisplay_max = 4096;
17338                 htotal_max = 8192;
17339                 vtotal_max = 8192;
17340         } else if (INTEL_GEN(dev_priv) >= 3) {
17341                 hdisplay_max = 4096;
17342                 vdisplay_max = 4096;
17343                 htotal_max = 8192;
17344                 vtotal_max = 8192;
17345         } else {
17346                 hdisplay_max = 2048;
17347                 vdisplay_max = 2048;
17348                 htotal_max = 4096;
17349                 vtotal_max = 4096;
17350         }
17351
17352         if (mode->hdisplay > hdisplay_max ||
17353             mode->hsync_start > htotal_max ||
17354             mode->hsync_end > htotal_max ||
17355             mode->htotal > htotal_max)
17356                 return MODE_H_ILLEGAL;
17357
17358         if (mode->vdisplay > vdisplay_max ||
17359             mode->vsync_start > vtotal_max ||
17360             mode->vsync_end > vtotal_max ||
17361             mode->vtotal > vtotal_max)
17362                 return MODE_V_ILLEGAL;
17363
17364         if (INTEL_GEN(dev_priv) >= 5) {
17365                 if (mode->hdisplay < 64 ||
17366                     mode->htotal - mode->hdisplay < 32)
17367                         return MODE_H_ILLEGAL;
17368
17369                 if (mode->vtotal - mode->vdisplay < 5)
17370                         return MODE_V_ILLEGAL;
17371         } else {
17372                 if (mode->htotal - mode->hdisplay < 32)
17373                         return MODE_H_ILLEGAL;
17374
17375                 if (mode->vtotal - mode->vdisplay < 3)
17376                         return MODE_V_ILLEGAL;
17377         }
17378
17379         return MODE_OK;
17380 }
17381
17382 enum drm_mode_status
17383 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
17384                                 const struct drm_display_mode *mode)
17385 {
17386         int plane_width_max, plane_height_max;
17387
17388         /*
17389          * intel_mode_valid() should be
17390          * sufficient on older platforms.
17391          */
17392         if (INTEL_GEN(dev_priv) < 9)
17393                 return MODE_OK;
17394
17395         /*
17396          * Most people will probably want a fullscreen
17397          * plane so let's not advertize modes that are
17398          * too big for that.
17399          */
17400         if (INTEL_GEN(dev_priv) >= 11) {
17401                 plane_width_max = 5120;
17402                 plane_height_max = 4320;
17403         } else {
17404                 plane_width_max = 5120;
17405                 plane_height_max = 4096;
17406         }
17407
17408         if (mode->hdisplay > plane_width_max)
17409                 return MODE_H_ILLEGAL;
17410
17411         if (mode->vdisplay > plane_height_max)
17412                 return MODE_V_ILLEGAL;
17413
17414         return MODE_OK;
17415 }
17416
17417 static const struct drm_mode_config_funcs intel_mode_funcs = {
17418         .fb_create = intel_user_framebuffer_create,
17419         .get_format_info = intel_get_format_info,
17420         .output_poll_changed = intel_fbdev_output_poll_changed,
17421         .mode_valid = intel_mode_valid,
17422         .atomic_check = intel_atomic_check,
17423         .atomic_commit = intel_atomic_commit,
17424         .atomic_state_alloc = intel_atomic_state_alloc,
17425         .atomic_state_clear = intel_atomic_state_clear,
17426         .atomic_state_free = intel_atomic_state_free,
17427 };
17428
17429 /**
17430  * intel_init_display_hooks - initialize the display modesetting hooks
17431  * @dev_priv: device private
17432  */
17433 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
17434 {
17435         intel_init_cdclk_hooks(dev_priv);
17436
17437         if (INTEL_GEN(dev_priv) >= 9) {
17438                 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
17439                 dev_priv->display.get_initial_plane_config =
17440                         skl_get_initial_plane_config;
17441                 dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
17442                 dev_priv->display.crtc_enable = hsw_crtc_enable;
17443                 dev_priv->display.crtc_disable = hsw_crtc_disable;
17444         } else if (HAS_DDI(dev_priv)) {
17445                 dev_priv->display.get_pipe_config = hsw_get_pipe_config;
17446                 dev_priv->display.get_initial_plane_config =
17447                         i9xx_get_initial_plane_config;
17448                 dev_priv->display.crtc_compute_clock =
17449                         hsw_crtc_compute_clock;
17450                 dev_priv->display.crtc_enable = hsw_crtc_enable;
17451                 dev_priv->display.crtc_disable = hsw_crtc_disable;
17452         } else if (HAS_PCH_SPLIT(dev_priv)) {
17453                 dev_priv->display.get_pipe_config = ilk_get_pipe_config;
17454                 dev_priv->display.get_initial_plane_config =
17455                         i9xx_get_initial_plane_config;
17456                 dev_priv->display.crtc_compute_clock =
17457                         ilk_crtc_compute_clock;
17458                 dev_priv->display.crtc_enable = ilk_crtc_enable;
17459                 dev_priv->display.crtc_disable = ilk_crtc_disable;
17460         } else if (IS_CHERRYVIEW(dev_priv)) {
17461                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17462                 dev_priv->display.get_initial_plane_config =
17463                         i9xx_get_initial_plane_config;
17464                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
17465                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
17466                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17467         } else if (IS_VALLEYVIEW(dev_priv)) {
17468                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17469                 dev_priv->display.get_initial_plane_config =
17470                         i9xx_get_initial_plane_config;
17471                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
17472                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
17473                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17474         } else if (IS_G4X(dev_priv)) {
17475                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17476                 dev_priv->display.get_initial_plane_config =
17477                         i9xx_get_initial_plane_config;
17478                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
17479                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17480                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17481         } else if (IS_PINEVIEW(dev_priv)) {
17482                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17483                 dev_priv->display.get_initial_plane_config =
17484                         i9xx_get_initial_plane_config;
17485                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
17486                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17487                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17488         } else if (!IS_GEN(dev_priv, 2)) {
17489                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17490                 dev_priv->display.get_initial_plane_config =
17491                         i9xx_get_initial_plane_config;
17492                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
17493                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17494                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17495         } else {
17496                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
17497                 dev_priv->display.get_initial_plane_config =
17498                         i9xx_get_initial_plane_config;
17499                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
17500                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
17501                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
17502         }
17503
17504         if (IS_GEN(dev_priv, 5)) {
17505                 dev_priv->display.fdi_link_train = ilk_fdi_link_train;
17506         } else if (IS_GEN(dev_priv, 6)) {
17507                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
17508         } else if (IS_IVYBRIDGE(dev_priv)) {
17509                 /* FIXME: detect B0+ stepping and use auto training */
17510                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
17511         }
17512
17513         if (INTEL_GEN(dev_priv) >= 9)
17514                 dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
17515         else
17516                 dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
17517
17518 }
17519
17520 void intel_modeset_init_hw(struct drm_i915_private *i915)
17521 {
17522         struct intel_cdclk_state *cdclk_state =
17523                 to_intel_cdclk_state(i915->cdclk.obj.state);
17524
17525         intel_update_cdclk(i915);
17526         intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
17527         cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
17528 }
17529
17530 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
17531 {
17532         struct drm_plane *plane;
17533         struct drm_crtc *crtc;
17534
17535         drm_for_each_crtc(crtc, state->dev) {
17536                 struct drm_crtc_state *crtc_state;
17537
17538                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
17539                 if (IS_ERR(crtc_state))
17540                         return PTR_ERR(crtc_state);
17541         }
17542
17543         drm_for_each_plane(plane, state->dev) {
17544                 struct drm_plane_state *plane_state;
17545
17546                 plane_state = drm_atomic_get_plane_state(state, plane);
17547                 if (IS_ERR(plane_state))
17548                         return PTR_ERR(plane_state);
17549         }
17550
17551         return 0;
17552 }
17553
17554 /*
17555  * Calculate what we think the watermarks should be for the state we've read
17556  * out of the hardware and then immediately program those watermarks so that
17557  * we ensure the hardware settings match our internal state.
17558  *
17559  * We can calculate what we think WM's should be by creating a duplicate of the
17560  * current state (which was constructed during hardware readout) and running it
17561  * through the atomic check code to calculate new watermark values in the
17562  * state object.
17563  */
17564 static void sanitize_watermarks(struct drm_i915_private *dev_priv)
17565 {
17566         struct drm_atomic_state *state;
17567         struct intel_atomic_state *intel_state;
17568         struct intel_crtc *crtc;
17569         struct intel_crtc_state *crtc_state;
17570         struct drm_modeset_acquire_ctx ctx;
17571         int ret;
17572         int i;
17573
17574         /* Only supported on platforms that use atomic watermark design */
17575         if (!dev_priv->display.optimize_watermarks)
17576                 return;
17577
17578         state = drm_atomic_state_alloc(&dev_priv->drm);
17579         if (drm_WARN_ON(&dev_priv->drm, !state))
17580                 return;
17581
17582         intel_state = to_intel_atomic_state(state);
17583
17584         drm_modeset_acquire_init(&ctx, 0);
17585
17586 retry:
17587         state->acquire_ctx = &ctx;
17588
17589         /*
17590          * Hardware readout is the only time we don't want to calculate
17591          * intermediate watermarks (since we don't trust the current
17592          * watermarks).
17593          */
17594         if (!HAS_GMCH(dev_priv))
17595                 intel_state->skip_intermediate_wm = true;
17596
17597         ret = sanitize_watermarks_add_affected(state);
17598         if (ret)
17599                 goto fail;
17600
17601         ret = intel_atomic_check(&dev_priv->drm, state);
17602         if (ret)
17603                 goto fail;
17604
17605         /* Write calculated watermark values back */
17606         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
17607                 crtc_state->wm.need_postvbl_update = true;
17608                 dev_priv->display.optimize_watermarks(intel_state, crtc);
17609
17610                 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
17611         }
17612
17613 fail:
17614         if (ret == -EDEADLK) {
17615                 drm_atomic_state_clear(state);
17616                 drm_modeset_backoff(&ctx);
17617                 goto retry;
17618         }
17619
17620         /*
17621          * If we fail here, it means that the hardware appears to be
17622          * programmed in a way that shouldn't be possible, given our
17623          * understanding of watermark requirements.  This might mean a
17624          * mistake in the hardware readout code or a mistake in the
17625          * watermark calculations for a given platform.  Raise a WARN
17626          * so that this is noticeable.
17627          *
17628          * If this actually happens, we'll have to just leave the
17629          * BIOS-programmed watermarks untouched and hope for the best.
17630          */
17631         drm_WARN(&dev_priv->drm, ret,
17632                  "Could not determine valid watermarks for inherited state\n");
17633
17634         drm_atomic_state_put(state);
17635
17636         drm_modeset_drop_locks(&ctx);
17637         drm_modeset_acquire_fini(&ctx);
17638 }
17639
17640 static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
17641 {
17642         if (IS_GEN(dev_priv, 5)) {
17643                 u32 fdi_pll_clk =
17644                         intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
17645
17646                 dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
17647         } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) {
17648                 dev_priv->fdi_pll_freq = 270000;
17649         } else {
17650                 return;
17651         }
17652
17653         drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
17654 }
17655
17656 static int intel_initial_commit(struct drm_device *dev)
17657 {
17658         struct drm_atomic_state *state = NULL;
17659         struct drm_modeset_acquire_ctx ctx;
17660         struct intel_crtc *crtc;
17661         int ret = 0;
17662
17663         state = drm_atomic_state_alloc(dev);
17664         if (!state)
17665                 return -ENOMEM;
17666
17667         drm_modeset_acquire_init(&ctx, 0);
17668
17669 retry:
17670         state->acquire_ctx = &ctx;
17671
17672         for_each_intel_crtc(dev, crtc) {
17673                 struct intel_crtc_state *crtc_state =
17674                         intel_atomic_get_crtc_state(state, crtc);
17675
17676                 if (IS_ERR(crtc_state)) {
17677                         ret = PTR_ERR(crtc_state);
17678                         goto out;
17679                 }
17680
17681                 if (crtc_state->hw.active) {
17682                         ret = drm_atomic_add_affected_planes(state, &crtc->base);
17683                         if (ret)
17684                                 goto out;
17685
17686                         /*
17687                          * FIXME hack to force a LUT update to avoid the
17688                          * plane update forcing the pipe gamma on without
17689                          * having a proper LUT loaded. Remove once we
17690                          * have readout for pipe gamma enable.
17691                          */
17692                         crtc_state->uapi.color_mgmt_changed = true;
17693
17694                         /*
17695                          * FIXME hack to force full modeset when DSC is being
17696                          * used.
17697                          *
17698                          * As long as we do not have full state readout and
17699                          * config comparison of crtc_state->dsc, we have no way
17700                          * to ensure reliable fastset. Remove once we have
17701                          * readout for DSC.
17702                          */
17703                         if (crtc_state->dsc.compression_enable) {
17704                                 ret = drm_atomic_add_affected_connectors(state,
17705                                                                          &crtc->base);
17706                                 if (ret)
17707                                         goto out;
17708                                 crtc_state->uapi.mode_changed = true;
17709                                 drm_dbg_kms(dev, "Force full modeset for DSC\n");
17710                         }
17711                 }
17712         }
17713
17714         ret = drm_atomic_commit(state);
17715
17716 out:
17717         if (ret == -EDEADLK) {
17718                 drm_atomic_state_clear(state);
17719                 drm_modeset_backoff(&ctx);
17720                 goto retry;
17721         }
17722
17723         drm_atomic_state_put(state);
17724
17725         drm_modeset_drop_locks(&ctx);
17726         drm_modeset_acquire_fini(&ctx);
17727
17728         return ret;
17729 }
17730
17731 static void intel_mode_config_init(struct drm_i915_private *i915)
17732 {
17733         struct drm_mode_config *mode_config = &i915->drm.mode_config;
17734
17735         drm_mode_config_init(&i915->drm);
17736         INIT_LIST_HEAD(&i915->global_obj_list);
17737
17738         mode_config->min_width = 0;
17739         mode_config->min_height = 0;
17740
17741         mode_config->preferred_depth = 24;
17742         mode_config->prefer_shadow = 1;
17743
17744         mode_config->allow_fb_modifiers = true;
17745
17746         mode_config->funcs = &intel_mode_funcs;
17747
17748         /*
17749          * Maximum framebuffer dimensions, chosen to match
17750          * the maximum render engine surface size on gen4+.
17751          */
17752         if (INTEL_GEN(i915) >= 7) {
17753                 mode_config->max_width = 16384;
17754                 mode_config->max_height = 16384;
17755         } else if (INTEL_GEN(i915) >= 4) {
17756                 mode_config->max_width = 8192;
17757                 mode_config->max_height = 8192;
17758         } else if (IS_GEN(i915, 3)) {
17759                 mode_config->max_width = 4096;
17760                 mode_config->max_height = 4096;
17761         } else {
17762                 mode_config->max_width = 2048;
17763                 mode_config->max_height = 2048;
17764         }
17765
17766         if (IS_I845G(i915) || IS_I865G(i915)) {
17767                 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
17768                 mode_config->cursor_height = 1023;
17769         } else if (IS_GEN(i915, 2)) {
17770                 mode_config->cursor_width = 64;
17771                 mode_config->cursor_height = 64;
17772         } else {
17773                 mode_config->cursor_width = 256;
17774                 mode_config->cursor_height = 256;
17775         }
17776 }
17777
17778 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
17779 {
17780         intel_atomic_global_obj_cleanup(i915);
17781         drm_mode_config_cleanup(&i915->drm);
17782 }
17783
17784 static void plane_config_fini(struct intel_initial_plane_config *plane_config)
17785 {
17786         if (plane_config->fb) {
17787                 struct drm_framebuffer *fb = &plane_config->fb->base;
17788
17789                 /* We may only have the stub and not a full framebuffer */
17790                 if (drm_framebuffer_read_refcount(fb))
17791                         drm_framebuffer_put(fb);
17792                 else
17793                         kfree(fb);
17794         }
17795
17796         if (plane_config->vma)
17797                 i915_vma_put(plane_config->vma);
17798 }
17799
17800 /* part #1: call before irq install */
17801 int intel_modeset_init_noirq(struct drm_i915_private *i915)
17802 {
17803         int ret;
17804
17805         i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
17806         i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
17807                                         WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
17808
17809         intel_mode_config_init(i915);
17810
17811         ret = intel_cdclk_init(i915);
17812         if (ret)
17813                 return ret;
17814
17815         ret = intel_bw_init(i915);
17816         if (ret)
17817                 return ret;
17818
17819         init_llist_head(&i915->atomic_helper.free_list);
17820         INIT_WORK(&i915->atomic_helper.free_work,
17821                   intel_atomic_helper_free_state_worker);
17822
17823         intel_init_quirks(i915);
17824
17825         intel_fbc_init(i915);
17826
17827         return 0;
17828 }
17829
17830 /* part #2: call after irq install */
17831 int intel_modeset_init(struct drm_i915_private *i915)
17832 {
17833         struct drm_device *dev = &i915->drm;
17834         enum pipe pipe;
17835         struct intel_crtc *crtc;
17836         int ret;
17837
17838         intel_init_pm(i915);
17839
17840         intel_panel_sanitize_ssc(i915);
17841
17842         intel_gmbus_setup(i915);
17843
17844         drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
17845                     INTEL_NUM_PIPES(i915),
17846                     INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
17847
17848         if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) {
17849                 for_each_pipe(i915, pipe) {
17850                         ret = intel_crtc_init(i915, pipe);
17851                         if (ret) {
17852                                 intel_mode_config_cleanup(i915);
17853                                 return ret;
17854                         }
17855                 }
17856         }
17857
17858         intel_plane_possible_crtcs_init(i915);
17859         intel_shared_dpll_init(dev);
17860         intel_update_fdi_pll_freq(i915);
17861
17862         intel_update_czclk(i915);
17863         intel_modeset_init_hw(i915);
17864
17865         intel_hdcp_component_init(i915);
17866
17867         if (i915->max_cdclk_freq == 0)
17868                 intel_update_max_cdclk(i915);
17869
17870         /* Just disable it once at startup */
17871         intel_vga_disable(i915);
17872         intel_setup_outputs(i915);
17873
17874         drm_modeset_lock_all(dev);
17875         intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
17876         drm_modeset_unlock_all(dev);
17877
17878         for_each_intel_crtc(dev, crtc) {
17879                 struct intel_initial_plane_config plane_config = {};
17880
17881                 if (!crtc->active)
17882                         continue;
17883
17884                 /*
17885                  * Note that reserving the BIOS fb up front prevents us
17886                  * from stuffing other stolen allocations like the ring
17887                  * on top.  This prevents some ugliness at boot time, and
17888                  * can even allow for smooth boot transitions if the BIOS
17889                  * fb is large enough for the active pipe configuration.
17890                  */
17891                 i915->display.get_initial_plane_config(crtc, &plane_config);
17892
17893                 /*
17894                  * If the fb is shared between multiple heads, we'll
17895                  * just get the first one.
17896                  */
17897                 intel_find_initial_plane_obj(crtc, &plane_config);
17898
17899                 plane_config_fini(&plane_config);
17900         }
17901
17902         /*
17903          * Make sure hardware watermarks really match the state we read out.
17904          * Note that we need to do this after reconstructing the BIOS fb's
17905          * since the watermark calculation done here will use pstate->fb.
17906          */
17907         if (!HAS_GMCH(i915))
17908                 sanitize_watermarks(i915);
17909
17910         /*
17911          * Force all active planes to recompute their states. So that on
17912          * mode_setcrtc after probe, all the intel_plane_state variables
17913          * are already calculated and there is no assert_plane warnings
17914          * during bootup.
17915          */
17916         ret = intel_initial_commit(dev);
17917         if (ret)
17918                 drm_dbg_kms(&i915->drm, "Initial commit in probe failed.\n");
17919
17920         return 0;
17921 }
17922
17923 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
17924 {
17925         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17926         /* 640x480@60Hz, ~25175 kHz */
17927         struct dpll clock = {
17928                 .m1 = 18,
17929                 .m2 = 7,
17930                 .p1 = 13,
17931                 .p2 = 4,
17932                 .n = 2,
17933         };
17934         u32 dpll, fp;
17935         int i;
17936
17937         drm_WARN_ON(&dev_priv->drm,
17938                     i9xx_calc_dpll_params(48000, &clock) != 25154);
17939
17940         drm_dbg_kms(&dev_priv->drm,
17941                     "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
17942                     pipe_name(pipe), clock.vco, clock.dot);
17943
17944         fp = i9xx_dpll_compute_fp(&clock);
17945         dpll = DPLL_DVO_2X_MODE |
17946                 DPLL_VGA_MODE_DIS |
17947                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
17948                 PLL_P2_DIVIDE_BY_4 |
17949                 PLL_REF_INPUT_DREFCLK |
17950                 DPLL_VCO_ENABLE;
17951
17952         intel_de_write(dev_priv, FP0(pipe), fp);
17953         intel_de_write(dev_priv, FP1(pipe), fp);
17954
17955         intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
17956         intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
17957         intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
17958         intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
17959         intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
17960         intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
17961         intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
17962
17963         /*
17964          * Apparently we need to have VGA mode enabled prior to changing
17965          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
17966          * dividers, even though the register value does change.
17967          */
17968         intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
17969         intel_de_write(dev_priv, DPLL(pipe), dpll);
17970
17971         /* Wait for the clocks to stabilize. */
17972         intel_de_posting_read(dev_priv, DPLL(pipe));
17973         udelay(150);
17974
17975         /* The pixel multiplier can only be updated once the
17976          * DPLL is enabled and the clocks are stable.
17977          *
17978          * So write it again.
17979          */
17980         intel_de_write(dev_priv, DPLL(pipe), dpll);
17981
17982         /* We do this three times for luck */
17983         for (i = 0; i < 3 ; i++) {
17984                 intel_de_write(dev_priv, DPLL(pipe), dpll);
17985                 intel_de_posting_read(dev_priv, DPLL(pipe));
17986                 udelay(150); /* wait for warmup */
17987         }
17988
17989         intel_de_write(dev_priv, PIPECONF(pipe),
17990                        PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
17991         intel_de_posting_read(dev_priv, PIPECONF(pipe));
17992
17993         intel_wait_for_pipe_scanline_moving(crtc);
17994 }
17995
17996 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
17997 {
17998         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
17999
18000         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
18001                     pipe_name(pipe));
18002
18003         drm_WARN_ON(&dev_priv->drm,
18004                     intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
18005                     DISPLAY_PLANE_ENABLE);
18006         drm_WARN_ON(&dev_priv->drm,
18007                     intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
18008                     DISPLAY_PLANE_ENABLE);
18009         drm_WARN_ON(&dev_priv->drm,
18010                     intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
18011                     DISPLAY_PLANE_ENABLE);
18012         drm_WARN_ON(&dev_priv->drm,
18013                     intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
18014         drm_WARN_ON(&dev_priv->drm,
18015                     intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
18016
18017         intel_de_write(dev_priv, PIPECONF(pipe), 0);
18018         intel_de_posting_read(dev_priv, PIPECONF(pipe));
18019
18020         intel_wait_for_pipe_scanline_stopped(crtc);
18021
18022         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
18023         intel_de_posting_read(dev_priv, DPLL(pipe));
18024 }
18025
18026 static void
18027 intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
18028 {
18029         struct intel_crtc *crtc;
18030
18031         if (INTEL_GEN(dev_priv) >= 4)
18032                 return;
18033
18034         for_each_intel_crtc(&dev_priv->drm, crtc) {
18035                 struct intel_plane *plane =
18036                         to_intel_plane(crtc->base.primary);
18037                 struct intel_crtc *plane_crtc;
18038                 enum pipe pipe;
18039
18040                 if (!plane->get_hw_state(plane, &pipe))
18041                         continue;
18042
18043                 if (pipe == crtc->pipe)
18044                         continue;
18045
18046                 drm_dbg_kms(&dev_priv->drm,
18047                             "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
18048                             plane->base.base.id, plane->base.name);
18049
18050                 plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18051                 intel_plane_disable_noatomic(plane_crtc, plane);
18052         }
18053 }
18054
18055 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
18056 {
18057         struct drm_device *dev = crtc->base.dev;
18058         struct intel_encoder *encoder;
18059
18060         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
18061                 return true;
18062
18063         return false;
18064 }
18065
18066 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
18067 {
18068         struct drm_device *dev = encoder->base.dev;
18069         struct intel_connector *connector;
18070
18071         for_each_connector_on_encoder(dev, &encoder->base, connector)
18072                 return connector;
18073
18074         return NULL;
18075 }
18076
18077 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
18078                               enum pipe pch_transcoder)
18079 {
18080         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
18081                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
18082 }
18083
18084 static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
18085 {
18086         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
18087         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
18088         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
18089
18090         if (INTEL_GEN(dev_priv) >= 9 ||
18091             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
18092                 i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
18093                 u32 val;
18094
18095                 if (transcoder_is_dsi(cpu_transcoder))
18096                         return;
18097
18098                 val = intel_de_read(dev_priv, reg);
18099                 val &= ~HSW_FRAME_START_DELAY_MASK;
18100                 val |= HSW_FRAME_START_DELAY(0);
18101                 intel_de_write(dev_priv, reg, val);
18102         } else {
18103                 i915_reg_t reg = PIPECONF(cpu_transcoder);
18104                 u32 val;
18105
18106                 val = intel_de_read(dev_priv, reg);
18107                 val &= ~PIPECONF_FRAME_START_DELAY_MASK;
18108                 val |= PIPECONF_FRAME_START_DELAY(0);
18109                 intel_de_write(dev_priv, reg, val);
18110         }
18111
18112         if (!crtc_state->has_pch_encoder)
18113                 return;
18114
18115         if (HAS_PCH_IBX(dev_priv)) {
18116                 i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
18117                 u32 val;
18118
18119                 val = intel_de_read(dev_priv, reg);
18120                 val &= ~TRANS_FRAME_START_DELAY_MASK;
18121                 val |= TRANS_FRAME_START_DELAY(0);
18122                 intel_de_write(dev_priv, reg, val);
18123         } else {
18124                 enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
18125                 i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
18126                 u32 val;
18127
18128                 val = intel_de_read(dev_priv, reg);
18129                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
18130                 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
18131                 intel_de_write(dev_priv, reg, val);
18132         }
18133 }
18134
18135 static void intel_sanitize_crtc(struct intel_crtc *crtc,
18136                                 struct drm_modeset_acquire_ctx *ctx)
18137 {
18138         struct drm_device *dev = crtc->base.dev;
18139         struct drm_i915_private *dev_priv = to_i915(dev);
18140         struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
18141
18142         if (crtc_state->hw.active) {
18143                 struct intel_plane *plane;
18144
18145                 /* Clear any frame start delays used for debugging left by the BIOS */
18146                 intel_sanitize_frame_start_delay(crtc_state);
18147
18148                 /* Disable everything but the primary plane */
18149                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
18150                         const struct intel_plane_state *plane_state =
18151                                 to_intel_plane_state(plane->base.state);
18152
18153                         if (plane_state->uapi.visible &&
18154                             plane->base.type != DRM_PLANE_TYPE_PRIMARY)
18155                                 intel_plane_disable_noatomic(crtc, plane);
18156                 }
18157
18158                 /*
18159                  * Disable any background color set by the BIOS, but enable the
18160                  * gamma and CSC to match how we program our planes.
18161                  */
18162                 if (INTEL_GEN(dev_priv) >= 9)
18163                         intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe),
18164                                        SKL_BOTTOM_COLOR_GAMMA_ENABLE | SKL_BOTTOM_COLOR_CSC_ENABLE);
18165         }
18166
18167         /* Adjust the state of the output pipe according to whether we
18168          * have active connectors/encoders. */
18169         if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
18170                 intel_crtc_disable_noatomic(crtc, ctx);
18171
18172         if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
18173                 /*
18174                  * We start out with underrun reporting disabled to avoid races.
18175                  * For correct bookkeeping mark this on active crtcs.
18176                  *
18177                  * Also on gmch platforms we dont have any hardware bits to
18178                  * disable the underrun reporting. Which means we need to start
18179                  * out with underrun reporting disabled also on inactive pipes,
18180                  * since otherwise we'll complain about the garbage we read when
18181                  * e.g. coming up after runtime pm.
18182                  *
18183                  * No protection against concurrent access is required - at
18184                  * worst a fifo underrun happens which also sets this to false.
18185                  */
18186                 crtc->cpu_fifo_underrun_disabled = true;
18187                 /*
18188                  * We track the PCH trancoder underrun reporting state
18189                  * within the crtc. With crtc for pipe A housing the underrun
18190                  * reporting state for PCH transcoder A, crtc for pipe B housing
18191                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
18192                  * and marking underrun reporting as disabled for the non-existing
18193                  * PCH transcoders B and C would prevent enabling the south
18194                  * error interrupt (see cpt_can_enable_serr_int()).
18195                  */
18196                 if (has_pch_trancoder(dev_priv, crtc->pipe))
18197                         crtc->pch_fifo_underrun_disabled = true;
18198         }
18199 }
18200
18201 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
18202 {
18203         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
18204
18205         /*
18206          * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
18207          * the hardware when a high res displays plugged in. DPLL P
18208          * divider is zero, and the pipe timings are bonkers. We'll
18209          * try to disable everything in that case.
18210          *
18211          * FIXME would be nice to be able to sanitize this state
18212          * without several WARNs, but for now let's take the easy
18213          * road.
18214          */
18215         return IS_GEN(dev_priv, 6) &&
18216                 crtc_state->hw.active &&
18217                 crtc_state->shared_dpll &&
18218                 crtc_state->port_clock == 0;
18219 }
18220
18221 static void intel_sanitize_encoder(struct intel_encoder *encoder)
18222 {
18223         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
18224         struct intel_connector *connector;
18225         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18226         struct intel_crtc_state *crtc_state = crtc ?
18227                 to_intel_crtc_state(crtc->base.state) : NULL;
18228
18229         /* We need to check both for a crtc link (meaning that the
18230          * encoder is active and trying to read from a pipe) and the
18231          * pipe itself being active. */
18232         bool has_active_crtc = crtc_state &&
18233                 crtc_state->hw.active;
18234
18235         if (crtc_state && has_bogus_dpll_config(crtc_state)) {
18236                 drm_dbg_kms(&dev_priv->drm,
18237                             "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
18238                             pipe_name(crtc->pipe));
18239                 has_active_crtc = false;
18240         }
18241
18242         connector = intel_encoder_find_connector(encoder);
18243         if (connector && !has_active_crtc) {
18244                 drm_dbg_kms(&dev_priv->drm,
18245                             "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
18246                             encoder->base.base.id,
18247                             encoder->base.name);
18248
18249                 /* Connector is active, but has no active pipe. This is
18250                  * fallout from our resume register restoring. Disable
18251                  * the encoder manually again. */
18252                 if (crtc_state) {
18253                         struct drm_encoder *best_encoder;
18254
18255                         drm_dbg_kms(&dev_priv->drm,
18256                                     "[ENCODER:%d:%s] manually disabled\n",
18257                                     encoder->base.base.id,
18258                                     encoder->base.name);
18259
18260                         /* avoid oopsing in case the hooks consult best_encoder */
18261                         best_encoder = connector->base.state->best_encoder;
18262                         connector->base.state->best_encoder = &encoder->base;
18263
18264                         if (encoder->disable)
18265                                 encoder->disable(encoder, crtc_state,
18266                                                  connector->base.state);
18267                         if (encoder->post_disable)
18268                                 encoder->post_disable(encoder, crtc_state,
18269                                                       connector->base.state);
18270
18271                         connector->base.state->best_encoder = best_encoder;
18272                 }
18273                 encoder->base.crtc = NULL;
18274
18275                 /* Inconsistent output/port/pipe state happens presumably due to
18276                  * a bug in one of the get_hw_state functions. Or someplace else
18277                  * in our code, like the register restore mess on resume. Clamp
18278                  * things to off as a safer default. */
18279
18280                 connector->base.dpms = DRM_MODE_DPMS_OFF;
18281                 connector->base.encoder = NULL;
18282         }
18283
18284         /* notify opregion of the sanitized encoder state */
18285         intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
18286
18287         if (INTEL_GEN(dev_priv) >= 11)
18288                 icl_sanitize_encoder_pll_mapping(encoder);
18289 }
18290
18291 /* FIXME read out full plane state for all planes */
18292 static void readout_plane_state(struct drm_i915_private *dev_priv)
18293 {
18294         struct intel_plane *plane;
18295         struct intel_crtc *crtc;
18296
18297         for_each_intel_plane(&dev_priv->drm, plane) {
18298                 struct intel_plane_state *plane_state =
18299                         to_intel_plane_state(plane->base.state);
18300                 struct intel_crtc_state *crtc_state;
18301                 enum pipe pipe = PIPE_A;
18302                 bool visible;
18303
18304                 visible = plane->get_hw_state(plane, &pipe);
18305
18306                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18307                 crtc_state = to_intel_crtc_state(crtc->base.state);
18308
18309                 intel_set_plane_visible(crtc_state, plane_state, visible);
18310
18311                 drm_dbg_kms(&dev_priv->drm,
18312                             "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
18313                             plane->base.base.id, plane->base.name,
18314                             enableddisabled(visible), pipe_name(pipe));
18315         }
18316
18317         for_each_intel_crtc(&dev_priv->drm, crtc) {
18318                 struct intel_crtc_state *crtc_state =
18319                         to_intel_crtc_state(crtc->base.state);
18320
18321                 fixup_active_planes(crtc_state);
18322         }
18323 }
18324
18325 static void intel_modeset_readout_hw_state(struct drm_device *dev)
18326 {
18327         struct drm_i915_private *dev_priv = to_i915(dev);
18328         struct intel_cdclk_state *cdclk_state =
18329                 to_intel_cdclk_state(dev_priv->cdclk.obj.state);
18330         enum pipe pipe;
18331         struct intel_crtc *crtc;
18332         struct intel_encoder *encoder;
18333         struct intel_connector *connector;
18334         struct drm_connector_list_iter conn_iter;
18335         u8 active_pipes = 0;
18336
18337         for_each_intel_crtc(dev, crtc) {
18338                 struct intel_crtc_state *crtc_state =
18339                         to_intel_crtc_state(crtc->base.state);
18340
18341                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
18342                 intel_crtc_free_hw_state(crtc_state);
18343                 intel_crtc_state_reset(crtc_state, crtc);
18344
18345                 crtc_state->hw.active = crtc_state->hw.enable =
18346                         dev_priv->display.get_pipe_config(crtc, crtc_state);
18347
18348                 crtc->base.enabled = crtc_state->hw.enable;
18349                 crtc->active = crtc_state->hw.active;
18350
18351                 if (crtc_state->hw.active)
18352                         active_pipes |= BIT(crtc->pipe);
18353
18354                 drm_dbg_kms(&dev_priv->drm,
18355                             "[CRTC:%d:%s] hw state readout: %s\n",
18356                             crtc->base.base.id, crtc->base.name,
18357                             enableddisabled(crtc_state->hw.active));
18358         }
18359
18360         dev_priv->active_pipes = cdclk_state->active_pipes = active_pipes;
18361
18362         readout_plane_state(dev_priv);
18363
18364         intel_dpll_readout_hw_state(dev_priv);
18365
18366         for_each_intel_encoder(dev, encoder) {
18367                 pipe = 0;
18368
18369                 if (encoder->get_hw_state(encoder, &pipe)) {
18370                         struct intel_crtc_state *crtc_state;
18371
18372                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
18373                         crtc_state = to_intel_crtc_state(crtc->base.state);
18374
18375                         encoder->base.crtc = &crtc->base;
18376                         encoder->get_config(encoder, crtc_state);
18377                 } else {
18378                         encoder->base.crtc = NULL;
18379                 }
18380
18381                 drm_dbg_kms(&dev_priv->drm,
18382                             "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
18383                             encoder->base.base.id, encoder->base.name,
18384                             enableddisabled(encoder->base.crtc),
18385                             pipe_name(pipe));
18386         }
18387
18388         drm_connector_list_iter_begin(dev, &conn_iter);
18389         for_each_intel_connector_iter(connector, &conn_iter) {
18390                 if (connector->get_hw_state(connector)) {
18391                         struct intel_crtc_state *crtc_state;
18392                         struct intel_crtc *crtc;
18393
18394                         connector->base.dpms = DRM_MODE_DPMS_ON;
18395
18396                         encoder = intel_attached_encoder(connector);
18397                         connector->base.encoder = &encoder->base;
18398
18399                         crtc = to_intel_crtc(encoder->base.crtc);
18400                         crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
18401
18402                         if (crtc_state && crtc_state->hw.active) {
18403                                 /*
18404                                  * This has to be done during hardware readout
18405                                  * because anything calling .crtc_disable may
18406                                  * rely on the connector_mask being accurate.
18407                                  */
18408                                 crtc_state->uapi.connector_mask |=
18409                                         drm_connector_mask(&connector->base);
18410                                 crtc_state->uapi.encoder_mask |=
18411                                         drm_encoder_mask(&encoder->base);
18412                         }
18413                 } else {
18414                         connector->base.dpms = DRM_MODE_DPMS_OFF;
18415                         connector->base.encoder = NULL;
18416                 }
18417                 drm_dbg_kms(&dev_priv->drm,
18418                             "[CONNECTOR:%d:%s] hw state readout: %s\n",
18419                             connector->base.base.id, connector->base.name,
18420                             enableddisabled(connector->base.encoder));
18421         }
18422         drm_connector_list_iter_end(&conn_iter);
18423
18424         for_each_intel_crtc(dev, crtc) {
18425                 struct intel_bw_state *bw_state =
18426                         to_intel_bw_state(dev_priv->bw_obj.state);
18427                 struct intel_crtc_state *crtc_state =
18428                         to_intel_crtc_state(crtc->base.state);
18429                 struct intel_plane *plane;
18430                 int min_cdclk = 0;
18431
18432                 if (crtc_state->hw.active) {
18433                         struct drm_display_mode *mode = &crtc_state->hw.mode;
18434
18435                         intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
18436                                                     crtc_state);
18437
18438                         *mode = crtc_state->hw.adjusted_mode;
18439                         mode->hdisplay = crtc_state->pipe_src_w;
18440                         mode->vdisplay = crtc_state->pipe_src_h;
18441
18442                         /*
18443                          * The initial mode needs to be set in order to keep
18444                          * the atomic core happy. It wants a valid mode if the
18445                          * crtc's enabled, so we do the above call.
18446                          *
18447                          * But we don't set all the derived state fully, hence
18448                          * set a flag to indicate that a full recalculation is
18449                          * needed on the next commit.
18450                          */
18451                         mode->private_flags = I915_MODE_FLAG_INHERITED;
18452
18453                         intel_crtc_compute_pixel_rate(crtc_state);
18454
18455                         intel_crtc_update_active_timings(crtc_state);
18456
18457                         intel_crtc_copy_hw_to_uapi_state(crtc_state);
18458                 }
18459
18460                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
18461                         const struct intel_plane_state *plane_state =
18462                                 to_intel_plane_state(plane->base.state);
18463
18464                         /*
18465                          * FIXME don't have the fb yet, so can't
18466                          * use intel_plane_data_rate() :(
18467                          */
18468                         if (plane_state->uapi.visible)
18469                                 crtc_state->data_rate[plane->id] =
18470                                         4 * crtc_state->pixel_rate;
18471                         /*
18472                          * FIXME don't have the fb yet, so can't
18473                          * use plane->min_cdclk() :(
18474                          */
18475                         if (plane_state->uapi.visible && plane->min_cdclk) {
18476                                 if (crtc_state->double_wide ||
18477                                     INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
18478                                         crtc_state->min_cdclk[plane->id] =
18479                                                 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
18480                                 else
18481                                         crtc_state->min_cdclk[plane->id] =
18482                                                 crtc_state->pixel_rate;
18483                         }
18484                         drm_dbg_kms(&dev_priv->drm,
18485                                     "[PLANE:%d:%s] min_cdclk %d kHz\n",
18486                                     plane->base.base.id, plane->base.name,
18487                                     crtc_state->min_cdclk[plane->id]);
18488                 }
18489
18490                 if (crtc_state->hw.active) {
18491                         min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
18492                         if (drm_WARN_ON(dev, min_cdclk < 0))
18493                                 min_cdclk = 0;
18494                 }
18495
18496                 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
18497                 cdclk_state->min_voltage_level[crtc->pipe] =
18498                         crtc_state->min_voltage_level;
18499
18500                 intel_bw_crtc_update(bw_state, crtc_state);
18501
18502                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
18503         }
18504 }
18505
18506 static void
18507 get_encoder_power_domains(struct drm_i915_private *dev_priv)
18508 {
18509         struct intel_encoder *encoder;
18510
18511         for_each_intel_encoder(&dev_priv->drm, encoder) {
18512                 struct intel_crtc_state *crtc_state;
18513
18514                 if (!encoder->get_power_domains)
18515                         continue;
18516
18517                 /*
18518                  * MST-primary and inactive encoders don't have a crtc state
18519                  * and neither of these require any power domain references.
18520                  */
18521                 if (!encoder->base.crtc)
18522                         continue;
18523
18524                 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
18525                 encoder->get_power_domains(encoder, crtc_state);
18526         }
18527 }
18528
18529 static void intel_early_display_was(struct drm_i915_private *dev_priv)
18530 {
18531         /*
18532          * Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl
18533          * Also known as Wa_14010480278.
18534          */
18535         if (IS_GEN_RANGE(dev_priv, 10, 12) || IS_GEMINILAKE(dev_priv))
18536                 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
18537                                intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
18538
18539         if (IS_HASWELL(dev_priv)) {
18540                 /*
18541                  * WaRsPkgCStateDisplayPMReq:hsw
18542                  * System hang if this isn't done before disabling all planes!
18543                  */
18544                 intel_de_write(dev_priv, CHICKEN_PAR1_1,
18545                                intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
18546         }
18547 }
18548
18549 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
18550                                        enum port port, i915_reg_t hdmi_reg)
18551 {
18552         u32 val = intel_de_read(dev_priv, hdmi_reg);
18553
18554         if (val & SDVO_ENABLE ||
18555             (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
18556                 return;
18557
18558         drm_dbg_kms(&dev_priv->drm,
18559                     "Sanitizing transcoder select for HDMI %c\n",
18560                     port_name(port));
18561
18562         val &= ~SDVO_PIPE_SEL_MASK;
18563         val |= SDVO_PIPE_SEL(PIPE_A);
18564
18565         intel_de_write(dev_priv, hdmi_reg, val);
18566 }
18567
18568 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
18569                                      enum port port, i915_reg_t dp_reg)
18570 {
18571         u32 val = intel_de_read(dev_priv, dp_reg);
18572
18573         if (val & DP_PORT_EN ||
18574             (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
18575                 return;
18576
18577         drm_dbg_kms(&dev_priv->drm,
18578                     "Sanitizing transcoder select for DP %c\n",
18579                     port_name(port));
18580
18581         val &= ~DP_PIPE_SEL_MASK;
18582         val |= DP_PIPE_SEL(PIPE_A);
18583
18584         intel_de_write(dev_priv, dp_reg, val);
18585 }
18586
18587 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
18588 {
18589         /*
18590          * The BIOS may select transcoder B on some of the PCH
18591          * ports even it doesn't enable the port. This would trip
18592          * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
18593          * Sanitize the transcoder select bits to prevent that. We
18594          * assume that the BIOS never actually enabled the port,
18595          * because if it did we'd actually have to toggle the port
18596          * on and back off to make the transcoder A select stick
18597          * (see. intel_dp_link_down(), intel_disable_hdmi(),
18598          * intel_disable_sdvo()).
18599          */
18600         ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
18601         ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
18602         ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
18603
18604         /* PCH SDVOB multiplex with HDMIB */
18605         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
18606         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
18607         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
18608 }
18609
18610 /* Scan out the current hw modeset state,
18611  * and sanitizes it to the current state
18612  */
18613 static void
18614 intel_modeset_setup_hw_state(struct drm_device *dev,
18615                              struct drm_modeset_acquire_ctx *ctx)
18616 {
18617         struct drm_i915_private *dev_priv = to_i915(dev);
18618         struct intel_encoder *encoder;
18619         struct intel_crtc *crtc;
18620         intel_wakeref_t wakeref;
18621
18622         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
18623
18624         intel_early_display_was(dev_priv);
18625         intel_modeset_readout_hw_state(dev);
18626
18627         /* HW state is read out, now we need to sanitize this mess. */
18628
18629         /* Sanitize the TypeC port mode upfront, encoders depend on this */
18630         for_each_intel_encoder(dev, encoder) {
18631                 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
18632
18633                 /* We need to sanitize only the MST primary port. */
18634                 if (encoder->type != INTEL_OUTPUT_DP_MST &&
18635                     intel_phy_is_tc(dev_priv, phy))
18636                         intel_tc_port_sanitize(enc_to_dig_port(encoder));
18637         }
18638
18639         get_encoder_power_domains(dev_priv);
18640
18641         if (HAS_PCH_IBX(dev_priv))
18642                 ibx_sanitize_pch_ports(dev_priv);
18643
18644         /*
18645          * intel_sanitize_plane_mapping() may need to do vblank
18646          * waits, so we need vblank interrupts restored beforehand.
18647          */
18648         for_each_intel_crtc(&dev_priv->drm, crtc) {
18649                 struct intel_crtc_state *crtc_state =
18650                         to_intel_crtc_state(crtc->base.state);
18651
18652                 drm_crtc_vblank_reset(&crtc->base);
18653
18654                 if (crtc_state->hw.active)
18655                         intel_crtc_vblank_on(crtc_state);
18656         }
18657
18658         intel_sanitize_plane_mapping(dev_priv);
18659
18660         for_each_intel_encoder(dev, encoder)
18661                 intel_sanitize_encoder(encoder);
18662
18663         for_each_intel_crtc(&dev_priv->drm, crtc) {
18664                 struct intel_crtc_state *crtc_state =
18665                         to_intel_crtc_state(crtc->base.state);
18666
18667                 intel_sanitize_crtc(crtc, ctx);
18668                 intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
18669         }
18670
18671         intel_modeset_update_connector_atomic_state(dev);
18672
18673         intel_dpll_sanitize_state(dev_priv);
18674
18675         if (IS_G4X(dev_priv)) {
18676                 g4x_wm_get_hw_state(dev_priv);
18677                 g4x_wm_sanitize(dev_priv);
18678         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
18679                 vlv_wm_get_hw_state(dev_priv);
18680                 vlv_wm_sanitize(dev_priv);
18681         } else if (INTEL_GEN(dev_priv) >= 9) {
18682                 skl_wm_get_hw_state(dev_priv);
18683         } else if (HAS_PCH_SPLIT(dev_priv)) {
18684                 ilk_wm_get_hw_state(dev_priv);
18685         }
18686
18687         for_each_intel_crtc(dev, crtc) {
18688                 struct intel_crtc_state *crtc_state =
18689                         to_intel_crtc_state(crtc->base.state);
18690                 u64 put_domains;
18691
18692                 put_domains = modeset_get_crtc_power_domains(crtc_state);
18693                 if (drm_WARN_ON(dev, put_domains))
18694                         modeset_put_power_domains(dev_priv, put_domains);
18695         }
18696
18697         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
18698 }
18699
18700 void intel_display_resume(struct drm_device *dev)
18701 {
18702         struct drm_i915_private *dev_priv = to_i915(dev);
18703         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
18704         struct drm_modeset_acquire_ctx ctx;
18705         int ret;
18706
18707         dev_priv->modeset_restore_state = NULL;
18708         if (state)
18709                 state->acquire_ctx = &ctx;
18710
18711         drm_modeset_acquire_init(&ctx, 0);
18712
18713         while (1) {
18714                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
18715                 if (ret != -EDEADLK)
18716                         break;
18717
18718                 drm_modeset_backoff(&ctx);
18719         }
18720
18721         if (!ret)
18722                 ret = __intel_display_resume(dev, state, &ctx);
18723
18724         intel_enable_ipc(dev_priv);
18725         drm_modeset_drop_locks(&ctx);
18726         drm_modeset_acquire_fini(&ctx);
18727
18728         if (ret)
18729                 drm_err(&dev_priv->drm,
18730                         "Restoring old state failed with %i\n", ret);
18731         if (state)
18732                 drm_atomic_state_put(state);
18733 }
18734
18735 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
18736 {
18737         struct intel_connector *connector;
18738         struct drm_connector_list_iter conn_iter;
18739
18740         /* Kill all the work that may have been queued by hpd. */
18741         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
18742         for_each_intel_connector_iter(connector, &conn_iter) {
18743                 if (connector->modeset_retry_work.func)
18744                         cancel_work_sync(&connector->modeset_retry_work);
18745                 if (connector->hdcp.shim) {
18746                         cancel_delayed_work_sync(&connector->hdcp.check_work);
18747                         cancel_work_sync(&connector->hdcp.prop_work);
18748                 }
18749         }
18750         drm_connector_list_iter_end(&conn_iter);
18751 }
18752
18753 /* part #1: call before irq uninstall */
18754 void intel_modeset_driver_remove(struct drm_i915_private *i915)
18755 {
18756         flush_workqueue(i915->flip_wq);
18757         flush_workqueue(i915->modeset_wq);
18758
18759         flush_work(&i915->atomic_helper.free_work);
18760         drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
18761 }
18762
18763 /* part #2: call after irq uninstall */
18764 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
18765 {
18766         /*
18767          * Due to the hpd irq storm handling the hotplug work can re-arm the
18768          * poll handlers. Hence disable polling after hpd handling is shut down.
18769          */
18770         intel_hpd_poll_fini(i915);
18771
18772         /*
18773          * MST topology needs to be suspended so we don't have any calls to
18774          * fbdev after it's finalized. MST will be destroyed later as part of
18775          * drm_mode_config_cleanup()
18776          */
18777         intel_dp_mst_suspend(i915);
18778
18779         /* poll work can call into fbdev, hence clean that up afterwards */
18780         intel_fbdev_fini(i915);
18781
18782         intel_unregister_dsm_handler();
18783
18784         intel_fbc_global_disable(i915);
18785
18786         /* flush any delayed tasks or pending work */
18787         flush_scheduled_work();
18788
18789         intel_hdcp_component_fini(i915);
18790
18791         intel_mode_config_cleanup(i915);
18792
18793         intel_overlay_cleanup(i915);
18794
18795         intel_gmbus_teardown(i915);
18796
18797         destroy_workqueue(i915->flip_wq);
18798         destroy_workqueue(i915->modeset_wq);
18799
18800         intel_fbc_cleanup_cfb(i915);
18801 }
18802
18803 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
18804
18805 static bool
18806 has_transcoder(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder)
18807 {
18808         if (cpu_transcoder == TRANSCODER_EDP)
18809                 return HAS_TRANSCODER_EDP(dev_priv);
18810         else
18811                 return INTEL_INFO(dev_priv)->pipe_mask & BIT(cpu_transcoder);
18812 }
18813
18814 struct intel_display_error_state {
18815
18816         u32 power_well_driver;
18817
18818         struct intel_cursor_error_state {
18819                 u32 control;
18820                 u32 position;
18821                 u32 base;
18822                 u32 size;
18823         } cursor[I915_MAX_PIPES];
18824
18825         struct intel_pipe_error_state {
18826                 bool power_domain_on;
18827                 u32 source;
18828                 u32 stat;
18829         } pipe[I915_MAX_PIPES];
18830
18831         struct intel_plane_error_state {
18832                 u32 control;
18833                 u32 stride;
18834                 u32 size;
18835                 u32 pos;
18836                 u32 addr;
18837                 u32 surface;
18838                 u32 tile_offset;
18839         } plane[I915_MAX_PIPES];
18840
18841         struct intel_transcoder_error_state {
18842                 bool available;
18843                 bool power_domain_on;
18844                 enum transcoder cpu_transcoder;
18845
18846                 u32 conf;
18847
18848                 u32 htotal;
18849                 u32 hblank;
18850                 u32 hsync;
18851                 u32 vtotal;
18852                 u32 vblank;
18853                 u32 vsync;
18854         } transcoder[5];
18855 };
18856
18857 struct intel_display_error_state *
18858 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
18859 {
18860         struct intel_display_error_state *error;
18861         int transcoders[] = {
18862                 TRANSCODER_A,
18863                 TRANSCODER_B,
18864                 TRANSCODER_C,
18865                 TRANSCODER_D,
18866                 TRANSCODER_EDP,
18867         };
18868         int i;
18869
18870         BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));
18871
18872         if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
18873                 return NULL;
18874
18875         error = kzalloc(sizeof(*error), GFP_ATOMIC);
18876         if (error == NULL)
18877                 return NULL;
18878
18879         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
18880                 error->power_well_driver = intel_de_read(dev_priv,
18881                                                          HSW_PWR_WELL_CTL2);
18882
18883         for_each_pipe(dev_priv, i) {
18884                 error->pipe[i].power_domain_on =
18885                         __intel_display_power_is_enabled(dev_priv,
18886                                                          POWER_DOMAIN_PIPE(i));
18887                 if (!error->pipe[i].power_domain_on)
18888                         continue;
18889
18890                 error->cursor[i].control = intel_de_read(dev_priv, CURCNTR(i));
18891                 error->cursor[i].position = intel_de_read(dev_priv, CURPOS(i));
18892                 error->cursor[i].base = intel_de_read(dev_priv, CURBASE(i));
18893
18894                 error->plane[i].control = intel_de_read(dev_priv, DSPCNTR(i));
18895                 error->plane[i].stride = intel_de_read(dev_priv, DSPSTRIDE(i));
18896                 if (INTEL_GEN(dev_priv) <= 3) {
18897                         error->plane[i].size = intel_de_read(dev_priv,
18898                                                              DSPSIZE(i));
18899                         error->plane[i].pos = intel_de_read(dev_priv,
18900                                                             DSPPOS(i));
18901                 }
18902                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
18903                         error->plane[i].addr = intel_de_read(dev_priv,
18904                                                              DSPADDR(i));
18905                 if (INTEL_GEN(dev_priv) >= 4) {
18906                         error->plane[i].surface = intel_de_read(dev_priv,
18907                                                                 DSPSURF(i));
18908                         error->plane[i].tile_offset = intel_de_read(dev_priv,
18909                                                                     DSPTILEOFF(i));
18910                 }
18911
18912                 error->pipe[i].source = intel_de_read(dev_priv, PIPESRC(i));
18913
18914                 if (HAS_GMCH(dev_priv))
18915                         error->pipe[i].stat = intel_de_read(dev_priv,
18916                                                             PIPESTAT(i));
18917         }
18918
18919         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
18920                 enum transcoder cpu_transcoder = transcoders[i];
18921
18922                 if (!has_transcoder(dev_priv, cpu_transcoder))
18923                         continue;
18924
18925                 error->transcoder[i].available = true;
18926                 error->transcoder[i].power_domain_on =
18927                         __intel_display_power_is_enabled(dev_priv,
18928                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
18929                 if (!error->transcoder[i].power_domain_on)
18930                         continue;
18931
18932                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
18933
18934                 error->transcoder[i].conf = intel_de_read(dev_priv,
18935                                                           PIPECONF(cpu_transcoder));
18936                 error->transcoder[i].htotal = intel_de_read(dev_priv,
18937                                                             HTOTAL(cpu_transcoder));
18938                 error->transcoder[i].hblank = intel_de_read(dev_priv,
18939                                                             HBLANK(cpu_transcoder));
18940                 error->transcoder[i].hsync = intel_de_read(dev_priv,
18941                                                            HSYNC(cpu_transcoder));
18942                 error->transcoder[i].vtotal = intel_de_read(dev_priv,
18943                                                             VTOTAL(cpu_transcoder));
18944                 error->transcoder[i].vblank = intel_de_read(dev_priv,
18945                                                             VBLANK(cpu_transcoder));
18946                 error->transcoder[i].vsync = intel_de_read(dev_priv,
18947                                                            VSYNC(cpu_transcoder));
18948         }
18949
18950         return error;
18951 }
18952
18953 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
18954
18955 void
18956 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
18957                                 struct intel_display_error_state *error)
18958 {
18959         struct drm_i915_private *dev_priv = m->i915;
18960         int i;
18961
18962         if (!error)
18963                 return;
18964
18965         err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
18966         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
18967                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
18968                            error->power_well_driver);
18969         for_each_pipe(dev_priv, i) {
18970                 err_printf(m, "Pipe [%d]:\n", i);
18971                 err_printf(m, "  Power: %s\n",
18972                            onoff(error->pipe[i].power_domain_on));
18973                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
18974                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
18975
18976                 err_printf(m, "Plane [%d]:\n", i);
18977                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
18978                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
18979                 if (INTEL_GEN(dev_priv) <= 3) {
18980                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
18981                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
18982                 }
18983                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
18984                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
18985                 if (INTEL_GEN(dev_priv) >= 4) {
18986                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
18987                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
18988                 }
18989
18990                 err_printf(m, "Cursor [%d]:\n", i);
18991                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
18992                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
18993                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
18994         }
18995
18996         for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {
18997                 if (!error->transcoder[i].available)
18998                         continue;
18999
19000                 err_printf(m, "CPU transcoder: %s\n",
19001                            transcoder_name(error->transcoder[i].cpu_transcoder));
19002                 err_printf(m, "  Power: %s\n",
19003                            onoff(error->transcoder[i].power_domain_on));
19004                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
19005                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
19006                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
19007                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
19008                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
19009                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
19010                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
19011         }
19012 }
19013
19014 #endif