drivers/gpu/drm/i915/display/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dma-resv.h>
  28 #include <linux/i2c.h>
  29 #include <linux/input.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/slab.h>
  33 #include <linux/string_helpers.h>
  34
  35 #include <drm/display/drm_dp_helper.h>
  36 #include <drm/display/drm_dp_tunnel.h>
  37 #include <drm/drm_atomic.h>
  38 #include <drm/drm_atomic_helper.h>
  39 #include <drm/drm_atomic_uapi.h>
  40 #include <drm/drm_damage_helper.h>
  41 #include <drm/drm_edid.h>
  42 #include <drm/drm_fourcc.h>
  43 #include <drm/drm_probe_helper.h>
  44 #include <drm/drm_rect.h>
  45
  46 #include "gem/i915_gem_lmem.h"
  47 #include "gem/i915_gem_object.h"
  48
  49 #include "g4x_dp.h"
  50 #include "g4x_hdmi.h"
  51 #include "hsw_ips.h"
  52 #include "i915_config.h"
  53 #include "i915_drv.h"
  54 #include "i915_reg.h"
  55 #include "i915_utils.h"
  56 #include "i9xx_plane.h"
  57 #include "i9xx_wm.h"
  58 #include "intel_atomic.h"
  59 #include "intel_atomic_plane.h"
  60 #include "intel_audio.h"
  61 #include "intel_bw.h"
  62 #include "intel_cdclk.h"
  63 #include "intel_clock_gating.h"
  64 #include "intel_color.h"
  65 #include "intel_crt.h"
  66 #include "intel_crtc.h"
  67 #include "intel_crtc_state_dump.h"
  68 #include "intel_ddi.h"
  69 #include "intel_de.h"
  70 #include "intel_display_driver.h"
  71 #include "intel_display_power.h"
  72 #include "intel_display_types.h"
  73 #include "intel_dmc.h"
  74 #include "intel_dp.h"
  75 #include "intel_dp_link_training.h"
  76 #include "intel_dp_mst.h"
  77 #include "intel_dp_tunnel.h"
  78 #include "intel_dpll.h"
  79 #include "intel_dpll_mgr.h"
  80 #include "intel_dpt.h"
  81 #include "intel_dpt_common.h"
  82 #include "intel_drrs.h"
  83 #include "intel_dsb.h"
  84 #include "intel_dsi.h"
  85 #include "intel_dvo.h"
  86 #include "intel_fb.h"
  87 #include "intel_fbc.h"
  88 #include "intel_fdi.h"
  89 #include "intel_fifo_underrun.h"
  90 #include "intel_frontbuffer.h"
  91 #include "intel_hdmi.h"
  92 #include "intel_hotplug.h"
  93 #include "intel_link_bw.h"
  94 #include "intel_lvds.h"
  95 #include "intel_lvds_regs.h"
  96 #include "intel_modeset_setup.h"
  97 #include "intel_modeset_verify.h"
  98 #include "intel_overlay.h"
  99 #include "intel_panel.h"
 100 #include "intel_pch_display.h"
 101 #include "intel_pch_refclk.h"
 102 #include "intel_pcode.h"
 103 #include "intel_pipe_crc.h"
 104 #include "intel_plane_initial.h"
 105 #include "intel_pmdemand.h"
 106 #include "intel_pps.h"
 107 #include "intel_psr.h"
 108 #include "intel_psr_regs.h"
 109 #include "intel_sdvo.h"
 110 #include "intel_snps_phy.h"
 111 #include "intel_tc.h"
 112 #include "intel_tv.h"
 113 #include "intel_vblank.h"
 114 #include "intel_vdsc.h"
 115 #include "intel_vdsc_regs.h"
 116 #include "intel_vga.h"
 117 #include "intel_vrr.h"
 118 #include "intel_wm.h"
 119 #include "skl_scaler.h"
 120 #include "skl_universal_plane.h"
 121 #include "skl_watermark.h"
 122 #include "vlv_dpio_phy_regs.h"
 123 #include "vlv_dsi.h"
 124 #include "vlv_dsi_pll.h"
 125 #include "vlv_dsi_regs.h"
 126 #include "vlv_sideband.h"
 127
 128 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 129 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 130 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
 131 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state);
 132
 133 /* returns HPLL frequency in kHz */
 134 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 135 {
 136         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 137
 138         /* Obtain SKU information */
 139         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 140                 CCK_FUSE_HPLL_FREQ_MASK;
 141
 142         return vco_freq[hpll_freq] * 1000;
 143 }
 144
 145 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 146                       const char *name, u32 reg, int ref_freq)
 147 {
 148         u32 val;
 149         int divider;
 150
 151         val = vlv_cck_read(dev_priv, reg);
 152         divider = val & CCK_FREQUENCY_VALUES;
 153
 154         drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
 155                  (divider << CCK_FREQUENCY_STATUS_SHIFT),
 156                  "%s change in progress\n", name);
 157
 158         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 159 }
 160
 161 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 162                            const char *name, u32 reg)
 163 {
 164         int hpll;
 165
 166         vlv_cck_get(dev_priv);
 167
 168         if (dev_priv->hpll_freq == 0)
 169                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 170
 171         hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
 172
 173         vlv_cck_put(dev_priv);
 174
 175         return hpll;
 176 }
 177
 178 void intel_update_czclk(struct drm_i915_private *dev_priv)
 179 {
 180         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 181                 return;
 182
 183         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 184                                                       CCK_CZ_CLOCK_CONTROL);
 185
 186         drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
 187                 dev_priv->czclk_freq);
 188 }
 189
 190 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
 191 {
 192         return (crtc_state->active_planes &
 193                 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0;
 194 }
 195
 196 /* WA Display #0827: Gen9:all */
 197 static void
 198 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
 199 {
 200         intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
 201                      DUPS1_GATING_DIS | DUPS2_GATING_DIS,
 202                      enable ? DUPS1_GATING_DIS | DUPS2_GATING_DIS : 0);
 203 }
 204
 205 /* Wa_2006604312:icl,ehl */
 206 static void
 207 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 208                        bool enable)
 209 {
 210         intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
 211                      DPFR_GATING_DIS,
 212                      enable ? DPFR_GATING_DIS : 0);
 213 }
 214
 215 /* Wa_1604331009:icl,jsl,ehl */
 216 static void
 217 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 218                        bool enable)
 219 {
 220         intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
 221                      CURSOR_GATING_DIS,
 222                      enable ? CURSOR_GATING_DIS : 0);
 223 }
 224
 225 static bool
 226 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
 227 {
 228         return crtc_state->master_transcoder != INVALID_TRANSCODER;
 229 }
 230
 231 bool
 232 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
 233 {
 234         return crtc_state->sync_mode_slaves_mask != 0;
 235 }
 236
 237 bool
 238 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 239 {
 240         return is_trans_port_sync_master(crtc_state) ||
 241                 is_trans_port_sync_slave(crtc_state);
 242 }
 243
 244 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state)
 245 {
 246         return ffs(crtc_state->bigjoiner_pipes) - 1;
 247 }
 248
 249 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state)
 250 {
 251         if (crtc_state->bigjoiner_pipes)
 252                 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state));
 253         else
 254                 return 0;
 255 }
 256
 257 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state)
 258 {
 259         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 260
 261         return crtc_state->bigjoiner_pipes &&
 262                 crtc->pipe != bigjoiner_master_pipe(crtc_state);
 263 }
 264
 265 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state)
 266 {
 267         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 268
 269         return crtc_state->bigjoiner_pipes &&
 270                 crtc->pipe == bigjoiner_master_pipe(crtc_state);
 271 }
 272
 273 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state)
 274 {
 275         return hweight8(crtc_state->bigjoiner_pipes);
 276 }
 277
 278 u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state)
 279 {
 280         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 281
 282         return BIT(crtc->pipe) | crtc_state->bigjoiner_pipes;
 283 }
 284
 285 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state)
 286 {
 287         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 288
 289         if (intel_crtc_is_bigjoiner_slave(crtc_state))
 290                 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state));
 291         else
 292                 return to_intel_crtc(crtc_state->uapi.crtc);
 293 }
 294
 295 static void
 296 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
 297 {
 298         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 299         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 300
 301         if (DISPLAY_VER(dev_priv) >= 4) {
 302                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 303
 304                 /* Wait for the Pipe State to go off */
 305                 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder),
 306                                             TRANSCONF_STATE_ENABLE, 100))
 307                         drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
 308         } else {
 309                 intel_wait_for_pipe_scanline_stopped(crtc);
 310         }
 311 }
 312
 313 void assert_transcoder(struct drm_i915_private *dev_priv,
 314                        enum transcoder cpu_transcoder, bool state)
 315 {
 316         bool cur_state;
 317         enum intel_display_power_domain power_domain;
 318         intel_wakeref_t wakeref;
 319
 320         /* we keep both pipes enabled on 830 */
 321         if (IS_I830(dev_priv))
 322                 state = true;
 323
 324         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 325         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
 326         if (wakeref) {
 327                 u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
 328                 cur_state = !!(val & TRANSCONF_ENABLE);
 329
 330                 intel_display_power_put(dev_priv, power_domain, wakeref);
 331         } else {
 332                 cur_state = false;
 333         }
 334
 335         I915_STATE_WARN(dev_priv, cur_state != state,
 336                         "transcoder %s assertion failure (expected %s, current %s)\n",
 337                         transcoder_name(cpu_transcoder), str_on_off(state),
 338                         str_on_off(cur_state));
 339 }
 340
 341 static void assert_plane(struct intel_plane *plane, bool state)
 342 {
 343         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 344         enum pipe pipe;
 345         bool cur_state;
 346
 347         cur_state = plane->get_hw_state(plane, &pipe);
 348
 349         I915_STATE_WARN(i915, cur_state != state,
 350                         "%s assertion failure (expected %s, current %s)\n",
 351                         plane->base.name, str_on_off(state),
 352                         str_on_off(cur_state));
 353 }
 354
 355 #define assert_plane_enabled(p) assert_plane(p, true)
 356 #define assert_plane_disabled(p) assert_plane(p, false)
 357
 358 static void assert_planes_disabled(struct intel_crtc *crtc)
 359 {
 360         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 361         struct intel_plane *plane;
 362
 363         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
 364                 assert_plane_disabled(plane);
 365 }
 366
 367 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 368                          struct intel_digital_port *dig_port,
 369                          unsigned int expected_mask)
 370 {
 371         u32 port_mask;
 372         i915_reg_t dpll_reg;
 373
 374         switch (dig_port->base.port) {
 375         default:
 376                 MISSING_CASE(dig_port->base.port);
 377                 fallthrough;
 378         case PORT_B:
 379                 port_mask = DPLL_PORTB_READY_MASK;
 380                 dpll_reg = DPLL(0);
 381                 break;
 382         case PORT_C:
 383                 port_mask = DPLL_PORTC_READY_MASK;
 384                 dpll_reg = DPLL(0);
 385                 expected_mask <<= 4;
 386                 break;
 387         case PORT_D:
 388                 port_mask = DPLL_PORTD_READY_MASK;
 389                 dpll_reg = DPIO_PHY_STATUS;
 390                 break;
 391         }
 392
 393         if (intel_de_wait(dev_priv, dpll_reg, port_mask, expected_mask, 1000))
 394                 drm_WARN(&dev_priv->drm, 1,
 395                          "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
 396                          dig_port->base.base.base.id, dig_port->base.base.name,
 397                          intel_de_read(dev_priv, dpll_reg) & port_mask,
 398                          expected_mask);
 399 }
 400
 401 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
 402 {
 403         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 404         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 405         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 406         enum pipe pipe = crtc->pipe;
 407         u32 val;
 408
 409         drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
 410
 411         assert_planes_disabled(crtc);
 412
 413         /*
 414          * A pipe without a PLL won't actually be able to drive bits from
 415          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
 416          * need the check.
 417          */
 418         if (HAS_GMCH(dev_priv)) {
 419                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
 420                         assert_dsi_pll_enabled(dev_priv);
 421                 else
 422                         assert_pll_enabled(dev_priv, pipe);
 423         } else {
 424                 if (new_crtc_state->has_pch_encoder) {
 425                         /* if driving the PCH, we need FDI enabled */
 426                         assert_fdi_rx_pll_enabled(dev_priv,
 427                                                   intel_crtc_pch_transcoder(crtc));
 428                         assert_fdi_tx_pll_enabled(dev_priv,
 429                                                   (enum pipe) cpu_transcoder);
 430                 }
 431                 /* FIXME: assert CPU port conditions for SNB+ */
 432         }
 433
 434         /* Wa_22012358565:adl-p */
 435         if (DISPLAY_VER(dev_priv) == 13)
 436                 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
 437                              0, PIPE_ARB_USE_PROG_SLOTS);
 438
 439         if (DISPLAY_VER(dev_priv) >= 14) {
 440                 u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA;
 441                 u32 set = 0;
 442
 443                 if (DISPLAY_VER(dev_priv) == 14)
 444                         set |= DP_FEC_BS_JITTER_WA;
 445
 446                 intel_de_rmw(dev_priv,
 447                              hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
 448                              clear, set);
 449         }
 450
 451         val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
 452         if (val & TRANSCONF_ENABLE) {
 453                 /* we keep both pipes enabled on 830 */
 454                 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
 455                 return;
 456         }
 457
 458         /* Wa_1409098942:adlp+ */
 459         if (DISPLAY_VER(dev_priv) >= 13 &&
 460             new_crtc_state->dsc.compression_enable) {
 461                 val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
 462                 val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK,
 463                                       TRANSCONF_PIXEL_COUNT_SCALING_X4);
 464         }
 465
 466         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder),
 467                        val | TRANSCONF_ENABLE);
 468         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
 469
 470         /*
 471          * Until the pipe starts PIPEDSL reads will return a stale value,
 472          * which causes an apparent vblank timestamp jump when PIPEDSL
 473          * resets to its proper value. That also messes up the frame count
 474          * when it's derived from the timestamps. So let's wait for the
 475          * pipe to start properly before we call drm_crtc_vblank_on()
 476          */
 477         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
 478                 intel_wait_for_pipe_scanline_moving(crtc);
 479 }
 480
 481 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
 482 {
 483         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 484         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 485         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 486         enum pipe pipe = crtc->pipe;
 487         u32 val;
 488
 489         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
 490
 491         /*
 492          * Make sure planes won't keep trying to pump pixels to us,
 493          * or we might hang the display.
 494          */
 495         assert_planes_disabled(crtc);
 496
 497         val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
 498         if ((val & TRANSCONF_ENABLE) == 0)
 499                 return;
 500
 501         /*
 502          * Double wide has implications for planes
 503          * so best keep it disabled when not needed.
 504          */
 505         if (old_crtc_state->double_wide)
 506                 val &= ~TRANSCONF_DOUBLE_WIDE;
 507
 508         /* Don't disable pipe or pipe PLLs if needed */
 509         if (!IS_I830(dev_priv))
 510                 val &= ~TRANSCONF_ENABLE;
 511
 512         /* Wa_1409098942:adlp+ */
 513         if (DISPLAY_VER(dev_priv) >= 13 &&
 514             old_crtc_state->dsc.compression_enable)
 515                 val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
 516
 517         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
 518
 519         if (DISPLAY_VER(dev_priv) >= 12)
 520                 intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
 521                              FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
 522
 523         if ((val & TRANSCONF_ENABLE) == 0)
 524                 intel_wait_for_pipe_off(old_crtc_state);
 525 }
 526
 527 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
 528 {
 529         unsigned int size = 0;
 530         int i;
 531
 532         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
 533                 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;
 534
 535         return size;
 536 }
 537
 538 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
 539 {
 540         unsigned int size = 0;
 541         int i;
 542
 543         for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
 544                 unsigned int plane_size;
 545
 546                 if (rem_info->plane[i].linear)
 547                         plane_size = rem_info->plane[i].size;
 548                 else
 549                         plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height;
 550
 551                 if (plane_size == 0)
 552                         continue;
 553
 554                 if (rem_info->plane_alignment)
 555                         size = ALIGN(size, rem_info->plane_alignment);
 556
 557                 size += plane_size;
 558         }
 559
 560         return size;
 561 }
 562
 563 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
 564 {
 565         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 566         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 567
 568         return DISPLAY_VER(dev_priv) < 4 ||
 569                 (plane->fbc && !plane_state->no_fbc_reason &&
 570                  plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL);
 571 }
 572
 573 /*
 574  * Convert the x/y offsets into a linear offset.
 575  * Only valid with 0/180 degree rotation, which is fine since linear
 576  * offset is only used with linear buffers on pre-hsw and tiled buffers
 577  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
 578  */
 579 u32 intel_fb_xy_to_linear(int x, int y,
 580                           const struct intel_plane_state *state,
 581                           int color_plane)
 582 {
 583         const struct drm_framebuffer *fb = state->hw.fb;
 584         unsigned int cpp = fb->format->cpp[color_plane];
 585         unsigned int pitch = state->view.color_plane[color_plane].mapping_stride;
 586
 587         return y * pitch + x * cpp;
 588 }
 589
 590 /*
 591  * Add the x/y offsets derived from fb->offsets[] to the user
 592  * specified plane src x/y offsets. The resulting x/y offsets
 593  * specify the start of scanout from the beginning of the gtt mapping.
 594  */
 595 void intel_add_fb_offsets(int *x, int *y,
 596                           const struct intel_plane_state *state,
 597                           int color_plane)
 598
 599 {
 600         *x += state->view.color_plane[color_plane].x;
 601         *y += state->view.color_plane[color_plane].y;
 602 }
 603
 604 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 605                               u32 pixel_format, u64 modifier)
 606 {
 607         struct intel_crtc *crtc;
 608         struct intel_plane *plane;
 609
 610         if (!HAS_DISPLAY(dev_priv))
 611                 return 0;
 612
 613         /*
 614          * We assume the primary plane for pipe A has
 615          * the highest stride limits of them all,
 616          * if in case pipe A is disabled, use the first pipe from pipe_mask.
 617          */
 618         crtc = intel_first_crtc(dev_priv);
 619         if (!crtc)
 620                 return 0;
 621
 622         plane = to_intel_plane(crtc->base.primary);
 623
 624         return plane->max_stride(plane, pixel_format, modifier,
 625                                  DRM_MODE_ROTATE_0);
 626 }
 627
 628 void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
 629                              struct intel_plane_state *plane_state,
 630                              bool visible)
 631 {
 632         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 633
 634         plane_state->uapi.visible = visible;
 635
 636         if (visible)
 637                 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
 638         else
 639                 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
 640 }
 641
 642 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
 643 {
 644         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 645         struct drm_plane *plane;
 646
 647         /*
 648          * Active_planes aliases if multiple "primary" or cursor planes
 649          * have been used on the same (or wrong) pipe. plane_mask uses
 650          * unique ids, hence we can use that to reconstruct active_planes.
 651          */
 652         crtc_state->enabled_planes = 0;
 653         crtc_state->active_planes = 0;
 654
 655         drm_for_each_plane_mask(plane, &dev_priv->drm,
 656                                 crtc_state->uapi.plane_mask) {
 657                 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
 658                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
 659         }
 660 }
 661
 662 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 663                                   struct intel_plane *plane)
 664 {
 665         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 666         struct intel_crtc_state *crtc_state =
 667                 to_intel_crtc_state(crtc->base.state);
 668         struct intel_plane_state *plane_state =
 669                 to_intel_plane_state(plane->base.state);
 670
 671         drm_dbg_kms(&dev_priv->drm,
 672                     "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
 673                     plane->base.base.id, plane->base.name,
 674                     crtc->base.base.id, crtc->base.name);
 675
 676         intel_set_plane_visible(crtc_state, plane_state, false);
 677         intel_plane_fixup_bitmasks(crtc_state);
 678         crtc_state->data_rate[plane->id] = 0;
 679         crtc_state->data_rate_y[plane->id] = 0;
 680         crtc_state->rel_data_rate[plane->id] = 0;
 681         crtc_state->rel_data_rate_y[plane->id] = 0;
 682         crtc_state->min_cdclk[plane->id] = 0;
 683
 684         if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
 685             hsw_ips_disable(crtc_state)) {
 686                 crtc_state->ips_enabled = false;
 687                 intel_crtc_wait_for_next_vblank(crtc);
 688         }
 689
 690         /*
 691          * Vblank time updates from the shadow to live plane control register
 692          * are blocked if the memory self-refresh mode is active at that
 693          * moment. So to make sure the plane gets truly disabled, disable
 694          * first the self-refresh mode. The self-refresh enable bit in turn
 695          * will be checked/applied by the HW only at the next frame start
 696          * event which is after the vblank start event, so we need to have a
 697          * wait-for-vblank between disabling the plane and the pipe.
 698          */
 699         if (HAS_GMCH(dev_priv) &&
 700             intel_set_memory_cxsr(dev_priv, false))
 701                 intel_crtc_wait_for_next_vblank(crtc);
 702
 703         /*
 704          * Gen2 reports pipe underruns whenever all planes are disabled.
 705          * So disable underrun reporting before all the planes get disabled.
 706          */
 707         if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
 708                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
 709
 710         intel_plane_disable_arm(plane, crtc_state);
 711         intel_crtc_wait_for_next_vblank(crtc);
 712 }
 713
 714 unsigned int
 715 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
 716 {
 717         int x = 0, y = 0;
 718
 719         intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
 720                                           plane_state->view.color_plane[0].offset, 0);
 721
 722         return y;
 723 }
 724
 725 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
 726 {
 727         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 728         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 729         enum pipe pipe = crtc->pipe;
 730         u32 tmp;
 731
 732         tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
 733
 734         /*
 735          * Display WA #1153: icl
 736          * enable hardware to bypass the alpha math
 737          * and rounding for per-pixel values 00 and 0xff
 738          */
 739         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
 740         /*
 741          * Display WA # 1605353570: icl
 742          * Set the pixel rounding bit to 1 for allowing
 743          * passthrough of Frame buffer pixels unmodified
 744          * across pipe
 745          */
 746         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
 747
 748         /*
 749          * Underrun recovery must always be disabled on display 13+.
 750          * DG2 chicken bit meaning is inverted compared to other platforms.
 751          */
 752         if (IS_DG2(dev_priv))
 753                 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
 754         else if (DISPLAY_VER(dev_priv) >= 13)
 755                 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
 756
 757         /* Wa_14010547955:dg2 */
 758         if (IS_DG2(dev_priv))
 759                 tmp |= DG2_RENDER_CCSTAG_4_3_EN;
 760
 761         intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
 762 }
 763
 764 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
 765 {
 766         struct drm_crtc *crtc;
 767         bool cleanup_done;
 768
 769         drm_for_each_crtc(crtc, &dev_priv->drm) {
 770                 struct drm_crtc_commit *commit;
 771                 spin_lock(&crtc->commit_lock);
 772                 commit = list_first_entry_or_null(&crtc->commit_list,
 773                                                   struct drm_crtc_commit, commit_entry);
 774                 cleanup_done = commit ?
 775                         try_wait_for_completion(&commit->cleanup_done) : true;
 776                 spin_unlock(&crtc->commit_lock);
 777
 778                 if (cleanup_done)
 779                         continue;
 780
 781                 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc));
 782
 783                 return true;
 784         }
 785
 786         return false;
 787 }
 788
 789 /*
 790  * Finds the encoder associated with the given CRTC. This can only be
 791  * used when we know that the CRTC isn't feeding multiple encoders!
 792  */
 793 struct intel_encoder *
 794 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
 795                            const struct intel_crtc_state *crtc_state)
 796 {
 797         const struct drm_connector_state *connector_state;
 798         const struct drm_connector *connector;
 799         struct intel_encoder *encoder = NULL;
 800         struct intel_crtc *master_crtc;
 801         int num_encoders = 0;
 802         int i;
 803
 804         master_crtc = intel_master_crtc(crtc_state);
 805
 806         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
 807                 if (connector_state->crtc != &master_crtc->base)
 808                         continue;
 809
 810                 encoder = to_intel_encoder(connector_state->best_encoder);
 811                 num_encoders++;
 812         }
 813
 814         drm_WARN(state->base.dev, num_encoders != 1,
 815                  "%d encoders for pipe %c\n",
 816                  num_encoders, pipe_name(master_crtc->pipe));
 817
 818         return encoder;
 819 }
 820
 821 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
 822 {
 823         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 824         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 825         const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
 826         enum pipe pipe = crtc->pipe;
 827         int width = drm_rect_width(dst);
 828         int height = drm_rect_height(dst);
 829         int x = dst->x1;
 830         int y = dst->y1;
 831
 832         if (!crtc_state->pch_pfit.enabled)
 833                 return;
 834
 835         /* Force use of hard-coded filter coefficients
 836          * as some pre-programmed values are broken,
 837          * e.g. x201.
 838          */
 839         if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
 840                 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
 841                                   PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
 842         else
 843                 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
 844                                   PF_FILTER_MED_3x3);
 845         intel_de_write_fw(dev_priv, PF_WIN_POS(pipe),
 846                           PF_WIN_XPOS(x) | PF_WIN_YPOS(y));
 847         intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe),
 848                           PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height));
 849 }
 850
 851 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
 852 {
 853         if (crtc->overlay)
 854                 (void) intel_overlay_switch_off(crtc->overlay);
 855
 856         /* Let userspace switch the overlay on again. In most cases userspace
 857          * has to recompute where to put it anyway.
 858          */
 859 }
 860
 861 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
 862 {
 863         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 864
 865         if (!crtc_state->nv12_planes)
 866                 return false;
 867
 868         /* WA Display #0827: Gen9:all */
 869         if (DISPLAY_VER(dev_priv) == 9)
 870                 return true;
 871
 872         return false;
 873 }
 874
 875 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
 876 {
 877         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 878
 879         /* Wa_2006604312:icl,ehl */
 880         if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
 881                 return true;
 882
 883         return false;
 884 }
 885
 886 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
 887 {
 888         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 889
 890         /* Wa_1604331009:icl,jsl,ehl */
 891         if (is_hdr_mode(crtc_state) &&
 892             crtc_state->active_planes & BIT(PLANE_CURSOR) &&
 893             DISPLAY_VER(dev_priv) == 11)
 894                 return true;
 895
 896         return false;
 897 }
 898
 899 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915,
 900                                     enum pipe pipe, bool enable)
 901 {
 902         if (DISPLAY_VER(i915) == 9) {
 903                 /*
 904                  * "Plane N strech max must be programmed to 11b (x1)
 905                  *  when Async flips are enabled on that plane."
 906                  */
 907                 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
 908                              SKL_PLANE1_STRETCH_MAX_MASK,
 909                              enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8);
 910         } else {
 911                 /* Also needed on HSW/BDW albeit undocumented */
 912                 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
 913                              HSW_PRI_STRETCH_MAX_MASK,
 914                              enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8);
 915         }
 916 }
 917
 918 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state)
 919 {
 920         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 921
 922         return crtc_state->uapi.async_flip && i915_vtd_active(i915) &&
 923                 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915));
 924 }
 925
 926 static void intel_encoders_audio_enable(struct intel_atomic_state *state,
 927                                         struct intel_crtc *crtc)
 928 {
 929         const struct intel_crtc_state *crtc_state =
 930                 intel_atomic_get_new_crtc_state(state, crtc);
 931         const struct drm_connector_state *conn_state;
 932         struct drm_connector *conn;
 933         int i;
 934
 935         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
 936                 struct intel_encoder *encoder =
 937                         to_intel_encoder(conn_state->best_encoder);
 938
 939                 if (conn_state->crtc != &crtc->base)
 940                         continue;
 941
 942                 if (encoder->audio_enable)
 943                         encoder->audio_enable(encoder, crtc_state, conn_state);
 944         }
 945 }
 946
 947 static void intel_encoders_audio_disable(struct intel_atomic_state *state,
 948                                          struct intel_crtc *crtc)
 949 {
 950         const struct intel_crtc_state *old_crtc_state =
 951                 intel_atomic_get_old_crtc_state(state, crtc);
 952         const struct drm_connector_state *old_conn_state;
 953         struct drm_connector *conn;
 954         int i;
 955
 956         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
 957                 struct intel_encoder *encoder =
 958                         to_intel_encoder(old_conn_state->best_encoder);
 959
 960                 if (old_conn_state->crtc != &crtc->base)
 961                         continue;
 962
 963                 if (encoder->audio_disable)
 964                         encoder->audio_disable(encoder, old_crtc_state, old_conn_state);
 965         }
 966 }
 967
 968 #define is_enabling(feature, old_crtc_state, new_crtc_state) \
 969         ((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
 970          (new_crtc_state)->feature)
 971 #define is_disabling(feature, old_crtc_state, new_crtc_state) \
 972         ((old_crtc_state)->feature && \
 973          (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))
 974
 975 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
 976                             const struct intel_crtc_state *new_crtc_state)
 977 {
 978         if (!new_crtc_state->hw.active)
 979                 return false;
 980
 981         return is_enabling(active_planes, old_crtc_state, new_crtc_state);
 982 }
 983
 984 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
 985                              const struct intel_crtc_state *new_crtc_state)
 986 {
 987         if (!old_crtc_state->hw.active)
 988                 return false;
 989
 990         return is_disabling(active_planes, old_crtc_state, new_crtc_state);
 991 }
 992
 993 static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
 994                                const struct intel_crtc_state *new_crtc_state)
 995 {
 996         return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline ||
 997                 old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||
 998                 old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||
 999                 old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||
1000                 old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
1001 }
1002
1003 static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
1004                          const struct intel_crtc_state *new_crtc_state)
1005 {
1006         if (!new_crtc_state->hw.active)
1007                 return false;
1008
1009         return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
1010                 (new_crtc_state->vrr.enable &&
1011                  (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
1012                   vrr_params_changed(old_crtc_state, new_crtc_state)));
1013 }
1014
1015 static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
1016                           const struct intel_crtc_state *new_crtc_state)
1017 {
1018         if (!old_crtc_state->hw.active)
1019                 return false;
1020
1021         return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
1022                 (old_crtc_state->vrr.enable &&
1023                  (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
1024                   vrr_params_changed(old_crtc_state, new_crtc_state)));
1025 }
1026
1027 static bool audio_enabling(const struct intel_crtc_state *old_crtc_state,
1028                            const struct intel_crtc_state *new_crtc_state)
1029 {
1030         if (!new_crtc_state->hw.active)
1031                 return false;
1032
1033         return is_enabling(has_audio, old_crtc_state, new_crtc_state) ||
1034                 (new_crtc_state->has_audio &&
1035                  memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);
1036 }
1037
1038 static bool audio_disabling(const struct intel_crtc_state *old_crtc_state,
1039                             const struct intel_crtc_state *new_crtc_state)
1040 {
1041         if (!old_crtc_state->hw.active)
1042                 return false;
1043
1044         return is_disabling(has_audio, old_crtc_state, new_crtc_state) ||
1045                 (old_crtc_state->has_audio &&
1046                  memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);
1047 }
1048
1049 #undef is_disabling
1050 #undef is_enabling
1051
1052 static void intel_post_plane_update(struct intel_atomic_state *state,
1053                                     struct intel_crtc *crtc)
1054 {
1055         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1056         const struct intel_crtc_state *old_crtc_state =
1057                 intel_atomic_get_old_crtc_state(state, crtc);
1058         const struct intel_crtc_state *new_crtc_state =
1059                 intel_atomic_get_new_crtc_state(state, crtc);
1060         enum pipe pipe = crtc->pipe;
1061
1062         intel_psr_post_plane_update(state, crtc);
1063
1064         intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
1065
1066         if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
1067                 intel_update_watermarks(dev_priv);
1068
1069         intel_fbc_post_update(state, crtc);
1070
1071         if (needs_async_flip_vtd_wa(old_crtc_state) &&
1072             !needs_async_flip_vtd_wa(new_crtc_state))
1073                 intel_async_flip_vtd_wa(dev_priv, pipe, false);
1074
1075         if (needs_nv12_wa(old_crtc_state) &&
1076             !needs_nv12_wa(new_crtc_state))
1077                 skl_wa_827(dev_priv, pipe, false);
1078
1079         if (needs_scalerclk_wa(old_crtc_state) &&
1080             !needs_scalerclk_wa(new_crtc_state))
1081                 icl_wa_scalerclkgating(dev_priv, pipe, false);
1082
1083         if (needs_cursorclk_wa(old_crtc_state) &&
1084             !needs_cursorclk_wa(new_crtc_state))
1085                 icl_wa_cursorclkgating(dev_priv, pipe, false);
1086
1087         if (intel_crtc_needs_color_update(new_crtc_state))
1088                 intel_color_post_update(new_crtc_state);
1089
1090         if (audio_enabling(old_crtc_state, new_crtc_state))
1091                 intel_encoders_audio_enable(state, crtc);
1092 }
1093
1094 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
1095                                         struct intel_crtc *crtc)
1096 {
1097         const struct intel_crtc_state *crtc_state =
1098                 intel_atomic_get_new_crtc_state(state, crtc);
1099         u8 update_planes = crtc_state->update_planes;
1100         const struct intel_plane_state __maybe_unused *plane_state;
1101         struct intel_plane *plane;
1102         int i;
1103
1104         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1105                 if (plane->pipe == crtc->pipe &&
1106                     update_planes & BIT(plane->id))
1107                         plane->enable_flip_done(plane);
1108         }
1109 }
1110
1111 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
1112                                          struct intel_crtc *crtc)
1113 {
1114         const struct intel_crtc_state *crtc_state =
1115                 intel_atomic_get_new_crtc_state(state, crtc);
1116         u8 update_planes = crtc_state->update_planes;
1117         const struct intel_plane_state __maybe_unused *plane_state;
1118         struct intel_plane *plane;
1119         int i;
1120
1121         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1122                 if (plane->pipe == crtc->pipe &&
1123                     update_planes & BIT(plane->id))
1124                         plane->disable_flip_done(plane);
1125         }
1126 }
1127
1128 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
1129                                              struct intel_crtc *crtc)
1130 {
1131         const struct intel_crtc_state *old_crtc_state =
1132                 intel_atomic_get_old_crtc_state(state, crtc);
1133         const struct intel_crtc_state *new_crtc_state =
1134                 intel_atomic_get_new_crtc_state(state, crtc);
1135         u8 disable_async_flip_planes = old_crtc_state->async_flip_planes &
1136                                        ~new_crtc_state->async_flip_planes;
1137         const struct intel_plane_state *old_plane_state;
1138         struct intel_plane *plane;
1139         bool need_vbl_wait = false;
1140         int i;
1141
1142         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1143                 if (plane->need_async_flip_disable_wa &&
1144                     plane->pipe == crtc->pipe &&
1145                     disable_async_flip_planes & BIT(plane->id)) {
1146                         /*
1147                          * Apart from the async flip bit we want to
1148                          * preserve the old state for the plane.
1149                          */
1150                         plane->async_flip(plane, old_crtc_state,
1151                                           old_plane_state, false);
1152                         need_vbl_wait = true;
1153                 }
1154         }
1155
1156         if (need_vbl_wait)
1157                 intel_crtc_wait_for_next_vblank(crtc);
1158 }
1159
1160 static void intel_pre_plane_update(struct intel_atomic_state *state,
1161                                    struct intel_crtc *crtc)
1162 {
1163         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1164         const struct intel_crtc_state *old_crtc_state =
1165                 intel_atomic_get_old_crtc_state(state, crtc);
1166         const struct intel_crtc_state *new_crtc_state =
1167                 intel_atomic_get_new_crtc_state(state, crtc);
1168         enum pipe pipe = crtc->pipe;
1169
1170         if (vrr_disabling(old_crtc_state, new_crtc_state)) {
1171                 intel_vrr_disable(old_crtc_state);
1172                 intel_crtc_update_active_timings(old_crtc_state, false);
1173         }
1174
1175         if (audio_disabling(old_crtc_state, new_crtc_state))
1176                 intel_encoders_audio_disable(state, crtc);
1177
1178         intel_drrs_deactivate(old_crtc_state);
1179
1180         intel_psr_pre_plane_update(state, crtc);
1181
1182         if (hsw_ips_pre_update(state, crtc))
1183                 intel_crtc_wait_for_next_vblank(crtc);
1184
1185         if (intel_fbc_pre_update(state, crtc))
1186                 intel_crtc_wait_for_next_vblank(crtc);
1187
1188         if (!needs_async_flip_vtd_wa(old_crtc_state) &&
1189             needs_async_flip_vtd_wa(new_crtc_state))
1190                 intel_async_flip_vtd_wa(dev_priv, pipe, true);
1191
1192         /* Display WA 827 */
1193         if (!needs_nv12_wa(old_crtc_state) &&
1194             needs_nv12_wa(new_crtc_state))
1195                 skl_wa_827(dev_priv, pipe, true);
1196
1197         /* Wa_2006604312:icl,ehl */
1198         if (!needs_scalerclk_wa(old_crtc_state) &&
1199             needs_scalerclk_wa(new_crtc_state))
1200                 icl_wa_scalerclkgating(dev_priv, pipe, true);
1201
1202         /* Wa_1604331009:icl,jsl,ehl */
1203         if (!needs_cursorclk_wa(old_crtc_state) &&
1204             needs_cursorclk_wa(new_crtc_state))
1205                 icl_wa_cursorclkgating(dev_priv, pipe, true);
1206
1207         /*
1208          * Vblank time updates from the shadow to live plane control register
1209          * are blocked if the memory self-refresh mode is active at that
1210          * moment. So to make sure the plane gets truly disabled, disable
1211          * first the self-refresh mode. The self-refresh enable bit in turn
1212          * will be checked/applied by the HW only at the next frame start
1213          * event which is after the vblank start event, so we need to have a
1214          * wait-for-vblank between disabling the plane and the pipe.
1215          */
1216         if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
1217             new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
1218                 intel_crtc_wait_for_next_vblank(crtc);
1219
1220         /*
1221          * IVB workaround: must disable low power watermarks for at least
1222          * one frame before enabling scaling.  LP watermarks can be re-enabled
1223          * when scaling is disabled.
1224          *
1225          * WaCxSRDisabledForSpriteScaling:ivb
1226          */
1227         if (old_crtc_state->hw.active &&
1228             new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
1229                 intel_crtc_wait_for_next_vblank(crtc);
1230
1231         /*
1232          * If we're doing a modeset we don't need to do any
1233          * pre-vblank watermark programming here.
1234          */
1235         if (!intel_crtc_needs_modeset(new_crtc_state)) {
1236                 /*
1237                  * For platforms that support atomic watermarks, program the
1238                  * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
1239                  * will be the intermediate values that are safe for both pre- and
1240                  * post- vblank; when vblank happens, the 'active' values will be set
1241                  * to the final 'target' values and we'll do this again to get the
1242                  * optimal watermarks.  For gen9+ platforms, the values we program here
1243                  * will be the final target values which will get automatically latched
1244                  * at vblank time; no further programming will be necessary.
1245                  *
1246                  * If a platform hasn't been transitioned to atomic watermarks yet,
1247                  * we'll continue to update watermarks the old way, if flags tell
1248                  * us to.
1249                  */
1250                 if (!intel_initial_watermarks(state, crtc))
1251                         if (new_crtc_state->update_wm_pre)
1252                                 intel_update_watermarks(dev_priv);
1253         }
1254
1255         /*
1256          * Gen2 reports pipe underruns whenever all planes are disabled.
1257          * So disable underrun reporting before all the planes get disabled.
1258          *
1259          * We do this after .initial_watermarks() so that we have a
1260          * chance of catching underruns with the intermediate watermarks
1261          * vs. the old plane configuration.
1262          */
1263         if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
1264                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1265
1266         /*
1267          * WA for platforms where async address update enable bit
1268          * is double buffered and only latched at start of vblank.
1269          */
1270         if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes)
1271                 intel_crtc_async_flip_disable_wa(state, crtc);
1272 }
1273
1274 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
1275                                       struct intel_crtc *crtc)
1276 {
1277         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1278         const struct intel_crtc_state *new_crtc_state =
1279                 intel_atomic_get_new_crtc_state(state, crtc);
1280         unsigned int update_mask = new_crtc_state->update_planes;
1281         const struct intel_plane_state *old_plane_state;
1282         struct intel_plane *plane;
1283         unsigned fb_bits = 0;
1284         int i;
1285
1286         intel_crtc_dpms_overlay_disable(crtc);
1287
1288         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1289                 if (crtc->pipe != plane->pipe ||
1290                     !(update_mask & BIT(plane->id)))
1291                         continue;
1292
1293                 intel_plane_disable_arm(plane, new_crtc_state);
1294
1295                 if (old_plane_state->uapi.visible)
1296                         fb_bits |= plane->frontbuffer_bit;
1297         }
1298
1299         intel_frontbuffer_flip(dev_priv, fb_bits);
1300 }
1301
1302 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
1303 {
1304         struct drm_i915_private *i915 = to_i915(state->base.dev);
1305         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
1306         struct intel_crtc *crtc;
1307         int i;
1308
1309         /*
1310          * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
1311          * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
1312          */
1313         if (i915->display.dpll.mgr) {
1314                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1315                         if (intel_crtc_needs_modeset(new_crtc_state))
1316                                 continue;
1317
1318                         new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;
1319                         new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
1320                 }
1321         }
1322 }
1323
1324 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
1325                                           struct intel_crtc *crtc)
1326 {
1327         const struct intel_crtc_state *crtc_state =
1328                 intel_atomic_get_new_crtc_state(state, crtc);
1329         const struct drm_connector_state *conn_state;
1330         struct drm_connector *conn;
1331         int i;
1332
1333         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1334                 struct intel_encoder *encoder =
1335                         to_intel_encoder(conn_state->best_encoder);
1336
1337                 if (conn_state->crtc != &crtc->base)
1338                         continue;
1339
1340                 if (encoder->pre_pll_enable)
1341                         encoder->pre_pll_enable(state, encoder,
1342                                                 crtc_state, conn_state);
1343         }
1344 }
1345
1346 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
1347                                       struct intel_crtc *crtc)
1348 {
1349         const struct intel_crtc_state *crtc_state =
1350                 intel_atomic_get_new_crtc_state(state, crtc);
1351         const struct drm_connector_state *conn_state;
1352         struct drm_connector *conn;
1353         int i;
1354
1355         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1356                 struct intel_encoder *encoder =
1357                         to_intel_encoder(conn_state->best_encoder);
1358
1359                 if (conn_state->crtc != &crtc->base)
1360                         continue;
1361
1362                 if (encoder->pre_enable)
1363                         encoder->pre_enable(state, encoder,
1364                                             crtc_state, conn_state);
1365         }
1366 }
1367
1368 static void intel_encoders_enable(struct intel_atomic_state *state,
1369                                   struct intel_crtc *crtc)
1370 {
1371         const struct intel_crtc_state *crtc_state =
1372                 intel_atomic_get_new_crtc_state(state, crtc);
1373         const struct drm_connector_state *conn_state;
1374         struct drm_connector *conn;
1375         int i;
1376
1377         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1378                 struct intel_encoder *encoder =
1379                         to_intel_encoder(conn_state->best_encoder);
1380
1381                 if (conn_state->crtc != &crtc->base)
1382                         continue;
1383
1384                 if (encoder->enable)
1385                         encoder->enable(state, encoder,
1386                                         crtc_state, conn_state);
1387                 intel_opregion_notify_encoder(encoder, true);
1388         }
1389 }
1390
1391 static void intel_encoders_disable(struct intel_atomic_state *state,
1392                                    struct intel_crtc *crtc)
1393 {
1394         const struct intel_crtc_state *old_crtc_state =
1395                 intel_atomic_get_old_crtc_state(state, crtc);
1396         const struct drm_connector_state *old_conn_state;
1397         struct drm_connector *conn;
1398         int i;
1399
1400         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1401                 struct intel_encoder *encoder =
1402                         to_intel_encoder(old_conn_state->best_encoder);
1403
1404                 if (old_conn_state->crtc != &crtc->base)
1405                         continue;
1406
1407                 intel_opregion_notify_encoder(encoder, false);
1408                 if (encoder->disable)
1409                         encoder->disable(state, encoder,
1410                                          old_crtc_state, old_conn_state);
1411         }
1412 }
1413
1414 static void intel_encoders_post_disable(struct intel_atomic_state *state,
1415                                         struct intel_crtc *crtc)
1416 {
1417         const struct intel_crtc_state *old_crtc_state =
1418                 intel_atomic_get_old_crtc_state(state, crtc);
1419         const struct drm_connector_state *old_conn_state;
1420         struct drm_connector *conn;
1421         int i;
1422
1423         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1424                 struct intel_encoder *encoder =
1425                         to_intel_encoder(old_conn_state->best_encoder);
1426
1427                 if (old_conn_state->crtc != &crtc->base)
1428                         continue;
1429
1430                 if (encoder->post_disable)
1431                         encoder->post_disable(state, encoder,
1432                                               old_crtc_state, old_conn_state);
1433         }
1434 }
1435
1436 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
1437                                             struct intel_crtc *crtc)
1438 {
1439         const struct intel_crtc_state *old_crtc_state =
1440                 intel_atomic_get_old_crtc_state(state, crtc);
1441         const struct drm_connector_state *old_conn_state;
1442         struct drm_connector *conn;
1443         int i;
1444
1445         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1446                 struct intel_encoder *encoder =
1447                         to_intel_encoder(old_conn_state->best_encoder);
1448
1449                 if (old_conn_state->crtc != &crtc->base)
1450                         continue;
1451
1452                 if (encoder->post_pll_disable)
1453                         encoder->post_pll_disable(state, encoder,
1454                                                   old_crtc_state, old_conn_state);
1455         }
1456 }
1457
1458 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
1459                                        struct intel_crtc *crtc)
1460 {
1461         const struct intel_crtc_state *crtc_state =
1462                 intel_atomic_get_new_crtc_state(state, crtc);
1463         const struct drm_connector_state *conn_state;
1464         struct drm_connector *conn;
1465         int i;
1466
1467         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1468                 struct intel_encoder *encoder =
1469                         to_intel_encoder(conn_state->best_encoder);
1470
1471                 if (conn_state->crtc != &crtc->base)
1472                         continue;
1473
1474                 if (encoder->update_pipe)
1475                         encoder->update_pipe(state, encoder,
1476                                              crtc_state, conn_state);
1477         }
1478 }
1479
1480 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
1481 {
1482         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1483         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1484
1485         plane->disable_arm(plane, crtc_state);
1486 }
1487
1488 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1489 {
1490         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1491         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1492
1493         if (crtc_state->has_pch_encoder) {
1494                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1495                                                &crtc_state->fdi_m_n);
1496         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1497                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1498                                                &crtc_state->dp_m_n);
1499                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1500                                                &crtc_state->dp_m2_n2);
1501         }
1502
1503         intel_set_transcoder_timings(crtc_state);
1504
1505         ilk_set_pipeconf(crtc_state);
1506 }
1507
1508 static void ilk_crtc_enable(struct intel_atomic_state *state,
1509                             struct intel_crtc *crtc)
1510 {
1511         const struct intel_crtc_state *new_crtc_state =
1512                 intel_atomic_get_new_crtc_state(state, crtc);
1513         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1514         enum pipe pipe = crtc->pipe;
1515
1516         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1517                 return;
1518
1519         /*
1520          * Sometimes spurious CPU pipe underruns happen during FDI
1521          * training, at least with VGA+HDMI cloning. Suppress them.
1522          *
1523          * On ILK we get an occasional spurious CPU pipe underruns
1524          * between eDP port A enable and vdd enable. Also PCH port
1525          * enable seems to result in the occasional CPU pipe underrun.
1526          *
1527          * Spurious PCH underruns also occur during PCH enabling.
1528          */
1529         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1530         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1531
1532         ilk_configure_cpu_transcoder(new_crtc_state);
1533
1534         intel_set_pipe_src_size(new_crtc_state);
1535
1536         crtc->active = true;
1537
1538         intel_encoders_pre_enable(state, crtc);
1539
1540         if (new_crtc_state->has_pch_encoder) {
1541                 ilk_pch_pre_enable(state, crtc);
1542         } else {
1543                 assert_fdi_tx_disabled(dev_priv, pipe);
1544                 assert_fdi_rx_disabled(dev_priv, pipe);
1545         }
1546
1547         ilk_pfit_enable(new_crtc_state);
1548
1549         /*
1550          * On ILK+ LUT must be loaded before the pipe is running but with
1551          * clocks enabled
1552          */
1553         intel_color_load_luts(new_crtc_state);
1554         intel_color_commit_noarm(new_crtc_state);
1555         intel_color_commit_arm(new_crtc_state);
1556         /* update DSPCNTR to configure gamma for pipe bottom color */
1557         intel_disable_primary_plane(new_crtc_state);
1558
1559         intel_initial_watermarks(state, crtc);
1560         intel_enable_transcoder(new_crtc_state);
1561
1562         if (new_crtc_state->has_pch_encoder)
1563                 ilk_pch_enable(state, crtc);
1564
1565         intel_crtc_vblank_on(new_crtc_state);
1566
1567         intel_encoders_enable(state, crtc);
1568
1569         if (HAS_PCH_CPT(dev_priv))
1570                 intel_wait_for_pipe_scanline_moving(crtc);
1571
1572         /*
1573          * Must wait for vblank to avoid spurious PCH FIFO underruns.
1574          * And a second vblank wait is needed at least on ILK with
1575          * some interlaced HDMI modes. Let's do the double wait always
1576          * in case there are more corner cases we don't know about.
1577          */
1578         if (new_crtc_state->has_pch_encoder) {
1579                 intel_crtc_wait_for_next_vblank(crtc);
1580                 intel_crtc_wait_for_next_vblank(crtc);
1581         }
1582         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1583         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1584 }
1585
1586 /* Display WA #1180: WaDisableScalarClockGating: glk */
1587 static bool glk_need_scaler_clock_gating_wa(const struct intel_crtc_state *crtc_state)
1588 {
1589         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1590
1591         return DISPLAY_VER(i915) == 10 && crtc_state->pch_pfit.enabled;
1592 }
1593
1594 static void glk_pipe_scaler_clock_gating_wa(struct intel_crtc *crtc, bool enable)
1595 {
1596         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1597         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
1598
1599         intel_de_rmw(i915, CLKGATE_DIS_PSL(crtc->pipe),
1600                      mask, enable ? mask : 0);
1601 }
1602
1603 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
1604 {
1605         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1606         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1607
1608         intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
1609                        HSW_LINETIME(crtc_state->linetime) |
1610                        HSW_IPS_LINETIME(crtc_state->ips_linetime));
1611 }
1612
1613 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
1614 {
1615         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1616         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1617
1618         intel_de_rmw(i915, hsw_chicken_trans_reg(i915, crtc_state->cpu_transcoder),
1619                      HSW_FRAME_START_DELAY_MASK,
1620                      HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));
1621 }
1622
1623 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1624 {
1625         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1626         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1627         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1628
1629         if (crtc_state->has_pch_encoder) {
1630                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1631                                                &crtc_state->fdi_m_n);
1632         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1633                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1634                                                &crtc_state->dp_m_n);
1635                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1636                                                &crtc_state->dp_m2_n2);
1637         }
1638
1639         intel_set_transcoder_timings(crtc_state);
1640         if (HAS_VRR(dev_priv))
1641                 intel_vrr_set_transcoder_timings(crtc_state);
1642
1643         if (cpu_transcoder != TRANSCODER_EDP)
1644                 intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder),
1645                                crtc_state->pixel_multiplier - 1);
1646
1647         hsw_set_frame_start_delay(crtc_state);
1648
1649         hsw_set_transconf(crtc_state);
1650 }
1651
1652 static void hsw_crtc_enable(struct intel_atomic_state *state,
1653                             struct intel_crtc *crtc)
1654 {
1655         const struct intel_crtc_state *new_crtc_state =
1656                 intel_atomic_get_new_crtc_state(state, crtc);
1657         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1658         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1659         struct intel_crtc *pipe_crtc;
1660
1661         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1662                 return;
1663
1664         for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
1665                                                  intel_crtc_joined_pipe_mask(new_crtc_state))
1666                 intel_dmc_enable_pipe(dev_priv, pipe_crtc->pipe);
1667
1668         intel_encoders_pre_pll_enable(state, crtc);
1669
1670         for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
1671                                                  intel_crtc_joined_pipe_mask(new_crtc_state)) {
1672                 const struct intel_crtc_state *pipe_crtc_state =
1673                         intel_atomic_get_new_crtc_state(state, pipe_crtc);
1674
1675                 if (pipe_crtc_state->shared_dpll)
1676                         intel_enable_shared_dpll(pipe_crtc_state);
1677         }
1678
1679         intel_encoders_pre_enable(state, crtc);
1680
1681         for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
1682                                                  intel_crtc_joined_pipe_mask(new_crtc_state)) {
1683                 const struct intel_crtc_state *pipe_crtc_state =
1684                         intel_atomic_get_new_crtc_state(state, pipe_crtc);
1685
1686                 intel_dsc_enable(pipe_crtc_state);
1687
1688                 if (DISPLAY_VER(dev_priv) >= 13)
1689                         intel_uncompressed_joiner_enable(pipe_crtc_state);
1690
1691                 intel_set_pipe_src_size(pipe_crtc_state);
1692
1693                 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
1694                         bdw_set_pipe_misc(pipe_crtc_state);
1695         }
1696
1697         if (!transcoder_is_dsi(cpu_transcoder))
1698                 hsw_configure_cpu_transcoder(new_crtc_state);
1699
1700         for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
1701                                                  intel_crtc_joined_pipe_mask(new_crtc_state)) {
1702                 const struct intel_crtc_state *pipe_crtc_state =
1703                         intel_atomic_get_new_crtc_state(state, pipe_crtc);
1704
1705                 pipe_crtc->active = true;
1706
1707                 if (glk_need_scaler_clock_gating_wa(pipe_crtc_state))
1708                         glk_pipe_scaler_clock_gating_wa(pipe_crtc, true);
1709
1710                 if (DISPLAY_VER(dev_priv) >= 9)
1711                         skl_pfit_enable(pipe_crtc_state);
1712                 else
1713                         ilk_pfit_enable(pipe_crtc_state);
1714
1715                 /*
1716                  * On ILK+ LUT must be loaded before the pipe is running but with
1717                  * clocks enabled
1718                  */
1719                 intel_color_load_luts(pipe_crtc_state);
1720                 intel_color_commit_noarm(pipe_crtc_state);
1721                 intel_color_commit_arm(pipe_crtc_state);
1722                 /* update DSPCNTR to configure gamma/csc for pipe bottom color */
1723                 if (DISPLAY_VER(dev_priv) < 9)
1724                         intel_disable_primary_plane(pipe_crtc_state);
1725
1726                 hsw_set_linetime_wm(pipe_crtc_state);
1727
1728                 if (DISPLAY_VER(dev_priv) >= 11)
1729                         icl_set_pipe_chicken(pipe_crtc_state);
1730
1731                 intel_initial_watermarks(state, pipe_crtc);
1732         }
1733
1734         intel_encoders_enable(state, crtc);
1735
1736         for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
1737                                                  intel_crtc_joined_pipe_mask(new_crtc_state)) {
1738                 const struct intel_crtc_state *pipe_crtc_state =
1739                         intel_atomic_get_new_crtc_state(state, pipe_crtc);
1740                 enum pipe hsw_workaround_pipe;
1741
1742                 if (glk_need_scaler_clock_gating_wa(pipe_crtc_state)) {
1743                         intel_crtc_wait_for_next_vblank(pipe_crtc);
1744                         glk_pipe_scaler_clock_gating_wa(pipe_crtc, false);
1745                 }
1746
1747                 /*
1748                  * If we change the relative order between pipe/planes
1749                  * enabling, we need to change the workaround.
1750                  */
1751                 hsw_workaround_pipe = pipe_crtc_state->hsw_workaround_pipe;
1752                 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
1753                         struct intel_crtc *wa_crtc =
1754                                 intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe);
1755
1756                         intel_crtc_wait_for_next_vblank(wa_crtc);
1757                         intel_crtc_wait_for_next_vblank(wa_crtc);
1758                 }
1759         }
1760 }
1761
1762 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
1763 {
1764         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1765         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1766         enum pipe pipe = crtc->pipe;
1767
1768         /* To avoid upsetting the power well on haswell only disable the pfit if
1769          * it's in use. The hw state code will make sure we get this right. */
1770         if (!old_crtc_state->pch_pfit.enabled)
1771                 return;
1772
1773         intel_de_write_fw(dev_priv, PF_CTL(pipe), 0);
1774         intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0);
1775         intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0);
1776 }
1777
1778 static void ilk_crtc_disable(struct intel_atomic_state *state,
1779                              struct intel_crtc *crtc)
1780 {
1781         const struct intel_crtc_state *old_crtc_state =
1782                 intel_atomic_get_old_crtc_state(state, crtc);
1783         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1784         enum pipe pipe = crtc->pipe;
1785
1786         /*
1787          * Sometimes spurious CPU pipe underruns happen when the
1788          * pipe is already disabled, but FDI RX/TX is still enabled.
1789          * Happens at least with VGA+HDMI cloning. Suppress them.
1790          */
1791         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1792         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1793
1794         intel_encoders_disable(state, crtc);
1795
1796         intel_crtc_vblank_off(old_crtc_state);
1797
1798         intel_disable_transcoder(old_crtc_state);
1799
1800         ilk_pfit_disable(old_crtc_state);
1801
1802         if (old_crtc_state->has_pch_encoder)
1803                 ilk_pch_disable(state, crtc);
1804
1805         intel_encoders_post_disable(state, crtc);
1806
1807         if (old_crtc_state->has_pch_encoder)
1808                 ilk_pch_post_disable(state, crtc);
1809
1810         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1811         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1812
1813         intel_disable_shared_dpll(old_crtc_state);
1814 }
1815
1816 static void hsw_crtc_disable(struct intel_atomic_state *state,
1817                              struct intel_crtc *crtc)
1818 {
1819         const struct intel_crtc_state *old_crtc_state =
1820                 intel_atomic_get_old_crtc_state(state, crtc);
1821         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1822         struct intel_crtc *pipe_crtc;
1823
1824         /*
1825          * FIXME collapse everything to one hook.
1826          * Need care with mst->ddi interactions.
1827          */
1828         intel_encoders_disable(state, crtc);
1829         intel_encoders_post_disable(state, crtc);
1830
1831         for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc,
1832                                          intel_crtc_joined_pipe_mask(old_crtc_state)) {
1833                 const struct intel_crtc_state *old_pipe_crtc_state =
1834                         intel_atomic_get_old_crtc_state(state, pipe_crtc);
1835
1836                 intel_disable_shared_dpll(old_pipe_crtc_state);
1837         }
1838
1839         intel_encoders_post_pll_disable(state, crtc);
1840
1841         for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc,
1842                                          intel_crtc_joined_pipe_mask(old_crtc_state))
1843                 intel_dmc_disable_pipe(i915, pipe_crtc->pipe);
1844 }
1845
1846 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
1847 {
1848         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1849         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1850
1851         if (!crtc_state->gmch_pfit.control)
1852                 return;
1853
1854         /*
1855          * The panel fitter should only be adjusted whilst the pipe is disabled,
1856          * according to register description and PRM.
1857          */
1858         drm_WARN_ON(&dev_priv->drm,
1859                     intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
1860         assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1861
1862         intel_de_write(dev_priv, PFIT_PGM_RATIOS,
1863                        crtc_state->gmch_pfit.pgm_ratios);
1864         intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
1865
1866         /* Border color in case we don't scale up to the full screen. Black by
1867          * default, change to something else for debugging. */
1868         intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
1869 }
1870
1871 /* Prefer intel_encoder_is_combo() */
1872 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
1873 {
1874         if (phy == PHY_NONE)
1875                 return false;
1876         else if (IS_ALDERLAKE_S(dev_priv))
1877                 return phy <= PHY_E;
1878         else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
1879                 return phy <= PHY_D;
1880         else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
1881                 return phy <= PHY_C;
1882         else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
1883                 return phy <= PHY_B;
1884         else
1885                 /*
1886                  * DG2 outputs labelled as "combo PHY" in the bspec use
1887                  * SNPS PHYs with completely different programming,
1888                  * hence we always return false here.
1889                  */
1890                 return false;
1891 }
1892
1893 /* Prefer intel_encoder_is_tc() */
1894 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
1895 {
1896         /*
1897          * DG2's "TC1", although TC-capable output, doesn't share the same flow
1898          * as other platforms on the display engine side and rather rely on the
1899          * SNPS PHY, that is programmed separately
1900          */
1901         if (IS_DG2(dev_priv))
1902                 return false;
1903
1904         if (DISPLAY_VER(dev_priv) >= 13)
1905                 return phy >= PHY_F && phy <= PHY_I;
1906         else if (IS_TIGERLAKE(dev_priv))
1907                 return phy >= PHY_D && phy <= PHY_I;
1908         else if (IS_ICELAKE(dev_priv))
1909                 return phy >= PHY_C && phy <= PHY_F;
1910
1911         return false;
1912 }
1913
1914 /* Prefer intel_encoder_is_snps() */
1915 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
1916 {
1917         /*
1918          * For DG2, and for DG2 only, all four "combo" ports and the TC1 port
1919          * (PHY E) use Synopsis PHYs. See intel_phy_is_tc().
1920          */
1921         return IS_DG2(dev_priv) && phy > PHY_NONE && phy <= PHY_E;
1922 }
1923
1924 /* Prefer intel_encoder_to_phy() */
1925 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
1926 {
1927         if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
1928                 return PHY_D + port - PORT_D_XELPD;
1929         else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
1930                 return PHY_F + port - PORT_TC1;
1931         else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
1932                 return PHY_B + port - PORT_TC1;
1933         else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
1934                 return PHY_C + port - PORT_TC1;
1935         else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
1936                  port == PORT_D)
1937                 return PHY_A;
1938
1939         return PHY_A + port - PORT_A;
1940 }
1941
1942 /* Prefer intel_encoder_to_tc() */
1943 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
1944 {
1945         if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
1946                 return TC_PORT_NONE;
1947
1948         if (DISPLAY_VER(dev_priv) >= 12)
1949                 return TC_PORT_1 + port - PORT_TC1;
1950         else
1951                 return TC_PORT_1 + port - PORT_C;
1952 }
1953
1954 enum phy intel_encoder_to_phy(struct intel_encoder *encoder)
1955 {
1956         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1957
1958         return intel_port_to_phy(i915, encoder->port);
1959 }
1960
1961 bool intel_encoder_is_combo(struct intel_encoder *encoder)
1962 {
1963         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1964
1965         return intel_phy_is_combo(i915, intel_encoder_to_phy(encoder));
1966 }
1967
1968 bool intel_encoder_is_snps(struct intel_encoder *encoder)
1969 {
1970         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1971
1972         return intel_phy_is_snps(i915, intel_encoder_to_phy(encoder));
1973 }
1974
1975 bool intel_encoder_is_tc(struct intel_encoder *encoder)
1976 {
1977         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1978
1979         return intel_phy_is_tc(i915, intel_encoder_to_phy(encoder));
1980 }
1981
1982 enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder)
1983 {
1984         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1985
1986         return intel_port_to_tc(i915, encoder->port);
1987 }
1988
1989 enum intel_display_power_domain
1990 intel_aux_power_domain(struct intel_digital_port *dig_port)
1991 {
1992         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1993
1994         if (intel_tc_port_in_tbt_alt_mode(dig_port))
1995                 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch);
1996
1997         return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch);
1998 }
1999
2000 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
2001                                    struct intel_power_domain_mask *mask)
2002 {
2003         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2004         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2005         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2006         struct drm_encoder *encoder;
2007         enum pipe pipe = crtc->pipe;
2008
2009         bitmap_zero(mask->bits, POWER_DOMAIN_NUM);
2010
2011         if (!crtc_state->hw.active)
2012                 return;
2013
2014         set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
2015         set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
2016         if (crtc_state->pch_pfit.enabled ||
2017             crtc_state->pch_pfit.force_thru)
2018                 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
2019
2020         drm_for_each_encoder_mask(encoder, &dev_priv->drm,
2021                                   crtc_state->uapi.encoder_mask) {
2022                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2023
2024                 set_bit(intel_encoder->power_domain, mask->bits);
2025         }
2026
2027         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
2028                 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
2029
2030         if (crtc_state->shared_dpll)
2031                 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
2032
2033         if (crtc_state->dsc.compression_enable)
2034                 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
2035 }
2036
2037 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
2038                                           struct intel_power_domain_mask *old_domains)
2039 {
2040         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2041         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2042         enum intel_display_power_domain domain;
2043         struct intel_power_domain_mask domains, new_domains;
2044
2045         get_crtc_power_domains(crtc_state, &domains);
2046
2047         bitmap_andnot(new_domains.bits,
2048                       domains.bits,
2049                       crtc->enabled_power_domains.mask.bits,
2050                       POWER_DOMAIN_NUM);
2051         bitmap_andnot(old_domains->bits,
2052                       crtc->enabled_power_domains.mask.bits,
2053                       domains.bits,
2054                       POWER_DOMAIN_NUM);
2055
2056         for_each_power_domain(domain, &new_domains)
2057                 intel_display_power_get_in_set(dev_priv,
2058                                                &crtc->enabled_power_domains,
2059                                                domain);
2060 }
2061
2062 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
2063                                           struct intel_power_domain_mask *domains)
2064 {
2065         intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
2066                                             &crtc->enabled_power_domains,
2067                                             domains);
2068 }
2069
2070 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
2071 {
2072         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2073         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2074
2075         if (intel_crtc_has_dp_encoder(crtc_state)) {
2076                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
2077                                                &crtc_state->dp_m_n);
2078                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
2079                                                &crtc_state->dp_m2_n2);
2080         }
2081
2082         intel_set_transcoder_timings(crtc_state);
2083
2084         i9xx_set_pipeconf(crtc_state);
2085 }
2086
2087 static void valleyview_crtc_enable(struct intel_atomic_state *state,
2088                                    struct intel_crtc *crtc)
2089 {
2090         const struct intel_crtc_state *new_crtc_state =
2091                 intel_atomic_get_new_crtc_state(state, crtc);
2092         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2093         enum pipe pipe = crtc->pipe;
2094
2095         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2096                 return;
2097
2098         i9xx_configure_cpu_transcoder(new_crtc_state);
2099
2100         intel_set_pipe_src_size(new_crtc_state);
2101
2102         intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0);
2103
2104         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
2105                 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
2106                 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
2107         }
2108
2109         crtc->active = true;
2110
2111         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2112
2113         intel_encoders_pre_pll_enable(state, crtc);
2114
2115         if (IS_CHERRYVIEW(dev_priv))
2116                 chv_enable_pll(new_crtc_state);
2117         else
2118                 vlv_enable_pll(new_crtc_state);
2119
2120         intel_encoders_pre_enable(state, crtc);
2121
2122         i9xx_pfit_enable(new_crtc_state);
2123
2124         intel_color_load_luts(new_crtc_state);
2125         intel_color_commit_noarm(new_crtc_state);
2126         intel_color_commit_arm(new_crtc_state);
2127         /* update DSPCNTR to configure gamma for pipe bottom color */
2128         intel_disable_primary_plane(new_crtc_state);
2129
2130         intel_initial_watermarks(state, crtc);
2131         intel_enable_transcoder(new_crtc_state);
2132
2133         intel_crtc_vblank_on(new_crtc_state);
2134
2135         intel_encoders_enable(state, crtc);
2136 }
2137
2138 static void i9xx_crtc_enable(struct intel_atomic_state *state,
2139                              struct intel_crtc *crtc)
2140 {
2141         const struct intel_crtc_state *new_crtc_state =
2142                 intel_atomic_get_new_crtc_state(state, crtc);
2143         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2144         enum pipe pipe = crtc->pipe;
2145
2146         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2147                 return;
2148
2149         i9xx_configure_cpu_transcoder(new_crtc_state);
2150
2151         intel_set_pipe_src_size(new_crtc_state);
2152
2153         crtc->active = true;
2154
2155         if (DISPLAY_VER(dev_priv) != 2)
2156                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2157
2158         intel_encoders_pre_enable(state, crtc);
2159
2160         i9xx_enable_pll(new_crtc_state);
2161
2162         i9xx_pfit_enable(new_crtc_state);
2163
2164         intel_color_load_luts(new_crtc_state);
2165         intel_color_commit_noarm(new_crtc_state);
2166         intel_color_commit_arm(new_crtc_state);
2167         /* update DSPCNTR to configure gamma for pipe bottom color */
2168         intel_disable_primary_plane(new_crtc_state);
2169
2170         if (!intel_initial_watermarks(state, crtc))
2171                 intel_update_watermarks(dev_priv);
2172         intel_enable_transcoder(new_crtc_state);
2173
2174         intel_crtc_vblank_on(new_crtc_state);
2175
2176         intel_encoders_enable(state, crtc);
2177
2178         /* prevents spurious underruns */
2179         if (DISPLAY_VER(dev_priv) == 2)
2180                 intel_crtc_wait_for_next_vblank(crtc);
2181 }
2182
2183 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
2184 {
2185         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
2186         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2187
2188         if (!old_crtc_state->gmch_pfit.control)
2189                 return;
2190
2191         assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
2192
2193         drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
2194                     intel_de_read(dev_priv, PFIT_CONTROL));
2195         intel_de_write(dev_priv, PFIT_CONTROL, 0);
2196 }
2197
2198 static void i9xx_crtc_disable(struct intel_atomic_state *state,
2199                               struct intel_crtc *crtc)
2200 {
2201         struct intel_crtc_state *old_crtc_state =
2202                 intel_atomic_get_old_crtc_state(state, crtc);
2203         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2204         enum pipe pipe = crtc->pipe;
2205
2206         /*
2207          * On gen2 planes are double buffered but the pipe isn't, so we must
2208          * wait for planes to fully turn off before disabling the pipe.
2209          */
2210         if (DISPLAY_VER(dev_priv) == 2)
2211                 intel_crtc_wait_for_next_vblank(crtc);
2212
2213         intel_encoders_disable(state, crtc);
2214
2215         intel_crtc_vblank_off(old_crtc_state);
2216
2217         intel_disable_transcoder(old_crtc_state);
2218
2219         i9xx_pfit_disable(old_crtc_state);
2220
2221         intel_encoders_post_disable(state, crtc);
2222
2223         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
2224                 if (IS_CHERRYVIEW(dev_priv))
2225                         chv_disable_pll(dev_priv, pipe);
2226                 else if (IS_VALLEYVIEW(dev_priv))
2227                         vlv_disable_pll(dev_priv, pipe);
2228                 else
2229                         i9xx_disable_pll(old_crtc_state);
2230         }
2231
2232         intel_encoders_post_pll_disable(state, crtc);
2233
2234         if (DISPLAY_VER(dev_priv) != 2)
2235                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2236
2237         if (!dev_priv->display.funcs.wm->initial_watermarks)
2238                 intel_update_watermarks(dev_priv);
2239
2240         /* clock the pipe down to 640x480@60 to potentially save power */
2241         if (IS_I830(dev_priv))
2242                 i830_enable_pipe(dev_priv, pipe);
2243 }
2244
2245 void intel_encoder_destroy(struct drm_encoder *encoder)
2246 {
2247         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2248
2249         drm_encoder_cleanup(encoder);
2250         kfree(intel_encoder);
2251 }
2252
2253 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
2254 {
2255         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2256
2257         /* GDG double wide on either pipe, otherwise pipe A only */
2258         return DISPLAY_VER(dev_priv) < 4 &&
2259                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
2260 }
2261
2262 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
2263 {
2264         u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
2265         struct drm_rect src;
2266
2267         /*
2268          * We only use IF-ID interlacing. If we ever use
2269          * PF-ID we'll need to adjust the pixel_rate here.
2270          */
2271
2272         if (!crtc_state->pch_pfit.enabled)
2273                 return pixel_rate;
2274
2275         drm_rect_init(&src, 0, 0,
2276                       drm_rect_width(&crtc_state->pipe_src) << 16,
2277                       drm_rect_height(&crtc_state->pipe_src) << 16);
2278
2279         return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
2280                                    pixel_rate);
2281 }
2282
2283 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
2284                                          const struct drm_display_mode *timings)
2285 {
2286         mode->hdisplay = timings->crtc_hdisplay;
2287         mode->htotal = timings->crtc_htotal;
2288         mode->hsync_start = timings->crtc_hsync_start;
2289         mode->hsync_end = timings->crtc_hsync_end;
2290
2291         mode->vdisplay = timings->crtc_vdisplay;
2292         mode->vtotal = timings->crtc_vtotal;
2293         mode->vsync_start = timings->crtc_vsync_start;
2294         mode->vsync_end = timings->crtc_vsync_end;
2295
2296         mode->flags = timings->flags;
2297         mode->type = DRM_MODE_TYPE_DRIVER;
2298
2299         mode->clock = timings->crtc_clock;
2300
2301         drm_mode_set_name(mode);
2302 }
2303
2304 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
2305 {
2306         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2307
2308         if (HAS_GMCH(dev_priv))
2309                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
2310                 crtc_state->pixel_rate =
2311                         crtc_state->hw.pipe_mode.crtc_clock;
2312         else
2313                 crtc_state->pixel_rate =
2314                         ilk_pipe_pixel_rate(crtc_state);
2315 }
2316
2317 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state,
2318                                            struct drm_display_mode *mode)
2319 {
2320         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2321
2322         if (num_pipes < 2)
2323                 return;
2324
2325         mode->crtc_clock /= num_pipes;
2326         mode->crtc_hdisplay /= num_pipes;
2327         mode->crtc_hblank_start /= num_pipes;
2328         mode->crtc_hblank_end /= num_pipes;
2329         mode->crtc_hsync_start /= num_pipes;
2330         mode->crtc_hsync_end /= num_pipes;
2331         mode->crtc_htotal /= num_pipes;
2332 }
2333
2334 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state,
2335                                           struct drm_display_mode *mode)
2336 {
2337         int overlap = crtc_state->splitter.pixel_overlap;
2338         int n = crtc_state->splitter.link_count;
2339
2340         if (!crtc_state->splitter.enable)
2341                 return;
2342
2343         /*
2344          * eDP MSO uses segment timings from EDID for transcoder
2345          * timings, but full mode for everything else.
2346          *
2347          * h_full = (h_segment - pixel_overlap) * link_count
2348          */
2349         mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;
2350         mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;
2351         mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;
2352         mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;
2353         mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;
2354         mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;
2355         mode->crtc_clock *= n;
2356 }
2357
2358 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
2359 {
2360         struct drm_display_mode *mode = &crtc_state->hw.mode;
2361         struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2362         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2363
2364         /*
2365          * Start with the adjusted_mode crtc timings, which
2366          * have been filled with the transcoder timings.
2367          */
2368         drm_mode_copy(pipe_mode, adjusted_mode);
2369
2370         /* Expand MSO per-segment transcoder timings to full */
2371         intel_splitter_adjust_timings(crtc_state, pipe_mode);
2372
2373         /*
2374          * We want the full numbers in adjusted_mode normal timings,
2375          * adjusted_mode crtc timings are left with the raw transcoder
2376          * timings.
2377          */
2378         intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);
2379
2380         /* Populate the "user" mode with full numbers */
2381         drm_mode_copy(mode, pipe_mode);
2382         intel_mode_from_crtc_timings(mode, mode);
2383         mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *
2384                 (intel_bigjoiner_num_pipes(crtc_state) ?: 1);
2385         mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);
2386
2387         /* Derive per-pipe timings in case bigjoiner is used */
2388         intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2389         intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2390
2391         intel_crtc_compute_pixel_rate(crtc_state);
2392 }
2393
2394 void intel_encoder_get_config(struct intel_encoder *encoder,
2395                               struct intel_crtc_state *crtc_state)
2396 {
2397         encoder->get_config(encoder, crtc_state);
2398
2399         intel_crtc_readout_derived_state(crtc_state);
2400 }
2401
2402 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
2403 {
2404         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2405         int width, height;
2406
2407         if (num_pipes < 2)
2408                 return;
2409
2410         width = drm_rect_width(&crtc_state->pipe_src);
2411         height = drm_rect_height(&crtc_state->pipe_src);
2412
2413         drm_rect_init(&crtc_state->pipe_src, 0, 0,
2414                       width / num_pipes, height);
2415 }
2416
2417 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state)
2418 {
2419         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2420         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2421
2422         intel_bigjoiner_compute_pipe_src(crtc_state);
2423
2424         /*
2425          * Pipe horizontal size must be even in:
2426          * - DVO ganged mode
2427          * - LVDS dual channel mode
2428          * - Double wide pipe
2429          */
2430         if (drm_rect_width(&crtc_state->pipe_src) & 1) {
2431                 if (crtc_state->double_wide) {
2432                         drm_dbg_kms(&i915->drm,
2433                                     "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n",
2434                                     crtc->base.base.id, crtc->base.name);
2435                         return -EINVAL;
2436                 }
2437
2438                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
2439                     intel_is_dual_link_lvds(i915)) {
2440                         drm_dbg_kms(&i915->drm,
2441                                     "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n",
2442                                     crtc->base.base.id, crtc->base.name);
2443                         return -EINVAL;
2444                 }
2445         }
2446
2447         return 0;
2448 }
2449
2450 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
2451 {
2452         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2453         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2454         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2455         struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2456         int clock_limit = i915->display.cdclk.max_dotclk_freq;
2457
2458         /*
2459          * Start with the adjusted_mode crtc timings, which
2460          * have been filled with the transcoder timings.
2461          */
2462         drm_mode_copy(pipe_mode, adjusted_mode);
2463
2464         /* Expand MSO per-segment transcoder timings to full */
2465         intel_splitter_adjust_timings(crtc_state, pipe_mode);
2466
2467         /* Derive per-pipe timings in case bigjoiner is used */
2468         intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2469         intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2470
2471         if (DISPLAY_VER(i915) < 4) {
2472                 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10;
2473
2474                 /*
2475                  * Enable double wide mode when the dot clock
2476                  * is > 90% of the (display) core speed.
2477                  */
2478                 if (intel_crtc_supports_double_wide(crtc) &&
2479                     pipe_mode->crtc_clock > clock_limit) {
2480                         clock_limit = i915->display.cdclk.max_dotclk_freq;
2481                         crtc_state->double_wide = true;
2482                 }
2483         }
2484
2485         if (pipe_mode->crtc_clock > clock_limit) {
2486                 drm_dbg_kms(&i915->drm,
2487                             "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
2488                             crtc->base.base.id, crtc->base.name,
2489                             pipe_mode->crtc_clock, clock_limit,
2490                             str_yes_no(crtc_state->double_wide));
2491                 return -EINVAL;
2492         }
2493
2494         return 0;
2495 }
2496
2497 static int intel_crtc_compute_config(struct intel_atomic_state *state,
2498                                      struct intel_crtc *crtc)
2499 {
2500         struct intel_crtc_state *crtc_state =
2501                 intel_atomic_get_new_crtc_state(state, crtc);
2502         int ret;
2503
2504         ret = intel_dpll_crtc_compute_clock(state, crtc);
2505         if (ret)
2506                 return ret;
2507
2508         ret = intel_crtc_compute_pipe_src(crtc_state);
2509         if (ret)
2510                 return ret;
2511
2512         ret = intel_crtc_compute_pipe_mode(crtc_state);
2513         if (ret)
2514                 return ret;
2515
2516         intel_crtc_compute_pixel_rate(crtc_state);
2517
2518         if (crtc_state->has_pch_encoder)
2519                 return ilk_fdi_compute_config(crtc, crtc_state);
2520
2521         return 0;
2522 }
2523
2524 static void
2525 intel_reduce_m_n_ratio(u32 *num, u32 *den)
2526 {
2527         while (*num > DATA_LINK_M_N_MASK ||
2528                *den > DATA_LINK_M_N_MASK) {
2529                 *num >>= 1;
2530                 *den >>= 1;
2531         }
2532 }
2533
2534 static void compute_m_n(u32 *ret_m, u32 *ret_n,
2535                         u32 m, u32 n, u32 constant_n)
2536 {
2537         if (constant_n)
2538                 *ret_n = constant_n;
2539         else
2540                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
2541
2542         *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
2543         intel_reduce_m_n_ratio(ret_m, ret_n);
2544 }
2545
2546 void
2547 intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
2548                        int pixel_clock, int link_clock,
2549                        int bw_overhead,
2550                        struct intel_link_m_n *m_n)
2551 {
2552         u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock);
2553         u32 data_m = intel_dp_effective_data_rate(pixel_clock, bits_per_pixel_x16,
2554                                                   bw_overhead);
2555         u32 data_n = drm_dp_max_dprx_data_rate(link_clock, nlanes);
2556
2557         /*
2558          * Windows/BIOS uses fixed M/N values always. Follow suit.
2559          *
2560          * Also several DP dongles in particular seem to be fussy
2561          * about too large link M/N values. Presumably the 20bit
2562          * value used by Windows/BIOS is acceptable to everyone.
2563          */
2564         m_n->tu = 64;
2565         compute_m_n(&m_n->data_m, &m_n->data_n,
2566                     data_m, data_n,
2567                     0x8000000);
2568
2569         compute_m_n(&m_n->link_m, &m_n->link_n,
2570                     pixel_clock, link_symbol_clock,
2571                     0x80000);
2572 }
2573
2574 void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
2575 {
2576         /*
2577          * There may be no VBT; and if the BIOS enabled SSC we can
2578          * just keep using it to avoid unnecessary flicker.  Whereas if the
2579          * BIOS isn't using it, don't assume it will work even if the VBT
2580          * indicates as much.
2581          */
2582         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
2583                 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
2584                                                        PCH_DREF_CONTROL) &
2585                         DREF_SSC1_ENABLE;
2586
2587                 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) {
2588                         drm_dbg_kms(&dev_priv->drm,
2589                                     "SSC %s by BIOS, overriding VBT which says %s\n",
2590                                     str_enabled_disabled(bios_lvds_use_ssc),
2591                                     str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc));
2592                         dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc;
2593                 }
2594         }
2595 }
2596
2597 void intel_zero_m_n(struct intel_link_m_n *m_n)
2598 {
2599         /* corresponds to 0 register value */
2600         memset(m_n, 0, sizeof(*m_n));
2601         m_n->tu = 1;
2602 }
2603
2604 void intel_set_m_n(struct drm_i915_private *i915,
2605                    const struct intel_link_m_n *m_n,
2606                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
2607                    i915_reg_t link_m_reg, i915_reg_t link_n_reg)
2608 {
2609         intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
2610         intel_de_write(i915, data_n_reg, m_n->data_n);
2611         intel_de_write(i915, link_m_reg, m_n->link_m);
2612         /*
2613          * On BDW+ writing LINK_N arms the double buffered update
2614          * of all the M/N registers, so it must be written last.
2615          */
2616         intel_de_write(i915, link_n_reg, m_n->link_n);
2617 }
2618
2619 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
2620                                     enum transcoder transcoder)
2621 {
2622         if (IS_HASWELL(dev_priv))
2623                 return transcoder == TRANSCODER_EDP;
2624
2625         return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv);
2626 }
2627
2628 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
2629                                     enum transcoder transcoder,
2630                                     const struct intel_link_m_n *m_n)
2631 {
2632         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2633         enum pipe pipe = crtc->pipe;
2634
2635         if (DISPLAY_VER(dev_priv) >= 5)
2636                 intel_set_m_n(dev_priv, m_n,
2637                               PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
2638                               PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
2639         else
2640                 intel_set_m_n(dev_priv, m_n,
2641                               PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
2642                               PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
2643 }
2644
2645 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
2646                                     enum transcoder transcoder,
2647                                     const struct intel_link_m_n *m_n)
2648 {
2649         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2650
2651         if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
2652                 return;
2653
2654         intel_set_m_n(dev_priv, m_n,
2655                       PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
2656                       PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
2657 }
2658
2659 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
2660 {
2661         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2662         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2663         enum pipe pipe = crtc->pipe;
2664         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2665         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2666         u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2667         int vsyncshift = 0;
2668
2669         /* We need to be careful not to changed the adjusted mode, for otherwise
2670          * the hw state checker will get angry at the mismatch. */
2671         crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2672         crtc_vtotal = adjusted_mode->crtc_vtotal;
2673         crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2674         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2675
2676         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
2677                 /* the chip adds 2 halflines automatically */
2678                 crtc_vtotal -= 1;
2679                 crtc_vblank_end -= 1;
2680
2681                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2682                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
2683                 else
2684                         vsyncshift = adjusted_mode->crtc_hsync_start -
2685                                 adjusted_mode->crtc_htotal / 2;
2686                 if (vsyncshift < 0)
2687                         vsyncshift += adjusted_mode->crtc_htotal;
2688         }
2689
2690         /*
2691          * VBLANK_START no longer works on ADL+, instead we must use
2692          * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
2693          */
2694         if (DISPLAY_VER(dev_priv) >= 13) {
2695                 intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder),
2696                                crtc_vblank_start - crtc_vdisplay);
2697
2698                 /*
2699                  * VBLANK_START not used by hw, just clear it
2700                  * to make it stand out in register dumps.
2701                  */
2702                 crtc_vblank_start = 1;
2703         }
2704
2705         if (DISPLAY_VER(dev_priv) >= 4)
2706                 intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),
2707                                vsyncshift);
2708
2709         intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
2710                        HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
2711                        HTOTAL(adjusted_mode->crtc_htotal - 1));
2712         intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
2713                        HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
2714                        HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
2715         intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
2716                        HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
2717                        HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
2718
2719         intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
2720                        VACTIVE(crtc_vdisplay - 1) |
2721                        VTOTAL(crtc_vtotal - 1));
2722         intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
2723                        VBLANK_START(crtc_vblank_start - 1) |
2724                        VBLANK_END(crtc_vblank_end - 1));
2725         intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
2726                        VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
2727                        VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
2728
2729         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
2730          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
2731          * documented on the DDI_FUNC_CTL register description, EDP Input Select
2732          * bits. */
2733         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
2734             (pipe == PIPE_B || pipe == PIPE_C))
2735                 intel_de_write(dev_priv, TRANS_VTOTAL(pipe),
2736                                VACTIVE(crtc_vdisplay - 1) |
2737                                VTOTAL(crtc_vtotal - 1));
2738 }
2739
2740 static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
2741 {
2742         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2743         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2744         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2745         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2746         u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2747
2748         crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2749         crtc_vtotal = adjusted_mode->crtc_vtotal;
2750         crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2751         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2752
2753         drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
2754
2755         /*
2756          * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
2757          * But let's write it anyway to keep the state checker happy.
2758          */
2759         intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
2760                        VBLANK_START(crtc_vblank_start - 1) |
2761                        VBLANK_END(crtc_vblank_end - 1));
2762         /*
2763          * The double buffer latch point for TRANS_VTOTAL
2764          * is the transcoder's undelayed vblank.
2765          */
2766         intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
2767                        VACTIVE(crtc_vdisplay - 1) |
2768                        VTOTAL(crtc_vtotal - 1));
2769 }
2770
2771 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
2772 {
2773         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2774         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2775         int width = drm_rect_width(&crtc_state->pipe_src);
2776         int height = drm_rect_height(&crtc_state->pipe_src);
2777         enum pipe pipe = crtc->pipe;
2778
2779         /* pipesrc controls the size that is scaled from, which should
2780          * always be the user's requested size.
2781          */
2782         intel_de_write(dev_priv, PIPESRC(pipe),
2783                        PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
2784 }
2785
2786 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
2787 {
2788         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2789         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2790
2791         if (DISPLAY_VER(dev_priv) == 2)
2792                 return false;
2793
2794         if (DISPLAY_VER(dev_priv) >= 9 ||
2795             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2796                 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
2797         else
2798                 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
2799 }
2800
2801 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
2802                                          struct intel_crtc_state *pipe_config)
2803 {
2804         struct drm_device *dev = crtc->base.dev;
2805         struct drm_i915_private *dev_priv = to_i915(dev);
2806         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2807         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2808         u32 tmp;
2809
2810         tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder));
2811         adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
2812         adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
2813
2814         if (!transcoder_is_dsi(cpu_transcoder)) {
2815                 tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
2816                 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
2817                 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
2818         }
2819
2820         tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder));
2821         adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
2822         adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
2823
2824         tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
2825         adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
2826         adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
2827
2828         /* FIXME TGL+ DSI transcoders have this! */
2829         if (!transcoder_is_dsi(cpu_transcoder)) {
2830                 tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
2831                 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
2832                 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
2833         }
2834         tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
2835         adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;
2836         adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;
2837
2838         if (intel_pipe_is_interlaced(pipe_config)) {
2839                 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
2840                 adjusted_mode->crtc_vtotal += 1;
2841                 adjusted_mode->crtc_vblank_end += 1;
2842         }
2843
2844         if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder))
2845                 adjusted_mode->crtc_vblank_start =
2846                         adjusted_mode->crtc_vdisplay +
2847                         intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder));
2848 }
2849
2850 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
2851 {
2852         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2853         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2854         enum pipe master_pipe, pipe = crtc->pipe;
2855         int width;
2856
2857         if (num_pipes < 2)
2858                 return;
2859
2860         master_pipe = bigjoiner_master_pipe(crtc_state);
2861         width = drm_rect_width(&crtc_state->pipe_src);
2862
2863         drm_rect_translate_to(&crtc_state->pipe_src,
2864                               (pipe - master_pipe) * width, 0);
2865 }
2866
2867 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
2868                                     struct intel_crtc_state *pipe_config)
2869 {
2870         struct drm_device *dev = crtc->base.dev;
2871         struct drm_i915_private *dev_priv = to_i915(dev);
2872         u32 tmp;
2873
2874         tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
2875
2876         drm_rect_init(&pipe_config->pipe_src, 0, 0,
2877                       REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
2878                       REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);
2879
2880         intel_bigjoiner_adjust_pipe_src(pipe_config);
2881 }
2882
2883 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
2884 {
2885         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2886         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2887         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2888         u32 val = 0;
2889
2890         /*
2891          * - We keep both pipes enabled on 830
2892          * - During modeset the pipe is still disabled and must remain so
2893          * - During fastset the pipe is already enabled and must remain so
2894          */
2895         if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state))
2896                 val |= TRANSCONF_ENABLE;
2897
2898         if (crtc_state->double_wide)
2899                 val |= TRANSCONF_DOUBLE_WIDE;
2900
2901         /* only g4x and later have fancy bpc/dither controls */
2902         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
2903             IS_CHERRYVIEW(dev_priv)) {
2904                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
2905                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
2906                         val |= TRANSCONF_DITHER_EN |
2907                                 TRANSCONF_DITHER_TYPE_SP;
2908
2909                 switch (crtc_state->pipe_bpp) {
2910                 default:
2911                         /* Case prevented by intel_choose_pipe_bpp_dither. */
2912                         MISSING_CASE(crtc_state->pipe_bpp);
2913                         fallthrough;
2914                 case 18:
2915                         val |= TRANSCONF_BPC_6;
2916                         break;
2917                 case 24:
2918                         val |= TRANSCONF_BPC_8;
2919                         break;
2920                 case 30:
2921                         val |= TRANSCONF_BPC_10;
2922                         break;
2923                 }
2924         }
2925
2926         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
2927                 if (DISPLAY_VER(dev_priv) < 4 ||
2928                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2929                         val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION;
2930                 else
2931                         val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT;
2932         } else {
2933                 val |= TRANSCONF_INTERLACE_PROGRESSIVE;
2934         }
2935
2936         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2937              crtc_state->limited_color_range)
2938                 val |= TRANSCONF_COLOR_RANGE_SELECT;
2939
2940         val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
2941
2942         if (crtc_state->wgc_enable)
2943                 val |= TRANSCONF_WGC_ENABLE;
2944
2945         val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
2946
2947         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
2948         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
2949 }
2950
2951 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
2952 {
2953         if (IS_I830(dev_priv))
2954                 return false;
2955
2956         return DISPLAY_VER(dev_priv) >= 4 ||
2957                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
2958 }
2959
2960 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
2961 {
2962         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2963         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2964         enum pipe pipe;
2965         u32 tmp;
2966
2967         if (!i9xx_has_pfit(dev_priv))
2968                 return;
2969
2970         tmp = intel_de_read(dev_priv, PFIT_CONTROL);
2971         if (!(tmp & PFIT_ENABLE))
2972                 return;
2973
2974         /* Check whether the pfit is attached to our pipe. */
2975         if (DISPLAY_VER(dev_priv) >= 4)
2976                 pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);
2977         else
2978                 pipe = PIPE_B;
2979
2980         if (pipe != crtc->pipe)
2981                 return;
2982
2983         crtc_state->gmch_pfit.control = tmp;
2984         crtc_state->gmch_pfit.pgm_ratios =
2985                 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
2986 }
2987
2988 static enum intel_output_format
2989 bdw_get_pipe_misc_output_format(struct intel_crtc *crtc)
2990 {
2991         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2992         u32 tmp;
2993
2994         tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
2995
2996         if (tmp & PIPE_MISC_YUV420_ENABLE) {
2997                 /* We support 4:2:0 in full blend mode only */
2998                 drm_WARN_ON(&dev_priv->drm,
2999                             (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0);
3000
3001                 return INTEL_OUTPUT_FORMAT_YCBCR420;
3002         } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) {
3003                 return INTEL_OUTPUT_FORMAT_YCBCR444;
3004         } else {
3005                 return INTEL_OUTPUT_FORMAT_RGB;
3006         }
3007 }
3008
3009 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
3010                                  struct intel_crtc_state *pipe_config)
3011 {
3012         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3013         enum intel_display_power_domain power_domain;
3014         intel_wakeref_t wakeref;
3015         u32 tmp;
3016         bool ret;
3017
3018         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3019         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3020         if (!wakeref)
3021                 return false;
3022
3023         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3024         pipe_config->sink_format = pipe_config->output_format;
3025         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3026         pipe_config->shared_dpll = NULL;
3027
3028         ret = false;
3029
3030         tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3031         if (!(tmp & TRANSCONF_ENABLE))
3032                 goto out;
3033
3034         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
3035             IS_CHERRYVIEW(dev_priv)) {
3036                 switch (tmp & TRANSCONF_BPC_MASK) {
3037                 case TRANSCONF_BPC_6:
3038                         pipe_config->pipe_bpp = 18;
3039                         break;
3040                 case TRANSCONF_BPC_8:
3041                         pipe_config->pipe_bpp = 24;
3042                         break;
3043                 case TRANSCONF_BPC_10:
3044                         pipe_config->pipe_bpp = 30;
3045                         break;
3046                 default:
3047                         MISSING_CASE(tmp);
3048                         break;
3049                 }
3050         }
3051
3052         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
3053             (tmp & TRANSCONF_COLOR_RANGE_SELECT))
3054                 pipe_config->limited_color_range = true;
3055
3056         pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);
3057
3058         pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3059
3060         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
3061             (tmp & TRANSCONF_WGC_ENABLE))
3062                 pipe_config->wgc_enable = true;
3063
3064         intel_color_get_config(pipe_config);
3065
3066         if (DISPLAY_VER(dev_priv) < 4)
3067                 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;
3068
3069         intel_get_transcoder_timings(crtc, pipe_config);
3070         intel_get_pipe_src_size(crtc, pipe_config);
3071
3072         i9xx_get_pfit_config(pipe_config);
3073
3074         i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state);
3075
3076         if (DISPLAY_VER(dev_priv) >= 4) {
3077                 tmp = pipe_config->dpll_hw_state.i9xx.dpll_md;
3078                 pipe_config->pixel_multiplier =
3079                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
3080                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
3081         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
3082                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
3083                 tmp = pipe_config->dpll_hw_state.i9xx.dpll;
3084                 pipe_config->pixel_multiplier =
3085                         ((tmp & SDVO_MULTIPLIER_MASK)
3086                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
3087         } else {
3088                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
3089                  * port and will be fixed up in the encoder->get_config
3090                  * function. */
3091                 pipe_config->pixel_multiplier = 1;
3092         }
3093
3094         if (IS_CHERRYVIEW(dev_priv))
3095                 chv_crtc_clock_get(pipe_config);
3096         else if (IS_VALLEYVIEW(dev_priv))
3097                 vlv_crtc_clock_get(pipe_config);
3098         else
3099                 i9xx_crtc_clock_get(pipe_config);
3100
3101         /*
3102          * Normally the dotclock is filled in by the encoder .get_config()
3103          * but in case the pipe is enabled w/o any ports we need a sane
3104          * default.
3105          */
3106         pipe_config->hw.adjusted_mode.crtc_clock =
3107                 pipe_config->port_clock / pipe_config->pixel_multiplier;
3108
3109         ret = true;
3110
3111 out:
3112         intel_display_power_put(dev_priv, power_domain, wakeref);
3113
3114         return ret;
3115 }
3116
3117 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
3118 {
3119         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3120         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3121         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3122         u32 val = 0;
3123
3124         /*
3125          * - During modeset the pipe is still disabled and must remain so
3126          * - During fastset the pipe is already enabled and must remain so
3127          */
3128         if (!intel_crtc_needs_modeset(crtc_state))
3129                 val |= TRANSCONF_ENABLE;
3130
3131         switch (crtc_state->pipe_bpp) {
3132         default:
3133                 /* Case prevented by intel_choose_pipe_bpp_dither. */
3134                 MISSING_CASE(crtc_state->pipe_bpp);
3135                 fallthrough;
3136         case 18:
3137                 val |= TRANSCONF_BPC_6;
3138                 break;
3139         case 24:
3140                 val |= TRANSCONF_BPC_8;
3141                 break;
3142         case 30:
3143                 val |= TRANSCONF_BPC_10;
3144                 break;
3145         case 36:
3146                 val |= TRANSCONF_BPC_12;
3147                 break;
3148         }
3149
3150         if (crtc_state->dither)
3151                 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3152
3153         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3154                 val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3155         else
3156                 val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3157
3158         /*
3159          * This would end up with an odd purple hue over
3160          * the entire display. Make sure we don't do it.
3161          */
3162         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
3163                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
3164
3165         if (crtc_state->limited_color_range &&
3166             !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
3167                 val |= TRANSCONF_COLOR_RANGE_SELECT;
3168
3169         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3170                 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709;
3171
3172         val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
3173
3174         val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
3175         val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
3176
3177         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
3178         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
3179 }
3180
3181 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
3182 {
3183         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3184         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3185         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3186         u32 val = 0;
3187
3188         /*
3189          * - During modeset the pipe is still disabled and must remain so
3190          * - During fastset the pipe is already enabled and must remain so
3191          */
3192         if (!intel_crtc_needs_modeset(crtc_state))
3193                 val |= TRANSCONF_ENABLE;
3194
3195         if (IS_HASWELL(dev_priv) && crtc_state->dither)
3196                 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3197
3198         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3199                 val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3200         else
3201                 val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3202
3203         if (IS_HASWELL(dev_priv) &&
3204             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3205                 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW;
3206
3207         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
3208         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
3209 }
3210
3211 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state)
3212 {
3213         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3214         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3215         u32 val = 0;
3216
3217         switch (crtc_state->pipe_bpp) {
3218         case 18:
3219                 val |= PIPE_MISC_BPC_6;
3220                 break;
3221         case 24:
3222                 val |= PIPE_MISC_BPC_8;
3223                 break;
3224         case 30:
3225                 val |= PIPE_MISC_BPC_10;
3226                 break;
3227         case 36:
3228                 /* Port output 12BPC defined for ADLP+ */
3229                 if (DISPLAY_VER(dev_priv) >= 13)
3230                         val |= PIPE_MISC_BPC_12_ADLP;
3231                 break;
3232         default:
3233                 MISSING_CASE(crtc_state->pipe_bpp);
3234                 break;
3235         }
3236
3237         if (crtc_state->dither)
3238                 val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP;
3239
3240         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
3241             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
3242                 val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV;
3243
3244         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3245                 val |= PIPE_MISC_YUV420_ENABLE |
3246                         PIPE_MISC_YUV420_MODE_FULL_BLEND;
3247
3248         if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state))
3249                 val |= PIPE_MISC_HDR_MODE_PRECISION;
3250
3251         if (DISPLAY_VER(dev_priv) >= 12)
3252                 val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC;
3253
3254         /* allow PSR with sprite enabled */
3255         if (IS_BROADWELL(dev_priv))
3256                 val |= PIPE_MISC_PSR_MASK_SPRITE_ENABLE;
3257
3258         intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val);
3259 }
3260
3261 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc)
3262 {
3263         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3264         u32 tmp;
3265
3266         tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
3267
3268         switch (tmp & PIPE_MISC_BPC_MASK) {
3269         case PIPE_MISC_BPC_6:
3270                 return 18;
3271         case PIPE_MISC_BPC_8:
3272                 return 24;
3273         case PIPE_MISC_BPC_10:
3274                 return 30;
3275         /*
3276          * PORT OUTPUT 12 BPC defined for ADLP+.
3277          *
3278          * TODO:
3279          * For previous platforms with DSI interface, bits 5:7
3280          * are used for storing pipe_bpp irrespective of dithering.
3281          * Since the value of 12 BPC is not defined for these bits
3282          * on older platforms, need to find a workaround for 12 BPC
3283          * MIPI DSI HW readout.
3284          */
3285         case PIPE_MISC_BPC_12_ADLP:
3286                 if (DISPLAY_VER(dev_priv) >= 13)
3287                         return 36;
3288                 fallthrough;
3289         default:
3290                 MISSING_CASE(tmp);
3291                 return 0;
3292         }
3293 }
3294
3295 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
3296 {
3297         /*
3298          * Account for spread spectrum to avoid
3299          * oversubscribing the link. Max center spread
3300          * is 2.5%; use 5% for safety's sake.
3301          */
3302         u32 bps = target_clock * bpp * 21 / 20;
3303         return DIV_ROUND_UP(bps, link_bw * 8);
3304 }
3305
3306 void intel_get_m_n(struct drm_i915_private *i915,
3307                    struct intel_link_m_n *m_n,
3308                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
3309                    i915_reg_t link_m_reg, i915_reg_t link_n_reg)
3310 {
3311         m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
3312         m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
3313         m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
3314         m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
3315         m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
3316 }
3317
3318 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
3319                                     enum transcoder transcoder,
3320                                     struct intel_link_m_n *m_n)
3321 {
3322         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3323         enum pipe pipe = crtc->pipe;
3324
3325         if (DISPLAY_VER(dev_priv) >= 5)
3326                 intel_get_m_n(dev_priv, m_n,
3327                               PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
3328                               PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
3329         else
3330                 intel_get_m_n(dev_priv, m_n,
3331                               PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
3332                               PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
3333 }
3334
3335 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
3336                                     enum transcoder transcoder,
3337                                     struct intel_link_m_n *m_n)
3338 {
3339         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3340
3341         if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
3342                 return;
3343
3344         intel_get_m_n(dev_priv, m_n,
3345                       PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
3346                       PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
3347 }
3348
3349 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
3350 {
3351         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3352         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3353         u32 ctl, pos, size;
3354         enum pipe pipe;
3355
3356         ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
3357         if ((ctl & PF_ENABLE) == 0)
3358                 return;
3359
3360         if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
3361                 pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl);
3362         else
3363                 pipe = crtc->pipe;
3364
3365         crtc_state->pch_pfit.enabled = true;
3366
3367         pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
3368         size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
3369
3370         drm_rect_init(&crtc_state->pch_pfit.dst,
3371                       REG_FIELD_GET(PF_WIN_XPOS_MASK, pos),
3372                       REG_FIELD_GET(PF_WIN_YPOS_MASK, pos),
3373                       REG_FIELD_GET(PF_WIN_XSIZE_MASK, size),
3374                       REG_FIELD_GET(PF_WIN_YSIZE_MASK, size));
3375
3376         /*
3377          * We currently do not free assignements of panel fitters on
3378          * ivb/hsw (since we don't use the higher upscaling modes which
3379          * differentiates them) so just WARN about this case for now.
3380          */
3381         drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe);
3382 }
3383
3384 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
3385                                 struct intel_crtc_state *pipe_config)
3386 {
3387         struct drm_device *dev = crtc->base.dev;
3388         struct drm_i915_private *dev_priv = to_i915(dev);
3389         enum intel_display_power_domain power_domain;
3390         intel_wakeref_t wakeref;
3391         u32 tmp;
3392         bool ret;
3393
3394         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3395         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3396         if (!wakeref)
3397                 return false;
3398
3399         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3400         pipe_config->shared_dpll = NULL;
3401
3402         ret = false;
3403         tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3404         if (!(tmp & TRANSCONF_ENABLE))
3405                 goto out;
3406
3407         switch (tmp & TRANSCONF_BPC_MASK) {
3408         case TRANSCONF_BPC_6:
3409                 pipe_config->pipe_bpp = 18;
3410                 break;
3411         case TRANSCONF_BPC_8:
3412                 pipe_config->pipe_bpp = 24;
3413                 break;
3414         case TRANSCONF_BPC_10:
3415                 pipe_config->pipe_bpp = 30;
3416                 break;
3417         case TRANSCONF_BPC_12:
3418                 pipe_config->pipe_bpp = 36;
3419                 break;
3420         default:
3421                 break;
3422         }
3423
3424         if (tmp & TRANSCONF_COLOR_RANGE_SELECT)
3425                 pipe_config->limited_color_range = true;
3426
3427         switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) {
3428         case TRANSCONF_OUTPUT_COLORSPACE_YUV601:
3429         case TRANSCONF_OUTPUT_COLORSPACE_YUV709:
3430                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3431                 break;
3432         default:
3433                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3434                 break;
3435         }
3436
3437         pipe_config->sink_format = pipe_config->output_format;
3438
3439         pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);
3440
3441         pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3442
3443         pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);
3444
3445         intel_color_get_config(pipe_config);
3446
3447         pipe_config->pixel_multiplier = 1;
3448
3449         ilk_pch_get_config(pipe_config);
3450
3451         intel_get_transcoder_timings(crtc, pipe_config);
3452         intel_get_pipe_src_size(crtc, pipe_config);
3453
3454         ilk_get_pfit_config(pipe_config);
3455
3456         ret = true;
3457
3458 out:
3459         intel_display_power_put(dev_priv, power_domain, wakeref);
3460
3461         return ret;
3462 }
3463
3464 static u8 bigjoiner_pipes(struct drm_i915_private *i915)
3465 {
3466         u8 pipes;
3467
3468         if (DISPLAY_VER(i915) >= 12)
3469                 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
3470         else if (DISPLAY_VER(i915) >= 11)
3471                 pipes = BIT(PIPE_B) | BIT(PIPE_C);
3472         else
3473                 pipes = 0;
3474
3475         return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask;
3476 }
3477
3478 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
3479                                            enum transcoder cpu_transcoder)
3480 {
3481         enum intel_display_power_domain power_domain;
3482         intel_wakeref_t wakeref;
3483         u32 tmp = 0;
3484
3485         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3486
3487         with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3488                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3489
3490         return tmp & TRANS_DDI_FUNC_ENABLE;
3491 }
3492
3493 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv,
3494                                     u8 *master_pipes, u8 *slave_pipes)
3495 {
3496         struct intel_crtc *crtc;
3497
3498         *master_pipes = 0;
3499         *slave_pipes = 0;
3500
3501         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,
3502                                          bigjoiner_pipes(dev_priv)) {
3503                 enum intel_display_power_domain power_domain;
3504                 enum pipe pipe = crtc->pipe;
3505                 intel_wakeref_t wakeref;
3506
3507                 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe);
3508                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3509                         u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3510
3511                         if (!(tmp & BIG_JOINER_ENABLE))
3512                                 continue;
3513
3514                         if (tmp & MASTER_BIG_JOINER_ENABLE)
3515                                 *master_pipes |= BIT(pipe);
3516                         else
3517                                 *slave_pipes |= BIT(pipe);
3518                 }
3519
3520                 if (DISPLAY_VER(dev_priv) < 13)
3521                         continue;
3522
3523                 power_domain = POWER_DOMAIN_PIPE(pipe);
3524                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3525                         u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3526
3527                         if (tmp & UNCOMPRESSED_JOINER_MASTER)
3528                                 *master_pipes |= BIT(pipe);
3529                         if (tmp & UNCOMPRESSED_JOINER_SLAVE)
3530                                 *slave_pipes |= BIT(pipe);
3531                 }
3532         }
3533
3534         /* Bigjoiner pipes should always be consecutive master and slave */
3535         drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1,
3536                  "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n",
3537                  *master_pipes, *slave_pipes);
3538 }
3539
3540 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3541 {
3542         if ((slave_pipes & BIT(pipe)) == 0)
3543                 return pipe;
3544
3545         /* ignore everything above our pipe */
3546         master_pipes &= ~GENMASK(7, pipe);
3547
3548         /* highest remaining bit should be our master pipe */
3549         return fls(master_pipes) - 1;
3550 }
3551
3552 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3553 {
3554         enum pipe master_pipe, next_master_pipe;
3555
3556         master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes);
3557
3558         if ((master_pipes & BIT(master_pipe)) == 0)
3559                 return 0;
3560
3561         /* ignore our master pipe and everything below it */
3562         master_pipes &= ~GENMASK(master_pipe, 0);
3563         /* make sure a high bit is set for the ffs() */
3564         master_pipes |= BIT(7);
3565         /* lowest remaining bit should be the next master pipe */
3566         next_master_pipe = ffs(master_pipes) - 1;
3567
3568         return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe);
3569 }
3570
3571 static u8 hsw_panel_transcoders(struct drm_i915_private *i915)
3572 {
3573         u8 panel_transcoder_mask = BIT(TRANSCODER_EDP);
3574
3575         if (DISPLAY_VER(i915) >= 11)
3576                 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
3577
3578         return panel_transcoder_mask;
3579 }
3580
3581 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
3582 {
3583         struct drm_device *dev = crtc->base.dev;
3584         struct drm_i915_private *dev_priv = to_i915(dev);
3585         u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv);
3586         enum transcoder cpu_transcoder;
3587         u8 master_pipes, slave_pipes;
3588         u8 enabled_transcoders = 0;
3589
3590         /*
3591          * XXX: Do intel_display_power_get_if_enabled before reading this (for
3592          * consistency and less surprising code; it's in always on power).
3593          */
3594         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder,
3595                                        panel_transcoder_mask) {
3596                 enum intel_display_power_domain power_domain;
3597                 intel_wakeref_t wakeref;
3598                 enum pipe trans_pipe;
3599                 u32 tmp = 0;
3600
3601                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3602                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3603                         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3604
3605                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
3606                         continue;
3607
3608                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
3609                 default:
3610                         drm_WARN(dev, 1,
3611                                  "unknown pipe linked to transcoder %s\n",
3612                                  transcoder_name(cpu_transcoder));
3613                         fallthrough;
3614                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
3615                 case TRANS_DDI_EDP_INPUT_A_ON:
3616                         trans_pipe = PIPE_A;
3617                         break;
3618                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
3619                         trans_pipe = PIPE_B;
3620                         break;
3621                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
3622                         trans_pipe = PIPE_C;
3623                         break;
3624                 case TRANS_DDI_EDP_INPUT_D_ONOFF:
3625                         trans_pipe = PIPE_D;
3626                         break;
3627                 }
3628
3629                 if (trans_pipe == crtc->pipe)
3630                         enabled_transcoders |= BIT(cpu_transcoder);
3631         }
3632
3633         /* single pipe or bigjoiner master */
3634         cpu_transcoder = (enum transcoder) crtc->pipe;
3635         if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3636                 enabled_transcoders |= BIT(cpu_transcoder);
3637
3638         /* bigjoiner slave -> consider the master pipe's transcoder as well */
3639         enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes);
3640         if (slave_pipes & BIT(crtc->pipe)) {
3641                 cpu_transcoder = (enum transcoder)
3642                         get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes);
3643                 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3644                         enabled_transcoders |= BIT(cpu_transcoder);
3645         }
3646
3647         return enabled_transcoders;
3648 }
3649
3650 static bool has_edp_transcoders(u8 enabled_transcoders)
3651 {
3652         return enabled_transcoders & BIT(TRANSCODER_EDP);
3653 }
3654
3655 static bool has_dsi_transcoders(u8 enabled_transcoders)
3656 {
3657         return enabled_transcoders & (BIT(TRANSCODER_DSI_0) |
3658                                       BIT(TRANSCODER_DSI_1));
3659 }
3660
3661 static bool has_pipe_transcoders(u8 enabled_transcoders)
3662 {
3663         return enabled_transcoders & ~(BIT(TRANSCODER_EDP) |
3664                                        BIT(TRANSCODER_DSI_0) |
3665                                        BIT(TRANSCODER_DSI_1));
3666 }
3667
3668 static void assert_enabled_transcoders(struct drm_i915_private *i915,
3669                                        u8 enabled_transcoders)
3670 {
3671         /* Only one type of transcoder please */
3672         drm_WARN_ON(&i915->drm,
3673                     has_edp_transcoders(enabled_transcoders) +
3674                     has_dsi_transcoders(enabled_transcoders) +
3675                     has_pipe_transcoders(enabled_transcoders) > 1);
3676
3677         /* Only DSI transcoders can be ganged */
3678         drm_WARN_ON(&i915->drm,
3679                     !has_dsi_transcoders(enabled_transcoders) &&
3680                     !is_power_of_2(enabled_transcoders));
3681 }
3682
3683 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
3684                                      struct intel_crtc_state *pipe_config,
3685                                      struct intel_display_power_domain_set *power_domain_set)
3686 {
3687         struct drm_device *dev = crtc->base.dev;
3688         struct drm_i915_private *dev_priv = to_i915(dev);
3689         unsigned long enabled_transcoders;
3690         u32 tmp;
3691
3692         enabled_transcoders = hsw_enabled_transcoders(crtc);
3693         if (!enabled_transcoders)
3694                 return false;
3695
3696         assert_enabled_transcoders(dev_priv, enabled_transcoders);
3697
3698         /*
3699          * With the exception of DSI we should only ever have
3700          * a single enabled transcoder. With DSI let's just
3701          * pick the first one.
3702          */
3703         pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;
3704
3705         if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3706                                                        POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
3707                 return false;
3708
3709         if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) {
3710                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
3711
3712                 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
3713                         pipe_config->pch_pfit.force_thru = true;
3714         }
3715
3716         tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3717
3718         return tmp & TRANSCONF_ENABLE;
3719 }
3720
3721 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
3722                                          struct intel_crtc_state *pipe_config,
3723                                          struct intel_display_power_domain_set *power_domain_set)
3724 {
3725         struct intel_display *display = to_intel_display(crtc);
3726         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3727         enum transcoder cpu_transcoder;
3728         enum port port;
3729         u32 tmp;
3730
3731         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
3732                 if (port == PORT_A)
3733                         cpu_transcoder = TRANSCODER_DSI_A;
3734                 else
3735                         cpu_transcoder = TRANSCODER_DSI_C;
3736
3737                 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3738                                                                POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
3739                         continue;
3740
3741                 /*
3742                  * The PLL needs to be enabled with a valid divider
3743                  * configuration, otherwise accessing DSI registers will hang
3744                  * the machine. See BSpec North Display Engine
3745                  * registers/MIPI[BXT]. We can break out here early, since we
3746                  * need the same DSI PLL to be enabled for both DSI ports.
3747                  */
3748                 if (!bxt_dsi_pll_is_enabled(dev_priv))
3749                         break;
3750
3751                 /* XXX: this works for video mode only */
3752                 tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port));
3753                 if (!(tmp & DPI_ENABLE))
3754                         continue;
3755
3756                 tmp = intel_de_read(display, MIPI_CTRL(display, port));
3757                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
3758                         continue;
3759
3760                 pipe_config->cpu_transcoder = cpu_transcoder;
3761                 break;
3762         }
3763
3764         return transcoder_is_dsi(pipe_config->cpu_transcoder);
3765 }
3766
3767 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state)
3768 {
3769         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3770         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3771         u8 master_pipes, slave_pipes;
3772         enum pipe pipe = crtc->pipe;
3773
3774         enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes);
3775
3776         if (((master_pipes | slave_pipes) & BIT(pipe)) == 0)
3777                 return;
3778
3779         crtc_state->bigjoiner_pipes =
3780                 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) |
3781                 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes);
3782 }
3783
3784 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
3785                                 struct intel_crtc_state *pipe_config)
3786 {
3787         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3788         bool active;
3789         u32 tmp;
3790
3791         if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
3792                                                        POWER_DOMAIN_PIPE(crtc->pipe)))
3793                 return false;
3794
3795         pipe_config->shared_dpll = NULL;
3796
3797         active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains);
3798
3799         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
3800             bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) {
3801                 drm_WARN_ON(&dev_priv->drm, active);
3802                 active = true;
3803         }
3804
3805         if (!active)
3806                 goto out;
3807
3808         intel_bigjoiner_get_config(pipe_config);
3809         intel_dsc_get_config(pipe_config);
3810
3811         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
3812             DISPLAY_VER(dev_priv) >= 11)
3813                 intel_get_transcoder_timings(crtc, pipe_config);
3814
3815         if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
3816                 intel_vrr_get_config(pipe_config);
3817
3818         intel_get_pipe_src_size(crtc, pipe_config);
3819
3820         if (IS_HASWELL(dev_priv)) {
3821                 u32 tmp = intel_de_read(dev_priv,
3822                                         TRANSCONF(pipe_config->cpu_transcoder));
3823
3824                 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW)
3825                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3826                 else
3827                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3828         } else {
3829                 pipe_config->output_format =
3830                         bdw_get_pipe_misc_output_format(crtc);
3831         }
3832
3833         pipe_config->sink_format = pipe_config->output_format;
3834
3835         intel_color_get_config(pipe_config);
3836
3837         tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
3838         pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
3839         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
3840                 pipe_config->ips_linetime =
3841                         REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
3842
3843         if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
3844                                                       POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
3845                 if (DISPLAY_VER(dev_priv) >= 9)
3846                         skl_scaler_get_config(pipe_config);
3847                 else
3848                         ilk_get_pfit_config(pipe_config);
3849         }
3850
3851         hsw_ips_get_config(pipe_config);
3852
3853         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
3854             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
3855                 pipe_config->pixel_multiplier =
3856                         intel_de_read(dev_priv,
3857                                       TRANS_MULT(pipe_config->cpu_transcoder)) + 1;
3858         } else {
3859                 pipe_config->pixel_multiplier = 1;
3860         }
3861
3862         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
3863                 tmp = intel_de_read(dev_priv, hsw_chicken_trans_reg(dev_priv, pipe_config->cpu_transcoder));
3864
3865                 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
3866         } else {
3867                 /* no idea if this is correct */
3868                 pipe_config->framestart_delay = 1;
3869         }
3870
3871 out:
3872         intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains);
3873
3874         return active;
3875 }
3876
3877 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
3878 {
3879         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3880         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3881
3882         if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state))
3883                 return false;
3884
3885         crtc_state->hw.active = true;
3886
3887         intel_crtc_readout_derived_state(crtc_state);
3888
3889         return true;
3890 }
3891
3892 int intel_dotclock_calculate(int link_freq,
3893                              const struct intel_link_m_n *m_n)
3894 {
3895         /*
3896          * The calculation for the data clock -> pixel clock is:
3897          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
3898          * But we want to avoid losing precison if possible, so:
3899          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
3900          *
3901          * and for link freq (10kbs units) -> pixel clock it is:
3902          * link_symbol_clock = link_freq * 10 / link_symbol_size
3903          * pixel_clock = (m * link_symbol_clock) / n
3904          *    or for more precision:
3905          * pixel_clock = (m * link_freq * 10) / (n * link_symbol_size)
3906          */
3907
3908         if (!m_n->link_n)
3909                 return 0;
3910
3911         return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10),
3912                                 m_n->link_n * intel_dp_link_symbol_size(link_freq));
3913 }
3914
3915 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
3916 {
3917         int dotclock;
3918
3919         if (intel_crtc_has_dp_encoder(pipe_config))
3920                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
3921                                                     &pipe_config->dp_m_n);
3922         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
3923                 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,
3924                                              pipe_config->pipe_bpp);
3925         else
3926                 dotclock = pipe_config->port_clock;
3927
3928         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
3929             !intel_crtc_has_dp_encoder(pipe_config))
3930                 dotclock *= 2;
3931
3932         if (pipe_config->pixel_multiplier)
3933                 dotclock /= pipe_config->pixel_multiplier;
3934
3935         return dotclock;
3936 }
3937
3938 /* Returns the currently programmed mode of the given encoder. */
3939 struct drm_display_mode *
3940 intel_encoder_current_mode(struct intel_encoder *encoder)
3941 {
3942         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3943         struct intel_crtc_state *crtc_state;
3944         struct drm_display_mode *mode;
3945         struct intel_crtc *crtc;
3946         enum pipe pipe;
3947
3948         if (!encoder->get_hw_state(encoder, &pipe))
3949                 return NULL;
3950
3951         crtc = intel_crtc_for_pipe(dev_priv, pipe);
3952
3953         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3954         if (!mode)
3955                 return NULL;
3956
3957         crtc_state = intel_crtc_state_alloc(crtc);
3958         if (!crtc_state) {
3959                 kfree(mode);
3960                 return NULL;
3961         }
3962
3963         if (!intel_crtc_get_pipe_config(crtc_state)) {
3964                 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
3965                 kfree(mode);
3966                 return NULL;
3967         }
3968
3969         intel_encoder_get_config(encoder, crtc_state);
3970
3971         intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
3972
3973         intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
3974
3975         return mode;
3976 }
3977
3978 static bool encoders_cloneable(const struct intel_encoder *a,
3979                                const struct intel_encoder *b)
3980 {
3981         /* masks could be asymmetric, so check both ways */
3982         return a == b || (a->cloneable & BIT(b->type) &&
3983                           b->cloneable & BIT(a->type));
3984 }
3985
3986 static bool check_single_encoder_cloning(struct intel_atomic_state *state,
3987                                          struct intel_crtc *crtc,
3988                                          struct intel_encoder *encoder)
3989 {
3990         struct intel_encoder *source_encoder;
3991         struct drm_connector *connector;
3992         struct drm_connector_state *connector_state;
3993         int i;
3994
3995         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
3996                 if (connector_state->crtc != &crtc->base)
3997                         continue;
3998
3999                 source_encoder =
4000                         to_intel_encoder(connector_state->best_encoder);
4001                 if (!encoders_cloneable(encoder, source_encoder))
4002                         return false;
4003         }
4004
4005         return true;
4006 }
4007
4008 static int icl_add_linked_planes(struct intel_atomic_state *state)
4009 {
4010         struct intel_plane *plane, *linked;
4011         struct intel_plane_state *plane_state, *linked_plane_state;
4012         int i;
4013
4014         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4015                 linked = plane_state->planar_linked_plane;
4016
4017                 if (!linked)
4018                         continue;
4019
4020                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
4021                 if (IS_ERR(linked_plane_state))
4022                         return PTR_ERR(linked_plane_state);
4023
4024                 drm_WARN_ON(state->base.dev,
4025                             linked_plane_state->planar_linked_plane != plane);
4026                 drm_WARN_ON(state->base.dev,
4027                             linked_plane_state->planar_slave == plane_state->planar_slave);
4028         }
4029
4030         return 0;
4031 }
4032
4033 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
4034 {
4035         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4036         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4037         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
4038         struct intel_plane *plane, *linked;
4039         struct intel_plane_state *plane_state;
4040         int i;
4041
4042         if (DISPLAY_VER(dev_priv) < 11)
4043                 return 0;
4044
4045         /*
4046          * Destroy all old plane links and make the slave plane invisible
4047          * in the crtc_state->active_planes mask.
4048          */
4049         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4050                 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
4051                         continue;
4052
4053                 plane_state->planar_linked_plane = NULL;
4054                 if (plane_state->planar_slave && !plane_state->uapi.visible) {
4055                         crtc_state->enabled_planes &= ~BIT(plane->id);
4056                         crtc_state->active_planes &= ~BIT(plane->id);
4057                         crtc_state->update_planes |= BIT(plane->id);
4058                         crtc_state->data_rate[plane->id] = 0;
4059                         crtc_state->rel_data_rate[plane->id] = 0;
4060                 }
4061
4062                 plane_state->planar_slave = false;
4063         }
4064
4065         if (!crtc_state->nv12_planes)
4066                 return 0;
4067
4068         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4069                 struct intel_plane_state *linked_state = NULL;
4070
4071                 if (plane->pipe != crtc->pipe ||
4072                     !(crtc_state->nv12_planes & BIT(plane->id)))
4073                         continue;
4074
4075                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
4076                         if (!icl_is_nv12_y_plane(dev_priv, linked->id))
4077                                 continue;
4078
4079                         if (crtc_state->active_planes & BIT(linked->id))
4080                                 continue;
4081
4082                         linked_state = intel_atomic_get_plane_state(state, linked);
4083                         if (IS_ERR(linked_state))
4084                                 return PTR_ERR(linked_state);
4085
4086                         break;
4087                 }
4088
4089                 if (!linked_state) {
4090                         drm_dbg_kms(&dev_priv->drm,
4091                                     "Need %d free Y planes for planar YUV\n",
4092                                     hweight8(crtc_state->nv12_planes));
4093
4094                         return -EINVAL;
4095                 }
4096
4097                 plane_state->planar_linked_plane = linked;
4098
4099                 linked_state->planar_slave = true;
4100                 linked_state->planar_linked_plane = plane;
4101                 crtc_state->enabled_planes |= BIT(linked->id);
4102                 crtc_state->active_planes |= BIT(linked->id);
4103                 crtc_state->update_planes |= BIT(linked->id);
4104                 crtc_state->data_rate[linked->id] =
4105                         crtc_state->data_rate_y[plane->id];
4106                 crtc_state->rel_data_rate[linked->id] =
4107                         crtc_state->rel_data_rate_y[plane->id];
4108                 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
4109                             linked->base.name, plane->base.name);
4110
4111                 /* Copy parameters to slave plane */
4112                 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
4113                 linked_state->color_ctl = plane_state->color_ctl;
4114                 linked_state->view = plane_state->view;
4115                 linked_state->decrypt = plane_state->decrypt;
4116
4117                 intel_plane_copy_hw_state(linked_state, plane_state);
4118                 linked_state->uapi.src = plane_state->uapi.src;
4119                 linked_state->uapi.dst = plane_state->uapi.dst;
4120
4121                 if (icl_is_hdr_plane(dev_priv, plane->id)) {
4122                         if (linked->id == PLANE_SPRITE5)
4123                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
4124                         else if (linked->id == PLANE_SPRITE4)
4125                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
4126                         else if (linked->id == PLANE_SPRITE3)
4127                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
4128                         else if (linked->id == PLANE_SPRITE2)
4129                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
4130                         else
4131                                 MISSING_CASE(linked->id);
4132                 }
4133         }
4134
4135         return 0;
4136 }
4137
4138 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
4139 {
4140         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
4141         struct intel_atomic_state *state =
4142                 to_intel_atomic_state(new_crtc_state->uapi.state);
4143         const struct intel_crtc_state *old_crtc_state =
4144                 intel_atomic_get_old_crtc_state(state, crtc);
4145
4146         return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
4147 }
4148
4149 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
4150 {
4151         const struct drm_display_mode *pipe_mode =
4152                 &crtc_state->hw.pipe_mode;
4153         int linetime_wm;
4154
4155         if (!crtc_state->hw.enable)
4156                 return 0;
4157
4158         linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4159                                         pipe_mode->crtc_clock);
4160
4161         return min(linetime_wm, 0x1ff);
4162 }
4163
4164 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
4165                                const struct intel_cdclk_state *cdclk_state)
4166 {
4167         const struct drm_display_mode *pipe_mode =
4168                 &crtc_state->hw.pipe_mode;
4169         int linetime_wm;
4170
4171         if (!crtc_state->hw.enable)
4172                 return 0;
4173
4174         linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4175                                         cdclk_state->logical.cdclk);
4176
4177         return min(linetime_wm, 0x1ff);
4178 }
4179
4180 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
4181 {
4182         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4183         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4184         const struct drm_display_mode *pipe_mode =
4185                 &crtc_state->hw.pipe_mode;
4186         int linetime_wm;
4187
4188         if (!crtc_state->hw.enable)
4189                 return 0;
4190
4191         linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
4192                                    crtc_state->pixel_rate);
4193
4194         /* Display WA #1135: BXT:ALL GLK:ALL */
4195         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
4196             skl_watermark_ipc_enabled(dev_priv))
4197                 linetime_wm /= 2;
4198
4199         return min(linetime_wm, 0x1ff);
4200 }
4201
4202 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
4203                                    struct intel_crtc *crtc)
4204 {
4205         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4206         struct intel_crtc_state *crtc_state =
4207                 intel_atomic_get_new_crtc_state(state, crtc);
4208         const struct intel_cdclk_state *cdclk_state;
4209
4210         if (DISPLAY_VER(dev_priv) >= 9)
4211                 crtc_state->linetime = skl_linetime_wm(crtc_state);
4212         else
4213                 crtc_state->linetime = hsw_linetime_wm(crtc_state);
4214
4215         if (!hsw_crtc_supports_ips(crtc))
4216                 return 0;
4217
4218         cdclk_state = intel_atomic_get_cdclk_state(state);
4219         if (IS_ERR(cdclk_state))
4220                 return PTR_ERR(cdclk_state);
4221
4222         crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
4223                                                        cdclk_state);
4224
4225         return 0;
4226 }
4227
4228 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
4229                                    struct intel_crtc *crtc)
4230 {
4231         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4232         struct intel_crtc_state *crtc_state =
4233                 intel_atomic_get_new_crtc_state(state, crtc);
4234         int ret;
4235
4236         if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) &&
4237             intel_crtc_needs_modeset(crtc_state) &&
4238             !crtc_state->hw.active)
4239                 crtc_state->update_wm_post = true;
4240
4241         if (intel_crtc_needs_modeset(crtc_state)) {
4242                 ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
4243                 if (ret)
4244                         return ret;
4245         }
4246
4247         /*
4248          * May need to update pipe gamma enable bits
4249          * when C8 planes are getting enabled/disabled.
4250          */
4251         if (c8_planes_changed(crtc_state))
4252                 crtc_state->uapi.color_mgmt_changed = true;
4253
4254         if (intel_crtc_needs_color_update(crtc_state)) {
4255                 ret = intel_color_check(crtc_state);
4256                 if (ret)
4257                         return ret;
4258         }
4259
4260         ret = intel_compute_pipe_wm(state, crtc);
4261         if (ret) {
4262                 drm_dbg_kms(&dev_priv->drm,
4263                             "Target pipe watermarks are invalid\n");
4264                 return ret;
4265         }
4266
4267         /*
4268          * Calculate 'intermediate' watermarks that satisfy both the
4269          * old state and the new state.  We can program these
4270          * immediately.
4271          */
4272         ret = intel_compute_intermediate_wm(state, crtc);
4273         if (ret) {
4274                 drm_dbg_kms(&dev_priv->drm,
4275                             "No valid intermediate pipe watermarks are possible\n");
4276                 return ret;
4277         }
4278
4279         if (DISPLAY_VER(dev_priv) >= 9) {
4280                 if (intel_crtc_needs_modeset(crtc_state) ||
4281                     intel_crtc_needs_fastset(crtc_state)) {
4282                         ret = skl_update_scaler_crtc(crtc_state);
4283                         if (ret)
4284                                 return ret;
4285                 }
4286
4287                 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
4288                 if (ret)
4289                         return ret;
4290         }
4291
4292         if (HAS_IPS(dev_priv)) {
4293                 ret = hsw_ips_compute_config(state, crtc);
4294                 if (ret)
4295                         return ret;
4296         }
4297
4298         if (DISPLAY_VER(dev_priv) >= 9 ||
4299             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4300                 ret = hsw_compute_linetime_wm(state, crtc);
4301                 if (ret)
4302                         return ret;
4303
4304         }
4305
4306         ret = intel_psr2_sel_fetch_update(state, crtc);
4307         if (ret)
4308                 return ret;
4309
4310         return 0;
4311 }
4312
4313 static int
4314 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
4315                       struct intel_crtc_state *crtc_state)
4316 {
4317         struct drm_connector *connector = conn_state->connector;
4318         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
4319         const struct drm_display_info *info = &connector->display_info;
4320         int bpp;
4321
4322         switch (conn_state->max_bpc) {
4323         case 6 ... 7:
4324                 bpp = 6 * 3;
4325                 break;
4326         case 8 ... 9:
4327                 bpp = 8 * 3;
4328                 break;
4329         case 10 ... 11:
4330                 bpp = 10 * 3;
4331                 break;
4332         case 12 ... 16:
4333                 bpp = 12 * 3;
4334                 break;
4335         default:
4336                 MISSING_CASE(conn_state->max_bpc);
4337                 return -EINVAL;
4338         }
4339
4340         if (bpp < crtc_state->pipe_bpp) {
4341                 drm_dbg_kms(&i915->drm,
4342                             "[CONNECTOR:%d:%s] Limiting display bpp to %d "
4343                             "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
4344                             connector->base.id, connector->name,
4345                             bpp, 3 * info->bpc,
4346                             3 * conn_state->max_requested_bpc,
4347                             crtc_state->pipe_bpp);
4348
4349                 crtc_state->pipe_bpp = bpp;
4350         }
4351
4352         return 0;
4353 }
4354
4355 static int
4356 compute_baseline_pipe_bpp(struct intel_atomic_state *state,
4357                           struct intel_crtc *crtc)
4358 {
4359         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4360         struct intel_crtc_state *crtc_state =
4361                 intel_atomic_get_new_crtc_state(state, crtc);
4362         struct drm_connector *connector;
4363         struct drm_connector_state *connector_state;
4364         int bpp, i;
4365
4366         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
4367             IS_CHERRYVIEW(dev_priv)))
4368                 bpp = 10*3;
4369         else if (DISPLAY_VER(dev_priv) >= 5)
4370                 bpp = 12*3;
4371         else
4372                 bpp = 8*3;
4373
4374         crtc_state->pipe_bpp = bpp;
4375
4376         /* Clamp display bpp to connector max bpp */
4377         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4378                 int ret;
4379
4380                 if (connector_state->crtc != &crtc->base)
4381                         continue;
4382
4383                 ret = compute_sink_pipe_bpp(connector_state, crtc_state);
4384                 if (ret)
4385                         return ret;
4386         }
4387
4388         return 0;
4389 }
4390
4391 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
4392 {
4393         struct drm_device *dev = state->base.dev;
4394         struct drm_connector *connector;
4395         struct drm_connector_list_iter conn_iter;
4396         unsigned int used_ports = 0;
4397         unsigned int used_mst_ports = 0;
4398         bool ret = true;
4399
4400         /*
4401          * We're going to peek into connector->state,
4402          * hence connection_mutex must be held.
4403          */
4404         drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
4405
4406         /*
4407          * Walk the connector list instead of the encoder
4408          * list to detect the problem on ddi platforms
4409          * where there's just one encoder per digital port.
4410          */
4411         drm_connector_list_iter_begin(dev, &conn_iter);
4412         drm_for_each_connector_iter(connector, &conn_iter) {
4413                 struct drm_connector_state *connector_state;
4414                 struct intel_encoder *encoder;
4415
4416                 connector_state =
4417                         drm_atomic_get_new_connector_state(&state->base,
4418                                                            connector);
4419                 if (!connector_state)
4420                         connector_state = connector->state;
4421
4422                 if (!connector_state->best_encoder)
4423                         continue;
4424
4425                 encoder = to_intel_encoder(connector_state->best_encoder);
4426
4427                 drm_WARN_ON(dev, !connector_state->crtc);
4428
4429                 switch (encoder->type) {
4430                 case INTEL_OUTPUT_DDI:
4431                         if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
4432                                 break;
4433                         fallthrough;
4434                 case INTEL_OUTPUT_DP:
4435                 case INTEL_OUTPUT_HDMI:
4436                 case INTEL_OUTPUT_EDP:
4437                         /* the same port mustn't appear more than once */
4438                         if (used_ports & BIT(encoder->port))
4439                                 ret = false;
4440
4441                         used_ports |= BIT(encoder->port);
4442                         break;
4443                 case INTEL_OUTPUT_DP_MST:
4444                         used_mst_ports |=
4445                                 1 << encoder->port;
4446                         break;
4447                 default:
4448                         break;
4449                 }
4450         }
4451         drm_connector_list_iter_end(&conn_iter);
4452
4453         /* can't mix MST and SST/HDMI on the same port */
4454         if (used_ports & used_mst_ports)
4455                 return false;
4456
4457         return ret;
4458 }
4459
4460 static void
4461 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
4462                                            struct intel_crtc *crtc)
4463 {
4464         struct intel_crtc_state *crtc_state =
4465                 intel_atomic_get_new_crtc_state(state, crtc);
4466
4467         WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
4468
4469         drm_property_replace_blob(&crtc_state->hw.degamma_lut,
4470                                   crtc_state->uapi.degamma_lut);
4471         drm_property_replace_blob(&crtc_state->hw.gamma_lut,
4472                                   crtc_state->uapi.gamma_lut);
4473         drm_property_replace_blob(&crtc_state->hw.ctm,
4474                                   crtc_state->uapi.ctm);
4475 }
4476
4477 static void
4478 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
4479                                          struct intel_crtc *crtc)
4480 {
4481         struct intel_crtc_state *crtc_state =
4482                 intel_atomic_get_new_crtc_state(state, crtc);
4483
4484         WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
4485
4486         crtc_state->hw.enable = crtc_state->uapi.enable;
4487         crtc_state->hw.active = crtc_state->uapi.active;
4488         drm_mode_copy(&crtc_state->hw.mode,
4489                       &crtc_state->uapi.mode);
4490         drm_mode_copy(&crtc_state->hw.adjusted_mode,
4491                       &crtc_state->uapi.adjusted_mode);
4492         crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
4493
4494         intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
4495 }
4496
4497 static void
4498 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state,
4499                                     struct intel_crtc *slave_crtc)
4500 {
4501         struct intel_crtc_state *slave_crtc_state =
4502                 intel_atomic_get_new_crtc_state(state, slave_crtc);
4503         struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
4504         const struct intel_crtc_state *master_crtc_state =
4505                 intel_atomic_get_new_crtc_state(state, master_crtc);
4506
4507         drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut,
4508                                   master_crtc_state->hw.degamma_lut);
4509         drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut,
4510                                   master_crtc_state->hw.gamma_lut);
4511         drm_property_replace_blob(&slave_crtc_state->hw.ctm,
4512                                   master_crtc_state->hw.ctm);
4513
4514         slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed;
4515 }
4516
4517 static int
4518 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state,
4519                                   struct intel_crtc *slave_crtc)
4520 {
4521         struct intel_crtc_state *slave_crtc_state =
4522                 intel_atomic_get_new_crtc_state(state, slave_crtc);
4523         struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
4524         const struct intel_crtc_state *master_crtc_state =
4525                 intel_atomic_get_new_crtc_state(state, master_crtc);
4526         struct intel_crtc_state *saved_state;
4527
4528         WARN_ON(master_crtc_state->bigjoiner_pipes !=
4529                 slave_crtc_state->bigjoiner_pipes);
4530
4531         saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL);
4532         if (!saved_state)
4533                 return -ENOMEM;
4534
4535         /* preserve some things from the slave's original crtc state */
4536         saved_state->uapi = slave_crtc_state->uapi;
4537         saved_state->scaler_state = slave_crtc_state->scaler_state;
4538         saved_state->shared_dpll = slave_crtc_state->shared_dpll;
4539         saved_state->crc_enabled = slave_crtc_state->crc_enabled;
4540
4541         intel_crtc_free_hw_state(slave_crtc_state);
4542         if (slave_crtc_state->dp_tunnel_ref.tunnel)
4543                 drm_dp_tunnel_ref_put(&slave_crtc_state->dp_tunnel_ref);
4544         memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state));
4545         kfree(saved_state);
4546
4547         /* Re-init hw state */
4548         memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw));
4549         slave_crtc_state->hw.enable = master_crtc_state->hw.enable;
4550         slave_crtc_state->hw.active = master_crtc_state->hw.active;
4551         drm_mode_copy(&slave_crtc_state->hw.mode,
4552                       &master_crtc_state->hw.mode);
4553         drm_mode_copy(&slave_crtc_state->hw.pipe_mode,
4554                       &master_crtc_state->hw.pipe_mode);
4555         drm_mode_copy(&slave_crtc_state->hw.adjusted_mode,
4556                       &master_crtc_state->hw.adjusted_mode);
4557         slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter;
4558
4559         if (master_crtc_state->dp_tunnel_ref.tunnel)
4560                 drm_dp_tunnel_ref_get(master_crtc_state->dp_tunnel_ref.tunnel,
4561                                       &slave_crtc_state->dp_tunnel_ref);
4562
4563         copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc);
4564
4565         slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed;
4566         slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed;
4567         slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed;
4568
4569         WARN_ON(master_crtc_state->bigjoiner_pipes !=
4570                 slave_crtc_state->bigjoiner_pipes);
4571
4572         return 0;
4573 }
4574
4575 static int
4576 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
4577                                  struct intel_crtc *crtc)
4578 {
4579         struct intel_crtc_state *crtc_state =
4580                 intel_atomic_get_new_crtc_state(state, crtc);
4581         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4582         struct intel_crtc_state *saved_state;
4583
4584         saved_state = intel_crtc_state_alloc(crtc);
4585         if (!saved_state)
4586                 return -ENOMEM;
4587
4588         /* free the old crtc_state->hw members */
4589         intel_crtc_free_hw_state(crtc_state);
4590
4591         intel_dp_tunnel_atomic_clear_stream_bw(state, crtc_state);
4592
4593         /* FIXME: before the switch to atomic started, a new pipe_config was
4594          * kzalloc'd. Code that depends on any field being zero should be
4595          * fixed, so that the crtc_state can be safely duplicated. For now,
4596          * only fields that are know to not cause problems are preserved. */
4597
4598         saved_state->uapi = crtc_state->uapi;
4599         saved_state->inherited = crtc_state->inherited;
4600         saved_state->scaler_state = crtc_state->scaler_state;
4601         saved_state->shared_dpll = crtc_state->shared_dpll;
4602         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
4603         memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
4604                sizeof(saved_state->icl_port_dplls));
4605         saved_state->crc_enabled = crtc_state->crc_enabled;
4606         if (IS_G4X(dev_priv) ||
4607             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4608                 saved_state->wm = crtc_state->wm;
4609
4610         memcpy(crtc_state, saved_state, sizeof(*crtc_state));
4611         kfree(saved_state);
4612
4613         intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc);
4614
4615         return 0;
4616 }
4617
4618 static int
4619 intel_modeset_pipe_config(struct intel_atomic_state *state,
4620                           struct intel_crtc *crtc,
4621                           const struct intel_link_bw_limits *limits)
4622 {
4623         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4624         struct intel_crtc_state *crtc_state =
4625                 intel_atomic_get_new_crtc_state(state, crtc);
4626         struct drm_connector *connector;
4627         struct drm_connector_state *connector_state;
4628         int pipe_src_w, pipe_src_h;
4629         int base_bpp, ret, i;
4630
4631         crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
4632
4633         crtc_state->framestart_delay = 1;
4634
4635         /*
4636          * Sanitize sync polarity flags based on requested ones. If neither
4637          * positive or negative polarity is requested, treat this as meaning
4638          * negative polarity.
4639          */
4640         if (!(crtc_state->hw.adjusted_mode.flags &
4641               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
4642                 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
4643
4644         if (!(crtc_state->hw.adjusted_mode.flags &
4645               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
4646                 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
4647
4648         ret = compute_baseline_pipe_bpp(state, crtc);
4649         if (ret)
4650                 return ret;
4651
4652         crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe);
4653         crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
4654
4655         if (crtc_state->pipe_bpp > to_bpp_int(crtc_state->max_link_bpp_x16)) {
4656                 drm_dbg_kms(&i915->drm,
4657                             "[CRTC:%d:%s] Link bpp limited to " BPP_X16_FMT "\n",
4658                             crtc->base.base.id, crtc->base.name,
4659                             BPP_X16_ARGS(crtc_state->max_link_bpp_x16));
4660                 crtc_state->bw_constrained = true;
4661         }
4662
4663         base_bpp = crtc_state->pipe_bpp;
4664
4665         /*
4666          * Determine the real pipe dimensions. Note that stereo modes can
4667          * increase the actual pipe size due to the frame doubling and
4668          * insertion of additional space for blanks between the frame. This
4669          * is stored in the crtc timings. We use the requested mode to do this
4670          * computation to clearly distinguish it from the adjusted mode, which
4671          * can be changed by the connectors in the below retry loop.
4672          */
4673         drm_mode_get_hv_timing(&crtc_state->hw.mode,
4674                                &pipe_src_w, &pipe_src_h);
4675         drm_rect_init(&crtc_state->pipe_src, 0, 0,
4676                       pipe_src_w, pipe_src_h);
4677
4678         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4679                 struct intel_encoder *encoder =
4680                         to_intel_encoder(connector_state->best_encoder);
4681
4682                 if (connector_state->crtc != &crtc->base)
4683                         continue;
4684
4685                 if (!check_single_encoder_cloning(state, crtc, encoder)) {
4686                         drm_dbg_kms(&i915->drm,
4687                                     "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
4688                                     encoder->base.base.id, encoder->base.name);
4689                         return -EINVAL;
4690                 }
4691
4692                 /*
4693                  * Determine output_types before calling the .compute_config()
4694                  * hooks so that the hooks can use this information safely.
4695                  */
4696                 if (encoder->compute_output_type)
4697                         crtc_state->output_types |=
4698                                 BIT(encoder->compute_output_type(encoder, crtc_state,
4699                                                                  connector_state));
4700                 else
4701                         crtc_state->output_types |= BIT(encoder->type);
4702         }
4703
4704         /* Ensure the port clock defaults are reset when retrying. */
4705         crtc_state->port_clock = 0;
4706         crtc_state->pixel_multiplier = 1;
4707
4708         /* Fill in default crtc timings, allow encoders to overwrite them. */
4709         drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,
4710                               CRTC_STEREO_DOUBLE);
4711
4712         /* Pass our mode to the connectors and the CRTC to give them a chance to
4713          * adjust it according to limitations or connector properties, and also
4714          * a chance to reject the mode entirely.
4715          */
4716         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4717                 struct intel_encoder *encoder =
4718                         to_intel_encoder(connector_state->best_encoder);
4719
4720                 if (connector_state->crtc != &crtc->base)
4721                         continue;
4722
4723                 ret = encoder->compute_config(encoder, crtc_state,
4724                                               connector_state);
4725                 if (ret == -EDEADLK)
4726                         return ret;
4727                 if (ret < 0) {
4728                         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n",
4729                                     encoder->base.base.id, encoder->base.name, ret);
4730                         return ret;
4731                 }
4732         }
4733
4734         /* Set default port clock if not overwritten by the encoder. Needs to be
4735          * done afterwards in case the encoder adjusts the mode. */
4736         if (!crtc_state->port_clock)
4737                 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
4738                         * crtc_state->pixel_multiplier;
4739
4740         ret = intel_crtc_compute_config(state, crtc);
4741         if (ret == -EDEADLK)
4742                 return ret;
4743         if (ret < 0) {
4744                 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
4745                             crtc->base.base.id, crtc->base.name, ret);
4746                 return ret;
4747         }
4748
4749         /* Dithering seems to not pass-through bits correctly when it should, so
4750          * only enable it on 6bpc panels and when its not a compliance
4751          * test requesting 6bpc video pattern.
4752          */
4753         crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
4754                 !crtc_state->dither_force_disable;
4755         drm_dbg_kms(&i915->drm,
4756                     "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
4757                     crtc->base.base.id, crtc->base.name,
4758                     base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
4759
4760         return 0;
4761 }
4762
4763 static int
4764 intel_modeset_pipe_config_late(struct intel_atomic_state *state,
4765                                struct intel_crtc *crtc)
4766 {
4767         struct intel_crtc_state *crtc_state =
4768                 intel_atomic_get_new_crtc_state(state, crtc);
4769         struct drm_connector_state *conn_state;
4770         struct drm_connector *connector;
4771         int i;
4772
4773         for_each_new_connector_in_state(&state->base, connector,
4774                                         conn_state, i) {
4775                 struct intel_encoder *encoder =
4776                         to_intel_encoder(conn_state->best_encoder);
4777                 int ret;
4778
4779                 if (conn_state->crtc != &crtc->base ||
4780                     !encoder->compute_config_late)
4781                         continue;
4782
4783                 ret = encoder->compute_config_late(encoder, crtc_state,
4784                                                    conn_state);
4785                 if (ret)
4786                         return ret;
4787         }
4788
4789         return 0;
4790 }
4791
4792 bool intel_fuzzy_clock_check(int clock1, int clock2)
4793 {
4794         int diff;
4795
4796         if (clock1 == clock2)
4797                 return true;
4798
4799         if (!clock1 || !clock2)
4800                 return false;
4801
4802         diff = abs(clock1 - clock2);
4803
4804         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
4805                 return true;
4806
4807         return false;
4808 }
4809
4810 static bool
4811 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
4812                        const struct intel_link_m_n *m2_n2)
4813 {
4814         return m_n->tu == m2_n2->tu &&
4815                 m_n->data_m == m2_n2->data_m &&
4816                 m_n->data_n == m2_n2->data_n &&
4817                 m_n->link_m == m2_n2->link_m &&
4818                 m_n->link_n == m2_n2->link_n;
4819 }
4820
4821 static bool
4822 intel_compare_infoframe(const union hdmi_infoframe *a,
4823                         const union hdmi_infoframe *b)
4824 {
4825         return memcmp(a, b, sizeof(*a)) == 0;
4826 }
4827
4828 static bool
4829 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
4830                          const struct drm_dp_vsc_sdp *b)
4831 {
4832         return a->pixelformat == b->pixelformat &&
4833                 a->colorimetry == b->colorimetry &&
4834                 a->bpc == b->bpc &&
4835                 a->dynamic_range == b->dynamic_range &&
4836                 a->content_type == b->content_type;
4837 }
4838
4839 static bool
4840 intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
4841                         const struct drm_dp_as_sdp *b)
4842 {
4843         return a->vtotal == b->vtotal &&
4844                 a->target_rr == b->target_rr &&
4845                 a->duration_incr_ms == b->duration_incr_ms &&
4846                 a->duration_decr_ms == b->duration_decr_ms &&
4847                 a->mode == b->mode;
4848 }
4849
4850 static bool
4851 intel_compare_buffer(const u8 *a, const u8 *b, size_t len)
4852 {
4853         return memcmp(a, b, len) == 0;
4854 }
4855
4856 static void __printf(5, 6)
4857 pipe_config_mismatch(struct drm_printer *p, bool fastset,
4858                      const struct intel_crtc *crtc,
4859                      const char *name, const char *format, ...)
4860 {
4861         struct va_format vaf;
4862         va_list args;
4863
4864         va_start(args, format);
4865         vaf.fmt = format;
4866         vaf.va = &args;
4867
4868         if (fastset)
4869                 drm_printf(p, "[CRTC:%d:%s] fastset requirement not met in %s %pV\n",
4870                            crtc->base.base.id, crtc->base.name, name, &vaf);
4871         else
4872                 drm_printf(p, "[CRTC:%d:%s] mismatch in %s %pV\n",
4873                            crtc->base.base.id, crtc->base.name, name, &vaf);
4874
4875         va_end(args);
4876 }
4877
4878 static void
4879 pipe_config_infoframe_mismatch(struct drm_printer *p, bool fastset,
4880                                const struct intel_crtc *crtc,
4881                                const char *name,
4882                                const union hdmi_infoframe *a,
4883                                const union hdmi_infoframe *b)
4884 {
4885         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4886         const char *loglevel;
4887
4888         if (fastset) {
4889                 if (!drm_debug_enabled(DRM_UT_KMS))
4890                         return;
4891
4892                 loglevel = KERN_DEBUG;
4893         } else {
4894                 loglevel = KERN_ERR;
4895         }
4896
4897         pipe_config_mismatch(p, fastset, crtc, name, "infoframe");
4898
4899         drm_printf(p, "expected:\n");
4900         hdmi_infoframe_log(loglevel, i915->drm.dev, a);
4901         drm_printf(p, "found:\n");
4902         hdmi_infoframe_log(loglevel, i915->drm.dev, b);
4903 }
4904
4905 static void
4906 pipe_config_dp_vsc_sdp_mismatch(struct drm_printer *p, bool fastset,
4907                                 const struct intel_crtc *crtc,
4908                                 const char *name,
4909                                 const struct drm_dp_vsc_sdp *a,
4910                                 const struct drm_dp_vsc_sdp *b)
4911 {
4912         pipe_config_mismatch(p, fastset, crtc, name, "dp sdp");
4913
4914         drm_printf(p, "expected:\n");
4915         drm_dp_vsc_sdp_log(p, a);
4916         drm_printf(p, "found:\n");
4917         drm_dp_vsc_sdp_log(p, b);
4918 }
4919
4920 static void
4921 pipe_config_dp_as_sdp_mismatch(struct drm_i915_private *i915,
4922                                bool fastset, const char *name,
4923                                const struct drm_dp_as_sdp *a,
4924                                const struct drm_dp_as_sdp *b)
4925 {
4926         struct drm_printer p;
4927
4928         if (fastset) {
4929                 p = drm_dbg_printer(&i915->drm, DRM_UT_KMS, NULL);
4930
4931                 drm_printf(&p, "fastset requirement not met in %s dp sdp\n", name);
4932         } else {
4933                 p = drm_err_printer(&i915->drm, NULL);
4934
4935                 drm_printf(&p, "mismatch in %s dp sdp\n", name);
4936         }
4937
4938         drm_printf(&p, "expected:\n");
4939         drm_dp_as_sdp_log(&p, a);
4940         drm_printf(&p, "found:\n");
4941         drm_dp_as_sdp_log(&p, b);
4942 }
4943
4944 /* Returns the length up to and including the last differing byte */
4945 static size_t
4946 memcmp_diff_len(const u8 *a, const u8 *b, size_t len)
4947 {
4948         int i;
4949
4950         for (i = len - 1; i >= 0; i--) {
4951                 if (a[i] != b[i])
4952                         return i + 1;
4953         }
4954
4955         return 0;
4956 }
4957
4958 static void
4959 pipe_config_buffer_mismatch(struct drm_printer *p, bool fastset,
4960                             const struct intel_crtc *crtc,
4961                             const char *name,
4962                             const u8 *a, const u8 *b, size_t len)
4963 {
4964         const char *loglevel;
4965
4966         if (fastset) {
4967                 if (!drm_debug_enabled(DRM_UT_KMS))
4968                         return;
4969
4970                 loglevel = KERN_DEBUG;
4971         } else {
4972                 loglevel = KERN_ERR;
4973         }
4974
4975         pipe_config_mismatch(p, fastset, crtc, name, "buffer");
4976
4977         /* only dump up to the last difference */
4978         len = memcmp_diff_len(a, b, len);
4979
4980         print_hex_dump(loglevel, "expected: ", DUMP_PREFIX_NONE,
4981                        16, 0, a, len, false);
4982         print_hex_dump(loglevel, "found: ", DUMP_PREFIX_NONE,
4983                        16, 0, b, len, false);
4984 }
4985
4986 static void
4987 pipe_config_pll_mismatch(struct drm_printer *p, bool fastset,
4988                          const struct intel_crtc *crtc,
4989                          const char *name,
4990                          const struct intel_dpll_hw_state *a,
4991                          const struct intel_dpll_hw_state *b)
4992 {
4993         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4994
4995         pipe_config_mismatch(p, fastset, crtc, name, " "); /* stupid -Werror=format-zero-length */
4996
4997         drm_printf(p, "expected:\n");
4998         intel_dpll_dump_hw_state(i915, p, a);
4999         drm_printf(p, "found:\n");
5000         intel_dpll_dump_hw_state(i915, p, b);
5001 }
5002
5003 bool
5004 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
5005                           const struct intel_crtc_state *pipe_config,
5006                           bool fastset)
5007 {
5008         struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
5009         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
5010         struct drm_printer p;
5011         bool ret = true;
5012
5013         if (fastset)
5014                 p = drm_dbg_printer(&dev_priv->drm, DRM_UT_KMS, NULL);
5015         else
5016                 p = drm_err_printer(&dev_priv->drm, NULL);
5017
5018 #define PIPE_CONF_CHECK_X(name) do { \
5019         if (current_config->name != pipe_config->name) { \
5020                 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
5021                                  __stringify(name) " is bool"); \
5022                 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5023                                      "(expected 0x%08x, found 0x%08x)", \
5024                                      current_config->name, \
5025                                      pipe_config->name); \
5026                 ret = false; \
5027         } \
5028 } while (0)
5029
5030 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
5031         if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
5032                 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
5033                                  __stringify(name) " is bool"); \
5034                 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5035                                      "(expected 0x%08x, found 0x%08x)", \
5036                                      current_config->name & (mask), \
5037                                      pipe_config->name & (mask)); \
5038                 ret = false; \
5039         } \
5040 } while (0)
5041
5042 #define PIPE_CONF_CHECK_I(name) do { \
5043         if (current_config->name != pipe_config->name) { \
5044                 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
5045                                  __stringify(name) " is bool"); \
5046                 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5047                                      "(expected %i, found %i)", \
5048                                      current_config->name, \
5049                                      pipe_config->name); \
5050                 ret = false; \
5051         } \
5052 } while (0)
5053
5054 #define PIPE_CONF_CHECK_BOOL(name) do { \
5055         if (current_config->name != pipe_config->name) { \
5056                 BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
5057                                  __stringify(name) " is not bool");     \
5058                 pipe_config_mismatch(&p, fastset, crtc,  __stringify(name), \
5059                                      "(expected %s, found %s)", \
5060                                      str_yes_no(current_config->name), \
5061                                      str_yes_no(pipe_config->name)); \
5062                 ret = false; \
5063         } \
5064 } while (0)
5065
5066 #define PIPE_CONF_CHECK_P(name) do { \
5067         if (current_config->name != pipe_config->name) { \
5068                 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5069                                      "(expected %p, found %p)", \
5070                                      current_config->name, \
5071                                      pipe_config->name); \
5072                 ret = false; \
5073         } \
5074 } while (0)
5075
5076 #define PIPE_CONF_CHECK_M_N(name) do { \
5077         if (!intel_compare_link_m_n(&current_config->name, \
5078                                     &pipe_config->name)) { \
5079                 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5080                                      "(expected tu %i data %i/%i link %i/%i, " \
5081                                      "found tu %i, data %i/%i link %i/%i)", \
5082                                      current_config->name.tu, \
5083                                      current_config->name.data_m, \
5084                                      current_config->name.data_n, \
5085                                      current_config->name.link_m, \
5086                                      current_config->name.link_n, \
5087                                      pipe_config->name.tu, \
5088                                      pipe_config->name.data_m, \
5089                                      pipe_config->name.data_n, \
5090                                      pipe_config->name.link_m, \
5091                                      pipe_config->name.link_n); \
5092                 ret = false; \
5093         } \
5094 } while (0)
5095
5096 #define PIPE_CONF_CHECK_PLL(name) do { \
5097         if (!intel_dpll_compare_hw_state(dev_priv, &current_config->name, \
5098                                          &pipe_config->name)) { \
5099                 pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \
5100                                          &current_config->name, \
5101                                          &pipe_config->name); \
5102                 ret = false; \
5103         } \
5104 } while (0)
5105
5106 #define PIPE_CONF_CHECK_TIMINGS(name) do {     \
5107         PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
5108         PIPE_CONF_CHECK_I(name.crtc_htotal); \
5109         PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
5110         PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
5111         PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
5112         PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
5113         PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
5114         PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
5115         PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
5116         PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
5117         if (!fastset || !pipe_config->update_lrr) { \
5118                 PIPE_CONF_CHECK_I(name.crtc_vtotal); \
5119                 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
5120         } \
5121 } while (0)
5122
5123 #define PIPE_CONF_CHECK_RECT(name) do { \
5124         PIPE_CONF_CHECK_I(name.x1); \
5125         PIPE_CONF_CHECK_I(name.x2); \
5126         PIPE_CONF_CHECK_I(name.y1); \
5127         PIPE_CONF_CHECK_I(name.y2); \
5128 } while (0)
5129
5130 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
5131         if ((current_config->name ^ pipe_config->name) & (mask)) { \
5132                 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5133                                      "(%x) (expected %i, found %i)", \
5134                                      (mask), \
5135                                      current_config->name & (mask), \
5136                                      pipe_config->name & (mask)); \
5137                 ret = false; \
5138         } \
5139 } while (0)
5140
5141 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
5142         if (!intel_compare_infoframe(&current_config->infoframes.name, \
5143                                      &pipe_config->infoframes.name)) { \
5144                 pipe_config_infoframe_mismatch(&p, fastset, crtc, __stringify(name), \
5145                                                &current_config->infoframes.name, \
5146                                                &pipe_config->infoframes.name); \
5147                 ret = false; \
5148         } \
5149 } while (0)
5150
5151 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
5152         if (!intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
5153                                       &pipe_config->infoframes.name)) { \
5154                 pipe_config_dp_vsc_sdp_mismatch(&p, fastset, crtc, __stringify(name), \
5155                                                 &current_config->infoframes.name, \
5156                                                 &pipe_config->infoframes.name); \
5157                 ret = false; \
5158         } \
5159 } while (0)
5160
5161 #define PIPE_CONF_CHECK_DP_AS_SDP(name) do { \
5162         if (!intel_compare_dp_as_sdp(&current_config->infoframes.name, \
5163                                       &pipe_config->infoframes.name)) { \
5164                 pipe_config_dp_as_sdp_mismatch(dev_priv, fastset, __stringify(name), \
5165                                                 &current_config->infoframes.name, \
5166                                                 &pipe_config->infoframes.name); \
5167                 ret = false; \
5168         } \
5169 } while (0)
5170
5171 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \
5172         BUILD_BUG_ON(sizeof(current_config->name) != (len)); \
5173         BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \
5174         if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \
5175                 pipe_config_buffer_mismatch(&p, fastset, crtc, __stringify(name), \
5176                                             current_config->name, \
5177                                             pipe_config->name, \
5178                                             (len)); \
5179                 ret = false; \
5180         } \
5181 } while (0)
5182
5183 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \
5184         if (current_config->gamma_mode == pipe_config->gamma_mode && \
5185             !intel_color_lut_equal(current_config, \
5186                                    current_config->lut, pipe_config->lut, \
5187                                    is_pre_csc_lut)) {   \
5188                 pipe_config_mismatch(&p, fastset, crtc, __stringify(lut), \
5189                                      "hw_state doesn't match sw_state"); \
5190                 ret = false; \
5191         } \
5192 } while (0)
5193
5194 #define PIPE_CONF_CHECK_CSC(name) do { \
5195         PIPE_CONF_CHECK_X(name.preoff[0]); \
5196         PIPE_CONF_CHECK_X(name.preoff[1]); \
5197         PIPE_CONF_CHECK_X(name.preoff[2]); \
5198         PIPE_CONF_CHECK_X(name.coeff[0]); \
5199         PIPE_CONF_CHECK_X(name.coeff[1]); \
5200         PIPE_CONF_CHECK_X(name.coeff[2]); \
5201         PIPE_CONF_CHECK_X(name.coeff[3]); \
5202         PIPE_CONF_CHECK_X(name.coeff[4]); \
5203         PIPE_CONF_CHECK_X(name.coeff[5]); \
5204         PIPE_CONF_CHECK_X(name.coeff[6]); \
5205         PIPE_CONF_CHECK_X(name.coeff[7]); \
5206         PIPE_CONF_CHECK_X(name.coeff[8]); \
5207         PIPE_CONF_CHECK_X(name.postoff[0]); \
5208         PIPE_CONF_CHECK_X(name.postoff[1]); \
5209         PIPE_CONF_CHECK_X(name.postoff[2]); \
5210 } while (0)
5211
5212 #define PIPE_CONF_QUIRK(quirk) \
5213         ((current_config->quirks | pipe_config->quirks) & (quirk))
5214
5215         PIPE_CONF_CHECK_BOOL(hw.enable);
5216         PIPE_CONF_CHECK_BOOL(hw.active);
5217
5218         PIPE_CONF_CHECK_I(cpu_transcoder);
5219         PIPE_CONF_CHECK_I(mst_master_transcoder);
5220
5221         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
5222         PIPE_CONF_CHECK_I(fdi_lanes);
5223         PIPE_CONF_CHECK_M_N(fdi_m_n);
5224
5225         PIPE_CONF_CHECK_I(lane_count);
5226         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
5227
5228         if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
5229                 if (!fastset || !pipe_config->update_m_n)
5230                         PIPE_CONF_CHECK_M_N(dp_m_n);
5231         } else {
5232                 PIPE_CONF_CHECK_M_N(dp_m_n);
5233                 PIPE_CONF_CHECK_M_N(dp_m2_n2);
5234         }
5235
5236         PIPE_CONF_CHECK_X(output_types);
5237
5238         PIPE_CONF_CHECK_I(framestart_delay);
5239         PIPE_CONF_CHECK_I(msa_timing_delay);
5240
5241         PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
5242         PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
5243
5244         PIPE_CONF_CHECK_I(pixel_multiplier);
5245
5246         PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5247                               DRM_MODE_FLAG_INTERLACE);
5248
5249         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
5250                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5251                                       DRM_MODE_FLAG_PHSYNC);
5252                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5253                                       DRM_MODE_FLAG_NHSYNC);
5254                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5255                                       DRM_MODE_FLAG_PVSYNC);
5256                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5257                                       DRM_MODE_FLAG_NVSYNC);
5258         }
5259
5260         PIPE_CONF_CHECK_I(output_format);
5261         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
5262         if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
5263             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5264                 PIPE_CONF_CHECK_BOOL(limited_color_range);
5265
5266         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
5267         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
5268         PIPE_CONF_CHECK_BOOL(has_infoframe);
5269         PIPE_CONF_CHECK_BOOL(enhanced_framing);
5270         PIPE_CONF_CHECK_BOOL(fec_enable);
5271
5272         if (!fastset) {
5273                 PIPE_CONF_CHECK_BOOL(has_audio);
5274                 PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES);
5275         }
5276
5277         PIPE_CONF_CHECK_X(gmch_pfit.control);
5278         /* pfit ratios are autocomputed by the hw on gen4+ */
5279         if (DISPLAY_VER(dev_priv) < 4)
5280                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
5281         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
5282
5283         /*
5284          * Changing the EDP transcoder input mux
5285          * (A_ONOFF vs. A_ON) requires a full modeset.
5286          */
5287         PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
5288
5289         if (!fastset) {
5290                 PIPE_CONF_CHECK_RECT(pipe_src);
5291
5292                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
5293                 PIPE_CONF_CHECK_RECT(pch_pfit.dst);
5294
5295                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
5296                 PIPE_CONF_CHECK_I(pixel_rate);
5297
5298                 PIPE_CONF_CHECK_X(gamma_mode);
5299                 if (IS_CHERRYVIEW(dev_priv))
5300                         PIPE_CONF_CHECK_X(cgm_mode);
5301                 else
5302                         PIPE_CONF_CHECK_X(csc_mode);
5303                 PIPE_CONF_CHECK_BOOL(gamma_enable);
5304                 PIPE_CONF_CHECK_BOOL(csc_enable);
5305                 PIPE_CONF_CHECK_BOOL(wgc_enable);
5306
5307                 PIPE_CONF_CHECK_I(linetime);
5308                 PIPE_CONF_CHECK_I(ips_linetime);
5309
5310                 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true);
5311                 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false);
5312
5313                 PIPE_CONF_CHECK_CSC(csc);
5314                 PIPE_CONF_CHECK_CSC(output_csc);
5315         }
5316
5317         /*
5318          * Panel replay has to be enabled before link training. PSR doesn't have
5319          * this requirement -> check these only if using panel replay
5320          */
5321         if (current_config->has_panel_replay || pipe_config->has_panel_replay) {
5322                 PIPE_CONF_CHECK_BOOL(has_psr);
5323                 PIPE_CONF_CHECK_BOOL(has_psr2);
5324                 PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
5325                 PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
5326                 PIPE_CONF_CHECK_BOOL(has_panel_replay);
5327         }
5328
5329         PIPE_CONF_CHECK_BOOL(double_wide);
5330
5331         if (dev_priv->display.dpll.mgr)
5332                 PIPE_CONF_CHECK_P(shared_dpll);
5333
5334         /* FIXME convert everything over the dpll_mgr */
5335         if (dev_priv->display.dpll.mgr || HAS_GMCH(dev_priv))
5336                 PIPE_CONF_CHECK_PLL(dpll_hw_state);
5337
5338         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
5339         PIPE_CONF_CHECK_X(dsi_pll.div);
5340
5341         if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
5342                 PIPE_CONF_CHECK_I(pipe_bpp);
5343
5344         if (!fastset || !pipe_config->update_m_n) {
5345                 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
5346                 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
5347         }
5348         PIPE_CONF_CHECK_I(port_clock);
5349
5350         PIPE_CONF_CHECK_I(min_voltage_level);
5351
5352         if (current_config->has_psr || pipe_config->has_psr)
5353                 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
5354                                             ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
5355         else
5356                 PIPE_CONF_CHECK_X(infoframes.enable);
5357
5358         PIPE_CONF_CHECK_X(infoframes.gcp);
5359         PIPE_CONF_CHECK_INFOFRAME(avi);
5360         PIPE_CONF_CHECK_INFOFRAME(spd);
5361         PIPE_CONF_CHECK_INFOFRAME(hdmi);
5362         PIPE_CONF_CHECK_INFOFRAME(drm);
5363         PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
5364         PIPE_CONF_CHECK_DP_AS_SDP(as_sdp);
5365
5366         PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
5367         PIPE_CONF_CHECK_I(master_transcoder);
5368         PIPE_CONF_CHECK_X(bigjoiner_pipes);
5369
5370         PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable);
5371         PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb);
5372         PIPE_CONF_CHECK_BOOL(dsc.config.simple_422);
5373         PIPE_CONF_CHECK_BOOL(dsc.config.native_422);
5374         PIPE_CONF_CHECK_BOOL(dsc.config.native_420);
5375         PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable);
5376         PIPE_CONF_CHECK_I(dsc.config.line_buf_depth);
5377         PIPE_CONF_CHECK_I(dsc.config.bits_per_component);
5378         PIPE_CONF_CHECK_I(dsc.config.pic_width);
5379         PIPE_CONF_CHECK_I(dsc.config.pic_height);
5380         PIPE_CONF_CHECK_I(dsc.config.slice_width);
5381         PIPE_CONF_CHECK_I(dsc.config.slice_height);
5382         PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay);
5383         PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay);
5384         PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval);
5385         PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval);
5386         PIPE_CONF_CHECK_I(dsc.config.initial_scale_value);
5387         PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset);
5388         PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp);
5389         PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp);
5390         PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset);
5391         PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset);
5392         PIPE_CONF_CHECK_I(dsc.config.initial_offset);
5393         PIPE_CONF_CHECK_I(dsc.config.final_offset);
5394         PIPE_CONF_CHECK_I(dsc.config.rc_model_size);
5395         PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0);
5396         PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1);
5397         PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size);
5398         PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset);
5399         PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
5400
5401         PIPE_CONF_CHECK_BOOL(dsc.compression_enable);
5402         PIPE_CONF_CHECK_BOOL(dsc.dsc_split);
5403         PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
5404
5405         PIPE_CONF_CHECK_BOOL(splitter.enable);
5406         PIPE_CONF_CHECK_I(splitter.link_count);
5407         PIPE_CONF_CHECK_I(splitter.pixel_overlap);
5408
5409         if (!fastset) {
5410                 PIPE_CONF_CHECK_BOOL(vrr.enable);
5411                 PIPE_CONF_CHECK_I(vrr.vmin);
5412                 PIPE_CONF_CHECK_I(vrr.vmax);
5413                 PIPE_CONF_CHECK_I(vrr.flipline);
5414                 PIPE_CONF_CHECK_I(vrr.pipeline_full);
5415                 PIPE_CONF_CHECK_I(vrr.guardband);
5416                 PIPE_CONF_CHECK_I(vrr.vsync_start);
5417                 PIPE_CONF_CHECK_I(vrr.vsync_end);
5418         }
5419
5420 #undef PIPE_CONF_CHECK_X
5421 #undef PIPE_CONF_CHECK_I
5422 #undef PIPE_CONF_CHECK_BOOL
5423 #undef PIPE_CONF_CHECK_P
5424 #undef PIPE_CONF_CHECK_FLAGS
5425 #undef PIPE_CONF_CHECK_COLOR_LUT
5426 #undef PIPE_CONF_CHECK_TIMINGS
5427 #undef PIPE_CONF_CHECK_RECT
5428 #undef PIPE_CONF_QUIRK
5429
5430         return ret;
5431 }
5432
5433 static void
5434 intel_verify_planes(struct intel_atomic_state *state)
5435 {
5436         struct intel_plane *plane;
5437         const struct intel_plane_state *plane_state;
5438         int i;
5439
5440         for_each_new_intel_plane_in_state(state, plane,
5441                                           plane_state, i)
5442                 assert_plane(plane, plane_state->planar_slave ||
5443                              plane_state->uapi.visible);
5444 }
5445
5446 static int intel_modeset_pipe(struct intel_atomic_state *state,
5447                               struct intel_crtc_state *crtc_state,
5448                               const char *reason)
5449 {
5450         struct drm_i915_private *i915 = to_i915(state->base.dev);
5451         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5452         int ret;
5453
5454         drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Full modeset due to %s\n",
5455                     crtc->base.base.id, crtc->base.name, reason);
5456
5457         ret = drm_atomic_add_affected_connectors(&state->base,
5458                                                  &crtc->base);
5459         if (ret)
5460                 return ret;
5461
5462         ret = intel_dp_tunnel_atomic_add_state_for_crtc(state, crtc);
5463         if (ret)
5464                 return ret;
5465
5466         ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc);
5467         if (ret)
5468                 return ret;
5469
5470         ret = intel_atomic_add_affected_planes(state, crtc);
5471         if (ret)
5472                 return ret;
5473
5474         crtc_state->uapi.mode_changed = true;
5475
5476         return 0;
5477 }
5478
5479 /**
5480  * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes
5481  * @state: intel atomic state
5482  * @reason: the reason for the full modeset
5483  * @mask: mask of pipes to modeset
5484  *
5485  * Add pipes in @mask to @state and force a full modeset on the enabled ones
5486  * due to the description in @reason.
5487  * This function can be called only before new plane states are computed.
5488  *
5489  * Returns 0 in case of success, negative error code otherwise.
5490  */
5491 int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
5492                                       const char *reason, u8 mask)
5493 {
5494         struct drm_i915_private *i915 = to_i915(state->base.dev);
5495         struct intel_crtc *crtc;
5496
5497         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, mask) {
5498                 struct intel_crtc_state *crtc_state;
5499                 int ret;
5500
5501                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5502                 if (IS_ERR(crtc_state))
5503                         return PTR_ERR(crtc_state);
5504
5505                 if (!crtc_state->hw.enable ||
5506                     intel_crtc_needs_modeset(crtc_state))
5507                         continue;
5508
5509                 ret = intel_modeset_pipe(state, crtc_state, reason);
5510                 if (ret)
5511                         return ret;
5512         }
5513
5514         return 0;
5515 }
5516
5517 static void
5518 intel_crtc_flag_modeset(struct intel_crtc_state *crtc_state)
5519 {
5520         crtc_state->uapi.mode_changed = true;
5521
5522         crtc_state->update_pipe = false;
5523         crtc_state->update_m_n = false;
5524         crtc_state->update_lrr = false;
5525 }
5526
5527 /**
5528  * intel_modeset_all_pipes_late - force a full modeset on all pipes
5529  * @state: intel atomic state
5530  * @reason: the reason for the full modeset
5531  *
5532  * Add all pipes to @state and force a full modeset on the active ones due to
5533  * the description in @reason.
5534  * This function can be called only after new plane states are computed already.
5535  *
5536  * Returns 0 in case of success, negative error code otherwise.
5537  */
5538 int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
5539                                  const char *reason)
5540 {
5541         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5542         struct intel_crtc *crtc;
5543
5544         for_each_intel_crtc(&dev_priv->drm, crtc) {
5545                 struct intel_crtc_state *crtc_state;
5546                 int ret;
5547
5548                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5549                 if (IS_ERR(crtc_state))
5550                         return PTR_ERR(crtc_state);
5551
5552                 if (!crtc_state->hw.active ||
5553                     intel_crtc_needs_modeset(crtc_state))
5554                         continue;
5555
5556                 ret = intel_modeset_pipe(state, crtc_state, reason);
5557                 if (ret)
5558                         return ret;
5559
5560                 intel_crtc_flag_modeset(crtc_state);
5561
5562                 crtc_state->update_planes |= crtc_state->active_planes;
5563                 crtc_state->async_flip_planes = 0;
5564                 crtc_state->do_async_flip = false;
5565         }
5566
5567         return 0;
5568 }
5569
5570 /*
5571  * This implements the workaround described in the "notes" section of the mode
5572  * set sequence documentation. When going from no pipes or single pipe to
5573  * multiple pipes, and planes are enabled after the pipe, we need to wait at
5574  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
5575  */
5576 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
5577 {
5578         struct intel_crtc_state *crtc_state;
5579         struct intel_crtc *crtc;
5580         struct intel_crtc_state *first_crtc_state = NULL;
5581         struct intel_crtc_state *other_crtc_state = NULL;
5582         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
5583         int i;
5584
5585         /* look at all crtc's that are going to be enabled in during modeset */
5586         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5587                 if (!crtc_state->hw.active ||
5588                     !intel_crtc_needs_modeset(crtc_state))
5589                         continue;
5590
5591                 if (first_crtc_state) {
5592                         other_crtc_state = crtc_state;
5593                         break;
5594                 } else {
5595                         first_crtc_state = crtc_state;
5596                         first_pipe = crtc->pipe;
5597                 }
5598         }
5599
5600         /* No workaround needed? */
5601         if (!first_crtc_state)
5602                 return 0;
5603
5604         /* w/a possibly needed, check how many crtc's are already enabled. */
5605         for_each_intel_crtc(state->base.dev, crtc) {
5606                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5607                 if (IS_ERR(crtc_state))
5608                         return PTR_ERR(crtc_state);
5609
5610                 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
5611
5612                 if (!crtc_state->hw.active ||
5613                     intel_crtc_needs_modeset(crtc_state))
5614                         continue;
5615
5616                 /* 2 or more enabled crtcs means no need for w/a */
5617                 if (enabled_pipe != INVALID_PIPE)
5618                         return 0;
5619
5620                 enabled_pipe = crtc->pipe;
5621         }
5622
5623         if (enabled_pipe != INVALID_PIPE)
5624                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
5625         else if (other_crtc_state)
5626                 other_crtc_state->hsw_workaround_pipe = first_pipe;
5627
5628         return 0;
5629 }
5630
5631 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
5632                            u8 active_pipes)
5633 {
5634         const struct intel_crtc_state *crtc_state;
5635         struct intel_crtc *crtc;
5636         int i;
5637
5638         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5639                 if (crtc_state->hw.active)
5640                         active_pipes |= BIT(crtc->pipe);
5641                 else
5642                         active_pipes &= ~BIT(crtc->pipe);
5643         }
5644
5645         return active_pipes;
5646 }
5647
5648 static int intel_modeset_checks(struct intel_atomic_state *state)
5649 {
5650         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5651
5652         state->modeset = true;
5653
5654         if (IS_HASWELL(dev_priv))
5655                 return hsw_mode_set_planes_workaround(state);
5656
5657         return 0;
5658 }
5659
5660 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
5661                                      struct intel_crtc_state *new_crtc_state)
5662 {
5663         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
5664         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5665
5666         /* only allow LRR when the timings stay within the VRR range */
5667         if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)
5668                 new_crtc_state->update_lrr = false;
5669
5670         if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
5671                 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n",
5672                             crtc->base.base.id, crtc->base.name);
5673         else
5674                 new_crtc_state->uapi.mode_changed = false;
5675
5676         if (intel_compare_link_m_n(&old_crtc_state->dp_m_n,
5677                                    &new_crtc_state->dp_m_n))
5678                 new_crtc_state->update_m_n = false;
5679
5680         if ((old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
5681              old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))
5682                 new_crtc_state->update_lrr = false;
5683
5684         if (intel_crtc_needs_modeset(new_crtc_state))
5685                 intel_crtc_flag_modeset(new_crtc_state);
5686         else
5687                 new_crtc_state->update_pipe = true;
5688 }
5689
5690 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
5691                                           struct intel_crtc *crtc,
5692                                           u8 plane_ids_mask)
5693 {
5694         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5695         struct intel_plane *plane;
5696
5697         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5698                 struct intel_plane_state *plane_state;
5699
5700                 if ((plane_ids_mask & BIT(plane->id)) == 0)
5701                         continue;
5702
5703                 plane_state = intel_atomic_get_plane_state(state, plane);
5704                 if (IS_ERR(plane_state))
5705                         return PTR_ERR(plane_state);
5706         }
5707
5708         return 0;
5709 }
5710
5711 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
5712                                      struct intel_crtc *crtc)
5713 {
5714         const struct intel_crtc_state *old_crtc_state =
5715                 intel_atomic_get_old_crtc_state(state, crtc);
5716         const struct intel_crtc_state *new_crtc_state =
5717                 intel_atomic_get_new_crtc_state(state, crtc);
5718
5719         return intel_crtc_add_planes_to_state(state, crtc,
5720                                               old_crtc_state->enabled_planes |
5721                                               new_crtc_state->enabled_planes);
5722 }
5723
5724 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
5725 {
5726         /* See {hsw,vlv,ivb}_plane_ratio() */
5727         return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
5728                 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
5729                 IS_IVYBRIDGE(dev_priv);
5730 }
5731
5732 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
5733                                            struct intel_crtc *crtc,
5734                                            struct intel_crtc *other)
5735 {
5736         const struct intel_plane_state __maybe_unused *plane_state;
5737         struct intel_plane *plane;
5738         u8 plane_ids = 0;
5739         int i;
5740
5741         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
5742                 if (plane->pipe == crtc->pipe)
5743                         plane_ids |= BIT(plane->id);
5744         }
5745
5746         return intel_crtc_add_planes_to_state(state, other, plane_ids);
5747 }
5748
5749 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state)
5750 {
5751         struct drm_i915_private *i915 = to_i915(state->base.dev);
5752         const struct intel_crtc_state *crtc_state;
5753         struct intel_crtc *crtc;
5754         int i;
5755
5756         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5757                 struct intel_crtc *other;
5758
5759                 for_each_intel_crtc_in_pipe_mask(&i915->drm, other,
5760                                                  crtc_state->bigjoiner_pipes) {
5761                         int ret;
5762
5763                         if (crtc == other)
5764                                 continue;
5765
5766                         ret = intel_crtc_add_bigjoiner_planes(state, crtc, other);
5767                         if (ret)
5768                                 return ret;
5769                 }
5770         }
5771
5772         return 0;
5773 }
5774
5775 static int intel_atomic_check_planes(struct intel_atomic_state *state)
5776 {
5777         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5778         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
5779         struct intel_plane_state __maybe_unused *plane_state;
5780         struct intel_plane *plane;
5781         struct intel_crtc *crtc;
5782         int i, ret;
5783
5784         ret = icl_add_linked_planes(state);
5785         if (ret)
5786                 return ret;
5787
5788         ret = intel_bigjoiner_add_affected_planes(state);
5789         if (ret)
5790                 return ret;
5791
5792         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
5793                 ret = intel_plane_atomic_check(state, plane);
5794                 if (ret) {
5795                         drm_dbg_atomic(&dev_priv->drm,
5796                                        "[PLANE:%d:%s] atomic driver check failed\n",
5797                                        plane->base.base.id, plane->base.name);
5798                         return ret;
5799                 }
5800         }
5801
5802         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
5803                                             new_crtc_state, i) {
5804                 u8 old_active_planes, new_active_planes;
5805
5806                 ret = icl_check_nv12_planes(new_crtc_state);
5807                 if (ret)
5808                         return ret;
5809
5810                 /*
5811                  * On some platforms the number of active planes affects
5812                  * the planes' minimum cdclk calculation. Add such planes
5813                  * to the state before we compute the minimum cdclk.
5814                  */
5815                 if (!active_planes_affects_min_cdclk(dev_priv))
5816                         continue;
5817
5818                 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
5819                 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
5820
5821                 if (hweight8(old_active_planes) == hweight8(new_active_planes))
5822                         continue;
5823
5824                 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
5825                 if (ret)
5826                         return ret;
5827         }
5828
5829         return 0;
5830 }
5831
5832 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
5833 {
5834         struct intel_crtc_state __maybe_unused *crtc_state;
5835         struct intel_crtc *crtc;
5836         int i;
5837
5838         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5839                 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5840                 int ret;
5841
5842                 ret = intel_crtc_atomic_check(state, crtc);
5843                 if (ret) {
5844                         drm_dbg_atomic(&i915->drm,
5845                                        "[CRTC:%d:%s] atomic driver check failed\n",
5846                                        crtc->base.base.id, crtc->base.name);
5847                         return ret;
5848                 }
5849         }
5850
5851         return 0;
5852 }
5853
5854 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
5855                                                u8 transcoders)
5856 {
5857         const struct intel_crtc_state *new_crtc_state;
5858         struct intel_crtc *crtc;
5859         int i;
5860
5861         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
5862                 if (new_crtc_state->hw.enable &&
5863                     transcoders & BIT(new_crtc_state->cpu_transcoder) &&
5864                     intel_crtc_needs_modeset(new_crtc_state))
5865                         return true;
5866         }
5867
5868         return false;
5869 }
5870
5871 static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
5872                                      u8 pipes)
5873 {
5874         const struct intel_crtc_state *new_crtc_state;
5875         struct intel_crtc *crtc;
5876         int i;
5877
5878         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
5879                 if (new_crtc_state->hw.enable &&
5880                     pipes & BIT(crtc->pipe) &&
5881                     intel_crtc_needs_modeset(new_crtc_state))
5882                         return true;
5883         }
5884
5885         return false;
5886 }
5887
5888 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
5889                                         struct intel_crtc *master_crtc)
5890 {
5891         struct drm_i915_private *i915 = to_i915(state->base.dev);
5892         struct intel_crtc_state *master_crtc_state =
5893                 intel_atomic_get_new_crtc_state(state, master_crtc);
5894         struct intel_crtc *slave_crtc;
5895
5896         if (!master_crtc_state->bigjoiner_pipes)
5897                 return 0;
5898
5899         /* sanity check */
5900         if (drm_WARN_ON(&i915->drm,
5901                         master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state)))
5902                 return -EINVAL;
5903
5904         if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) {
5905                 drm_dbg_kms(&i915->drm,
5906                             "[CRTC:%d:%s] Cannot act as big joiner master "
5907                             "(need 0x%x as pipes, only 0x%x possible)\n",
5908                             master_crtc->base.base.id, master_crtc->base.name,
5909                             master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915));
5910                 return -EINVAL;
5911         }
5912
5913         for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
5914                                          intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
5915                 struct intel_crtc_state *slave_crtc_state;
5916                 int ret;
5917
5918                 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc);
5919                 if (IS_ERR(slave_crtc_state))
5920                         return PTR_ERR(slave_crtc_state);
5921
5922                 /* master being enabled, slave was already configured? */
5923                 if (slave_crtc_state->uapi.enable) {
5924                         drm_dbg_kms(&i915->drm,
5925                                     "[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
5926                                     "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
5927                                     slave_crtc->base.base.id, slave_crtc->base.name,
5928                                     master_crtc->base.base.id, master_crtc->base.name);
5929                         return -EINVAL;
5930                 }
5931
5932                 /*
5933                  * The state copy logic assumes the master crtc gets processed
5934                  * before the slave crtc during the main compute_config loop.
5935                  * This works because the crtcs are created in pipe order,
5936                  * and the hardware requires master pipe < slave pipe as well.
5937                  * Should that change we need to rethink the logic.
5938                  */
5939                 if (WARN_ON(drm_crtc_index(&master_crtc->base) >
5940                             drm_crtc_index(&slave_crtc->base)))
5941                         return -EINVAL;
5942
5943                 drm_dbg_kms(&i915->drm,
5944                             "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n",
5945                             slave_crtc->base.base.id, slave_crtc->base.name,
5946                             master_crtc->base.base.id, master_crtc->base.name);
5947
5948                 slave_crtc_state->bigjoiner_pipes =
5949                         master_crtc_state->bigjoiner_pipes;
5950
5951                 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc);
5952                 if (ret)
5953                         return ret;
5954         }
5955
5956         return 0;
5957 }
5958
5959 static void kill_bigjoiner_slave(struct intel_atomic_state *state,
5960                                  struct intel_crtc *master_crtc)
5961 {
5962         struct drm_i915_private *i915 = to_i915(state->base.dev);
5963         struct intel_crtc_state *master_crtc_state =
5964                 intel_atomic_get_new_crtc_state(state, master_crtc);
5965         struct intel_crtc *slave_crtc;
5966
5967         for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
5968                                          intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
5969                 struct intel_crtc_state *slave_crtc_state =
5970                         intel_atomic_get_new_crtc_state(state, slave_crtc);
5971
5972                 slave_crtc_state->bigjoiner_pipes = 0;
5973
5974                 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc);
5975         }
5976
5977         master_crtc_state->bigjoiner_pipes = 0;
5978 }
5979
5980 /**
5981  * DOC: asynchronous flip implementation
5982  *
5983  * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
5984  * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
5985  * Correspondingly, support is currently added for primary plane only.
5986  *
5987  * Async flip can only change the plane surface address, so anything else
5988  * changing is rejected from the intel_async_flip_check_hw() function.
5989  * Once this check is cleared, flip done interrupt is enabled using
5990  * the intel_crtc_enable_flip_done() function.
5991  *
5992  * As soon as the surface address register is written, flip done interrupt is
5993  * generated and the requested events are sent to the usersapce in the interrupt
5994  * handler itself. The timestamp and sequence sent during the flip done event
5995  * correspond to the last vblank and have no relation to the actual time when
5996  * the flip done event was sent.
5997  */
5998 static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
5999                                        struct intel_crtc *crtc)
6000 {
6001         struct drm_i915_private *i915 = to_i915(state->base.dev);
6002         const struct intel_crtc_state *new_crtc_state =
6003                 intel_atomic_get_new_crtc_state(state, crtc);
6004         const struct intel_plane_state *old_plane_state;
6005         struct intel_plane_state *new_plane_state;
6006         struct intel_plane *plane;
6007         int i;
6008
6009         if (!new_crtc_state->uapi.async_flip)
6010                 return 0;
6011
6012         if (!new_crtc_state->uapi.active) {
6013                 drm_dbg_kms(&i915->drm,
6014                             "[CRTC:%d:%s] not active\n",
6015                             crtc->base.base.id, crtc->base.name);
6016                 return -EINVAL;
6017         }
6018
6019         if (intel_crtc_needs_modeset(new_crtc_state)) {
6020                 drm_dbg_kms(&i915->drm,
6021                             "[CRTC:%d:%s] modeset required\n",
6022                             crtc->base.base.id, crtc->base.name);
6023                 return -EINVAL;
6024         }
6025
6026         /*
6027          * FIXME: Bigjoiner+async flip is busted currently.
6028          * Remove this check once the issues are fixed.
6029          */
6030         if (new_crtc_state->bigjoiner_pipes) {
6031                 drm_dbg_kms(&i915->drm,
6032                             "[CRTC:%d:%s] async flip disallowed with bigjoiner\n",
6033                             crtc->base.base.id, crtc->base.name);
6034                 return -EINVAL;
6035         }
6036
6037         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6038                                              new_plane_state, i) {
6039                 if (plane->pipe != crtc->pipe)
6040                         continue;
6041
6042                 /*
6043                  * TODO: Async flip is only supported through the page flip IOCTL
6044                  * as of now. So support currently added for primary plane only.
6045                  * Support for other planes on platforms on which supports
6046                  * this(vlv/chv and icl+) should be added when async flip is
6047                  * enabled in the atomic IOCTL path.
6048                  */
6049                 if (!plane->async_flip) {
6050                         drm_dbg_kms(&i915->drm,
6051                                     "[PLANE:%d:%s] async flip not supported\n",
6052                                     plane->base.base.id, plane->base.name);
6053                         return -EINVAL;
6054                 }
6055
6056                 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {
6057                         drm_dbg_kms(&i915->drm,
6058                                     "[PLANE:%d:%s] no old or new framebuffer\n",
6059                                     plane->base.base.id, plane->base.name);
6060                         return -EINVAL;
6061                 }
6062         }
6063
6064         return 0;
6065 }
6066
6067 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc)
6068 {
6069         struct drm_i915_private *i915 = to_i915(state->base.dev);
6070         const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6071         const struct intel_plane_state *new_plane_state, *old_plane_state;
6072         struct intel_plane *plane;
6073         int i;
6074
6075         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6076         new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6077
6078         if (!new_crtc_state->uapi.async_flip)
6079                 return 0;
6080
6081         if (!new_crtc_state->hw.active) {
6082                 drm_dbg_kms(&i915->drm,
6083                             "[CRTC:%d:%s] not active\n",
6084                             crtc->base.base.id, crtc->base.name);
6085                 return -EINVAL;
6086         }
6087
6088         if (intel_crtc_needs_modeset(new_crtc_state)) {
6089                 drm_dbg_kms(&i915->drm,
6090                             "[CRTC:%d:%s] modeset required\n",
6091                             crtc->base.base.id, crtc->base.name);
6092                 return -EINVAL;
6093         }
6094
6095         if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
6096                 drm_dbg_kms(&i915->drm,
6097                             "[CRTC:%d:%s] Active planes cannot be in async flip\n",
6098                             crtc->base.base.id, crtc->base.name);
6099                 return -EINVAL;
6100         }
6101
6102         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6103                                              new_plane_state, i) {
6104                 if (plane->pipe != crtc->pipe)
6105                         continue;
6106
6107                 /*
6108                  * Only async flip capable planes should be in the state
6109                  * if we're really about to ask the hardware to perform
6110                  * an async flip. We should never get this far otherwise.
6111                  */
6112                 if (drm_WARN_ON(&i915->drm,
6113                                 new_crtc_state->do_async_flip && !plane->async_flip))
6114                         return -EINVAL;
6115
6116                 /*
6117                  * Only check async flip capable planes other planes
6118                  * may be involved in the initial commit due to
6119                  * the wm0/ddb optimization.
6120                  *
6121                  * TODO maybe should track which planes actually
6122                  * were requested to do the async flip...
6123                  */
6124                 if (!plane->async_flip)
6125                         continue;
6126
6127                 /*
6128                  * FIXME: This check is kept generic for all platforms.
6129                  * Need to verify this for all gen9 platforms to enable
6130                  * this selectively if required.
6131                  */
6132                 switch (new_plane_state->hw.fb->modifier) {
6133                 case DRM_FORMAT_MOD_LINEAR:
6134                         /*
6135                          * FIXME: Async on Linear buffer is supported on ICL as
6136                          * but with additional alignment and fbc restrictions
6137                          * need to be taken care of. These aren't applicable for
6138                          * gen12+.
6139                          */
6140                         if (DISPLAY_VER(i915) < 12) {
6141                                 drm_dbg_kms(&i915->drm,
6142                                             "[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d\n",
6143                                             plane->base.base.id, plane->base.name,
6144                                             new_plane_state->hw.fb->modifier, DISPLAY_VER(i915));
6145                                 return -EINVAL;
6146                         }
6147                         break;
6148
6149                 case I915_FORMAT_MOD_X_TILED:
6150                 case I915_FORMAT_MOD_Y_TILED:
6151                 case I915_FORMAT_MOD_Yf_TILED:
6152                 case I915_FORMAT_MOD_4_TILED:
6153                         break;
6154                 default:
6155                         drm_dbg_kms(&i915->drm,
6156                                     "[PLANE:%d:%s] Modifier 0x%llx does not support async flip\n",
6157                                     plane->base.base.id, plane->base.name,
6158                                     new_plane_state->hw.fb->modifier);
6159                         return -EINVAL;
6160                 }
6161
6162                 if (new_plane_state->hw.fb->format->num_planes > 1) {
6163                         drm_dbg_kms(&i915->drm,
6164                                     "[PLANE:%d:%s] Planar formats do not support async flips\n",
6165                                     plane->base.base.id, plane->base.name);
6166                         return -EINVAL;
6167                 }
6168
6169                 if (old_plane_state->view.color_plane[0].mapping_stride !=
6170                     new_plane_state->view.color_plane[0].mapping_stride) {
6171                         drm_dbg_kms(&i915->drm,
6172                                     "[PLANE:%d:%s] Stride cannot be changed in async flip\n",
6173                                     plane->base.base.id, plane->base.name);
6174                         return -EINVAL;
6175                 }
6176
6177                 if (old_plane_state->hw.fb->modifier !=
6178                     new_plane_state->hw.fb->modifier) {
6179                         drm_dbg_kms(&i915->drm,
6180                                     "[PLANE:%d:%s] Modifier cannot be changed in async flip\n",
6181                                     plane->base.base.id, plane->base.name);
6182                         return -EINVAL;
6183                 }
6184
6185                 if (old_plane_state->hw.fb->format !=
6186                     new_plane_state->hw.fb->format) {
6187                         drm_dbg_kms(&i915->drm,
6188                                     "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n",
6189                                     plane->base.base.id, plane->base.name);
6190                         return -EINVAL;
6191                 }
6192
6193                 if (old_plane_state->hw.rotation !=
6194                     new_plane_state->hw.rotation) {
6195                         drm_dbg_kms(&i915->drm,
6196                                     "[PLANE:%d:%s] Rotation cannot be changed in async flip\n",
6197                                     plane->base.base.id, plane->base.name);
6198                         return -EINVAL;
6199                 }
6200
6201                 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
6202                     !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
6203                         drm_dbg_kms(&i915->drm,
6204                                     "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",
6205                                     plane->base.base.id, plane->base.name);
6206                         return -EINVAL;
6207                 }
6208
6209                 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
6210                         drm_dbg_kms(&i915->drm,
6211                                     "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n",
6212                                     plane->base.base.id, plane->base.name);
6213                         return -EINVAL;
6214                 }
6215
6216                 if (old_plane_state->hw.pixel_blend_mode !=
6217                     new_plane_state->hw.pixel_blend_mode) {
6218                         drm_dbg_kms(&i915->drm,
6219                                     "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n",
6220                                     plane->base.base.id, plane->base.name);
6221                         return -EINVAL;
6222                 }
6223
6224                 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
6225                         drm_dbg_kms(&i915->drm,
6226                                     "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n",
6227                                     plane->base.base.id, plane->base.name);
6228                         return -EINVAL;
6229                 }
6230
6231                 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
6232                         drm_dbg_kms(&i915->drm,
6233                                     "[PLANE:%d:%s] Color range cannot be changed in async flip\n",
6234                                     plane->base.base.id, plane->base.name);
6235                         return -EINVAL;
6236                 }
6237
6238                 /* plane decryption is allow to change only in synchronous flips */
6239                 if (old_plane_state->decrypt != new_plane_state->decrypt) {
6240                         drm_dbg_kms(&i915->drm,
6241                                     "[PLANE:%d:%s] Decryption cannot be changed in async flip\n",
6242                                     plane->base.base.id, plane->base.name);
6243                         return -EINVAL;
6244                 }
6245         }
6246
6247         return 0;
6248 }
6249
6250 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
6251 {
6252         struct drm_i915_private *i915 = to_i915(state->base.dev);
6253         struct intel_crtc_state *crtc_state;
6254         struct intel_crtc *crtc;
6255         u8 affected_pipes = 0;
6256         u8 modeset_pipes = 0;
6257         int i;
6258
6259         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6260                 affected_pipes |= crtc_state->bigjoiner_pipes;
6261                 if (intel_crtc_needs_modeset(crtc_state))
6262                         modeset_pipes |= crtc_state->bigjoiner_pipes;
6263         }
6264
6265         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) {
6266                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6267                 if (IS_ERR(crtc_state))
6268                         return PTR_ERR(crtc_state);
6269         }
6270
6271         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) {
6272                 int ret;
6273
6274                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6275
6276                 crtc_state->uapi.mode_changed = true;
6277
6278                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6279                 if (ret)
6280                         return ret;
6281
6282                 ret = intel_atomic_add_affected_planes(state, crtc);
6283                 if (ret)
6284                         return ret;
6285         }
6286
6287         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6288                 /* Kill old bigjoiner link, we may re-establish afterwards */
6289                 if (intel_crtc_needs_modeset(crtc_state) &&
6290                     intel_crtc_is_bigjoiner_master(crtc_state))
6291                         kill_bigjoiner_slave(state, crtc);
6292         }
6293
6294         return 0;
6295 }
6296
6297 static int intel_atomic_check_config(struct intel_atomic_state *state,
6298                                      struct intel_link_bw_limits *limits,
6299                                      enum pipe *failed_pipe)
6300 {
6301         struct drm_i915_private *i915 = to_i915(state->base.dev);
6302         struct intel_crtc_state *new_crtc_state;
6303         struct intel_crtc *crtc;
6304         int ret;
6305         int i;
6306
6307         *failed_pipe = INVALID_PIPE;
6308
6309         ret = intel_bigjoiner_add_affected_crtcs(state);
6310         if (ret)
6311                 return ret;
6312
6313         ret = intel_fdi_add_affected_crtcs(state);
6314         if (ret)
6315                 return ret;
6316
6317         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6318                 if (!intel_crtc_needs_modeset(new_crtc_state)) {
6319                         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
6320                                 copy_bigjoiner_crtc_state_nomodeset(state, crtc);
6321                         else
6322                                 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
6323                         continue;
6324                 }
6325
6326                 if (drm_WARN_ON(&i915->drm, intel_crtc_is_bigjoiner_slave(new_crtc_state)))
6327                         continue;
6328
6329                 ret = intel_crtc_prepare_cleared_state(state, crtc);
6330                 if (ret)
6331                         goto fail;
6332
6333                 if (!new_crtc_state->hw.enable)
6334                         continue;
6335
6336                 ret = intel_modeset_pipe_config(state, crtc, limits);
6337                 if (ret)
6338                         goto fail;
6339         }
6340
6341         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6342                 if (!intel_crtc_needs_modeset(new_crtc_state))
6343                         continue;
6344
6345                 if (drm_WARN_ON(&i915->drm, intel_crtc_is_bigjoiner_slave(new_crtc_state)))
6346                         continue;
6347
6348                 if (!new_crtc_state->hw.enable)
6349                         continue;
6350
6351                 ret = intel_modeset_pipe_config_late(state, crtc);
6352                 if (ret)
6353                         goto fail;
6354         }
6355
6356 fail:
6357         if (ret)
6358                 *failed_pipe = crtc->pipe;
6359
6360         return ret;
6361 }
6362
6363 static int intel_atomic_check_config_and_link(struct intel_atomic_state *state)
6364 {
6365         struct intel_link_bw_limits new_limits;
6366         struct intel_link_bw_limits old_limits;
6367         int ret;
6368
6369         intel_link_bw_init_limits(state, &new_limits);
6370         old_limits = new_limits;
6371
6372         while (true) {
6373                 enum pipe failed_pipe;
6374
6375                 ret = intel_atomic_check_config(state, &new_limits,
6376                                                 &failed_pipe);
6377                 if (ret) {
6378                         /*
6379                          * The bpp limit for a pipe is below the minimum it supports, set the
6380                          * limit to the minimum and recalculate the config.
6381                          */
6382                         if (ret == -EINVAL &&
6383                             intel_link_bw_set_bpp_limit_for_pipe(state,
6384                                                                  &old_limits,
6385                                                                  &new_limits,
6386                                                                  failed_pipe))
6387                                 continue;
6388
6389                         break;
6390                 }
6391
6392                 old_limits = new_limits;
6393
6394                 ret = intel_link_bw_atomic_check(state, &new_limits);
6395                 if (ret != -EAGAIN)
6396                         break;
6397         }
6398
6399         return ret;
6400 }
6401 /**
6402  * intel_atomic_check - validate state object
6403  * @dev: drm device
6404  * @_state: state to validate
6405  */
6406 int intel_atomic_check(struct drm_device *dev,
6407                        struct drm_atomic_state *_state)
6408 {
6409         struct drm_i915_private *dev_priv = to_i915(dev);
6410         struct intel_atomic_state *state = to_intel_atomic_state(_state);
6411         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6412         struct intel_crtc *crtc;
6413         int ret, i;
6414         bool any_ms = false;
6415
6416         if (!intel_display_driver_check_access(dev_priv))
6417                 return -ENODEV;
6418
6419         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6420                                             new_crtc_state, i) {
6421                 /*
6422                  * crtc's state no longer considered to be inherited
6423                  * after the first userspace/client initiated commit.
6424                  */
6425                 if (!state->internal)
6426                         new_crtc_state->inherited = false;
6427
6428                 if (new_crtc_state->inherited != old_crtc_state->inherited)
6429                         new_crtc_state->uapi.mode_changed = true;
6430
6431                 if (new_crtc_state->uapi.scaling_filter !=
6432                     old_crtc_state->uapi.scaling_filter)
6433                         new_crtc_state->uapi.mode_changed = true;
6434         }
6435
6436         intel_vrr_check_modeset(state);
6437
6438         ret = drm_atomic_helper_check_modeset(dev, &state->base);
6439         if (ret)
6440                 goto fail;
6441
6442         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6443                 ret = intel_async_flip_check_uapi(state, crtc);
6444                 if (ret)
6445                         return ret;
6446         }
6447
6448         ret = intel_atomic_check_config_and_link(state);
6449         if (ret)
6450                 goto fail;
6451
6452         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6453                 if (!intel_crtc_needs_modeset(new_crtc_state))
6454                         continue;
6455
6456                 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
6457                         drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable);
6458                         continue;
6459                 }
6460
6461                 ret = intel_atomic_check_bigjoiner(state, crtc);
6462                 if (ret)
6463                         goto fail;
6464         }
6465
6466         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6467                                             new_crtc_state, i) {
6468                 if (!intel_crtc_needs_modeset(new_crtc_state))
6469                         continue;
6470
6471                 intel_bigjoiner_adjust_pipe_src(new_crtc_state);
6472
6473                 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
6474         }
6475
6476         /**
6477          * Check if fastset is allowed by external dependencies like other
6478          * pipes and transcoders.
6479          *
6480          * Right now it only forces a fullmodeset when the MST master
6481          * transcoder did not changed but the pipe of the master transcoder
6482          * needs a fullmodeset so all slaves also needs to do a fullmodeset or
6483          * in case of port synced crtcs, if one of the synced crtcs
6484          * needs a full modeset, all other synced crtcs should be
6485          * forced a full modeset.
6486          */
6487         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6488                 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
6489                         continue;
6490
6491                 if (intel_dp_mst_crtc_needs_modeset(state, crtc))
6492                         intel_crtc_flag_modeset(new_crtc_state);
6493
6494                 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
6495                         enum transcoder master = new_crtc_state->mst_master_transcoder;
6496
6497                         if (intel_cpu_transcoders_need_modeset(state, BIT(master)))
6498                                 intel_crtc_flag_modeset(new_crtc_state);
6499                 }
6500
6501                 if (is_trans_port_sync_mode(new_crtc_state)) {
6502                         u8 trans = new_crtc_state->sync_mode_slaves_mask;
6503
6504                         if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
6505                                 trans |= BIT(new_crtc_state->master_transcoder);
6506
6507                         if (intel_cpu_transcoders_need_modeset(state, trans))
6508                                 intel_crtc_flag_modeset(new_crtc_state);
6509                 }
6510
6511                 if (new_crtc_state->bigjoiner_pipes) {
6512                         if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes))
6513                                 intel_crtc_flag_modeset(new_crtc_state);
6514                 }
6515         }
6516
6517         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6518                                             new_crtc_state, i) {
6519                 if (!intel_crtc_needs_modeset(new_crtc_state))
6520                         continue;
6521
6522                 any_ms = true;
6523
6524                 intel_release_shared_dplls(state, crtc);
6525         }
6526
6527         if (any_ms && !check_digital_port_conflicts(state)) {
6528                 drm_dbg_kms(&dev_priv->drm,
6529                             "rejecting conflicting digital port configuration\n");
6530                 ret = -EINVAL;
6531                 goto fail;
6532         }
6533
6534         ret = intel_atomic_check_planes(state);
6535         if (ret)
6536                 goto fail;
6537
6538         ret = intel_compute_global_watermarks(state);
6539         if (ret)
6540                 goto fail;
6541
6542         ret = intel_bw_atomic_check(state);
6543         if (ret)
6544                 goto fail;
6545
6546         ret = intel_cdclk_atomic_check(state, &any_ms);
6547         if (ret)
6548                 goto fail;
6549
6550         if (intel_any_crtc_needs_modeset(state))
6551                 any_ms = true;
6552
6553         if (any_ms) {
6554                 ret = intel_modeset_checks(state);
6555                 if (ret)
6556                         goto fail;
6557
6558                 ret = intel_modeset_calc_cdclk(state);
6559                 if (ret)
6560                         return ret;
6561         }
6562
6563         ret = intel_pmdemand_atomic_check(state);
6564         if (ret)
6565                 goto fail;
6566
6567         ret = intel_atomic_check_crtcs(state);
6568         if (ret)
6569                 goto fail;
6570
6571         ret = intel_fbc_atomic_check(state);
6572         if (ret)
6573                 goto fail;
6574
6575         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6576                                             new_crtc_state, i) {
6577                 intel_color_assert_luts(new_crtc_state);
6578
6579                 ret = intel_async_flip_check_hw(state, crtc);
6580                 if (ret)
6581                         goto fail;
6582
6583                 /* Either full modeset or fastset (or neither), never both */
6584                 drm_WARN_ON(&dev_priv->drm,
6585                             intel_crtc_needs_modeset(new_crtc_state) &&
6586                             intel_crtc_needs_fastset(new_crtc_state));
6587
6588                 if (!intel_crtc_needs_modeset(new_crtc_state) &&
6589                     !intel_crtc_needs_fastset(new_crtc_state))
6590                         continue;
6591
6592                 intel_crtc_state_dump(new_crtc_state, state,
6593                                       intel_crtc_needs_modeset(new_crtc_state) ?
6594                                       "modeset" : "fastset");
6595         }
6596
6597         return 0;
6598
6599  fail:
6600         if (ret == -EDEADLK)
6601                 return ret;
6602
6603         /*
6604          * FIXME would probably be nice to know which crtc specifically
6605          * caused the failure, in cases where we can pinpoint it.
6606          */
6607         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6608                                             new_crtc_state, i)
6609                 intel_crtc_state_dump(new_crtc_state, state, "failed");
6610
6611         return ret;
6612 }
6613
6614 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
6615 {
6616         struct intel_crtc_state *crtc_state;
6617         struct intel_crtc *crtc;
6618         int i, ret;
6619
6620         ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
6621         if (ret < 0)
6622                 return ret;
6623
6624         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6625                 if (intel_crtc_needs_color_update(crtc_state))
6626                         intel_color_prepare_commit(crtc_state);
6627         }
6628
6629         return 0;
6630 }
6631
6632 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
6633                                   struct intel_crtc_state *crtc_state)
6634 {
6635         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6636
6637         if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
6638                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
6639
6640         if (crtc_state->has_pch_encoder) {
6641                 enum pipe pch_transcoder =
6642                         intel_crtc_pch_transcoder(crtc);
6643
6644                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
6645         }
6646 }
6647
6648 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
6649                                const struct intel_crtc_state *new_crtc_state)
6650 {
6651         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6652         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6653
6654         /*
6655          * Update pipe size and adjust fitter if needed: the reason for this is
6656          * that in compute_mode_changes we check the native mode (not the pfit
6657          * mode) to see if we can flip rather than do a full mode set. In the
6658          * fastboot case, we'll flip, but if we don't update the pipesrc and
6659          * pfit state, we'll end up with a big fb scanned out into the wrong
6660          * sized surface.
6661          */
6662         intel_set_pipe_src_size(new_crtc_state);
6663
6664         /* on skylake this is done by detaching scalers */
6665         if (DISPLAY_VER(dev_priv) >= 9) {
6666                 if (new_crtc_state->pch_pfit.enabled)
6667                         skl_pfit_enable(new_crtc_state);
6668         } else if (HAS_PCH_SPLIT(dev_priv)) {
6669                 if (new_crtc_state->pch_pfit.enabled)
6670                         ilk_pfit_enable(new_crtc_state);
6671                 else if (old_crtc_state->pch_pfit.enabled)
6672                         ilk_pfit_disable(old_crtc_state);
6673         }
6674
6675         /*
6676          * The register is supposedly single buffered so perhaps
6677          * not 100% correct to do this here. But SKL+ calculate
6678          * this based on the adjust pixel rate so pfit changes do
6679          * affect it and so it must be updated for fastsets.
6680          * HSW/BDW only really need this here for fastboot, after
6681          * that the value should not change without a full modeset.
6682          */
6683         if (DISPLAY_VER(dev_priv) >= 9 ||
6684             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
6685                 hsw_set_linetime_wm(new_crtc_state);
6686
6687         if (new_crtc_state->update_m_n)
6688                 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
6689                                                &new_crtc_state->dp_m_n);
6690
6691         if (new_crtc_state->update_lrr)
6692                 intel_set_transcoder_timings_lrr(new_crtc_state);
6693 }
6694
6695 static void commit_pipe_pre_planes(struct intel_atomic_state *state,
6696                                    struct intel_crtc *crtc)
6697 {
6698         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6699         const struct intel_crtc_state *old_crtc_state =
6700                 intel_atomic_get_old_crtc_state(state, crtc);
6701         const struct intel_crtc_state *new_crtc_state =
6702                 intel_atomic_get_new_crtc_state(state, crtc);
6703         bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6704
6705         /*
6706          * During modesets pipe configuration was programmed as the
6707          * CRTC was enabled.
6708          */
6709         if (!modeset) {
6710                 if (intel_crtc_needs_color_update(new_crtc_state))
6711                         intel_color_commit_arm(new_crtc_state);
6712
6713                 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
6714                         bdw_set_pipe_misc(new_crtc_state);
6715
6716                 if (intel_crtc_needs_fastset(new_crtc_state))
6717                         intel_pipe_fastset(old_crtc_state, new_crtc_state);
6718         }
6719
6720         intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
6721
6722         intel_atomic_update_watermarks(state, crtc);
6723 }
6724
6725 static void commit_pipe_post_planes(struct intel_atomic_state *state,
6726                                     struct intel_crtc *crtc)
6727 {
6728         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6729         const struct intel_crtc_state *old_crtc_state =
6730                 intel_atomic_get_old_crtc_state(state, crtc);
6731         const struct intel_crtc_state *new_crtc_state =
6732                 intel_atomic_get_new_crtc_state(state, crtc);
6733
6734         /*
6735          * Disable the scaler(s) after the plane(s) so that we don't
6736          * get a catastrophic underrun even if the two operations
6737          * end up happening in two different frames.
6738          */
6739         if (DISPLAY_VER(dev_priv) >= 9 &&
6740             !intel_crtc_needs_modeset(new_crtc_state))
6741                 skl_detach_scalers(new_crtc_state);
6742
6743         if (vrr_enabling(old_crtc_state, new_crtc_state))
6744                 intel_vrr_enable(new_crtc_state);
6745 }
6746
6747 static void intel_enable_crtc(struct intel_atomic_state *state,
6748                               struct intel_crtc *crtc)
6749 {
6750         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6751         const struct intel_crtc_state *new_crtc_state =
6752                 intel_atomic_get_new_crtc_state(state, crtc);
6753         struct intel_crtc *pipe_crtc;
6754
6755         if (!intel_crtc_needs_modeset(new_crtc_state))
6756                 return;
6757
6758         for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
6759                                                  intel_crtc_joined_pipe_mask(new_crtc_state)) {
6760                 const struct intel_crtc_state *pipe_crtc_state =
6761                         intel_atomic_get_new_crtc_state(state, pipe_crtc);
6762
6763                 /* VRR will be enable later, if required */
6764                 intel_crtc_update_active_timings(pipe_crtc_state, false);
6765         }
6766
6767         dev_priv->display.funcs.display->crtc_enable(state, crtc);
6768
6769         /* vblanks work again, re-enable pipe CRC. */
6770         intel_crtc_enable_pipe_crc(crtc);
6771 }
6772
6773 static void intel_pre_update_crtc(struct intel_atomic_state *state,
6774                                   struct intel_crtc *crtc)
6775 {
6776         struct drm_i915_private *i915 = to_i915(state->base.dev);
6777         const struct intel_crtc_state *old_crtc_state =
6778                 intel_atomic_get_old_crtc_state(state, crtc);
6779         struct intel_crtc_state *new_crtc_state =
6780                 intel_atomic_get_new_crtc_state(state, crtc);
6781         bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6782
6783         if (old_crtc_state->inherited ||
6784             intel_crtc_needs_modeset(new_crtc_state)) {
6785                 if (HAS_DPT(i915))
6786                         intel_dpt_configure(crtc);
6787         }
6788
6789         if (!modeset) {
6790                 if (new_crtc_state->preload_luts &&
6791                     intel_crtc_needs_color_update(new_crtc_state))
6792                         intel_color_load_luts(new_crtc_state);
6793
6794                 intel_pre_plane_update(state, crtc);
6795
6796                 if (intel_crtc_needs_fastset(new_crtc_state))
6797                         intel_encoders_update_pipe(state, crtc);
6798
6799                 if (DISPLAY_VER(i915) >= 11 &&
6800                     intel_crtc_needs_fastset(new_crtc_state))
6801                         icl_set_pipe_chicken(new_crtc_state);
6802
6803                 if (vrr_params_changed(old_crtc_state, new_crtc_state))
6804                         intel_vrr_set_transcoder_timings(new_crtc_state);
6805         }
6806
6807         intel_fbc_update(state, crtc);
6808
6809         drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF));
6810
6811         if (!modeset &&
6812             intel_crtc_needs_color_update(new_crtc_state))
6813                 intel_color_commit_noarm(new_crtc_state);
6814
6815         intel_crtc_planes_update_noarm(state, crtc);
6816 }
6817
6818 static void intel_update_crtc(struct intel_atomic_state *state,
6819                               struct intel_crtc *crtc)
6820 {
6821         const struct intel_crtc_state *old_crtc_state =
6822                 intel_atomic_get_old_crtc_state(state, crtc);
6823         struct intel_crtc_state *new_crtc_state =
6824                 intel_atomic_get_new_crtc_state(state, crtc);
6825
6826         /* Perform vblank evasion around commit operation */
6827         intel_pipe_update_start(state, crtc);
6828
6829         commit_pipe_pre_planes(state, crtc);
6830
6831         intel_crtc_planes_update_arm(state, crtc);
6832
6833         commit_pipe_post_planes(state, crtc);
6834
6835         intel_pipe_update_end(state, crtc);
6836
6837         /*
6838          * VRR/Seamless M/N update may need to update frame timings.
6839          *
6840          * FIXME Should be synchronized with the start of vblank somehow...
6841          */
6842         if (vrr_enabling(old_crtc_state, new_crtc_state) ||
6843             new_crtc_state->update_m_n || new_crtc_state->update_lrr)
6844                 intel_crtc_update_active_timings(new_crtc_state,
6845                                                  new_crtc_state->vrr.enable);
6846
6847         /*
6848          * We usually enable FIFO underrun interrupts as part of the
6849          * CRTC enable sequence during modesets.  But when we inherit a
6850          * valid pipe configuration from the BIOS we need to take care
6851          * of enabling them on the CRTC's first fastset.
6852          */
6853         if (intel_crtc_needs_fastset(new_crtc_state) &&
6854             old_crtc_state->inherited)
6855                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
6856 }
6857
6858 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
6859                                           struct intel_crtc *crtc)
6860 {
6861         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6862         const struct intel_crtc_state *old_crtc_state =
6863                 intel_atomic_get_old_crtc_state(state, crtc);
6864         struct intel_crtc *pipe_crtc;
6865
6866         /*
6867          * We need to disable pipe CRC before disabling the pipe,
6868          * or we race against vblank off.
6869          */
6870         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,
6871                                          intel_crtc_joined_pipe_mask(old_crtc_state))
6872                 intel_crtc_disable_pipe_crc(pipe_crtc);
6873
6874         dev_priv->display.funcs.display->crtc_disable(state, crtc);
6875
6876         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,
6877                                          intel_crtc_joined_pipe_mask(old_crtc_state)) {
6878                 const struct intel_crtc_state *new_pipe_crtc_state =
6879                         intel_atomic_get_new_crtc_state(state, pipe_crtc);
6880
6881                 pipe_crtc->active = false;
6882                 intel_fbc_disable(pipe_crtc);
6883
6884                 if (!new_pipe_crtc_state->hw.active)
6885                         intel_initial_watermarks(state, pipe_crtc);
6886         }
6887 }
6888
6889 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
6890 {
6891         struct drm_i915_private *i915 = to_i915(state->base.dev);
6892         const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
6893         struct intel_crtc *crtc;
6894         u8 disable_pipes = 0;
6895         int i;
6896
6897         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6898                                             new_crtc_state, i) {
6899                 if (!intel_crtc_needs_modeset(new_crtc_state))
6900                         continue;
6901
6902                 /*
6903                  * Needs to be done even for pipes
6904                  * that weren't enabled previously.
6905                  */
6906                 intel_pre_plane_update(state, crtc);
6907
6908                 if (!old_crtc_state->hw.active)
6909                         continue;
6910
6911                 disable_pipes |= BIT(crtc->pipe);
6912         }
6913
6914         for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) {
6915                 if ((disable_pipes & BIT(crtc->pipe)) == 0)
6916                         continue;
6917
6918                 intel_crtc_disable_planes(state, crtc);
6919         }
6920
6921         /* Only disable port sync and MST slaves */
6922         for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) {
6923                 if ((disable_pipes & BIT(crtc->pipe)) == 0)
6924                         continue;
6925
6926                 if (intel_crtc_is_bigjoiner_slave(old_crtc_state))
6927                         continue;
6928
6929                 /* In case of Transcoder port Sync master slave CRTCs can be
6930                  * assigned in any order and we need to make sure that
6931                  * slave CRTCs are disabled first and then master CRTC since
6932                  * Slave vblanks are masked till Master Vblanks.
6933                  */
6934                 if (!is_trans_port_sync_slave(old_crtc_state) &&
6935                     !intel_dp_mst_is_slave_trans(old_crtc_state))
6936                         continue;
6937
6938                 intel_old_crtc_state_disables(state, crtc);
6939
6940                 disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state);
6941         }
6942
6943         /* Disable everything else left on */
6944         for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) {
6945                 if ((disable_pipes & BIT(crtc->pipe)) == 0)
6946                         continue;
6947
6948                 if (intel_crtc_is_bigjoiner_slave(old_crtc_state))
6949                         continue;
6950
6951                 intel_old_crtc_state_disables(state, crtc);
6952
6953                 disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state);
6954         }
6955
6956         drm_WARN_ON(&i915->drm, disable_pipes);
6957 }
6958
6959 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
6960 {
6961         struct intel_crtc_state *new_crtc_state;
6962         struct intel_crtc *crtc;
6963         int i;
6964
6965         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6966                 if (!new_crtc_state->hw.active)
6967                         continue;
6968
6969                 intel_enable_crtc(state, crtc);
6970                 intel_pre_update_crtc(state, crtc);
6971         }
6972
6973         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6974                 if (!new_crtc_state->hw.active)
6975                         continue;
6976
6977                 intel_update_crtc(state, crtc);
6978         }
6979 }
6980
6981 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
6982 {
6983         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6984         struct intel_crtc *crtc;
6985         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6986         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
6987         u8 update_pipes = 0, modeset_pipes = 0;
6988         int i;
6989
6990         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6991                 enum pipe pipe = crtc->pipe;
6992
6993                 if (!new_crtc_state->hw.active)
6994                         continue;
6995
6996                 /* ignore allocations for crtc's that have been turned off. */
6997                 if (!intel_crtc_needs_modeset(new_crtc_state)) {
6998                         entries[pipe] = old_crtc_state->wm.skl.ddb;
6999                         update_pipes |= BIT(pipe);
7000                 } else {
7001                         modeset_pipes |= BIT(pipe);
7002                 }
7003         }
7004
7005         /*
7006          * Whenever the number of active pipes changes, we need to make sure we
7007          * update the pipes in the right order so that their ddb allocations
7008          * never overlap with each other between CRTC updates. Otherwise we'll
7009          * cause pipe underruns and other bad stuff.
7010          *
7011          * So first lets enable all pipes that do not need a fullmodeset as
7012          * those don't have any external dependency.
7013          */
7014         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7015                 enum pipe pipe = crtc->pipe;
7016
7017                 if ((update_pipes & BIT(pipe)) == 0)
7018                         continue;
7019
7020                 intel_pre_update_crtc(state, crtc);
7021         }
7022
7023         intel_dbuf_mbus_pre_ddb_update(state);
7024
7025         while (update_pipes) {
7026                 /*
7027                  * Commit in reverse order to make bigjoiner master
7028                  * send the uapi events after slaves are done.
7029                  */
7030                 for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state,
7031                                                             new_crtc_state, i) {
7032                         enum pipe pipe = crtc->pipe;
7033
7034                         if ((update_pipes & BIT(pipe)) == 0)
7035                                 continue;
7036
7037                         if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7038                                                         entries, I915_MAX_PIPES, pipe))
7039                                 continue;
7040
7041                         entries[pipe] = new_crtc_state->wm.skl.ddb;
7042                         update_pipes &= ~BIT(pipe);
7043
7044                         intel_update_crtc(state, crtc);
7045
7046                         /*
7047                          * If this is an already active pipe, it's DDB changed,
7048                          * and this isn't the last pipe that needs updating
7049                          * then we need to wait for a vblank to pass for the
7050                          * new ddb allocation to take effect.
7051                          */
7052                         if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
7053                                                  &old_crtc_state->wm.skl.ddb) &&
7054                             (update_pipes | modeset_pipes))
7055                                 intel_crtc_wait_for_next_vblank(crtc);
7056                 }
7057         }
7058
7059         intel_dbuf_mbus_post_ddb_update(state);
7060
7061         update_pipes = modeset_pipes;
7062
7063         /*
7064          * Enable all pipes that needs a modeset and do not depends on other
7065          * pipes
7066          */
7067         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7068                 enum pipe pipe = crtc->pipe;
7069
7070                 if ((modeset_pipes & BIT(pipe)) == 0)
7071                         continue;
7072
7073                 if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
7074                         continue;
7075
7076                 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
7077                     is_trans_port_sync_master(new_crtc_state))
7078                         continue;
7079
7080                 modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state);
7081
7082                 intel_enable_crtc(state, crtc);
7083         }
7084
7085         /*
7086          * Then we enable all remaining pipes that depend on other
7087          * pipes: MST slaves and port sync masters, big joiner master
7088          */
7089         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7090                 enum pipe pipe = crtc->pipe;
7091
7092                 if ((modeset_pipes & BIT(pipe)) == 0)
7093                         continue;
7094
7095                 if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
7096                         continue;
7097
7098                 modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state);
7099
7100                 intel_enable_crtc(state, crtc);
7101         }
7102
7103         /*
7104          * Finally we do the plane updates/etc. for all pipes that got enabled.
7105          */
7106         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7107                 enum pipe pipe = crtc->pipe;
7108
7109                 if ((update_pipes & BIT(pipe)) == 0)
7110                         continue;
7111
7112                 intel_pre_update_crtc(state, crtc);
7113         }
7114
7115         /*
7116          * Commit in reverse order to make bigjoiner master
7117          * send the uapi events after slaves are done.
7118          */
7119         for_each_new_intel_crtc_in_state_reverse(state, crtc, new_crtc_state, i) {
7120                 enum pipe pipe = crtc->pipe;
7121
7122                 if ((update_pipes & BIT(pipe)) == 0)
7123                         continue;
7124
7125                 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7126                                                                         entries, I915_MAX_PIPES, pipe));
7127
7128                 entries[pipe] = new_crtc_state->wm.skl.ddb;
7129                 update_pipes &= ~BIT(pipe);
7130
7131                 intel_update_crtc(state, crtc);
7132         }
7133
7134         drm_WARN_ON(&dev_priv->drm, modeset_pipes);
7135         drm_WARN_ON(&dev_priv->drm, update_pipes);
7136 }
7137
7138 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
7139 {
7140         struct drm_i915_private *i915 = to_i915(intel_state->base.dev);
7141         struct drm_plane *plane;
7142         struct drm_plane_state *new_plane_state;
7143         int ret, i;
7144
7145         for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) {
7146                 if (new_plane_state->fence) {
7147                         ret = dma_fence_wait_timeout(new_plane_state->fence, false,
7148                                                      i915_fence_timeout(i915));
7149                         if (ret <= 0)
7150                                 break;
7151
7152                         dma_fence_put(new_plane_state->fence);
7153                         new_plane_state->fence = NULL;
7154                 }
7155         }
7156 }
7157
7158 static void intel_atomic_cleanup_work(struct work_struct *work)
7159 {
7160         struct intel_atomic_state *state =
7161                 container_of(work, struct intel_atomic_state, base.commit_work);
7162         struct drm_i915_private *i915 = to_i915(state->base.dev);
7163         struct intel_crtc_state *old_crtc_state;
7164         struct intel_crtc *crtc;
7165         int i;
7166
7167         for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i)
7168                 intel_color_cleanup_commit(old_crtc_state);
7169
7170         drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
7171         drm_atomic_helper_commit_cleanup_done(&state->base);
7172         drm_atomic_state_put(&state->base);
7173 }
7174
7175 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
7176 {
7177         struct drm_i915_private *i915 = to_i915(state->base.dev);
7178         struct intel_plane *plane;
7179         struct intel_plane_state *plane_state;
7180         int i;
7181
7182         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7183                 struct drm_framebuffer *fb = plane_state->hw.fb;
7184                 int cc_plane;
7185                 int ret;
7186
7187                 if (!fb)
7188                         continue;
7189
7190                 cc_plane = intel_fb_rc_ccs_cc_plane(fb);
7191                 if (cc_plane < 0)
7192                         continue;
7193
7194                 /*
7195                  * The layout of the fast clear color value expected by HW
7196                  * (the DRM ABI requiring this value to be located in fb at
7197                  * offset 0 of cc plane, plane #2 previous generations or
7198                  * plane #1 for flat ccs):
7199                  * - 4 x 4 bytes per-channel value
7200                  *   (in surface type specific float/int format provided by the fb user)
7201                  * - 8 bytes native color value used by the display
7202                  *   (converted/written by GPU during a fast clear operation using the
7203                  *    above per-channel values)
7204                  *
7205                  * The commit's FB prepare hook already ensured that FB obj is pinned and the
7206                  * caller made sure that the object is synced wrt. the related color clear value
7207                  * GPU write on it.
7208                  */
7209                 ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
7210                                                      fb->offsets[cc_plane] + 16,
7211                                                      &plane_state->ccval,
7212                                                      sizeof(plane_state->ccval));
7213                 /* The above could only fail if the FB obj has an unexpected backing store type. */
7214                 drm_WARN_ON(&i915->drm, ret);
7215         }
7216 }
7217
7218 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
7219 {
7220         struct drm_device *dev = state->base.dev;
7221         struct drm_i915_private *dev_priv = to_i915(dev);
7222         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
7223         struct intel_crtc *crtc;
7224         struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
7225         intel_wakeref_t wakeref = 0;
7226         int i;
7227
7228         intel_atomic_commit_fence_wait(state);
7229
7230         drm_atomic_helper_wait_for_dependencies(&state->base);
7231         drm_dp_mst_atomic_wait_for_dependencies(&state->base);
7232         intel_atomic_global_state_wait_for_dependencies(state);
7233
7234         /*
7235          * During full modesets we write a lot of registers, wait
7236          * for PLLs, etc. Doing that while DC states are enabled
7237          * is not a good idea.
7238          *
7239          * During fastsets and other updates we also need to
7240          * disable DC states due to the following scenario:
7241          * 1. DC5 exit and PSR exit happen
7242          * 2. Some or all _noarm() registers are written
7243          * 3. Due to some long delay PSR is re-entered
7244          * 4. DC5 entry -> DMC saves the already written new
7245          *    _noarm() registers and the old not yet written
7246          *    _arm() registers
7247          * 5. DC5 exit -> DMC restores a mixture of old and
7248          *    new register values and arms the update
7249          * 6. PSR exit -> hardware latches a mixture of old and
7250          *    new register values -> corrupted frame, or worse
7251          * 7. New _arm() registers are finally written
7252          * 8. Hardware finally latches a complete set of new
7253          *    register values, and subsequent frames will be OK again
7254          *
7255          * Also note that due to the pipe CSC hardware issues on
7256          * SKL/GLK DC states must remain off until the pipe CSC
7257          * state readout has happened. Otherwise we risk corrupting
7258          * the CSC latched register values with the readout (see
7259          * skl_read_csc() and skl_color_commit_noarm()).
7260          */
7261         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DC_OFF);
7262
7263         intel_atomic_prepare_plane_clear_colors(state);
7264
7265         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7266                                             new_crtc_state, i) {
7267                 if (intel_crtc_needs_modeset(new_crtc_state) ||
7268                     intel_crtc_needs_fastset(new_crtc_state))
7269                         intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
7270         }
7271
7272         intel_commit_modeset_disables(state);
7273
7274         intel_dp_tunnel_atomic_alloc_bw(state);
7275
7276         /* FIXME: Eventually get rid of our crtc->config pointer */
7277         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7278                 crtc->config = new_crtc_state;
7279
7280         /*
7281          * In XE_LPD+ Pmdemand combines many parameters such as voltage index,
7282          * plls, cdclk frequency, QGV point selection parameter etc. Voltage
7283          * index, cdclk/ddiclk frequencies are supposed to be configured before
7284          * the cdclk config is set.
7285          */
7286         intel_pmdemand_pre_plane_update(state);
7287
7288         if (state->modeset) {
7289                 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
7290
7291                 intel_set_cdclk_pre_plane_update(state);
7292
7293                 intel_modeset_verify_disabled(state);
7294         }
7295
7296         intel_sagv_pre_plane_update(state);
7297
7298         /* Complete the events for pipes that have now been disabled */
7299         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7300                 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7301
7302                 /* Complete events for now disable pipes here. */
7303                 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
7304                         spin_lock_irq(&dev->event_lock);
7305                         drm_crtc_send_vblank_event(&crtc->base,
7306                                                    new_crtc_state->uapi.event);
7307                         spin_unlock_irq(&dev->event_lock);
7308
7309                         new_crtc_state->uapi.event = NULL;
7310                 }
7311         }
7312
7313         intel_encoders_update_prepare(state);
7314
7315         intel_dbuf_pre_plane_update(state);
7316
7317         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7318                 if (new_crtc_state->do_async_flip)
7319                         intel_crtc_enable_flip_done(state, crtc);
7320         }
7321
7322         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7323         dev_priv->display.funcs.display->commit_modeset_enables(state);
7324
7325         if (state->modeset)
7326                 intel_set_cdclk_post_plane_update(state);
7327
7328         intel_wait_for_vblank_workers(state);
7329
7330         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
7331          * already, but still need the state for the delayed optimization. To
7332          * fix this:
7333          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
7334          * - schedule that vblank worker _before_ calling hw_done
7335          * - at the start of commit_tail, cancel it _synchrously
7336          * - switch over to the vblank wait helper in the core after that since
7337          *   we don't need out special handling any more.
7338          */
7339         drm_atomic_helper_wait_for_flip_done(dev, &state->base);
7340
7341         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7342                 if (new_crtc_state->do_async_flip)
7343                         intel_crtc_disable_flip_done(state, crtc);
7344
7345                 intel_color_wait_commit(new_crtc_state);
7346         }
7347
7348         /*
7349          * Now that the vblank has passed, we can go ahead and program the
7350          * optimal watermarks on platforms that need two-step watermark
7351          * programming.
7352          *
7353          * TODO: Move this (and other cleanup) to an async worker eventually.
7354          */
7355         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7356                                             new_crtc_state, i) {
7357                 /*
7358                  * Gen2 reports pipe underruns whenever all planes are disabled.
7359                  * So re-enable underrun reporting after some planes get enabled.
7360                  *
7361                  * We do this before .optimize_watermarks() so that we have a
7362                  * chance of catching underruns with the intermediate watermarks
7363                  * vs. the new plane configuration.
7364                  */
7365                 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
7366                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
7367
7368                 intel_optimize_watermarks(state, crtc);
7369         }
7370
7371         intel_dbuf_post_plane_update(state);
7372
7373         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7374                 intel_post_plane_update(state, crtc);
7375
7376                 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
7377
7378                 intel_modeset_verify_crtc(state, crtc);
7379
7380                 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */
7381                 hsw_ips_post_update(state, crtc);
7382
7383                 /*
7384                  * Activate DRRS after state readout to avoid
7385                  * dp_m_n vs. dp_m2_n2 confusion on BDW+.
7386                  */
7387                 intel_drrs_activate(new_crtc_state);
7388
7389                 /*
7390                  * DSB cleanup is done in cleanup_work aligning with framebuffer
7391                  * cleanup. So copy and reset the dsb structure to sync with
7392                  * commit_done and later do dsb cleanup in cleanup_work.
7393                  *
7394                  * FIXME get rid of this funny new->old swapping
7395                  */
7396                 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
7397         }
7398
7399         /* Underruns don't always raise interrupts, so check manually */
7400         intel_check_cpu_fifo_underruns(dev_priv);
7401         intel_check_pch_fifo_underruns(dev_priv);
7402
7403         if (state->modeset)
7404                 intel_verify_planes(state);
7405
7406         intel_sagv_post_plane_update(state);
7407         intel_pmdemand_post_plane_update(state);
7408
7409         drm_atomic_helper_commit_hw_done(&state->base);
7410         intel_atomic_global_state_commit_done(state);
7411
7412         if (state->modeset) {
7413                 /* As one of the primary mmio accessors, KMS has a high
7414                  * likelihood of triggering bugs in unclaimed access. After we
7415                  * finish modesetting, see if an error has been flagged, and if
7416                  * so enable debugging for the next modeset - and hope we catch
7417                  * the culprit.
7418                  */
7419                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
7420         }
7421         /*
7422          * Delay re-enabling DC states by 17 ms to avoid the off->on->off
7423          * toggling overhead at and above 60 FPS.
7424          */
7425         intel_display_power_put_async_delay(dev_priv, POWER_DOMAIN_DC_OFF, wakeref, 17);
7426         intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7427
7428         /*
7429          * Defer the cleanup of the old state to a separate worker to not
7430          * impede the current task (userspace for blocking modesets) that
7431          * are executed inline. For out-of-line asynchronous modesets/flips,
7432          * deferring to a new worker seems overkill, but we would place a
7433          * schedule point (cond_resched()) here anyway to keep latencies
7434          * down.
7435          */
7436         INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
7437         queue_work(system_highpri_wq, &state->base.commit_work);
7438 }
7439
7440 static void intel_atomic_commit_work(struct work_struct *work)
7441 {
7442         struct intel_atomic_state *state =
7443                 container_of(work, struct intel_atomic_state, base.commit_work);
7444
7445         intel_atomic_commit_tail(state);
7446 }
7447
7448 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
7449 {
7450         struct intel_plane_state *old_plane_state, *new_plane_state;
7451         struct intel_plane *plane;
7452         int i;
7453
7454         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
7455                                              new_plane_state, i)
7456                 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
7457                                         to_intel_frontbuffer(new_plane_state->hw.fb),
7458                                         plane->frontbuffer_bit);
7459 }
7460
7461 static int intel_atomic_setup_commit(struct intel_atomic_state *state, bool nonblock)
7462 {
7463         int ret;
7464
7465         ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
7466         if (ret)
7467                 return ret;
7468
7469         ret = intel_atomic_global_state_setup_commit(state);
7470         if (ret)
7471                 return ret;
7472
7473         return 0;
7474 }
7475
7476 static int intel_atomic_swap_state(struct intel_atomic_state *state)
7477 {
7478         int ret;
7479
7480         ret = drm_atomic_helper_swap_state(&state->base, true);
7481         if (ret)
7482                 return ret;
7483
7484         intel_atomic_swap_global_state(state);
7485
7486         intel_shared_dpll_swap_state(state);
7487
7488         intel_atomic_track_fbs(state);
7489
7490         return 0;
7491 }
7492
7493 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
7494                         bool nonblock)
7495 {
7496         struct intel_atomic_state *state = to_intel_atomic_state(_state);
7497         struct drm_i915_private *dev_priv = to_i915(dev);
7498         int ret = 0;
7499
7500         state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
7501
7502         /*
7503          * The intel_legacy_cursor_update() fast path takes care
7504          * of avoiding the vblank waits for simple cursor
7505          * movement and flips. For cursor on/off and size changes,
7506          * we want to perform the vblank waits so that watermark
7507          * updates happen during the correct frames. Gen9+ have
7508          * double buffered watermarks and so shouldn't need this.
7509          *
7510          * Unset state->legacy_cursor_update before the call to
7511          * drm_atomic_helper_setup_commit() because otherwise
7512          * drm_atomic_helper_wait_for_flip_done() is a noop and
7513          * we get FIFO underruns because we didn't wait
7514          * for vblank.
7515          *
7516          * FIXME doing watermarks and fb cleanup from a vblank worker
7517          * (assuming we had any) would solve these problems.
7518          */
7519         if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {
7520                 struct intel_crtc_state *new_crtc_state;
7521                 struct intel_crtc *crtc;
7522                 int i;
7523
7524                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7525                         if (new_crtc_state->wm.need_postvbl_update ||
7526                             new_crtc_state->update_wm_post)
7527                                 state->base.legacy_cursor_update = false;
7528         }
7529
7530         ret = intel_atomic_prepare_commit(state);
7531         if (ret) {
7532                 drm_dbg_atomic(&dev_priv->drm,
7533                                "Preparing state failed with %i\n", ret);
7534                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7535                 return ret;
7536         }
7537
7538         ret = intel_atomic_setup_commit(state, nonblock);
7539         if (!ret)
7540                 ret = intel_atomic_swap_state(state);
7541
7542         if (ret) {
7543                 struct intel_crtc_state *new_crtc_state;
7544                 struct intel_crtc *crtc;
7545                 int i;
7546
7547                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7548                         intel_color_cleanup_commit(new_crtc_state);
7549
7550                 drm_atomic_helper_unprepare_planes(dev, &state->base);
7551                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7552                 return ret;
7553         }
7554
7555         drm_atomic_state_get(&state->base);
7556         INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
7557
7558         if (nonblock && state->modeset) {
7559                 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work);
7560         } else if (nonblock) {
7561                 queue_work(dev_priv->display.wq.flip, &state->base.commit_work);
7562         } else {
7563                 if (state->modeset)
7564                         flush_workqueue(dev_priv->display.wq.modeset);
7565                 intel_atomic_commit_tail(state);
7566         }
7567
7568         return 0;
7569 }
7570
7571 /**
7572  * intel_plane_destroy - destroy a plane
7573  * @plane: plane to destroy
7574  *
7575  * Common destruction function for all types of planes (primary, cursor,
7576  * sprite).
7577  */
7578 void intel_plane_destroy(struct drm_plane *plane)
7579 {
7580         drm_plane_cleanup(plane);
7581         kfree(to_intel_plane(plane));
7582 }
7583
7584 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
7585                                       struct drm_file *file)
7586 {
7587         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7588         struct drm_crtc *drmmode_crtc;
7589         struct intel_crtc *crtc;
7590
7591         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
7592         if (!drmmode_crtc)
7593                 return -ENOENT;
7594
7595         crtc = to_intel_crtc(drmmode_crtc);
7596         pipe_from_crtc_id->pipe = crtc->pipe;
7597
7598         return 0;
7599 }
7600
7601 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
7602 {
7603         struct drm_device *dev = encoder->base.dev;
7604         struct intel_encoder *source_encoder;
7605         u32 possible_clones = 0;
7606
7607         for_each_intel_encoder(dev, source_encoder) {
7608                 if (encoders_cloneable(encoder, source_encoder))
7609                         possible_clones |= drm_encoder_mask(&source_encoder->base);
7610         }
7611
7612         return possible_clones;
7613 }
7614
7615 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
7616 {
7617         struct drm_device *dev = encoder->base.dev;
7618         struct intel_crtc *crtc;
7619         u32 possible_crtcs = 0;
7620
7621         for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask)
7622                 possible_crtcs |= drm_crtc_mask(&crtc->base);
7623
7624         return possible_crtcs;
7625 }
7626
7627 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
7628 {
7629         if (!IS_MOBILE(dev_priv))
7630                 return false;
7631
7632         if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
7633                 return false;
7634
7635         if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
7636                 return false;
7637
7638         return true;
7639 }
7640
7641 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
7642 {
7643         if (DISPLAY_VER(dev_priv) >= 9)
7644                 return false;
7645
7646         if (IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv))
7647                 return false;
7648
7649         if (HAS_PCH_LPT_H(dev_priv) &&
7650             intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
7651                 return false;
7652
7653         /* DDI E can't be used if DDI A requires 4 lanes */
7654         if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
7655                 return false;
7656
7657         if (!dev_priv->display.vbt.int_crt_support)
7658                 return false;
7659
7660         return true;
7661 }
7662
7663 bool assert_port_valid(struct drm_i915_private *i915, enum port port)
7664 {
7665         return !drm_WARN(&i915->drm, !(DISPLAY_RUNTIME_INFO(i915)->port_mask & BIT(port)),
7666                          "Platform does not support port %c\n", port_name(port));
7667 }
7668
7669 void intel_setup_outputs(struct drm_i915_private *dev_priv)
7670 {
7671         struct intel_encoder *encoder;
7672         bool dpd_is_edp = false;
7673
7674         intel_pps_unlock_regs_wa(dev_priv);
7675
7676         if (!HAS_DISPLAY(dev_priv))
7677                 return;
7678
7679         if (HAS_DDI(dev_priv)) {
7680                 if (intel_ddi_crt_present(dev_priv))
7681                         intel_crt_init(dev_priv);
7682
7683                 intel_bios_for_each_encoder(dev_priv, intel_ddi_init);
7684
7685                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
7686                         vlv_dsi_init(dev_priv);
7687         } else if (HAS_PCH_SPLIT(dev_priv)) {
7688                 int found;
7689
7690                 /*
7691                  * intel_edp_init_connector() depends on this completing first,
7692                  * to prevent the registration of both eDP and LVDS and the
7693                  * incorrect sharing of the PPS.
7694                  */
7695                 intel_lvds_init(dev_priv);
7696                 intel_crt_init(dev_priv);
7697
7698                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
7699
7700                 if (ilk_has_edp_a(dev_priv))
7701                         g4x_dp_init(dev_priv, DP_A, PORT_A);
7702
7703                 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
7704                         /* PCH SDVOB multiplex with HDMIB */
7705                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
7706                         if (!found)
7707                                 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
7708                         if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
7709                                 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
7710                 }
7711
7712                 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
7713                         g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
7714
7715                 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
7716                         g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
7717
7718                 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
7719                         g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
7720
7721                 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
7722                         g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
7723         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7724                 bool has_edp, has_port;
7725
7726                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support)
7727                         intel_crt_init(dev_priv);
7728
7729                 /*
7730                  * The DP_DETECTED bit is the latched state of the DDC
7731                  * SDA pin at boot. However since eDP doesn't require DDC
7732                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
7733                  * eDP ports may have been muxed to an alternate function.
7734                  * Thus we can't rely on the DP_DETECTED bit alone to detect
7735                  * eDP ports. Consult the VBT as well as DP_DETECTED to
7736                  * detect eDP ports.
7737                  *
7738                  * Sadly the straps seem to be missing sometimes even for HDMI
7739                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
7740                  * and VBT for the presence of the port. Additionally we can't
7741                  * trust the port type the VBT declares as we've seen at least
7742                  * HDMI ports that the VBT claim are DP or eDP.
7743                  */
7744                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
7745                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
7746                 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
7747                         has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
7748                 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
7749                         g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
7750
7751                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
7752                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
7753                 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
7754                         has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
7755                 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
7756                         g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
7757
7758                 if (IS_CHERRYVIEW(dev_priv)) {
7759                         /*
7760                          * eDP not supported on port D,
7761                          * so no need to worry about it
7762                          */
7763                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
7764                         if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
7765                                 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
7766                         if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
7767                                 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
7768                 }
7769
7770                 vlv_dsi_init(dev_priv);
7771         } else if (IS_PINEVIEW(dev_priv)) {
7772                 intel_lvds_init(dev_priv);
7773                 intel_crt_init(dev_priv);
7774         } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
7775                 bool found = false;
7776
7777                 if (IS_MOBILE(dev_priv))
7778                         intel_lvds_init(dev_priv);
7779
7780                 intel_crt_init(dev_priv);
7781
7782                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
7783                         drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
7784                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
7785                         if (!found && IS_G4X(dev_priv)) {
7786                                 drm_dbg_kms(&dev_priv->drm,
7787                                             "probing HDMI on SDVOB\n");
7788                                 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
7789                         }
7790
7791                         if (!found && IS_G4X(dev_priv))
7792                                 g4x_dp_init(dev_priv, DP_B, PORT_B);
7793                 }
7794
7795                 /* Before G4X SDVOC doesn't have its own detect register */
7796
7797                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
7798                         drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
7799                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
7800                 }
7801
7802                 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
7803
7804                         if (IS_G4X(dev_priv)) {
7805                                 drm_dbg_kms(&dev_priv->drm,
7806                                             "probing HDMI on SDVOC\n");
7807                                 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
7808                         }
7809                         if (IS_G4X(dev_priv))
7810                                 g4x_dp_init(dev_priv, DP_C, PORT_C);
7811                 }
7812
7813                 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
7814                         g4x_dp_init(dev_priv, DP_D, PORT_D);
7815
7816                 if (SUPPORTS_TV(dev_priv))
7817                         intel_tv_init(dev_priv);
7818         } else if (DISPLAY_VER(dev_priv) == 2) {
7819                 if (IS_I85X(dev_priv))
7820                         intel_lvds_init(dev_priv);
7821
7822                 intel_crt_init(dev_priv);
7823                 intel_dvo_init(dev_priv);
7824         }
7825
7826         for_each_intel_encoder(&dev_priv->drm, encoder) {
7827                 encoder->base.possible_crtcs =
7828                         intel_encoder_possible_crtcs(encoder);
7829                 encoder->base.possible_clones =
7830                         intel_encoder_possible_clones(encoder);
7831         }
7832
7833         intel_init_pch_refclk(dev_priv);
7834
7835         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
7836 }
7837
7838 static int max_dotclock(struct drm_i915_private *i915)
7839 {
7840         int max_dotclock = i915->display.cdclk.max_dotclk_freq;
7841
7842         /* icl+ might use bigjoiner */
7843         if (DISPLAY_VER(i915) >= 11)
7844                 max_dotclock *= 2;
7845
7846         return max_dotclock;
7847 }
7848
7849 enum drm_mode_status intel_mode_valid(struct drm_device *dev,
7850                                       const struct drm_display_mode *mode)
7851 {
7852         struct drm_i915_private *dev_priv = to_i915(dev);
7853         int hdisplay_max, htotal_max;
7854         int vdisplay_max, vtotal_max;
7855
7856         /*
7857          * Can't reject DBLSCAN here because Xorg ddxen can add piles
7858          * of DBLSCAN modes to the output's mode list when they detect
7859          * the scaling mode property on the connector. And they don't
7860          * ask the kernel to validate those modes in any way until
7861          * modeset time at which point the client gets a protocol error.
7862          * So in order to not upset those clients we silently ignore the
7863          * DBLSCAN flag on such connectors. For other connectors we will
7864          * reject modes with the DBLSCAN flag in encoder->compute_config().
7865          * And we always reject DBLSCAN modes in connector->mode_valid()
7866          * as we never want such modes on the connector's mode list.
7867          */
7868
7869         if (mode->vscan > 1)
7870                 return MODE_NO_VSCAN;
7871
7872         if (mode->flags & DRM_MODE_FLAG_HSKEW)
7873                 return MODE_H_ILLEGAL;
7874
7875         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
7876                            DRM_MODE_FLAG_NCSYNC |
7877                            DRM_MODE_FLAG_PCSYNC))
7878                 return MODE_HSYNC;
7879
7880         if (mode->flags & (DRM_MODE_FLAG_BCAST |
7881                            DRM_MODE_FLAG_PIXMUX |
7882                            DRM_MODE_FLAG_CLKDIV2))
7883                 return MODE_BAD;
7884
7885         /*
7886          * Reject clearly excessive dotclocks early to
7887          * avoid having to worry about huge integers later.
7888          */
7889         if (mode->clock > max_dotclock(dev_priv))
7890                 return MODE_CLOCK_HIGH;
7891
7892         /* Transcoder timing limits */
7893         if (DISPLAY_VER(dev_priv) >= 11) {
7894                 hdisplay_max = 16384;
7895                 vdisplay_max = 8192;
7896                 htotal_max = 16384;
7897                 vtotal_max = 8192;
7898         } else if (DISPLAY_VER(dev_priv) >= 9 ||
7899                    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
7900                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
7901                 vdisplay_max = 4096;
7902                 htotal_max = 8192;
7903                 vtotal_max = 8192;
7904         } else if (DISPLAY_VER(dev_priv) >= 3) {
7905                 hdisplay_max = 4096;
7906                 vdisplay_max = 4096;
7907                 htotal_max = 8192;
7908                 vtotal_max = 8192;
7909         } else {
7910                 hdisplay_max = 2048;
7911                 vdisplay_max = 2048;
7912                 htotal_max = 4096;
7913                 vtotal_max = 4096;
7914         }
7915
7916         if (mode->hdisplay > hdisplay_max ||
7917             mode->hsync_start > htotal_max ||
7918             mode->hsync_end > htotal_max ||
7919             mode->htotal > htotal_max)
7920                 return MODE_H_ILLEGAL;
7921
7922         if (mode->vdisplay > vdisplay_max ||
7923             mode->vsync_start > vtotal_max ||
7924             mode->vsync_end > vtotal_max ||
7925             mode->vtotal > vtotal_max)
7926                 return MODE_V_ILLEGAL;
7927
7928         return MODE_OK;
7929 }
7930
7931 enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *dev_priv,
7932                                                      const struct drm_display_mode *mode)
7933 {
7934         /*
7935          * Additional transcoder timing limits,
7936          * excluding BXT/GLK DSI transcoders.
7937          */
7938         if (DISPLAY_VER(dev_priv) >= 5) {
7939                 if (mode->hdisplay < 64 ||
7940                     mode->htotal - mode->hdisplay < 32)
7941                         return MODE_H_ILLEGAL;
7942
7943                 if (mode->vtotal - mode->vdisplay < 5)
7944                         return MODE_V_ILLEGAL;
7945         } else {
7946                 if (mode->htotal - mode->hdisplay < 32)
7947                         return MODE_H_ILLEGAL;
7948
7949                 if (mode->vtotal - mode->vdisplay < 3)
7950                         return MODE_V_ILLEGAL;
7951         }
7952
7953         /*
7954          * Cantiga+ cannot handle modes with a hsync front porch of 0.
7955          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7956          */
7957         if ((DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) &&
7958             mode->hsync_start == mode->hdisplay)
7959                 return MODE_H_ILLEGAL;
7960
7961         return MODE_OK;
7962 }
7963
7964 enum drm_mode_status
7965 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
7966                                 const struct drm_display_mode *mode,
7967                                 bool bigjoiner)
7968 {
7969         int plane_width_max, plane_height_max;
7970
7971         /*
7972          * intel_mode_valid() should be
7973          * sufficient on older platforms.
7974          */
7975         if (DISPLAY_VER(dev_priv) < 9)
7976                 return MODE_OK;
7977
7978         /*
7979          * Most people will probably want a fullscreen
7980          * plane so let's not advertize modes that are
7981          * too big for that.
7982          */
7983         if (DISPLAY_VER(dev_priv) >= 11) {
7984                 plane_width_max = 5120 << bigjoiner;
7985                 plane_height_max = 4320;
7986         } else {
7987                 plane_width_max = 5120;
7988                 plane_height_max = 4096;
7989         }
7990
7991         if (mode->hdisplay > plane_width_max)
7992                 return MODE_H_ILLEGAL;
7993
7994         if (mode->vdisplay > plane_height_max)
7995                 return MODE_V_ILLEGAL;
7996
7997         return MODE_OK;
7998 }
7999
8000 static const struct intel_display_funcs skl_display_funcs = {
8001         .get_pipe_config = hsw_get_pipe_config,
8002         .crtc_enable = hsw_crtc_enable,
8003         .crtc_disable = hsw_crtc_disable,
8004         .commit_modeset_enables = skl_commit_modeset_enables,
8005         .get_initial_plane_config = skl_get_initial_plane_config,
8006         .fixup_initial_plane_config = skl_fixup_initial_plane_config,
8007 };
8008
8009 static const struct intel_display_funcs ddi_display_funcs = {
8010         .get_pipe_config = hsw_get_pipe_config,
8011         .crtc_enable = hsw_crtc_enable,
8012         .crtc_disable = hsw_crtc_disable,
8013         .commit_modeset_enables = intel_commit_modeset_enables,
8014         .get_initial_plane_config = i9xx_get_initial_plane_config,
8015         .fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8016 };
8017
8018 static const struct intel_display_funcs pch_split_display_funcs = {
8019         .get_pipe_config = ilk_get_pipe_config,
8020         .crtc_enable = ilk_crtc_enable,
8021         .crtc_disable = ilk_crtc_disable,
8022         .commit_modeset_enables = intel_commit_modeset_enables,
8023         .get_initial_plane_config = i9xx_get_initial_plane_config,
8024         .fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8025 };
8026
8027 static const struct intel_display_funcs vlv_display_funcs = {
8028         .get_pipe_config = i9xx_get_pipe_config,
8029         .crtc_enable = valleyview_crtc_enable,
8030         .crtc_disable = i9xx_crtc_disable,
8031         .commit_modeset_enables = intel_commit_modeset_enables,
8032         .get_initial_plane_config = i9xx_get_initial_plane_config,
8033         .fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8034 };
8035
8036 static const struct intel_display_funcs i9xx_display_funcs = {
8037         .get_pipe_config = i9xx_get_pipe_config,
8038         .crtc_enable = i9xx_crtc_enable,
8039         .crtc_disable = i9xx_crtc_disable,
8040         .commit_modeset_enables = intel_commit_modeset_enables,
8041         .get_initial_plane_config = i9xx_get_initial_plane_config,
8042         .fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8043 };
8044
8045 /**
8046  * intel_init_display_hooks - initialize the display modesetting hooks
8047  * @dev_priv: device private
8048  */
8049 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
8050 {
8051         if (DISPLAY_VER(dev_priv) >= 9) {
8052                 dev_priv->display.funcs.display = &skl_display_funcs;
8053         } else if (HAS_DDI(dev_priv)) {
8054                 dev_priv->display.funcs.display = &ddi_display_funcs;
8055         } else if (HAS_PCH_SPLIT(dev_priv)) {
8056                 dev_priv->display.funcs.display = &pch_split_display_funcs;
8057         } else if (IS_CHERRYVIEW(dev_priv) ||
8058                    IS_VALLEYVIEW(dev_priv)) {
8059                 dev_priv->display.funcs.display = &vlv_display_funcs;
8060         } else {
8061                 dev_priv->display.funcs.display = &i9xx_display_funcs;
8062         }
8063 }
8064
8065 int intel_initial_commit(struct drm_device *dev)
8066 {
8067         struct drm_atomic_state *state = NULL;
8068         struct drm_modeset_acquire_ctx ctx;
8069         struct intel_crtc *crtc;
8070         int ret = 0;
8071
8072         state = drm_atomic_state_alloc(dev);
8073         if (!state)
8074                 return -ENOMEM;
8075
8076         drm_modeset_acquire_init(&ctx, 0);
8077
8078         state->acquire_ctx = &ctx;
8079         to_intel_atomic_state(state)->internal = true;
8080
8081 retry:
8082         for_each_intel_crtc(dev, crtc) {
8083                 struct intel_crtc_state *crtc_state =
8084                         intel_atomic_get_crtc_state(state, crtc);
8085
8086                 if (IS_ERR(crtc_state)) {
8087                         ret = PTR_ERR(crtc_state);
8088                         goto out;
8089                 }
8090
8091                 if (crtc_state->hw.active) {
8092                         struct intel_encoder *encoder;
8093
8094                         ret = drm_atomic_add_affected_planes(state, &crtc->base);
8095                         if (ret)
8096                                 goto out;
8097
8098                         /*
8099                          * FIXME hack to force a LUT update to avoid the
8100                          * plane update forcing the pipe gamma on without
8101                          * having a proper LUT loaded. Remove once we
8102                          * have readout for pipe gamma enable.
8103                          */
8104                         crtc_state->uapi.color_mgmt_changed = true;
8105
8106                         for_each_intel_encoder_mask(dev, encoder,
8107                                                     crtc_state->uapi.encoder_mask) {
8108                                 if (encoder->initial_fastset_check &&
8109                                     !encoder->initial_fastset_check(encoder, crtc_state)) {
8110                                         ret = drm_atomic_add_affected_connectors(state,
8111                                                                                  &crtc->base);
8112                                         if (ret)
8113                                                 goto out;
8114                                 }
8115                         }
8116                 }
8117         }
8118
8119         ret = drm_atomic_commit(state);
8120
8121 out:
8122         if (ret == -EDEADLK) {
8123                 drm_atomic_state_clear(state);
8124                 drm_modeset_backoff(&ctx);
8125                 goto retry;
8126         }
8127
8128         drm_atomic_state_put(state);
8129
8130         drm_modeset_drop_locks(&ctx);
8131         drm_modeset_acquire_fini(&ctx);
8132
8133         return ret;
8134 }
8135
8136 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
8137 {
8138         struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8139         enum transcoder cpu_transcoder = (enum transcoder)pipe;
8140         /* 640x480@60Hz, ~25175 kHz */
8141         struct dpll clock = {
8142                 .m1 = 18,
8143                 .m2 = 7,
8144                 .p1 = 13,
8145                 .p2 = 4,
8146                 .n = 2,
8147         };
8148         u32 dpll, fp;
8149         int i;
8150
8151         drm_WARN_ON(&dev_priv->drm,
8152                     i9xx_calc_dpll_params(48000, &clock) != 25154);
8153
8154         drm_dbg_kms(&dev_priv->drm,
8155                     "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
8156                     pipe_name(pipe), clock.vco, clock.dot);
8157
8158         fp = i9xx_dpll_compute_fp(&clock);
8159         dpll = DPLL_DVO_2X_MODE |
8160                 DPLL_VGA_MODE_DIS |
8161                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
8162                 PLL_P2_DIVIDE_BY_4 |
8163                 PLL_REF_INPUT_DREFCLK |
8164                 DPLL_VCO_ENABLE;
8165
8166         intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
8167                        HACTIVE(640 - 1) | HTOTAL(800 - 1));
8168         intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
8169                        HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
8170         intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
8171                        HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
8172         intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
8173                        VACTIVE(480 - 1) | VTOTAL(525 - 1));
8174         intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
8175                        VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
8176         intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
8177                        VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
8178         intel_de_write(dev_priv, PIPESRC(pipe),
8179                        PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
8180
8181         intel_de_write(dev_priv, FP0(pipe), fp);
8182         intel_de_write(dev_priv, FP1(pipe), fp);
8183
8184         /*
8185          * Apparently we need to have VGA mode enabled prior to changing
8186          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
8187          * dividers, even though the register value does change.
8188          */
8189         intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
8190         intel_de_write(dev_priv, DPLL(pipe), dpll);
8191
8192         /* Wait for the clocks to stabilize. */
8193         intel_de_posting_read(dev_priv, DPLL(pipe));
8194         udelay(150);
8195
8196         /* The pixel multiplier can only be updated once the
8197          * DPLL is enabled and the clocks are stable.
8198          *
8199          * So write it again.
8200          */
8201         intel_de_write(dev_priv, DPLL(pipe), dpll);
8202
8203         /* We do this three times for luck */
8204         for (i = 0; i < 3 ; i++) {
8205                 intel_de_write(dev_priv, DPLL(pipe), dpll);
8206                 intel_de_posting_read(dev_priv, DPLL(pipe));
8207                 udelay(150); /* wait for warmup */
8208         }
8209
8210         intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE);
8211         intel_de_posting_read(dev_priv, TRANSCONF(pipe));
8212
8213         intel_wait_for_pipe_scanline_moving(crtc);
8214 }
8215
8216 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
8217 {
8218         struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8219
8220         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
8221                     pipe_name(pipe));
8222
8223         drm_WARN_ON(&dev_priv->drm,
8224                     intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE);
8225         drm_WARN_ON(&dev_priv->drm,
8226                     intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE);
8227         drm_WARN_ON(&dev_priv->drm,
8228                     intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE);
8229         drm_WARN_ON(&dev_priv->drm,
8230                     intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);
8231         drm_WARN_ON(&dev_priv->drm,
8232                     intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);
8233
8234         intel_de_write(dev_priv, TRANSCONF(pipe), 0);
8235         intel_de_posting_read(dev_priv, TRANSCONF(pipe));
8236
8237         intel_wait_for_pipe_scanline_stopped(crtc);
8238
8239         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
8240         intel_de_posting_read(dev_priv, DPLL(pipe));
8241 }
8242
8243 void intel_hpd_poll_fini(struct drm_i915_private *i915)
8244 {
8245         struct intel_connector *connector;
8246         struct drm_connector_list_iter conn_iter;
8247
8248         /* Kill all the work that may have been queued by hpd. */
8249         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
8250         for_each_intel_connector_iter(connector, &conn_iter) {
8251                 if (connector->modeset_retry_work.func &&
8252                     cancel_work_sync(&connector->modeset_retry_work))
8253                         drm_connector_put(&connector->base);
8254                 if (connector->hdcp.shim) {
8255                         cancel_delayed_work_sync(&connector->hdcp.check_work);
8256                         cancel_work_sync(&connector->hdcp.prop_work);
8257                 }
8258         }
8259         drm_connector_list_iter_end(&conn_iter);
8260 }
8261
8262 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915)
8263 {
8264         return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915);
8265 }