drivers/gpu/drm/i915/display/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <acpi/video.h>
  28 #include <linux/i2c.h>
  29 #include <linux/input.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/dma-resv.h>
  33 #include <linux/slab.h>
  34 #include <linux/string_helpers.h>
  35 #include <linux/vga_switcheroo.h>
  36
  37 #include <drm/display/drm_dp_helper.h>
  38 #include <drm/drm_atomic.h>
  39 #include <drm/drm_atomic_helper.h>
  40 #include <drm/drm_atomic_uapi.h>
  41 #include <drm/drm_damage_helper.h>
  42 #include <drm/drm_edid.h>
  43 #include <drm/drm_fourcc.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_privacy_screen_consumer.h>
  46 #include <drm/drm_probe_helper.h>
  47 #include <drm/drm_rect.h>
  48
  49 #include "display/intel_audio.h"
  50 #include "display/intel_crt.h"
  51 #include "display/intel_ddi.h"
  52 #include "display/intel_display_debugfs.h"
  53 #include "display/intel_display_power.h"
  54 #include "display/intel_dp.h"
  55 #include "display/intel_dp_mst.h"
  56 #include "display/intel_dpll.h"
  57 #include "display/intel_dpll_mgr.h"
  58 #include "display/intel_drrs.h"
  59 #include "display/intel_dsi.h"
  60 #include "display/intel_dvo.h"
  61 #include "display/intel_fb.h"
  62 #include "display/intel_gmbus.h"
  63 #include "display/intel_hdmi.h"
  64 #include "display/intel_lvds.h"
  65 #include "display/intel_sdvo.h"
  66 #include "display/intel_snps_phy.h"
  67 #include "display/intel_tv.h"
  68 #include "display/intel_vdsc.h"
  69 #include "display/intel_vrr.h"
  70
  71 #include "gem/i915_gem_lmem.h"
  72 #include "gem/i915_gem_object.h"
  73
  74 #include "gt/gen8_ppgtt.h"
  75
  76 #include "g4x_dp.h"
  77 #include "g4x_hdmi.h"
  78 #include "hsw_ips.h"
  79 #include "i915_drv.h"
  80 #include "i915_utils.h"
  81 #include "icl_dsi.h"
  82 #include "intel_acpi.h"
  83 #include "intel_atomic.h"
  84 #include "intel_atomic_plane.h"
  85 #include "intel_bw.h"
  86 #include "intel_cdclk.h"
  87 #include "intel_color.h"
  88 #include "intel_crtc.h"
  89 #include "intel_crtc_state_dump.h"
  90 #include "intel_de.h"
  91 #include "intel_display_types.h"
  92 #include "intel_dmc.h"
  93 #include "intel_dp_link_training.h"
  94 #include "intel_dpt.h"
  95 #include "intel_fbc.h"
  96 #include "intel_fbdev.h"
  97 #include "intel_fdi.h"
  98 #include "intel_fifo_underrun.h"
  99 #include "intel_frontbuffer.h"
 100 #include "intel_hdcp.h"
 101 #include "intel_hotplug.h"
 102 #include "intel_modeset_verify.h"
 103 #include "intel_modeset_setup.h"
 104 #include "intel_overlay.h"
 105 #include "intel_panel.h"
 106 #include "intel_pch_display.h"
 107 #include "intel_pch_refclk.h"
 108 #include "intel_pcode.h"
 109 #include "intel_pipe_crc.h"
 110 #include "intel_plane_initial.h"
 111 #include "intel_pm.h"
 112 #include "intel_pps.h"
 113 #include "intel_psr.h"
 114 #include "intel_quirks.h"
 115 #include "intel_sprite.h"
 116 #include "intel_tc.h"
 117 #include "intel_vga.h"
 118 #include "i9xx_plane.h"
 119 #include "skl_scaler.h"
 120 #include "skl_universal_plane.h"
 121 #include "vlv_dsi.h"
 122 #include "vlv_dsi_pll.h"
 123 #include "vlv_dsi_regs.h"
 124 #include "vlv_sideband.h"
 125
 126 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 127 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 128 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
 129 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
 130 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
 131
 132 /**
 133  * intel_update_watermarks - update FIFO watermark values based on current modes
 134  * @dev_priv: i915 device
 135  *
 136  * Calculate watermark values for the various WM regs based on current mode
 137  * and plane configuration.
 138  *
 139  * There are several cases to deal with here:
 140  *   - normal (i.e. non-self-refresh)
 141  *   - self-refresh (SR) mode
 142  *   - lines are large relative to FIFO size (buffer can hold up to 2)
 143  *   - lines are small relative to FIFO size (buffer can hold more than 2
 144  *     lines), so need to account for TLB latency
 145  *
 146  *   The normal calculation is:
 147  *     watermark = dotclock * bytes per pixel * latency
 148  *   where latency is platform & configuration dependent (we assume pessimal
 149  *   values here).
 150  *
 151  *   The SR calculation is:
 152  *     watermark = (trunc(latency/line time)+1) * surface width *
 153  *       bytes per pixel
 154  *   where
 155  *     line time = htotal / dotclock
 156  *     surface width = hdisplay for normal plane and 64 for cursor
 157  *   and latency is assumed to be high, as above.
 158  *
 159  * The final value programmed to the register should always be rounded up,
 160  * and include an extra 2 entries to account for clock crossings.
 161  *
 162  * We don't use the sprite, so we can ignore that.  And on Crestline we have
 163  * to set the non-SR watermarks to 8.
 164  */
 165 void intel_update_watermarks(struct drm_i915_private *dev_priv)
 166 {
 167         if (dev_priv->wm_disp->update_wm)
 168                 dev_priv->wm_disp->update_wm(dev_priv);
 169 }
 170
 171 static int intel_compute_pipe_wm(struct intel_atomic_state *state,
 172                                  struct intel_crtc *crtc)
 173 {
 174         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 175         if (dev_priv->wm_disp->compute_pipe_wm)
 176                 return dev_priv->wm_disp->compute_pipe_wm(state, crtc);
 177         return 0;
 178 }
 179
 180 static int intel_compute_intermediate_wm(struct intel_atomic_state *state,
 181                                          struct intel_crtc *crtc)
 182 {
 183         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 184         if (!dev_priv->wm_disp->compute_intermediate_wm)
 185                 return 0;
 186         if (drm_WARN_ON(&dev_priv->drm,
 187                         !dev_priv->wm_disp->compute_pipe_wm))
 188                 return 0;
 189         return dev_priv->wm_disp->compute_intermediate_wm(state, crtc);
 190 }
 191
 192 static bool intel_initial_watermarks(struct intel_atomic_state *state,
 193                                      struct intel_crtc *crtc)
 194 {
 195         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 196         if (dev_priv->wm_disp->initial_watermarks) {
 197                 dev_priv->wm_disp->initial_watermarks(state, crtc);
 198                 return true;
 199         }
 200         return false;
 201 }
 202
 203 static void intel_atomic_update_watermarks(struct intel_atomic_state *state,
 204                                            struct intel_crtc *crtc)
 205 {
 206         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 207         if (dev_priv->wm_disp->atomic_update_watermarks)
 208                 dev_priv->wm_disp->atomic_update_watermarks(state, crtc);
 209 }
 210
 211 static void intel_optimize_watermarks(struct intel_atomic_state *state,
 212                                       struct intel_crtc *crtc)
 213 {
 214         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 215         if (dev_priv->wm_disp->optimize_watermarks)
 216                 dev_priv->wm_disp->optimize_watermarks(state, crtc);
 217 }
 218
 219 static int intel_compute_global_watermarks(struct intel_atomic_state *state)
 220 {
 221         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 222         if (dev_priv->wm_disp->compute_global_watermarks)
 223                 return dev_priv->wm_disp->compute_global_watermarks(state);
 224         return 0;
 225 }
 226
 227 /* returns HPLL frequency in kHz */
 228 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 229 {
 230         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 231
 232         /* Obtain SKU information */
 233         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 234                 CCK_FUSE_HPLL_FREQ_MASK;
 235
 236         return vco_freq[hpll_freq] * 1000;
 237 }
 238
 239 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 240                       const char *name, u32 reg, int ref_freq)
 241 {
 242         u32 val;
 243         int divider;
 244
 245         val = vlv_cck_read(dev_priv, reg);
 246         divider = val & CCK_FREQUENCY_VALUES;
 247
 248         drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
 249                  (divider << CCK_FREQUENCY_STATUS_SHIFT),
 250                  "%s change in progress\n", name);
 251
 252         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 253 }
 254
 255 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 256                            const char *name, u32 reg)
 257 {
 258         int hpll;
 259
 260         vlv_cck_get(dev_priv);
 261
 262         if (dev_priv->hpll_freq == 0)
 263                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 264
 265         hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
 266
 267         vlv_cck_put(dev_priv);
 268
 269         return hpll;
 270 }
 271
 272 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 273 {
 274         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 275                 return;
 276
 277         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 278                                                       CCK_CZ_CLOCK_CONTROL);
 279
 280         drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
 281                 dev_priv->czclk_freq);
 282 }
 283
 284 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
 285 {
 286         return (crtc_state->active_planes &
 287                 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0;
 288 }
 289
 290 /* WA Display #0827: Gen9:all */
 291 static void
 292 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
 293 {
 294         if (enable)
 295                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 296                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 297         else
 298                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 299                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
 300 }
 301
 302 /* Wa_2006604312:icl,ehl */
 303 static void
 304 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 305                        bool enable)
 306 {
 307         if (enable)
 308                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 309                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
 310         else
 311                 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe),
 312                                intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
 313 }
 314
 315 /* Wa_1604331009:icl,jsl,ehl */
 316 static void
 317 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 318                        bool enable)
 319 {
 320         intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS,
 321                      enable ? CURSOR_GATING_DIS : 0);
 322 }
 323
 324 static bool
 325 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
 326 {
 327         return crtc_state->master_transcoder != INVALID_TRANSCODER;
 328 }
 329
 330 static bool
 331 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
 332 {
 333         return crtc_state->sync_mode_slaves_mask != 0;
 334 }
 335
 336 bool
 337 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 338 {
 339         return is_trans_port_sync_master(crtc_state) ||
 340                 is_trans_port_sync_slave(crtc_state);
 341 }
 342
 343 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state)
 344 {
 345         return ffs(crtc_state->bigjoiner_pipes) - 1;
 346 }
 347
 348 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state)
 349 {
 350         if (crtc_state->bigjoiner_pipes)
 351                 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state));
 352         else
 353                 return 0;
 354 }
 355
 356 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state)
 357 {
 358         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 359
 360         return crtc_state->bigjoiner_pipes &&
 361                 crtc->pipe != bigjoiner_master_pipe(crtc_state);
 362 }
 363
 364 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state)
 365 {
 366         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 367
 368         return crtc_state->bigjoiner_pipes &&
 369                 crtc->pipe == bigjoiner_master_pipe(crtc_state);
 370 }
 371
 372 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state)
 373 {
 374         return hweight8(crtc_state->bigjoiner_pipes);
 375 }
 376
 377 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state)
 378 {
 379         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 380
 381         if (intel_crtc_is_bigjoiner_slave(crtc_state))
 382                 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state));
 383         else
 384                 return to_intel_crtc(crtc_state->uapi.crtc);
 385 }
 386
 387 static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
 388                                     enum pipe pipe)
 389 {
 390         i915_reg_t reg = PIPEDSL(pipe);
 391         u32 line1, line2;
 392
 393         line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
 394         msleep(5);
 395         line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
 396
 397         return line1 != line2;
 398 }
 399
 400 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
 401 {
 402         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 403         enum pipe pipe = crtc->pipe;
 404
 405         /* Wait for the display line to settle/start moving */
 406         if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))
 407                 drm_err(&dev_priv->drm,
 408                         "pipe %c scanline %s wait timed out\n",
 409                         pipe_name(pipe), str_on_off(state));
 410 }
 411
 412 static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
 413 {
 414         wait_for_pipe_scanline_moving(crtc, false);
 415 }
 416
 417 static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
 418 {
 419         wait_for_pipe_scanline_moving(crtc, true);
 420 }
 421
 422 static void
 423 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
 424 {
 425         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 426         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 427
 428         if (DISPLAY_VER(dev_priv) >= 4) {
 429                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 430
 431                 /* Wait for the Pipe State to go off */
 432                 if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder),
 433                                             PIPECONF_STATE_ENABLE, 100))
 434                         drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
 435         } else {
 436                 intel_wait_for_pipe_scanline_stopped(crtc);
 437         }
 438 }
 439
 440 void assert_transcoder(struct drm_i915_private *dev_priv,
 441                        enum transcoder cpu_transcoder, bool state)
 442 {
 443         bool cur_state;
 444         enum intel_display_power_domain power_domain;
 445         intel_wakeref_t wakeref;
 446
 447         /* we keep both pipes enabled on 830 */
 448         if (IS_I830(dev_priv))
 449                 state = true;
 450
 451         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 452         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
 453         if (wakeref) {
 454                 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
 455                 cur_state = !!(val & PIPECONF_ENABLE);
 456
 457                 intel_display_power_put(dev_priv, power_domain, wakeref);
 458         } else {
 459                 cur_state = false;
 460         }
 461
 462         I915_STATE_WARN(cur_state != state,
 463                         "transcoder %s assertion failure (expected %s, current %s)\n",
 464                         transcoder_name(cpu_transcoder),
 465                         str_on_off(state), str_on_off(cur_state));
 466 }
 467
 468 static void assert_plane(struct intel_plane *plane, bool state)
 469 {
 470         enum pipe pipe;
 471         bool cur_state;
 472
 473         cur_state = plane->get_hw_state(plane, &pipe);
 474
 475         I915_STATE_WARN(cur_state != state,
 476                         "%s assertion failure (expected %s, current %s)\n",
 477                         plane->base.name, str_on_off(state),
 478                         str_on_off(cur_state));
 479 }
 480
 481 #define assert_plane_enabled(p) assert_plane(p, true)
 482 #define assert_plane_disabled(p) assert_plane(p, false)
 483
 484 static void assert_planes_disabled(struct intel_crtc *crtc)
 485 {
 486         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 487         struct intel_plane *plane;
 488
 489         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
 490                 assert_plane_disabled(plane);
 491 }
 492
 493 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 494                          struct intel_digital_port *dig_port,
 495                          unsigned int expected_mask)
 496 {
 497         u32 port_mask;
 498         i915_reg_t dpll_reg;
 499
 500         switch (dig_port->base.port) {
 501         default:
 502                 MISSING_CASE(dig_port->base.port);
 503                 fallthrough;
 504         case PORT_B:
 505                 port_mask = DPLL_PORTB_READY_MASK;
 506                 dpll_reg = DPLL(0);
 507                 break;
 508         case PORT_C:
 509                 port_mask = DPLL_PORTC_READY_MASK;
 510                 dpll_reg = DPLL(0);
 511                 expected_mask <<= 4;
 512                 break;
 513         case PORT_D:
 514                 port_mask = DPLL_PORTD_READY_MASK;
 515                 dpll_reg = DPIO_PHY_STATUS;
 516                 break;
 517         }
 518
 519         if (intel_de_wait_for_register(dev_priv, dpll_reg,
 520                                        port_mask, expected_mask, 1000))
 521                 drm_WARN(&dev_priv->drm, 1,
 522                          "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
 523                          dig_port->base.base.base.id, dig_port->base.base.name,
 524                          intel_de_read(dev_priv, dpll_reg) & port_mask,
 525                          expected_mask);
 526 }
 527
 528 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
 529 {
 530         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 531         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 532         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 533         enum pipe pipe = crtc->pipe;
 534         i915_reg_t reg;
 535         u32 val;
 536
 537         drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
 538
 539         assert_planes_disabled(crtc);
 540
 541         /*
 542          * A pipe without a PLL won't actually be able to drive bits from
 543          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
 544          * need the check.
 545          */
 546         if (HAS_GMCH(dev_priv)) {
 547                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
 548                         assert_dsi_pll_enabled(dev_priv);
 549                 else
 550                         assert_pll_enabled(dev_priv, pipe);
 551         } else {
 552                 if (new_crtc_state->has_pch_encoder) {
 553                         /* if driving the PCH, we need FDI enabled */
 554                         assert_fdi_rx_pll_enabled(dev_priv,
 555                                                   intel_crtc_pch_transcoder(crtc));
 556                         assert_fdi_tx_pll_enabled(dev_priv,
 557                                                   (enum pipe) cpu_transcoder);
 558                 }
 559                 /* FIXME: assert CPU port conditions for SNB+ */
 560         }
 561
 562         /* Wa_22012358565:adl-p */
 563         if (DISPLAY_VER(dev_priv) == 13)
 564                 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
 565                              0, PIPE_ARB_USE_PROG_SLOTS);
 566
 567         reg = PIPECONF(cpu_transcoder);
 568         val = intel_de_read(dev_priv, reg);
 569         if (val & PIPECONF_ENABLE) {
 570                 /* we keep both pipes enabled on 830 */
 571                 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
 572                 return;
 573         }
 574
 575         intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
 576         intel_de_posting_read(dev_priv, reg);
 577
 578         /*
 579          * Until the pipe starts PIPEDSL reads will return a stale value,
 580          * which causes an apparent vblank timestamp jump when PIPEDSL
 581          * resets to its proper value. That also messes up the frame count
 582          * when it's derived from the timestamps. So let's wait for the
 583          * pipe to start properly before we call drm_crtc_vblank_on()
 584          */
 585         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
 586                 intel_wait_for_pipe_scanline_moving(crtc);
 587 }
 588
 589 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
 590 {
 591         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 592         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 593         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 594         enum pipe pipe = crtc->pipe;
 595         i915_reg_t reg;
 596         u32 val;
 597
 598         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
 599
 600         /*
 601          * Make sure planes won't keep trying to pump pixels to us,
 602          * or we might hang the display.
 603          */
 604         assert_planes_disabled(crtc);
 605
 606         reg = PIPECONF(cpu_transcoder);
 607         val = intel_de_read(dev_priv, reg);
 608         if ((val & PIPECONF_ENABLE) == 0)
 609                 return;
 610
 611         /*
 612          * Double wide has implications for planes
 613          * so best keep it disabled when not needed.
 614          */
 615         if (old_crtc_state->double_wide)
 616                 val &= ~PIPECONF_DOUBLE_WIDE;
 617
 618         /* Don't disable pipe or pipe PLLs if needed */
 619         if (!IS_I830(dev_priv))
 620                 val &= ~PIPECONF_ENABLE;
 621
 622         if (DISPLAY_VER(dev_priv) >= 12)
 623                 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
 624                              FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
 625
 626         intel_de_write(dev_priv, reg, val);
 627         if ((val & PIPECONF_ENABLE) == 0)
 628                 intel_wait_for_pipe_off(old_crtc_state);
 629 }
 630
 631 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
 632 {
 633         unsigned int size = 0;
 634         int i;
 635
 636         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
 637                 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;
 638
 639         return size;
 640 }
 641
 642 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
 643 {
 644         unsigned int size = 0;
 645         int i;
 646
 647         for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
 648                 unsigned int plane_size;
 649
 650                 if (rem_info->plane[i].linear)
 651                         plane_size = rem_info->plane[i].size;
 652                 else
 653                         plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height;
 654
 655                 if (plane_size == 0)
 656                         continue;
 657
 658                 if (rem_info->plane_alignment)
 659                         size = ALIGN(size, rem_info->plane_alignment);
 660
 661                 size += plane_size;
 662         }
 663
 664         return size;
 665 }
 666
 667 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
 668 {
 669         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 670         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 671
 672         return DISPLAY_VER(dev_priv) < 4 ||
 673                 (plane->fbc &&
 674                  plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL);
 675 }
 676
 677 /*
 678  * Convert the x/y offsets into a linear offset.
 679  * Only valid with 0/180 degree rotation, which is fine since linear
 680  * offset is only used with linear buffers on pre-hsw and tiled buffers
 681  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
 682  */
 683 u32 intel_fb_xy_to_linear(int x, int y,
 684                           const struct intel_plane_state *state,
 685                           int color_plane)
 686 {
 687         const struct drm_framebuffer *fb = state->hw.fb;
 688         unsigned int cpp = fb->format->cpp[color_plane];
 689         unsigned int pitch = state->view.color_plane[color_plane].mapping_stride;
 690
 691         return y * pitch + x * cpp;
 692 }
 693
 694 /*
 695  * Add the x/y offsets derived from fb->offsets[] to the user
 696  * specified plane src x/y offsets. The resulting x/y offsets
 697  * specify the start of scanout from the beginning of the gtt mapping.
 698  */
 699 void intel_add_fb_offsets(int *x, int *y,
 700                           const struct intel_plane_state *state,
 701                           int color_plane)
 702
 703 {
 704         *x += state->view.color_plane[color_plane].x;
 705         *y += state->view.color_plane[color_plane].y;
 706 }
 707
 708 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 709                               u32 pixel_format, u64 modifier)
 710 {
 711         struct intel_crtc *crtc;
 712         struct intel_plane *plane;
 713
 714         if (!HAS_DISPLAY(dev_priv))
 715                 return 0;
 716
 717         /*
 718          * We assume the primary plane for pipe A has
 719          * the highest stride limits of them all,
 720          * if in case pipe A is disabled, use the first pipe from pipe_mask.
 721          */
 722         crtc = intel_first_crtc(dev_priv);
 723         if (!crtc)
 724                 return 0;
 725
 726         plane = to_intel_plane(crtc->base.primary);
 727
 728         return plane->max_stride(plane, pixel_format, modifier,
 729                                  DRM_MODE_ROTATE_0);
 730 }
 731
 732 void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
 733                              struct intel_plane_state *plane_state,
 734                              bool visible)
 735 {
 736         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 737
 738         plane_state->uapi.visible = visible;
 739
 740         if (visible)
 741                 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
 742         else
 743                 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
 744 }
 745
 746 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
 747 {
 748         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 749         struct drm_plane *plane;
 750
 751         /*
 752          * Active_planes aliases if multiple "primary" or cursor planes
 753          * have been used on the same (or wrong) pipe. plane_mask uses
 754          * unique ids, hence we can use that to reconstruct active_planes.
 755          */
 756         crtc_state->enabled_planes = 0;
 757         crtc_state->active_planes = 0;
 758
 759         drm_for_each_plane_mask(plane, &dev_priv->drm,
 760                                 crtc_state->uapi.plane_mask) {
 761                 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
 762                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
 763         }
 764 }
 765
 766 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 767                                   struct intel_plane *plane)
 768 {
 769         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 770         struct intel_crtc_state *crtc_state =
 771                 to_intel_crtc_state(crtc->base.state);
 772         struct intel_plane_state *plane_state =
 773                 to_intel_plane_state(plane->base.state);
 774
 775         drm_dbg_kms(&dev_priv->drm,
 776                     "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
 777                     plane->base.base.id, plane->base.name,
 778                     crtc->base.base.id, crtc->base.name);
 779
 780         intel_set_plane_visible(crtc_state, plane_state, false);
 781         intel_plane_fixup_bitmasks(crtc_state);
 782         crtc_state->data_rate[plane->id] = 0;
 783         crtc_state->data_rate_y[plane->id] = 0;
 784         crtc_state->rel_data_rate[plane->id] = 0;
 785         crtc_state->rel_data_rate_y[plane->id] = 0;
 786         crtc_state->min_cdclk[plane->id] = 0;
 787
 788         if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
 789             hsw_ips_disable(crtc_state)) {
 790                 crtc_state->ips_enabled = false;
 791                 intel_crtc_wait_for_next_vblank(crtc);
 792         }
 793
 794         /*
 795          * Vblank time updates from the shadow to live plane control register
 796          * are blocked if the memory self-refresh mode is active at that
 797          * moment. So to make sure the plane gets truly disabled, disable
 798          * first the self-refresh mode. The self-refresh enable bit in turn
 799          * will be checked/applied by the HW only at the next frame start
 800          * event which is after the vblank start event, so we need to have a
 801          * wait-for-vblank between disabling the plane and the pipe.
 802          */
 803         if (HAS_GMCH(dev_priv) &&
 804             intel_set_memory_cxsr(dev_priv, false))
 805                 intel_crtc_wait_for_next_vblank(crtc);
 806
 807         /*
 808          * Gen2 reports pipe underruns whenever all planes are disabled.
 809          * So disable underrun reporting before all the planes get disabled.
 810          */
 811         if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
 812                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
 813
 814         intel_plane_disable_arm(plane, crtc_state);
 815         intel_crtc_wait_for_next_vblank(crtc);
 816 }
 817
 818 unsigned int
 819 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
 820 {
 821         int x = 0, y = 0;
 822
 823         intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
 824                                           plane_state->view.color_plane[0].offset, 0);
 825
 826         return y;
 827 }
 828
 829 static int
 830 __intel_display_resume(struct drm_i915_private *i915,
 831                        struct drm_atomic_state *state,
 832                        struct drm_modeset_acquire_ctx *ctx)
 833 {
 834         struct drm_crtc_state *crtc_state;
 835         struct drm_crtc *crtc;
 836         int i, ret;
 837
 838         intel_modeset_setup_hw_state(i915, ctx);
 839         intel_vga_redisable(i915);
 840
 841         if (!state)
 842                 return 0;
 843
 844         /*
 845          * We've duplicated the state, pointers to the old state are invalid.
 846          *
 847          * Don't attempt to use the old state until we commit the duplicated state.
 848          */
 849         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 850                 /*
 851                  * Force recalculation even if we restore
 852                  * current state. With fast modeset this may not result
 853                  * in a modeset when the state is compatible.
 854                  */
 855                 crtc_state->mode_changed = true;
 856         }
 857
 858         /* ignore any reset values/BIOS leftovers in the WM registers */
 859         if (!HAS_GMCH(i915))
 860                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
 861
 862         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
 863
 864         drm_WARN_ON(&i915->drm, ret == -EDEADLK);
 865
 866         return ret;
 867 }
 868
 869 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
 870 {
 871         return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display &&
 872                 intel_has_gpu_reset(to_gt(dev_priv)));
 873 }
 874
 875 void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
 876 {
 877         struct drm_device *dev = &dev_priv->drm;
 878         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
 879         struct drm_atomic_state *state;
 880         int ret;
 881
 882         if (!HAS_DISPLAY(dev_priv))
 883                 return;
 884
 885         /* reset doesn't touch the display */
 886         if (!dev_priv->params.force_reset_modeset_test &&
 887             !gpu_reset_clobbers_display(dev_priv))
 888                 return;
 889
 890         /* We have a modeset vs reset deadlock, defensively unbreak it. */
 891         set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags);
 892         smp_mb__after_atomic();
 893         wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET);
 894
 895         if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
 896                 drm_dbg_kms(&dev_priv->drm,
 897                             "Modeset potentially stuck, unbreaking through wedging\n");
 898                 intel_gt_set_wedged(to_gt(dev_priv));
 899         }
 900
 901         /*
 902          * Need mode_config.mutex so that we don't
 903          * trample ongoing ->detect() and whatnot.
 904          */
 905         mutex_lock(&dev->mode_config.mutex);
 906         drm_modeset_acquire_init(ctx, 0);
 907         while (1) {
 908                 ret = drm_modeset_lock_all_ctx(dev, ctx);
 909                 if (ret != -EDEADLK)
 910                         break;
 911
 912                 drm_modeset_backoff(ctx);
 913         }
 914         /*
 915          * Disabling the crtcs gracefully seems nicer. Also the
 916          * g33 docs say we should at least disable all the planes.
 917          */
 918         state = drm_atomic_helper_duplicate_state(dev, ctx);
 919         if (IS_ERR(state)) {
 920                 ret = PTR_ERR(state);
 921                 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",
 922                         ret);
 923                 return;
 924         }
 925
 926         ret = drm_atomic_helper_disable_all(dev, ctx);
 927         if (ret) {
 928                 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
 929                         ret);
 930                 drm_atomic_state_put(state);
 931                 return;
 932         }
 933
 934         dev_priv->modeset_restore_state = state;
 935         state->acquire_ctx = ctx;
 936 }
 937
 938 void intel_display_finish_reset(struct drm_i915_private *i915)
 939 {
 940         struct drm_modeset_acquire_ctx *ctx = &i915->reset_ctx;
 941         struct drm_atomic_state *state;
 942         int ret;
 943
 944         if (!HAS_DISPLAY(i915))
 945                 return;
 946
 947         /* reset doesn't touch the display */
 948         if (!test_bit(I915_RESET_MODESET, &to_gt(i915)->reset.flags))
 949                 return;
 950
 951         state = fetch_and_zero(&i915->modeset_restore_state);
 952         if (!state)
 953                 goto unlock;
 954
 955         /* reset doesn't touch the display */
 956         if (!gpu_reset_clobbers_display(i915)) {
 957                 /* for testing only restore the display */
 958                 ret = __intel_display_resume(i915, state, ctx);
 959                 if (ret)
 960                         drm_err(&i915->drm,
 961                                 "Restoring old state failed with %i\n", ret);
 962         } else {
 963                 /*
 964                  * The display has been reset as well,
 965                  * so need a full re-initialization.
 966                  */
 967                 intel_pps_unlock_regs_wa(i915);
 968                 intel_modeset_init_hw(i915);
 969                 intel_init_clock_gating(i915);
 970                 intel_hpd_init(i915);
 971
 972                 ret = __intel_display_resume(i915, state, ctx);
 973                 if (ret)
 974                         drm_err(&i915->drm,
 975                                 "Restoring old state failed with %i\n", ret);
 976
 977                 intel_hpd_poll_disable(i915);
 978         }
 979
 980         drm_atomic_state_put(state);
 981 unlock:
 982         drm_modeset_drop_locks(ctx);
 983         drm_modeset_acquire_fini(ctx);
 984         mutex_unlock(&i915->drm.mode_config.mutex);
 985
 986         clear_bit_unlock(I915_RESET_MODESET, &to_gt(i915)->reset.flags);
 987 }
 988
 989 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
 990 {
 991         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 992         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 993         enum pipe pipe = crtc->pipe;
 994         u32 tmp;
 995
 996         tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
 997
 998         /*
 999          * Display WA #1153: icl
1000          * enable hardware to bypass the alpha math
1001          * and rounding for per-pixel values 00 and 0xff
1002          */
1003         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
1004         /*
1005          * Display WA # 1605353570: icl
1006          * Set the pixel rounding bit to 1 for allowing
1007          * passthrough of Frame buffer pixels unmodified
1008          * across pipe
1009          */
1010         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
1011
1012         /*
1013          * Underrun recovery must always be disabled on display 13+.
1014          * DG2 chicken bit meaning is inverted compared to other platforms.
1015          */
1016         if (IS_DG2(dev_priv))
1017                 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
1018         else if (DISPLAY_VER(dev_priv) >= 13)
1019                 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
1020
1021         /* Wa_14010547955:dg2 */
1022         if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER))
1023                 tmp |= DG2_RENDER_CCSTAG_4_3_EN;
1024
1025         intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
1026 }
1027
1028 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
1029 {
1030         struct drm_crtc *crtc;
1031         bool cleanup_done;
1032
1033         drm_for_each_crtc(crtc, &dev_priv->drm) {
1034                 struct drm_crtc_commit *commit;
1035                 spin_lock(&crtc->commit_lock);
1036                 commit = list_first_entry_or_null(&crtc->commit_list,
1037                                                   struct drm_crtc_commit, commit_entry);
1038                 cleanup_done = commit ?
1039                         try_wait_for_completion(&commit->cleanup_done) : true;
1040                 spin_unlock(&crtc->commit_lock);
1041
1042                 if (cleanup_done)
1043                         continue;
1044
1045                 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc));
1046
1047                 return true;
1048         }
1049
1050         return false;
1051 }
1052
1053 /*
1054  * Finds the encoder associated with the given CRTC. This can only be
1055  * used when we know that the CRTC isn't feeding multiple encoders!
1056  */
1057 struct intel_encoder *
1058 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
1059                            const struct intel_crtc_state *crtc_state)
1060 {
1061         const struct drm_connector_state *connector_state;
1062         const struct drm_connector *connector;
1063         struct intel_encoder *encoder = NULL;
1064         struct intel_crtc *master_crtc;
1065         int num_encoders = 0;
1066         int i;
1067
1068         master_crtc = intel_master_crtc(crtc_state);
1069
1070         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
1071                 if (connector_state->crtc != &master_crtc->base)
1072                         continue;
1073
1074                 encoder = to_intel_encoder(connector_state->best_encoder);
1075                 num_encoders++;
1076         }
1077
1078         drm_WARN(encoder->base.dev, num_encoders != 1,
1079                  "%d encoders for pipe %c\n",
1080                  num_encoders, pipe_name(master_crtc->pipe));
1081
1082         return encoder;
1083 }
1084
1085 static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
1086                                enum pipe pipe)
1087 {
1088         i915_reg_t dslreg = PIPEDSL(pipe);
1089         u32 temp;
1090
1091         temp = intel_de_read(dev_priv, dslreg);
1092         udelay(500);
1093         if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) {
1094                 if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5))
1095                         drm_err(&dev_priv->drm,
1096                                 "mode set failed: pipe %c stuck\n",
1097                                 pipe_name(pipe));
1098         }
1099 }
1100
1101 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
1102 {
1103         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1104         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1105         const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
1106         enum pipe pipe = crtc->pipe;
1107         int width = drm_rect_width(dst);
1108         int height = drm_rect_height(dst);
1109         int x = dst->x1;
1110         int y = dst->y1;
1111
1112         if (!crtc_state->pch_pfit.enabled)
1113                 return;
1114
1115         /* Force use of hard-coded filter coefficients
1116          * as some pre-programmed values are broken,
1117          * e.g. x201.
1118          */
1119         if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
1120                 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
1121                                   PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
1122         else
1123                 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
1124                                   PF_FILTER_MED_3x3);
1125         intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
1126         intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
1127 }
1128
1129 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
1130 {
1131         if (crtc->overlay)
1132                 (void) intel_overlay_switch_off(crtc->overlay);
1133
1134         /* Let userspace switch the overlay on again. In most cases userspace
1135          * has to recompute where to put it anyway.
1136          */
1137 }
1138
1139 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
1140 {
1141         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1142
1143         if (!crtc_state->nv12_planes)
1144                 return false;
1145
1146         /* WA Display #0827: Gen9:all */
1147         if (DISPLAY_VER(dev_priv) == 9)
1148                 return true;
1149
1150         return false;
1151 }
1152
1153 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
1154 {
1155         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1156
1157         /* Wa_2006604312:icl,ehl */
1158         if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
1159                 return true;
1160
1161         return false;
1162 }
1163
1164 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
1165 {
1166         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1167
1168         /* Wa_1604331009:icl,jsl,ehl */
1169         if (is_hdr_mode(crtc_state) &&
1170             crtc_state->active_planes & BIT(PLANE_CURSOR) &&
1171             DISPLAY_VER(dev_priv) == 11)
1172                 return true;
1173
1174         return false;
1175 }
1176
1177 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915,
1178                                     enum pipe pipe, bool enable)
1179 {
1180         if (DISPLAY_VER(i915) == 9) {
1181                 /*
1182                  * "Plane N strech max must be programmed to 11b (x1)
1183                  *  when Async flips are enabled on that plane."
1184                  */
1185                 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
1186                              SKL_PLANE1_STRETCH_MAX_MASK,
1187                              enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8);
1188         } else {
1189                 /* Also needed on HSW/BDW albeit undocumented */
1190                 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
1191                              HSW_PRI_STRETCH_MAX_MASK,
1192                              enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8);
1193         }
1194 }
1195
1196 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state)
1197 {
1198         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1199
1200         return crtc_state->uapi.async_flip && i915_vtd_active(i915) &&
1201                 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915));
1202 }
1203
1204 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
1205                             const struct intel_crtc_state *new_crtc_state)
1206 {
1207         return (!old_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state)) &&
1208                 new_crtc_state->active_planes;
1209 }
1210
1211 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
1212                              const struct intel_crtc_state *new_crtc_state)
1213 {
1214         return old_crtc_state->active_planes &&
1215                 (!new_crtc_state->active_planes || intel_crtc_needs_modeset(new_crtc_state));
1216 }
1217
1218 static void intel_post_plane_update(struct intel_atomic_state *state,
1219                                     struct intel_crtc *crtc)
1220 {
1221         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1222         const struct intel_crtc_state *old_crtc_state =
1223                 intel_atomic_get_old_crtc_state(state, crtc);
1224         const struct intel_crtc_state *new_crtc_state =
1225                 intel_atomic_get_new_crtc_state(state, crtc);
1226         enum pipe pipe = crtc->pipe;
1227
1228         intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
1229
1230         if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
1231                 intel_update_watermarks(dev_priv);
1232
1233         hsw_ips_post_update(state, crtc);
1234         intel_fbc_post_update(state, crtc);
1235
1236         if (needs_async_flip_vtd_wa(old_crtc_state) &&
1237             !needs_async_flip_vtd_wa(new_crtc_state))
1238                 intel_async_flip_vtd_wa(dev_priv, pipe, false);
1239
1240         if (needs_nv12_wa(old_crtc_state) &&
1241             !needs_nv12_wa(new_crtc_state))
1242                 skl_wa_827(dev_priv, pipe, false);
1243
1244         if (needs_scalerclk_wa(old_crtc_state) &&
1245             !needs_scalerclk_wa(new_crtc_state))
1246                 icl_wa_scalerclkgating(dev_priv, pipe, false);
1247
1248         if (needs_cursorclk_wa(old_crtc_state) &&
1249             !needs_cursorclk_wa(new_crtc_state))
1250                 icl_wa_cursorclkgating(dev_priv, pipe, false);
1251
1252         intel_drrs_activate(new_crtc_state);
1253 }
1254
1255 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
1256                                         struct intel_crtc *crtc)
1257 {
1258         const struct intel_crtc_state *crtc_state =
1259                 intel_atomic_get_new_crtc_state(state, crtc);
1260         u8 update_planes = crtc_state->update_planes;
1261         const struct intel_plane_state *plane_state;
1262         struct intel_plane *plane;
1263         int i;
1264
1265         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1266                 if (plane->pipe == crtc->pipe &&
1267                     update_planes & BIT(plane->id))
1268                         plane->enable_flip_done(plane);
1269         }
1270 }
1271
1272 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
1273                                          struct intel_crtc *crtc)
1274 {
1275         const struct intel_crtc_state *crtc_state =
1276                 intel_atomic_get_new_crtc_state(state, crtc);
1277         u8 update_planes = crtc_state->update_planes;
1278         const struct intel_plane_state *plane_state;
1279         struct intel_plane *plane;
1280         int i;
1281
1282         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1283                 if (plane->pipe == crtc->pipe &&
1284                     update_planes & BIT(plane->id))
1285                         plane->disable_flip_done(plane);
1286         }
1287 }
1288
1289 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
1290                                              struct intel_crtc *crtc)
1291 {
1292         const struct intel_crtc_state *old_crtc_state =
1293                 intel_atomic_get_old_crtc_state(state, crtc);
1294         const struct intel_crtc_state *new_crtc_state =
1295                 intel_atomic_get_new_crtc_state(state, crtc);
1296         u8 update_planes = new_crtc_state->update_planes;
1297         const struct intel_plane_state *old_plane_state;
1298         struct intel_plane *plane;
1299         bool need_vbl_wait = false;
1300         int i;
1301
1302         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1303                 if (plane->need_async_flip_disable_wa &&
1304                     plane->pipe == crtc->pipe &&
1305                     update_planes & BIT(plane->id)) {
1306                         /*
1307                          * Apart from the async flip bit we want to
1308                          * preserve the old state for the plane.
1309                          */
1310                         plane->async_flip(plane, old_crtc_state,
1311                                           old_plane_state, false);
1312                         need_vbl_wait = true;
1313                 }
1314         }
1315
1316         if (need_vbl_wait)
1317                 intel_crtc_wait_for_next_vblank(crtc);
1318 }
1319
1320 static void intel_pre_plane_update(struct intel_atomic_state *state,
1321                                    struct intel_crtc *crtc)
1322 {
1323         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1324         const struct intel_crtc_state *old_crtc_state =
1325                 intel_atomic_get_old_crtc_state(state, crtc);
1326         const struct intel_crtc_state *new_crtc_state =
1327                 intel_atomic_get_new_crtc_state(state, crtc);
1328         enum pipe pipe = crtc->pipe;
1329
1330         intel_drrs_deactivate(old_crtc_state);
1331
1332         intel_psr_pre_plane_update(state, crtc);
1333
1334         if (hsw_ips_pre_update(state, crtc))
1335                 intel_crtc_wait_for_next_vblank(crtc);
1336
1337         if (intel_fbc_pre_update(state, crtc))
1338                 intel_crtc_wait_for_next_vblank(crtc);
1339
1340         if (!needs_async_flip_vtd_wa(old_crtc_state) &&
1341             needs_async_flip_vtd_wa(new_crtc_state))
1342                 intel_async_flip_vtd_wa(dev_priv, pipe, true);
1343
1344         /* Display WA 827 */
1345         if (!needs_nv12_wa(old_crtc_state) &&
1346             needs_nv12_wa(new_crtc_state))
1347                 skl_wa_827(dev_priv, pipe, true);
1348
1349         /* Wa_2006604312:icl,ehl */
1350         if (!needs_scalerclk_wa(old_crtc_state) &&
1351             needs_scalerclk_wa(new_crtc_state))
1352                 icl_wa_scalerclkgating(dev_priv, pipe, true);
1353
1354         /* Wa_1604331009:icl,jsl,ehl */
1355         if (!needs_cursorclk_wa(old_crtc_state) &&
1356             needs_cursorclk_wa(new_crtc_state))
1357                 icl_wa_cursorclkgating(dev_priv, pipe, true);
1358
1359         /*
1360          * Vblank time updates from the shadow to live plane control register
1361          * are blocked if the memory self-refresh mode is active at that
1362          * moment. So to make sure the plane gets truly disabled, disable
1363          * first the self-refresh mode. The self-refresh enable bit in turn
1364          * will be checked/applied by the HW only at the next frame start
1365          * event which is after the vblank start event, so we need to have a
1366          * wait-for-vblank between disabling the plane and the pipe.
1367          */
1368         if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
1369             new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
1370                 intel_crtc_wait_for_next_vblank(crtc);
1371
1372         /*
1373          * IVB workaround: must disable low power watermarks for at least
1374          * one frame before enabling scaling.  LP watermarks can be re-enabled
1375          * when scaling is disabled.
1376          *
1377          * WaCxSRDisabledForSpriteScaling:ivb
1378          */
1379         if (old_crtc_state->hw.active &&
1380             new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
1381                 intel_crtc_wait_for_next_vblank(crtc);
1382
1383         /*
1384          * If we're doing a modeset we don't need to do any
1385          * pre-vblank watermark programming here.
1386          */
1387         if (!intel_crtc_needs_modeset(new_crtc_state)) {
1388                 /*
1389                  * For platforms that support atomic watermarks, program the
1390                  * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
1391                  * will be the intermediate values that are safe for both pre- and
1392                  * post- vblank; when vblank happens, the 'active' values will be set
1393                  * to the final 'target' values and we'll do this again to get the
1394                  * optimal watermarks.  For gen9+ platforms, the values we program here
1395                  * will be the final target values which will get automatically latched
1396                  * at vblank time; no further programming will be necessary.
1397                  *
1398                  * If a platform hasn't been transitioned to atomic watermarks yet,
1399                  * we'll continue to update watermarks the old way, if flags tell
1400                  * us to.
1401                  */
1402                 if (!intel_initial_watermarks(state, crtc))
1403                         if (new_crtc_state->update_wm_pre)
1404                                 intel_update_watermarks(dev_priv);
1405         }
1406
1407         /*
1408          * Gen2 reports pipe underruns whenever all planes are disabled.
1409          * So disable underrun reporting before all the planes get disabled.
1410          *
1411          * We do this after .initial_watermarks() so that we have a
1412          * chance of catching underruns with the intermediate watermarks
1413          * vs. the old plane configuration.
1414          */
1415         if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
1416                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1417
1418         /*
1419          * WA for platforms where async address update enable bit
1420          * is double buffered and only latched at start of vblank.
1421          */
1422         if (old_crtc_state->uapi.async_flip && !new_crtc_state->uapi.async_flip)
1423                 intel_crtc_async_flip_disable_wa(state, crtc);
1424 }
1425
1426 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
1427                                       struct intel_crtc *crtc)
1428 {
1429         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1430         const struct intel_crtc_state *new_crtc_state =
1431                 intel_atomic_get_new_crtc_state(state, crtc);
1432         unsigned int update_mask = new_crtc_state->update_planes;
1433         const struct intel_plane_state *old_plane_state;
1434         struct intel_plane *plane;
1435         unsigned fb_bits = 0;
1436         int i;
1437
1438         intel_crtc_dpms_overlay_disable(crtc);
1439
1440         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1441                 if (crtc->pipe != plane->pipe ||
1442                     !(update_mask & BIT(plane->id)))
1443                         continue;
1444
1445                 intel_plane_disable_arm(plane, new_crtc_state);
1446
1447                 if (old_plane_state->uapi.visible)
1448                         fb_bits |= plane->frontbuffer_bit;
1449         }
1450
1451         intel_frontbuffer_flip(dev_priv, fb_bits);
1452 }
1453
1454 /*
1455  * intel_connector_primary_encoder - get the primary encoder for a connector
1456  * @connector: connector for which to return the encoder
1457  *
1458  * Returns the primary encoder for a connector. There is a 1:1 mapping from
1459  * all connectors to their encoder, except for DP-MST connectors which have
1460  * both a virtual and a primary encoder. These DP-MST primary encoders can be
1461  * pointed to by as many DP-MST connectors as there are pipes.
1462  */
1463 static struct intel_encoder *
1464 intel_connector_primary_encoder(struct intel_connector *connector)
1465 {
1466         struct intel_encoder *encoder;
1467
1468         if (connector->mst_port)
1469                 return &dp_to_dig_port(connector->mst_port)->base;
1470
1471         encoder = intel_attached_encoder(connector);
1472         drm_WARN_ON(connector->base.dev, !encoder);
1473
1474         return encoder;
1475 }
1476
1477 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
1478 {
1479         struct drm_i915_private *i915 = to_i915(state->base.dev);
1480         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
1481         struct intel_crtc *crtc;
1482         struct drm_connector_state *new_conn_state;
1483         struct drm_connector *connector;
1484         int i;
1485
1486         /*
1487          * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
1488          * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
1489          */
1490         if (i915->dpll.mgr) {
1491                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1492                         if (intel_crtc_needs_modeset(new_crtc_state))
1493                                 continue;
1494
1495                         new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;
1496                         new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
1497                 }
1498         }
1499
1500         if (!state->modeset)
1501                 return;
1502
1503         for_each_new_connector_in_state(&state->base, connector, new_conn_state,
1504                                         i) {
1505                 struct intel_connector *intel_connector;
1506                 struct intel_encoder *encoder;
1507                 struct intel_crtc *crtc;
1508
1509                 if (!intel_connector_needs_modeset(state, connector))
1510                         continue;
1511
1512                 intel_connector = to_intel_connector(connector);
1513                 encoder = intel_connector_primary_encoder(intel_connector);
1514                 if (!encoder->update_prepare)
1515                         continue;
1516
1517                 crtc = new_conn_state->crtc ?
1518                         to_intel_crtc(new_conn_state->crtc) : NULL;
1519                 encoder->update_prepare(state, encoder, crtc);
1520         }
1521 }
1522
1523 static void intel_encoders_update_complete(struct intel_atomic_state *state)
1524 {
1525         struct drm_connector_state *new_conn_state;
1526         struct drm_connector *connector;
1527         int i;
1528
1529         if (!state->modeset)
1530                 return;
1531
1532         for_each_new_connector_in_state(&state->base, connector, new_conn_state,
1533                                         i) {
1534                 struct intel_connector *intel_connector;
1535                 struct intel_encoder *encoder;
1536                 struct intel_crtc *crtc;
1537
1538                 if (!intel_connector_needs_modeset(state, connector))
1539                         continue;
1540
1541                 intel_connector = to_intel_connector(connector);
1542                 encoder = intel_connector_primary_encoder(intel_connector);
1543                 if (!encoder->update_complete)
1544                         continue;
1545
1546                 crtc = new_conn_state->crtc ?
1547                         to_intel_crtc(new_conn_state->crtc) : NULL;
1548                 encoder->update_complete(state, encoder, crtc);
1549         }
1550 }
1551
1552 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
1553                                           struct intel_crtc *crtc)
1554 {
1555         const struct intel_crtc_state *crtc_state =
1556                 intel_atomic_get_new_crtc_state(state, crtc);
1557         const struct drm_connector_state *conn_state;
1558         struct drm_connector *conn;
1559         int i;
1560
1561         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1562                 struct intel_encoder *encoder =
1563                         to_intel_encoder(conn_state->best_encoder);
1564
1565                 if (conn_state->crtc != &crtc->base)
1566                         continue;
1567
1568                 if (encoder->pre_pll_enable)
1569                         encoder->pre_pll_enable(state, encoder,
1570                                                 crtc_state, conn_state);
1571         }
1572 }
1573
1574 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
1575                                       struct intel_crtc *crtc)
1576 {
1577         const struct intel_crtc_state *crtc_state =
1578                 intel_atomic_get_new_crtc_state(state, crtc);
1579         const struct drm_connector_state *conn_state;
1580         struct drm_connector *conn;
1581         int i;
1582
1583         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1584                 struct intel_encoder *encoder =
1585                         to_intel_encoder(conn_state->best_encoder);
1586
1587                 if (conn_state->crtc != &crtc->base)
1588                         continue;
1589
1590                 if (encoder->pre_enable)
1591                         encoder->pre_enable(state, encoder,
1592                                             crtc_state, conn_state);
1593         }
1594 }
1595
1596 static void intel_encoders_enable(struct intel_atomic_state *state,
1597                                   struct intel_crtc *crtc)
1598 {
1599         const struct intel_crtc_state *crtc_state =
1600                 intel_atomic_get_new_crtc_state(state, crtc);
1601         const struct drm_connector_state *conn_state;
1602         struct drm_connector *conn;
1603         int i;
1604
1605         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1606                 struct intel_encoder *encoder =
1607                         to_intel_encoder(conn_state->best_encoder);
1608
1609                 if (conn_state->crtc != &crtc->base)
1610                         continue;
1611
1612                 if (encoder->enable)
1613                         encoder->enable(state, encoder,
1614                                         crtc_state, conn_state);
1615                 intel_opregion_notify_encoder(encoder, true);
1616         }
1617 }
1618
1619 static void intel_encoders_disable(struct intel_atomic_state *state,
1620                                    struct intel_crtc *crtc)
1621 {
1622         const struct intel_crtc_state *old_crtc_state =
1623                 intel_atomic_get_old_crtc_state(state, crtc);
1624         const struct drm_connector_state *old_conn_state;
1625         struct drm_connector *conn;
1626         int i;
1627
1628         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1629                 struct intel_encoder *encoder =
1630                         to_intel_encoder(old_conn_state->best_encoder);
1631
1632                 if (old_conn_state->crtc != &crtc->base)
1633                         continue;
1634
1635                 intel_opregion_notify_encoder(encoder, false);
1636                 if (encoder->disable)
1637                         encoder->disable(state, encoder,
1638                                          old_crtc_state, old_conn_state);
1639         }
1640 }
1641
1642 static void intel_encoders_post_disable(struct intel_atomic_state *state,
1643                                         struct intel_crtc *crtc)
1644 {
1645         const struct intel_crtc_state *old_crtc_state =
1646                 intel_atomic_get_old_crtc_state(state, crtc);
1647         const struct drm_connector_state *old_conn_state;
1648         struct drm_connector *conn;
1649         int i;
1650
1651         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1652                 struct intel_encoder *encoder =
1653                         to_intel_encoder(old_conn_state->best_encoder);
1654
1655                 if (old_conn_state->crtc != &crtc->base)
1656                         continue;
1657
1658                 if (encoder->post_disable)
1659                         encoder->post_disable(state, encoder,
1660                                               old_crtc_state, old_conn_state);
1661         }
1662 }
1663
1664 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
1665                                             struct intel_crtc *crtc)
1666 {
1667         const struct intel_crtc_state *old_crtc_state =
1668                 intel_atomic_get_old_crtc_state(state, crtc);
1669         const struct drm_connector_state *old_conn_state;
1670         struct drm_connector *conn;
1671         int i;
1672
1673         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1674                 struct intel_encoder *encoder =
1675                         to_intel_encoder(old_conn_state->best_encoder);
1676
1677                 if (old_conn_state->crtc != &crtc->base)
1678                         continue;
1679
1680                 if (encoder->post_pll_disable)
1681                         encoder->post_pll_disable(state, encoder,
1682                                                   old_crtc_state, old_conn_state);
1683         }
1684 }
1685
1686 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
1687                                        struct intel_crtc *crtc)
1688 {
1689         const struct intel_crtc_state *crtc_state =
1690                 intel_atomic_get_new_crtc_state(state, crtc);
1691         const struct drm_connector_state *conn_state;
1692         struct drm_connector *conn;
1693         int i;
1694
1695         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1696                 struct intel_encoder *encoder =
1697                         to_intel_encoder(conn_state->best_encoder);
1698
1699                 if (conn_state->crtc != &crtc->base)
1700                         continue;
1701
1702                 if (encoder->update_pipe)
1703                         encoder->update_pipe(state, encoder,
1704                                              crtc_state, conn_state);
1705         }
1706 }
1707
1708 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
1709 {
1710         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1711         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1712
1713         plane->disable_arm(plane, crtc_state);
1714 }
1715
1716 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1717 {
1718         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1719         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1720
1721         if (crtc_state->has_pch_encoder) {
1722                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1723                                                &crtc_state->fdi_m_n);
1724         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1725                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1726                                                &crtc_state->dp_m_n);
1727                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1728                                                &crtc_state->dp_m2_n2);
1729         }
1730
1731         intel_set_transcoder_timings(crtc_state);
1732
1733         ilk_set_pipeconf(crtc_state);
1734 }
1735
1736 static void ilk_crtc_enable(struct intel_atomic_state *state,
1737                             struct intel_crtc *crtc)
1738 {
1739         const struct intel_crtc_state *new_crtc_state =
1740                 intel_atomic_get_new_crtc_state(state, crtc);
1741         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1742         enum pipe pipe = crtc->pipe;
1743
1744         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1745                 return;
1746
1747         /*
1748          * Sometimes spurious CPU pipe underruns happen during FDI
1749          * training, at least with VGA+HDMI cloning. Suppress them.
1750          *
1751          * On ILK we get an occasional spurious CPU pipe underruns
1752          * between eDP port A enable and vdd enable. Also PCH port
1753          * enable seems to result in the occasional CPU pipe underrun.
1754          *
1755          * Spurious PCH underruns also occur during PCH enabling.
1756          */
1757         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1758         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1759
1760         ilk_configure_cpu_transcoder(new_crtc_state);
1761
1762         intel_set_pipe_src_size(new_crtc_state);
1763
1764         crtc->active = true;
1765
1766         intel_encoders_pre_enable(state, crtc);
1767
1768         if (new_crtc_state->has_pch_encoder) {
1769                 ilk_pch_pre_enable(state, crtc);
1770         } else {
1771                 assert_fdi_tx_disabled(dev_priv, pipe);
1772                 assert_fdi_rx_disabled(dev_priv, pipe);
1773         }
1774
1775         ilk_pfit_enable(new_crtc_state);
1776
1777         /*
1778          * On ILK+ LUT must be loaded before the pipe is running but with
1779          * clocks enabled
1780          */
1781         intel_color_load_luts(new_crtc_state);
1782         intel_color_commit_noarm(new_crtc_state);
1783         intel_color_commit_arm(new_crtc_state);
1784         /* update DSPCNTR to configure gamma for pipe bottom color */
1785         intel_disable_primary_plane(new_crtc_state);
1786
1787         intel_initial_watermarks(state, crtc);
1788         intel_enable_transcoder(new_crtc_state);
1789
1790         if (new_crtc_state->has_pch_encoder)
1791                 ilk_pch_enable(state, crtc);
1792
1793         intel_crtc_vblank_on(new_crtc_state);
1794
1795         intel_encoders_enable(state, crtc);
1796
1797         if (HAS_PCH_CPT(dev_priv))
1798                 cpt_verify_modeset(dev_priv, pipe);
1799
1800         /*
1801          * Must wait for vblank to avoid spurious PCH FIFO underruns.
1802          * And a second vblank wait is needed at least on ILK with
1803          * some interlaced HDMI modes. Let's do the double wait always
1804          * in case there are more corner cases we don't know about.
1805          */
1806         if (new_crtc_state->has_pch_encoder) {
1807                 intel_crtc_wait_for_next_vblank(crtc);
1808                 intel_crtc_wait_for_next_vblank(crtc);
1809         }
1810         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1811         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1812 }
1813
1814 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
1815                                             enum pipe pipe, bool apply)
1816 {
1817         u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
1818         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
1819
1820         if (apply)
1821                 val |= mask;
1822         else
1823                 val &= ~mask;
1824
1825         intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
1826 }
1827
1828 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
1829 {
1830         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1831         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1832
1833         intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
1834                        HSW_LINETIME(crtc_state->linetime) |
1835                        HSW_IPS_LINETIME(crtc_state->ips_linetime));
1836 }
1837
1838 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
1839 {
1840         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1841         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1842         i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
1843         u32 val;
1844
1845         val = intel_de_read(dev_priv, reg);
1846         val &= ~HSW_FRAME_START_DELAY_MASK;
1847         val |= HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
1848         intel_de_write(dev_priv, reg, val);
1849 }
1850
1851 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
1852                                          const struct intel_crtc_state *crtc_state)
1853 {
1854         struct intel_crtc *master_crtc = intel_master_crtc(crtc_state);
1855
1856         /*
1857          * Enable sequence steps 1-7 on bigjoiner master
1858          */
1859         if (intel_crtc_is_bigjoiner_slave(crtc_state))
1860                 intel_encoders_pre_pll_enable(state, master_crtc);
1861
1862         if (crtc_state->shared_dpll)
1863                 intel_enable_shared_dpll(crtc_state);
1864
1865         if (intel_crtc_is_bigjoiner_slave(crtc_state))
1866                 intel_encoders_pre_enable(state, master_crtc);
1867 }
1868
1869 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1870 {
1871         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1872         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1873         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1874
1875         if (crtc_state->has_pch_encoder) {
1876                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1877                                                &crtc_state->fdi_m_n);
1878         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1879                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1880                                                &crtc_state->dp_m_n);
1881                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1882                                                &crtc_state->dp_m2_n2);
1883         }
1884
1885         intel_set_transcoder_timings(crtc_state);
1886
1887         if (cpu_transcoder != TRANSCODER_EDP)
1888                 intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
1889                                crtc_state->pixel_multiplier - 1);
1890
1891         hsw_set_frame_start_delay(crtc_state);
1892
1893         hsw_set_transconf(crtc_state);
1894 }
1895
1896 static void hsw_crtc_enable(struct intel_atomic_state *state,
1897                             struct intel_crtc *crtc)
1898 {
1899         const struct intel_crtc_state *new_crtc_state =
1900                 intel_atomic_get_new_crtc_state(state, crtc);
1901         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1902         enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
1903         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1904         bool psl_clkgate_wa;
1905
1906         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1907                 return;
1908
1909         if (!new_crtc_state->bigjoiner_pipes) {
1910                 intel_encoders_pre_pll_enable(state, crtc);
1911
1912                 if (new_crtc_state->shared_dpll)
1913                         intel_enable_shared_dpll(new_crtc_state);
1914
1915                 intel_encoders_pre_enable(state, crtc);
1916         } else {
1917                 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
1918         }
1919
1920         intel_dsc_enable(new_crtc_state);
1921
1922         if (DISPLAY_VER(dev_priv) >= 13)
1923                 intel_uncompressed_joiner_enable(new_crtc_state);
1924
1925         intel_set_pipe_src_size(new_crtc_state);
1926         if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
1927                 bdw_set_pipemisc(new_crtc_state);
1928
1929         if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) &&
1930             !transcoder_is_dsi(cpu_transcoder))
1931                 hsw_configure_cpu_transcoder(new_crtc_state);
1932
1933         crtc->active = true;
1934
1935         /* Display WA #1180: WaDisableScalarClockGating: glk */
1936         psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
1937                 new_crtc_state->pch_pfit.enabled;
1938         if (psl_clkgate_wa)
1939                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
1940
1941         if (DISPLAY_VER(dev_priv) >= 9)
1942                 skl_pfit_enable(new_crtc_state);
1943         else
1944                 ilk_pfit_enable(new_crtc_state);
1945
1946         /*
1947          * On ILK+ LUT must be loaded before the pipe is running but with
1948          * clocks enabled
1949          */
1950         intel_color_load_luts(new_crtc_state);
1951         intel_color_commit_noarm(new_crtc_state);
1952         intel_color_commit_arm(new_crtc_state);
1953         /* update DSPCNTR to configure gamma/csc for pipe bottom color */
1954         if (DISPLAY_VER(dev_priv) < 9)
1955                 intel_disable_primary_plane(new_crtc_state);
1956
1957         hsw_set_linetime_wm(new_crtc_state);
1958
1959         if (DISPLAY_VER(dev_priv) >= 11)
1960                 icl_set_pipe_chicken(new_crtc_state);
1961
1962         intel_initial_watermarks(state, crtc);
1963
1964         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
1965                 intel_crtc_vblank_on(new_crtc_state);
1966
1967         intel_encoders_enable(state, crtc);
1968
1969         if (psl_clkgate_wa) {
1970                 intel_crtc_wait_for_next_vblank(crtc);
1971                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
1972         }
1973
1974         /* If we change the relative order between pipe/planes enabling, we need
1975          * to change the workaround. */
1976         hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
1977         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
1978                 struct intel_crtc *wa_crtc;
1979
1980                 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe);
1981
1982                 intel_crtc_wait_for_next_vblank(wa_crtc);
1983                 intel_crtc_wait_for_next_vblank(wa_crtc);
1984         }
1985 }
1986
1987 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
1988 {
1989         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1990         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1991         enum pipe pipe = crtc->pipe;
1992
1993         /* To avoid upsetting the power well on haswell only disable the pfit if
1994          * it's in use. The hw state code will make sure we get this right. */
1995         if (!old_crtc_state->pch_pfit.enabled)
1996                 return;
1997
1998         intel_de_write_fw(dev_priv, PF_CTL(pipe), 0);
1999         intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0);
2000         intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0);
2001 }
2002
2003 static void ilk_crtc_disable(struct intel_atomic_state *state,
2004                              struct intel_crtc *crtc)
2005 {
2006         const struct intel_crtc_state *old_crtc_state =
2007                 intel_atomic_get_old_crtc_state(state, crtc);
2008         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2009         enum pipe pipe = crtc->pipe;
2010
2011         /*
2012          * Sometimes spurious CPU pipe underruns happen when the
2013          * pipe is already disabled, but FDI RX/TX is still enabled.
2014          * Happens at least with VGA+HDMI cloning. Suppress them.
2015          */
2016         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2017         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
2018
2019         intel_encoders_disable(state, crtc);
2020
2021         intel_crtc_vblank_off(old_crtc_state);
2022
2023         intel_disable_transcoder(old_crtc_state);
2024
2025         ilk_pfit_disable(old_crtc_state);
2026
2027         if (old_crtc_state->has_pch_encoder)
2028                 ilk_pch_disable(state, crtc);
2029
2030         intel_encoders_post_disable(state, crtc);
2031
2032         if (old_crtc_state->has_pch_encoder)
2033                 ilk_pch_post_disable(state, crtc);
2034
2035         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2036         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
2037 }
2038
2039 static void hsw_crtc_disable(struct intel_atomic_state *state,
2040                              struct intel_crtc *crtc)
2041 {
2042         const struct intel_crtc_state *old_crtc_state =
2043                 intel_atomic_get_old_crtc_state(state, crtc);
2044
2045         /*
2046          * FIXME collapse everything to one hook.
2047          * Need care with mst->ddi interactions.
2048          */
2049         if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) {
2050                 intel_encoders_disable(state, crtc);
2051                 intel_encoders_post_disable(state, crtc);
2052         }
2053 }
2054
2055 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
2056 {
2057         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2058         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2059
2060         if (!crtc_state->gmch_pfit.control)
2061                 return;
2062
2063         /*
2064          * The panel fitter should only be adjusted whilst the pipe is disabled,
2065          * according to register description and PRM.
2066          */
2067         drm_WARN_ON(&dev_priv->drm,
2068                     intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
2069         assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
2070
2071         intel_de_write(dev_priv, PFIT_PGM_RATIOS,
2072                        crtc_state->gmch_pfit.pgm_ratios);
2073         intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
2074
2075         /* Border color in case we don't scale up to the full screen. Black by
2076          * default, change to something else for debugging. */
2077         intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
2078 }
2079
2080 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
2081 {
2082         if (phy == PHY_NONE)
2083                 return false;
2084         else if (IS_DG2(dev_priv))
2085                 /*
2086                  * DG2 outputs labelled as "combo PHY" in the bspec use
2087                  * SNPS PHYs with completely different programming,
2088                  * hence we always return false here.
2089                  */
2090                 return false;
2091         else if (IS_ALDERLAKE_S(dev_priv))
2092                 return phy <= PHY_E;
2093         else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
2094                 return phy <= PHY_D;
2095         else if (IS_JSL_EHL(dev_priv))
2096                 return phy <= PHY_C;
2097         else if (DISPLAY_VER(dev_priv) >= 11)
2098                 return phy <= PHY_B;
2099         else
2100                 return false;
2101 }
2102
2103 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
2104 {
2105         if (IS_DG2(dev_priv))
2106                 /* DG2's "TC1" output uses a SNPS PHY */
2107                 return false;
2108         else if (IS_ALDERLAKE_P(dev_priv))
2109                 return phy >= PHY_F && phy <= PHY_I;
2110         else if (IS_TIGERLAKE(dev_priv))
2111                 return phy >= PHY_D && phy <= PHY_I;
2112         else if (IS_ICELAKE(dev_priv))
2113                 return phy >= PHY_C && phy <= PHY_F;
2114         else
2115                 return false;
2116 }
2117
2118 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
2119 {
2120         if (phy == PHY_NONE)
2121                 return false;
2122         else if (IS_DG2(dev_priv))
2123                 /*
2124                  * All four "combo" ports and the TC1 port (PHY E) use
2125                  * Synopsis PHYs.
2126                  */
2127                 return phy <= PHY_E;
2128
2129         return false;
2130 }
2131
2132 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
2133 {
2134         if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
2135                 return PHY_D + port - PORT_D_XELPD;
2136         else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
2137                 return PHY_F + port - PORT_TC1;
2138         else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
2139                 return PHY_B + port - PORT_TC1;
2140         else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
2141                 return PHY_C + port - PORT_TC1;
2142         else if (IS_JSL_EHL(i915) && port == PORT_D)
2143                 return PHY_A;
2144
2145         return PHY_A + port - PORT_A;
2146 }
2147
2148 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
2149 {
2150         if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
2151                 return TC_PORT_NONE;
2152
2153         if (DISPLAY_VER(dev_priv) >= 12)
2154                 return TC_PORT_1 + port - PORT_TC1;
2155         else
2156                 return TC_PORT_1 + port - PORT_C;
2157 }
2158
2159 enum intel_display_power_domain
2160 intel_aux_power_domain(struct intel_digital_port *dig_port)
2161 {
2162         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
2163
2164         if (intel_tc_port_in_tbt_alt_mode(dig_port))
2165                 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch);
2166
2167         return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch);
2168 }
2169
2170 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
2171                                    struct intel_power_domain_mask *mask)
2172 {
2173         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2174         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2175         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2176         struct drm_encoder *encoder;
2177         enum pipe pipe = crtc->pipe;
2178
2179         bitmap_zero(mask->bits, POWER_DOMAIN_NUM);
2180
2181         if (!crtc_state->hw.active)
2182                 return;
2183
2184         set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
2185         set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
2186         if (crtc_state->pch_pfit.enabled ||
2187             crtc_state->pch_pfit.force_thru)
2188                 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
2189
2190         drm_for_each_encoder_mask(encoder, &dev_priv->drm,
2191                                   crtc_state->uapi.encoder_mask) {
2192                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2193
2194                 set_bit(intel_encoder->power_domain, mask->bits);
2195         }
2196
2197         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
2198                 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
2199
2200         if (crtc_state->shared_dpll)
2201                 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
2202
2203         if (crtc_state->dsc.compression_enable)
2204                 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
2205 }
2206
2207 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
2208                                           struct intel_power_domain_mask *old_domains)
2209 {
2210         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2211         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2212         enum intel_display_power_domain domain;
2213         struct intel_power_domain_mask domains, new_domains;
2214
2215         get_crtc_power_domains(crtc_state, &domains);
2216
2217         bitmap_andnot(new_domains.bits,
2218                       domains.bits,
2219                       crtc->enabled_power_domains.mask.bits,
2220                       POWER_DOMAIN_NUM);
2221         bitmap_andnot(old_domains->bits,
2222                       crtc->enabled_power_domains.mask.bits,
2223                       domains.bits,
2224                       POWER_DOMAIN_NUM);
2225
2226         for_each_power_domain(domain, &new_domains)
2227                 intel_display_power_get_in_set(dev_priv,
2228                                                &crtc->enabled_power_domains,
2229                                                domain);
2230 }
2231
2232 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
2233                                           struct intel_power_domain_mask *domains)
2234 {
2235         intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
2236                                             &crtc->enabled_power_domains,
2237                                             domains);
2238 }
2239
2240 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
2241 {
2242         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2243         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2244
2245         if (intel_crtc_has_dp_encoder(crtc_state)) {
2246                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
2247                                                &crtc_state->dp_m_n);
2248                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
2249                                                &crtc_state->dp_m2_n2);
2250         }
2251
2252         intel_set_transcoder_timings(crtc_state);
2253
2254         i9xx_set_pipeconf(crtc_state);
2255 }
2256
2257 static void valleyview_crtc_enable(struct intel_atomic_state *state,
2258                                    struct intel_crtc *crtc)
2259 {
2260         const struct intel_crtc_state *new_crtc_state =
2261                 intel_atomic_get_new_crtc_state(state, crtc);
2262         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2263         enum pipe pipe = crtc->pipe;
2264
2265         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2266                 return;
2267
2268         i9xx_configure_cpu_transcoder(new_crtc_state);
2269
2270         intel_set_pipe_src_size(new_crtc_state);
2271
2272         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
2273                 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
2274                 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
2275         }
2276
2277         crtc->active = true;
2278
2279         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2280
2281         intel_encoders_pre_pll_enable(state, crtc);
2282
2283         if (IS_CHERRYVIEW(dev_priv))
2284                 chv_enable_pll(new_crtc_state);
2285         else
2286                 vlv_enable_pll(new_crtc_state);
2287
2288         intel_encoders_pre_enable(state, crtc);
2289
2290         i9xx_pfit_enable(new_crtc_state);
2291
2292         intel_color_load_luts(new_crtc_state);
2293         intel_color_commit_noarm(new_crtc_state);
2294         intel_color_commit_arm(new_crtc_state);
2295         /* update DSPCNTR to configure gamma for pipe bottom color */
2296         intel_disable_primary_plane(new_crtc_state);
2297
2298         intel_initial_watermarks(state, crtc);
2299         intel_enable_transcoder(new_crtc_state);
2300
2301         intel_crtc_vblank_on(new_crtc_state);
2302
2303         intel_encoders_enable(state, crtc);
2304 }
2305
2306 static void i9xx_crtc_enable(struct intel_atomic_state *state,
2307                              struct intel_crtc *crtc)
2308 {
2309         const struct intel_crtc_state *new_crtc_state =
2310                 intel_atomic_get_new_crtc_state(state, crtc);
2311         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2312         enum pipe pipe = crtc->pipe;
2313
2314         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2315                 return;
2316
2317         i9xx_configure_cpu_transcoder(new_crtc_state);
2318
2319         intel_set_pipe_src_size(new_crtc_state);
2320
2321         crtc->active = true;
2322
2323         if (DISPLAY_VER(dev_priv) != 2)
2324                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2325
2326         intel_encoders_pre_enable(state, crtc);
2327
2328         i9xx_enable_pll(new_crtc_state);
2329
2330         i9xx_pfit_enable(new_crtc_state);
2331
2332         intel_color_load_luts(new_crtc_state);
2333         intel_color_commit_noarm(new_crtc_state);
2334         intel_color_commit_arm(new_crtc_state);
2335         /* update DSPCNTR to configure gamma for pipe bottom color */
2336         intel_disable_primary_plane(new_crtc_state);
2337
2338         if (!intel_initial_watermarks(state, crtc))
2339                 intel_update_watermarks(dev_priv);
2340         intel_enable_transcoder(new_crtc_state);
2341
2342         intel_crtc_vblank_on(new_crtc_state);
2343
2344         intel_encoders_enable(state, crtc);
2345
2346         /* prevents spurious underruns */
2347         if (DISPLAY_VER(dev_priv) == 2)
2348                 intel_crtc_wait_for_next_vblank(crtc);
2349 }
2350
2351 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
2352 {
2353         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
2354         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2355
2356         if (!old_crtc_state->gmch_pfit.control)
2357                 return;
2358
2359         assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
2360
2361         drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
2362                     intel_de_read(dev_priv, PFIT_CONTROL));
2363         intel_de_write(dev_priv, PFIT_CONTROL, 0);
2364 }
2365
2366 static void i9xx_crtc_disable(struct intel_atomic_state *state,
2367                               struct intel_crtc *crtc)
2368 {
2369         struct intel_crtc_state *old_crtc_state =
2370                 intel_atomic_get_old_crtc_state(state, crtc);
2371         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2372         enum pipe pipe = crtc->pipe;
2373
2374         /*
2375          * On gen2 planes are double buffered but the pipe isn't, so we must
2376          * wait for planes to fully turn off before disabling the pipe.
2377          */
2378         if (DISPLAY_VER(dev_priv) == 2)
2379                 intel_crtc_wait_for_next_vblank(crtc);
2380
2381         intel_encoders_disable(state, crtc);
2382
2383         intel_crtc_vblank_off(old_crtc_state);
2384
2385         intel_disable_transcoder(old_crtc_state);
2386
2387         i9xx_pfit_disable(old_crtc_state);
2388
2389         intel_encoders_post_disable(state, crtc);
2390
2391         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
2392                 if (IS_CHERRYVIEW(dev_priv))
2393                         chv_disable_pll(dev_priv, pipe);
2394                 else if (IS_VALLEYVIEW(dev_priv))
2395                         vlv_disable_pll(dev_priv, pipe);
2396                 else
2397                         i9xx_disable_pll(old_crtc_state);
2398         }
2399
2400         intel_encoders_post_pll_disable(state, crtc);
2401
2402         if (DISPLAY_VER(dev_priv) != 2)
2403                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2404
2405         if (!dev_priv->wm_disp->initial_watermarks)
2406                 intel_update_watermarks(dev_priv);
2407
2408         /* clock the pipe down to 640x480@60 to potentially save power */
2409         if (IS_I830(dev_priv))
2410                 i830_enable_pipe(dev_priv, pipe);
2411 }
2412
2413
2414 /*
2415  * turn all crtc's off, but do not adjust state
2416  * This has to be paired with a call to intel_modeset_setup_hw_state.
2417  */
2418 int intel_display_suspend(struct drm_device *dev)
2419 {
2420         struct drm_i915_private *dev_priv = to_i915(dev);
2421         struct drm_atomic_state *state;
2422         int ret;
2423
2424         if (!HAS_DISPLAY(dev_priv))
2425                 return 0;
2426
2427         state = drm_atomic_helper_suspend(dev);
2428         ret = PTR_ERR_OR_ZERO(state);
2429         if (ret)
2430                 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
2431                         ret);
2432         else
2433                 dev_priv->modeset_restore_state = state;
2434         return ret;
2435 }
2436
2437 void intel_encoder_destroy(struct drm_encoder *encoder)
2438 {
2439         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2440
2441         drm_encoder_cleanup(encoder);
2442         kfree(intel_encoder);
2443 }
2444
2445 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
2446 {
2447         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2448
2449         /* GDG double wide on either pipe, otherwise pipe A only */
2450         return DISPLAY_VER(dev_priv) < 4 &&
2451                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
2452 }
2453
2454 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
2455 {
2456         u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
2457         struct drm_rect src;
2458
2459         /*
2460          * We only use IF-ID interlacing. If we ever use
2461          * PF-ID we'll need to adjust the pixel_rate here.
2462          */
2463
2464         if (!crtc_state->pch_pfit.enabled)
2465                 return pixel_rate;
2466
2467         drm_rect_init(&src, 0, 0,
2468                       drm_rect_width(&crtc_state->pipe_src) << 16,
2469                       drm_rect_height(&crtc_state->pipe_src) << 16);
2470
2471         return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
2472                                    pixel_rate);
2473 }
2474
2475 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
2476                                          const struct drm_display_mode *timings)
2477 {
2478         mode->hdisplay = timings->crtc_hdisplay;
2479         mode->htotal = timings->crtc_htotal;
2480         mode->hsync_start = timings->crtc_hsync_start;
2481         mode->hsync_end = timings->crtc_hsync_end;
2482
2483         mode->vdisplay = timings->crtc_vdisplay;
2484         mode->vtotal = timings->crtc_vtotal;
2485         mode->vsync_start = timings->crtc_vsync_start;
2486         mode->vsync_end = timings->crtc_vsync_end;
2487
2488         mode->flags = timings->flags;
2489         mode->type = DRM_MODE_TYPE_DRIVER;
2490
2491         mode->clock = timings->crtc_clock;
2492
2493         drm_mode_set_name(mode);
2494 }
2495
2496 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
2497 {
2498         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2499
2500         if (HAS_GMCH(dev_priv))
2501                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
2502                 crtc_state->pixel_rate =
2503                         crtc_state->hw.pipe_mode.crtc_clock;
2504         else
2505                 crtc_state->pixel_rate =
2506                         ilk_pipe_pixel_rate(crtc_state);
2507 }
2508
2509 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state,
2510                                            struct drm_display_mode *mode)
2511 {
2512         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2513
2514         if (num_pipes < 2)
2515                 return;
2516
2517         mode->crtc_clock /= num_pipes;
2518         mode->crtc_hdisplay /= num_pipes;
2519         mode->crtc_hblank_start /= num_pipes;
2520         mode->crtc_hblank_end /= num_pipes;
2521         mode->crtc_hsync_start /= num_pipes;
2522         mode->crtc_hsync_end /= num_pipes;
2523         mode->crtc_htotal /= num_pipes;
2524 }
2525
2526 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state,
2527                                           struct drm_display_mode *mode)
2528 {
2529         int overlap = crtc_state->splitter.pixel_overlap;
2530         int n = crtc_state->splitter.link_count;
2531
2532         if (!crtc_state->splitter.enable)
2533                 return;
2534
2535         /*
2536          * eDP MSO uses segment timings from EDID for transcoder
2537          * timings, but full mode for everything else.
2538          *
2539          * h_full = (h_segment - pixel_overlap) * link_count
2540          */
2541         mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;
2542         mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;
2543         mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;
2544         mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;
2545         mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;
2546         mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;
2547         mode->crtc_clock *= n;
2548 }
2549
2550 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
2551 {
2552         struct drm_display_mode *mode = &crtc_state->hw.mode;
2553         struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2554         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2555
2556         /*
2557          * Start with the adjusted_mode crtc timings, which
2558          * have been filled with the transcoder timings.
2559          */
2560         drm_mode_copy(pipe_mode, adjusted_mode);
2561
2562         /* Expand MSO per-segment transcoder timings to full */
2563         intel_splitter_adjust_timings(crtc_state, pipe_mode);
2564
2565         /*
2566          * We want the full numbers in adjusted_mode normal timings,
2567          * adjusted_mode crtc timings are left with the raw transcoder
2568          * timings.
2569          */
2570         intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);
2571
2572         /* Populate the "user" mode with full numbers */
2573         drm_mode_copy(mode, pipe_mode);
2574         intel_mode_from_crtc_timings(mode, mode);
2575         mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *
2576                 (intel_bigjoiner_num_pipes(crtc_state) ?: 1);
2577         mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);
2578
2579         /* Derive per-pipe timings in case bigjoiner is used */
2580         intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2581         intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2582
2583         intel_crtc_compute_pixel_rate(crtc_state);
2584 }
2585
2586 void intel_encoder_get_config(struct intel_encoder *encoder,
2587                               struct intel_crtc_state *crtc_state)
2588 {
2589         encoder->get_config(encoder, crtc_state);
2590
2591         intel_crtc_readout_derived_state(crtc_state);
2592 }
2593
2594 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
2595 {
2596         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2597         int width, height;
2598
2599         if (num_pipes < 2)
2600                 return;
2601
2602         width = drm_rect_width(&crtc_state->pipe_src);
2603         height = drm_rect_height(&crtc_state->pipe_src);
2604
2605         drm_rect_init(&crtc_state->pipe_src, 0, 0,
2606                       width / num_pipes, height);
2607 }
2608
2609 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state)
2610 {
2611         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2612         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2613
2614         intel_bigjoiner_compute_pipe_src(crtc_state);
2615
2616         /*
2617          * Pipe horizontal size must be even in:
2618          * - DVO ganged mode
2619          * - LVDS dual channel mode
2620          * - Double wide pipe
2621          */
2622         if (drm_rect_width(&crtc_state->pipe_src) & 1) {
2623                 if (crtc_state->double_wide) {
2624                         drm_dbg_kms(&i915->drm,
2625                                     "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n",
2626                                     crtc->base.base.id, crtc->base.name);
2627                         return -EINVAL;
2628                 }
2629
2630                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
2631                     intel_is_dual_link_lvds(i915)) {
2632                         drm_dbg_kms(&i915->drm,
2633                                     "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n",
2634                                     crtc->base.base.id, crtc->base.name);
2635                         return -EINVAL;
2636                 }
2637         }
2638
2639         return 0;
2640 }
2641
2642 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
2643 {
2644         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2645         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2646         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2647         struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2648         int clock_limit = i915->max_dotclk_freq;
2649
2650         /*
2651          * Start with the adjusted_mode crtc timings, which
2652          * have been filled with the transcoder timings.
2653          */
2654         drm_mode_copy(pipe_mode, adjusted_mode);
2655
2656         /* Expand MSO per-segment transcoder timings to full */
2657         intel_splitter_adjust_timings(crtc_state, pipe_mode);
2658
2659         /* Derive per-pipe timings in case bigjoiner is used */
2660         intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2661         intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2662
2663         if (DISPLAY_VER(i915) < 4) {
2664                 clock_limit = i915->max_cdclk_freq * 9 / 10;
2665
2666                 /*
2667                  * Enable double wide mode when the dot clock
2668                  * is > 90% of the (display) core speed.
2669                  */
2670                 if (intel_crtc_supports_double_wide(crtc) &&
2671                     pipe_mode->crtc_clock > clock_limit) {
2672                         clock_limit = i915->max_dotclk_freq;
2673                         crtc_state->double_wide = true;
2674                 }
2675         }
2676
2677         if (pipe_mode->crtc_clock > clock_limit) {
2678                 drm_dbg_kms(&i915->drm,
2679                             "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
2680                             crtc->base.base.id, crtc->base.name,
2681                             pipe_mode->crtc_clock, clock_limit,
2682                             str_yes_no(crtc_state->double_wide));
2683                 return -EINVAL;
2684         }
2685
2686         return 0;
2687 }
2688
2689 static int intel_crtc_compute_config(struct intel_atomic_state *state,
2690                                      struct intel_crtc *crtc)
2691 {
2692         struct intel_crtc_state *crtc_state =
2693                 intel_atomic_get_new_crtc_state(state, crtc);
2694         int ret;
2695
2696         ret = intel_crtc_compute_pipe_src(crtc_state);
2697         if (ret)
2698                 return ret;
2699
2700         ret = intel_crtc_compute_pipe_mode(crtc_state);
2701         if (ret)
2702                 return ret;
2703
2704         intel_crtc_compute_pixel_rate(crtc_state);
2705
2706         if (crtc_state->has_pch_encoder)
2707                 return ilk_fdi_compute_config(crtc, crtc_state);
2708
2709         return 0;
2710 }
2711
2712 static void
2713 intel_reduce_m_n_ratio(u32 *num, u32 *den)
2714 {
2715         while (*num > DATA_LINK_M_N_MASK ||
2716                *den > DATA_LINK_M_N_MASK) {
2717                 *num >>= 1;
2718                 *den >>= 1;
2719         }
2720 }
2721
2722 static void compute_m_n(unsigned int m, unsigned int n,
2723                         u32 *ret_m, u32 *ret_n,
2724                         bool constant_n)
2725 {
2726         /*
2727          * Several DP dongles in particular seem to be fussy about
2728          * too large link M/N values. Give N value as 0x8000 that
2729          * should be acceptable by specific devices. 0x8000 is the
2730          * specified fixed N value for asynchronous clock mode,
2731          * which the devices expect also in synchronous clock mode.
2732          */
2733         if (constant_n)
2734                 *ret_n = DP_LINK_CONSTANT_N_VALUE;
2735         else
2736                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
2737
2738         *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
2739         intel_reduce_m_n_ratio(ret_m, ret_n);
2740 }
2741
2742 void
2743 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
2744                        int pixel_clock, int link_clock,
2745                        struct intel_link_m_n *m_n,
2746                        bool constant_n, bool fec_enable)
2747 {
2748         u32 data_clock = bits_per_pixel * pixel_clock;
2749
2750         if (fec_enable)
2751                 data_clock = intel_dp_mode_to_fec_clock(data_clock);
2752
2753         m_n->tu = 64;
2754         compute_m_n(data_clock,
2755                     link_clock * nlanes * 8,
2756                     &m_n->data_m, &m_n->data_n,
2757                     constant_n);
2758
2759         compute_m_n(pixel_clock, link_clock,
2760                     &m_n->link_m, &m_n->link_n,
2761                     constant_n);
2762 }
2763
2764 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
2765 {
2766         /*
2767          * There may be no VBT; and if the BIOS enabled SSC we can
2768          * just keep using it to avoid unnecessary flicker.  Whereas if the
2769          * BIOS isn't using it, don't assume it will work even if the VBT
2770          * indicates as much.
2771          */
2772         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
2773                 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
2774                                                        PCH_DREF_CONTROL) &
2775                         DREF_SSC1_ENABLE;
2776
2777                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
2778                         drm_dbg_kms(&dev_priv->drm,
2779                                     "SSC %s by BIOS, overriding VBT which says %s\n",
2780                                     str_enabled_disabled(bios_lvds_use_ssc),
2781                                     str_enabled_disabled(dev_priv->vbt.lvds_use_ssc));
2782                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
2783                 }
2784         }
2785 }
2786
2787 void intel_zero_m_n(struct intel_link_m_n *m_n)
2788 {
2789         /* corresponds to 0 register value */
2790         memset(m_n, 0, sizeof(*m_n));
2791         m_n->tu = 1;
2792 }
2793
2794 void intel_set_m_n(struct drm_i915_private *i915,
2795                    const struct intel_link_m_n *m_n,
2796                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
2797                    i915_reg_t link_m_reg, i915_reg_t link_n_reg)
2798 {
2799         intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
2800         intel_de_write(i915, data_n_reg, m_n->data_n);
2801         intel_de_write(i915, link_m_reg, m_n->link_m);
2802         /*
2803          * On BDW+ writing LINK_N arms the double buffered update
2804          * of all the M/N registers, so it must be written last.
2805          */
2806         intel_de_write(i915, link_n_reg, m_n->link_n);
2807 }
2808
2809 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
2810                                     enum transcoder transcoder)
2811 {
2812         if (IS_HASWELL(dev_priv))
2813                 return transcoder == TRANSCODER_EDP;
2814
2815         return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv);
2816 }
2817
2818 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
2819                                     enum transcoder transcoder,
2820                                     const struct intel_link_m_n *m_n)
2821 {
2822         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2823         enum pipe pipe = crtc->pipe;
2824
2825         if (DISPLAY_VER(dev_priv) >= 5)
2826                 intel_set_m_n(dev_priv, m_n,
2827                               PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
2828                               PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
2829         else
2830                 intel_set_m_n(dev_priv, m_n,
2831                               PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
2832                               PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
2833 }
2834
2835 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
2836                                     enum transcoder transcoder,
2837                                     const struct intel_link_m_n *m_n)
2838 {
2839         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2840
2841         if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
2842                 return;
2843
2844         intel_set_m_n(dev_priv, m_n,
2845                       PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
2846                       PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
2847 }
2848
2849 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
2850 {
2851         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2852         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2853         enum pipe pipe = crtc->pipe;
2854         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2855         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2856         u32 crtc_vtotal, crtc_vblank_end;
2857         int vsyncshift = 0;
2858
2859         /* We need to be careful not to changed the adjusted mode, for otherwise
2860          * the hw state checker will get angry at the mismatch. */
2861         crtc_vtotal = adjusted_mode->crtc_vtotal;
2862         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2863
2864         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
2865                 /* the chip adds 2 halflines automatically */
2866                 crtc_vtotal -= 1;
2867                 crtc_vblank_end -= 1;
2868
2869                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2870                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
2871                 else
2872                         vsyncshift = adjusted_mode->crtc_hsync_start -
2873                                 adjusted_mode->crtc_htotal / 2;
2874                 if (vsyncshift < 0)
2875                         vsyncshift += adjusted_mode->crtc_htotal;
2876         }
2877
2878         if (DISPLAY_VER(dev_priv) > 3)
2879                 intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
2880                                vsyncshift);
2881
2882         intel_de_write(dev_priv, HTOTAL(cpu_transcoder),
2883                        (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
2884         intel_de_write(dev_priv, HBLANK(cpu_transcoder),
2885                        (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
2886         intel_de_write(dev_priv, HSYNC(cpu_transcoder),
2887                        (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
2888
2889         intel_de_write(dev_priv, VTOTAL(cpu_transcoder),
2890                        (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
2891         intel_de_write(dev_priv, VBLANK(cpu_transcoder),
2892                        (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
2893         intel_de_write(dev_priv, VSYNC(cpu_transcoder),
2894                        (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
2895
2896         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
2897          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
2898          * documented on the DDI_FUNC_CTL register description, EDP Input Select
2899          * bits. */
2900         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
2901             (pipe == PIPE_B || pipe == PIPE_C))
2902                 intel_de_write(dev_priv, VTOTAL(pipe),
2903                                intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
2904
2905 }
2906
2907 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
2908 {
2909         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2910         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2911         int width = drm_rect_width(&crtc_state->pipe_src);
2912         int height = drm_rect_height(&crtc_state->pipe_src);
2913         enum pipe pipe = crtc->pipe;
2914
2915         /* pipesrc controls the size that is scaled from, which should
2916          * always be the user's requested size.
2917          */
2918         intel_de_write(dev_priv, PIPESRC(pipe),
2919                        PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
2920 }
2921
2922 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
2923 {
2924         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2925         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2926
2927         if (DISPLAY_VER(dev_priv) == 2)
2928                 return false;
2929
2930         if (DISPLAY_VER(dev_priv) >= 9 ||
2931             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2932                 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
2933         else
2934                 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
2935 }
2936
2937 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
2938                                          struct intel_crtc_state *pipe_config)
2939 {
2940         struct drm_device *dev = crtc->base.dev;
2941         struct drm_i915_private *dev_priv = to_i915(dev);
2942         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2943         u32 tmp;
2944
2945         tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));
2946         pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
2947         pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
2948
2949         if (!transcoder_is_dsi(cpu_transcoder)) {
2950                 tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));
2951                 pipe_config->hw.adjusted_mode.crtc_hblank_start =
2952                                                         (tmp & 0xffff) + 1;
2953                 pipe_config->hw.adjusted_mode.crtc_hblank_end =
2954                                                 ((tmp >> 16) & 0xffff) + 1;
2955         }
2956         tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));
2957         pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
2958         pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
2959
2960         tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));
2961         pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
2962         pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
2963
2964         if (!transcoder_is_dsi(cpu_transcoder)) {
2965                 tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));
2966                 pipe_config->hw.adjusted_mode.crtc_vblank_start =
2967                                                         (tmp & 0xffff) + 1;
2968                 pipe_config->hw.adjusted_mode.crtc_vblank_end =
2969                                                 ((tmp >> 16) & 0xffff) + 1;
2970         }
2971         tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));
2972         pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
2973         pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
2974
2975         if (intel_pipe_is_interlaced(pipe_config)) {
2976                 pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
2977                 pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
2978                 pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
2979         }
2980 }
2981
2982 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
2983 {
2984         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2985         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2986         enum pipe master_pipe, pipe = crtc->pipe;
2987         int width;
2988
2989         if (num_pipes < 2)
2990                 return;
2991
2992         master_pipe = bigjoiner_master_pipe(crtc_state);
2993         width = drm_rect_width(&crtc_state->pipe_src);
2994
2995         drm_rect_translate_to(&crtc_state->pipe_src,
2996                               (pipe - master_pipe) * width, 0);
2997 }
2998
2999 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
3000                                     struct intel_crtc_state *pipe_config)
3001 {
3002         struct drm_device *dev = crtc->base.dev;
3003         struct drm_i915_private *dev_priv = to_i915(dev);
3004         u32 tmp;
3005
3006         tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
3007
3008         drm_rect_init(&pipe_config->pipe_src, 0, 0,
3009                       REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
3010                       REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);
3011
3012         intel_bigjoiner_adjust_pipe_src(pipe_config);
3013 }
3014
3015 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
3016 {
3017         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3018         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3019         u32 pipeconf = 0;
3020
3021         /*
3022          * - We keep both pipes enabled on 830
3023          * - During modeset the pipe is still disabled and must remain so
3024          * - During fastset the pipe is already enabled and must remain so
3025          */
3026         if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state))
3027                 pipeconf |= PIPECONF_ENABLE;
3028
3029         if (crtc_state->double_wide)
3030                 pipeconf |= PIPECONF_DOUBLE_WIDE;
3031
3032         /* only g4x and later have fancy bpc/dither controls */
3033         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
3034             IS_CHERRYVIEW(dev_priv)) {
3035                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
3036                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
3037                         pipeconf |= PIPECONF_DITHER_EN |
3038                                     PIPECONF_DITHER_TYPE_SP;
3039
3040                 switch (crtc_state->pipe_bpp) {
3041                 default:
3042                         /* Case prevented by intel_choose_pipe_bpp_dither. */
3043                         MISSING_CASE(crtc_state->pipe_bpp);
3044                         fallthrough;
3045                 case 18:
3046                         pipeconf |= PIPECONF_BPC_6;
3047                         break;
3048                 case 24:
3049                         pipeconf |= PIPECONF_BPC_8;
3050                         break;
3051                 case 30:
3052                         pipeconf |= PIPECONF_BPC_10;
3053                         break;
3054                 }
3055         }
3056
3057         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3058                 if (DISPLAY_VER(dev_priv) < 4 ||
3059                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
3060                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3061                 else
3062                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
3063         } else {
3064                 pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE;
3065         }
3066
3067         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
3068              crtc_state->limited_color_range)
3069                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
3070
3071         pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
3072
3073         pipeconf |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
3074
3075         intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
3076         intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
3077 }
3078
3079 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
3080 {
3081         if (IS_I830(dev_priv))
3082                 return false;
3083
3084         return DISPLAY_VER(dev_priv) >= 4 ||
3085                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
3086 }
3087
3088 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
3089 {
3090         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3091         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3092         u32 tmp;
3093
3094         if (!i9xx_has_pfit(dev_priv))
3095                 return;
3096
3097         tmp = intel_de_read(dev_priv, PFIT_CONTROL);
3098         if (!(tmp & PFIT_ENABLE))
3099                 return;
3100
3101         /* Check whether the pfit is attached to our pipe. */
3102         if (DISPLAY_VER(dev_priv) < 4) {
3103                 if (crtc->pipe != PIPE_B)
3104                         return;
3105         } else {
3106                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
3107                         return;
3108         }
3109
3110         crtc_state->gmch_pfit.control = tmp;
3111         crtc_state->gmch_pfit.pgm_ratios =
3112                 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
3113 }
3114
3115 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
3116                                struct intel_crtc_state *pipe_config)
3117 {
3118         struct drm_device *dev = crtc->base.dev;
3119         struct drm_i915_private *dev_priv = to_i915(dev);
3120         enum pipe pipe = crtc->pipe;
3121         struct dpll clock;
3122         u32 mdiv;
3123         int refclk = 100000;
3124
3125         /* In case of DSI, DPLL will not be used */
3126         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
3127                 return;
3128
3129         vlv_dpio_get(dev_priv);
3130         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
3131         vlv_dpio_put(dev_priv);
3132
3133         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
3134         clock.m2 = mdiv & DPIO_M2DIV_MASK;
3135         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
3136         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
3137         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
3138
3139         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
3140 }
3141
3142 static void chv_crtc_clock_get(struct intel_crtc *crtc,
3143                                struct intel_crtc_state *pipe_config)
3144 {
3145         struct drm_device *dev = crtc->base.dev;
3146         struct drm_i915_private *dev_priv = to_i915(dev);
3147         enum pipe pipe = crtc->pipe;
3148         enum dpio_channel port = vlv_pipe_to_channel(pipe);
3149         struct dpll clock;
3150         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
3151         int refclk = 100000;
3152
3153         /* In case of DSI, DPLL will not be used */
3154         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
3155                 return;
3156
3157         vlv_dpio_get(dev_priv);
3158         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
3159         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
3160         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
3161         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
3162         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
3163         vlv_dpio_put(dev_priv);
3164
3165         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
3166         clock.m2 = (pll_dw0 & 0xff) << 22;
3167         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
3168                 clock.m2 |= pll_dw2 & 0x3fffff;
3169         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
3170         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
3171         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
3172
3173         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
3174 }
3175
3176 static enum intel_output_format
3177 bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
3178 {
3179         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3180         u32 tmp;
3181
3182         tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
3183
3184         if (tmp & PIPEMISC_YUV420_ENABLE) {
3185                 /* We support 4:2:0 in full blend mode only */
3186                 drm_WARN_ON(&dev_priv->drm,
3187                             (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
3188
3189                 return INTEL_OUTPUT_FORMAT_YCBCR420;
3190         } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
3191                 return INTEL_OUTPUT_FORMAT_YCBCR444;
3192         } else {
3193                 return INTEL_OUTPUT_FORMAT_RGB;
3194         }
3195 }
3196
3197 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
3198 {
3199         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3200         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
3201         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3202         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
3203         u32 tmp;
3204
3205         tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
3206
3207         if (tmp & DISP_PIPE_GAMMA_ENABLE)
3208                 crtc_state->gamma_enable = true;
3209
3210         if (!HAS_GMCH(dev_priv) &&
3211             tmp & DISP_PIPE_CSC_ENABLE)
3212                 crtc_state->csc_enable = true;
3213 }
3214
3215 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
3216                                  struct intel_crtc_state *pipe_config)
3217 {
3218         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3219         enum intel_display_power_domain power_domain;
3220         intel_wakeref_t wakeref;
3221         u32 tmp;
3222         bool ret;
3223
3224         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3225         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3226         if (!wakeref)
3227                 return false;
3228
3229         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3230         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3231         pipe_config->shared_dpll = NULL;
3232
3233         ret = false;
3234
3235         tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
3236         if (!(tmp & PIPECONF_ENABLE))
3237                 goto out;
3238
3239         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
3240             IS_CHERRYVIEW(dev_priv)) {
3241                 switch (tmp & PIPECONF_BPC_MASK) {
3242                 case PIPECONF_BPC_6:
3243                         pipe_config->pipe_bpp = 18;
3244                         break;
3245                 case PIPECONF_BPC_8:
3246                         pipe_config->pipe_bpp = 24;
3247                         break;
3248                 case PIPECONF_BPC_10:
3249                         pipe_config->pipe_bpp = 30;
3250                         break;
3251                 default:
3252                         MISSING_CASE(tmp);
3253                         break;
3254                 }
3255         }
3256
3257         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
3258             (tmp & PIPECONF_COLOR_RANGE_SELECT))
3259                 pipe_config->limited_color_range = true;
3260
3261         pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp);
3262
3263         pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1;
3264
3265         if (IS_CHERRYVIEW(dev_priv))
3266                 pipe_config->cgm_mode = intel_de_read(dev_priv,
3267                                                       CGM_PIPE_MODE(crtc->pipe));
3268
3269         i9xx_get_pipe_color_config(pipe_config);
3270         intel_color_get_config(pipe_config);
3271
3272         if (DISPLAY_VER(dev_priv) < 4)
3273                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
3274
3275         intel_get_transcoder_timings(crtc, pipe_config);
3276         intel_get_pipe_src_size(crtc, pipe_config);
3277
3278         i9xx_get_pfit_config(pipe_config);
3279
3280         if (DISPLAY_VER(dev_priv) >= 4) {
3281                 /* No way to read it out on pipes B and C */
3282                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
3283                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
3284                 else
3285                         tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
3286                 pipe_config->pixel_multiplier =
3287                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
3288                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
3289                 pipe_config->dpll_hw_state.dpll_md = tmp;
3290         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
3291                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
3292                 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
3293                 pipe_config->pixel_multiplier =
3294                         ((tmp & SDVO_MULTIPLIER_MASK)
3295                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
3296         } else {
3297                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
3298                  * port and will be fixed up in the encoder->get_config
3299                  * function. */
3300                 pipe_config->pixel_multiplier = 1;
3301         }
3302         pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
3303                                                         DPLL(crtc->pipe));
3304         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
3305                 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
3306                                                                FP0(crtc->pipe));
3307                 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
3308                                                                FP1(crtc->pipe));
3309         } else {
3310                 /* Mask out read-only status bits. */
3311                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
3312                                                      DPLL_PORTC_READY_MASK |
3313                                                      DPLL_PORTB_READY_MASK);
3314         }
3315
3316         if (IS_CHERRYVIEW(dev_priv))
3317                 chv_crtc_clock_get(crtc, pipe_config);
3318         else if (IS_VALLEYVIEW(dev_priv))
3319                 vlv_crtc_clock_get(crtc, pipe_config);
3320         else
3321                 i9xx_crtc_clock_get(crtc, pipe_config);
3322
3323         /*
3324          * Normally the dotclock is filled in by the encoder .get_config()
3325          * but in case the pipe is enabled w/o any ports we need a sane
3326          * default.
3327          */
3328         pipe_config->hw.adjusted_mode.crtc_clock =
3329                 pipe_config->port_clock / pipe_config->pixel_multiplier;
3330
3331         ret = true;
3332
3333 out:
3334         intel_display_power_put(dev_priv, power_domain, wakeref);
3335
3336         return ret;
3337 }
3338
3339 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
3340 {
3341         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3342         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3343         enum pipe pipe = crtc->pipe;
3344         u32 val = 0;
3345
3346         /*
3347          * - During modeset the pipe is still disabled and must remain so
3348          * - During fastset the pipe is already enabled and must remain so
3349          */
3350         if (!intel_crtc_needs_modeset(crtc_state))
3351                 val |= PIPECONF_ENABLE;
3352
3353         switch (crtc_state->pipe_bpp) {
3354         default:
3355                 /* Case prevented by intel_choose_pipe_bpp_dither. */
3356                 MISSING_CASE(crtc_state->pipe_bpp);
3357                 fallthrough;
3358         case 18:
3359                 val |= PIPECONF_BPC_6;
3360                 break;
3361         case 24:
3362                 val |= PIPECONF_BPC_8;
3363                 break;
3364         case 30:
3365                 val |= PIPECONF_BPC_10;
3366                 break;
3367         case 36:
3368                 val |= PIPECONF_BPC_12;
3369                 break;
3370         }
3371
3372         if (crtc_state->dither)
3373                 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
3374
3375         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3376                 val |= PIPECONF_INTERLACE_IF_ID_ILK;
3377         else
3378                 val |= PIPECONF_INTERLACE_PF_PD_ILK;
3379
3380         /*
3381          * This would end up with an odd purple hue over
3382          * the entire display. Make sure we don't do it.
3383          */
3384         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
3385                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
3386
3387         if (crtc_state->limited_color_range &&
3388             !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
3389                 val |= PIPECONF_COLOR_RANGE_SELECT;
3390
3391         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3392                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
3393
3394         val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
3395
3396         val |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
3397         val |= PIPECONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
3398
3399         intel_de_write(dev_priv, PIPECONF(pipe), val);
3400         intel_de_posting_read(dev_priv, PIPECONF(pipe));
3401 }
3402
3403 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
3404 {
3405         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3406         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3407         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3408         u32 val = 0;
3409
3410         /*
3411          * - During modeset the pipe is still disabled and must remain so
3412          * - During fastset the pipe is already enabled and must remain so
3413          */
3414         if (!intel_crtc_needs_modeset(crtc_state))
3415                 val |= PIPECONF_ENABLE;
3416
3417         if (IS_HASWELL(dev_priv) && crtc_state->dither)
3418                 val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
3419
3420         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3421                 val |= PIPECONF_INTERLACE_IF_ID_ILK;
3422         else
3423                 val |= PIPECONF_INTERLACE_PF_PD_ILK;
3424
3425         if (IS_HASWELL(dev_priv) &&
3426             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3427                 val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
3428
3429         intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
3430         intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
3431 }
3432
3433 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
3434 {
3435         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3436         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3437         u32 val = 0;
3438
3439         switch (crtc_state->pipe_bpp) {
3440         case 18:
3441                 val |= PIPEMISC_BPC_6;
3442                 break;
3443         case 24:
3444                 val |= PIPEMISC_BPC_8;
3445                 break;
3446         case 30:
3447                 val |= PIPEMISC_BPC_10;
3448                 break;
3449         case 36:
3450                 /* Port output 12BPC defined for ADLP+ */
3451                 if (DISPLAY_VER(dev_priv) > 12)
3452                         val |= PIPEMISC_BPC_12_ADLP;
3453                 break;
3454         default:
3455                 MISSING_CASE(crtc_state->pipe_bpp);
3456                 break;
3457         }
3458
3459         if (crtc_state->dither)
3460                 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
3461
3462         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
3463             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
3464                 val |= PIPEMISC_OUTPUT_COLORSPACE_YUV;
3465
3466         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3467                 val |= PIPEMISC_YUV420_ENABLE |
3468                         PIPEMISC_YUV420_MODE_FULL_BLEND;
3469
3470         if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state))
3471                 val |= PIPEMISC_HDR_MODE_PRECISION;
3472
3473         if (DISPLAY_VER(dev_priv) >= 12)
3474                 val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
3475
3476         intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
3477 }
3478
3479 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
3480 {
3481         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3482         u32 tmp;
3483
3484         tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
3485
3486         switch (tmp & PIPEMISC_BPC_MASK) {
3487         case PIPEMISC_BPC_6:
3488                 return 18;
3489         case PIPEMISC_BPC_8:
3490                 return 24;
3491         case PIPEMISC_BPC_10:
3492                 return 30;
3493         /*
3494          * PORT OUTPUT 12 BPC defined for ADLP+.
3495          *
3496          * TODO:
3497          * For previous platforms with DSI interface, bits 5:7
3498          * are used for storing pipe_bpp irrespective of dithering.
3499          * Since the value of 12 BPC is not defined for these bits
3500          * on older platforms, need to find a workaround for 12 BPC
3501          * MIPI DSI HW readout.
3502          */
3503         case PIPEMISC_BPC_12_ADLP:
3504                 if (DISPLAY_VER(dev_priv) > 12)
3505                         return 36;
3506                 fallthrough;
3507         default:
3508                 MISSING_CASE(tmp);
3509                 return 0;
3510         }
3511 }
3512
3513 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
3514 {
3515         /*
3516          * Account for spread spectrum to avoid
3517          * oversubscribing the link. Max center spread
3518          * is 2.5%; use 5% for safety's sake.
3519          */
3520         u32 bps = target_clock * bpp * 21 / 20;
3521         return DIV_ROUND_UP(bps, link_bw * 8);
3522 }
3523
3524 void intel_get_m_n(struct drm_i915_private *i915,
3525                    struct intel_link_m_n *m_n,
3526                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
3527                    i915_reg_t link_m_reg, i915_reg_t link_n_reg)
3528 {
3529         m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
3530         m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
3531         m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
3532         m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
3533         m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
3534 }
3535
3536 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
3537                                     enum transcoder transcoder,
3538                                     struct intel_link_m_n *m_n)
3539 {
3540         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3541         enum pipe pipe = crtc->pipe;
3542
3543         if (DISPLAY_VER(dev_priv) >= 5)
3544                 intel_get_m_n(dev_priv, m_n,
3545                               PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
3546                               PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
3547         else
3548                 intel_get_m_n(dev_priv, m_n,
3549                               PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
3550                               PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
3551 }
3552
3553 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
3554                                     enum transcoder transcoder,
3555                                     struct intel_link_m_n *m_n)
3556 {
3557         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3558
3559         if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
3560                 return;
3561
3562         intel_get_m_n(dev_priv, m_n,
3563                       PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
3564                       PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
3565 }
3566
3567 static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
3568                                   u32 pos, u32 size)
3569 {
3570         drm_rect_init(&crtc_state->pch_pfit.dst,
3571                       pos >> 16, pos & 0xffff,
3572                       size >> 16, size & 0xffff);
3573 }
3574
3575 static void skl_get_pfit_config(struct intel_crtc_state *crtc_state)
3576 {
3577         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3578         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3579         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
3580         int id = -1;
3581         int i;
3582
3583         /* find scaler attached to this pipe */
3584         for (i = 0; i < crtc->num_scalers; i++) {
3585                 u32 ctl, pos, size;
3586
3587                 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
3588                 if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
3589                         continue;
3590
3591                 id = i;
3592                 crtc_state->pch_pfit.enabled = true;
3593
3594                 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
3595                 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
3596
3597                 ilk_get_pfit_pos_size(crtc_state, pos, size);
3598
3599                 scaler_state->scalers[i].in_use = true;
3600                 break;
3601         }
3602
3603         scaler_state->scaler_id = id;
3604         if (id >= 0)
3605                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
3606         else
3607                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
3608 }
3609
3610 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
3611 {
3612         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3613         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3614         u32 ctl, pos, size;
3615
3616         ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
3617         if ((ctl & PF_ENABLE) == 0)
3618                 return;
3619
3620         crtc_state->pch_pfit.enabled = true;
3621
3622         pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
3623         size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
3624
3625         ilk_get_pfit_pos_size(crtc_state, pos, size);
3626
3627         /*
3628          * We currently do not free assignements of panel fitters on
3629          * ivb/hsw (since we don't use the higher upscaling modes which
3630          * differentiates them) so just WARN about this case for now.
3631          */
3632         drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 7 &&
3633                     (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
3634 }
3635
3636 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
3637                                 struct intel_crtc_state *pipe_config)
3638 {
3639         struct drm_device *dev = crtc->base.dev;
3640         struct drm_i915_private *dev_priv = to_i915(dev);
3641         enum intel_display_power_domain power_domain;
3642         intel_wakeref_t wakeref;
3643         u32 tmp;
3644         bool ret;
3645
3646         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3647         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3648         if (!wakeref)
3649                 return false;
3650
3651         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3652         pipe_config->shared_dpll = NULL;
3653
3654         ret = false;
3655         tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
3656         if (!(tmp & PIPECONF_ENABLE))
3657                 goto out;
3658
3659         switch (tmp & PIPECONF_BPC_MASK) {
3660         case PIPECONF_BPC_6:
3661                 pipe_config->pipe_bpp = 18;
3662                 break;
3663         case PIPECONF_BPC_8:
3664                 pipe_config->pipe_bpp = 24;
3665                 break;
3666         case PIPECONF_BPC_10:
3667                 pipe_config->pipe_bpp = 30;
3668                 break;
3669         case PIPECONF_BPC_12:
3670                 pipe_config->pipe_bpp = 36;
3671                 break;
3672         default:
3673                 break;
3674         }
3675
3676         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
3677                 pipe_config->limited_color_range = true;
3678
3679         switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
3680         case PIPECONF_OUTPUT_COLORSPACE_YUV601:
3681         case PIPECONF_OUTPUT_COLORSPACE_YUV709:
3682                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3683                 break;
3684         default:
3685                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3686                 break;
3687         }
3688
3689         pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp);
3690
3691         pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1;
3692
3693         pipe_config->msa_timing_delay = REG_FIELD_GET(PIPECONF_MSA_TIMING_DELAY_MASK, tmp);
3694
3695         pipe_config->csc_mode = intel_de_read(dev_priv,
3696                                               PIPE_CSC_MODE(crtc->pipe));
3697
3698         i9xx_get_pipe_color_config(pipe_config);
3699         intel_color_get_config(pipe_config);
3700
3701         pipe_config->pixel_multiplier = 1;
3702
3703         ilk_pch_get_config(pipe_config);
3704
3705         intel_get_transcoder_timings(crtc, pipe_config);
3706         intel_get_pipe_src_size(crtc, pipe_config);
3707
3708         ilk_get_pfit_config(pipe_config);
3709
3710         ret = true;
3711
3712 out:
3713         intel_display_power_put(dev_priv, power_domain, wakeref);
3714
3715         return ret;
3716 }
3717
3718 static u8 bigjoiner_pipes(struct drm_i915_private *i915)
3719 {
3720         if (DISPLAY_VER(i915) >= 12)
3721                 return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
3722         else if (DISPLAY_VER(i915) >= 11)
3723                 return BIT(PIPE_B) | BIT(PIPE_C);
3724         else
3725                 return 0;
3726 }
3727
3728 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
3729                                            enum transcoder cpu_transcoder)
3730 {
3731         enum intel_display_power_domain power_domain;
3732         intel_wakeref_t wakeref;
3733         u32 tmp = 0;
3734
3735         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3736
3737         with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3738                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3739
3740         return tmp & TRANS_DDI_FUNC_ENABLE;
3741 }
3742
3743 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv,
3744                                     u8 *master_pipes, u8 *slave_pipes)
3745 {
3746         struct intel_crtc *crtc;
3747
3748         *master_pipes = 0;
3749         *slave_pipes = 0;
3750
3751         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,
3752                                          bigjoiner_pipes(dev_priv)) {
3753                 enum intel_display_power_domain power_domain;
3754                 enum pipe pipe = crtc->pipe;
3755                 intel_wakeref_t wakeref;
3756
3757                 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe);
3758                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3759                         u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3760
3761                         if (!(tmp & BIG_JOINER_ENABLE))
3762                                 continue;
3763
3764                         if (tmp & MASTER_BIG_JOINER_ENABLE)
3765                                 *master_pipes |= BIT(pipe);
3766                         else
3767                                 *slave_pipes |= BIT(pipe);
3768                 }
3769
3770                 if (DISPLAY_VER(dev_priv) < 13)
3771                         continue;
3772
3773                 power_domain = POWER_DOMAIN_PIPE(pipe);
3774                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3775                         u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3776
3777                         if (tmp & UNCOMPRESSED_JOINER_MASTER)
3778                                 *master_pipes |= BIT(pipe);
3779                         if (tmp & UNCOMPRESSED_JOINER_SLAVE)
3780                                 *slave_pipes |= BIT(pipe);
3781                 }
3782         }
3783
3784         /* Bigjoiner pipes should always be consecutive master and slave */
3785         drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1,
3786                  "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n",
3787                  *master_pipes, *slave_pipes);
3788 }
3789
3790 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3791 {
3792         if ((slave_pipes & BIT(pipe)) == 0)
3793                 return pipe;
3794
3795         /* ignore everything above our pipe */
3796         master_pipes &= ~GENMASK(7, pipe);
3797
3798         /* highest remaining bit should be our master pipe */
3799         return fls(master_pipes) - 1;
3800 }
3801
3802 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3803 {
3804         enum pipe master_pipe, next_master_pipe;
3805
3806         master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes);
3807
3808         if ((master_pipes & BIT(master_pipe)) == 0)
3809                 return 0;
3810
3811         /* ignore our master pipe and everything below it */
3812         master_pipes &= ~GENMASK(master_pipe, 0);
3813         /* make sure a high bit is set for the ffs() */
3814         master_pipes |= BIT(7);
3815         /* lowest remaining bit should be the next master pipe */
3816         next_master_pipe = ffs(master_pipes) - 1;
3817
3818         return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe);
3819 }
3820
3821 static u8 hsw_panel_transcoders(struct drm_i915_private *i915)
3822 {
3823         u8 panel_transcoder_mask = BIT(TRANSCODER_EDP);
3824
3825         if (DISPLAY_VER(i915) >= 11)
3826                 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
3827
3828         return panel_transcoder_mask;
3829 }
3830
3831 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
3832 {
3833         struct drm_device *dev = crtc->base.dev;
3834         struct drm_i915_private *dev_priv = to_i915(dev);
3835         u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv);
3836         enum transcoder cpu_transcoder;
3837         u8 master_pipes, slave_pipes;
3838         u8 enabled_transcoders = 0;
3839
3840         /*
3841          * XXX: Do intel_display_power_get_if_enabled before reading this (for
3842          * consistency and less surprising code; it's in always on power).
3843          */
3844         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder,
3845                                        panel_transcoder_mask) {
3846                 enum intel_display_power_domain power_domain;
3847                 intel_wakeref_t wakeref;
3848                 enum pipe trans_pipe;
3849                 u32 tmp = 0;
3850
3851                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3852                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3853                         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3854
3855                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
3856                         continue;
3857
3858                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
3859                 default:
3860                         drm_WARN(dev, 1,
3861                                  "unknown pipe linked to transcoder %s\n",
3862                                  transcoder_name(cpu_transcoder));
3863                         fallthrough;
3864                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
3865                 case TRANS_DDI_EDP_INPUT_A_ON:
3866                         trans_pipe = PIPE_A;
3867                         break;
3868                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
3869                         trans_pipe = PIPE_B;
3870                         break;
3871                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
3872                         trans_pipe = PIPE_C;
3873                         break;
3874                 case TRANS_DDI_EDP_INPUT_D_ONOFF:
3875                         trans_pipe = PIPE_D;
3876                         break;
3877                 }
3878
3879                 if (trans_pipe == crtc->pipe)
3880                         enabled_transcoders |= BIT(cpu_transcoder);
3881         }
3882
3883         /* single pipe or bigjoiner master */
3884         cpu_transcoder = (enum transcoder) crtc->pipe;
3885         if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3886                 enabled_transcoders |= BIT(cpu_transcoder);
3887
3888         /* bigjoiner slave -> consider the master pipe's transcoder as well */
3889         enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes);
3890         if (slave_pipes & BIT(crtc->pipe)) {
3891                 cpu_transcoder = (enum transcoder)
3892                         get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes);
3893                 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3894                         enabled_transcoders |= BIT(cpu_transcoder);
3895         }
3896
3897         return enabled_transcoders;
3898 }
3899
3900 static bool has_edp_transcoders(u8 enabled_transcoders)
3901 {
3902         return enabled_transcoders & BIT(TRANSCODER_EDP);
3903 }
3904
3905 static bool has_dsi_transcoders(u8 enabled_transcoders)
3906 {
3907         return enabled_transcoders & (BIT(TRANSCODER_DSI_0) |
3908                                       BIT(TRANSCODER_DSI_1));
3909 }
3910
3911 static bool has_pipe_transcoders(u8 enabled_transcoders)
3912 {
3913         return enabled_transcoders & ~(BIT(TRANSCODER_EDP) |
3914                                        BIT(TRANSCODER_DSI_0) |
3915                                        BIT(TRANSCODER_DSI_1));
3916 }
3917
3918 static void assert_enabled_transcoders(struct drm_i915_private *i915,
3919                                        u8 enabled_transcoders)
3920 {
3921         /* Only one type of transcoder please */
3922         drm_WARN_ON(&i915->drm,
3923                     has_edp_transcoders(enabled_transcoders) +
3924                     has_dsi_transcoders(enabled_transcoders) +
3925                     has_pipe_transcoders(enabled_transcoders) > 1);
3926
3927         /* Only DSI transcoders can be ganged */
3928         drm_WARN_ON(&i915->drm,
3929                     !has_dsi_transcoders(enabled_transcoders) &&
3930                     !is_power_of_2(enabled_transcoders));
3931 }
3932
3933 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
3934                                      struct intel_crtc_state *pipe_config,
3935                                      struct intel_display_power_domain_set *power_domain_set)
3936 {
3937         struct drm_device *dev = crtc->base.dev;
3938         struct drm_i915_private *dev_priv = to_i915(dev);
3939         unsigned long enabled_transcoders;
3940         u32 tmp;
3941
3942         enabled_transcoders = hsw_enabled_transcoders(crtc);
3943         if (!enabled_transcoders)
3944                 return false;
3945
3946         assert_enabled_transcoders(dev_priv, enabled_transcoders);
3947
3948         /*
3949          * With the exception of DSI we should only ever have
3950          * a single enabled transcoder. With DSI let's just
3951          * pick the first one.
3952          */
3953         pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;
3954
3955         if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3956                                                        POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
3957                 return false;
3958
3959         if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) {
3960                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
3961
3962                 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
3963                         pipe_config->pch_pfit.force_thru = true;
3964         }
3965
3966         tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
3967
3968         return tmp & PIPECONF_ENABLE;
3969 }
3970
3971 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
3972                                          struct intel_crtc_state *pipe_config,
3973                                          struct intel_display_power_domain_set *power_domain_set)
3974 {
3975         struct drm_device *dev = crtc->base.dev;
3976         struct drm_i915_private *dev_priv = to_i915(dev);
3977         enum transcoder cpu_transcoder;
3978         enum port port;
3979         u32 tmp;
3980
3981         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
3982                 if (port == PORT_A)
3983                         cpu_transcoder = TRANSCODER_DSI_A;
3984                 else
3985                         cpu_transcoder = TRANSCODER_DSI_C;
3986
3987                 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3988                                                                POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
3989                         continue;
3990
3991                 /*
3992                  * The PLL needs to be enabled with a valid divider
3993                  * configuration, otherwise accessing DSI registers will hang
3994                  * the machine. See BSpec North Display Engine
3995                  * registers/MIPI[BXT]. We can break out here early, since we
3996                  * need the same DSI PLL to be enabled for both DSI ports.
3997                  */
3998                 if (!bxt_dsi_pll_is_enabled(dev_priv))
3999                         break;
4000
4001                 /* XXX: this works for video mode only */
4002                 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
4003                 if (!(tmp & DPI_ENABLE))
4004                         continue;
4005
4006                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
4007                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
4008                         continue;
4009
4010                 pipe_config->cpu_transcoder = cpu_transcoder;
4011                 break;
4012         }
4013
4014         return transcoder_is_dsi(pipe_config->cpu_transcoder);
4015 }
4016
4017 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state)
4018 {
4019         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4020         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4021         u8 master_pipes, slave_pipes;
4022         enum pipe pipe = crtc->pipe;
4023
4024         enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes);
4025
4026         if (((master_pipes | slave_pipes) & BIT(pipe)) == 0)
4027                 return;
4028
4029         crtc_state->bigjoiner_pipes =
4030                 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) |
4031                 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes);
4032 }
4033
4034 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
4035                                 struct intel_crtc_state *pipe_config)
4036 {
4037         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4038         struct intel_display_power_domain_set power_domain_set = { };
4039         bool active;
4040         u32 tmp;
4041
4042         if (!intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
4043                                                        POWER_DOMAIN_PIPE(crtc->pipe)))
4044                 return false;
4045
4046         pipe_config->shared_dpll = NULL;
4047
4048         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_set);
4049
4050         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
4051             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_set)) {
4052                 drm_WARN_ON(&dev_priv->drm, active);
4053                 active = true;
4054         }
4055
4056         if (!active)
4057                 goto out;
4058
4059         intel_dsc_get_config(pipe_config);
4060         intel_bigjoiner_get_config(pipe_config);
4061
4062         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
4063             DISPLAY_VER(dev_priv) >= 11)
4064                 intel_get_transcoder_timings(crtc, pipe_config);
4065
4066         if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
4067                 intel_vrr_get_config(crtc, pipe_config);
4068
4069         intel_get_pipe_src_size(crtc, pipe_config);
4070
4071         if (IS_HASWELL(dev_priv)) {
4072                 u32 tmp = intel_de_read(dev_priv,
4073                                         PIPECONF(pipe_config->cpu_transcoder));
4074
4075                 if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
4076                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
4077                 else
4078                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
4079         } else {
4080                 pipe_config->output_format =
4081                         bdw_get_pipemisc_output_format(crtc);
4082         }
4083
4084         pipe_config->gamma_mode = intel_de_read(dev_priv,
4085                                                 GAMMA_MODE(crtc->pipe));
4086
4087         pipe_config->csc_mode = intel_de_read(dev_priv,
4088                                               PIPE_CSC_MODE(crtc->pipe));
4089
4090         if (DISPLAY_VER(dev_priv) >= 9) {
4091                 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
4092
4093                 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
4094                         pipe_config->gamma_enable = true;
4095
4096                 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
4097                         pipe_config->csc_enable = true;
4098         } else {
4099                 i9xx_get_pipe_color_config(pipe_config);
4100         }
4101
4102         intel_color_get_config(pipe_config);
4103
4104         tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
4105         pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
4106         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
4107                 pipe_config->ips_linetime =
4108                         REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
4109
4110         if (intel_display_power_get_in_set_if_enabled(dev_priv, &power_domain_set,
4111                                                       POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
4112                 if (DISPLAY_VER(dev_priv) >= 9)
4113                         skl_get_pfit_config(pipe_config);
4114                 else
4115                         ilk_get_pfit_config(pipe_config);
4116         }
4117
4118         hsw_ips_get_config(pipe_config);
4119
4120         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
4121             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
4122                 pipe_config->pixel_multiplier =
4123                         intel_de_read(dev_priv,
4124                                       PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
4125         } else {
4126                 pipe_config->pixel_multiplier = 1;
4127         }
4128
4129         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
4130                 tmp = intel_de_read(dev_priv, CHICKEN_TRANS(pipe_config->cpu_transcoder));
4131
4132                 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
4133         } else {
4134                 /* no idea if this is correct */
4135                 pipe_config->framestart_delay = 1;
4136         }
4137
4138 out:
4139         intel_display_power_put_all_in_set(dev_priv, &power_domain_set);
4140
4141         return active;
4142 }
4143
4144 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
4145 {
4146         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4147         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4148
4149         if (!i915->display->get_pipe_config(crtc, crtc_state))
4150                 return false;
4151
4152         crtc_state->hw.active = true;
4153
4154         intel_crtc_readout_derived_state(crtc_state);
4155
4156         return true;
4157 }
4158
4159 /* VESA 640x480x72Hz mode to set on the pipe */
4160 static const struct drm_display_mode load_detect_mode = {
4161         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4162                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4163 };
4164
4165 static int intel_modeset_disable_planes(struct drm_atomic_state *state,
4166                                         struct drm_crtc *crtc)
4167 {
4168         struct drm_plane *plane;
4169         struct drm_plane_state *plane_state;
4170         int ret, i;
4171
4172         ret = drm_atomic_add_affected_planes(state, crtc);
4173         if (ret)
4174                 return ret;
4175
4176         for_each_new_plane_in_state(state, plane, plane_state, i) {
4177                 if (plane_state->crtc != crtc)
4178                         continue;
4179
4180                 ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
4181                 if (ret)
4182                         return ret;
4183
4184                 drm_atomic_set_fb_for_plane(plane_state, NULL);
4185         }
4186
4187         return 0;
4188 }
4189
4190 int intel_get_load_detect_pipe(struct drm_connector *connector,
4191                                struct intel_load_detect_pipe *old,
4192                                struct drm_modeset_acquire_ctx *ctx)
4193 {
4194         struct intel_encoder *encoder =
4195                 intel_attached_encoder(to_intel_connector(connector));
4196         struct intel_crtc *possible_crtc;
4197         struct intel_crtc *crtc = NULL;
4198         struct drm_device *dev = encoder->base.dev;
4199         struct drm_i915_private *dev_priv = to_i915(dev);
4200         struct drm_mode_config *config = &dev->mode_config;
4201         struct drm_atomic_state *state = NULL, *restore_state = NULL;
4202         struct drm_connector_state *connector_state;
4203         struct intel_crtc_state *crtc_state;
4204         int ret;
4205
4206         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4207                     connector->base.id, connector->name,
4208                     encoder->base.base.id, encoder->base.name);
4209
4210         old->restore_state = NULL;
4211
4212         drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex));
4213
4214         /*
4215          * Algorithm gets a little messy:
4216          *
4217          *   - if the connector already has an assigned crtc, use it (but make
4218          *     sure it's on first)
4219          *
4220          *   - try to find the first unused crtc that can drive this connector,
4221          *     and use that if we find one
4222          */
4223
4224         /* See if we already have a CRTC for this connector */
4225         if (connector->state->crtc) {
4226                 crtc = to_intel_crtc(connector->state->crtc);
4227
4228                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4229                 if (ret)
4230                         goto fail;
4231
4232                 /* Make sure the crtc and connector are running */
4233                 goto found;
4234         }
4235
4236         /* Find an unused one (if possible) */
4237         for_each_intel_crtc(dev, possible_crtc) {
4238                 if (!(encoder->base.possible_crtcs &
4239                       drm_crtc_mask(&possible_crtc->base)))
4240                         continue;
4241
4242                 ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx);
4243                 if (ret)
4244                         goto fail;
4245
4246                 if (possible_crtc->base.state->enable) {
4247                         drm_modeset_unlock(&possible_crtc->base.mutex);
4248                         continue;
4249                 }
4250
4251                 crtc = possible_crtc;
4252                 break;
4253         }
4254
4255         /*
4256          * If we didn't find an unused CRTC, don't use any.
4257          */
4258         if (!crtc) {
4259                 drm_dbg_kms(&dev_priv->drm,
4260                             "no pipe available for load-detect\n");
4261                 ret = -ENODEV;
4262                 goto fail;
4263         }
4264
4265 found:
4266         state = drm_atomic_state_alloc(dev);
4267         restore_state = drm_atomic_state_alloc(dev);
4268         if (!state || !restore_state) {
4269                 ret = -ENOMEM;
4270                 goto fail;
4271         }
4272
4273         state->acquire_ctx = ctx;
4274         restore_state->acquire_ctx = ctx;
4275
4276         connector_state = drm_atomic_get_connector_state(state, connector);
4277         if (IS_ERR(connector_state)) {
4278                 ret = PTR_ERR(connector_state);
4279                 goto fail;
4280         }
4281
4282         ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base);
4283         if (ret)
4284                 goto fail;
4285
4286         crtc_state = intel_atomic_get_crtc_state(state, crtc);
4287         if (IS_ERR(crtc_state)) {
4288                 ret = PTR_ERR(crtc_state);
4289                 goto fail;
4290         }
4291
4292         crtc_state->uapi.active = true;
4293
4294         ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi,
4295                                            &load_detect_mode);
4296         if (ret)
4297                 goto fail;
4298
4299         ret = intel_modeset_disable_planes(state, &crtc->base);
4300         if (ret)
4301                 goto fail;
4302
4303         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
4304         if (!ret)
4305                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, &crtc->base));
4306         if (!ret)
4307                 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base);
4308         if (ret) {
4309                 drm_dbg_kms(&dev_priv->drm,
4310                             "Failed to create a copy of old state to restore: %i\n",
4311                             ret);
4312                 goto fail;
4313         }
4314
4315         ret = drm_atomic_commit(state);
4316         if (ret) {
4317                 drm_dbg_kms(&dev_priv->drm,
4318                             "failed to set mode on load-detect pipe\n");
4319                 goto fail;
4320         }
4321
4322         old->restore_state = restore_state;
4323         drm_atomic_state_put(state);
4324
4325         /* let the connector get through one full cycle before testing */
4326         intel_crtc_wait_for_next_vblank(crtc);
4327
4328         return true;
4329
4330 fail:
4331         if (state) {
4332                 drm_atomic_state_put(state);
4333                 state = NULL;
4334         }
4335         if (restore_state) {
4336                 drm_atomic_state_put(restore_state);
4337                 restore_state = NULL;
4338         }
4339
4340         if (ret == -EDEADLK)
4341                 return ret;
4342
4343         return false;
4344 }
4345
4346 void intel_release_load_detect_pipe(struct drm_connector *connector,
4347                                     struct intel_load_detect_pipe *old,
4348                                     struct drm_modeset_acquire_ctx *ctx)
4349 {
4350         struct intel_encoder *intel_encoder =
4351                 intel_attached_encoder(to_intel_connector(connector));
4352         struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev);
4353         struct drm_encoder *encoder = &intel_encoder->base;
4354         struct drm_atomic_state *state = old->restore_state;
4355         int ret;
4356
4357         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4358                     connector->base.id, connector->name,
4359                     encoder->base.id, encoder->name);
4360
4361         if (!state)
4362                 return;
4363
4364         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4365         if (ret)
4366                 drm_dbg_kms(&i915->drm,
4367                             "Couldn't release load detect pipe: %i\n", ret);
4368         drm_atomic_state_put(state);
4369 }
4370
4371 static int i9xx_pll_refclk(struct drm_device *dev,
4372                            const struct intel_crtc_state *pipe_config)
4373 {
4374         struct drm_i915_private *dev_priv = to_i915(dev);
4375         u32 dpll = pipe_config->dpll_hw_state.dpll;
4376
4377         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
4378                 return dev_priv->vbt.lvds_ssc_freq;
4379         else if (HAS_PCH_SPLIT(dev_priv))
4380                 return 120000;
4381         else if (DISPLAY_VER(dev_priv) != 2)
4382                 return 96000;
4383         else
4384                 return 48000;
4385 }
4386
4387 /* Returns the clock of the currently programmed mode of the given pipe. */
4388 void i9xx_crtc_clock_get(struct intel_crtc *crtc,
4389                          struct intel_crtc_state *pipe_config)
4390 {
4391         struct drm_device *dev = crtc->base.dev;
4392         struct drm_i915_private *dev_priv = to_i915(dev);
4393         u32 dpll = pipe_config->dpll_hw_state.dpll;
4394         u32 fp;
4395         struct dpll clock;
4396         int port_clock;
4397         int refclk = i9xx_pll_refclk(dev, pipe_config);
4398
4399         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4400                 fp = pipe_config->dpll_hw_state.fp0;
4401         else
4402                 fp = pipe_config->dpll_hw_state.fp1;
4403
4404         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4405         if (IS_PINEVIEW(dev_priv)) {
4406                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4407                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4408         } else {
4409                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4410                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4411         }
4412
4413         if (DISPLAY_VER(dev_priv) != 2) {
4414                 if (IS_PINEVIEW(dev_priv))
4415                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4416                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4417                 else
4418                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4419                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4420
4421                 switch (dpll & DPLL_MODE_MASK) {
4422                 case DPLLB_MODE_DAC_SERIAL:
4423                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4424                                 5 : 10;
4425                         break;
4426                 case DPLLB_MODE_LVDS:
4427                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4428                                 7 : 14;
4429                         break;
4430                 default:
4431                         drm_dbg_kms(&dev_priv->drm,
4432                                     "Unknown DPLL mode %08x in programmed "
4433                                     "mode\n", (int)(dpll & DPLL_MODE_MASK));
4434                         return;
4435                 }
4436
4437                 if (IS_PINEVIEW(dev_priv))
4438                         port_clock = pnv_calc_dpll_params(refclk, &clock);
4439                 else
4440                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
4441         } else {
4442                 enum pipe lvds_pipe;
4443
4444                 if (IS_I85X(dev_priv) &&
4445                     intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) &&
4446                     lvds_pipe == crtc->pipe) {
4447                         u32 lvds = intel_de_read(dev_priv, LVDS);
4448
4449                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4450                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4451
4452                         if (lvds & LVDS_CLKB_POWER_UP)
4453                                 clock.p2 = 7;
4454                         else
4455                                 clock.p2 = 14;
4456                 } else {
4457                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4458                                 clock.p1 = 2;
4459                         else {
4460                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4461                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4462                         }
4463                         if (dpll & PLL_P2_DIVIDE_BY_4)
4464                                 clock.p2 = 4;
4465                         else
4466                                 clock.p2 = 2;
4467                 }
4468
4469                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
4470         }
4471
4472         /*
4473          * This value includes pixel_multiplier. We will use
4474          * port_clock to compute adjusted_mode.crtc_clock in the
4475          * encoder's get_config() function.
4476          */
4477         pipe_config->port_clock = port_clock;
4478 }
4479
4480 int intel_dotclock_calculate(int link_freq,
4481                              const struct intel_link_m_n *m_n)
4482 {
4483         /*
4484          * The calculation for the data clock is:
4485          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
4486          * But we want to avoid losing precison if possible, so:
4487          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
4488          *
4489          * and the link clock is simpler:
4490          * link_clock = (m * link_clock) / n
4491          */
4492
4493         if (!m_n->link_n)
4494                 return 0;
4495
4496         return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
4497 }
4498
4499 /* Returns the currently programmed mode of the given encoder. */
4500 struct drm_display_mode *
4501 intel_encoder_current_mode(struct intel_encoder *encoder)
4502 {
4503         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4504         struct intel_crtc_state *crtc_state;
4505         struct drm_display_mode *mode;
4506         struct intel_crtc *crtc;
4507         enum pipe pipe;
4508
4509         if (!encoder->get_hw_state(encoder, &pipe))
4510                 return NULL;
4511
4512         crtc = intel_crtc_for_pipe(dev_priv, pipe);
4513
4514         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4515         if (!mode)
4516                 return NULL;
4517
4518         crtc_state = intel_crtc_state_alloc(crtc);
4519         if (!crtc_state) {
4520                 kfree(mode);
4521                 return NULL;
4522         }
4523
4524         if (!intel_crtc_get_pipe_config(crtc_state)) {
4525                 kfree(crtc_state);
4526                 kfree(mode);
4527                 return NULL;
4528         }
4529
4530         intel_encoder_get_config(encoder, crtc_state);
4531
4532         intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
4533
4534         kfree(crtc_state);
4535
4536         return mode;
4537 }
4538
4539 static bool encoders_cloneable(const struct intel_encoder *a,
4540                                const struct intel_encoder *b)
4541 {
4542         /* masks could be asymmetric, so check both ways */
4543         return a == b || (a->cloneable & (1 << b->type) &&
4544                           b->cloneable & (1 << a->type));
4545 }
4546
4547 static bool check_single_encoder_cloning(struct intel_atomic_state *state,
4548                                          struct intel_crtc *crtc,
4549                                          struct intel_encoder *encoder)
4550 {
4551         struct intel_encoder *source_encoder;
4552         struct drm_connector *connector;
4553         struct drm_connector_state *connector_state;
4554         int i;
4555
4556         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4557                 if (connector_state->crtc != &crtc->base)
4558                         continue;
4559
4560                 source_encoder =
4561                         to_intel_encoder(connector_state->best_encoder);
4562                 if (!encoders_cloneable(encoder, source_encoder))
4563                         return false;
4564         }
4565
4566         return true;
4567 }
4568
4569 static int icl_add_linked_planes(struct intel_atomic_state *state)
4570 {
4571         struct intel_plane *plane, *linked;
4572         struct intel_plane_state *plane_state, *linked_plane_state;
4573         int i;
4574
4575         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4576                 linked = plane_state->planar_linked_plane;
4577
4578                 if (!linked)
4579                         continue;
4580
4581                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
4582                 if (IS_ERR(linked_plane_state))
4583                         return PTR_ERR(linked_plane_state);
4584
4585                 drm_WARN_ON(state->base.dev,
4586                             linked_plane_state->planar_linked_plane != plane);
4587                 drm_WARN_ON(state->base.dev,
4588                             linked_plane_state->planar_slave == plane_state->planar_slave);
4589         }
4590
4591         return 0;
4592 }
4593
4594 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
4595 {
4596         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4597         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4598         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
4599         struct intel_plane *plane, *linked;
4600         struct intel_plane_state *plane_state;
4601         int i;
4602
4603         if (DISPLAY_VER(dev_priv) < 11)
4604                 return 0;
4605
4606         /*
4607          * Destroy all old plane links and make the slave plane invisible
4608          * in the crtc_state->active_planes mask.
4609          */
4610         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4611                 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
4612                         continue;
4613
4614                 plane_state->planar_linked_plane = NULL;
4615                 if (plane_state->planar_slave && !plane_state->uapi.visible) {
4616                         crtc_state->enabled_planes &= ~BIT(plane->id);
4617                         crtc_state->active_planes &= ~BIT(plane->id);
4618                         crtc_state->update_planes |= BIT(plane->id);
4619                         crtc_state->data_rate[plane->id] = 0;
4620                         crtc_state->rel_data_rate[plane->id] = 0;
4621                 }
4622
4623                 plane_state->planar_slave = false;
4624         }
4625
4626         if (!crtc_state->nv12_planes)
4627                 return 0;
4628
4629         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4630                 struct intel_plane_state *linked_state = NULL;
4631
4632                 if (plane->pipe != crtc->pipe ||
4633                     !(crtc_state->nv12_planes & BIT(plane->id)))
4634                         continue;
4635
4636                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
4637                         if (!icl_is_nv12_y_plane(dev_priv, linked->id))
4638                                 continue;
4639
4640                         if (crtc_state->active_planes & BIT(linked->id))
4641                                 continue;
4642
4643                         linked_state = intel_atomic_get_plane_state(state, linked);
4644                         if (IS_ERR(linked_state))
4645                                 return PTR_ERR(linked_state);
4646
4647                         break;
4648                 }
4649
4650                 if (!linked_state) {
4651                         drm_dbg_kms(&dev_priv->drm,
4652                                     "Need %d free Y planes for planar YUV\n",
4653                                     hweight8(crtc_state->nv12_planes));
4654
4655                         return -EINVAL;
4656                 }
4657
4658                 plane_state->planar_linked_plane = linked;
4659
4660                 linked_state->planar_slave = true;
4661                 linked_state->planar_linked_plane = plane;
4662                 crtc_state->enabled_planes |= BIT(linked->id);
4663                 crtc_state->active_planes |= BIT(linked->id);
4664                 crtc_state->update_planes |= BIT(linked->id);
4665                 crtc_state->data_rate[linked->id] =
4666                         crtc_state->data_rate_y[plane->id];
4667                 crtc_state->rel_data_rate[linked->id] =
4668                         crtc_state->rel_data_rate_y[plane->id];
4669                 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
4670                             linked->base.name, plane->base.name);
4671
4672                 /* Copy parameters to slave plane */
4673                 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
4674                 linked_state->color_ctl = plane_state->color_ctl;
4675                 linked_state->view = plane_state->view;
4676                 linked_state->decrypt = plane_state->decrypt;
4677
4678                 intel_plane_copy_hw_state(linked_state, plane_state);
4679                 linked_state->uapi.src = plane_state->uapi.src;
4680                 linked_state->uapi.dst = plane_state->uapi.dst;
4681
4682                 if (icl_is_hdr_plane(dev_priv, plane->id)) {
4683                         if (linked->id == PLANE_SPRITE5)
4684                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
4685                         else if (linked->id == PLANE_SPRITE4)
4686                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
4687                         else if (linked->id == PLANE_SPRITE3)
4688                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
4689                         else if (linked->id == PLANE_SPRITE2)
4690                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
4691                         else
4692                                 MISSING_CASE(linked->id);
4693                 }
4694         }
4695
4696         return 0;
4697 }
4698
4699 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
4700 {
4701         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
4702         struct intel_atomic_state *state =
4703                 to_intel_atomic_state(new_crtc_state->uapi.state);
4704         const struct intel_crtc_state *old_crtc_state =
4705                 intel_atomic_get_old_crtc_state(state, crtc);
4706
4707         return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
4708 }
4709
4710 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
4711 {
4712         const struct drm_display_mode *pipe_mode =
4713                 &crtc_state->hw.pipe_mode;
4714         int linetime_wm;
4715
4716         if (!crtc_state->hw.enable)
4717                 return 0;
4718
4719         linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4720                                         pipe_mode->crtc_clock);
4721
4722         return min(linetime_wm, 0x1ff);
4723 }
4724
4725 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
4726                                const struct intel_cdclk_state *cdclk_state)
4727 {
4728         const struct drm_display_mode *pipe_mode =
4729                 &crtc_state->hw.pipe_mode;
4730         int linetime_wm;
4731
4732         if (!crtc_state->hw.enable)
4733                 return 0;
4734
4735         linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4736                                         cdclk_state->logical.cdclk);
4737
4738         return min(linetime_wm, 0x1ff);
4739 }
4740
4741 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
4742 {
4743         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4744         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4745         const struct drm_display_mode *pipe_mode =
4746                 &crtc_state->hw.pipe_mode;
4747         int linetime_wm;
4748
4749         if (!crtc_state->hw.enable)
4750                 return 0;
4751
4752         linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
4753                                    crtc_state->pixel_rate);
4754
4755         /* Display WA #1135: BXT:ALL GLK:ALL */
4756         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
4757             dev_priv->ipc_enabled)
4758                 linetime_wm /= 2;
4759
4760         return min(linetime_wm, 0x1ff);
4761 }
4762
4763 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
4764                                    struct intel_crtc *crtc)
4765 {
4766         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4767         struct intel_crtc_state *crtc_state =
4768                 intel_atomic_get_new_crtc_state(state, crtc);
4769         const struct intel_cdclk_state *cdclk_state;
4770
4771         if (DISPLAY_VER(dev_priv) >= 9)
4772                 crtc_state->linetime = skl_linetime_wm(crtc_state);
4773         else
4774                 crtc_state->linetime = hsw_linetime_wm(crtc_state);
4775
4776         if (!hsw_crtc_supports_ips(crtc))
4777                 return 0;
4778
4779         cdclk_state = intel_atomic_get_cdclk_state(state);
4780         if (IS_ERR(cdclk_state))
4781                 return PTR_ERR(cdclk_state);
4782
4783         crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
4784                                                        cdclk_state);
4785
4786         return 0;
4787 }
4788
4789 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
4790                                    struct intel_crtc *crtc)
4791 {
4792         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4793         struct intel_crtc_state *crtc_state =
4794                 intel_atomic_get_new_crtc_state(state, crtc);
4795         bool mode_changed = intel_crtc_needs_modeset(crtc_state);
4796         int ret;
4797
4798         if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) &&
4799             mode_changed && !crtc_state->hw.active)
4800                 crtc_state->update_wm_post = true;
4801
4802         if (mode_changed) {
4803                 ret = intel_dpll_crtc_compute_clock(state, crtc);
4804                 if (ret)
4805                         return ret;
4806
4807                 ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
4808                 if (ret)
4809                         return ret;
4810         }
4811
4812         /*
4813          * May need to update pipe gamma enable bits
4814          * when C8 planes are getting enabled/disabled.
4815          */
4816         if (c8_planes_changed(crtc_state))
4817                 crtc_state->uapi.color_mgmt_changed = true;
4818
4819         if (mode_changed || crtc_state->update_pipe ||
4820             crtc_state->uapi.color_mgmt_changed) {
4821                 ret = intel_color_check(crtc_state);
4822                 if (ret)
4823                         return ret;
4824         }
4825
4826         ret = intel_compute_pipe_wm(state, crtc);
4827         if (ret) {
4828                 drm_dbg_kms(&dev_priv->drm,
4829                             "Target pipe watermarks are invalid\n");
4830                 return ret;
4831         }
4832
4833         /*
4834          * Calculate 'intermediate' watermarks that satisfy both the
4835          * old state and the new state.  We can program these
4836          * immediately.
4837          */
4838         ret = intel_compute_intermediate_wm(state, crtc);
4839         if (ret) {
4840                 drm_dbg_kms(&dev_priv->drm,
4841                             "No valid intermediate pipe watermarks are possible\n");
4842                 return ret;
4843         }
4844
4845         if (DISPLAY_VER(dev_priv) >= 9) {
4846                 if (mode_changed || crtc_state->update_pipe) {
4847                         ret = skl_update_scaler_crtc(crtc_state);
4848                         if (ret)
4849                                 return ret;
4850                 }
4851
4852                 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
4853                 if (ret)
4854                         return ret;
4855         }
4856
4857         if (HAS_IPS(dev_priv)) {
4858                 ret = hsw_ips_compute_config(state, crtc);
4859                 if (ret)
4860                         return ret;
4861         }
4862
4863         if (DISPLAY_VER(dev_priv) >= 9 ||
4864             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4865                 ret = hsw_compute_linetime_wm(state, crtc);
4866                 if (ret)
4867                         return ret;
4868
4869         }
4870
4871         ret = intel_psr2_sel_fetch_update(state, crtc);
4872         if (ret)
4873                 return ret;
4874
4875         return 0;
4876 }
4877
4878 static int
4879 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
4880                       struct intel_crtc_state *crtc_state)
4881 {
4882         struct drm_connector *connector = conn_state->connector;
4883         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
4884         const struct drm_display_info *info = &connector->display_info;
4885         int bpp;
4886
4887         switch (conn_state->max_bpc) {
4888         case 6 ... 7:
4889                 bpp = 6 * 3;
4890                 break;
4891         case 8 ... 9:
4892                 bpp = 8 * 3;
4893                 break;
4894         case 10 ... 11:
4895                 bpp = 10 * 3;
4896                 break;
4897         case 12 ... 16:
4898                 bpp = 12 * 3;
4899                 break;
4900         default:
4901                 MISSING_CASE(conn_state->max_bpc);
4902                 return -EINVAL;
4903         }
4904
4905         if (bpp < crtc_state->pipe_bpp) {
4906                 drm_dbg_kms(&i915->drm,
4907                             "[CONNECTOR:%d:%s] Limiting display bpp to %d "
4908                             "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
4909                             connector->base.id, connector->name,
4910                             bpp, 3 * info->bpc,
4911                             3 * conn_state->max_requested_bpc,
4912                             crtc_state->pipe_bpp);
4913
4914                 crtc_state->pipe_bpp = bpp;
4915         }
4916
4917         return 0;
4918 }
4919
4920 static int
4921 compute_baseline_pipe_bpp(struct intel_atomic_state *state,
4922                           struct intel_crtc *crtc)
4923 {
4924         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4925         struct intel_crtc_state *crtc_state =
4926                 intel_atomic_get_new_crtc_state(state, crtc);
4927         struct drm_connector *connector;
4928         struct drm_connector_state *connector_state;
4929         int bpp, i;
4930
4931         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
4932             IS_CHERRYVIEW(dev_priv)))
4933                 bpp = 10*3;
4934         else if (DISPLAY_VER(dev_priv) >= 5)
4935                 bpp = 12*3;
4936         else
4937                 bpp = 8*3;
4938
4939         crtc_state->pipe_bpp = bpp;
4940
4941         /* Clamp display bpp to connector max bpp */
4942         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4943                 int ret;
4944
4945                 if (connector_state->crtc != &crtc->base)
4946                         continue;
4947
4948                 ret = compute_sink_pipe_bpp(connector_state, crtc_state);
4949                 if (ret)
4950                         return ret;
4951         }
4952
4953         return 0;
4954 }
4955
4956 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
4957 {
4958         struct drm_device *dev = state->base.dev;
4959         struct drm_connector *connector;
4960         struct drm_connector_list_iter conn_iter;
4961         unsigned int used_ports = 0;
4962         unsigned int used_mst_ports = 0;
4963         bool ret = true;
4964
4965         /*
4966          * We're going to peek into connector->state,
4967          * hence connection_mutex must be held.
4968          */
4969         drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
4970
4971         /*
4972          * Walk the connector list instead of the encoder
4973          * list to detect the problem on ddi platforms
4974          * where there's just one encoder per digital port.
4975          */
4976         drm_connector_list_iter_begin(dev, &conn_iter);
4977         drm_for_each_connector_iter(connector, &conn_iter) {
4978                 struct drm_connector_state *connector_state;
4979                 struct intel_encoder *encoder;
4980
4981                 connector_state =
4982                         drm_atomic_get_new_connector_state(&state->base,
4983                                                            connector);
4984                 if (!connector_state)
4985                         connector_state = connector->state;
4986
4987                 if (!connector_state->best_encoder)
4988                         continue;
4989
4990                 encoder = to_intel_encoder(connector_state->best_encoder);
4991
4992                 drm_WARN_ON(dev, !connector_state->crtc);
4993
4994                 switch (encoder->type) {
4995                 case INTEL_OUTPUT_DDI:
4996                         if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
4997                                 break;
4998                         fallthrough;
4999                 case INTEL_OUTPUT_DP:
5000                 case INTEL_OUTPUT_HDMI:
5001                 case INTEL_OUTPUT_EDP:
5002                         /* the same port mustn't appear more than once */
5003                         if (used_ports & BIT(encoder->port))
5004                                 ret = false;
5005
5006                         used_ports |= BIT(encoder->port);
5007                         break;
5008                 case INTEL_OUTPUT_DP_MST:
5009                         used_mst_ports |=
5010                                 1 << encoder->port;
5011                         break;
5012                 default:
5013                         break;
5014                 }
5015         }
5016         drm_connector_list_iter_end(&conn_iter);
5017
5018         /* can't mix MST and SST/HDMI on the same port */
5019         if (used_ports & used_mst_ports)
5020                 return false;
5021
5022         return ret;
5023 }
5024
5025 static void
5026 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
5027                                            struct intel_crtc *crtc)
5028 {
5029         struct intel_crtc_state *crtc_state =
5030                 intel_atomic_get_new_crtc_state(state, crtc);
5031
5032         WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
5033
5034         drm_property_replace_blob(&crtc_state->hw.degamma_lut,
5035                                   crtc_state->uapi.degamma_lut);
5036         drm_property_replace_blob(&crtc_state->hw.gamma_lut,
5037                                   crtc_state->uapi.gamma_lut);
5038         drm_property_replace_blob(&crtc_state->hw.ctm,
5039                                   crtc_state->uapi.ctm);
5040 }
5041
5042 static void
5043 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
5044                                          struct intel_crtc *crtc)
5045 {
5046         struct intel_crtc_state *crtc_state =
5047                 intel_atomic_get_new_crtc_state(state, crtc);
5048
5049         WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
5050
5051         crtc_state->hw.enable = crtc_state->uapi.enable;
5052         crtc_state->hw.active = crtc_state->uapi.active;
5053         drm_mode_copy(&crtc_state->hw.mode,
5054                       &crtc_state->uapi.mode);
5055         drm_mode_copy(&crtc_state->hw.adjusted_mode,
5056                       &crtc_state->uapi.adjusted_mode);
5057         crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
5058
5059         intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
5060 }
5061
5062 static void
5063 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state,
5064                                     struct intel_crtc *slave_crtc)
5065 {
5066         struct intel_crtc_state *slave_crtc_state =
5067                 intel_atomic_get_new_crtc_state(state, slave_crtc);
5068         struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
5069         const struct intel_crtc_state *master_crtc_state =
5070                 intel_atomic_get_new_crtc_state(state, master_crtc);
5071
5072         drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut,
5073                                   master_crtc_state->hw.degamma_lut);
5074         drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut,
5075                                   master_crtc_state->hw.gamma_lut);
5076         drm_property_replace_blob(&slave_crtc_state->hw.ctm,
5077                                   master_crtc_state->hw.ctm);
5078
5079         slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed;
5080 }
5081
5082 static int
5083 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state,
5084                                   struct intel_crtc *slave_crtc)
5085 {
5086         struct intel_crtc_state *slave_crtc_state =
5087                 intel_atomic_get_new_crtc_state(state, slave_crtc);
5088         struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
5089         const struct intel_crtc_state *master_crtc_state =
5090                 intel_atomic_get_new_crtc_state(state, master_crtc);
5091         struct intel_crtc_state *saved_state;
5092
5093         WARN_ON(master_crtc_state->bigjoiner_pipes !=
5094                 slave_crtc_state->bigjoiner_pipes);
5095
5096         saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL);
5097         if (!saved_state)
5098                 return -ENOMEM;
5099
5100         /* preserve some things from the slave's original crtc state */
5101         saved_state->uapi = slave_crtc_state->uapi;
5102         saved_state->scaler_state = slave_crtc_state->scaler_state;
5103         saved_state->shared_dpll = slave_crtc_state->shared_dpll;
5104         saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state;
5105         saved_state->crc_enabled = slave_crtc_state->crc_enabled;
5106
5107         intel_crtc_free_hw_state(slave_crtc_state);
5108         memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state));
5109         kfree(saved_state);
5110
5111         /* Re-init hw state */
5112         memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw));
5113         slave_crtc_state->hw.enable = master_crtc_state->hw.enable;
5114         slave_crtc_state->hw.active = master_crtc_state->hw.active;
5115         drm_mode_copy(&slave_crtc_state->hw.mode,
5116                       &master_crtc_state->hw.mode);
5117         drm_mode_copy(&slave_crtc_state->hw.pipe_mode,
5118                       &master_crtc_state->hw.pipe_mode);
5119         drm_mode_copy(&slave_crtc_state->hw.adjusted_mode,
5120                       &master_crtc_state->hw.adjusted_mode);
5121         slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter;
5122
5123         copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc);
5124
5125         slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed;
5126         slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed;
5127         slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed;
5128
5129         WARN_ON(master_crtc_state->bigjoiner_pipes !=
5130                 slave_crtc_state->bigjoiner_pipes);
5131
5132         return 0;
5133 }
5134
5135 static int
5136 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
5137                                  struct intel_crtc *crtc)
5138 {
5139         struct intel_crtc_state *crtc_state =
5140                 intel_atomic_get_new_crtc_state(state, crtc);
5141         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5142         struct intel_crtc_state *saved_state;
5143
5144         saved_state = intel_crtc_state_alloc(crtc);
5145         if (!saved_state)
5146                 return -ENOMEM;
5147
5148         /* free the old crtc_state->hw members */
5149         intel_crtc_free_hw_state(crtc_state);
5150
5151         /* FIXME: before the switch to atomic started, a new pipe_config was
5152          * kzalloc'd. Code that depends on any field being zero should be
5153          * fixed, so that the crtc_state can be safely duplicated. For now,
5154          * only fields that are know to not cause problems are preserved. */
5155
5156         saved_state->uapi = crtc_state->uapi;
5157         saved_state->scaler_state = crtc_state->scaler_state;
5158         saved_state->shared_dpll = crtc_state->shared_dpll;
5159         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
5160         memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
5161                sizeof(saved_state->icl_port_dplls));
5162         saved_state->crc_enabled = crtc_state->crc_enabled;
5163         if (IS_G4X(dev_priv) ||
5164             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5165                 saved_state->wm = crtc_state->wm;
5166
5167         memcpy(crtc_state, saved_state, sizeof(*crtc_state));
5168         kfree(saved_state);
5169
5170         intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc);
5171
5172         return 0;
5173 }
5174
5175 static int
5176 intel_modeset_pipe_config(struct intel_atomic_state *state,
5177                           struct intel_crtc *crtc)
5178 {
5179         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5180         struct intel_crtc_state *crtc_state =
5181                 intel_atomic_get_new_crtc_state(state, crtc);
5182         struct drm_connector *connector;
5183         struct drm_connector_state *connector_state;
5184         int pipe_src_w, pipe_src_h;
5185         int base_bpp, ret, i;
5186         bool retry = true;
5187
5188         crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
5189
5190         crtc_state->framestart_delay = 1;
5191
5192         /*
5193          * Sanitize sync polarity flags based on requested ones. If neither
5194          * positive or negative polarity is requested, treat this as meaning
5195          * negative polarity.
5196          */
5197         if (!(crtc_state->hw.adjusted_mode.flags &
5198               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
5199                 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
5200
5201         if (!(crtc_state->hw.adjusted_mode.flags &
5202               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
5203                 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
5204
5205         ret = compute_baseline_pipe_bpp(state, crtc);
5206         if (ret)
5207                 return ret;
5208
5209         base_bpp = crtc_state->pipe_bpp;
5210
5211         /*
5212          * Determine the real pipe dimensions. Note that stereo modes can
5213          * increase the actual pipe size due to the frame doubling and
5214          * insertion of additional space for blanks between the frame. This
5215          * is stored in the crtc timings. We use the requested mode to do this
5216          * computation to clearly distinguish it from the adjusted mode, which
5217          * can be changed by the connectors in the below retry loop.
5218          */
5219         drm_mode_get_hv_timing(&crtc_state->hw.mode,
5220                                &pipe_src_w, &pipe_src_h);
5221         drm_rect_init(&crtc_state->pipe_src, 0, 0,
5222                       pipe_src_w, pipe_src_h);
5223
5224         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5225                 struct intel_encoder *encoder =
5226                         to_intel_encoder(connector_state->best_encoder);
5227
5228                 if (connector_state->crtc != &crtc->base)
5229                         continue;
5230
5231                 if (!check_single_encoder_cloning(state, crtc, encoder)) {
5232                         drm_dbg_kms(&i915->drm,
5233                                     "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
5234                                     encoder->base.base.id, encoder->base.name);
5235                         return -EINVAL;
5236                 }
5237
5238                 /*
5239                  * Determine output_types before calling the .compute_config()
5240                  * hooks so that the hooks can use this information safely.
5241                  */
5242                 if (encoder->compute_output_type)
5243                         crtc_state->output_types |=
5244                                 BIT(encoder->compute_output_type(encoder, crtc_state,
5245                                                                  connector_state));
5246                 else
5247                         crtc_state->output_types |= BIT(encoder->type);
5248         }
5249
5250 encoder_retry:
5251         /* Ensure the port clock defaults are reset when retrying. */
5252         crtc_state->port_clock = 0;
5253         crtc_state->pixel_multiplier = 1;
5254
5255         /* Fill in default crtc timings, allow encoders to overwrite them. */
5256         drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,
5257                               CRTC_STEREO_DOUBLE);
5258
5259         /* Pass our mode to the connectors and the CRTC to give them a chance to
5260          * adjust it according to limitations or connector properties, and also
5261          * a chance to reject the mode entirely.
5262          */
5263         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
5264                 struct intel_encoder *encoder =
5265                         to_intel_encoder(connector_state->best_encoder);
5266
5267                 if (connector_state->crtc != &crtc->base)
5268                         continue;
5269
5270                 ret = encoder->compute_config(encoder, crtc_state,
5271                                               connector_state);
5272                 if (ret == -EDEADLK)
5273                         return ret;
5274                 if (ret < 0) {
5275                         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n",
5276                                     encoder->base.base.id, encoder->base.name, ret);
5277                         return ret;
5278                 }
5279         }
5280
5281         /* Set default port clock if not overwritten by the encoder. Needs to be
5282          * done afterwards in case the encoder adjusts the mode. */
5283         if (!crtc_state->port_clock)
5284                 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
5285                         * crtc_state->pixel_multiplier;
5286
5287         ret = intel_crtc_compute_config(state, crtc);
5288         if (ret == -EDEADLK)
5289                 return ret;
5290         if (ret == -EAGAIN) {
5291                 if (drm_WARN(&i915->drm, !retry,
5292                              "[CRTC:%d:%s] loop in pipe configuration computation\n",
5293                              crtc->base.base.id, crtc->base.name))
5294                         return -EINVAL;
5295
5296                 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n",
5297                             crtc->base.base.id, crtc->base.name);
5298                 retry = false;
5299                 goto encoder_retry;
5300         }
5301         if (ret < 0) {
5302                 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
5303                             crtc->base.base.id, crtc->base.name, ret);
5304                 return ret;
5305         }
5306
5307         /* Dithering seems to not pass-through bits correctly when it should, so
5308          * only enable it on 6bpc panels and when its not a compliance
5309          * test requesting 6bpc video pattern.
5310          */
5311         crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
5312                 !crtc_state->dither_force_disable;
5313         drm_dbg_kms(&i915->drm,
5314                     "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
5315                     crtc->base.base.id, crtc->base.name,
5316                     base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
5317
5318         return 0;
5319 }
5320
5321 static int
5322 intel_modeset_pipe_config_late(struct intel_atomic_state *state,
5323                                struct intel_crtc *crtc)
5324 {
5325         struct intel_crtc_state *crtc_state =
5326                 intel_atomic_get_new_crtc_state(state, crtc);
5327         struct drm_connector_state *conn_state;
5328         struct drm_connector *connector;
5329         int i;
5330
5331         intel_bigjoiner_adjust_pipe_src(crtc_state);
5332
5333         for_each_new_connector_in_state(&state->base, connector,
5334                                         conn_state, i) {
5335                 struct intel_encoder *encoder =
5336                         to_intel_encoder(conn_state->best_encoder);
5337                 int ret;
5338
5339                 if (conn_state->crtc != &crtc->base ||
5340                     !encoder->compute_config_late)
5341                         continue;
5342
5343                 ret = encoder->compute_config_late(encoder, crtc_state,
5344                                                    conn_state);
5345                 if (ret)
5346                         return ret;
5347         }
5348
5349         return 0;
5350 }
5351
5352 bool intel_fuzzy_clock_check(int clock1, int clock2)
5353 {
5354         int diff;
5355
5356         if (clock1 == clock2)
5357                 return true;
5358
5359         if (!clock1 || !clock2)
5360                 return false;
5361
5362         diff = abs(clock1 - clock2);
5363
5364         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
5365                 return true;
5366
5367         return false;
5368 }
5369
5370 static bool
5371 intel_compare_m_n(unsigned int m, unsigned int n,
5372                   unsigned int m2, unsigned int n2,
5373                   bool exact)
5374 {
5375         if (m == m2 && n == n2)
5376                 return true;
5377
5378         if (exact || !m || !n || !m2 || !n2)
5379                 return false;
5380
5381         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
5382
5383         if (n > n2) {
5384                 while (n > n2) {
5385                         m2 <<= 1;
5386                         n2 <<= 1;
5387                 }
5388         } else if (n < n2) {
5389                 while (n < n2) {
5390                         m <<= 1;
5391                         n <<= 1;
5392                 }
5393         }
5394
5395         if (n != n2)
5396                 return false;
5397
5398         return intel_fuzzy_clock_check(m, m2);
5399 }
5400
5401 static bool
5402 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
5403                        const struct intel_link_m_n *m2_n2,
5404                        bool exact)
5405 {
5406         return m_n->tu == m2_n2->tu &&
5407                 intel_compare_m_n(m_n->data_m, m_n->data_n,
5408                                   m2_n2->data_m, m2_n2->data_n, exact) &&
5409                 intel_compare_m_n(m_n->link_m, m_n->link_n,
5410                                   m2_n2->link_m, m2_n2->link_n, exact);
5411 }
5412
5413 static bool
5414 intel_compare_infoframe(const union hdmi_infoframe *a,
5415                         const union hdmi_infoframe *b)
5416 {
5417         return memcmp(a, b, sizeof(*a)) == 0;
5418 }
5419
5420 static bool
5421 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
5422                          const struct drm_dp_vsc_sdp *b)
5423 {
5424         return memcmp(a, b, sizeof(*a)) == 0;
5425 }
5426
5427 static void
5428 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
5429                                bool fastset, const char *name,
5430                                const union hdmi_infoframe *a,
5431                                const union hdmi_infoframe *b)
5432 {
5433         if (fastset) {
5434                 if (!drm_debug_enabled(DRM_UT_KMS))
5435                         return;
5436
5437                 drm_dbg_kms(&dev_priv->drm,
5438                             "fastset mismatch in %s infoframe\n", name);
5439                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
5440                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
5441                 drm_dbg_kms(&dev_priv->drm, "found:\n");
5442                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
5443         } else {
5444                 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
5445                 drm_err(&dev_priv->drm, "expected:\n");
5446                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
5447                 drm_err(&dev_priv->drm, "found:\n");
5448                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
5449         }
5450 }
5451
5452 static void
5453 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
5454                                 bool fastset, const char *name,
5455                                 const struct drm_dp_vsc_sdp *a,
5456                                 const struct drm_dp_vsc_sdp *b)
5457 {
5458         if (fastset) {
5459                 if (!drm_debug_enabled(DRM_UT_KMS))
5460                         return;
5461
5462                 drm_dbg_kms(&dev_priv->drm,
5463                             "fastset mismatch in %s dp sdp\n", name);
5464                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
5465                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
5466                 drm_dbg_kms(&dev_priv->drm, "found:\n");
5467                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
5468         } else {
5469                 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
5470                 drm_err(&dev_priv->drm, "expected:\n");
5471                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
5472                 drm_err(&dev_priv->drm, "found:\n");
5473                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
5474         }
5475 }
5476
5477 static void __printf(4, 5)
5478 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
5479                      const char *name, const char *format, ...)
5480 {
5481         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5482         struct va_format vaf;
5483         va_list args;
5484
5485         va_start(args, format);
5486         vaf.fmt = format;
5487         vaf.va = &args;
5488
5489         if (fastset)
5490                 drm_dbg_kms(&i915->drm,
5491                             "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
5492                             crtc->base.base.id, crtc->base.name, name, &vaf);
5493         else
5494                 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
5495                         crtc->base.base.id, crtc->base.name, name, &vaf);
5496
5497         va_end(args);
5498 }
5499
5500 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
5501 {
5502         if (dev_priv->params.fastboot != -1)
5503                 return dev_priv->params.fastboot;
5504
5505         /* Enable fastboot by default on Skylake and newer */
5506         if (DISPLAY_VER(dev_priv) >= 9)
5507                 return true;
5508
5509         /* Enable fastboot by default on VLV and CHV */
5510         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5511                 return true;
5512
5513         /* Disabled by default on all others */
5514         return false;
5515 }
5516
5517 bool
5518 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
5519                           const struct intel_crtc_state *pipe_config,
5520                           bool fastset)
5521 {
5522         struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
5523         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
5524         bool ret = true;
5525         u32 bp_gamma = 0;
5526         bool fixup_inherited = fastset &&
5527                 current_config->inherited && !pipe_config->inherited;
5528
5529         if (fixup_inherited && !fastboot_enabled(dev_priv)) {
5530                 drm_dbg_kms(&dev_priv->drm,
5531                             "initial modeset and fastboot not set\n");
5532                 ret = false;
5533         }
5534
5535 #define PIPE_CONF_CHECK_X(name) do { \
5536         if (current_config->name != pipe_config->name) { \
5537                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5538                                      "(expected 0x%08x, found 0x%08x)", \
5539                                      current_config->name, \
5540                                      pipe_config->name); \
5541                 ret = false; \
5542         } \
5543 } while (0)
5544
5545 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
5546         if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
5547                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5548                                      "(expected 0x%08x, found 0x%08x)", \
5549                                      current_config->name & (mask), \
5550                                      pipe_config->name & (mask)); \
5551                 ret = false; \
5552         } \
5553 } while (0)
5554
5555 #define PIPE_CONF_CHECK_I(name) do { \
5556         if (current_config->name != pipe_config->name) { \
5557                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5558                                      "(expected %i, found %i)", \
5559                                      current_config->name, \
5560                                      pipe_config->name); \
5561                 ret = false; \
5562         } \
5563 } while (0)
5564
5565 #define PIPE_CONF_CHECK_BOOL(name) do { \
5566         if (current_config->name != pipe_config->name) { \
5567                 pipe_config_mismatch(fastset, crtc,  __stringify(name), \
5568                                      "(expected %s, found %s)", \
5569                                      str_yes_no(current_config->name), \
5570                                      str_yes_no(pipe_config->name)); \
5571                 ret = false; \
5572         } \
5573 } while (0)
5574
5575 /*
5576  * Checks state where we only read out the enabling, but not the entire
5577  * state itself (like full infoframes or ELD for audio). These states
5578  * require a full modeset on bootup to fix up.
5579  */
5580 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
5581         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
5582                 PIPE_CONF_CHECK_BOOL(name); \
5583         } else { \
5584                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5585                                      "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
5586                                      str_yes_no(current_config->name), \
5587                                      str_yes_no(pipe_config->name)); \
5588                 ret = false; \
5589         } \
5590 } while (0)
5591
5592 #define PIPE_CONF_CHECK_P(name) do { \
5593         if (current_config->name != pipe_config->name) { \
5594                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5595                                      "(expected %p, found %p)", \
5596                                      current_config->name, \
5597                                      pipe_config->name); \
5598                 ret = false; \
5599         } \
5600 } while (0)
5601
5602 #define PIPE_CONF_CHECK_M_N(name) do { \
5603         if (!intel_compare_link_m_n(&current_config->name, \
5604                                     &pipe_config->name,\
5605                                     !fastset)) { \
5606                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5607                                      "(expected tu %i data %i/%i link %i/%i, " \
5608                                      "found tu %i, data %i/%i link %i/%i)", \
5609                                      current_config->name.tu, \
5610                                      current_config->name.data_m, \
5611                                      current_config->name.data_n, \
5612                                      current_config->name.link_m, \
5613                                      current_config->name.link_n, \
5614                                      pipe_config->name.tu, \
5615                                      pipe_config->name.data_m, \
5616                                      pipe_config->name.data_n, \
5617                                      pipe_config->name.link_m, \
5618                                      pipe_config->name.link_n); \
5619                 ret = false; \
5620         } \
5621 } while (0)
5622
5623 #define PIPE_CONF_CHECK_TIMINGS(name) do { \
5624         PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
5625         PIPE_CONF_CHECK_I(name.crtc_htotal); \
5626         PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
5627         PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
5628         PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
5629         PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
5630         PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
5631         PIPE_CONF_CHECK_I(name.crtc_vtotal); \
5632         PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
5633         PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
5634         PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
5635         PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
5636 } while (0)
5637
5638 #define PIPE_CONF_CHECK_RECT(name) do { \
5639         PIPE_CONF_CHECK_I(name.x1); \
5640         PIPE_CONF_CHECK_I(name.x2); \
5641         PIPE_CONF_CHECK_I(name.y1); \
5642         PIPE_CONF_CHECK_I(name.y2); \
5643 } while (0)
5644
5645 /* This is required for BDW+ where there is only one set of registers for
5646  * switching between high and low RR.
5647  * This macro can be used whenever a comparison has to be made between one
5648  * hw state and multiple sw state variables.
5649  */
5650 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
5651         if (!intel_compare_link_m_n(&current_config->name, \
5652                                     &pipe_config->name, !fastset) && \
5653             !intel_compare_link_m_n(&current_config->alt_name, \
5654                                     &pipe_config->name, !fastset)) { \
5655                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5656                                      "(expected tu %i data %i/%i link %i/%i, " \
5657                                      "or tu %i data %i/%i link %i/%i, " \
5658                                      "found tu %i, data %i/%i link %i/%i)", \
5659                                      current_config->name.tu, \
5660                                      current_config->name.data_m, \
5661                                      current_config->name.data_n, \
5662                                      current_config->name.link_m, \
5663                                      current_config->name.link_n, \
5664                                      current_config->alt_name.tu, \
5665                                      current_config->alt_name.data_m, \
5666                                      current_config->alt_name.data_n, \
5667                                      current_config->alt_name.link_m, \
5668                                      current_config->alt_name.link_n, \
5669                                      pipe_config->name.tu, \
5670                                      pipe_config->name.data_m, \
5671                                      pipe_config->name.data_n, \
5672                                      pipe_config->name.link_m, \
5673                                      pipe_config->name.link_n); \
5674                 ret = false; \
5675         } \
5676 } while (0)
5677
5678 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
5679         if ((current_config->name ^ pipe_config->name) & (mask)) { \
5680                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5681                                      "(%x) (expected %i, found %i)", \
5682                                      (mask), \
5683                                      current_config->name & (mask), \
5684                                      pipe_config->name & (mask)); \
5685                 ret = false; \
5686         } \
5687 } while (0)
5688
5689 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
5690         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
5691                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5692                                      "(expected %i, found %i)", \
5693                                      current_config->name, \
5694                                      pipe_config->name); \
5695                 ret = false; \
5696         } \
5697 } while (0)
5698
5699 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
5700         if (!intel_compare_infoframe(&current_config->infoframes.name, \
5701                                      &pipe_config->infoframes.name)) { \
5702                 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
5703                                                &current_config->infoframes.name, \
5704                                                &pipe_config->infoframes.name); \
5705                 ret = false; \
5706         } \
5707 } while (0)
5708
5709 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
5710         if (!current_config->has_psr && !pipe_config->has_psr && \
5711             !intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
5712                                       &pipe_config->infoframes.name)) { \
5713                 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
5714                                                 &current_config->infoframes.name, \
5715                                                 &pipe_config->infoframes.name); \
5716                 ret = false; \
5717         } \
5718 } while (0)
5719
5720 #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
5721         if (current_config->name1 != pipe_config->name1) { \
5722                 pipe_config_mismatch(fastset, crtc, __stringify(name1), \
5723                                 "(expected %i, found %i, won't compare lut values)", \
5724                                 current_config->name1, \
5725                                 pipe_config->name1); \
5726                 ret = false;\
5727         } else { \
5728                 if (!intel_color_lut_equal(current_config->name2, \
5729                                         pipe_config->name2, pipe_config->name1, \
5730                                         bit_precision)) { \
5731                         pipe_config_mismatch(fastset, crtc, __stringify(name2), \
5732                                         "hw_state doesn't match sw_state"); \
5733                         ret = false; \
5734                 } \
5735         } \
5736 } while (0)
5737
5738 #define PIPE_CONF_QUIRK(quirk) \
5739         ((current_config->quirks | pipe_config->quirks) & (quirk))
5740
5741         PIPE_CONF_CHECK_I(hw.enable);
5742         PIPE_CONF_CHECK_I(hw.active);
5743
5744         PIPE_CONF_CHECK_I(cpu_transcoder);
5745         PIPE_CONF_CHECK_I(mst_master_transcoder);
5746
5747         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
5748         PIPE_CONF_CHECK_I(fdi_lanes);
5749         PIPE_CONF_CHECK_M_N(fdi_m_n);
5750
5751         PIPE_CONF_CHECK_I(lane_count);
5752         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
5753
5754         if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) {
5755                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
5756         } else {
5757                 PIPE_CONF_CHECK_M_N(dp_m_n);
5758                 PIPE_CONF_CHECK_M_N(dp_m2_n2);
5759         }
5760
5761         PIPE_CONF_CHECK_X(output_types);
5762
5763         PIPE_CONF_CHECK_I(framestart_delay);
5764         PIPE_CONF_CHECK_I(msa_timing_delay);
5765
5766         PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
5767         PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
5768
5769         PIPE_CONF_CHECK_I(pixel_multiplier);
5770
5771         PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5772                               DRM_MODE_FLAG_INTERLACE);
5773
5774         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
5775                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5776                                       DRM_MODE_FLAG_PHSYNC);
5777                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5778                                       DRM_MODE_FLAG_NHSYNC);
5779                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5780                                       DRM_MODE_FLAG_PVSYNC);
5781                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5782                                       DRM_MODE_FLAG_NVSYNC);
5783         }
5784
5785         PIPE_CONF_CHECK_I(output_format);
5786         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
5787         if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
5788             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5789                 PIPE_CONF_CHECK_BOOL(limited_color_range);
5790
5791         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
5792         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
5793         PIPE_CONF_CHECK_BOOL(has_infoframe);
5794         PIPE_CONF_CHECK_BOOL(fec_enable);
5795
5796         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
5797
5798         PIPE_CONF_CHECK_X(gmch_pfit.control);
5799         /* pfit ratios are autocomputed by the hw on gen4+ */
5800         if (DISPLAY_VER(dev_priv) < 4)
5801                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
5802         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
5803
5804         /*
5805          * Changing the EDP transcoder input mux
5806          * (A_ONOFF vs. A_ON) requires a full modeset.
5807          */
5808         PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
5809
5810         if (!fastset) {
5811                 PIPE_CONF_CHECK_RECT(pipe_src);
5812
5813                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
5814                 PIPE_CONF_CHECK_RECT(pch_pfit.dst);
5815
5816                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
5817                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
5818
5819                 PIPE_CONF_CHECK_X(gamma_mode);
5820                 if (IS_CHERRYVIEW(dev_priv))
5821                         PIPE_CONF_CHECK_X(cgm_mode);
5822                 else
5823                         PIPE_CONF_CHECK_X(csc_mode);
5824                 PIPE_CONF_CHECK_BOOL(gamma_enable);
5825                 PIPE_CONF_CHECK_BOOL(csc_enable);
5826
5827                 PIPE_CONF_CHECK_I(linetime);
5828                 PIPE_CONF_CHECK_I(ips_linetime);
5829
5830                 bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
5831                 if (bp_gamma)
5832                         PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
5833
5834                 if (current_config->active_planes) {
5835                         PIPE_CONF_CHECK_BOOL(has_psr);
5836                         PIPE_CONF_CHECK_BOOL(has_psr2);
5837                         PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
5838                         PIPE_CONF_CHECK_I(dc3co_exitline);
5839                 }
5840         }
5841
5842         PIPE_CONF_CHECK_BOOL(double_wide);
5843
5844         if (dev_priv->dpll.mgr) {
5845                 PIPE_CONF_CHECK_P(shared_dpll);
5846
5847                 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
5848                 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
5849                 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
5850                 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
5851                 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
5852                 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
5853                 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
5854                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
5855                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
5856                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
5857                 PIPE_CONF_CHECK_X(dpll_hw_state.div0);
5858                 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
5859                 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
5860                 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
5861                 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
5862                 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
5863                 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
5864                 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
5865                 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
5866                 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
5867                 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
5868                 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
5869                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
5870                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
5871                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
5872                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
5873                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
5874                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
5875                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
5876                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
5877                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
5878                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
5879         }
5880
5881         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
5882         PIPE_CONF_CHECK_X(dsi_pll.div);
5883
5884         if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
5885                 PIPE_CONF_CHECK_I(pipe_bpp);
5886
5887         PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
5888         PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
5889         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5890
5891         PIPE_CONF_CHECK_I(min_voltage_level);
5892
5893         if (current_config->has_psr || pipe_config->has_psr)
5894                 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
5895                                             ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
5896         else
5897                 PIPE_CONF_CHECK_X(infoframes.enable);
5898
5899         PIPE_CONF_CHECK_X(infoframes.gcp);
5900         PIPE_CONF_CHECK_INFOFRAME(avi);
5901         PIPE_CONF_CHECK_INFOFRAME(spd);
5902         PIPE_CONF_CHECK_INFOFRAME(hdmi);
5903         PIPE_CONF_CHECK_INFOFRAME(drm);
5904         PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
5905
5906         PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
5907         PIPE_CONF_CHECK_I(master_transcoder);
5908         PIPE_CONF_CHECK_X(bigjoiner_pipes);
5909
5910         PIPE_CONF_CHECK_I(dsc.compression_enable);
5911         PIPE_CONF_CHECK_I(dsc.dsc_split);
5912         PIPE_CONF_CHECK_I(dsc.compressed_bpp);
5913
5914         PIPE_CONF_CHECK_BOOL(splitter.enable);
5915         PIPE_CONF_CHECK_I(splitter.link_count);
5916         PIPE_CONF_CHECK_I(splitter.pixel_overlap);
5917
5918         PIPE_CONF_CHECK_BOOL(vrr.enable);
5919         PIPE_CONF_CHECK_I(vrr.vmin);
5920         PIPE_CONF_CHECK_I(vrr.vmax);
5921         PIPE_CONF_CHECK_I(vrr.flipline);
5922         PIPE_CONF_CHECK_I(vrr.pipeline_full);
5923         PIPE_CONF_CHECK_I(vrr.guardband);
5924
5925 #undef PIPE_CONF_CHECK_X
5926 #undef PIPE_CONF_CHECK_I
5927 #undef PIPE_CONF_CHECK_BOOL
5928 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
5929 #undef PIPE_CONF_CHECK_P
5930 #undef PIPE_CONF_CHECK_FLAGS
5931 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
5932 #undef PIPE_CONF_CHECK_COLOR_LUT
5933 #undef PIPE_CONF_CHECK_TIMINGS
5934 #undef PIPE_CONF_CHECK_RECT
5935 #undef PIPE_CONF_QUIRK
5936
5937         return ret;
5938 }
5939
5940 static void
5941 intel_verify_planes(struct intel_atomic_state *state)
5942 {
5943         struct intel_plane *plane;
5944         const struct intel_plane_state *plane_state;
5945         int i;
5946
5947         for_each_new_intel_plane_in_state(state, plane,
5948                                           plane_state, i)
5949                 assert_plane(plane, plane_state->planar_slave ||
5950                              plane_state->uapi.visible);
5951 }
5952
5953 int intel_modeset_all_pipes(struct intel_atomic_state *state)
5954 {
5955         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5956         struct intel_crtc *crtc;
5957
5958         /*
5959          * Add all pipes to the state, and force
5960          * a modeset on all the active ones.
5961          */
5962         for_each_intel_crtc(&dev_priv->drm, crtc) {
5963                 struct intel_crtc_state *crtc_state;
5964                 int ret;
5965
5966                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5967                 if (IS_ERR(crtc_state))
5968                         return PTR_ERR(crtc_state);
5969
5970                 if (!crtc_state->hw.active ||
5971                     drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
5972                         continue;
5973
5974                 crtc_state->uapi.mode_changed = true;
5975
5976                 ret = drm_atomic_add_affected_connectors(&state->base,
5977                                                          &crtc->base);
5978                 if (ret)
5979                         return ret;
5980
5981                 ret = intel_atomic_add_affected_planes(state, crtc);
5982                 if (ret)
5983                         return ret;
5984
5985                 crtc_state->update_planes |= crtc_state->active_planes;
5986         }
5987
5988         return 0;
5989 }
5990
5991 void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
5992 {
5993         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5994         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5995         struct drm_display_mode adjusted_mode;
5996
5997         drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode);
5998
5999         if (crtc_state->vrr.enable) {
6000                 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax;
6001                 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax;
6002                 adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
6003                 crtc->vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
6004         }
6005
6006         drm_calc_timestamping_constants(&crtc->base, &adjusted_mode);
6007
6008         crtc->mode_flags = crtc_state->mode_flags;
6009
6010         /*
6011          * The scanline counter increments at the leading edge of hsync.
6012          *
6013          * On most platforms it starts counting from vtotal-1 on the
6014          * first active line. That means the scanline counter value is
6015          * always one less than what we would expect. Ie. just after
6016          * start of vblank, which also occurs at start of hsync (on the
6017          * last active line), the scanline counter will read vblank_start-1.
6018          *
6019          * On gen2 the scanline counter starts counting from 1 instead
6020          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
6021          * to keep the value positive), instead of adding one.
6022          *
6023          * On HSW+ the behaviour of the scanline counter depends on the output
6024          * type. For DP ports it behaves like most other platforms, but on HDMI
6025          * there's an extra 1 line difference. So we need to add two instead of
6026          * one to the value.
6027          *
6028          * On VLV/CHV DSI the scanline counter would appear to increment
6029          * approx. 1/3 of a scanline before start of vblank. Unfortunately
6030          * that means we can't tell whether we're in vblank or not while
6031          * we're on that particular line. We must still set scanline_offset
6032          * to 1 so that the vblank timestamps come out correct when we query
6033          * the scanline counter from within the vblank interrupt handler.
6034          * However if queried just before the start of vblank we'll get an
6035          * answer that's slightly in the future.
6036          */
6037         if (DISPLAY_VER(dev_priv) == 2) {
6038                 int vtotal;
6039
6040                 vtotal = adjusted_mode.crtc_vtotal;
6041                 if (adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6042                         vtotal /= 2;
6043
6044                 crtc->scanline_offset = vtotal - 1;
6045         } else if (HAS_DDI(dev_priv) &&
6046                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
6047                 crtc->scanline_offset = 2;
6048         } else {
6049                 crtc->scanline_offset = 1;
6050         }
6051 }
6052
6053 static void intel_modeset_clear_plls(struct intel_atomic_state *state)
6054 {
6055         struct intel_crtc_state *new_crtc_state;
6056         struct intel_crtc *crtc;
6057         int i;
6058
6059         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6060                 if (!intel_crtc_needs_modeset(new_crtc_state))
6061                         continue;
6062
6063                 intel_release_shared_dplls(state, crtc);
6064         }
6065 }
6066
6067 /*
6068  * This implements the workaround described in the "notes" section of the mode
6069  * set sequence documentation. When going from no pipes or single pipe to
6070  * multiple pipes, and planes are enabled after the pipe, we need to wait at
6071  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
6072  */
6073 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
6074 {
6075         struct intel_crtc_state *crtc_state;
6076         struct intel_crtc *crtc;
6077         struct intel_crtc_state *first_crtc_state = NULL;
6078         struct intel_crtc_state *other_crtc_state = NULL;
6079         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
6080         int i;
6081
6082         /* look at all crtc's that are going to be enabled in during modeset */
6083         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6084                 if (!crtc_state->hw.active ||
6085                     !intel_crtc_needs_modeset(crtc_state))
6086                         continue;
6087
6088                 if (first_crtc_state) {
6089                         other_crtc_state = crtc_state;
6090                         break;
6091                 } else {
6092                         first_crtc_state = crtc_state;
6093                         first_pipe = crtc->pipe;
6094                 }
6095         }
6096
6097         /* No workaround needed? */
6098         if (!first_crtc_state)
6099                 return 0;
6100
6101         /* w/a possibly needed, check how many crtc's are already enabled. */
6102         for_each_intel_crtc(state->base.dev, crtc) {
6103                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6104                 if (IS_ERR(crtc_state))
6105                         return PTR_ERR(crtc_state);
6106
6107                 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
6108
6109                 if (!crtc_state->hw.active ||
6110                     intel_crtc_needs_modeset(crtc_state))
6111                         continue;
6112
6113                 /* 2 or more enabled crtcs means no need for w/a */
6114                 if (enabled_pipe != INVALID_PIPE)
6115                         return 0;
6116
6117                 enabled_pipe = crtc->pipe;
6118         }
6119
6120         if (enabled_pipe != INVALID_PIPE)
6121                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
6122         else if (other_crtc_state)
6123                 other_crtc_state->hsw_workaround_pipe = first_pipe;
6124
6125         return 0;
6126 }
6127
6128 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
6129                            u8 active_pipes)
6130 {
6131         const struct intel_crtc_state *crtc_state;
6132         struct intel_crtc *crtc;
6133         int i;
6134
6135         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6136                 if (crtc_state->hw.active)
6137                         active_pipes |= BIT(crtc->pipe);
6138                 else
6139                         active_pipes &= ~BIT(crtc->pipe);
6140         }
6141
6142         return active_pipes;
6143 }
6144
6145 static int intel_modeset_checks(struct intel_atomic_state *state)
6146 {
6147         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6148
6149         state->modeset = true;
6150
6151         if (IS_HASWELL(dev_priv))
6152                 return hsw_mode_set_planes_workaround(state);
6153
6154         return 0;
6155 }
6156
6157 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
6158                                      struct intel_crtc_state *new_crtc_state)
6159 {
6160         if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
6161                 return;
6162
6163         new_crtc_state->uapi.mode_changed = false;
6164         new_crtc_state->update_pipe = true;
6165 }
6166
6167 static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
6168                                     struct intel_crtc_state *new_crtc_state)
6169 {
6170         /*
6171          * If we're not doing the full modeset we want to
6172          * keep the current M/N values as they may be
6173          * sufficiently different to the computed values
6174          * to cause problems.
6175          *
6176          * FIXME: should really copy more fuzzy state here
6177          */
6178         new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
6179         new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
6180         new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
6181         new_crtc_state->has_drrs = old_crtc_state->has_drrs;
6182 }
6183
6184 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
6185                                           struct intel_crtc *crtc,
6186                                           u8 plane_ids_mask)
6187 {
6188         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6189         struct intel_plane *plane;
6190
6191         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
6192                 struct intel_plane_state *plane_state;
6193
6194                 if ((plane_ids_mask & BIT(plane->id)) == 0)
6195                         continue;
6196
6197                 plane_state = intel_atomic_get_plane_state(state, plane);
6198                 if (IS_ERR(plane_state))
6199                         return PTR_ERR(plane_state);
6200         }
6201
6202         return 0;
6203 }
6204
6205 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
6206                                      struct intel_crtc *crtc)
6207 {
6208         const struct intel_crtc_state *old_crtc_state =
6209                 intel_atomic_get_old_crtc_state(state, crtc);
6210         const struct intel_crtc_state *new_crtc_state =
6211                 intel_atomic_get_new_crtc_state(state, crtc);
6212
6213         return intel_crtc_add_planes_to_state(state, crtc,
6214                                               old_crtc_state->enabled_planes |
6215                                               new_crtc_state->enabled_planes);
6216 }
6217
6218 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
6219 {
6220         /* See {hsw,vlv,ivb}_plane_ratio() */
6221         return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
6222                 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
6223                 IS_IVYBRIDGE(dev_priv);
6224 }
6225
6226 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
6227                                            struct intel_crtc *crtc,
6228                                            struct intel_crtc *other)
6229 {
6230         const struct intel_plane_state *plane_state;
6231         struct intel_plane *plane;
6232         u8 plane_ids = 0;
6233         int i;
6234
6235         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6236                 if (plane->pipe == crtc->pipe)
6237                         plane_ids |= BIT(plane->id);
6238         }
6239
6240         return intel_crtc_add_planes_to_state(state, other, plane_ids);
6241 }
6242
6243 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state)
6244 {
6245         struct drm_i915_private *i915 = to_i915(state->base.dev);
6246         const struct intel_crtc_state *crtc_state;
6247         struct intel_crtc *crtc;
6248         int i;
6249
6250         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6251                 struct intel_crtc *other;
6252
6253                 for_each_intel_crtc_in_pipe_mask(&i915->drm, other,
6254                                                  crtc_state->bigjoiner_pipes) {
6255                         int ret;
6256
6257                         if (crtc == other)
6258                                 continue;
6259
6260                         ret = intel_crtc_add_bigjoiner_planes(state, crtc, other);
6261                         if (ret)
6262                                 return ret;
6263                 }
6264         }
6265
6266         return 0;
6267 }
6268
6269 static int intel_atomic_check_planes(struct intel_atomic_state *state)
6270 {
6271         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6272         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6273         struct intel_plane_state *plane_state;
6274         struct intel_plane *plane;
6275         struct intel_crtc *crtc;
6276         int i, ret;
6277
6278         ret = icl_add_linked_planes(state);
6279         if (ret)
6280                 return ret;
6281
6282         ret = intel_bigjoiner_add_affected_planes(state);
6283         if (ret)
6284                 return ret;
6285
6286         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6287                 ret = intel_plane_atomic_check(state, plane);
6288                 if (ret) {
6289                         drm_dbg_atomic(&dev_priv->drm,
6290                                        "[PLANE:%d:%s] atomic driver check failed\n",
6291                                        plane->base.base.id, plane->base.name);
6292                         return ret;
6293                 }
6294         }
6295
6296         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6297                                             new_crtc_state, i) {
6298                 u8 old_active_planes, new_active_planes;
6299
6300                 ret = icl_check_nv12_planes(new_crtc_state);
6301                 if (ret)
6302                         return ret;
6303
6304                 /*
6305                  * On some platforms the number of active planes affects
6306                  * the planes' minimum cdclk calculation. Add such planes
6307                  * to the state before we compute the minimum cdclk.
6308                  */
6309                 if (!active_planes_affects_min_cdclk(dev_priv))
6310                         continue;
6311
6312                 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
6313                 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
6314
6315                 if (hweight8(old_active_planes) == hweight8(new_active_planes))
6316                         continue;
6317
6318                 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
6319                 if (ret)
6320                         return ret;
6321         }
6322
6323         return 0;
6324 }
6325
6326 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
6327 {
6328         struct intel_crtc_state *crtc_state;
6329         struct intel_crtc *crtc;
6330         int i;
6331
6332         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6333                 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
6334                 int ret;
6335
6336                 ret = intel_crtc_atomic_check(state, crtc);
6337                 if (ret) {
6338                         drm_dbg_atomic(&i915->drm,
6339                                        "[CRTC:%d:%s] atomic driver check failed\n",
6340                                        crtc->base.base.id, crtc->base.name);
6341                         return ret;
6342                 }
6343         }
6344
6345         return 0;
6346 }
6347
6348 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
6349                                                u8 transcoders)
6350 {
6351         const struct intel_crtc_state *new_crtc_state;
6352         struct intel_crtc *crtc;
6353         int i;
6354
6355         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6356                 if (new_crtc_state->hw.enable &&
6357                     transcoders & BIT(new_crtc_state->cpu_transcoder) &&
6358                     intel_crtc_needs_modeset(new_crtc_state))
6359                         return true;
6360         }
6361
6362         return false;
6363 }
6364
6365 static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
6366                                      u8 pipes)
6367 {
6368         const struct intel_crtc_state *new_crtc_state;
6369         struct intel_crtc *crtc;
6370         int i;
6371
6372         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6373                 if (new_crtc_state->hw.enable &&
6374                     pipes & BIT(crtc->pipe) &&
6375                     intel_crtc_needs_modeset(new_crtc_state))
6376                         return true;
6377         }
6378
6379         return false;
6380 }
6381
6382 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
6383                                         struct intel_crtc *master_crtc)
6384 {
6385         struct drm_i915_private *i915 = to_i915(state->base.dev);
6386         struct intel_crtc_state *master_crtc_state =
6387                 intel_atomic_get_new_crtc_state(state, master_crtc);
6388         struct intel_crtc *slave_crtc;
6389
6390         if (!master_crtc_state->bigjoiner_pipes)
6391                 return 0;
6392
6393         /* sanity check */
6394         if (drm_WARN_ON(&i915->drm,
6395                         master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state)))
6396                 return -EINVAL;
6397
6398         if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) {
6399                 drm_dbg_kms(&i915->drm,
6400                             "[CRTC:%d:%s] Cannot act as big joiner master "
6401                             "(need 0x%x as pipes, only 0x%x possible)\n",
6402                             master_crtc->base.base.id, master_crtc->base.name,
6403                             master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915));
6404                 return -EINVAL;
6405         }
6406
6407         for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
6408                                          intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
6409                 struct intel_crtc_state *slave_crtc_state;
6410                 int ret;
6411
6412                 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc);
6413                 if (IS_ERR(slave_crtc_state))
6414                         return PTR_ERR(slave_crtc_state);
6415
6416                 /* master being enabled, slave was already configured? */
6417                 if (slave_crtc_state->uapi.enable) {
6418                         drm_dbg_kms(&i915->drm,
6419                                     "[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
6420                                     "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
6421                                     slave_crtc->base.base.id, slave_crtc->base.name,
6422                                     master_crtc->base.base.id, master_crtc->base.name);
6423                         return -EINVAL;
6424                 }
6425
6426                 /*
6427                  * The state copy logic assumes the master crtc gets processed
6428                  * before the slave crtc during the main compute_config loop.
6429                  * This works because the crtcs are created in pipe order,
6430                  * and the hardware requires master pipe < slave pipe as well.
6431                  * Should that change we need to rethink the logic.
6432                  */
6433                 if (WARN_ON(drm_crtc_index(&master_crtc->base) >
6434                             drm_crtc_index(&slave_crtc->base)))
6435                         return -EINVAL;
6436
6437                 drm_dbg_kms(&i915->drm,
6438                             "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n",
6439                             slave_crtc->base.base.id, slave_crtc->base.name,
6440                             master_crtc->base.base.id, master_crtc->base.name);
6441
6442                 slave_crtc_state->bigjoiner_pipes =
6443                         master_crtc_state->bigjoiner_pipes;
6444
6445                 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc);
6446                 if (ret)
6447                         return ret;
6448         }
6449
6450         return 0;
6451 }
6452
6453 static void kill_bigjoiner_slave(struct intel_atomic_state *state,
6454                                  struct intel_crtc *master_crtc)
6455 {
6456         struct drm_i915_private *i915 = to_i915(state->base.dev);
6457         struct intel_crtc_state *master_crtc_state =
6458                 intel_atomic_get_new_crtc_state(state, master_crtc);
6459         struct intel_crtc *slave_crtc;
6460
6461         for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
6462                                          intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
6463                 struct intel_crtc_state *slave_crtc_state =
6464                         intel_atomic_get_new_crtc_state(state, slave_crtc);
6465
6466                 slave_crtc_state->bigjoiner_pipes = 0;
6467
6468                 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc);
6469         }
6470
6471         master_crtc_state->bigjoiner_pipes = 0;
6472 }
6473
6474 /**
6475  * DOC: asynchronous flip implementation
6476  *
6477  * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
6478  * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
6479  * Correspondingly, support is currently added for primary plane only.
6480  *
6481  * Async flip can only change the plane surface address, so anything else
6482  * changing is rejected from the intel_async_flip_check_hw() function.
6483  * Once this check is cleared, flip done interrupt is enabled using
6484  * the intel_crtc_enable_flip_done() function.
6485  *
6486  * As soon as the surface address register is written, flip done interrupt is
6487  * generated and the requested events are sent to the usersapce in the interrupt
6488  * handler itself. The timestamp and sequence sent during the flip done event
6489  * correspond to the last vblank and have no relation to the actual time when
6490  * the flip done event was sent.
6491  */
6492 static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
6493                                        struct intel_crtc *crtc)
6494 {
6495         struct drm_i915_private *i915 = to_i915(state->base.dev);
6496         const struct intel_crtc_state *new_crtc_state =
6497                 intel_atomic_get_new_crtc_state(state, crtc);
6498         const struct intel_plane_state *old_plane_state;
6499         struct intel_plane_state *new_plane_state;
6500         struct intel_plane *plane;
6501         int i;
6502
6503         if (!new_crtc_state->uapi.async_flip)
6504                 return 0;
6505
6506         if (!new_crtc_state->uapi.active) {
6507                 drm_dbg_kms(&i915->drm,
6508                             "[CRTC:%d:%s] not active\n",
6509                             crtc->base.base.id, crtc->base.name);
6510                 return -EINVAL;
6511         }
6512
6513         if (intel_crtc_needs_modeset(new_crtc_state)) {
6514                 drm_dbg_kms(&i915->drm,
6515                             "[CRTC:%d:%s] modeset required\n",
6516                             crtc->base.base.id, crtc->base.name);
6517                 return -EINVAL;
6518         }
6519
6520         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6521                                              new_plane_state, i) {
6522                 if (plane->pipe != crtc->pipe)
6523                         continue;
6524
6525                 /*
6526                  * TODO: Async flip is only supported through the page flip IOCTL
6527                  * as of now. So support currently added for primary plane only.
6528                  * Support for other planes on platforms on which supports
6529                  * this(vlv/chv and icl+) should be added when async flip is
6530                  * enabled in the atomic IOCTL path.
6531                  */
6532                 if (!plane->async_flip) {
6533                         drm_dbg_kms(&i915->drm,
6534                                     "[PLANE:%d:%s] async flip not supported\n",
6535                                     plane->base.base.id, plane->base.name);
6536                         return -EINVAL;
6537                 }
6538
6539                 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {
6540                         drm_dbg_kms(&i915->drm,
6541                                     "[PLANE:%d:%s] no old or new framebuffer\n",
6542                                     plane->base.base.id, plane->base.name);
6543                         return -EINVAL;
6544                 }
6545         }
6546
6547         return 0;
6548 }
6549
6550 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc)
6551 {
6552         struct drm_i915_private *i915 = to_i915(state->base.dev);
6553         const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6554         const struct intel_plane_state *new_plane_state, *old_plane_state;
6555         struct intel_plane *plane;
6556         int i;
6557
6558         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6559         new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6560
6561         if (!new_crtc_state->uapi.async_flip)
6562                 return 0;
6563
6564         if (!new_crtc_state->hw.active) {
6565                 drm_dbg_kms(&i915->drm,
6566                             "[CRTC:%d:%s] not active\n",
6567                             crtc->base.base.id, crtc->base.name);
6568                 return -EINVAL;
6569         }
6570
6571         if (intel_crtc_needs_modeset(new_crtc_state)) {
6572                 drm_dbg_kms(&i915->drm,
6573                             "[CRTC:%d:%s] modeset required\n",
6574                             crtc->base.base.id, crtc->base.name);
6575                 return -EINVAL;
6576         }
6577
6578         if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
6579                 drm_dbg_kms(&i915->drm,
6580                             "[CRTC:%d:%s] Active planes cannot be in async flip\n",
6581                             crtc->base.base.id, crtc->base.name);
6582                 return -EINVAL;
6583         }
6584
6585         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6586                                              new_plane_state, i) {
6587                 if (plane->pipe != crtc->pipe)
6588                         continue;
6589
6590                 /*
6591                  * Only async flip capable planes should be in the state
6592                  * if we're really about to ask the hardware to perform
6593                  * an async flip. We should never get this far otherwise.
6594                  */
6595                 if (drm_WARN_ON(&i915->drm,
6596                                 new_crtc_state->do_async_flip && !plane->async_flip))
6597                         return -EINVAL;
6598
6599                 /*
6600                  * Only check async flip capable planes other planes
6601                  * may be involved in the initial commit due to
6602                  * the wm0/ddb optimization.
6603                  *
6604                  * TODO maybe should track which planes actually
6605                  * were requested to do the async flip...
6606                  */
6607                 if (!plane->async_flip)
6608                         continue;
6609
6610                 /*
6611                  * FIXME: This check is kept generic for all platforms.
6612                  * Need to verify this for all gen9 platforms to enable
6613                  * this selectively if required.
6614                  */
6615                 switch (new_plane_state->hw.fb->modifier) {
6616                 case I915_FORMAT_MOD_X_TILED:
6617                 case I915_FORMAT_MOD_Y_TILED:
6618                 case I915_FORMAT_MOD_Yf_TILED:
6619                 case I915_FORMAT_MOD_4_TILED:
6620                         break;
6621                 default:
6622                         drm_dbg_kms(&i915->drm,
6623                                     "[PLANE:%d:%s] Modifier does not support async flips\n",
6624                                     plane->base.base.id, plane->base.name);
6625                         return -EINVAL;
6626                 }
6627
6628                 if (new_plane_state->hw.fb->format->num_planes > 1) {
6629                         drm_dbg_kms(&i915->drm,
6630                                     "[PLANE:%d:%s] Planar formats do not support async flips\n",
6631                                     plane->base.base.id, plane->base.name);
6632                         return -EINVAL;
6633                 }
6634
6635                 if (old_plane_state->view.color_plane[0].mapping_stride !=
6636                     new_plane_state->view.color_plane[0].mapping_stride) {
6637                         drm_dbg_kms(&i915->drm,
6638                                     "[PLANE:%d:%s] Stride cannot be changed in async flip\n",
6639                                     plane->base.base.id, plane->base.name);
6640                         return -EINVAL;
6641                 }
6642
6643                 if (old_plane_state->hw.fb->modifier !=
6644                     new_plane_state->hw.fb->modifier) {
6645                         drm_dbg_kms(&i915->drm,
6646                                     "[PLANE:%d:%s] Modifier cannot be changed in async flip\n",
6647                                     plane->base.base.id, plane->base.name);
6648                         return -EINVAL;
6649                 }
6650
6651                 if (old_plane_state->hw.fb->format !=
6652                     new_plane_state->hw.fb->format) {
6653                         drm_dbg_kms(&i915->drm,
6654                                     "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n",
6655                                     plane->base.base.id, plane->base.name);
6656                         return -EINVAL;
6657                 }
6658
6659                 if (old_plane_state->hw.rotation !=
6660                     new_plane_state->hw.rotation) {
6661                         drm_dbg_kms(&i915->drm,
6662                                     "[PLANE:%d:%s] Rotation cannot be changed in async flip\n",
6663                                     plane->base.base.id, plane->base.name);
6664                         return -EINVAL;
6665                 }
6666
6667                 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
6668                     !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
6669                         drm_dbg_kms(&i915->drm,
6670                                     "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",
6671                                     plane->base.base.id, plane->base.name);
6672                         return -EINVAL;
6673                 }
6674
6675                 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
6676                         drm_dbg_kms(&i915->drm,
6677                                     "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n",
6678                                     plane->base.base.id, plane->base.name);
6679                         return -EINVAL;
6680                 }
6681
6682                 if (old_plane_state->hw.pixel_blend_mode !=
6683                     new_plane_state->hw.pixel_blend_mode) {
6684                         drm_dbg_kms(&i915->drm,
6685                                     "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n",
6686                                     plane->base.base.id, plane->base.name);
6687                         return -EINVAL;
6688                 }
6689
6690                 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
6691                         drm_dbg_kms(&i915->drm,
6692                                     "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n",
6693                                     plane->base.base.id, plane->base.name);
6694                         return -EINVAL;
6695                 }
6696
6697                 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
6698                         drm_dbg_kms(&i915->drm,
6699                                     "[PLANE:%d:%s] Color range cannot be changed in async flip\n",
6700                                     plane->base.base.id, plane->base.name);
6701                         return -EINVAL;
6702                 }
6703
6704                 /* plane decryption is allow to change only in synchronous flips */
6705                 if (old_plane_state->decrypt != new_plane_state->decrypt) {
6706                         drm_dbg_kms(&i915->drm,
6707                                     "[PLANE:%d:%s] Decryption cannot be changed in async flip\n",
6708                                     plane->base.base.id, plane->base.name);
6709                         return -EINVAL;
6710                 }
6711         }
6712
6713         return 0;
6714 }
6715
6716 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
6717 {
6718         struct drm_i915_private *i915 = to_i915(state->base.dev);
6719         struct intel_crtc_state *crtc_state;
6720         struct intel_crtc *crtc;
6721         u8 affected_pipes = 0;
6722         u8 modeset_pipes = 0;
6723         int i;
6724
6725         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6726                 affected_pipes |= crtc_state->bigjoiner_pipes;
6727                 if (intel_crtc_needs_modeset(crtc_state))
6728                         modeset_pipes |= crtc_state->bigjoiner_pipes;
6729         }
6730
6731         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) {
6732                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6733                 if (IS_ERR(crtc_state))
6734                         return PTR_ERR(crtc_state);
6735         }
6736
6737         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) {
6738                 int ret;
6739
6740                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6741
6742                 crtc_state->uapi.mode_changed = true;
6743
6744                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6745                 if (ret)
6746                         return ret;
6747
6748                 ret = intel_atomic_add_affected_planes(state, crtc);
6749                 if (ret)
6750                         return ret;
6751         }
6752
6753         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6754                 /* Kill old bigjoiner link, we may re-establish afterwards */
6755                 if (intel_crtc_needs_modeset(crtc_state) &&
6756                     intel_crtc_is_bigjoiner_master(crtc_state))
6757                         kill_bigjoiner_slave(state, crtc);
6758         }
6759
6760         return 0;
6761 }
6762
6763 /**
6764  * intel_atomic_check - validate state object
6765  * @dev: drm device
6766  * @_state: state to validate
6767  */
6768 static int intel_atomic_check(struct drm_device *dev,
6769                               struct drm_atomic_state *_state)
6770 {
6771         struct drm_i915_private *dev_priv = to_i915(dev);
6772         struct intel_atomic_state *state = to_intel_atomic_state(_state);
6773         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6774         struct intel_crtc *crtc;
6775         int ret, i;
6776         bool any_ms = false;
6777
6778         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6779                                             new_crtc_state, i) {
6780                 if (new_crtc_state->inherited != old_crtc_state->inherited)
6781                         new_crtc_state->uapi.mode_changed = true;
6782
6783                 if (new_crtc_state->uapi.scaling_filter !=
6784                     old_crtc_state->uapi.scaling_filter)
6785                         new_crtc_state->uapi.mode_changed = true;
6786         }
6787
6788         intel_vrr_check_modeset(state);
6789
6790         ret = drm_atomic_helper_check_modeset(dev, &state->base);
6791         if (ret)
6792                 goto fail;
6793
6794         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6795                 ret = intel_async_flip_check_uapi(state, crtc);
6796                 if (ret)
6797                         return ret;
6798         }
6799
6800         ret = intel_bigjoiner_add_affected_crtcs(state);
6801         if (ret)
6802                 goto fail;
6803
6804         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6805                                             new_crtc_state, i) {
6806                 if (!intel_crtc_needs_modeset(new_crtc_state)) {
6807                         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
6808                                 copy_bigjoiner_crtc_state_nomodeset(state, crtc);
6809                         else
6810                                 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
6811                         continue;
6812                 }
6813
6814                 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
6815                         drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable);
6816                         continue;
6817                 }
6818
6819                 ret = intel_crtc_prepare_cleared_state(state, crtc);
6820                 if (ret)
6821                         goto fail;
6822
6823                 if (!new_crtc_state->hw.enable)
6824                         continue;
6825
6826                 ret = intel_modeset_pipe_config(state, crtc);
6827                 if (ret)
6828                         goto fail;
6829
6830                 ret = intel_atomic_check_bigjoiner(state, crtc);
6831                 if (ret)
6832                         goto fail;
6833         }
6834
6835         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6836                                             new_crtc_state, i) {
6837                 if (!intel_crtc_needs_modeset(new_crtc_state))
6838                         continue;
6839
6840                 ret = intel_modeset_pipe_config_late(state, crtc);
6841                 if (ret)
6842                         goto fail;
6843
6844                 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
6845         }
6846
6847         /**
6848          * Check if fastset is allowed by external dependencies like other
6849          * pipes and transcoders.
6850          *
6851          * Right now it only forces a fullmodeset when the MST master
6852          * transcoder did not changed but the pipe of the master transcoder
6853          * needs a fullmodeset so all slaves also needs to do a fullmodeset or
6854          * in case of port synced crtcs, if one of the synced crtcs
6855          * needs a full modeset, all other synced crtcs should be
6856          * forced a full modeset.
6857          */
6858         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6859                 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
6860                         continue;
6861
6862                 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
6863                         enum transcoder master = new_crtc_state->mst_master_transcoder;
6864
6865                         if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
6866                                 new_crtc_state->uapi.mode_changed = true;
6867                                 new_crtc_state->update_pipe = false;
6868                         }
6869                 }
6870
6871                 if (is_trans_port_sync_mode(new_crtc_state)) {
6872                         u8 trans = new_crtc_state->sync_mode_slaves_mask;
6873
6874                         if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
6875                                 trans |= BIT(new_crtc_state->master_transcoder);
6876
6877                         if (intel_cpu_transcoders_need_modeset(state, trans)) {
6878                                 new_crtc_state->uapi.mode_changed = true;
6879                                 new_crtc_state->update_pipe = false;
6880                         }
6881                 }
6882
6883                 if (new_crtc_state->bigjoiner_pipes) {
6884                         if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) {
6885                                 new_crtc_state->uapi.mode_changed = true;
6886                                 new_crtc_state->update_pipe = false;
6887                         }
6888                 }
6889         }
6890
6891         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6892                                             new_crtc_state, i) {
6893                 if (intel_crtc_needs_modeset(new_crtc_state)) {
6894                         any_ms = true;
6895                         continue;
6896                 }
6897
6898                 if (!new_crtc_state->update_pipe)
6899                         continue;
6900
6901                 intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
6902         }
6903
6904         if (any_ms && !check_digital_port_conflicts(state)) {
6905                 drm_dbg_kms(&dev_priv->drm,
6906                             "rejecting conflicting digital port configuration\n");
6907                 ret = -EINVAL;
6908                 goto fail;
6909         }
6910
6911         ret = drm_dp_mst_atomic_check(&state->base);
6912         if (ret)
6913                 goto fail;
6914
6915         ret = intel_atomic_check_planes(state);
6916         if (ret)
6917                 goto fail;
6918
6919         ret = intel_compute_global_watermarks(state);
6920         if (ret)
6921                 goto fail;
6922
6923         ret = intel_bw_atomic_check(state);
6924         if (ret)
6925                 goto fail;
6926
6927         ret = intel_cdclk_atomic_check(state, &any_ms);
6928         if (ret)
6929                 goto fail;
6930
6931         if (intel_any_crtc_needs_modeset(state))
6932                 any_ms = true;
6933
6934         if (any_ms) {
6935                 ret = intel_modeset_checks(state);
6936                 if (ret)
6937                         goto fail;
6938
6939                 ret = intel_modeset_calc_cdclk(state);
6940                 if (ret)
6941                         return ret;
6942
6943                 intel_modeset_clear_plls(state);
6944         }
6945
6946         ret = intel_atomic_check_crtcs(state);
6947         if (ret)
6948                 goto fail;
6949
6950         ret = intel_fbc_atomic_check(state);
6951         if (ret)
6952                 goto fail;
6953
6954         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6955                                             new_crtc_state, i) {
6956                 ret = intel_async_flip_check_hw(state, crtc);
6957                 if (ret)
6958                         goto fail;
6959
6960                 if (!intel_crtc_needs_modeset(new_crtc_state) &&
6961                     !new_crtc_state->update_pipe)
6962                         continue;
6963
6964                 intel_crtc_state_dump(new_crtc_state, state,
6965                                       intel_crtc_needs_modeset(new_crtc_state) ?
6966                                       "modeset" : "fastset");
6967         }
6968
6969         return 0;
6970
6971  fail:
6972         if (ret == -EDEADLK)
6973                 return ret;
6974
6975         /*
6976          * FIXME would probably be nice to know which crtc specifically
6977          * caused the failure, in cases where we can pinpoint it.
6978          */
6979         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6980                                             new_crtc_state, i)
6981                 intel_crtc_state_dump(new_crtc_state, state, "failed");
6982
6983         return ret;
6984 }
6985
6986 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
6987 {
6988         struct intel_crtc_state *crtc_state;
6989         struct intel_crtc *crtc;
6990         int i, ret;
6991
6992         ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
6993         if (ret < 0)
6994                 return ret;
6995
6996         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6997                 bool mode_changed = intel_crtc_needs_modeset(crtc_state);
6998
6999                 if (mode_changed || crtc_state->update_pipe ||
7000                     crtc_state->uapi.color_mgmt_changed) {
7001                         intel_dsb_prepare(crtc_state);
7002                 }
7003         }
7004
7005         return 0;
7006 }
7007
7008 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
7009                                   struct intel_crtc_state *crtc_state)
7010 {
7011         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7012
7013         if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
7014                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
7015
7016         if (crtc_state->has_pch_encoder) {
7017                 enum pipe pch_transcoder =
7018                         intel_crtc_pch_transcoder(crtc);
7019
7020                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
7021         }
7022 }
7023
7024 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
7025                                const struct intel_crtc_state *new_crtc_state)
7026 {
7027         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
7028         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7029
7030         /*
7031          * Update pipe size and adjust fitter if needed: the reason for this is
7032          * that in compute_mode_changes we check the native mode (not the pfit
7033          * mode) to see if we can flip rather than do a full mode set. In the
7034          * fastboot case, we'll flip, but if we don't update the pipesrc and
7035          * pfit state, we'll end up with a big fb scanned out into the wrong
7036          * sized surface.
7037          */
7038         intel_set_pipe_src_size(new_crtc_state);
7039
7040         /* on skylake this is done by detaching scalers */
7041         if (DISPLAY_VER(dev_priv) >= 9) {
7042                 if (new_crtc_state->pch_pfit.enabled)
7043                         skl_pfit_enable(new_crtc_state);
7044         } else if (HAS_PCH_SPLIT(dev_priv)) {
7045                 if (new_crtc_state->pch_pfit.enabled)
7046                         ilk_pfit_enable(new_crtc_state);
7047                 else if (old_crtc_state->pch_pfit.enabled)
7048                         ilk_pfit_disable(old_crtc_state);
7049         }
7050
7051         /*
7052          * The register is supposedly single buffered so perhaps
7053          * not 100% correct to do this here. But SKL+ calculate
7054          * this based on the adjust pixel rate so pfit changes do
7055          * affect it and so it must be updated for fastsets.
7056          * HSW/BDW only really need this here for fastboot, after
7057          * that the value should not change without a full modeset.
7058          */
7059         if (DISPLAY_VER(dev_priv) >= 9 ||
7060             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
7061                 hsw_set_linetime_wm(new_crtc_state);
7062 }
7063
7064 static void commit_pipe_pre_planes(struct intel_atomic_state *state,
7065                                    struct intel_crtc *crtc)
7066 {
7067         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7068         const struct intel_crtc_state *old_crtc_state =
7069                 intel_atomic_get_old_crtc_state(state, crtc);
7070         const struct intel_crtc_state *new_crtc_state =
7071                 intel_atomic_get_new_crtc_state(state, crtc);
7072         bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7073
7074         /*
7075          * During modesets pipe configuration was programmed as the
7076          * CRTC was enabled.
7077          */
7078         if (!modeset) {
7079                 if (new_crtc_state->uapi.color_mgmt_changed ||
7080                     new_crtc_state->update_pipe)
7081                         intel_color_commit_arm(new_crtc_state);
7082
7083                 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
7084                         bdw_set_pipemisc(new_crtc_state);
7085
7086                 if (new_crtc_state->update_pipe)
7087                         intel_pipe_fastset(old_crtc_state, new_crtc_state);
7088         }
7089
7090         intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
7091
7092         intel_atomic_update_watermarks(state, crtc);
7093 }
7094
7095 static void commit_pipe_post_planes(struct intel_atomic_state *state,
7096                                     struct intel_crtc *crtc)
7097 {
7098         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7099         const struct intel_crtc_state *new_crtc_state =
7100                 intel_atomic_get_new_crtc_state(state, crtc);
7101
7102         /*
7103          * Disable the scaler(s) after the plane(s) so that we don't
7104          * get a catastrophic underrun even if the two operations
7105          * end up happening in two different frames.
7106          */
7107         if (DISPLAY_VER(dev_priv) >= 9 &&
7108             !intel_crtc_needs_modeset(new_crtc_state))
7109                 skl_detach_scalers(new_crtc_state);
7110 }
7111
7112 static void intel_enable_crtc(struct intel_atomic_state *state,
7113                               struct intel_crtc *crtc)
7114 {
7115         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7116         const struct intel_crtc_state *new_crtc_state =
7117                 intel_atomic_get_new_crtc_state(state, crtc);
7118
7119         if (!intel_crtc_needs_modeset(new_crtc_state))
7120                 return;
7121
7122         intel_crtc_update_active_timings(new_crtc_state);
7123
7124         dev_priv->display->crtc_enable(state, crtc);
7125
7126         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
7127                 return;
7128
7129         /* vblanks work again, re-enable pipe CRC. */
7130         intel_crtc_enable_pipe_crc(crtc);
7131 }
7132
7133 static void intel_update_crtc(struct intel_atomic_state *state,
7134                               struct intel_crtc *crtc)
7135 {
7136         struct drm_i915_private *i915 = to_i915(state->base.dev);
7137         const struct intel_crtc_state *old_crtc_state =
7138                 intel_atomic_get_old_crtc_state(state, crtc);
7139         struct intel_crtc_state *new_crtc_state =
7140                 intel_atomic_get_new_crtc_state(state, crtc);
7141         bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7142
7143         if (!modeset) {
7144                 if (new_crtc_state->preload_luts &&
7145                     (new_crtc_state->uapi.color_mgmt_changed ||
7146                      new_crtc_state->update_pipe))
7147                         intel_color_load_luts(new_crtc_state);
7148
7149                 intel_pre_plane_update(state, crtc);
7150
7151                 if (new_crtc_state->update_pipe)
7152                         intel_encoders_update_pipe(state, crtc);
7153
7154                 if (DISPLAY_VER(i915) >= 11 &&
7155                     new_crtc_state->update_pipe)
7156                         icl_set_pipe_chicken(new_crtc_state);
7157         }
7158
7159         intel_fbc_update(state, crtc);
7160
7161         if (!modeset &&
7162             (new_crtc_state->uapi.color_mgmt_changed ||
7163              new_crtc_state->update_pipe))
7164                 intel_color_commit_noarm(new_crtc_state);
7165
7166         intel_crtc_planes_update_noarm(state, crtc);
7167
7168         /* Perform vblank evasion around commit operation */
7169         intel_pipe_update_start(new_crtc_state);
7170
7171         commit_pipe_pre_planes(state, crtc);
7172
7173         intel_crtc_planes_update_arm(state, crtc);
7174
7175         commit_pipe_post_planes(state, crtc);
7176
7177         intel_pipe_update_end(new_crtc_state);
7178
7179         /*
7180          * We usually enable FIFO underrun interrupts as part of the
7181          * CRTC enable sequence during modesets.  But when we inherit a
7182          * valid pipe configuration from the BIOS we need to take care
7183          * of enabling them on the CRTC's first fastset.
7184          */
7185         if (new_crtc_state->update_pipe && !modeset &&
7186             old_crtc_state->inherited)
7187                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
7188 }
7189
7190 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
7191                                           struct intel_crtc_state *old_crtc_state,
7192                                           struct intel_crtc_state *new_crtc_state,
7193                                           struct intel_crtc *crtc)
7194 {
7195         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7196
7197         /*
7198          * We need to disable pipe CRC before disabling the pipe,
7199          * or we race against vblank off.
7200          */
7201         intel_crtc_disable_pipe_crc(crtc);
7202
7203         dev_priv->display->crtc_disable(state, crtc);
7204         crtc->active = false;
7205         intel_fbc_disable(crtc);
7206         intel_disable_shared_dpll(old_crtc_state);
7207
7208         /* FIXME unify this for all platforms */
7209         if (!new_crtc_state->hw.active &&
7210             !HAS_GMCH(dev_priv))
7211                 intel_initial_watermarks(state, crtc);
7212 }
7213
7214 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
7215 {
7216         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
7217         struct intel_crtc *crtc;
7218         u32 handled = 0;
7219         int i;
7220
7221         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7222                                             new_crtc_state, i) {
7223                 if (!intel_crtc_needs_modeset(new_crtc_state))
7224                         continue;
7225
7226                 if (!old_crtc_state->hw.active)
7227                         continue;
7228
7229                 intel_pre_plane_update(state, crtc);
7230                 intel_crtc_disable_planes(state, crtc);
7231         }
7232
7233         /* Only disable port sync and MST slaves */
7234         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7235                                             new_crtc_state, i) {
7236                 if (!intel_crtc_needs_modeset(new_crtc_state))
7237                         continue;
7238
7239                 if (!old_crtc_state->hw.active)
7240                         continue;
7241
7242                 /* In case of Transcoder port Sync master slave CRTCs can be
7243                  * assigned in any order and we need to make sure that
7244                  * slave CRTCs are disabled first and then master CRTC since
7245                  * Slave vblanks are masked till Master Vblanks.
7246                  */
7247                 if (!is_trans_port_sync_slave(old_crtc_state) &&
7248                     !intel_dp_mst_is_slave_trans(old_crtc_state) &&
7249                     !intel_crtc_is_bigjoiner_slave(old_crtc_state))
7250                         continue;
7251
7252                 intel_old_crtc_state_disables(state, old_crtc_state,
7253                                               new_crtc_state, crtc);
7254                 handled |= BIT(crtc->pipe);
7255         }
7256
7257         /* Disable everything else left on */
7258         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7259                                             new_crtc_state, i) {
7260                 if (!intel_crtc_needs_modeset(new_crtc_state) ||
7261                     (handled & BIT(crtc->pipe)))
7262                         continue;
7263
7264                 if (!old_crtc_state->hw.active)
7265                         continue;
7266
7267                 intel_old_crtc_state_disables(state, old_crtc_state,
7268                                               new_crtc_state, crtc);
7269         }
7270 }
7271
7272 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
7273 {
7274         struct intel_crtc_state *new_crtc_state;
7275         struct intel_crtc *crtc;
7276         int i;
7277
7278         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7279                 if (!new_crtc_state->hw.active)
7280                         continue;
7281
7282                 intel_enable_crtc(state, crtc);
7283                 intel_update_crtc(state, crtc);
7284         }
7285 }
7286
7287 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
7288 {
7289         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7290         struct intel_crtc *crtc;
7291         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
7292         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
7293         u8 update_pipes = 0, modeset_pipes = 0;
7294         int i;
7295
7296         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7297                 enum pipe pipe = crtc->pipe;
7298
7299                 if (!new_crtc_state->hw.active)
7300                         continue;
7301
7302                 /* ignore allocations for crtc's that have been turned off. */
7303                 if (!intel_crtc_needs_modeset(new_crtc_state)) {
7304                         entries[pipe] = old_crtc_state->wm.skl.ddb;
7305                         update_pipes |= BIT(pipe);
7306                 } else {
7307                         modeset_pipes |= BIT(pipe);
7308                 }
7309         }
7310
7311         /*
7312          * Whenever the number of active pipes changes, we need to make sure we
7313          * update the pipes in the right order so that their ddb allocations
7314          * never overlap with each other between CRTC updates. Otherwise we'll
7315          * cause pipe underruns and other bad stuff.
7316          *
7317          * So first lets enable all pipes that do not need a fullmodeset as
7318          * those don't have any external dependency.
7319          */
7320         while (update_pipes) {
7321                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7322                                                     new_crtc_state, i) {
7323                         enum pipe pipe = crtc->pipe;
7324
7325                         if ((update_pipes & BIT(pipe)) == 0)
7326                                 continue;
7327
7328                         if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7329                                                         entries, I915_MAX_PIPES, pipe))
7330                                 continue;
7331
7332                         entries[pipe] = new_crtc_state->wm.skl.ddb;
7333                         update_pipes &= ~BIT(pipe);
7334
7335                         intel_update_crtc(state, crtc);
7336
7337                         /*
7338                          * If this is an already active pipe, it's DDB changed,
7339                          * and this isn't the last pipe that needs updating
7340                          * then we need to wait for a vblank to pass for the
7341                          * new ddb allocation to take effect.
7342                          */
7343                         if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
7344                                                  &old_crtc_state->wm.skl.ddb) &&
7345                             (update_pipes | modeset_pipes))
7346                                 intel_crtc_wait_for_next_vblank(crtc);
7347                 }
7348         }
7349
7350         update_pipes = modeset_pipes;
7351
7352         /*
7353          * Enable all pipes that needs a modeset and do not depends on other
7354          * pipes
7355          */
7356         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7357                 enum pipe pipe = crtc->pipe;
7358
7359                 if ((modeset_pipes & BIT(pipe)) == 0)
7360                         continue;
7361
7362                 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
7363                     is_trans_port_sync_master(new_crtc_state) ||
7364                     intel_crtc_is_bigjoiner_master(new_crtc_state))
7365                         continue;
7366
7367                 modeset_pipes &= ~BIT(pipe);
7368
7369                 intel_enable_crtc(state, crtc);
7370         }
7371
7372         /*
7373          * Then we enable all remaining pipes that depend on other
7374          * pipes: MST slaves and port sync masters, big joiner master
7375          */
7376         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7377                 enum pipe pipe = crtc->pipe;
7378
7379                 if ((modeset_pipes & BIT(pipe)) == 0)
7380                         continue;
7381
7382                 modeset_pipes &= ~BIT(pipe);
7383
7384                 intel_enable_crtc(state, crtc);
7385         }
7386
7387         /*
7388          * Finally we do the plane updates/etc. for all pipes that got enabled.
7389          */
7390         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7391                 enum pipe pipe = crtc->pipe;
7392
7393                 if ((update_pipes & BIT(pipe)) == 0)
7394                         continue;
7395
7396                 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7397                                                                         entries, I915_MAX_PIPES, pipe));
7398
7399                 entries[pipe] = new_crtc_state->wm.skl.ddb;
7400                 update_pipes &= ~BIT(pipe);
7401
7402                 intel_update_crtc(state, crtc);
7403         }
7404
7405         drm_WARN_ON(&dev_priv->drm, modeset_pipes);
7406         drm_WARN_ON(&dev_priv->drm, update_pipes);
7407 }
7408
7409 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
7410 {
7411         struct intel_atomic_state *state, *next;
7412         struct llist_node *freed;
7413
7414         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
7415         llist_for_each_entry_safe(state, next, freed, freed)
7416                 drm_atomic_state_put(&state->base);
7417 }
7418
7419 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
7420 {
7421         struct drm_i915_private *dev_priv =
7422                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
7423
7424         intel_atomic_helper_free_state(dev_priv);
7425 }
7426
7427 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
7428 {
7429         struct wait_queue_entry wait_fence, wait_reset;
7430         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
7431
7432         init_wait_entry(&wait_fence, 0);
7433         init_wait_entry(&wait_reset, 0);
7434         for (;;) {
7435                 prepare_to_wait(&intel_state->commit_ready.wait,
7436                                 &wait_fence, TASK_UNINTERRUPTIBLE);
7437                 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags,
7438                                               I915_RESET_MODESET),
7439                                 &wait_reset, TASK_UNINTERRUPTIBLE);
7440
7441
7442                 if (i915_sw_fence_done(&intel_state->commit_ready) ||
7443                     test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags))
7444                         break;
7445
7446                 schedule();
7447         }
7448         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
7449         finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags,
7450                                   I915_RESET_MODESET),
7451                     &wait_reset);
7452 }
7453
7454 static void intel_cleanup_dsbs(struct intel_atomic_state *state)
7455 {
7456         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
7457         struct intel_crtc *crtc;
7458         int i;
7459
7460         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7461                                             new_crtc_state, i)
7462                 intel_dsb_cleanup(old_crtc_state);
7463 }
7464
7465 static void intel_atomic_cleanup_work(struct work_struct *work)
7466 {
7467         struct intel_atomic_state *state =
7468                 container_of(work, struct intel_atomic_state, base.commit_work);
7469         struct drm_i915_private *i915 = to_i915(state->base.dev);
7470
7471         intel_cleanup_dsbs(state);
7472         drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
7473         drm_atomic_helper_commit_cleanup_done(&state->base);
7474         drm_atomic_state_put(&state->base);
7475
7476         intel_atomic_helper_free_state(i915);
7477 }
7478
7479 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
7480 {
7481         struct drm_i915_private *i915 = to_i915(state->base.dev);
7482         struct intel_plane *plane;
7483         struct intel_plane_state *plane_state;
7484         int i;
7485
7486         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7487                 struct drm_framebuffer *fb = plane_state->hw.fb;
7488                 int cc_plane;
7489                 int ret;
7490
7491                 if (!fb)
7492                         continue;
7493
7494                 cc_plane = intel_fb_rc_ccs_cc_plane(fb);
7495                 if (cc_plane < 0)
7496                         continue;
7497
7498                 /*
7499                  * The layout of the fast clear color value expected by HW
7500                  * (the DRM ABI requiring this value to be located in fb at
7501                  * offset 0 of cc plane, plane #2 previous generations or
7502                  * plane #1 for flat ccs):
7503                  * - 4 x 4 bytes per-channel value
7504                  *   (in surface type specific float/int format provided by the fb user)
7505                  * - 8 bytes native color value used by the display
7506                  *   (converted/written by GPU during a fast clear operation using the
7507                  *    above per-channel values)
7508                  *
7509                  * The commit's FB prepare hook already ensured that FB obj is pinned and the
7510                  * caller made sure that the object is synced wrt. the related color clear value
7511                  * GPU write on it.
7512                  */
7513                 ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
7514                                                      fb->offsets[cc_plane] + 16,
7515                                                      &plane_state->ccval,
7516                                                      sizeof(plane_state->ccval));
7517                 /* The above could only fail if the FB obj has an unexpected backing store type. */
7518                 drm_WARN_ON(&i915->drm, ret);
7519         }
7520 }
7521
7522 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
7523 {
7524         struct drm_device *dev = state->base.dev;
7525         struct drm_i915_private *dev_priv = to_i915(dev);
7526         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
7527         struct intel_crtc *crtc;
7528         struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
7529         intel_wakeref_t wakeref = 0;
7530         int i;
7531
7532         intel_atomic_commit_fence_wait(state);
7533
7534         drm_atomic_helper_wait_for_dependencies(&state->base);
7535
7536         if (state->modeset)
7537                 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
7538
7539         intel_atomic_prepare_plane_clear_colors(state);
7540
7541         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7542                                             new_crtc_state, i) {
7543                 if (intel_crtc_needs_modeset(new_crtc_state) ||
7544                     new_crtc_state->update_pipe) {
7545                         intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
7546                 }
7547         }
7548
7549         intel_commit_modeset_disables(state);
7550
7551         /* FIXME: Eventually get rid of our crtc->config pointer */
7552         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7553                 crtc->config = new_crtc_state;
7554
7555         if (state->modeset) {
7556                 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
7557
7558                 intel_set_cdclk_pre_plane_update(state);
7559
7560                 intel_modeset_verify_disabled(dev_priv, state);
7561         }
7562
7563         intel_sagv_pre_plane_update(state);
7564
7565         /* Complete the events for pipes that have now been disabled */
7566         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7567                 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7568
7569                 /* Complete events for now disable pipes here. */
7570                 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
7571                         spin_lock_irq(&dev->event_lock);
7572                         drm_crtc_send_vblank_event(&crtc->base,
7573                                                    new_crtc_state->uapi.event);
7574                         spin_unlock_irq(&dev->event_lock);
7575
7576                         new_crtc_state->uapi.event = NULL;
7577                 }
7578         }
7579
7580         intel_encoders_update_prepare(state);
7581
7582         intel_dbuf_pre_plane_update(state);
7583         intel_mbus_dbox_update(state);
7584
7585         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7586                 if (new_crtc_state->do_async_flip)
7587                         intel_crtc_enable_flip_done(state, crtc);
7588         }
7589
7590         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7591         dev_priv->display->commit_modeset_enables(state);
7592
7593         intel_encoders_update_complete(state);
7594
7595         if (state->modeset)
7596                 intel_set_cdclk_post_plane_update(state);
7597
7598         intel_wait_for_vblank_workers(state);
7599
7600         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
7601          * already, but still need the state for the delayed optimization. To
7602          * fix this:
7603          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
7604          * - schedule that vblank worker _before_ calling hw_done
7605          * - at the start of commit_tail, cancel it _synchrously
7606          * - switch over to the vblank wait helper in the core after that since
7607          *   we don't need out special handling any more.
7608          */
7609         drm_atomic_helper_wait_for_flip_done(dev, &state->base);
7610
7611         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7612                 if (new_crtc_state->do_async_flip)
7613                         intel_crtc_disable_flip_done(state, crtc);
7614         }
7615
7616         /*
7617          * Now that the vblank has passed, we can go ahead and program the
7618          * optimal watermarks on platforms that need two-step watermark
7619          * programming.
7620          *
7621          * TODO: Move this (and other cleanup) to an async worker eventually.
7622          */
7623         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7624                                             new_crtc_state, i) {
7625                 /*
7626                  * Gen2 reports pipe underruns whenever all planes are disabled.
7627                  * So re-enable underrun reporting after some planes get enabled.
7628                  *
7629                  * We do this before .optimize_watermarks() so that we have a
7630                  * chance of catching underruns with the intermediate watermarks
7631                  * vs. the new plane configuration.
7632                  */
7633                 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
7634                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
7635
7636                 intel_optimize_watermarks(state, crtc);
7637         }
7638
7639         intel_dbuf_post_plane_update(state);
7640         intel_psr_post_plane_update(state);
7641
7642         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7643                 intel_post_plane_update(state, crtc);
7644
7645                 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
7646
7647                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
7648
7649                 /*
7650                  * DSB cleanup is done in cleanup_work aligning with framebuffer
7651                  * cleanup. So copy and reset the dsb structure to sync with
7652                  * commit_done and later do dsb cleanup in cleanup_work.
7653                  */
7654                 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
7655         }
7656
7657         /* Underruns don't always raise interrupts, so check manually */
7658         intel_check_cpu_fifo_underruns(dev_priv);
7659         intel_check_pch_fifo_underruns(dev_priv);
7660
7661         if (state->modeset)
7662                 intel_verify_planes(state);
7663
7664         intel_sagv_post_plane_update(state);
7665
7666         drm_atomic_helper_commit_hw_done(&state->base);
7667
7668         if (state->modeset) {
7669                 /* As one of the primary mmio accessors, KMS has a high
7670                  * likelihood of triggering bugs in unclaimed access. After we
7671                  * finish modesetting, see if an error has been flagged, and if
7672                  * so enable debugging for the next modeset - and hope we catch
7673                  * the culprit.
7674                  */
7675                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
7676                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
7677         }
7678         intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7679
7680         /*
7681          * Defer the cleanup of the old state to a separate worker to not
7682          * impede the current task (userspace for blocking modesets) that
7683          * are executed inline. For out-of-line asynchronous modesets/flips,
7684          * deferring to a new worker seems overkill, but we would place a
7685          * schedule point (cond_resched()) here anyway to keep latencies
7686          * down.
7687          */
7688         INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
7689         queue_work(system_highpri_wq, &state->base.commit_work);
7690 }
7691
7692 static void intel_atomic_commit_work(struct work_struct *work)
7693 {
7694         struct intel_atomic_state *state =
7695                 container_of(work, struct intel_atomic_state, base.commit_work);
7696
7697         intel_atomic_commit_tail(state);
7698 }
7699
7700 static int
7701 intel_atomic_commit_ready(struct i915_sw_fence *fence,
7702                           enum i915_sw_fence_notify notify)
7703 {
7704         struct intel_atomic_state *state =
7705                 container_of(fence, struct intel_atomic_state, commit_ready);
7706
7707         switch (notify) {
7708         case FENCE_COMPLETE:
7709                 /* we do blocking waits in the worker, nothing to do here */
7710                 break;
7711         case FENCE_FREE:
7712                 {
7713                         struct intel_atomic_helper *helper =
7714                                 &to_i915(state->base.dev)->atomic_helper;
7715
7716                         if (llist_add(&state->freed, &helper->free_list))
7717                                 schedule_work(&helper->free_work);
7718                         break;
7719                 }
7720         }
7721
7722         return NOTIFY_DONE;
7723 }
7724
7725 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
7726 {
7727         struct intel_plane_state *old_plane_state, *new_plane_state;
7728         struct intel_plane *plane;
7729         int i;
7730
7731         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
7732                                              new_plane_state, i)
7733                 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
7734                                         to_intel_frontbuffer(new_plane_state->hw.fb),
7735                                         plane->frontbuffer_bit);
7736 }
7737
7738 static int intel_atomic_commit(struct drm_device *dev,
7739                                struct drm_atomic_state *_state,
7740                                bool nonblock)
7741 {
7742         struct intel_atomic_state *state = to_intel_atomic_state(_state);
7743         struct drm_i915_private *dev_priv = to_i915(dev);
7744         int ret = 0;
7745
7746         state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
7747
7748         drm_atomic_state_get(&state->base);
7749         i915_sw_fence_init(&state->commit_ready,
7750                            intel_atomic_commit_ready);
7751
7752         /*
7753          * The intel_legacy_cursor_update() fast path takes care
7754          * of avoiding the vblank waits for simple cursor
7755          * movement and flips. For cursor on/off and size changes,
7756          * we want to perform the vblank waits so that watermark
7757          * updates happen during the correct frames. Gen9+ have
7758          * double buffered watermarks and so shouldn't need this.
7759          *
7760          * Unset state->legacy_cursor_update before the call to
7761          * drm_atomic_helper_setup_commit() because otherwise
7762          * drm_atomic_helper_wait_for_flip_done() is a noop and
7763          * we get FIFO underruns because we didn't wait
7764          * for vblank.
7765          *
7766          * FIXME doing watermarks and fb cleanup from a vblank worker
7767          * (assuming we had any) would solve these problems.
7768          */
7769         if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {
7770                 struct intel_crtc_state *new_crtc_state;
7771                 struct intel_crtc *crtc;
7772                 int i;
7773
7774                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7775                         if (new_crtc_state->wm.need_postvbl_update ||
7776                             new_crtc_state->update_wm_post)
7777                                 state->base.legacy_cursor_update = false;
7778         }
7779
7780         ret = intel_atomic_prepare_commit(state);
7781         if (ret) {
7782                 drm_dbg_atomic(&dev_priv->drm,
7783                                "Preparing state failed with %i\n", ret);
7784                 i915_sw_fence_commit(&state->commit_ready);
7785                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7786                 return ret;
7787         }
7788
7789         ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
7790         if (!ret)
7791                 ret = drm_atomic_helper_swap_state(&state->base, true);
7792         if (!ret)
7793                 intel_atomic_swap_global_state(state);
7794
7795         if (ret) {
7796                 struct intel_crtc_state *new_crtc_state;
7797                 struct intel_crtc *crtc;
7798                 int i;
7799
7800                 i915_sw_fence_commit(&state->commit_ready);
7801
7802                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7803                         intel_dsb_cleanup(new_crtc_state);
7804
7805                 drm_atomic_helper_cleanup_planes(dev, &state->base);
7806                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7807                 return ret;
7808         }
7809         intel_shared_dpll_swap_state(state);
7810         intel_atomic_track_fbs(state);
7811
7812         drm_atomic_state_get(&state->base);
7813         INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
7814
7815         i915_sw_fence_commit(&state->commit_ready);
7816         if (nonblock && state->modeset) {
7817                 queue_work(dev_priv->modeset_wq, &state->base.commit_work);
7818         } else if (nonblock) {
7819                 queue_work(dev_priv->flip_wq, &state->base.commit_work);
7820         } else {
7821                 if (state->modeset)
7822                         flush_workqueue(dev_priv->modeset_wq);
7823                 intel_atomic_commit_tail(state);
7824         }
7825
7826         return 0;
7827 }
7828
7829 /**
7830  * intel_plane_destroy - destroy a plane
7831  * @plane: plane to destroy
7832  *
7833  * Common destruction function for all types of planes (primary, cursor,
7834  * sprite).
7835  */
7836 void intel_plane_destroy(struct drm_plane *plane)
7837 {
7838         drm_plane_cleanup(plane);
7839         kfree(to_intel_plane(plane));
7840 }
7841
7842 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
7843 {
7844         struct intel_plane *plane;
7845
7846         for_each_intel_plane(&dev_priv->drm, plane) {
7847                 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv,
7848                                                               plane->pipe);
7849
7850                 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
7851         }
7852 }
7853
7854
7855 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
7856                                       struct drm_file *file)
7857 {
7858         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7859         struct drm_crtc *drmmode_crtc;
7860         struct intel_crtc *crtc;
7861
7862         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
7863         if (!drmmode_crtc)
7864                 return -ENOENT;
7865
7866         crtc = to_intel_crtc(drmmode_crtc);
7867         pipe_from_crtc_id->pipe = crtc->pipe;
7868
7869         return 0;
7870 }
7871
7872 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
7873 {
7874         struct drm_device *dev = encoder->base.dev;
7875         struct intel_encoder *source_encoder;
7876         u32 possible_clones = 0;
7877
7878         for_each_intel_encoder(dev, source_encoder) {
7879                 if (encoders_cloneable(encoder, source_encoder))
7880                         possible_clones |= drm_encoder_mask(&source_encoder->base);
7881         }
7882
7883         return possible_clones;
7884 }
7885
7886 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
7887 {
7888         struct drm_device *dev = encoder->base.dev;
7889         struct intel_crtc *crtc;
7890         u32 possible_crtcs = 0;
7891
7892         for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask)
7893                 possible_crtcs |= drm_crtc_mask(&crtc->base);
7894
7895         return possible_crtcs;
7896 }
7897
7898 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
7899 {
7900         if (!IS_MOBILE(dev_priv))
7901                 return false;
7902
7903         if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
7904                 return false;
7905
7906         if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
7907                 return false;
7908
7909         return true;
7910 }
7911
7912 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
7913 {
7914         if (DISPLAY_VER(dev_priv) >= 9)
7915                 return false;
7916
7917         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
7918                 return false;
7919
7920         if (HAS_PCH_LPT_H(dev_priv) &&
7921             intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
7922                 return false;
7923
7924         /* DDI E can't be used if DDI A requires 4 lanes */
7925         if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
7926                 return false;
7927
7928         if (!dev_priv->vbt.int_crt_support)
7929                 return false;
7930
7931         return true;
7932 }
7933
7934 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
7935 {
7936         struct intel_encoder *encoder;
7937         bool dpd_is_edp = false;
7938
7939         intel_pps_unlock_regs_wa(dev_priv);
7940
7941         if (!HAS_DISPLAY(dev_priv))
7942                 return;
7943
7944         if (IS_DG2(dev_priv)) {
7945                 intel_ddi_init(dev_priv, PORT_A);
7946                 intel_ddi_init(dev_priv, PORT_B);
7947                 intel_ddi_init(dev_priv, PORT_C);
7948                 intel_ddi_init(dev_priv, PORT_D_XELPD);
7949                 intel_ddi_init(dev_priv, PORT_TC1);
7950         } else if (IS_ALDERLAKE_P(dev_priv)) {
7951                 intel_ddi_init(dev_priv, PORT_A);
7952                 intel_ddi_init(dev_priv, PORT_B);
7953                 intel_ddi_init(dev_priv, PORT_TC1);
7954                 intel_ddi_init(dev_priv, PORT_TC2);
7955                 intel_ddi_init(dev_priv, PORT_TC3);
7956                 intel_ddi_init(dev_priv, PORT_TC4);
7957                 icl_dsi_init(dev_priv);
7958         } else if (IS_ALDERLAKE_S(dev_priv)) {
7959                 intel_ddi_init(dev_priv, PORT_A);
7960                 intel_ddi_init(dev_priv, PORT_TC1);
7961                 intel_ddi_init(dev_priv, PORT_TC2);
7962                 intel_ddi_init(dev_priv, PORT_TC3);
7963                 intel_ddi_init(dev_priv, PORT_TC4);
7964         } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
7965                 intel_ddi_init(dev_priv, PORT_A);
7966                 intel_ddi_init(dev_priv, PORT_B);
7967                 intel_ddi_init(dev_priv, PORT_TC1);
7968                 intel_ddi_init(dev_priv, PORT_TC2);
7969         } else if (DISPLAY_VER(dev_priv) >= 12) {
7970                 intel_ddi_init(dev_priv, PORT_A);
7971                 intel_ddi_init(dev_priv, PORT_B);
7972                 intel_ddi_init(dev_priv, PORT_TC1);
7973                 intel_ddi_init(dev_priv, PORT_TC2);
7974                 intel_ddi_init(dev_priv, PORT_TC3);
7975                 intel_ddi_init(dev_priv, PORT_TC4);
7976                 intel_ddi_init(dev_priv, PORT_TC5);
7977                 intel_ddi_init(dev_priv, PORT_TC6);
7978                 icl_dsi_init(dev_priv);
7979         } else if (IS_JSL_EHL(dev_priv)) {
7980                 intel_ddi_init(dev_priv, PORT_A);
7981                 intel_ddi_init(dev_priv, PORT_B);
7982                 intel_ddi_init(dev_priv, PORT_C);
7983                 intel_ddi_init(dev_priv, PORT_D);
7984                 icl_dsi_init(dev_priv);
7985         } else if (DISPLAY_VER(dev_priv) == 11) {
7986                 intel_ddi_init(dev_priv, PORT_A);
7987                 intel_ddi_init(dev_priv, PORT_B);
7988                 intel_ddi_init(dev_priv, PORT_C);
7989                 intel_ddi_init(dev_priv, PORT_D);
7990                 intel_ddi_init(dev_priv, PORT_E);
7991                 intel_ddi_init(dev_priv, PORT_F);
7992                 icl_dsi_init(dev_priv);
7993         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
7994                 intel_ddi_init(dev_priv, PORT_A);
7995                 intel_ddi_init(dev_priv, PORT_B);
7996                 intel_ddi_init(dev_priv, PORT_C);
7997                 vlv_dsi_init(dev_priv);
7998         } else if (DISPLAY_VER(dev_priv) >= 9) {
7999                 intel_ddi_init(dev_priv, PORT_A);
8000                 intel_ddi_init(dev_priv, PORT_B);
8001                 intel_ddi_init(dev_priv, PORT_C);
8002                 intel_ddi_init(dev_priv, PORT_D);
8003                 intel_ddi_init(dev_priv, PORT_E);
8004         } else if (HAS_DDI(dev_priv)) {
8005                 u32 found;
8006
8007                 if (intel_ddi_crt_present(dev_priv))
8008                         intel_crt_init(dev_priv);
8009
8010                 /* Haswell uses DDI functions to detect digital outputs. */
8011                 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
8012                 if (found)
8013                         intel_ddi_init(dev_priv, PORT_A);
8014
8015                 found = intel_de_read(dev_priv, SFUSE_STRAP);
8016                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8017                         intel_ddi_init(dev_priv, PORT_B);
8018                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8019                         intel_ddi_init(dev_priv, PORT_C);
8020                 if (found & SFUSE_STRAP_DDID_DETECTED)
8021                         intel_ddi_init(dev_priv, PORT_D);
8022                 if (found & SFUSE_STRAP_DDIF_DETECTED)
8023                         intel_ddi_init(dev_priv, PORT_F);
8024         } else if (HAS_PCH_SPLIT(dev_priv)) {
8025                 int found;
8026
8027                 /*
8028                  * intel_edp_init_connector() depends on this completing first,
8029                  * to prevent the registration of both eDP and LVDS and the
8030                  * incorrect sharing of the PPS.
8031                  */
8032                 intel_lvds_init(dev_priv);
8033                 intel_crt_init(dev_priv);
8034
8035                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
8036
8037                 if (ilk_has_edp_a(dev_priv))
8038                         g4x_dp_init(dev_priv, DP_A, PORT_A);
8039
8040                 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
8041                         /* PCH SDVOB multiplex with HDMIB */
8042                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
8043                         if (!found)
8044                                 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
8045                         if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
8046                                 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
8047                 }
8048
8049                 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
8050                         g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
8051
8052                 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
8053                         g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
8054
8055                 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
8056                         g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
8057
8058                 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
8059                         g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
8060         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
8061                 bool has_edp, has_port;
8062
8063                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
8064                         intel_crt_init(dev_priv);
8065
8066                 /*
8067                  * The DP_DETECTED bit is the latched state of the DDC
8068                  * SDA pin at boot. However since eDP doesn't require DDC
8069                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
8070                  * eDP ports may have been muxed to an alternate function.
8071                  * Thus we can't rely on the DP_DETECTED bit alone to detect
8072                  * eDP ports. Consult the VBT as well as DP_DETECTED to
8073                  * detect eDP ports.
8074                  *
8075                  * Sadly the straps seem to be missing sometimes even for HDMI
8076                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
8077                  * and VBT for the presence of the port. Additionally we can't
8078                  * trust the port type the VBT declares as we've seen at least
8079                  * HDMI ports that the VBT claim are DP or eDP.
8080                  */
8081                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
8082                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
8083                 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
8084                         has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
8085                 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
8086                         g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
8087
8088                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
8089                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
8090                 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
8091                         has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
8092                 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
8093                         g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
8094
8095                 if (IS_CHERRYVIEW(dev_priv)) {
8096                         /*
8097                          * eDP not supported on port D,
8098                          * so no need to worry about it
8099                          */
8100                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
8101                         if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
8102                                 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
8103                         if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
8104                                 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
8105                 }
8106
8107                 vlv_dsi_init(dev_priv);
8108         } else if (IS_PINEVIEW(dev_priv)) {
8109                 intel_lvds_init(dev_priv);
8110                 intel_crt_init(dev_priv);
8111         } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
8112                 bool found = false;
8113
8114                 if (IS_MOBILE(dev_priv))
8115                         intel_lvds_init(dev_priv);
8116
8117                 intel_crt_init(dev_priv);
8118
8119                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
8120                         drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
8121                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
8122                         if (!found && IS_G4X(dev_priv)) {
8123                                 drm_dbg_kms(&dev_priv->drm,
8124                                             "probing HDMI on SDVOB\n");
8125                                 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
8126                         }
8127
8128                         if (!found && IS_G4X(dev_priv))
8129                                 g4x_dp_init(dev_priv, DP_B, PORT_B);
8130                 }
8131
8132                 /* Before G4X SDVOC doesn't have its own detect register */
8133
8134                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
8135                         drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
8136                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
8137                 }
8138
8139                 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
8140
8141                         if (IS_G4X(dev_priv)) {
8142                                 drm_dbg_kms(&dev_priv->drm,
8143                                             "probing HDMI on SDVOC\n");
8144                                 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
8145                         }
8146                         if (IS_G4X(dev_priv))
8147                                 g4x_dp_init(dev_priv, DP_C, PORT_C);
8148                 }
8149
8150                 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
8151                         g4x_dp_init(dev_priv, DP_D, PORT_D);
8152
8153                 if (SUPPORTS_TV(dev_priv))
8154                         intel_tv_init(dev_priv);
8155         } else if (DISPLAY_VER(dev_priv) == 2) {
8156                 if (IS_I85X(dev_priv))
8157                         intel_lvds_init(dev_priv);
8158
8159                 intel_crt_init(dev_priv);
8160                 intel_dvo_init(dev_priv);
8161         }
8162
8163         for_each_intel_encoder(&dev_priv->drm, encoder) {
8164                 encoder->base.possible_crtcs =
8165                         intel_encoder_possible_crtcs(encoder);
8166                 encoder->base.possible_clones =
8167                         intel_encoder_possible_clones(encoder);
8168         }
8169
8170         intel_init_pch_refclk(dev_priv);
8171
8172         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
8173 }
8174
8175 static enum drm_mode_status
8176 intel_mode_valid(struct drm_device *dev,
8177                  const struct drm_display_mode *mode)
8178 {
8179         struct drm_i915_private *dev_priv = to_i915(dev);
8180         int hdisplay_max, htotal_max;
8181         int vdisplay_max, vtotal_max;
8182
8183         /*
8184          * Can't reject DBLSCAN here because Xorg ddxen can add piles
8185          * of DBLSCAN modes to the output's mode list when they detect
8186          * the scaling mode property on the connector. And they don't
8187          * ask the kernel to validate those modes in any way until
8188          * modeset time at which point the client gets a protocol error.
8189          * So in order to not upset those clients we silently ignore the
8190          * DBLSCAN flag on such connectors. For other connectors we will
8191          * reject modes with the DBLSCAN flag in encoder->compute_config().
8192          * And we always reject DBLSCAN modes in connector->mode_valid()
8193          * as we never want such modes on the connector's mode list.
8194          */
8195
8196         if (mode->vscan > 1)
8197                 return MODE_NO_VSCAN;
8198
8199         if (mode->flags & DRM_MODE_FLAG_HSKEW)
8200                 return MODE_H_ILLEGAL;
8201
8202         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
8203                            DRM_MODE_FLAG_NCSYNC |
8204                            DRM_MODE_FLAG_PCSYNC))
8205                 return MODE_HSYNC;
8206
8207         if (mode->flags & (DRM_MODE_FLAG_BCAST |
8208                            DRM_MODE_FLAG_PIXMUX |
8209                            DRM_MODE_FLAG_CLKDIV2))
8210                 return MODE_BAD;
8211
8212         /* Transcoder timing limits */
8213         if (DISPLAY_VER(dev_priv) >= 11) {
8214                 hdisplay_max = 16384;
8215                 vdisplay_max = 8192;
8216                 htotal_max = 16384;
8217                 vtotal_max = 8192;
8218         } else if (DISPLAY_VER(dev_priv) >= 9 ||
8219                    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
8220                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
8221                 vdisplay_max = 4096;
8222                 htotal_max = 8192;
8223                 vtotal_max = 8192;
8224         } else if (DISPLAY_VER(dev_priv) >= 3) {
8225                 hdisplay_max = 4096;
8226                 vdisplay_max = 4096;
8227                 htotal_max = 8192;
8228                 vtotal_max = 8192;
8229         } else {
8230                 hdisplay_max = 2048;
8231                 vdisplay_max = 2048;
8232                 htotal_max = 4096;
8233                 vtotal_max = 4096;
8234         }
8235
8236         if (mode->hdisplay > hdisplay_max ||
8237             mode->hsync_start > htotal_max ||
8238             mode->hsync_end > htotal_max ||
8239             mode->htotal > htotal_max)
8240                 return MODE_H_ILLEGAL;
8241
8242         if (mode->vdisplay > vdisplay_max ||
8243             mode->vsync_start > vtotal_max ||
8244             mode->vsync_end > vtotal_max ||
8245             mode->vtotal > vtotal_max)
8246                 return MODE_V_ILLEGAL;
8247
8248         if (DISPLAY_VER(dev_priv) >= 5) {
8249                 if (mode->hdisplay < 64 ||
8250                     mode->htotal - mode->hdisplay < 32)
8251                         return MODE_H_ILLEGAL;
8252
8253                 if (mode->vtotal - mode->vdisplay < 5)
8254                         return MODE_V_ILLEGAL;
8255         } else {
8256                 if (mode->htotal - mode->hdisplay < 32)
8257                         return MODE_H_ILLEGAL;
8258
8259                 if (mode->vtotal - mode->vdisplay < 3)
8260                         return MODE_V_ILLEGAL;
8261         }
8262
8263         /*
8264          * Cantiga+ cannot handle modes with a hsync front porch of 0.
8265          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
8266          */
8267         if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) &&
8268             mode->hsync_start == mode->hdisplay)
8269                 return MODE_H_ILLEGAL;
8270
8271         return MODE_OK;
8272 }
8273
8274 enum drm_mode_status
8275 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
8276                                 const struct drm_display_mode *mode,
8277                                 bool bigjoiner)
8278 {
8279         int plane_width_max, plane_height_max;
8280
8281         /*
8282          * intel_mode_valid() should be
8283          * sufficient on older platforms.
8284          */
8285         if (DISPLAY_VER(dev_priv) < 9)
8286                 return MODE_OK;
8287
8288         /*
8289          * Most people will probably want a fullscreen
8290          * plane so let's not advertize modes that are
8291          * too big for that.
8292          */
8293         if (DISPLAY_VER(dev_priv) >= 11) {
8294                 plane_width_max = 5120 << bigjoiner;
8295                 plane_height_max = 4320;
8296         } else {
8297                 plane_width_max = 5120;
8298                 plane_height_max = 4096;
8299         }
8300
8301         if (mode->hdisplay > plane_width_max)
8302                 return MODE_H_ILLEGAL;
8303
8304         if (mode->vdisplay > plane_height_max)
8305                 return MODE_V_ILLEGAL;
8306
8307         return MODE_OK;
8308 }
8309
8310 static const struct drm_mode_config_funcs intel_mode_funcs = {
8311         .fb_create = intel_user_framebuffer_create,
8312         .get_format_info = intel_fb_get_format_info,
8313         .output_poll_changed = intel_fbdev_output_poll_changed,
8314         .mode_valid = intel_mode_valid,
8315         .atomic_check = intel_atomic_check,
8316         .atomic_commit = intel_atomic_commit,
8317         .atomic_state_alloc = intel_atomic_state_alloc,
8318         .atomic_state_clear = intel_atomic_state_clear,
8319         .atomic_state_free = intel_atomic_state_free,
8320 };
8321
8322 static const struct drm_i915_display_funcs skl_display_funcs = {
8323         .get_pipe_config = hsw_get_pipe_config,
8324         .crtc_enable = hsw_crtc_enable,
8325         .crtc_disable = hsw_crtc_disable,
8326         .commit_modeset_enables = skl_commit_modeset_enables,
8327         .get_initial_plane_config = skl_get_initial_plane_config,
8328 };
8329
8330 static const struct drm_i915_display_funcs ddi_display_funcs = {
8331         .get_pipe_config = hsw_get_pipe_config,
8332         .crtc_enable = hsw_crtc_enable,
8333         .crtc_disable = hsw_crtc_disable,
8334         .commit_modeset_enables = intel_commit_modeset_enables,
8335         .get_initial_plane_config = i9xx_get_initial_plane_config,
8336 };
8337
8338 static const struct drm_i915_display_funcs pch_split_display_funcs = {
8339         .get_pipe_config = ilk_get_pipe_config,
8340         .crtc_enable = ilk_crtc_enable,
8341         .crtc_disable = ilk_crtc_disable,
8342         .commit_modeset_enables = intel_commit_modeset_enables,
8343         .get_initial_plane_config = i9xx_get_initial_plane_config,
8344 };
8345
8346 static const struct drm_i915_display_funcs vlv_display_funcs = {
8347         .get_pipe_config = i9xx_get_pipe_config,
8348         .crtc_enable = valleyview_crtc_enable,
8349         .crtc_disable = i9xx_crtc_disable,
8350         .commit_modeset_enables = intel_commit_modeset_enables,
8351         .get_initial_plane_config = i9xx_get_initial_plane_config,
8352 };
8353
8354 static const struct drm_i915_display_funcs i9xx_display_funcs = {
8355         .get_pipe_config = i9xx_get_pipe_config,
8356         .crtc_enable = i9xx_crtc_enable,
8357         .crtc_disable = i9xx_crtc_disable,
8358         .commit_modeset_enables = intel_commit_modeset_enables,
8359         .get_initial_plane_config = i9xx_get_initial_plane_config,
8360 };
8361
8362 /**
8363  * intel_init_display_hooks - initialize the display modesetting hooks
8364  * @dev_priv: device private
8365  */
8366 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
8367 {
8368         if (!HAS_DISPLAY(dev_priv))
8369                 return;
8370
8371         intel_init_cdclk_hooks(dev_priv);
8372         intel_audio_hooks_init(dev_priv);
8373
8374         intel_dpll_init_clock_hook(dev_priv);
8375
8376         if (DISPLAY_VER(dev_priv) >= 9) {
8377                 dev_priv->display = &skl_display_funcs;
8378         } else if (HAS_DDI(dev_priv)) {
8379                 dev_priv->display = &ddi_display_funcs;
8380         } else if (HAS_PCH_SPLIT(dev_priv)) {
8381                 dev_priv->display = &pch_split_display_funcs;
8382         } else if (IS_CHERRYVIEW(dev_priv) ||
8383                    IS_VALLEYVIEW(dev_priv)) {
8384                 dev_priv->display = &vlv_display_funcs;
8385         } else {
8386                 dev_priv->display = &i9xx_display_funcs;
8387         }
8388
8389         intel_fdi_init_hook(dev_priv);
8390 }
8391
8392 void intel_modeset_init_hw(struct drm_i915_private *i915)
8393 {
8394         struct intel_cdclk_state *cdclk_state;
8395
8396         if (!HAS_DISPLAY(i915))
8397                 return;
8398
8399         cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state);
8400
8401         intel_update_cdclk(i915);
8402         intel_cdclk_dump_config(i915, &i915->cdclk.hw, "Current CDCLK");
8403         cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
8404 }
8405
8406 static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
8407 {
8408         struct drm_plane *plane;
8409         struct intel_crtc *crtc;
8410
8411         for_each_intel_crtc(state->dev, crtc) {
8412                 struct intel_crtc_state *crtc_state;
8413
8414                 crtc_state = intel_atomic_get_crtc_state(state, crtc);
8415                 if (IS_ERR(crtc_state))
8416                         return PTR_ERR(crtc_state);
8417
8418                 if (crtc_state->hw.active) {
8419                         /*
8420                          * Preserve the inherited flag to avoid
8421                          * taking the full modeset path.
8422                          */
8423                         crtc_state->inherited = true;
8424                 }
8425         }
8426
8427         drm_for_each_plane(plane, state->dev) {
8428                 struct drm_plane_state *plane_state;
8429
8430                 plane_state = drm_atomic_get_plane_state(state, plane);
8431                 if (IS_ERR(plane_state))
8432                         return PTR_ERR(plane_state);
8433         }
8434
8435         return 0;
8436 }
8437
8438 /*
8439  * Calculate what we think the watermarks should be for the state we've read
8440  * out of the hardware and then immediately program those watermarks so that
8441  * we ensure the hardware settings match our internal state.
8442  *
8443  * We can calculate what we think WM's should be by creating a duplicate of the
8444  * current state (which was constructed during hardware readout) and running it
8445  * through the atomic check code to calculate new watermark values in the
8446  * state object.
8447  */
8448 static void sanitize_watermarks(struct drm_i915_private *dev_priv)
8449 {
8450         struct drm_atomic_state *state;
8451         struct intel_atomic_state *intel_state;
8452         struct intel_crtc *crtc;
8453         struct intel_crtc_state *crtc_state;
8454         struct drm_modeset_acquire_ctx ctx;
8455         int ret;
8456         int i;
8457
8458         /* Only supported on platforms that use atomic watermark design */
8459         if (!dev_priv->wm_disp->optimize_watermarks)
8460                 return;
8461
8462         state = drm_atomic_state_alloc(&dev_priv->drm);
8463         if (drm_WARN_ON(&dev_priv->drm, !state))
8464                 return;
8465
8466         intel_state = to_intel_atomic_state(state);
8467
8468         drm_modeset_acquire_init(&ctx, 0);
8469
8470 retry:
8471         state->acquire_ctx = &ctx;
8472
8473         /*
8474          * Hardware readout is the only time we don't want to calculate
8475          * intermediate watermarks (since we don't trust the current
8476          * watermarks).
8477          */
8478         if (!HAS_GMCH(dev_priv))
8479                 intel_state->skip_intermediate_wm = true;
8480
8481         ret = sanitize_watermarks_add_affected(state);
8482         if (ret)
8483                 goto fail;
8484
8485         ret = intel_atomic_check(&dev_priv->drm, state);
8486         if (ret)
8487                 goto fail;
8488
8489         /* Write calculated watermark values back */
8490         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
8491                 crtc_state->wm.need_postvbl_update = true;
8492                 intel_optimize_watermarks(intel_state, crtc);
8493
8494                 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
8495         }
8496
8497 fail:
8498         if (ret == -EDEADLK) {
8499                 drm_atomic_state_clear(state);
8500                 drm_modeset_backoff(&ctx);
8501                 goto retry;
8502         }
8503
8504         /*
8505          * If we fail here, it means that the hardware appears to be
8506          * programmed in a way that shouldn't be possible, given our
8507          * understanding of watermark requirements.  This might mean a
8508          * mistake in the hardware readout code or a mistake in the
8509          * watermark calculations for a given platform.  Raise a WARN
8510          * so that this is noticeable.
8511          *
8512          * If this actually happens, we'll have to just leave the
8513          * BIOS-programmed watermarks untouched and hope for the best.
8514          */
8515         drm_WARN(&dev_priv->drm, ret,
8516                  "Could not determine valid watermarks for inherited state\n");
8517
8518         drm_atomic_state_put(state);
8519
8520         drm_modeset_drop_locks(&ctx);
8521         drm_modeset_acquire_fini(&ctx);
8522 }
8523
8524 static int intel_initial_commit(struct drm_device *dev)
8525 {
8526         struct drm_atomic_state *state = NULL;
8527         struct drm_modeset_acquire_ctx ctx;
8528         struct intel_crtc *crtc;
8529         int ret = 0;
8530
8531         state = drm_atomic_state_alloc(dev);
8532         if (!state)
8533                 return -ENOMEM;
8534
8535         drm_modeset_acquire_init(&ctx, 0);
8536
8537 retry:
8538         state->acquire_ctx = &ctx;
8539
8540         for_each_intel_crtc(dev, crtc) {
8541                 struct intel_crtc_state *crtc_state =
8542                         intel_atomic_get_crtc_state(state, crtc);
8543
8544                 if (IS_ERR(crtc_state)) {
8545                         ret = PTR_ERR(crtc_state);
8546                         goto out;
8547                 }
8548
8549                 if (crtc_state->hw.active) {
8550                         struct intel_encoder *encoder;
8551
8552                         /*
8553                          * We've not yet detected sink capabilities
8554                          * (audio,infoframes,etc.) and thus we don't want to
8555                          * force a full state recomputation yet. We want that to
8556                          * happen only for the first real commit from userspace.
8557                          * So preserve the inherited flag for the time being.
8558                          */
8559                         crtc_state->inherited = true;
8560
8561                         ret = drm_atomic_add_affected_planes(state, &crtc->base);
8562                         if (ret)
8563                                 goto out;
8564
8565                         /*
8566                          * FIXME hack to force a LUT update to avoid the
8567                          * plane update forcing the pipe gamma on without
8568                          * having a proper LUT loaded. Remove once we
8569                          * have readout for pipe gamma enable.
8570                          */
8571                         crtc_state->uapi.color_mgmt_changed = true;
8572
8573                         for_each_intel_encoder_mask(dev, encoder,
8574                                                     crtc_state->uapi.encoder_mask) {
8575                                 if (encoder->initial_fastset_check &&
8576                                     !encoder->initial_fastset_check(encoder, crtc_state)) {
8577                                         ret = drm_atomic_add_affected_connectors(state,
8578                                                                                  &crtc->base);
8579                                         if (ret)
8580                                                 goto out;
8581                                 }
8582                         }
8583                 }
8584         }
8585
8586         ret = drm_atomic_commit(state);
8587
8588 out:
8589         if (ret == -EDEADLK) {
8590                 drm_atomic_state_clear(state);
8591                 drm_modeset_backoff(&ctx);
8592                 goto retry;
8593         }
8594
8595         drm_atomic_state_put(state);
8596
8597         drm_modeset_drop_locks(&ctx);
8598         drm_modeset_acquire_fini(&ctx);
8599
8600         return ret;
8601 }
8602
8603 static void intel_mode_config_init(struct drm_i915_private *i915)
8604 {
8605         struct drm_mode_config *mode_config = &i915->drm.mode_config;
8606
8607         drm_mode_config_init(&i915->drm);
8608         INIT_LIST_HEAD(&i915->global_obj_list);
8609
8610         mode_config->min_width = 0;
8611         mode_config->min_height = 0;
8612
8613         mode_config->preferred_depth = 24;
8614         mode_config->prefer_shadow = 1;
8615
8616         mode_config->funcs = &intel_mode_funcs;
8617
8618         mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915);
8619
8620         /*
8621          * Maximum framebuffer dimensions, chosen to match
8622          * the maximum render engine surface size on gen4+.
8623          */
8624         if (DISPLAY_VER(i915) >= 7) {
8625                 mode_config->max_width = 16384;
8626                 mode_config->max_height = 16384;
8627         } else if (DISPLAY_VER(i915) >= 4) {
8628                 mode_config->max_width = 8192;
8629                 mode_config->max_height = 8192;
8630         } else if (DISPLAY_VER(i915) == 3) {
8631                 mode_config->max_width = 4096;
8632                 mode_config->max_height = 4096;
8633         } else {
8634                 mode_config->max_width = 2048;
8635                 mode_config->max_height = 2048;
8636         }
8637
8638         if (IS_I845G(i915) || IS_I865G(i915)) {
8639                 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
8640                 mode_config->cursor_height = 1023;
8641         } else if (IS_I830(i915) || IS_I85X(i915) ||
8642                    IS_I915G(i915) || IS_I915GM(i915)) {
8643                 mode_config->cursor_width = 64;
8644                 mode_config->cursor_height = 64;
8645         } else {
8646                 mode_config->cursor_width = 256;
8647                 mode_config->cursor_height = 256;
8648         }
8649 }
8650
8651 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
8652 {
8653         intel_atomic_global_obj_cleanup(i915);
8654         drm_mode_config_cleanup(&i915->drm);
8655 }
8656
8657 /* part #1: call before irq install */
8658 int intel_modeset_init_noirq(struct drm_i915_private *i915)
8659 {
8660         int ret;
8661
8662         if (i915_inject_probe_failure(i915))
8663                 return -ENODEV;
8664
8665         if (HAS_DISPLAY(i915)) {
8666                 ret = drm_vblank_init(&i915->drm,
8667                                       INTEL_NUM_PIPES(i915));
8668                 if (ret)
8669                         return ret;
8670         }
8671
8672         intel_bios_init(i915);
8673
8674         ret = intel_vga_register(i915);
8675         if (ret)
8676                 goto cleanup_bios;
8677
8678         /* FIXME: completely on the wrong abstraction layer */
8679         intel_power_domains_init_hw(i915, false);
8680
8681         if (!HAS_DISPLAY(i915))
8682                 return 0;
8683
8684         intel_dmc_ucode_init(i915);
8685
8686         i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
8687         i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
8688                                         WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
8689
8690         i915->window2_delay = 0; /* No DSB so no window2 delay */
8691
8692         intel_mode_config_init(i915);
8693
8694         ret = intel_cdclk_init(i915);
8695         if (ret)
8696                 goto cleanup_vga_client_pw_domain_dmc;
8697
8698         ret = intel_dbuf_init(i915);
8699         if (ret)
8700                 goto cleanup_vga_client_pw_domain_dmc;
8701
8702         ret = intel_bw_init(i915);
8703         if (ret)
8704                 goto cleanup_vga_client_pw_domain_dmc;
8705
8706         init_llist_head(&i915->atomic_helper.free_list);
8707         INIT_WORK(&i915->atomic_helper.free_work,
8708                   intel_atomic_helper_free_state_worker);
8709
8710         intel_init_quirks(i915);
8711
8712         intel_fbc_init(i915);
8713
8714         return 0;
8715
8716 cleanup_vga_client_pw_domain_dmc:
8717         intel_dmc_ucode_fini(i915);
8718         intel_power_domains_driver_remove(i915);
8719         intel_vga_unregister(i915);
8720 cleanup_bios:
8721         intel_bios_driver_remove(i915);
8722
8723         return ret;
8724 }
8725
8726 /* part #2: call after irq install, but before gem init */
8727 int intel_modeset_init_nogem(struct drm_i915_private *i915)
8728 {
8729         struct drm_device *dev = &i915->drm;
8730         enum pipe pipe;
8731         struct intel_crtc *crtc;
8732         int ret;
8733
8734         if (!HAS_DISPLAY(i915))
8735                 return 0;
8736
8737         intel_init_pm(i915);
8738
8739         intel_panel_sanitize_ssc(i915);
8740
8741         intel_pps_setup(i915);
8742
8743         intel_gmbus_setup(i915);
8744
8745         drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
8746                     INTEL_NUM_PIPES(i915),
8747                     INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
8748
8749         for_each_pipe(i915, pipe) {
8750                 ret = intel_crtc_init(i915, pipe);
8751                 if (ret) {
8752                         intel_mode_config_cleanup(i915);
8753                         return ret;
8754                 }
8755         }
8756
8757         intel_plane_possible_crtcs_init(i915);
8758         intel_shared_dpll_init(i915);
8759         intel_fdi_pll_freq_update(i915);
8760
8761         intel_update_czclk(i915);
8762         intel_modeset_init_hw(i915);
8763         intel_dpll_update_ref_clks(i915);
8764
8765         intel_hdcp_component_init(i915);
8766
8767         if (i915->max_cdclk_freq == 0)
8768                 intel_update_max_cdclk(i915);
8769
8770         /*
8771          * If the platform has HTI, we need to find out whether it has reserved
8772          * any display resources before we create our display outputs.
8773          */
8774         if (INTEL_INFO(i915)->display.has_hti)
8775                 i915->hti_state = intel_de_read(i915, HDPORT_STATE);
8776
8777         /* Just disable it once at startup */
8778         intel_vga_disable(i915);
8779         intel_setup_outputs(i915);
8780
8781         drm_modeset_lock_all(dev);
8782         intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx);
8783         intel_acpi_assign_connector_fwnodes(i915);
8784         drm_modeset_unlock_all(dev);
8785
8786         for_each_intel_crtc(dev, crtc) {
8787                 if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
8788                         continue;
8789                 intel_crtc_initial_plane_config(crtc);
8790         }
8791
8792         /*
8793          * Make sure hardware watermarks really match the state we read out.
8794          * Note that we need to do this after reconstructing the BIOS fb's
8795          * since the watermark calculation done here will use pstate->fb.
8796          */
8797         if (!HAS_GMCH(i915))
8798                 sanitize_watermarks(i915);
8799
8800         return 0;
8801 }
8802
8803 /* part #3: call after gem init */
8804 int intel_modeset_init(struct drm_i915_private *i915)
8805 {
8806         int ret;
8807
8808         if (!HAS_DISPLAY(i915))
8809                 return 0;
8810
8811         /*
8812          * Force all active planes to recompute their states. So that on
8813          * mode_setcrtc after probe, all the intel_plane_state variables
8814          * are already calculated and there is no assert_plane warnings
8815          * during bootup.
8816          */
8817         ret = intel_initial_commit(&i915->drm);
8818         if (ret)
8819                 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret);
8820
8821         intel_overlay_setup(i915);
8822
8823         ret = intel_fbdev_init(&i915->drm);
8824         if (ret)
8825                 return ret;
8826
8827         /* Only enable hotplug handling once the fbdev is fully set up. */
8828         intel_hpd_init(i915);
8829         intel_hpd_poll_disable(i915);
8830
8831         intel_init_ipc(i915);
8832
8833         return 0;
8834 }
8835
8836 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
8837 {
8838         struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8839         /* 640x480@60Hz, ~25175 kHz */
8840         struct dpll clock = {
8841                 .m1 = 18,
8842                 .m2 = 7,
8843                 .p1 = 13,
8844                 .p2 = 4,
8845                 .n = 2,
8846         };
8847         u32 dpll, fp;
8848         int i;
8849
8850         drm_WARN_ON(&dev_priv->drm,
8851                     i9xx_calc_dpll_params(48000, &clock) != 25154);
8852
8853         drm_dbg_kms(&dev_priv->drm,
8854                     "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
8855                     pipe_name(pipe), clock.vco, clock.dot);
8856
8857         fp = i9xx_dpll_compute_fp(&clock);
8858         dpll = DPLL_DVO_2X_MODE |
8859                 DPLL_VGA_MODE_DIS |
8860                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
8861                 PLL_P2_DIVIDE_BY_4 |
8862                 PLL_REF_INPUT_DREFCLK |
8863                 DPLL_VCO_ENABLE;
8864
8865         intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
8866         intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
8867         intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
8868         intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
8869         intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
8870         intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
8871         intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
8872
8873         intel_de_write(dev_priv, FP0(pipe), fp);
8874         intel_de_write(dev_priv, FP1(pipe), fp);
8875
8876         /*
8877          * Apparently we need to have VGA mode enabled prior to changing
8878          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
8879          * dividers, even though the register value does change.
8880          */
8881         intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
8882         intel_de_write(dev_priv, DPLL(pipe), dpll);
8883
8884         /* Wait for the clocks to stabilize. */
8885         intel_de_posting_read(dev_priv, DPLL(pipe));
8886         udelay(150);
8887
8888         /* The pixel multiplier can only be updated once the
8889          * DPLL is enabled and the clocks are stable.
8890          *
8891          * So write it again.
8892          */
8893         intel_de_write(dev_priv, DPLL(pipe), dpll);
8894
8895         /* We do this three times for luck */
8896         for (i = 0; i < 3 ; i++) {
8897                 intel_de_write(dev_priv, DPLL(pipe), dpll);
8898                 intel_de_posting_read(dev_priv, DPLL(pipe));
8899                 udelay(150); /* wait for warmup */
8900         }
8901
8902         intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE);
8903         intel_de_posting_read(dev_priv, PIPECONF(pipe));
8904
8905         intel_wait_for_pipe_scanline_moving(crtc);
8906 }
8907
8908 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
8909 {
8910         struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8911
8912         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
8913                     pipe_name(pipe));
8914
8915         drm_WARN_ON(&dev_priv->drm,
8916                     intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE);
8917         drm_WARN_ON(&dev_priv->drm,
8918                     intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE);
8919         drm_WARN_ON(&dev_priv->drm,
8920                     intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE);
8921         drm_WARN_ON(&dev_priv->drm,
8922                     intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);
8923         drm_WARN_ON(&dev_priv->drm,
8924                     intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);
8925
8926         intel_de_write(dev_priv, PIPECONF(pipe), 0);
8927         intel_de_posting_read(dev_priv, PIPECONF(pipe));
8928
8929         intel_wait_for_pipe_scanline_stopped(crtc);
8930
8931         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
8932         intel_de_posting_read(dev_priv, DPLL(pipe));
8933 }
8934
8935 void intel_display_resume(struct drm_device *dev)
8936 {
8937         struct drm_i915_private *i915 = to_i915(dev);
8938         struct drm_atomic_state *state = i915->modeset_restore_state;
8939         struct drm_modeset_acquire_ctx ctx;
8940         int ret;
8941
8942         if (!HAS_DISPLAY(i915))
8943                 return;
8944
8945         i915->modeset_restore_state = NULL;
8946         if (state)
8947                 state->acquire_ctx = &ctx;
8948
8949         drm_modeset_acquire_init(&ctx, 0);
8950
8951         while (1) {
8952                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
8953                 if (ret != -EDEADLK)
8954                         break;
8955
8956                 drm_modeset_backoff(&ctx);
8957         }
8958
8959         if (!ret)
8960                 ret = __intel_display_resume(i915, state, &ctx);
8961
8962         intel_enable_ipc(i915);
8963         drm_modeset_drop_locks(&ctx);
8964         drm_modeset_acquire_fini(&ctx);
8965
8966         if (ret)
8967                 drm_err(&i915->drm,
8968                         "Restoring old state failed with %i\n", ret);
8969         if (state)
8970                 drm_atomic_state_put(state);
8971 }
8972
8973 static void intel_hpd_poll_fini(struct drm_i915_private *i915)
8974 {
8975         struct intel_connector *connector;
8976         struct drm_connector_list_iter conn_iter;
8977
8978         /* Kill all the work that may have been queued by hpd. */
8979         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
8980         for_each_intel_connector_iter(connector, &conn_iter) {
8981                 if (connector->modeset_retry_work.func)
8982                         cancel_work_sync(&connector->modeset_retry_work);
8983                 if (connector->hdcp.shim) {
8984                         cancel_delayed_work_sync(&connector->hdcp.check_work);
8985                         cancel_work_sync(&connector->hdcp.prop_work);
8986                 }
8987         }
8988         drm_connector_list_iter_end(&conn_iter);
8989 }
8990
8991 /* part #1: call before irq uninstall */
8992 void intel_modeset_driver_remove(struct drm_i915_private *i915)
8993 {
8994         if (!HAS_DISPLAY(i915))
8995                 return;
8996
8997         flush_workqueue(i915->flip_wq);
8998         flush_workqueue(i915->modeset_wq);
8999
9000         flush_work(&i915->atomic_helper.free_work);
9001         drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
9002 }
9003
9004 /* part #2: call after irq uninstall */
9005 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
9006 {
9007         if (!HAS_DISPLAY(i915))
9008                 return;
9009
9010         /*
9011          * Due to the hpd irq storm handling the hotplug work can re-arm the
9012          * poll handlers. Hence disable polling after hpd handling is shut down.
9013          */
9014         intel_hpd_poll_fini(i915);
9015
9016         /*
9017          * MST topology needs to be suspended so we don't have any calls to
9018          * fbdev after it's finalized. MST will be destroyed later as part of
9019          * drm_mode_config_cleanup()
9020          */
9021         intel_dp_mst_suspend(i915);
9022
9023         /* poll work can call into fbdev, hence clean that up afterwards */
9024         intel_fbdev_fini(i915);
9025
9026         intel_unregister_dsm_handler();
9027
9028         /* flush any delayed tasks or pending work */
9029         flush_scheduled_work();
9030
9031         intel_hdcp_component_fini(i915);
9032
9033         intel_mode_config_cleanup(i915);
9034
9035         intel_overlay_cleanup(i915);
9036
9037         intel_gmbus_teardown(i915);
9038
9039         destroy_workqueue(i915->flip_wq);
9040         destroy_workqueue(i915->modeset_wq);
9041
9042         intel_fbc_cleanup(i915);
9043 }
9044
9045 /* part #3: call after gem init */
9046 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915)
9047 {
9048         intel_dmc_ucode_fini(i915);
9049
9050         intel_power_domains_driver_remove(i915);
9051
9052         intel_vga_unregister(i915);
9053
9054         intel_bios_driver_remove(i915);
9055 }
9056
9057 bool intel_modeset_probe_defer(struct pci_dev *pdev)
9058 {
9059         struct drm_privacy_screen *privacy_screen;
9060
9061         /*
9062          * apple-gmux is needed on dual GPU MacBook Pro
9063          * to probe the panel if we're the inactive GPU.
9064          */
9065         if (vga_switcheroo_client_probe_defer(pdev))
9066                 return true;
9067
9068         /* If the LCD panel has a privacy-screen, wait for it */
9069         privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL);
9070         if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER)
9071                 return true;
9072
9073         drm_privacy_screen_put(privacy_screen);
9074
9075         return false;
9076 }
9077
9078 void intel_display_driver_register(struct drm_i915_private *i915)
9079 {
9080         if (!HAS_DISPLAY(i915))
9081                 return;
9082
9083         intel_display_debugfs_register(i915);
9084
9085         /* Must be done after probing outputs */
9086         intel_opregion_register(i915);
9087         acpi_video_register();
9088
9089         intel_audio_init(i915);
9090
9091         /*
9092          * Some ports require correctly set-up hpd registers for
9093          * detection to work properly (leading to ghost connected
9094          * connector status), e.g. VGA on gm45.  Hence we can only set
9095          * up the initial fbdev config after hpd irqs are fully
9096          * enabled. We do it last so that the async config cannot run
9097          * before the connectors are registered.
9098          */
9099         intel_fbdev_initial_config_async(&i915->drm);
9100
9101         /*
9102          * We need to coordinate the hotplugs with the asynchronous
9103          * fbdev configuration, for which we use the
9104          * fbdev->async_cookie.
9105          */
9106         drm_kms_helper_poll_init(&i915->drm);
9107 }
9108
9109 void intel_display_driver_unregister(struct drm_i915_private *i915)
9110 {
9111         if (!HAS_DISPLAY(i915))
9112                 return;
9113
9114         intel_fbdev_unregister(i915);
9115         intel_audio_deinit(i915);
9116
9117         /*
9118          * After flushing the fbdev (incl. a late async config which
9119          * will have delayed queuing of a hotplug event), then flush
9120          * the hotplug events.
9121          */
9122         drm_kms_helper_poll_fini(&i915->drm);
9123         drm_atomic_helper_shutdown(&i915->drm);
9124
9125         acpi_video_unregister();
9126         intel_opregion_unregister(i915);
9127 }
9128
9129 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915)
9130 {
9131         return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915);
9132 }