drivers/gpu/drm/i915/display/intel_csr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/firmware.h>
  26
  27 #include "i915_drv.h"
  28 #include "i915_reg.h"
  29 #include "intel_csr.h"
  30
  31 /**
  32  * DOC: csr support for dmc
  33  *
  34  * Display Context Save and Restore (CSR) firmware support added from gen9
  35  * onwards to drive newly added DMC (Display microcontroller) in display
  36  * engine to save and restore the state of display engine when it enter into
  37  * low-power state and comes back to normal.
  38  */
  39
  40 #define GEN12_CSR_MAX_FW_SIZE           ICL_CSR_MAX_FW_SIZE
  41
  42 #define TGL_CSR_PATH                    "i915/tgl_dmc_ver2_04.bin"
  43 #define TGL_CSR_VERSION_REQUIRED        CSR_VERSION(2, 4)
  44 #define TGL_CSR_MAX_FW_SIZE             0x6000
  45 MODULE_FIRMWARE(TGL_CSR_PATH);
  46
  47 #define ICL_CSR_PATH                    "i915/icl_dmc_ver1_09.bin"
  48 #define ICL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 9)
  49 #define ICL_CSR_MAX_FW_SIZE             0x6000
  50 MODULE_FIRMWARE(ICL_CSR_PATH);
  51
  52 #define CNL_CSR_PATH                    "i915/cnl_dmc_ver1_07.bin"
  53 #define CNL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 7)
  54 #define CNL_CSR_MAX_FW_SIZE             GLK_CSR_MAX_FW_SIZE
  55 MODULE_FIRMWARE(CNL_CSR_PATH);
  56
  57 #define GLK_CSR_PATH                    "i915/glk_dmc_ver1_04.bin"
  58 #define GLK_CSR_VERSION_REQUIRED        CSR_VERSION(1, 4)
  59 #define GLK_CSR_MAX_FW_SIZE             0x4000
  60 MODULE_FIRMWARE(GLK_CSR_PATH);
  61
  62 #define KBL_CSR_PATH                    "i915/kbl_dmc_ver1_04.bin"
  63 #define KBL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 4)
  64 #define KBL_CSR_MAX_FW_SIZE             BXT_CSR_MAX_FW_SIZE
  65 MODULE_FIRMWARE(KBL_CSR_PATH);
  66
  67 #define SKL_CSR_PATH                    "i915/skl_dmc_ver1_27.bin"
  68 #define SKL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 27)
  69 #define SKL_CSR_MAX_FW_SIZE             BXT_CSR_MAX_FW_SIZE
  70 MODULE_FIRMWARE(SKL_CSR_PATH);
  71
  72 #define BXT_CSR_PATH                    "i915/bxt_dmc_ver1_07.bin"
  73 #define BXT_CSR_VERSION_REQUIRED        CSR_VERSION(1, 7)
  74 #define BXT_CSR_MAX_FW_SIZE             0x3000
  75 MODULE_FIRMWARE(BXT_CSR_PATH);
  76
  77 #define CSR_DEFAULT_FW_OFFSET           0xFFFFFFFF
  78 #define PACKAGE_MAX_FW_INFO_ENTRIES     20
  79 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES  32
  80 #define DMC_V1_MAX_MMIO_COUNT           8
  81 #define DMC_V3_MAX_MMIO_COUNT           20
  82
  83 struct intel_css_header {
  84         /* 0x09 for DMC */
  85         u32 module_type;
  86
  87         /* Includes the DMC specific header in dwords */
  88         u32 header_len;
  89
  90         /* always value would be 0x10000 */
  91         u32 header_ver;
  92
  93         /* Not used */
  94         u32 module_id;
  95
  96         /* Not used */
  97         u32 module_vendor;
  98
  99         /* in YYYYMMDD format */
 100         u32 date;
 101
 102         /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
 103         u32 size;
 104
 105         /* Not used */
 106         u32 key_size;
 107
 108         /* Not used */
 109         u32 modulus_size;
 110
 111         /* Not used */
 112         u32 exponent_size;
 113
 114         /* Not used */
 115         u32 reserved1[12];
 116
 117         /* Major Minor */
 118         u32 version;
 119
 120         /* Not used */
 121         u32 reserved2[8];
 122
 123         /* Not used */
 124         u32 kernel_header_info;
 125 } __packed;
 126
 127 struct intel_fw_info {
 128         u8 reserved1;
 129
 130         /* reserved on package_header version 1, must be 0 on version 2 */
 131         u8 dmc_id;
 132
 133         /* Stepping (A, B, C, ..., *). * is a wildcard */
 134         char stepping;
 135
 136         /* Sub-stepping (0, 1, ..., *). * is a wildcard */
 137         char substepping;
 138
 139         u32 offset;
 140         u32 reserved2;
 141 } __packed;
 142
 143 struct intel_package_header {
 144         /* DMC container header length in dwords */
 145         u8 header_len;
 146
 147         /* 0x01, 0x02 */
 148         u8 header_ver;
 149
 150         u8 reserved[10];
 151
 152         /* Number of valid entries in the FWInfo array below */
 153         u32 num_entries;
 154 } __packed;
 155
 156 struct intel_dmc_header_base {
 157         /* always value would be 0x40403E3E */
 158         u32 signature;
 159
 160         /* DMC binary header length */
 161         u8 header_len;
 162
 163         /* 0x01 */
 164         u8 header_ver;
 165
 166         /* Reserved */
 167         u16 dmcc_ver;
 168
 169         /* Major, Minor */
 170         u32 project;
 171
 172         /* Firmware program size (excluding header) in dwords */
 173         u32 fw_size;
 174
 175         /* Major Minor version */
 176         u32 fw_version;
 177 } __packed;
 178
 179 struct intel_dmc_header_v1 {
 180         struct intel_dmc_header_base base;
 181
 182         /* Number of valid MMIO cycles present. */
 183         u32 mmio_count;
 184
 185         /* MMIO address */
 186         u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT];
 187
 188         /* MMIO data */
 189         u32 mmiodata[DMC_V1_MAX_MMIO_COUNT];
 190
 191         /* FW filename  */
 192         char dfile[32];
 193
 194         u32 reserved1[2];
 195 } __packed;
 196
 197 struct intel_dmc_header_v3 {
 198         struct intel_dmc_header_base base;
 199
 200         /* DMC RAM start MMIO address */
 201         u32 start_mmioaddr;
 202
 203         u32 reserved[9];
 204
 205         /* FW filename */
 206         char dfile[32];
 207
 208         /* Number of valid MMIO cycles present. */
 209         u32 mmio_count;
 210
 211         /* MMIO address */
 212         u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT];
 213
 214         /* MMIO data */
 215         u32 mmiodata[DMC_V3_MAX_MMIO_COUNT];
 216 } __packed;
 217
 218 struct stepping_info {
 219         char stepping;
 220         char substepping;
 221 };
 222
 223 static const struct stepping_info skl_stepping_info[] = {
 224         {'A', '0'}, {'B', '0'}, {'C', '0'},
 225         {'D', '0'}, {'E', '0'}, {'F', '0'},
 226         {'G', '0'}, {'H', '0'}, {'I', '0'},
 227         {'J', '0'}, {'K', '0'}
 228 };
 229
 230 static const struct stepping_info bxt_stepping_info[] = {
 231         {'A', '0'}, {'A', '1'}, {'A', '2'},
 232         {'B', '0'}, {'B', '1'}, {'B', '2'}
 233 };
 234
 235 static const struct stepping_info icl_stepping_info[] = {
 236         {'A', '0'}, {'A', '1'}, {'A', '2'},
 237         {'B', '0'}, {'B', '2'},
 238         {'C', '0'}
 239 };
 240
 241 static const struct stepping_info no_stepping_info = { '*', '*' };
 242
 243 static const struct stepping_info *
 244 intel_get_stepping_info(struct drm_i915_private *dev_priv)
 245 {
 246         const struct stepping_info *si;
 247         unsigned int size;
 248
 249         if (IS_ICELAKE(dev_priv)) {
 250                 size = ARRAY_SIZE(icl_stepping_info);
 251                 si = icl_stepping_info;
 252         } else if (IS_SKYLAKE(dev_priv)) {
 253                 size = ARRAY_SIZE(skl_stepping_info);
 254                 si = skl_stepping_info;
 255         } else if (IS_BROXTON(dev_priv)) {
 256                 size = ARRAY_SIZE(bxt_stepping_info);
 257                 si = bxt_stepping_info;
 258         } else {
 259                 size = 0;
 260                 si = NULL;
 261         }
 262
 263         if (INTEL_REVID(dev_priv) < size)
 264                 return si + INTEL_REVID(dev_priv);
 265
 266         return &no_stepping_info;
 267 }
 268
 269 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 270 {
 271         u32 val, mask;
 272
 273         mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
 274
 275         if (IS_GEN9_LP(dev_priv))
 276                 mask |= DC_STATE_DEBUG_MASK_CORES;
 277
 278         /* The below bit doesn't need to be cleared ever afterwards */
 279         val = I915_READ(DC_STATE_DEBUG);
 280         if ((val & mask) != mask) {
 281                 val |= mask;
 282                 I915_WRITE(DC_STATE_DEBUG, val);
 283                 POSTING_READ(DC_STATE_DEBUG);
 284         }
 285 }
 286
 287 /**
 288  * intel_csr_load_program() - write the firmware from memory to register.
 289  * @dev_priv: i915 drm device.
 290  *
 291  * CSR firmware is read from a .bin file and kept in internal memory one time.
 292  * Everytime display comes back from low power state this function is called to
 293  * copy the firmware from internal memory to registers.
 294  */
 295 void intel_csr_load_program(struct drm_i915_private *dev_priv)
 296 {
 297         u32 *payload = dev_priv->csr.dmc_payload;
 298         u32 i, fw_size;
 299
 300         if (!HAS_CSR(dev_priv)) {
 301                 drm_err(&dev_priv->drm,
 302                         "No CSR support available for this platform\n");
 303                 return;
 304         }
 305
 306         if (!dev_priv->csr.dmc_payload) {
 307                 drm_err(&dev_priv->drm,
 308                         "Tried to program CSR with empty payload\n");
 309                 return;
 310         }
 311
 312         fw_size = dev_priv->csr.dmc_fw_size;
 313         assert_rpm_wakelock_held(&dev_priv->runtime_pm);
 314
 315         preempt_disable();
 316
 317         for (i = 0; i < fw_size; i++)
 318                 intel_uncore_write_fw(&dev_priv->uncore, CSR_PROGRAM(i),
 319                                       payload[i]);
 320
 321         preempt_enable();
 322
 323         for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 324                 I915_WRITE(dev_priv->csr.mmioaddr[i],
 325                            dev_priv->csr.mmiodata[i]);
 326         }
 327
 328         dev_priv->csr.dc_state = 0;
 329
 330         gen9_set_dc_state_debugmask(dev_priv);
 331 }
 332
 333 /*
 334  * Search fw_info table for dmc_offset to find firmware binary: num_entries is
 335  * already sanitized.
 336  */
 337 static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
 338                               unsigned int num_entries,
 339                               const struct stepping_info *si,
 340                               u8 package_ver)
 341 {
 342         u32 dmc_offset = CSR_DEFAULT_FW_OFFSET;
 343         unsigned int i;
 344
 345         for (i = 0; i < num_entries; i++) {
 346                 if (package_ver > 1 && fw_info[i].dmc_id != 0)
 347                         continue;
 348
 349                 if (fw_info[i].substepping == '*' &&
 350                     si->stepping == fw_info[i].stepping) {
 351                         dmc_offset = fw_info[i].offset;
 352                         break;
 353                 }
 354
 355                 if (si->stepping == fw_info[i].stepping &&
 356                     si->substepping == fw_info[i].substepping) {
 357                         dmc_offset = fw_info[i].offset;
 358                         break;
 359                 }
 360
 361                 if (fw_info[i].stepping == '*' &&
 362                     fw_info[i].substepping == '*') {
 363                         /*
 364                          * In theory we should stop the search as generic
 365                          * entries should always come after the more specific
 366                          * ones, but let's continue to make sure to work even
 367                          * with "broken" firmwares. If we don't find a more
 368                          * specific one, then we use this entry
 369                          */
 370                         dmc_offset = fw_info[i].offset;
 371                 }
 372         }
 373
 374         return dmc_offset;
 375 }
 376
 377 static u32 parse_csr_fw_dmc(struct intel_csr *csr,
 378                             const struct intel_dmc_header_base *dmc_header,
 379                             size_t rem_size)
 380 {
 381         unsigned int header_len_bytes, dmc_header_size, payload_size, i;
 382         const u32 *mmioaddr, *mmiodata;
 383         u32 mmio_count, mmio_count_max;
 384         u8 *payload;
 385
 386         BUILD_BUG_ON(ARRAY_SIZE(csr->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
 387                      ARRAY_SIZE(csr->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
 388
 389         /*
 390          * Check if we can access common fields, we will checkc again below
 391          * after we have read the version
 392          */
 393         if (rem_size < sizeof(struct intel_dmc_header_base))
 394                 goto error_truncated;
 395
 396         /* Cope with small differences between v1 and v3 */
 397         if (dmc_header->header_ver == 3) {
 398                 const struct intel_dmc_header_v3 *v3 =
 399                         (const struct intel_dmc_header_v3 *)dmc_header;
 400
 401                 if (rem_size < sizeof(struct intel_dmc_header_v3))
 402                         goto error_truncated;
 403
 404                 mmioaddr = v3->mmioaddr;
 405                 mmiodata = v3->mmiodata;
 406                 mmio_count = v3->mmio_count;
 407                 mmio_count_max = DMC_V3_MAX_MMIO_COUNT;
 408                 /* header_len is in dwords */
 409                 header_len_bytes = dmc_header->header_len * 4;
 410                 dmc_header_size = sizeof(*v3);
 411         } else if (dmc_header->header_ver == 1) {
 412                 const struct intel_dmc_header_v1 *v1 =
 413                         (const struct intel_dmc_header_v1 *)dmc_header;
 414
 415                 if (rem_size < sizeof(struct intel_dmc_header_v1))
 416                         goto error_truncated;
 417
 418                 mmioaddr = v1->mmioaddr;
 419                 mmiodata = v1->mmiodata;
 420                 mmio_count = v1->mmio_count;
 421                 mmio_count_max = DMC_V1_MAX_MMIO_COUNT;
 422                 header_len_bytes = dmc_header->header_len;
 423                 dmc_header_size = sizeof(*v1);
 424         } else {
 425                 DRM_ERROR("Unknown DMC fw header version: %u\n",
 426                           dmc_header->header_ver);
 427                 return 0;
 428         }
 429
 430         if (header_len_bytes != dmc_header_size) {
 431                 DRM_ERROR("DMC firmware has wrong dmc header length "
 432                           "(%u bytes)\n", header_len_bytes);
 433                 return 0;
 434         }
 435
 436         /* Cache the dmc header info. */
 437         if (mmio_count > mmio_count_max) {
 438                 DRM_ERROR("DMC firmware has wrong mmio count %u\n", mmio_count);
 439                 return 0;
 440         }
 441
 442         for (i = 0; i < mmio_count; i++) {
 443                 if (mmioaddr[i] < CSR_MMIO_START_RANGE ||
 444                     mmioaddr[i] > CSR_MMIO_END_RANGE) {
 445                         DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
 446                                   mmioaddr[i]);
 447                         return 0;
 448                 }
 449                 csr->mmioaddr[i] = _MMIO(mmioaddr[i]);
 450                 csr->mmiodata[i] = mmiodata[i];
 451         }
 452         csr->mmio_count = mmio_count;
 453
 454         rem_size -= header_len_bytes;
 455
 456         /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
 457         payload_size = dmc_header->fw_size * 4;
 458         if (rem_size < payload_size)
 459                 goto error_truncated;
 460
 461         if (payload_size > csr->max_fw_size) {
 462                 DRM_ERROR("DMC FW too big (%u bytes)\n", payload_size);
 463                 return 0;
 464         }
 465         csr->dmc_fw_size = dmc_header->fw_size;
 466
 467         csr->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
 468         if (!csr->dmc_payload) {
 469                 DRM_ERROR("Memory allocation failed for dmc payload\n");
 470                 return 0;
 471         }
 472
 473         payload = (u8 *)(dmc_header) + header_len_bytes;
 474         memcpy(csr->dmc_payload, payload, payload_size);
 475
 476         return header_len_bytes + payload_size;
 477
 478 error_truncated:
 479         DRM_ERROR("Truncated DMC firmware, refusing.\n");
 480         return 0;
 481 }
 482
 483 static u32
 484 parse_csr_fw_package(struct intel_csr *csr,
 485                      const struct intel_package_header *package_header,
 486                      const struct stepping_info *si,
 487                      size_t rem_size)
 488 {
 489         u32 package_size = sizeof(struct intel_package_header);
 490         u32 num_entries, max_entries, dmc_offset;
 491         const struct intel_fw_info *fw_info;
 492
 493         if (rem_size < package_size)
 494                 goto error_truncated;
 495
 496         if (package_header->header_ver == 1) {
 497                 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES;
 498         } else if (package_header->header_ver == 2) {
 499                 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES;
 500         } else {
 501                 DRM_ERROR("DMC firmware has unknown header version %u\n",
 502                           package_header->header_ver);
 503                 return 0;
 504         }
 505
 506         /*
 507          * We should always have space for max_entries,
 508          * even if not all are used
 509          */
 510         package_size += max_entries * sizeof(struct intel_fw_info);
 511         if (rem_size < package_size)
 512                 goto error_truncated;
 513
 514         if (package_header->header_len * 4 != package_size) {
 515                 DRM_ERROR("DMC firmware has wrong package header length "
 516                           "(%u bytes)\n", package_size);
 517                 return 0;
 518         }
 519
 520         num_entries = package_header->num_entries;
 521         if (WARN_ON(package_header->num_entries > max_entries))
 522                 num_entries = max_entries;
 523
 524         fw_info = (const struct intel_fw_info *)
 525                 ((u8 *)package_header + sizeof(*package_header));
 526         dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si,
 527                                         package_header->header_ver);
 528         if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
 529                 DRM_ERROR("DMC firmware not supported for %c stepping\n",
 530                           si->stepping);
 531                 return 0;
 532         }
 533
 534         /* dmc_offset is in dwords */
 535         return package_size + dmc_offset * 4;
 536
 537 error_truncated:
 538         DRM_ERROR("Truncated DMC firmware, refusing.\n");
 539         return 0;
 540 }
 541
 542 /* Return number of bytes parsed or 0 on error */
 543 static u32 parse_csr_fw_css(struct intel_csr *csr,
 544                             struct intel_css_header *css_header,
 545                             size_t rem_size)
 546 {
 547         if (rem_size < sizeof(struct intel_css_header)) {
 548                 DRM_ERROR("Truncated DMC firmware, refusing.\n");
 549                 return 0;
 550         }
 551
 552         if (sizeof(struct intel_css_header) !=
 553             (css_header->header_len * 4)) {
 554                 DRM_ERROR("DMC firmware has wrong CSS header length "
 555                           "(%u bytes)\n",
 556                           (css_header->header_len * 4));
 557                 return 0;
 558         }
 559
 560         if (csr->required_version &&
 561             css_header->version != csr->required_version) {
 562                 DRM_INFO("Refusing to load DMC firmware v%u.%u,"
 563                          " please use v%u.%u\n",
 564                          CSR_VERSION_MAJOR(css_header->version),
 565                          CSR_VERSION_MINOR(css_header->version),
 566                          CSR_VERSION_MAJOR(csr->required_version),
 567                          CSR_VERSION_MINOR(csr->required_version));
 568                 return 0;
 569         }
 570
 571         csr->version = css_header->version;
 572
 573         return sizeof(struct intel_css_header);
 574 }
 575
 576 static void parse_csr_fw(struct drm_i915_private *dev_priv,
 577                          const struct firmware *fw)
 578 {
 579         struct intel_css_header *css_header;
 580         struct intel_package_header *package_header;
 581         struct intel_dmc_header_base *dmc_header;
 582         struct intel_csr *csr = &dev_priv->csr;
 583         const struct stepping_info *si = intel_get_stepping_info(dev_priv);
 584         u32 readcount = 0;
 585         u32 r;
 586
 587         if (!fw)
 588                 return;
 589
 590         /* Extract CSS Header information */
 591         css_header = (struct intel_css_header *)fw->data;
 592         r = parse_csr_fw_css(csr, css_header, fw->size);
 593         if (!r)
 594                 return;
 595
 596         readcount += r;
 597
 598         /* Extract Package Header information */
 599         package_header = (struct intel_package_header *)&fw->data[readcount];
 600         r = parse_csr_fw_package(csr, package_header, si, fw->size - readcount);
 601         if (!r)
 602                 return;
 603
 604         readcount += r;
 605
 606         /* Extract dmc_header information */
 607         dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount];
 608         parse_csr_fw_dmc(csr, dmc_header, fw->size - readcount);
 609 }
 610
 611 static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv)
 612 {
 613         drm_WARN_ON(&dev_priv->drm, dev_priv->csr.wakeref);
 614         dev_priv->csr.wakeref =
 615                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 616 }
 617
 618 static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv)
 619 {
 620         intel_wakeref_t wakeref __maybe_unused =
 621                 fetch_and_zero(&dev_priv->csr.wakeref);
 622
 623         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
 624 }
 625
 626 static void csr_load_work_fn(struct work_struct *work)
 627 {
 628         struct drm_i915_private *dev_priv;
 629         struct intel_csr *csr;
 630         const struct firmware *fw = NULL;
 631
 632         dev_priv = container_of(work, typeof(*dev_priv), csr.work);
 633         csr = &dev_priv->csr;
 634
 635         request_firmware(&fw, dev_priv->csr.fw_path, &dev_priv->drm.pdev->dev);
 636         parse_csr_fw(dev_priv, fw);
 637
 638         if (dev_priv->csr.dmc_payload) {
 639                 intel_csr_load_program(dev_priv);
 640                 intel_csr_runtime_pm_put(dev_priv);
 641
 642                 drm_info(&dev_priv->drm,
 643                          "Finished loading DMC firmware %s (v%u.%u)\n",
 644                          dev_priv->csr.fw_path, CSR_VERSION_MAJOR(csr->version),
 645                          CSR_VERSION_MINOR(csr->version));
 646         } else {
 647                 drm_notice(&dev_priv->drm,
 648                            "Failed to load DMC firmware %s."
 649                            " Disabling runtime power management.\n",
 650                            csr->fw_path);
 651                 drm_notice(&dev_priv->drm, "DMC firmware homepage: %s",
 652                            INTEL_UC_FIRMWARE_URL);
 653         }
 654
 655         release_firmware(fw);
 656 }
 657
 658 /**
 659  * intel_csr_ucode_init() - initialize the firmware loading.
 660  * @dev_priv: i915 drm device.
 661  *
 662  * This function is called at the time of loading the display driver to read
 663  * firmware from a .bin file and copied into a internal memory.
 664  */
 665 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 666 {
 667         struct intel_csr *csr = &dev_priv->csr;
 668
 669         INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
 670
 671         if (!HAS_CSR(dev_priv))
 672                 return;
 673
 674         /*
 675          * Obtain a runtime pm reference, until CSR is loaded, to avoid entering
 676          * runtime-suspend.
 677          *
 678          * On error, we return with the rpm wakeref held to prevent runtime
 679          * suspend as runtime suspend *requires* a working CSR for whatever
 680          * reason.
 681          */
 682         intel_csr_runtime_pm_get(dev_priv);
 683
 684         if (INTEL_GEN(dev_priv) >= 12) {
 685                 csr->fw_path = TGL_CSR_PATH;
 686                 csr->required_version = TGL_CSR_VERSION_REQUIRED;
 687                 /* Allow to load fw via parameter using the last known size */
 688                 csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
 689         } else if (IS_GEN(dev_priv, 11)) {
 690                 csr->fw_path = ICL_CSR_PATH;
 691                 csr->required_version = ICL_CSR_VERSION_REQUIRED;
 692                 csr->max_fw_size = ICL_CSR_MAX_FW_SIZE;
 693         } else if (IS_CANNONLAKE(dev_priv)) {
 694                 csr->fw_path = CNL_CSR_PATH;
 695                 csr->required_version = CNL_CSR_VERSION_REQUIRED;
 696                 csr->max_fw_size = CNL_CSR_MAX_FW_SIZE;
 697         } else if (IS_GEMINILAKE(dev_priv)) {
 698                 csr->fw_path = GLK_CSR_PATH;
 699                 csr->required_version = GLK_CSR_VERSION_REQUIRED;
 700                 csr->max_fw_size = GLK_CSR_MAX_FW_SIZE;
 701         } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 702                 csr->fw_path = KBL_CSR_PATH;
 703                 csr->required_version = KBL_CSR_VERSION_REQUIRED;
 704                 csr->max_fw_size = KBL_CSR_MAX_FW_SIZE;
 705         } else if (IS_SKYLAKE(dev_priv)) {
 706                 csr->fw_path = SKL_CSR_PATH;
 707                 csr->required_version = SKL_CSR_VERSION_REQUIRED;
 708                 csr->max_fw_size = SKL_CSR_MAX_FW_SIZE;
 709         } else if (IS_BROXTON(dev_priv)) {
 710                 csr->fw_path = BXT_CSR_PATH;
 711                 csr->required_version = BXT_CSR_VERSION_REQUIRED;
 712                 csr->max_fw_size = BXT_CSR_MAX_FW_SIZE;
 713         }
 714
 715         if (i915_modparams.dmc_firmware_path) {
 716                 if (strlen(i915_modparams.dmc_firmware_path) == 0) {
 717                         csr->fw_path = NULL;
 718                         drm_info(&dev_priv->drm,
 719                                  "Disabling CSR firmware and runtime PM\n");
 720                         return;
 721                 }
 722
 723                 csr->fw_path = i915_modparams.dmc_firmware_path;
 724                 /* Bypass version check for firmware override. */
 725                 csr->required_version = 0;
 726         }
 727
 728         if (csr->fw_path == NULL) {
 729                 drm_dbg_kms(&dev_priv->drm,
 730                             "No known CSR firmware for platform, disabling runtime PM\n");
 731                 return;
 732         }
 733
 734         drm_dbg_kms(&dev_priv->drm, "Loading %s\n", csr->fw_path);
 735         schedule_work(&dev_priv->csr.work);
 736 }
 737
 738 /**
 739  * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
 740  * @dev_priv: i915 drm device
 741  *
 742  * Prepare the DMC firmware before entering system suspend. This includes
 743  * flushing pending work items and releasing any resources acquired during
 744  * init.
 745  */
 746 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
 747 {
 748         if (!HAS_CSR(dev_priv))
 749                 return;
 750
 751         flush_work(&dev_priv->csr.work);
 752
 753         /* Drop the reference held in case DMC isn't loaded. */
 754         if (!dev_priv->csr.dmc_payload)
 755                 intel_csr_runtime_pm_put(dev_priv);
 756 }
 757
 758 /**
 759  * intel_csr_ucode_resume() - init CSR firmware during system resume
 760  * @dev_priv: i915 drm device
 761  *
 762  * Reinitialize the DMC firmware during system resume, reacquiring any
 763  * resources released in intel_csr_ucode_suspend().
 764  */
 765 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
 766 {
 767         if (!HAS_CSR(dev_priv))
 768                 return;
 769
 770         /*
 771          * Reacquire the reference to keep RPM disabled in case DMC isn't
 772          * loaded.
 773          */
 774         if (!dev_priv->csr.dmc_payload)
 775                 intel_csr_runtime_pm_get(dev_priv);
 776 }
 777
 778 /**
 779  * intel_csr_ucode_fini() - unload the CSR firmware.
 780  * @dev_priv: i915 drm device.
 781  *
 782  * Firmmware unloading includes freeing the internal memory and reset the
 783  * firmware loading status.
 784  */
 785 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
 786 {
 787         if (!HAS_CSR(dev_priv))
 788                 return;
 789
 790         intel_csr_ucode_suspend(dev_priv);
 791         drm_WARN_ON(&dev_priv->drm, dev_priv->csr.wakeref);
 792
 793         kfree(dev_priv->csr.dmc_payload);
 794 }