1 // SPDX-License-Identifier: GPL-2.0-only
2 /**************************************************************************
3 * Copyright (c) 2007, Intel Corporation.
6 * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
9 **************************************************************************/
11 #include <drm/drm_vblank.h>
13 #include "mdfld_output.h"
16 #include "psb_intel_reg.h"
25 psb_pipestat(int pipe)
37 mid_pipe_event(int pipe)
40 return _PSB_PIPEA_EVENT_FLAG;
42 return _MDFLD_PIPEB_EVENT_FLAG;
44 return _MDFLD_PIPEC_EVENT_FLAG;
49 mid_pipe_vsync(int pipe)
52 return _PSB_VSYNC_PIPEA_FLAG;
54 return _PSB_VSYNC_PIPEB_FLAG;
56 return _MDFLD_PIPEC_VBLANK_FLAG;
61 mid_pipeconf(int pipe)
73 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
75 if ((dev_priv->pipestat[pipe] & mask) != mask) {
76 u32 reg = psb_pipestat(pipe);
77 dev_priv->pipestat[pipe] |= mask;
78 /* Enable the interrupt, clear any pending status */
79 if (gma_power_begin(dev_priv->dev, false)) {
80 u32 writeVal = PSB_RVDC32(reg);
81 writeVal |= (mask | (mask >> 16));
82 PSB_WVDC32(writeVal, reg);
83 (void) PSB_RVDC32(reg);
84 gma_power_end(dev_priv->dev);
90 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
92 if ((dev_priv->pipestat[pipe] & mask) != 0) {
93 u32 reg = psb_pipestat(pipe);
94 dev_priv->pipestat[pipe] &= ~mask;
95 if (gma_power_begin(dev_priv->dev, false)) {
96 u32 writeVal = PSB_RVDC32(reg);
98 PSB_WVDC32(writeVal, reg);
99 (void) PSB_RVDC32(reg);
100 gma_power_end(dev_priv->dev);
105 static void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
107 if (gma_power_begin(dev_priv->dev, false)) {
108 u32 pipe_event = mid_pipe_event(pipe);
109 dev_priv->vdc_irq_mask |= pipe_event;
110 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
111 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
112 gma_power_end(dev_priv->dev);
116 static void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
118 if (dev_priv->pipestat[pipe] == 0) {
119 if (gma_power_begin(dev_priv->dev, false)) {
120 u32 pipe_event = mid_pipe_event(pipe);
121 dev_priv->vdc_irq_mask &= ~pipe_event;
122 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
123 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
124 gma_power_end(dev_priv->dev);
130 * Display controller interrupt handler for pipe event.
133 static void mid_pipe_event_handler(struct drm_device *dev, int pipe)
135 struct drm_psb_private *dev_priv =
136 (struct drm_psb_private *) dev->dev_private;
138 uint32_t pipe_stat_val = 0;
139 uint32_t pipe_stat_reg = psb_pipestat(pipe);
140 uint32_t pipe_enable = dev_priv->pipestat[pipe];
141 uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
145 spin_lock(&dev_priv->irqmask_lock);
147 pipe_stat_val = PSB_RVDC32(pipe_stat_reg);
148 pipe_stat_val &= pipe_enable | pipe_status;
149 pipe_stat_val &= pipe_stat_val >> 16;
151 spin_unlock(&dev_priv->irqmask_lock);
153 /* Clear the 2nd level interrupt status bits
154 * Sometimes the bits are very sticky so we repeat until they unstick */
155 for (i = 0; i < 0xffff; i++) {
156 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
157 pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status;
165 "%s, can't clear status bits for pipe %d, its value = 0x%x.\n",
166 __func__, pipe, PSB_RVDC32(pipe_stat_reg));
168 if (pipe_stat_val & PIPE_VBLANK_STATUS ||
169 (IS_MFLD(dev) && pipe_stat_val & PIPE_TE_STATUS)) {
170 struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe);
171 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
174 drm_handle_vblank(dev, pipe);
176 spin_lock_irqsave(&dev->event_lock, flags);
177 if (gma_crtc->page_flip_event) {
178 drm_crtc_send_vblank_event(crtc,
179 gma_crtc->page_flip_event);
180 gma_crtc->page_flip_event = NULL;
181 drm_crtc_vblank_put(crtc);
183 spin_unlock_irqrestore(&dev->event_lock, flags);
188 * Display controller interrupt handler.
190 static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
192 if (vdc_stat & _PSB_IRQ_ASLE)
193 psb_intel_opregion_asle_intr(dev);
195 if (vdc_stat & _PSB_VSYNC_PIPEA_FLAG)
196 mid_pipe_event_handler(dev, 0);
198 if (vdc_stat & _PSB_VSYNC_PIPEB_FLAG)
199 mid_pipe_event_handler(dev, 1);
203 * SGX interrupt handler
205 static void psb_sgx_interrupt(struct drm_device *dev, u32 stat_1, u32 stat_2)
207 struct drm_psb_private *dev_priv = dev->dev_private;
210 if (stat_1 & _PSB_CE_TWOD_COMPLETE)
211 val = PSB_RSGX32(PSB_CR_2D_BLIT_STATUS);
213 if (stat_2 & _PSB_CE2_BIF_REQUESTER_FAULT) {
214 val = PSB_RSGX32(PSB_CR_BIF_INT_STAT);
215 addr = PSB_RSGX32(PSB_CR_BIF_FAULT);
217 if (val & _PSB_CBI_STAT_PF_N_RW)
218 DRM_ERROR("SGX MMU page fault:");
220 DRM_ERROR("SGX MMU read / write protection fault:");
222 if (val & _PSB_CBI_STAT_FAULT_CACHE)
223 DRM_ERROR("\tCache requestor");
224 if (val & _PSB_CBI_STAT_FAULT_TA)
225 DRM_ERROR("\tTA requestor");
226 if (val & _PSB_CBI_STAT_FAULT_VDM)
227 DRM_ERROR("\tVDM requestor");
228 if (val & _PSB_CBI_STAT_FAULT_2D)
229 DRM_ERROR("\t2D requestor");
230 if (val & _PSB_CBI_STAT_FAULT_PBE)
231 DRM_ERROR("\tPBE requestor");
232 if (val & _PSB_CBI_STAT_FAULT_TSP)
233 DRM_ERROR("\tTSP requestor");
234 if (val & _PSB_CBI_STAT_FAULT_ISP)
235 DRM_ERROR("\tISP requestor");
236 if (val & _PSB_CBI_STAT_FAULT_USSEPDS)
237 DRM_ERROR("\tUSSEPDS requestor");
238 if (val & _PSB_CBI_STAT_FAULT_HOST)
239 DRM_ERROR("\tHost requestor");
241 DRM_ERROR("\tMMU failing address is 0x%08x.\n",
247 PSB_WSGX32(stat_1, PSB_CR_EVENT_HOST_CLEAR);
248 PSB_WSGX32(stat_2, PSB_CR_EVENT_HOST_CLEAR2);
249 PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR2);
252 irqreturn_t psb_irq_handler(int irq, void *arg)
254 struct drm_device *dev = arg;
255 struct drm_psb_private *dev_priv = dev->dev_private;
256 uint32_t vdc_stat, dsp_int = 0, sgx_int = 0, hotplug_int = 0;
257 u32 sgx_stat_1, sgx_stat_2;
260 spin_lock(&dev_priv->irqmask_lock);
262 vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
264 if (vdc_stat & (_PSB_PIPE_EVENT_FLAG|_PSB_IRQ_ASLE))
267 /* FIXME: Handle Medfield
268 if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG)
272 if (vdc_stat & _PSB_IRQ_SGX_FLAG)
274 if (vdc_stat & _PSB_IRQ_DISP_HOTSYNC)
277 vdc_stat &= dev_priv->vdc_irq_mask;
278 spin_unlock(&dev_priv->irqmask_lock);
280 if (dsp_int && gma_power_is_on(dev)) {
281 psb_vdc_interrupt(dev, vdc_stat);
286 sgx_stat_1 = PSB_RSGX32(PSB_CR_EVENT_STATUS);
287 sgx_stat_2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
288 psb_sgx_interrupt(dev, sgx_stat_1, sgx_stat_2);
292 /* Note: this bit has other meanings on some devices, so we will
293 need to address that later if it ever matters */
294 if (hotplug_int && dev_priv->ops->hotplug) {
295 handled = dev_priv->ops->hotplug(dev);
296 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
299 PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
300 (void) PSB_RVDC32(PSB_INT_IDENTITY_R);
309 void psb_irq_preinstall(struct drm_device *dev)
311 struct drm_psb_private *dev_priv =
312 (struct drm_psb_private *) dev->dev_private;
313 unsigned long irqflags;
315 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
317 if (gma_power_is_on(dev)) {
318 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
319 PSB_WVDC32(0x00000000, PSB_INT_MASK_R);
320 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
321 PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE);
322 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
324 if (dev->vblank[0].enabled)
325 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
326 if (dev->vblank[1].enabled)
327 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
329 /* FIXME: Handle Medfield irq mask
330 if (dev->vblank[1].enabled)
331 dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG;
332 if (dev->vblank[2].enabled)
333 dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG;
336 /* Revisit this area - want per device masks ? */
337 if (dev_priv->ops->hotplug)
338 dev_priv->vdc_irq_mask |= _PSB_IRQ_DISP_HOTSYNC;
339 dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE | _PSB_IRQ_SGX_FLAG;
341 /* This register is safe even if display island is off */
342 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
343 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
346 int psb_irq_postinstall(struct drm_device *dev)
348 struct drm_psb_private *dev_priv = dev->dev_private;
349 unsigned long irqflags;
351 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
353 /* Enable 2D and MMU fault interrupts */
354 PSB_WSGX32(_PSB_CE2_BIF_REQUESTER_FAULT, PSB_CR_EVENT_HOST_ENABLE2);
355 PSB_WSGX32(_PSB_CE_TWOD_COMPLETE, PSB_CR_EVENT_HOST_ENABLE);
356 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); /* Post */
358 /* This register is safe even if display island is off */
359 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
360 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
362 if (dev->vblank[0].enabled)
363 psb_enable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
365 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
367 if (dev->vblank[1].enabled)
368 psb_enable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
370 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
372 if (dev->vblank[2].enabled)
373 psb_enable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
375 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
377 if (dev_priv->ops->hotplug_enable)
378 dev_priv->ops->hotplug_enable(dev, true);
380 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
384 void psb_irq_uninstall(struct drm_device *dev)
386 struct drm_psb_private *dev_priv = dev->dev_private;
387 unsigned long irqflags;
389 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
391 if (dev_priv->ops->hotplug_enable)
392 dev_priv->ops->hotplug_enable(dev, false);
394 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
396 if (dev->vblank[0].enabled)
397 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
399 if (dev->vblank[1].enabled)
400 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
402 if (dev->vblank[2].enabled)
403 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
405 dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
406 _PSB_IRQ_MSVDX_FLAG |
409 /* These two registers are safe even if display island is off */
410 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
411 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
415 /* This register is safe even if display island is off */
416 PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
417 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
420 void psb_irq_turn_on_dpst(struct drm_device *dev)
422 struct drm_psb_private *dev_priv =
423 (struct drm_psb_private *) dev->dev_private;
427 if (gma_power_begin(dev, false)) {
428 PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL);
429 hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
430 PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL);
431 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
433 PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC);
434 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
435 PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE
436 | PWM_PHASEIN_INT_ENABLE,
438 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
440 psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
442 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
443 PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR,
444 HISTOGRAM_INT_CONTROL);
445 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
446 PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE,
453 int psb_irq_enable_dpst(struct drm_device *dev)
455 struct drm_psb_private *dev_priv =
456 (struct drm_psb_private *) dev->dev_private;
457 unsigned long irqflags;
459 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
462 mid_enable_pipe_event(dev_priv, 0);
463 psb_irq_turn_on_dpst(dev);
465 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
469 void psb_irq_turn_off_dpst(struct drm_device *dev)
471 struct drm_psb_private *dev_priv =
472 (struct drm_psb_private *) dev->dev_private;
475 if (gma_power_begin(dev, false)) {
476 PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL);
477 PSB_RVDC32(HISTOGRAM_INT_CONTROL);
479 psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
481 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
482 PSB_WVDC32(pwm_reg & ~PWM_PHASEIN_INT_ENABLE,
484 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
490 int psb_irq_disable_dpst(struct drm_device *dev)
492 struct drm_psb_private *dev_priv =
493 (struct drm_psb_private *) dev->dev_private;
494 unsigned long irqflags;
496 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
498 mid_disable_pipe_event(dev_priv, 0);
499 psb_irq_turn_off_dpst(dev);
501 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
507 * It is used to enable VBLANK interrupt
509 int psb_enable_vblank(struct drm_crtc *crtc)
511 struct drm_device *dev = crtc->dev;
512 unsigned int pipe = crtc->index;
513 struct drm_psb_private *dev_priv = dev->dev_private;
514 unsigned long irqflags;
515 uint32_t reg_val = 0;
516 uint32_t pipeconf_reg = mid_pipeconf(pipe);
518 /* Medfield is different - we should perhaps extract out vblank
519 and blacklight etc ops */
521 return mdfld_enable_te(dev, pipe);
523 if (gma_power_begin(dev, false)) {
524 reg_val = REG_READ(pipeconf_reg);
528 if (!(reg_val & PIPEACONF_ENABLE))
531 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
534 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
536 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
538 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
539 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
540 psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
542 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
548 * It is used to disable VBLANK interrupt
550 void psb_disable_vblank(struct drm_crtc *crtc)
552 struct drm_device *dev = crtc->dev;
553 unsigned int pipe = crtc->index;
554 struct drm_psb_private *dev_priv = dev->dev_private;
555 unsigned long irqflags;
558 mdfld_disable_te(dev, pipe);
559 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
562 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG;
564 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG;
566 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
567 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
568 psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
570 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
574 * It is used to enable TE interrupt
576 int mdfld_enable_te(struct drm_device *dev, int pipe)
578 struct drm_psb_private *dev_priv =
579 (struct drm_psb_private *) dev->dev_private;
580 unsigned long irqflags;
581 uint32_t reg_val = 0;
582 uint32_t pipeconf_reg = mid_pipeconf(pipe);
584 if (gma_power_begin(dev, false)) {
585 reg_val = REG_READ(pipeconf_reg);
589 if (!(reg_val & PIPEACONF_ENABLE))
592 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
594 mid_enable_pipe_event(dev_priv, pipe);
595 psb_enable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
597 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
603 * It is used to disable TE interrupt
605 void mdfld_disable_te(struct drm_device *dev, int pipe)
607 struct drm_psb_private *dev_priv =
608 (struct drm_psb_private *) dev->dev_private;
609 unsigned long irqflags;
611 if (!dev_priv->dsr_enable)
614 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
616 mid_disable_pipe_event(dev_priv, pipe);
617 psb_disable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
619 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
622 /* Called from drm generic code, passed a 'crtc', which
623 * we use as a pipe index
625 u32 psb_get_vblank_counter(struct drm_crtc *crtc)
627 struct drm_device *dev = crtc->dev;
628 unsigned int pipe = crtc->index;
629 uint32_t high_frame = PIPEAFRAMEHIGH;
630 uint32_t low_frame = PIPEAFRAMEPIXEL;
631 uint32_t pipeconf_reg = PIPEACONF;
632 uint32_t reg_val = 0;
633 uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
639 high_frame = PIPEBFRAMEHIGH;
640 low_frame = PIPEBFRAMEPIXEL;
641 pipeconf_reg = PIPEBCONF;
644 high_frame = PIPECFRAMEHIGH;
645 low_frame = PIPECFRAMEPIXEL;
646 pipeconf_reg = PIPECCONF;
649 dev_err(dev->dev, "%s, invalid pipe.\n", __func__);
653 if (!gma_power_begin(dev, false))
656 reg_val = REG_READ(pipeconf_reg);
658 if (!(reg_val & PIPEACONF_ENABLE)) {
659 dev_err(dev->dev, "trying to get vblank count for disabled pipe %u\n",
661 goto psb_get_vblank_counter_exit;
665 * High & low register fields aren't synchronized, so make sure
666 * we get a low value that's stable across two reads of the high
670 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
671 PIPE_FRAME_HIGH_SHIFT);
672 low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
673 PIPE_FRAME_LOW_SHIFT);
674 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
675 PIPE_FRAME_HIGH_SHIFT);
676 } while (high1 != high2);
678 count = (high1 << 8) | low;
680 psb_get_vblank_counter_exit: