drivers/gpu/drm/exynos/exynos_drm_mic.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Hyungwon Hwang <human.hwang@samsung.com>
   6  */
   7
   8 #include <linux/platform_device.h>
   9 #include <video/of_videomode.h>
  10 #include <linux/of_address.h>
  11 #include <video/videomode.h>
  12 #include <linux/module.h>
  13 #include <linux/delay.h>
  14 #include <linux/mutex.h>
  15 #include <linux/of.h>
  16 #include <linux/of_graph.h>
  17 #include <linux/clk.h>
  18 #include <linux/component.h>
  19 #include <linux/pm_runtime.h>
  20 #include <drm/drmP.h>
  21 #include <drm/drm_encoder.h>
  22 #include <linux/mfd/syscon.h>
  23 #include <linux/regmap.h>
  24
  25 #include "exynos_drm_drv.h"
  26
  27 /* Sysreg registers for MIC */
  28 #define DSD_CFG_MUX     0x1004
  29 #define MIC0_RGB_MUX    (1 << 0)
  30 #define MIC0_I80_MUX    (1 << 1)
  31 #define MIC0_ON_MUX     (1 << 5)
  32
  33 /* MIC registers */
  34 #define MIC_OP                          0x0
  35 #define MIC_IP_VER                      0x0004
  36 #define MIC_V_TIMING_0                  0x0008
  37 #define MIC_V_TIMING_1                  0x000C
  38 #define MIC_IMG_SIZE                    0x0010
  39 #define MIC_INPUT_TIMING_0              0x0014
  40 #define MIC_INPUT_TIMING_1              0x0018
  41 #define MIC_2D_OUTPUT_TIMING_0          0x001C
  42 #define MIC_2D_OUTPUT_TIMING_1          0x0020
  43 #define MIC_2D_OUTPUT_TIMING_2          0x0024
  44 #define MIC_3D_OUTPUT_TIMING_0          0x0028
  45 #define MIC_3D_OUTPUT_TIMING_1          0x002C
  46 #define MIC_3D_OUTPUT_TIMING_2          0x0030
  47 #define MIC_CORE_PARA_0                 0x0034
  48 #define MIC_CORE_PARA_1                 0x0038
  49 #define MIC_CTC_CTRL                    0x0040
  50 #define MIC_RD_DATA                     0x0044
  51
  52 #define MIC_UPD_REG                     (1 << 31)
  53 #define MIC_ON_REG                      (1 << 30)
  54 #define MIC_TD_ON_REG                   (1 << 29)
  55 #define MIC_BS_CHG_OUT                  (1 << 16)
  56 #define MIC_VIDEO_TYPE(x)               (((x) & 0xf) << 12)
  57 #define MIC_PSR_EN                      (1 << 5)
  58 #define MIC_SW_RST                      (1 << 4)
  59 #define MIC_ALL_RST                     (1 << 3)
  60 #define MIC_CORE_VER_CONTROL            (1 << 2)
  61 #define MIC_MODE_SEL_COMMAND_MODE       (1 << 1)
  62 #define MIC_MODE_SEL_MASK               (1 << 1)
  63 #define MIC_CORE_EN                     (1 << 0)
  64
  65 #define MIC_V_PULSE_WIDTH(x)            (((x) & 0x3fff) << 16)
  66 #define MIC_V_PERIOD_LINE(x)            ((x) & 0x3fff)
  67
  68 #define MIC_VBP_SIZE(x)                 (((x) & 0x3fff) << 16)
  69 #define MIC_VFP_SIZE(x)                 ((x) & 0x3fff)
  70
  71 #define MIC_IMG_V_SIZE(x)               (((x) & 0x3fff) << 16)
  72 #define MIC_IMG_H_SIZE(x)               ((x) & 0x3fff)
  73
  74 #define MIC_H_PULSE_WIDTH_IN(x)         (((x) & 0x3fff) << 16)
  75 #define MIC_H_PERIOD_PIXEL_IN(x)        ((x) & 0x3fff)
  76
  77 #define MIC_HBP_SIZE_IN(x)              (((x) & 0x3fff) << 16)
  78 #define MIC_HFP_SIZE_IN(x)              ((x) & 0x3fff)
  79
  80 #define MIC_H_PULSE_WIDTH_2D(x)         (((x) & 0x3fff) << 16)
  81 #define MIC_H_PERIOD_PIXEL_2D(x)        ((x) & 0x3fff)
  82
  83 #define MIC_HBP_SIZE_2D(x)              (((x) & 0x3fff) << 16)
  84 #define MIC_HFP_SIZE_2D(x)              ((x) & 0x3fff)
  85
  86 #define MIC_BS_SIZE_2D(x)       ((x) & 0x3fff)
  87
  88 static char *clk_names[] = { "pclk_mic0", "sclk_rgb_vclk_to_mic0" };
  89 #define NUM_CLKS                ARRAY_SIZE(clk_names)
  90 static DEFINE_MUTEX(mic_mutex);
  91
  92 struct exynos_mic {
  93         struct device *dev;
  94         void __iomem *reg;
  95         struct regmap *sysreg;
  96         struct clk *clks[NUM_CLKS];
  97
  98         bool i80_mode;
  99         struct videomode vm;
 100         struct drm_encoder *encoder;
 101         struct drm_bridge bridge;
 102
 103         bool enabled;
 104 };
 105
 106 static void mic_set_path(struct exynos_mic *mic, bool enable)
 107 {
 108         int ret;
 109         unsigned int val;
 110
 111         ret = regmap_read(mic->sysreg, DSD_CFG_MUX, &val);
 112         if (ret) {
 113                 DRM_DEV_ERROR(mic->dev,
 114                               "mic: Failed to read system register\n");
 115                 return;
 116         }
 117
 118         if (enable) {
 119                 if (mic->i80_mode)
 120                         val |= MIC0_I80_MUX;
 121                 else
 122                         val |= MIC0_RGB_MUX;
 123
 124                 val |=  MIC0_ON_MUX;
 125         } else
 126                 val &= ~(MIC0_RGB_MUX | MIC0_I80_MUX | MIC0_ON_MUX);
 127
 128         ret = regmap_write(mic->sysreg, DSD_CFG_MUX, val);
 129         if (ret)
 130                 DRM_DEV_ERROR(mic->dev,
 131                               "mic: Failed to read system register\n");
 132 }
 133
 134 static int mic_sw_reset(struct exynos_mic *mic)
 135 {
 136         unsigned int retry = 100;
 137         int ret;
 138
 139         writel(MIC_SW_RST, mic->reg + MIC_OP);
 140
 141         while (retry-- > 0) {
 142                 ret = readl(mic->reg + MIC_OP);
 143                 if (!(ret & MIC_SW_RST))
 144                         return 0;
 145
 146                 udelay(10);
 147         }
 148
 149         return -ETIMEDOUT;
 150 }
 151
 152 static void mic_set_porch_timing(struct exynos_mic *mic)
 153 {
 154         struct videomode vm = mic->vm;
 155         u32 reg;
 156
 157         reg = MIC_V_PULSE_WIDTH(vm.vsync_len) +
 158                 MIC_V_PERIOD_LINE(vm.vsync_len + vm.vactive +
 159                                 vm.vback_porch + vm.vfront_porch);
 160         writel(reg, mic->reg + MIC_V_TIMING_0);
 161
 162         reg = MIC_VBP_SIZE(vm.vback_porch) +
 163                 MIC_VFP_SIZE(vm.vfront_porch);
 164         writel(reg, mic->reg + MIC_V_TIMING_1);
 165
 166         reg = MIC_V_PULSE_WIDTH(vm.hsync_len) +
 167                 MIC_V_PERIOD_LINE(vm.hsync_len + vm.hactive +
 168                                 vm.hback_porch + vm.hfront_porch);
 169         writel(reg, mic->reg + MIC_INPUT_TIMING_0);
 170
 171         reg = MIC_VBP_SIZE(vm.hback_porch) +
 172                 MIC_VFP_SIZE(vm.hfront_porch);
 173         writel(reg, mic->reg + MIC_INPUT_TIMING_1);
 174 }
 175
 176 static void mic_set_img_size(struct exynos_mic *mic)
 177 {
 178         struct videomode *vm = &mic->vm;
 179         u32 reg;
 180
 181         reg = MIC_IMG_H_SIZE(vm->hactive) +
 182                 MIC_IMG_V_SIZE(vm->vactive);
 183
 184         writel(reg, mic->reg + MIC_IMG_SIZE);
 185 }
 186
 187 static void mic_set_output_timing(struct exynos_mic *mic)
 188 {
 189         struct videomode vm = mic->vm;
 190         u32 reg, bs_size_2d;
 191
 192         DRM_DEV_DEBUG(mic->dev, "w: %u, h: %u\n", vm.hactive, vm.vactive);
 193         bs_size_2d = ((vm.hactive >> 2) << 1) + (vm.vactive % 4);
 194         reg = MIC_BS_SIZE_2D(bs_size_2d);
 195         writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_2);
 196
 197         if (!mic->i80_mode) {
 198                 reg = MIC_H_PULSE_WIDTH_2D(vm.hsync_len) +
 199                         MIC_H_PERIOD_PIXEL_2D(vm.hsync_len + bs_size_2d +
 200                                         vm.hback_porch + vm.hfront_porch);
 201                 writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_0);
 202
 203                 reg = MIC_HBP_SIZE_2D(vm.hback_porch) +
 204                         MIC_H_PERIOD_PIXEL_2D(vm.hfront_porch);
 205                 writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_1);
 206         }
 207 }
 208
 209 static void mic_set_reg_on(struct exynos_mic *mic, bool enable)
 210 {
 211         u32 reg = readl(mic->reg + MIC_OP);
 212
 213         if (enable) {
 214                 reg &= ~(MIC_MODE_SEL_MASK | MIC_CORE_VER_CONTROL | MIC_PSR_EN);
 215                 reg |= (MIC_CORE_EN | MIC_BS_CHG_OUT | MIC_ON_REG);
 216
 217                 reg  &= ~MIC_MODE_SEL_COMMAND_MODE;
 218                 if (mic->i80_mode)
 219                         reg |= MIC_MODE_SEL_COMMAND_MODE;
 220         } else {
 221                 reg &= ~MIC_CORE_EN;
 222         }
 223
 224         reg |= MIC_UPD_REG;
 225         writel(reg, mic->reg + MIC_OP);
 226 }
 227
 228 static void mic_disable(struct drm_bridge *bridge) { }
 229
 230 static void mic_post_disable(struct drm_bridge *bridge)
 231 {
 232         struct exynos_mic *mic = bridge->driver_private;
 233
 234         mutex_lock(&mic_mutex);
 235         if (!mic->enabled)
 236                 goto already_disabled;
 237
 238         mic_set_path(mic, 0);
 239
 240         pm_runtime_put(mic->dev);
 241         mic->enabled = 0;
 242
 243 already_disabled:
 244         mutex_unlock(&mic_mutex);
 245 }
 246
 247 static void mic_mode_set(struct drm_bridge *bridge,
 248                          const struct drm_display_mode *mode,
 249                          const struct drm_display_mode *adjusted_mode)
 250 {
 251         struct exynos_mic *mic = bridge->driver_private;
 252
 253         mutex_lock(&mic_mutex);
 254         drm_display_mode_to_videomode(mode, &mic->vm);
 255         mic->i80_mode = to_exynos_crtc(bridge->encoder->crtc)->i80_mode;
 256         mutex_unlock(&mic_mutex);
 257 }
 258
 259 static void mic_pre_enable(struct drm_bridge *bridge)
 260 {
 261         struct exynos_mic *mic = bridge->driver_private;
 262         int ret;
 263
 264         mutex_lock(&mic_mutex);
 265         if (mic->enabled)
 266                 goto unlock;
 267
 268         ret = pm_runtime_get_sync(mic->dev);
 269         if (ret < 0)
 270                 goto unlock;
 271
 272         mic_set_path(mic, 1);
 273
 274         ret = mic_sw_reset(mic);
 275         if (ret) {
 276                 DRM_DEV_ERROR(mic->dev, "Failed to reset\n");
 277                 goto turn_off;
 278         }
 279
 280         if (!mic->i80_mode)
 281                 mic_set_porch_timing(mic);
 282         mic_set_img_size(mic);
 283         mic_set_output_timing(mic);
 284         mic_set_reg_on(mic, 1);
 285         mic->enabled = 1;
 286         mutex_unlock(&mic_mutex);
 287
 288         return;
 289
 290 turn_off:
 291         pm_runtime_put(mic->dev);
 292 unlock:
 293         mutex_unlock(&mic_mutex);
 294 }
 295
 296 static void mic_enable(struct drm_bridge *bridge) { }
 297
 298 static const struct drm_bridge_funcs mic_bridge_funcs = {
 299         .disable = mic_disable,
 300         .post_disable = mic_post_disable,
 301         .mode_set = mic_mode_set,
 302         .pre_enable = mic_pre_enable,
 303         .enable = mic_enable,
 304 };
 305
 306 static int exynos_mic_bind(struct device *dev, struct device *master,
 307                            void *data)
 308 {
 309         struct exynos_mic *mic = dev_get_drvdata(dev);
 310
 311         mic->bridge.driver_private = mic;
 312
 313         return 0;
 314 }
 315
 316 static void exynos_mic_unbind(struct device *dev, struct device *master,
 317                               void *data)
 318 {
 319         struct exynos_mic *mic = dev_get_drvdata(dev);
 320
 321         mutex_lock(&mic_mutex);
 322         if (!mic->enabled)
 323                 goto already_disabled;
 324
 325         pm_runtime_put(mic->dev);
 326
 327 already_disabled:
 328         mutex_unlock(&mic_mutex);
 329 }
 330
 331 static const struct component_ops exynos_mic_component_ops = {
 332         .bind   = exynos_mic_bind,
 333         .unbind = exynos_mic_unbind,
 334 };
 335
 336 #ifdef CONFIG_PM
 337 static int exynos_mic_suspend(struct device *dev)
 338 {
 339         struct exynos_mic *mic = dev_get_drvdata(dev);
 340         int i;
 341
 342         for (i = NUM_CLKS - 1; i > -1; i--)
 343                 clk_disable_unprepare(mic->clks[i]);
 344
 345         return 0;
 346 }
 347
 348 static int exynos_mic_resume(struct device *dev)
 349 {
 350         struct exynos_mic *mic = dev_get_drvdata(dev);
 351         int ret, i;
 352
 353         for (i = 0; i < NUM_CLKS; i++) {
 354                 ret = clk_prepare_enable(mic->clks[i]);
 355                 if (ret < 0) {
 356                         DRM_DEV_ERROR(dev, "Failed to enable clock (%s)\n",
 357                                       clk_names[i]);
 358                         while (--i > -1)
 359                                 clk_disable_unprepare(mic->clks[i]);
 360                         return ret;
 361                 }
 362         }
 363         return 0;
 364 }
 365 #endif
 366
 367 static const struct dev_pm_ops exynos_mic_pm_ops = {
 368         SET_RUNTIME_PM_OPS(exynos_mic_suspend, exynos_mic_resume, NULL)
 369         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 370                                 pm_runtime_force_resume)
 371 };
 372
 373 static int exynos_mic_probe(struct platform_device *pdev)
 374 {
 375         struct device *dev = &pdev->dev;
 376         struct exynos_mic *mic;
 377         struct resource res;
 378         int ret, i;
 379
 380         mic = devm_kzalloc(dev, sizeof(*mic), GFP_KERNEL);
 381         if (!mic) {
 382                 DRM_DEV_ERROR(dev,
 383                               "mic: Failed to allocate memory for MIC object\n");
 384                 ret = -ENOMEM;
 385                 goto err;
 386         }
 387
 388         mic->dev = dev;
 389
 390         ret = of_address_to_resource(dev->of_node, 0, &res);
 391         if (ret) {
 392                 DRM_DEV_ERROR(dev, "mic: Failed to get mem region for MIC\n");
 393                 goto err;
 394         }
 395         mic->reg = devm_ioremap(dev, res.start, resource_size(&res));
 396         if (!mic->reg) {
 397                 DRM_DEV_ERROR(dev, "mic: Failed to remap for MIC\n");
 398                 ret = -ENOMEM;
 399                 goto err;
 400         }
 401
 402         mic->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
 403                                                         "samsung,disp-syscon");
 404         if (IS_ERR(mic->sysreg)) {
 405                 DRM_DEV_ERROR(dev, "mic: Failed to get system register.\n");
 406                 ret = PTR_ERR(mic->sysreg);
 407                 goto err;
 408         }
 409
 410         for (i = 0; i < NUM_CLKS; i++) {
 411                 mic->clks[i] = devm_clk_get(dev, clk_names[i]);
 412                 if (IS_ERR(mic->clks[i])) {
 413                         DRM_DEV_ERROR(dev, "mic: Failed to get clock (%s)\n",
 414                                       clk_names[i]);
 415                         ret = PTR_ERR(mic->clks[i]);
 416                         goto err;
 417                 }
 418         }
 419
 420         platform_set_drvdata(pdev, mic);
 421
 422         mic->bridge.funcs = &mic_bridge_funcs;
 423         mic->bridge.of_node = dev->of_node;
 424
 425         drm_bridge_add(&mic->bridge);
 426
 427         pm_runtime_enable(dev);
 428
 429         ret = component_add(dev, &exynos_mic_component_ops);
 430         if (ret)
 431                 goto err_pm;
 432
 433         DRM_DEV_DEBUG_KMS(dev, "MIC has been probed\n");
 434
 435         return 0;
 436
 437 err_pm:
 438         pm_runtime_disable(dev);
 439 err:
 440         return ret;
 441 }
 442
 443 static int exynos_mic_remove(struct platform_device *pdev)
 444 {
 445         struct exynos_mic *mic = platform_get_drvdata(pdev);
 446
 447         component_del(&pdev->dev, &exynos_mic_component_ops);
 448         pm_runtime_disable(&pdev->dev);
 449
 450         drm_bridge_remove(&mic->bridge);
 451
 452         return 0;
 453 }
 454
 455 static const struct of_device_id exynos_mic_of_match[] = {
 456         { .compatible = "samsung,exynos5433-mic" },
 457         { }
 458 };
 459 MODULE_DEVICE_TABLE(of, exynos_mic_of_match);
 460
 461 struct platform_driver mic_driver = {
 462         .probe          = exynos_mic_probe,
 463         .remove         = exynos_mic_remove,
 464         .driver         = {
 465                 .name   = "exynos-mic",
 466                 .pm     = &exynos_mic_pm_ops,
 467                 .owner  = THIS_MODULE,
 468                 .of_match_table = exynos_mic_of_match,
 469         },
 470 };