2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
31 #include <linux/hdmi.h>
32 #include <linux/i2c.h>
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/slab.h>
36 #include <linux/vga_switcheroo.h>
38 #include <drm/drm_displayid.h>
39 #include <drm/drm_drv.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_encoder.h>
42 #include <drm/drm_print.h>
43 #include <drm/drm_scdc_helper.h>
45 #include "drm_crtc_internal.h"
47 #define version_greater(edid, maj, min) \
48 (((edid)->version > (maj)) || \
49 ((edid)->version == (maj) && (edid)->revision > (min)))
51 #define EDID_EST_TIMINGS 16
52 #define EDID_STD_TIMINGS 8
53 #define EDID_DETAILED_TIMINGS 4
56 * EDID blocks out in the wild have a variety of bugs, try to collect
57 * them here (note that userspace may work around broken monitors first,
58 * but fixes should make their way here so that the kernel "just works"
59 * on as many displays as possible).
62 /* First detailed mode wrong, use largest 60Hz mode */
63 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
64 /* Reported 135MHz pixel clock is too high, needs adjustment */
65 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
66 /* Prefer the largest mode at 75 Hz */
67 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
68 /* Detail timing is in cm not mm */
69 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
70 /* Detailed timing descriptors have bogus size values, so just take the
71 * maximum size and use that.
73 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
74 /* use +hsync +vsync for detailed mode */
75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
76 /* Force reduced-blanking timings for detailed modes */
77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
79 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
81 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
83 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
85 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
86 /* Non desktop display (i.e. HMD) */
87 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
89 struct detailed_mode_closure {
90 struct drm_connector *connector;
102 static const struct edid_quirk {
106 } edid_quirk_list[] = {
108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
127 /* Belinea 10 15 55 */
128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
131 /* Envision Peripherals, Inc. EN-7100e */
132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
133 /* Envision EN2028 */
134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
136 /* Funai Electronics PM36B */
137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
138 EDID_QUIRK_DETAILED_IN_CM },
140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
143 /* LG Philips LCD LP154W01-A5 */
144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
147 /* Samsung SyncMaster 205BW. Note: irony */
148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
149 /* Samsung SyncMaster 22[5-6]BW */
150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
156 /* ViewSonic VA2026w */
157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
159 /* Medion MD 30217 PG */
160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
163 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC },
165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
171 /* Valve Index Headset */
172 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP },
173 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP },
174 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP },
175 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP },
176 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP },
177 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP },
178 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP },
179 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP },
180 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP },
181 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP },
182 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP },
183 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP },
184 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP },
185 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP },
186 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP },
187 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP },
188 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP },
190 /* HTC Vive and Vive Pro VR Headsets */
191 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
192 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
194 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */
195 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
196 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
197 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
199 /* Windows Mixed Reality Headsets */
200 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
201 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
202 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
203 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
204 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
205 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
206 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
207 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
209 /* Sony PlayStation VR Headset */
210 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
212 /* Sensics VR Headsets */
213 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP },
215 /* OSVR HDK and HDK2 VR Headsets */
216 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
220 * Autogenerated from the DMT spec.
221 * This table is copied from xfree86/modes/xf86EdidModes.c.
223 static const struct drm_display_mode drm_dmt_modes[] = {
224 /* 0x01 - 640x350@85Hz */
225 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
226 736, 832, 0, 350, 382, 385, 445, 0,
227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
228 /* 0x02 - 640x400@85Hz */
229 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
230 736, 832, 0, 400, 401, 404, 445, 0,
231 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
232 /* 0x03 - 720x400@85Hz */
233 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
234 828, 936, 0, 400, 401, 404, 446, 0,
235 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
236 /* 0x04 - 640x480@60Hz */
237 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
238 752, 800, 0, 480, 490, 492, 525, 0,
239 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
240 /* 0x05 - 640x480@72Hz */
241 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
242 704, 832, 0, 480, 489, 492, 520, 0,
243 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
244 /* 0x06 - 640x480@75Hz */
245 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
246 720, 840, 0, 480, 481, 484, 500, 0,
247 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
248 /* 0x07 - 640x480@85Hz */
249 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
250 752, 832, 0, 480, 481, 484, 509, 0,
251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
252 /* 0x08 - 800x600@56Hz */
253 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
254 896, 1024, 0, 600, 601, 603, 625, 0,
255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
256 /* 0x09 - 800x600@60Hz */
257 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
258 968, 1056, 0, 600, 601, 605, 628, 0,
259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
260 /* 0x0a - 800x600@72Hz */
261 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
262 976, 1040, 0, 600, 637, 643, 666, 0,
263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
264 /* 0x0b - 800x600@75Hz */
265 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
266 896, 1056, 0, 600, 601, 604, 625, 0,
267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
268 /* 0x0c - 800x600@85Hz */
269 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
270 896, 1048, 0, 600, 601, 604, 631, 0,
271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
272 /* 0x0d - 800x600@120Hz RB */
273 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
274 880, 960, 0, 600, 603, 607, 636, 0,
275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
276 /* 0x0e - 848x480@60Hz */
277 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
278 976, 1088, 0, 480, 486, 494, 517, 0,
279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
280 /* 0x0f - 1024x768@43Hz, interlace */
281 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
282 1208, 1264, 0, 768, 768, 776, 817, 0,
283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
284 DRM_MODE_FLAG_INTERLACE) },
285 /* 0x10 - 1024x768@60Hz */
286 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
287 1184, 1344, 0, 768, 771, 777, 806, 0,
288 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
289 /* 0x11 - 1024x768@70Hz */
290 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
291 1184, 1328, 0, 768, 771, 777, 806, 0,
292 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
293 /* 0x12 - 1024x768@75Hz */
294 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
295 1136, 1312, 0, 768, 769, 772, 800, 0,
296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
297 /* 0x13 - 1024x768@85Hz */
298 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
299 1168, 1376, 0, 768, 769, 772, 808, 0,
300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
301 /* 0x14 - 1024x768@120Hz RB */
302 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
303 1104, 1184, 0, 768, 771, 775, 813, 0,
304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
305 /* 0x15 - 1152x864@75Hz */
306 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
307 1344, 1600, 0, 864, 865, 868, 900, 0,
308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
309 /* 0x55 - 1280x720@60Hz */
310 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
311 1430, 1650, 0, 720, 725, 730, 750, 0,
312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
313 /* 0x16 - 1280x768@60Hz RB */
314 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
315 1360, 1440, 0, 768, 771, 778, 790, 0,
316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
317 /* 0x17 - 1280x768@60Hz */
318 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
319 1472, 1664, 0, 768, 771, 778, 798, 0,
320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
321 /* 0x18 - 1280x768@75Hz */
322 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
323 1488, 1696, 0, 768, 771, 778, 805, 0,
324 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
325 /* 0x19 - 1280x768@85Hz */
326 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
327 1496, 1712, 0, 768, 771, 778, 809, 0,
328 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
329 /* 0x1a - 1280x768@120Hz RB */
330 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
331 1360, 1440, 0, 768, 771, 778, 813, 0,
332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
333 /* 0x1b - 1280x800@60Hz RB */
334 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
335 1360, 1440, 0, 800, 803, 809, 823, 0,
336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
337 /* 0x1c - 1280x800@60Hz */
338 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
339 1480, 1680, 0, 800, 803, 809, 831, 0,
340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
341 /* 0x1d - 1280x800@75Hz */
342 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
343 1488, 1696, 0, 800, 803, 809, 838, 0,
344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
345 /* 0x1e - 1280x800@85Hz */
346 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
347 1496, 1712, 0, 800, 803, 809, 843, 0,
348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
349 /* 0x1f - 1280x800@120Hz RB */
350 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
351 1360, 1440, 0, 800, 803, 809, 847, 0,
352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
353 /* 0x20 - 1280x960@60Hz */
354 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
355 1488, 1800, 0, 960, 961, 964, 1000, 0,
356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
357 /* 0x21 - 1280x960@85Hz */
358 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
359 1504, 1728, 0, 960, 961, 964, 1011, 0,
360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
361 /* 0x22 - 1280x960@120Hz RB */
362 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
363 1360, 1440, 0, 960, 963, 967, 1017, 0,
364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
365 /* 0x23 - 1280x1024@60Hz */
366 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
367 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
369 /* 0x24 - 1280x1024@75Hz */
370 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
371 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
373 /* 0x25 - 1280x1024@85Hz */
374 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
375 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
377 /* 0x26 - 1280x1024@120Hz RB */
378 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
379 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
381 /* 0x27 - 1360x768@60Hz */
382 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
383 1536, 1792, 0, 768, 771, 777, 795, 0,
384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
385 /* 0x28 - 1360x768@120Hz RB */
386 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
387 1440, 1520, 0, 768, 771, 776, 813, 0,
388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
389 /* 0x51 - 1366x768@60Hz */
390 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
391 1579, 1792, 0, 768, 771, 774, 798, 0,
392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
393 /* 0x56 - 1366x768@60Hz */
394 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
395 1436, 1500, 0, 768, 769, 772, 800, 0,
396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
397 /* 0x29 - 1400x1050@60Hz RB */
398 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
399 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
401 /* 0x2a - 1400x1050@60Hz */
402 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
403 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
404 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
405 /* 0x2b - 1400x1050@75Hz */
406 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
407 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
408 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
409 /* 0x2c - 1400x1050@85Hz */
410 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
411 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
412 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
413 /* 0x2d - 1400x1050@120Hz RB */
414 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
415 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
417 /* 0x2e - 1440x900@60Hz RB */
418 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
419 1520, 1600, 0, 900, 903, 909, 926, 0,
420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
421 /* 0x2f - 1440x900@60Hz */
422 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
423 1672, 1904, 0, 900, 903, 909, 934, 0,
424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
425 /* 0x30 - 1440x900@75Hz */
426 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
427 1688, 1936, 0, 900, 903, 909, 942, 0,
428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
429 /* 0x31 - 1440x900@85Hz */
430 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
431 1696, 1952, 0, 900, 903, 909, 948, 0,
432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
433 /* 0x32 - 1440x900@120Hz RB */
434 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
435 1520, 1600, 0, 900, 903, 909, 953, 0,
436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
437 /* 0x53 - 1600x900@60Hz */
438 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
439 1704, 1800, 0, 900, 901, 904, 1000, 0,
440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
441 /* 0x33 - 1600x1200@60Hz */
442 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
443 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
445 /* 0x34 - 1600x1200@65Hz */
446 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
447 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
449 /* 0x35 - 1600x1200@70Hz */
450 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
451 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
453 /* 0x36 - 1600x1200@75Hz */
454 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
455 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
457 /* 0x37 - 1600x1200@85Hz */
458 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
459 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
461 /* 0x38 - 1600x1200@120Hz RB */
462 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
463 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
465 /* 0x39 - 1680x1050@60Hz RB */
466 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
467 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
469 /* 0x3a - 1680x1050@60Hz */
470 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
471 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
472 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
473 /* 0x3b - 1680x1050@75Hz */
474 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
475 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
477 /* 0x3c - 1680x1050@85Hz */
478 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
479 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
480 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
481 /* 0x3d - 1680x1050@120Hz RB */
482 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
483 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
485 /* 0x3e - 1792x1344@60Hz */
486 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
487 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
489 /* 0x3f - 1792x1344@75Hz */
490 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
491 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
493 /* 0x40 - 1792x1344@120Hz RB */
494 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
495 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
497 /* 0x41 - 1856x1392@60Hz */
498 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
499 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
500 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
501 /* 0x42 - 1856x1392@75Hz */
502 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
503 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
505 /* 0x43 - 1856x1392@120Hz RB */
506 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
507 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
509 /* 0x52 - 1920x1080@60Hz */
510 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
511 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
513 /* 0x44 - 1920x1200@60Hz RB */
514 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
515 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
517 /* 0x45 - 1920x1200@60Hz */
518 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
519 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
521 /* 0x46 - 1920x1200@75Hz */
522 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
523 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
525 /* 0x47 - 1920x1200@85Hz */
526 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
527 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
528 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
529 /* 0x48 - 1920x1200@120Hz RB */
530 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
531 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
533 /* 0x49 - 1920x1440@60Hz */
534 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
535 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
537 /* 0x4a - 1920x1440@75Hz */
538 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
539 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
541 /* 0x4b - 1920x1440@120Hz RB */
542 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
543 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
544 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
545 /* 0x54 - 2048x1152@60Hz */
546 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
547 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
549 /* 0x4c - 2560x1600@60Hz RB */
550 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
551 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
553 /* 0x4d - 2560x1600@60Hz */
554 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
555 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
557 /* 0x4e - 2560x1600@75Hz */
558 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
559 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
561 /* 0x4f - 2560x1600@85Hz */
562 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
563 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
564 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
565 /* 0x50 - 2560x1600@120Hz RB */
566 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
567 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
569 /* 0x57 - 4096x2160@60Hz RB */
570 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
571 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
573 /* 0x58 - 4096x2160@59.94Hz RB */
574 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
575 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
580 * These more or less come from the DMT spec. The 720x400 modes are
581 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
582 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
583 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
586 * The DMT modes have been fact-checked; the rest are mild guesses.
588 static const struct drm_display_mode edid_est_modes[] = {
589 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
590 968, 1056, 0, 600, 601, 605, 628, 0,
591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
592 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
593 896, 1024, 0, 600, 601, 603, 625, 0,
594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
595 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
596 720, 840, 0, 480, 481, 484, 500, 0,
597 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
598 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
599 704, 832, 0, 480, 489, 492, 520, 0,
600 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
601 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
602 768, 864, 0, 480, 483, 486, 525, 0,
603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
604 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
605 752, 800, 0, 480, 490, 492, 525, 0,
606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
607 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
608 846, 900, 0, 400, 421, 423, 449, 0,
609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
610 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
611 846, 900, 0, 400, 412, 414, 449, 0,
612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
613 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
614 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
616 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
617 1136, 1312, 0, 768, 769, 772, 800, 0,
618 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
619 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
620 1184, 1328, 0, 768, 771, 777, 806, 0,
621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
622 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
623 1184, 1344, 0, 768, 771, 777, 806, 0,
624 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
625 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
626 1208, 1264, 0, 768, 768, 776, 817, 0,
627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
628 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
629 928, 1152, 0, 624, 625, 628, 667, 0,
630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
631 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
632 896, 1056, 0, 600, 601, 604, 625, 0,
633 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
634 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
635 976, 1040, 0, 600, 637, 643, 666, 0,
636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
637 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
638 1344, 1600, 0, 864, 865, 868, 900, 0,
639 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
649 static const struct minimode est3_modes[] = {
657 { 1024, 768, 85, 0 },
658 { 1152, 864, 75, 0 },
660 { 1280, 768, 60, 1 },
661 { 1280, 768, 60, 0 },
662 { 1280, 768, 75, 0 },
663 { 1280, 768, 85, 0 },
664 { 1280, 960, 60, 0 },
665 { 1280, 960, 85, 0 },
666 { 1280, 1024, 60, 0 },
667 { 1280, 1024, 85, 0 },
669 { 1360, 768, 60, 0 },
670 { 1440, 900, 60, 1 },
671 { 1440, 900, 60, 0 },
672 { 1440, 900, 75, 0 },
673 { 1440, 900, 85, 0 },
674 { 1400, 1050, 60, 1 },
675 { 1400, 1050, 60, 0 },
676 { 1400, 1050, 75, 0 },
678 { 1400, 1050, 85, 0 },
679 { 1680, 1050, 60, 1 },
680 { 1680, 1050, 60, 0 },
681 { 1680, 1050, 75, 0 },
682 { 1680, 1050, 85, 0 },
683 { 1600, 1200, 60, 0 },
684 { 1600, 1200, 65, 0 },
685 { 1600, 1200, 70, 0 },
687 { 1600, 1200, 75, 0 },
688 { 1600, 1200, 85, 0 },
689 { 1792, 1344, 60, 0 },
690 { 1792, 1344, 75, 0 },
691 { 1856, 1392, 60, 0 },
692 { 1856, 1392, 75, 0 },
693 { 1920, 1200, 60, 1 },
694 { 1920, 1200, 60, 0 },
696 { 1920, 1200, 75, 0 },
697 { 1920, 1200, 85, 0 },
698 { 1920, 1440, 60, 0 },
699 { 1920, 1440, 75, 0 },
702 static const struct minimode extra_modes[] = {
703 { 1024, 576, 60, 0 },
704 { 1366, 768, 60, 0 },
705 { 1600, 900, 60, 0 },
706 { 1680, 945, 60, 0 },
707 { 1920, 1080, 60, 0 },
708 { 2048, 1152, 60, 0 },
709 { 2048, 1536, 60, 0 },
713 * Probably taken from CEA-861 spec.
714 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
716 * Index using the VIC.
718 static const struct drm_display_mode edid_cea_modes[] = {
719 /* 0 - dummy, VICs start at 1 */
721 /* 1 - 640x480@60Hz 4:3 */
722 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
723 752, 800, 0, 480, 490, 492, 525, 0,
724 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
725 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
726 /* 2 - 720x480@60Hz 4:3 */
727 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
728 798, 858, 0, 480, 489, 495, 525, 0,
729 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
730 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
731 /* 3 - 720x480@60Hz 16:9 */
732 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
733 798, 858, 0, 480, 489, 495, 525, 0,
734 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
735 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
736 /* 4 - 1280x720@60Hz 16:9 */
737 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
738 1430, 1650, 0, 720, 725, 730, 750, 0,
739 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
740 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
741 /* 5 - 1920x1080i@60Hz 16:9 */
742 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
743 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
744 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
745 DRM_MODE_FLAG_INTERLACE),
746 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
747 /* 6 - 720(1440)x480i@60Hz 4:3 */
748 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
749 801, 858, 0, 480, 488, 494, 525, 0,
750 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
751 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
752 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
753 /* 7 - 720(1440)x480i@60Hz 16:9 */
754 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
755 801, 858, 0, 480, 488, 494, 525, 0,
756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
757 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
758 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
759 /* 8 - 720(1440)x240@60Hz 4:3 */
760 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
761 801, 858, 0, 240, 244, 247, 262, 0,
762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
763 DRM_MODE_FLAG_DBLCLK),
764 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
765 /* 9 - 720(1440)x240@60Hz 16:9 */
766 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
767 801, 858, 0, 240, 244, 247, 262, 0,
768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
769 DRM_MODE_FLAG_DBLCLK),
770 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
771 /* 10 - 2880x480i@60Hz 4:3 */
772 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
773 3204, 3432, 0, 480, 488, 494, 525, 0,
774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
775 DRM_MODE_FLAG_INTERLACE),
776 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
777 /* 11 - 2880x480i@60Hz 16:9 */
778 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
779 3204, 3432, 0, 480, 488, 494, 525, 0,
780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
781 DRM_MODE_FLAG_INTERLACE),
782 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
783 /* 12 - 2880x240@60Hz 4:3 */
784 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
785 3204, 3432, 0, 240, 244, 247, 262, 0,
786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
787 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
788 /* 13 - 2880x240@60Hz 16:9 */
789 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
790 3204, 3432, 0, 240, 244, 247, 262, 0,
791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
792 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
793 /* 14 - 1440x480@60Hz 4:3 */
794 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
795 1596, 1716, 0, 480, 489, 495, 525, 0,
796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
797 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
798 /* 15 - 1440x480@60Hz 16:9 */
799 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
800 1596, 1716, 0, 480, 489, 495, 525, 0,
801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
802 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
803 /* 16 - 1920x1080@60Hz 16:9 */
804 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
805 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
806 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
807 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
808 /* 17 - 720x576@50Hz 4:3 */
809 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
810 796, 864, 0, 576, 581, 586, 625, 0,
811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
812 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
813 /* 18 - 720x576@50Hz 16:9 */
814 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
815 796, 864, 0, 576, 581, 586, 625, 0,
816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
817 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
818 /* 19 - 1280x720@50Hz 16:9 */
819 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
820 1760, 1980, 0, 720, 725, 730, 750, 0,
821 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
822 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
823 /* 20 - 1920x1080i@50Hz 16:9 */
824 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
825 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
826 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
827 DRM_MODE_FLAG_INTERLACE),
828 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
829 /* 21 - 720(1440)x576i@50Hz 4:3 */
830 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
831 795, 864, 0, 576, 580, 586, 625, 0,
832 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
833 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
834 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
835 /* 22 - 720(1440)x576i@50Hz 16:9 */
836 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
837 795, 864, 0, 576, 580, 586, 625, 0,
838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
839 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
840 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
841 /* 23 - 720(1440)x288@50Hz 4:3 */
842 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
843 795, 864, 0, 288, 290, 293, 312, 0,
844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
845 DRM_MODE_FLAG_DBLCLK),
846 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
847 /* 24 - 720(1440)x288@50Hz 16:9 */
848 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
849 795, 864, 0, 288, 290, 293, 312, 0,
850 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
851 DRM_MODE_FLAG_DBLCLK),
852 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
853 /* 25 - 2880x576i@50Hz 4:3 */
854 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
855 3180, 3456, 0, 576, 580, 586, 625, 0,
856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
857 DRM_MODE_FLAG_INTERLACE),
858 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
859 /* 26 - 2880x576i@50Hz 16:9 */
860 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
861 3180, 3456, 0, 576, 580, 586, 625, 0,
862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
863 DRM_MODE_FLAG_INTERLACE),
864 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
865 /* 27 - 2880x288@50Hz 4:3 */
866 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
867 3180, 3456, 0, 288, 290, 293, 312, 0,
868 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
869 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
870 /* 28 - 2880x288@50Hz 16:9 */
871 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
872 3180, 3456, 0, 288, 290, 293, 312, 0,
873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
874 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
875 /* 29 - 1440x576@50Hz 4:3 */
876 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
877 1592, 1728, 0, 576, 581, 586, 625, 0,
878 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
879 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
880 /* 30 - 1440x576@50Hz 16:9 */
881 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
882 1592, 1728, 0, 576, 581, 586, 625, 0,
883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
884 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
885 /* 31 - 1920x1080@50Hz 16:9 */
886 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
887 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
888 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
889 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
890 /* 32 - 1920x1080@24Hz 16:9 */
891 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
892 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
893 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
894 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
895 /* 33 - 1920x1080@25Hz 16:9 */
896 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
897 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
898 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
899 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
900 /* 34 - 1920x1080@30Hz 16:9 */
901 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
902 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
903 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
904 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
905 /* 35 - 2880x480@60Hz 4:3 */
906 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
907 3192, 3432, 0, 480, 489, 495, 525, 0,
908 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
909 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
910 /* 36 - 2880x480@60Hz 16:9 */
911 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
912 3192, 3432, 0, 480, 489, 495, 525, 0,
913 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
914 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
915 /* 37 - 2880x576@50Hz 4:3 */
916 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
917 3184, 3456, 0, 576, 581, 586, 625, 0,
918 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
919 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
920 /* 38 - 2880x576@50Hz 16:9 */
921 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
922 3184, 3456, 0, 576, 581, 586, 625, 0,
923 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
924 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
925 /* 39 - 1920x1080i@50Hz 16:9 */
926 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
927 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
928 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
929 DRM_MODE_FLAG_INTERLACE),
930 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
931 /* 40 - 1920x1080i@100Hz 16:9 */
932 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
933 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
934 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
935 DRM_MODE_FLAG_INTERLACE),
936 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
937 /* 41 - 1280x720@100Hz 16:9 */
938 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
939 1760, 1980, 0, 720, 725, 730, 750, 0,
940 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
941 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
942 /* 42 - 720x576@100Hz 4:3 */
943 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
944 796, 864, 0, 576, 581, 586, 625, 0,
945 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
946 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
947 /* 43 - 720x576@100Hz 16:9 */
948 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
949 796, 864, 0, 576, 581, 586, 625, 0,
950 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
951 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
952 /* 44 - 720(1440)x576i@100Hz 4:3 */
953 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
954 795, 864, 0, 576, 580, 586, 625, 0,
955 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
956 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
957 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
958 /* 45 - 720(1440)x576i@100Hz 16:9 */
959 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
960 795, 864, 0, 576, 580, 586, 625, 0,
961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
962 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
963 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
964 /* 46 - 1920x1080i@120Hz 16:9 */
965 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
966 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
967 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
968 DRM_MODE_FLAG_INTERLACE),
969 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
970 /* 47 - 1280x720@120Hz 16:9 */
971 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
972 1430, 1650, 0, 720, 725, 730, 750, 0,
973 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
974 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
975 /* 48 - 720x480@120Hz 4:3 */
976 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
977 798, 858, 0, 480, 489, 495, 525, 0,
978 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
979 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
980 /* 49 - 720x480@120Hz 16:9 */
981 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
982 798, 858, 0, 480, 489, 495, 525, 0,
983 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
984 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
985 /* 50 - 720(1440)x480i@120Hz 4:3 */
986 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
987 801, 858, 0, 480, 488, 494, 525, 0,
988 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
989 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
990 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
991 /* 51 - 720(1440)x480i@120Hz 16:9 */
992 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
993 801, 858, 0, 480, 488, 494, 525, 0,
994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
995 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
996 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
997 /* 52 - 720x576@200Hz 4:3 */
998 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
999 796, 864, 0, 576, 581, 586, 625, 0,
1000 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1001 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1002 /* 53 - 720x576@200Hz 16:9 */
1003 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1004 796, 864, 0, 576, 581, 586, 625, 0,
1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1006 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1007 /* 54 - 720(1440)x576i@200Hz 4:3 */
1008 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1009 795, 864, 0, 576, 580, 586, 625, 0,
1010 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1011 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1012 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1013 /* 55 - 720(1440)x576i@200Hz 16:9 */
1014 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1015 795, 864, 0, 576, 580, 586, 625, 0,
1016 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1017 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1018 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1019 /* 56 - 720x480@240Hz 4:3 */
1020 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1021 798, 858, 0, 480, 489, 495, 525, 0,
1022 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1023 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1024 /* 57 - 720x480@240Hz 16:9 */
1025 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1026 798, 858, 0, 480, 489, 495, 525, 0,
1027 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1028 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1029 /* 58 - 720(1440)x480i@240Hz 4:3 */
1030 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1031 801, 858, 0, 480, 488, 494, 525, 0,
1032 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1033 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1034 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1035 /* 59 - 720(1440)x480i@240Hz 16:9 */
1036 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1037 801, 858, 0, 480, 488, 494, 525, 0,
1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1039 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1040 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1041 /* 60 - 1280x720@24Hz 16:9 */
1042 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1043 3080, 3300, 0, 720, 725, 730, 750, 0,
1044 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1045 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1046 /* 61 - 1280x720@25Hz 16:9 */
1047 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1048 3740, 3960, 0, 720, 725, 730, 750, 0,
1049 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1050 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1051 /* 62 - 1280x720@30Hz 16:9 */
1052 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1053 3080, 3300, 0, 720, 725, 730, 750, 0,
1054 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1055 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1056 /* 63 - 1920x1080@120Hz 16:9 */
1057 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1058 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1059 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1060 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1061 /* 64 - 1920x1080@100Hz 16:9 */
1062 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1063 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1064 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1065 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1066 /* 65 - 1280x720@24Hz 64:27 */
1067 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1068 3080, 3300, 0, 720, 725, 730, 750, 0,
1069 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1070 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1071 /* 66 - 1280x720@25Hz 64:27 */
1072 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1073 3740, 3960, 0, 720, 725, 730, 750, 0,
1074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1075 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1076 /* 67 - 1280x720@30Hz 64:27 */
1077 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1078 3080, 3300, 0, 720, 725, 730, 750, 0,
1079 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1080 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1081 /* 68 - 1280x720@50Hz 64:27 */
1082 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1083 1760, 1980, 0, 720, 725, 730, 750, 0,
1084 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1085 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1086 /* 69 - 1280x720@60Hz 64:27 */
1087 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1088 1430, 1650, 0, 720, 725, 730, 750, 0,
1089 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1090 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1091 /* 70 - 1280x720@100Hz 64:27 */
1092 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1093 1760, 1980, 0, 720, 725, 730, 750, 0,
1094 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1095 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1096 /* 71 - 1280x720@120Hz 64:27 */
1097 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1098 1430, 1650, 0, 720, 725, 730, 750, 0,
1099 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1100 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1101 /* 72 - 1920x1080@24Hz 64:27 */
1102 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1103 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1105 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1106 /* 73 - 1920x1080@25Hz 64:27 */
1107 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1108 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1109 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1110 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1111 /* 74 - 1920x1080@30Hz 64:27 */
1112 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1113 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1114 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1115 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1116 /* 75 - 1920x1080@50Hz 64:27 */
1117 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1118 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1119 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1120 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1121 /* 76 - 1920x1080@60Hz 64:27 */
1122 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1123 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1124 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1125 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1126 /* 77 - 1920x1080@100Hz 64:27 */
1127 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1128 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1129 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1130 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1131 /* 78 - 1920x1080@120Hz 64:27 */
1132 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1133 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1135 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1136 /* 79 - 1680x720@24Hz 64:27 */
1137 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1138 3080, 3300, 0, 720, 725, 730, 750, 0,
1139 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1140 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1141 /* 80 - 1680x720@25Hz 64:27 */
1142 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1143 2948, 3168, 0, 720, 725, 730, 750, 0,
1144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1145 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1146 /* 81 - 1680x720@30Hz 64:27 */
1147 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1148 2420, 2640, 0, 720, 725, 730, 750, 0,
1149 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1150 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1151 /* 82 - 1680x720@50Hz 64:27 */
1152 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1153 1980, 2200, 0, 720, 725, 730, 750, 0,
1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1155 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1156 /* 83 - 1680x720@60Hz 64:27 */
1157 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1158 1980, 2200, 0, 720, 725, 730, 750, 0,
1159 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1160 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1161 /* 84 - 1680x720@100Hz 64:27 */
1162 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1163 1780, 2000, 0, 720, 725, 730, 825, 0,
1164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1165 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1166 /* 85 - 1680x720@120Hz 64:27 */
1167 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1168 1780, 2000, 0, 720, 725, 730, 825, 0,
1169 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1170 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1171 /* 86 - 2560x1080@24Hz 64:27 */
1172 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1173 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1175 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1176 /* 87 - 2560x1080@25Hz 64:27 */
1177 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1178 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1180 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1181 /* 88 - 2560x1080@30Hz 64:27 */
1182 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1183 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1185 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1186 /* 89 - 2560x1080@50Hz 64:27 */
1187 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1188 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1190 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1191 /* 90 - 2560x1080@60Hz 64:27 */
1192 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1193 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1195 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1196 /* 91 - 2560x1080@100Hz 64:27 */
1197 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1198 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1200 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1201 /* 92 - 2560x1080@120Hz 64:27 */
1202 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1203 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1205 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1206 /* 93 - 3840x2160@24Hz 16:9 */
1207 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1208 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1210 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1211 /* 94 - 3840x2160@25Hz 16:9 */
1212 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1213 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1215 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1216 /* 95 - 3840x2160@30Hz 16:9 */
1217 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1218 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1220 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1221 /* 96 - 3840x2160@50Hz 16:9 */
1222 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1223 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1225 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1226 /* 97 - 3840x2160@60Hz 16:9 */
1227 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1228 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1230 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1231 /* 98 - 4096x2160@24Hz 256:135 */
1232 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1233 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1235 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1236 /* 99 - 4096x2160@25Hz 256:135 */
1237 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1238 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1240 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1241 /* 100 - 4096x2160@30Hz 256:135 */
1242 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1243 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1245 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1246 /* 101 - 4096x2160@50Hz 256:135 */
1247 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1248 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1250 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1251 /* 102 - 4096x2160@60Hz 256:135 */
1252 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1253 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1255 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1256 /* 103 - 3840x2160@24Hz 64:27 */
1257 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1258 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1260 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1261 /* 104 - 3840x2160@25Hz 64:27 */
1262 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1263 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1265 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1266 /* 105 - 3840x2160@30Hz 64:27 */
1267 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1268 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1270 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1271 /* 106 - 3840x2160@50Hz 64:27 */
1272 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1273 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1275 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1276 /* 107 - 3840x2160@60Hz 64:27 */
1277 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1278 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1280 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1284 * HDMI 1.4 4k modes. Index using the VIC.
1286 static const struct drm_display_mode edid_4k_modes[] = {
1287 /* 0 - dummy, VICs start at 1 */
1289 /* 1 - 3840x2160@30Hz */
1290 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1291 3840, 4016, 4104, 4400, 0,
1292 2160, 2168, 2178, 2250, 0,
1293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1295 /* 2 - 3840x2160@25Hz */
1296 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1297 3840, 4896, 4984, 5280, 0,
1298 2160, 2168, 2178, 2250, 0,
1299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1301 /* 3 - 3840x2160@24Hz */
1302 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1303 3840, 5116, 5204, 5500, 0,
1304 2160, 2168, 2178, 2250, 0,
1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1307 /* 4 - 4096x2160@24Hz (SMPTE) */
1308 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1309 4096, 5116, 5204, 5500, 0,
1310 2160, 2168, 2178, 2250, 0,
1311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1315 /*** DDC fetch and block validation ***/
1317 static const u8 edid_header[] = {
1318 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1322 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1323 * @raw_edid: pointer to raw base EDID block
1325 * Sanity check the header of the base EDID block.
1327 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1329 int drm_edid_header_is_valid(const u8 *raw_edid)
1333 for (i = 0; i < sizeof(edid_header); i++)
1334 if (raw_edid[i] == edid_header[i])
1339 EXPORT_SYMBOL(drm_edid_header_is_valid);
1341 static int edid_fixup __read_mostly = 6;
1342 module_param_named(edid_fixup, edid_fixup, int, 0400);
1343 MODULE_PARM_DESC(edid_fixup,
1344 "Minimum number of valid EDID header bytes (0-8, default 6)");
1346 static void drm_get_displayid(struct drm_connector *connector,
1348 static int validate_displayid(u8 *displayid, int length, int idx);
1350 static int drm_edid_block_checksum(const u8 *raw_edid)
1354 for (i = 0; i < EDID_LENGTH; i++)
1355 csum += raw_edid[i];
1360 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1362 if (memchr_inv(in_edid, 0, length))
1369 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1370 * @raw_edid: pointer to raw EDID block
1371 * @block: type of block to validate (0 for base, extension otherwise)
1372 * @print_bad_edid: if true, dump bad EDID blocks to the console
1373 * @edid_corrupt: if true, the header or checksum is invalid
1375 * Validate a base or extension EDID block and optionally dump bad blocks to
1378 * Return: True if the block is valid, false otherwise.
1380 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1384 struct edid *edid = (struct edid *)raw_edid;
1386 if (WARN_ON(!raw_edid))
1389 if (edid_fixup > 8 || edid_fixup < 0)
1393 int score = drm_edid_header_is_valid(raw_edid);
1396 *edid_corrupt = false;
1397 } else if (score >= edid_fixup) {
1398 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1399 * The corrupt flag needs to be set here otherwise, the
1400 * fix-up code here will correct the problem, the
1401 * checksum is correct and the test fails
1404 *edid_corrupt = true;
1405 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1406 memcpy(raw_edid, edid_header, sizeof(edid_header));
1409 *edid_corrupt = true;
1414 csum = drm_edid_block_checksum(raw_edid);
1417 *edid_corrupt = true;
1419 /* allow CEA to slide through, switches mangle this */
1420 if (raw_edid[0] == CEA_EXT) {
1421 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1422 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1425 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1431 /* per-block-type checks */
1432 switch (raw_edid[0]) {
1434 if (edid->version != 1) {
1435 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1439 if (edid->revision > 4)
1440 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1450 if (print_bad_edid) {
1451 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1452 pr_notice("EDID block is all zeroes\n");
1454 pr_notice("Raw EDID:\n");
1455 print_hex_dump(KERN_NOTICE,
1456 " \t", DUMP_PREFIX_NONE, 16, 1,
1457 raw_edid, EDID_LENGTH, false);
1462 EXPORT_SYMBOL(drm_edid_block_valid);
1465 * drm_edid_is_valid - sanity check EDID data
1468 * Sanity-check an entire EDID record (including extensions)
1470 * Return: True if the EDID data is valid, false otherwise.
1472 bool drm_edid_is_valid(struct edid *edid)
1475 u8 *raw = (u8 *)edid;
1480 for (i = 0; i <= edid->extensions; i++)
1481 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1486 EXPORT_SYMBOL(drm_edid_is_valid);
1488 #define DDC_SEGMENT_ADDR 0x30
1490 * drm_do_probe_ddc_edid() - get EDID information via I2C
1491 * @data: I2C device adapter
1492 * @buf: EDID data buffer to be filled
1493 * @block: 128 byte EDID block to start fetching from
1494 * @len: EDID data buffer length to fetch
1496 * Try to fetch EDID information by calling I2C driver functions.
1498 * Return: 0 on success or -1 on failure.
1501 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1503 struct i2c_adapter *adapter = data;
1504 unsigned char start = block * EDID_LENGTH;
1505 unsigned char segment = block >> 1;
1506 unsigned char xfers = segment ? 3 : 2;
1507 int ret, retries = 5;
1510 * The core I2C driver will automatically retry the transfer if the
1511 * adapter reports EAGAIN. However, we find that bit-banging transfers
1512 * are susceptible to errors under a heavily loaded machine and
1513 * generate spurious NAKs and timeouts. Retrying the transfer
1514 * of the individual block a few times seems to overcome this.
1517 struct i2c_msg msgs[] = {
1519 .addr = DDC_SEGMENT_ADDR,
1537 * Avoid sending the segment addr to not upset non-compliant
1540 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1542 if (ret == -ENXIO) {
1543 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1547 } while (ret != xfers && --retries);
1549 return ret == xfers ? 0 : -1;
1552 static void connector_bad_edid(struct drm_connector *connector,
1553 u8 *edid, int num_blocks)
1557 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1560 dev_warn(connector->dev->dev,
1561 "%s: EDID is invalid:\n",
1563 for (i = 0; i < num_blocks; i++) {
1564 u8 *block = edid + i * EDID_LENGTH;
1567 if (drm_edid_is_zero(block, EDID_LENGTH))
1568 sprintf(prefix, "\t[%02x] ZERO ", i);
1569 else if (!drm_edid_block_valid(block, i, false, NULL))
1570 sprintf(prefix, "\t[%02x] BAD ", i);
1572 sprintf(prefix, "\t[%02x] GOOD ", i);
1574 print_hex_dump(KERN_WARNING,
1575 prefix, DUMP_PREFIX_NONE, 16, 1,
1576 block, EDID_LENGTH, false);
1580 /* Get override or firmware EDID */
1581 static struct edid *drm_get_override_edid(struct drm_connector *connector)
1583 struct edid *override = NULL;
1585 if (connector->override_edid)
1586 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1589 override = drm_load_edid_firmware(connector);
1591 return IS_ERR(override) ? NULL : override;
1595 * drm_add_override_edid_modes - add modes from override/firmware EDID
1596 * @connector: connector we're probing
1598 * Add modes from the override/firmware EDID, if available. Only to be used from
1599 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1600 * failed during drm_get_edid() and caused the override/firmware EDID to be
1603 * Return: The number of modes added or 0 if we couldn't find any.
1605 int drm_add_override_edid_modes(struct drm_connector *connector)
1607 struct edid *override;
1610 override = drm_get_override_edid(connector);
1612 drm_connector_update_edid_property(connector, override);
1613 num_modes = drm_add_edid_modes(connector, override);
1616 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1617 connector->base.id, connector->name, num_modes);
1622 EXPORT_SYMBOL(drm_add_override_edid_modes);
1625 * drm_do_get_edid - get EDID data using a custom EDID block read function
1626 * @connector: connector we're probing
1627 * @get_edid_block: EDID block read function
1628 * @data: private data passed to the block read function
1630 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1631 * exposes a different interface to read EDID blocks this function can be used
1632 * to get EDID data using a custom block read function.
1634 * As in the general case the DDC bus is accessible by the kernel at the I2C
1635 * level, drivers must make all reasonable efforts to expose it as an I2C
1636 * adapter and use drm_get_edid() instead of abusing this function.
1638 * The EDID may be overridden using debugfs override_edid or firmare EDID
1639 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1640 * order. Having either of them bypasses actual EDID reads.
1642 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1644 struct edid *drm_do_get_edid(struct drm_connector *connector,
1645 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1649 int i, j = 0, valid_extensions = 0;
1651 struct edid *override;
1653 override = drm_get_override_edid(connector);
1657 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1660 /* base block fetch */
1661 for (i = 0; i < 4; i++) {
1662 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1664 if (drm_edid_block_valid(edid, 0, false,
1665 &connector->edid_corrupt))
1667 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1668 connector->null_edid_counter++;
1675 /* if there's no extensions, we're done */
1676 valid_extensions = edid[0x7e];
1677 if (valid_extensions == 0)
1678 return (struct edid *)edid;
1680 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1685 for (j = 1; j <= edid[0x7e]; j++) {
1686 u8 *block = edid + j * EDID_LENGTH;
1688 for (i = 0; i < 4; i++) {
1689 if (get_edid_block(data, block, j, EDID_LENGTH))
1691 if (drm_edid_block_valid(block, j, false, NULL))
1699 if (valid_extensions != edid[0x7e]) {
1702 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1704 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1705 edid[0x7e] = valid_extensions;
1707 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1713 for (i = 0; i <= edid[0x7e]; i++) {
1714 u8 *block = edid + i * EDID_LENGTH;
1716 if (!drm_edid_block_valid(block, i, false, NULL))
1719 memcpy(base, block, EDID_LENGTH);
1720 base += EDID_LENGTH;
1727 return (struct edid *)edid;
1730 connector_bad_edid(connector, edid, 1);
1735 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1738 * drm_probe_ddc() - probe DDC presence
1739 * @adapter: I2C adapter to probe
1741 * Return: True on success, false on failure.
1744 drm_probe_ddc(struct i2c_adapter *adapter)
1748 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1750 EXPORT_SYMBOL(drm_probe_ddc);
1753 * drm_get_edid - get EDID data, if available
1754 * @connector: connector we're probing
1755 * @adapter: I2C adapter to use for DDC
1757 * Poke the given I2C channel to grab EDID data if possible. If found,
1758 * attach it to the connector.
1760 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1762 struct edid *drm_get_edid(struct drm_connector *connector,
1763 struct i2c_adapter *adapter)
1767 if (connector->force == DRM_FORCE_OFF)
1770 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1773 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1775 drm_get_displayid(connector, edid);
1778 EXPORT_SYMBOL(drm_get_edid);
1781 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1782 * @connector: connector we're probing
1783 * @adapter: I2C adapter to use for DDC
1785 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1786 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1787 * switch DDC to the GPU which is retrieving EDID.
1789 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1791 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1792 struct i2c_adapter *adapter)
1794 struct pci_dev *pdev = connector->dev->pdev;
1797 vga_switcheroo_lock_ddc(pdev);
1798 edid = drm_get_edid(connector, adapter);
1799 vga_switcheroo_unlock_ddc(pdev);
1803 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1806 * drm_edid_duplicate - duplicate an EDID and the extensions
1807 * @edid: EDID to duplicate
1809 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1811 struct edid *drm_edid_duplicate(const struct edid *edid)
1813 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1815 EXPORT_SYMBOL(drm_edid_duplicate);
1817 /*** EDID parsing ***/
1820 * edid_vendor - match a string against EDID's obfuscated vendor field
1821 * @edid: EDID to match
1822 * @vendor: vendor string
1824 * Returns true if @vendor is in @edid, false otherwise
1826 static bool edid_vendor(const struct edid *edid, const char *vendor)
1828 char edid_vendor[3];
1830 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1831 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1832 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1833 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1835 return !strncmp(edid_vendor, vendor, 3);
1839 * edid_get_quirks - return quirk flags for a given EDID
1840 * @edid: EDID to process
1842 * This tells subsequent routines what fixes they need to apply.
1844 static u32 edid_get_quirks(const struct edid *edid)
1846 const struct edid_quirk *quirk;
1849 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1850 quirk = &edid_quirk_list[i];
1852 if (edid_vendor(edid, quirk->vendor) &&
1853 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1854 return quirk->quirks;
1860 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1861 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1864 * edid_fixup_preferred - set preferred modes based on quirk list
1865 * @connector: has mode list to fix up
1866 * @quirks: quirks list
1868 * Walk the mode list for @connector, clearing the preferred status
1869 * on existing modes and setting it anew for the right mode ala @quirks.
1871 static void edid_fixup_preferred(struct drm_connector *connector,
1874 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1875 int target_refresh = 0;
1876 int cur_vrefresh, preferred_vrefresh;
1878 if (list_empty(&connector->probed_modes))
1881 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1882 target_refresh = 60;
1883 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1884 target_refresh = 75;
1886 preferred_mode = list_first_entry(&connector->probed_modes,
1887 struct drm_display_mode, head);
1889 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1890 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1892 if (cur_mode == preferred_mode)
1895 /* Largest mode is preferred */
1896 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1897 preferred_mode = cur_mode;
1899 cur_vrefresh = cur_mode->vrefresh ?
1900 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1901 preferred_vrefresh = preferred_mode->vrefresh ?
1902 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1903 /* At a given size, try to get closest to target refresh */
1904 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1905 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1906 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1907 preferred_mode = cur_mode;
1911 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1915 mode_is_rb(const struct drm_display_mode *mode)
1917 return (mode->htotal - mode->hdisplay == 160) &&
1918 (mode->hsync_end - mode->hdisplay == 80) &&
1919 (mode->hsync_end - mode->hsync_start == 32) &&
1920 (mode->vsync_start - mode->vdisplay == 3);
1924 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1925 * @dev: Device to duplicate against
1926 * @hsize: Mode width
1927 * @vsize: Mode height
1928 * @fresh: Mode refresh rate
1929 * @rb: Mode reduced-blanking-ness
1931 * Walk the DMT mode list looking for a match for the given parameters.
1933 * Return: A newly allocated copy of the mode, or NULL if not found.
1935 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1936 int hsize, int vsize, int fresh,
1941 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1942 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1943 if (hsize != ptr->hdisplay)
1945 if (vsize != ptr->vdisplay)
1947 if (fresh != drm_mode_vrefresh(ptr))
1949 if (rb != mode_is_rb(ptr))
1952 return drm_mode_duplicate(dev, ptr);
1957 EXPORT_SYMBOL(drm_mode_find_dmt);
1959 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1962 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1966 u8 *det_base = ext + d;
1969 for (i = 0; i < n; i++)
1970 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1974 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1976 unsigned int i, n = min((int)ext[0x02], 6);
1977 u8 *det_base = ext + 5;
1980 return; /* unknown version */
1982 for (i = 0; i < n; i++)
1983 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1987 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1990 struct edid *edid = (struct edid *)raw_edid;
1995 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1996 cb(&(edid->detailed_timings[i]), closure);
1998 for (i = 1; i <= raw_edid[0x7e]; i++) {
1999 u8 *ext = raw_edid + (i * EDID_LENGTH);
2002 cea_for_each_detailed_block(ext, cb, closure);
2005 vtb_for_each_detailed_block(ext, cb, closure);
2014 is_rb(struct detailed_timing *t, void *data)
2017 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
2019 *(bool *)data = true;
2022 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2024 drm_monitor_supports_rb(struct edid *edid)
2026 if (edid->revision >= 4) {
2028 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
2032 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2036 find_gtf2(struct detailed_timing *t, void *data)
2039 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
2043 /* Secondary GTF curve kicks in above some break frequency */
2045 drm_gtf2_hbreak(struct edid *edid)
2048 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2049 return r ? (r[12] * 2) : 0;
2053 drm_gtf2_2c(struct edid *edid)
2056 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2057 return r ? r[13] : 0;
2061 drm_gtf2_m(struct edid *edid)
2064 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2065 return r ? (r[15] << 8) + r[14] : 0;
2069 drm_gtf2_k(struct edid *edid)
2072 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2073 return r ? r[16] : 0;
2077 drm_gtf2_2j(struct edid *edid)
2080 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2081 return r ? r[17] : 0;
2085 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2086 * @edid: EDID block to scan
2088 static int standard_timing_level(struct edid *edid)
2090 if (edid->revision >= 2) {
2091 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2093 if (drm_gtf2_hbreak(edid))
2101 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2102 * monitors fill with ascii space (0x20) instead.
2105 bad_std_timing(u8 a, u8 b)
2107 return (a == 0x00 && b == 0x00) ||
2108 (a == 0x01 && b == 0x01) ||
2109 (a == 0x20 && b == 0x20);
2113 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2114 * @connector: connector of for the EDID block
2115 * @edid: EDID block to scan
2116 * @t: standard timing params
2118 * Take the standard timing params (in this case width, aspect, and refresh)
2119 * and convert them into a real mode using CVT/GTF/DMT.
2121 static struct drm_display_mode *
2122 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2123 struct std_timing *t)
2125 struct drm_device *dev = connector->dev;
2126 struct drm_display_mode *m, *mode = NULL;
2129 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2130 >> EDID_TIMING_ASPECT_SHIFT;
2131 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2132 >> EDID_TIMING_VFREQ_SHIFT;
2133 int timing_level = standard_timing_level(edid);
2135 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2138 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2139 hsize = t->hsize * 8 + 248;
2140 /* vrefresh_rate = vfreq + 60 */
2141 vrefresh_rate = vfreq + 60;
2142 /* the vdisplay is calculated based on the aspect ratio */
2143 if (aspect_ratio == 0) {
2144 if (edid->revision < 3)
2147 vsize = (hsize * 10) / 16;
2148 } else if (aspect_ratio == 1)
2149 vsize = (hsize * 3) / 4;
2150 else if (aspect_ratio == 2)
2151 vsize = (hsize * 4) / 5;
2153 vsize = (hsize * 9) / 16;
2155 /* HDTV hack, part 1 */
2156 if (vrefresh_rate == 60 &&
2157 ((hsize == 1360 && vsize == 765) ||
2158 (hsize == 1368 && vsize == 769))) {
2164 * If this connector already has a mode for this size and refresh
2165 * rate (because it came from detailed or CVT info), use that
2166 * instead. This way we don't have to guess at interlace or
2169 list_for_each_entry(m, &connector->probed_modes, head)
2170 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2171 drm_mode_vrefresh(m) == vrefresh_rate)
2174 /* HDTV hack, part 2 */
2175 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2176 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2180 mode->hdisplay = 1366;
2181 mode->hsync_start = mode->hsync_start - 1;
2182 mode->hsync_end = mode->hsync_end - 1;
2186 /* check whether it can be found in default mode table */
2187 if (drm_monitor_supports_rb(edid)) {
2188 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2193 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2197 /* okay, generate it */
2198 switch (timing_level) {
2202 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2206 * This is potentially wrong if there's ever a monitor with
2207 * more than one ranges section, each claiming a different
2208 * secondary GTF curve. Please don't do that.
2210 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2213 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2214 drm_mode_destroy(dev, mode);
2215 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2216 vrefresh_rate, 0, 0,
2224 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2232 * EDID is delightfully ambiguous about how interlaced modes are to be
2233 * encoded. Our internal representation is of frame height, but some
2234 * HDTV detailed timings are encoded as field height.
2236 * The format list here is from CEA, in frame size. Technically we
2237 * should be checking refresh rate too. Whatever.
2240 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2241 struct detailed_pixel_timing *pt)
2244 static const struct {
2246 } cea_interlaced[] = {
2256 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2259 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2260 if ((mode->hdisplay == cea_interlaced[i].w) &&
2261 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2262 mode->vdisplay *= 2;
2263 mode->vsync_start *= 2;
2264 mode->vsync_end *= 2;
2270 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2274 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2275 * @dev: DRM device (needed to create new mode)
2277 * @timing: EDID detailed timing info
2278 * @quirks: quirks to apply
2280 * An EDID detailed timing block contains enough info for us to create and
2281 * return a new struct drm_display_mode.
2283 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2285 struct detailed_timing *timing,
2288 struct drm_display_mode *mode;
2289 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2290 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2291 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2292 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2293 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2294 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2295 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2296 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2297 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2299 /* ignore tiny modes */
2300 if (hactive < 64 || vactive < 64)
2303 if (pt->misc & DRM_EDID_PT_STEREO) {
2304 DRM_DEBUG_KMS("stereo mode not supported\n");
2307 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2308 DRM_DEBUG_KMS("composite sync not supported\n");
2311 /* it is incorrect if hsync/vsync width is zero */
2312 if (!hsync_pulse_width || !vsync_pulse_width) {
2313 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2314 "Wrong Hsync/Vsync pulse width\n");
2318 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2319 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2326 mode = drm_mode_create(dev);
2330 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2331 timing->pixel_clock = cpu_to_le16(1088);
2333 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2335 mode->hdisplay = hactive;
2336 mode->hsync_start = mode->hdisplay + hsync_offset;
2337 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2338 mode->htotal = mode->hdisplay + hblank;
2340 mode->vdisplay = vactive;
2341 mode->vsync_start = mode->vdisplay + vsync_offset;
2342 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2343 mode->vtotal = mode->vdisplay + vblank;
2345 /* Some EDIDs have bogus h/vtotal values */
2346 if (mode->hsync_end > mode->htotal)
2347 mode->htotal = mode->hsync_end + 1;
2348 if (mode->vsync_end > mode->vtotal)
2349 mode->vtotal = mode->vsync_end + 1;
2351 drm_mode_do_interlace_quirk(mode, pt);
2353 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2354 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2357 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2358 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2359 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2360 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2363 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2364 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2366 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2367 mode->width_mm *= 10;
2368 mode->height_mm *= 10;
2371 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2372 mode->width_mm = edid->width_cm * 10;
2373 mode->height_mm = edid->height_cm * 10;
2376 mode->type = DRM_MODE_TYPE_DRIVER;
2377 mode->vrefresh = drm_mode_vrefresh(mode);
2378 drm_mode_set_name(mode);
2384 mode_in_hsync_range(const struct drm_display_mode *mode,
2385 struct edid *edid, u8 *t)
2387 int hsync, hmin, hmax;
2390 if (edid->revision >= 4)
2391 hmin += ((t[4] & 0x04) ? 255 : 0);
2393 if (edid->revision >= 4)
2394 hmax += ((t[4] & 0x08) ? 255 : 0);
2395 hsync = drm_mode_hsync(mode);
2397 return (hsync <= hmax && hsync >= hmin);
2401 mode_in_vsync_range(const struct drm_display_mode *mode,
2402 struct edid *edid, u8 *t)
2404 int vsync, vmin, vmax;
2407 if (edid->revision >= 4)
2408 vmin += ((t[4] & 0x01) ? 255 : 0);
2410 if (edid->revision >= 4)
2411 vmax += ((t[4] & 0x02) ? 255 : 0);
2412 vsync = drm_mode_vrefresh(mode);
2414 return (vsync <= vmax && vsync >= vmin);
2418 range_pixel_clock(struct edid *edid, u8 *t)
2421 if (t[9] == 0 || t[9] == 255)
2424 /* 1.4 with CVT support gives us real precision, yay */
2425 if (edid->revision >= 4 && t[10] == 0x04)
2426 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2428 /* 1.3 is pathetic, so fuzz up a bit */
2429 return t[9] * 10000 + 5001;
2433 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2434 struct detailed_timing *timing)
2437 u8 *t = (u8 *)timing;
2439 if (!mode_in_hsync_range(mode, edid, t))
2442 if (!mode_in_vsync_range(mode, edid, t))
2445 if ((max_clock = range_pixel_clock(edid, t)))
2446 if (mode->clock > max_clock)
2449 /* 1.4 max horizontal check */
2450 if (edid->revision >= 4 && t[10] == 0x04)
2451 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2454 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2460 static bool valid_inferred_mode(const struct drm_connector *connector,
2461 const struct drm_display_mode *mode)
2463 const struct drm_display_mode *m;
2466 list_for_each_entry(m, &connector->probed_modes, head) {
2467 if (mode->hdisplay == m->hdisplay &&
2468 mode->vdisplay == m->vdisplay &&
2469 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2470 return false; /* duplicated */
2471 if (mode->hdisplay <= m->hdisplay &&
2472 mode->vdisplay <= m->vdisplay)
2479 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2480 struct detailed_timing *timing)
2483 struct drm_display_mode *newmode;
2484 struct drm_device *dev = connector->dev;
2486 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2487 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2488 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2489 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2491 drm_mode_probed_add(connector, newmode);
2500 /* fix up 1366x768 mode from 1368x768;
2501 * GFT/CVT can't express 1366 width which isn't dividable by 8
2503 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2505 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2506 mode->hdisplay = 1366;
2507 mode->hsync_start--;
2509 drm_mode_set_name(mode);
2514 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2515 struct detailed_timing *timing)
2518 struct drm_display_mode *newmode;
2519 struct drm_device *dev = connector->dev;
2521 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2522 const struct minimode *m = &extra_modes[i];
2523 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2527 drm_mode_fixup_1366x768(newmode);
2528 if (!mode_in_range(newmode, edid, timing) ||
2529 !valid_inferred_mode(connector, newmode)) {
2530 drm_mode_destroy(dev, newmode);
2534 drm_mode_probed_add(connector, newmode);
2542 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2543 struct detailed_timing *timing)
2546 struct drm_display_mode *newmode;
2547 struct drm_device *dev = connector->dev;
2548 bool rb = drm_monitor_supports_rb(edid);
2550 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2551 const struct minimode *m = &extra_modes[i];
2552 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2556 drm_mode_fixup_1366x768(newmode);
2557 if (!mode_in_range(newmode, edid, timing) ||
2558 !valid_inferred_mode(connector, newmode)) {
2559 drm_mode_destroy(dev, newmode);
2563 drm_mode_probed_add(connector, newmode);
2571 do_inferred_modes(struct detailed_timing *timing, void *c)
2573 struct detailed_mode_closure *closure = c;
2574 struct detailed_non_pixel *data = &timing->data.other_data;
2575 struct detailed_data_monitor_range *range = &data->data.range;
2577 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2580 closure->modes += drm_dmt_modes_for_range(closure->connector,
2584 if (!version_greater(closure->edid, 1, 1))
2585 return; /* GTF not defined yet */
2587 switch (range->flags) {
2588 case 0x02: /* secondary gtf, XXX could do more */
2589 case 0x00: /* default gtf */
2590 closure->modes += drm_gtf_modes_for_range(closure->connector,
2594 case 0x04: /* cvt, only in 1.4+ */
2595 if (!version_greater(closure->edid, 1, 3))
2598 closure->modes += drm_cvt_modes_for_range(closure->connector,
2602 case 0x01: /* just the ranges, no formula */
2609 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2611 struct detailed_mode_closure closure = {
2612 .connector = connector,
2616 if (version_greater(edid, 1, 0))
2617 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2620 return closure.modes;
2624 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2626 int i, j, m, modes = 0;
2627 struct drm_display_mode *mode;
2628 u8 *est = ((u8 *)timing) + 6;
2630 for (i = 0; i < 6; i++) {
2631 for (j = 7; j >= 0; j--) {
2632 m = (i * 8) + (7 - j);
2633 if (m >= ARRAY_SIZE(est3_modes))
2635 if (est[i] & (1 << j)) {
2636 mode = drm_mode_find_dmt(connector->dev,
2642 drm_mode_probed_add(connector, mode);
2653 do_established_modes(struct detailed_timing *timing, void *c)
2655 struct detailed_mode_closure *closure = c;
2656 struct detailed_non_pixel *data = &timing->data.other_data;
2658 if (data->type == EDID_DETAIL_EST_TIMINGS)
2659 closure->modes += drm_est3_modes(closure->connector, timing);
2663 * add_established_modes - get est. modes from EDID and add them
2664 * @connector: connector to add mode(s) to
2665 * @edid: EDID block to scan
2667 * Each EDID block contains a bitmap of the supported "established modes" list
2668 * (defined above). Tease them out and add them to the global modes list.
2671 add_established_modes(struct drm_connector *connector, struct edid *edid)
2673 struct drm_device *dev = connector->dev;
2674 unsigned long est_bits = edid->established_timings.t1 |
2675 (edid->established_timings.t2 << 8) |
2676 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2678 struct detailed_mode_closure closure = {
2679 .connector = connector,
2683 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2684 if (est_bits & (1<<i)) {
2685 struct drm_display_mode *newmode;
2686 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2688 drm_mode_probed_add(connector, newmode);
2694 if (version_greater(edid, 1, 0))
2695 drm_for_each_detailed_block((u8 *)edid,
2696 do_established_modes, &closure);
2698 return modes + closure.modes;
2702 do_standard_modes(struct detailed_timing *timing, void *c)
2704 struct detailed_mode_closure *closure = c;
2705 struct detailed_non_pixel *data = &timing->data.other_data;
2706 struct drm_connector *connector = closure->connector;
2707 struct edid *edid = closure->edid;
2709 if (data->type == EDID_DETAIL_STD_MODES) {
2711 for (i = 0; i < 6; i++) {
2712 struct std_timing *std;
2713 struct drm_display_mode *newmode;
2715 std = &data->data.timings[i];
2716 newmode = drm_mode_std(connector, edid, std);
2718 drm_mode_probed_add(connector, newmode);
2726 * add_standard_modes - get std. modes from EDID and add them
2727 * @connector: connector to add mode(s) to
2728 * @edid: EDID block to scan
2730 * Standard modes can be calculated using the appropriate standard (DMT,
2731 * GTF or CVT. Grab them from @edid and add them to the list.
2734 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2737 struct detailed_mode_closure closure = {
2738 .connector = connector,
2742 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2743 struct drm_display_mode *newmode;
2745 newmode = drm_mode_std(connector, edid,
2746 &edid->standard_timings[i]);
2748 drm_mode_probed_add(connector, newmode);
2753 if (version_greater(edid, 1, 0))
2754 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2757 /* XXX should also look for standard codes in VTB blocks */
2759 return modes + closure.modes;
2762 static int drm_cvt_modes(struct drm_connector *connector,
2763 struct detailed_timing *timing)
2765 int i, j, modes = 0;
2766 struct drm_display_mode *newmode;
2767 struct drm_device *dev = connector->dev;
2768 struct cvt_timing *cvt;
2769 const int rates[] = { 60, 85, 75, 60, 50 };
2770 const u8 empty[3] = { 0, 0, 0 };
2772 for (i = 0; i < 4; i++) {
2773 int uninitialized_var(width), height;
2774 cvt = &(timing->data.other_data.data.cvt[i]);
2776 if (!memcmp(cvt->code, empty, 3))
2779 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2780 switch (cvt->code[1] & 0x0c) {
2782 width = height * 4 / 3;
2785 width = height * 16 / 9;
2788 width = height * 16 / 10;
2791 width = height * 15 / 9;
2795 for (j = 1; j < 5; j++) {
2796 if (cvt->code[2] & (1 << j)) {
2797 newmode = drm_cvt_mode(dev, width, height,
2801 drm_mode_probed_add(connector, newmode);
2812 do_cvt_mode(struct detailed_timing *timing, void *c)
2814 struct detailed_mode_closure *closure = c;
2815 struct detailed_non_pixel *data = &timing->data.other_data;
2817 if (data->type == EDID_DETAIL_CVT_3BYTE)
2818 closure->modes += drm_cvt_modes(closure->connector, timing);
2822 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2824 struct detailed_mode_closure closure = {
2825 .connector = connector,
2829 if (version_greater(edid, 1, 2))
2830 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2832 /* XXX should also look for CVT codes in VTB blocks */
2834 return closure.modes;
2837 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2840 do_detailed_mode(struct detailed_timing *timing, void *c)
2842 struct detailed_mode_closure *closure = c;
2843 struct drm_display_mode *newmode;
2845 if (timing->pixel_clock) {
2846 newmode = drm_mode_detailed(closure->connector->dev,
2847 closure->edid, timing,
2852 if (closure->preferred)
2853 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2856 * Detailed modes are limited to 10kHz pixel clock resolution,
2857 * so fix up anything that looks like CEA/HDMI mode, but the clock
2858 * is just slightly off.
2860 fixup_detailed_cea_mode_clock(newmode);
2862 drm_mode_probed_add(closure->connector, newmode);
2864 closure->preferred = false;
2869 * add_detailed_modes - Add modes from detailed timings
2870 * @connector: attached connector
2871 * @edid: EDID block to scan
2872 * @quirks: quirks to apply
2875 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2878 struct detailed_mode_closure closure = {
2879 .connector = connector,
2885 if (closure.preferred && !version_greater(edid, 1, 3))
2887 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2889 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2891 return closure.modes;
2894 #define AUDIO_BLOCK 0x01
2895 #define VIDEO_BLOCK 0x02
2896 #define VENDOR_BLOCK 0x03
2897 #define SPEAKER_BLOCK 0x04
2898 #define HDR_STATIC_METADATA_BLOCK 0x6
2899 #define USE_EXTENDED_TAG 0x07
2900 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
2901 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
2902 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
2903 #define EDID_BASIC_AUDIO (1 << 6)
2904 #define EDID_CEA_YCRCB444 (1 << 5)
2905 #define EDID_CEA_YCRCB422 (1 << 4)
2906 #define EDID_CEA_VCDB_QS (1 << 6)
2909 * Search EDID for CEA extension block.
2911 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
2913 u8 *edid_ext = NULL;
2916 /* No EDID or EDID extensions */
2917 if (edid == NULL || edid->extensions == 0)
2920 /* Find CEA extension */
2921 for (i = 0; i < edid->extensions; i++) {
2922 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2923 if (edid_ext[0] == ext_id)
2927 if (i == edid->extensions)
2934 static u8 *drm_find_displayid_extension(const struct edid *edid)
2936 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2939 static u8 *drm_find_cea_extension(const struct edid *edid)
2943 int length = EDID_LENGTH;
2944 struct displayid_block *block;
2948 /* Look for a top level CEA extension block */
2949 cea = drm_find_edid_extension(edid, CEA_EXT);
2953 /* CEA blocks can also be found embedded in a DisplayID block */
2954 displayid = drm_find_displayid_extension(edid);
2958 ret = validate_displayid(displayid, length, idx);
2962 idx += sizeof(struct displayid_hdr);
2963 for_each_displayid_db(displayid, block, idx, length) {
2964 if (block->tag == DATA_BLOCK_CTA) {
2974 * Calculate the alternate clock for the CEA mode
2975 * (60Hz vs. 59.94Hz etc.)
2978 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2980 unsigned int clock = cea_mode->clock;
2982 if (cea_mode->vrefresh % 6 != 0)
2986 * edid_cea_modes contains the 59.94Hz
2987 * variant for 240 and 480 line modes,
2988 * and the 60Hz variant otherwise.
2990 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2991 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2993 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2999 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3002 * For certain VICs the spec allows the vertical
3003 * front porch to vary by one or two lines.
3005 * cea_modes[] stores the variant with the shortest
3006 * vertical front porch. We can adjust the mode to
3007 * get the other variants by simply increasing the
3008 * vertical front porch length.
3010 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
3011 edid_cea_modes[9].vtotal != 262 ||
3012 edid_cea_modes[12].vtotal != 262 ||
3013 edid_cea_modes[13].vtotal != 262 ||
3014 edid_cea_modes[23].vtotal != 312 ||
3015 edid_cea_modes[24].vtotal != 312 ||
3016 edid_cea_modes[27].vtotal != 312 ||
3017 edid_cea_modes[28].vtotal != 312);
3019 if (((vic == 8 || vic == 9 ||
3020 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3021 ((vic == 23 || vic == 24 ||
3022 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3023 mode->vsync_start++;
3033 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3034 unsigned int clock_tolerance)
3036 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3039 if (!to_match->clock)
3042 if (to_match->picture_aspect_ratio)
3043 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3045 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
3046 struct drm_display_mode cea_mode = edid_cea_modes[vic];
3047 unsigned int clock1, clock2;
3049 /* Check both 60Hz and 59.94Hz */
3050 clock1 = cea_mode.clock;
3051 clock2 = cea_mode_alternate_clock(&cea_mode);
3053 if (abs(to_match->clock - clock1) > clock_tolerance &&
3054 abs(to_match->clock - clock2) > clock_tolerance)
3058 if (drm_mode_match(to_match, &cea_mode, match_flags))
3060 } while (cea_mode_alternate_timings(vic, &cea_mode));
3067 * drm_match_cea_mode - look for a CEA mode matching given mode
3068 * @to_match: display mode
3070 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
3073 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
3075 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3078 if (!to_match->clock)
3081 if (to_match->picture_aspect_ratio)
3082 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3084 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
3085 struct drm_display_mode cea_mode = edid_cea_modes[vic];
3086 unsigned int clock1, clock2;
3088 /* Check both 60Hz and 59.94Hz */
3089 clock1 = cea_mode.clock;
3090 clock2 = cea_mode_alternate_clock(&cea_mode);
3092 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3093 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3097 if (drm_mode_match(to_match, &cea_mode, match_flags))
3099 } while (cea_mode_alternate_timings(vic, &cea_mode));
3104 EXPORT_SYMBOL(drm_match_cea_mode);
3106 static bool drm_valid_cea_vic(u8 vic)
3108 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
3112 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
3113 * the input VIC from the CEA mode list
3114 * @video_code: ID given to each of the CEA modes
3116 * Returns picture aspect ratio
3118 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3120 return edid_cea_modes[video_code].picture_aspect_ratio;
3122 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
3125 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3128 * It's almost like cea_mode_alternate_clock(), we just need to add an
3129 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
3133 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3135 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
3136 return hdmi_mode->clock;
3138 return cea_mode_alternate_clock(hdmi_mode);
3141 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3142 unsigned int clock_tolerance)
3144 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3147 if (!to_match->clock)
3150 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3151 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3152 unsigned int clock1, clock2;
3154 /* Make sure to also match alternate clocks */
3155 clock1 = hdmi_mode->clock;
3156 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3158 if (abs(to_match->clock - clock1) > clock_tolerance &&
3159 abs(to_match->clock - clock2) > clock_tolerance)
3162 if (drm_mode_match(to_match, hdmi_mode, match_flags))
3170 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3171 * @to_match: display mode
3173 * An HDMI mode is one defined in the HDMI vendor specific block.
3175 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3177 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3179 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3182 if (!to_match->clock)
3185 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3186 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3187 unsigned int clock1, clock2;
3189 /* Make sure to also match alternate clocks */
3190 clock1 = hdmi_mode->clock;
3191 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3193 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3194 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3195 drm_mode_match(to_match, hdmi_mode, match_flags))
3201 static bool drm_valid_hdmi_vic(u8 vic)
3203 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3207 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3209 struct drm_device *dev = connector->dev;
3210 struct drm_display_mode *mode, *tmp;
3214 /* Don't add CEA modes if the CEA extension block is missing */
3215 if (!drm_find_cea_extension(edid))
3219 * Go through all probed modes and create a new mode
3220 * with the alternate clock for certain CEA modes.
3222 list_for_each_entry(mode, &connector->probed_modes, head) {
3223 const struct drm_display_mode *cea_mode = NULL;
3224 struct drm_display_mode *newmode;
3225 u8 vic = drm_match_cea_mode(mode);
3226 unsigned int clock1, clock2;
3228 if (drm_valid_cea_vic(vic)) {
3229 cea_mode = &edid_cea_modes[vic];
3230 clock2 = cea_mode_alternate_clock(cea_mode);
3232 vic = drm_match_hdmi_mode(mode);
3233 if (drm_valid_hdmi_vic(vic)) {
3234 cea_mode = &edid_4k_modes[vic];
3235 clock2 = hdmi_mode_alternate_clock(cea_mode);
3242 clock1 = cea_mode->clock;
3244 if (clock1 == clock2)
3247 if (mode->clock != clock1 && mode->clock != clock2)
3250 newmode = drm_mode_duplicate(dev, cea_mode);
3254 /* Carry over the stereo flags */
3255 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3258 * The current mode could be either variant. Make
3259 * sure to pick the "other" clock for the new mode.
3261 if (mode->clock != clock1)
3262 newmode->clock = clock1;
3264 newmode->clock = clock2;
3266 list_add_tail(&newmode->head, &list);
3269 list_for_each_entry_safe(mode, tmp, &list, head) {
3270 list_del(&mode->head);
3271 drm_mode_probed_add(connector, mode);
3278 static u8 svd_to_vic(u8 svd)
3280 /* 0-6 bit vic, 7th bit native mode indicator */
3281 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3287 static struct drm_display_mode *
3288 drm_display_mode_from_vic_index(struct drm_connector *connector,
3289 const u8 *video_db, u8 video_len,
3292 struct drm_device *dev = connector->dev;
3293 struct drm_display_mode *newmode;
3296 if (video_db == NULL || video_index >= video_len)
3299 /* CEA modes are numbered 1..127 */
3300 vic = svd_to_vic(video_db[video_index]);
3301 if (!drm_valid_cea_vic(vic))
3304 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3308 newmode->vrefresh = 0;
3314 * do_y420vdb_modes - Parse YCBCR 420 only modes
3315 * @connector: connector corresponding to the HDMI sink
3316 * @svds: start of the data block of CEA YCBCR 420 VDB
3317 * @len: length of the CEA YCBCR 420 VDB
3319 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3320 * which contains modes which can be supported in YCBCR 420
3321 * output format only.
3323 static int do_y420vdb_modes(struct drm_connector *connector,
3324 const u8 *svds, u8 svds_len)
3327 struct drm_device *dev = connector->dev;
3328 struct drm_display_info *info = &connector->display_info;
3329 struct drm_hdmi_info *hdmi = &info->hdmi;
3331 for (i = 0; i < svds_len; i++) {
3332 u8 vic = svd_to_vic(svds[i]);
3333 struct drm_display_mode *newmode;
3335 if (!drm_valid_cea_vic(vic))
3338 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3341 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3342 drm_mode_probed_add(connector, newmode);
3347 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3352 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3353 * @connector: connector corresponding to the HDMI sink
3354 * @vic: CEA vic for the video mode to be added in the map
3356 * Makes an entry for a videomode in the YCBCR 420 bitmap
3359 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3361 u8 vic = svd_to_vic(svd);
3362 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3364 if (!drm_valid_cea_vic(vic))
3367 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3371 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3374 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3376 for (i = 0; i < len; i++) {
3377 struct drm_display_mode *mode;
3378 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3381 * YCBCR420 capability block contains a bitmap which
3382 * gives the index of CEA modes from CEA VDB, which
3383 * can support YCBCR 420 sampling output also (apart
3384 * from RGB/YCBCR444 etc).
3385 * For example, if the bit 0 in bitmap is set,
3386 * first mode in VDB can support YCBCR420 output too.
3387 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3389 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3390 drm_add_cmdb_modes(connector, db[i]);
3392 drm_mode_probed_add(connector, mode);
3400 struct stereo_mandatory_mode {
3401 int width, height, vrefresh;
3405 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3406 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3407 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3409 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3411 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3412 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3413 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3414 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3415 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3419 stereo_match_mandatory(const struct drm_display_mode *mode,
3420 const struct stereo_mandatory_mode *stereo_mode)
3422 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3424 return mode->hdisplay == stereo_mode->width &&
3425 mode->vdisplay == stereo_mode->height &&
3426 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3427 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3430 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3432 struct drm_device *dev = connector->dev;
3433 const struct drm_display_mode *mode;
3434 struct list_head stereo_modes;
3437 INIT_LIST_HEAD(&stereo_modes);
3439 list_for_each_entry(mode, &connector->probed_modes, head) {
3440 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3441 const struct stereo_mandatory_mode *mandatory;
3442 struct drm_display_mode *new_mode;
3444 if (!stereo_match_mandatory(mode,
3445 &stereo_mandatory_modes[i]))
3448 mandatory = &stereo_mandatory_modes[i];
3449 new_mode = drm_mode_duplicate(dev, mode);
3453 new_mode->flags |= mandatory->flags;
3454 list_add_tail(&new_mode->head, &stereo_modes);
3459 list_splice_tail(&stereo_modes, &connector->probed_modes);
3464 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3466 struct drm_device *dev = connector->dev;
3467 struct drm_display_mode *newmode;
3469 if (!drm_valid_hdmi_vic(vic)) {
3470 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3474 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3478 drm_mode_probed_add(connector, newmode);
3483 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3484 const u8 *video_db, u8 video_len, u8 video_index)
3486 struct drm_display_mode *newmode;
3489 if (structure & (1 << 0)) {
3490 newmode = drm_display_mode_from_vic_index(connector, video_db,
3494 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3495 drm_mode_probed_add(connector, newmode);
3499 if (structure & (1 << 6)) {
3500 newmode = drm_display_mode_from_vic_index(connector, video_db,
3504 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3505 drm_mode_probed_add(connector, newmode);
3509 if (structure & (1 << 8)) {
3510 newmode = drm_display_mode_from_vic_index(connector, video_db,
3514 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3515 drm_mode_probed_add(connector, newmode);
3524 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3525 * @connector: connector corresponding to the HDMI sink
3526 * @db: start of the CEA vendor specific block
3527 * @len: length of the CEA block payload, ie. one can access up to db[len]
3529 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3530 * also adds the stereo 3d modes when applicable.
3533 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3534 const u8 *video_db, u8 video_len)
3536 struct drm_display_info *info = &connector->display_info;
3537 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3538 u8 vic_len, hdmi_3d_len = 0;
3545 /* no HDMI_Video_Present */
3546 if (!(db[8] & (1 << 5)))
3549 /* Latency_Fields_Present */
3550 if (db[8] & (1 << 7))
3553 /* I_Latency_Fields_Present */
3554 if (db[8] & (1 << 6))
3557 /* the declared length is not long enough for the 2 first bytes
3558 * of additional video format capabilities */
3559 if (len < (8 + offset + 2))
3564 if (db[8 + offset] & (1 << 7)) {
3565 modes += add_hdmi_mandatory_stereo_modes(connector);
3567 /* 3D_Multi_present */
3568 multi_present = (db[8 + offset] & 0x60) >> 5;
3572 vic_len = db[8 + offset] >> 5;
3573 hdmi_3d_len = db[8 + offset] & 0x1f;
3575 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3578 vic = db[9 + offset + i];
3579 modes += add_hdmi_mode(connector, vic);
3581 offset += 1 + vic_len;
3583 if (multi_present == 1)
3585 else if (multi_present == 2)
3590 if (len < (8 + offset + hdmi_3d_len - 1))
3593 if (hdmi_3d_len < multi_len)
3596 if (multi_present == 1 || multi_present == 2) {
3597 /* 3D_Structure_ALL */
3598 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3600 /* check if 3D_MASK is present */
3601 if (multi_present == 2)
3602 mask = (db[10 + offset] << 8) | db[11 + offset];
3606 for (i = 0; i < 16; i++) {
3607 if (mask & (1 << i))
3608 modes += add_3d_struct_modes(connector,
3615 offset += multi_len;
3617 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3619 struct drm_display_mode *newmode = NULL;
3620 unsigned int newflag = 0;
3621 bool detail_present;
3623 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3625 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3628 /* 2D_VIC_order_X */
3629 vic_index = db[8 + offset + i] >> 4;
3631 /* 3D_Structure_X */
3632 switch (db[8 + offset + i] & 0x0f) {
3634 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3637 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3641 if ((db[9 + offset + i] >> 4) == 1)
3642 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3647 newmode = drm_display_mode_from_vic_index(connector,
3653 newmode->flags |= newflag;
3654 drm_mode_probed_add(connector, newmode);
3665 info->has_hdmi_infoframe = true;
3670 cea_db_payload_len(const u8 *db)
3672 return db[0] & 0x1f;
3676 cea_db_extended_tag(const u8 *db)
3682 cea_db_tag(const u8 *db)
3688 cea_revision(const u8 *cea)
3694 cea_db_offsets(const u8 *cea, int *start, int *end)
3696 /* DisplayID CTA extension blocks and top-level CEA EDID
3697 * block header definitions differ in the following bytes:
3698 * 1) Byte 2 of the header specifies length differently,
3699 * 2) Byte 3 is only present in the CEA top level block.
3701 * The different definitions for byte 2 follow.
3703 * DisplayID CTA extension block defines byte 2 as:
3704 * Number of payload bytes
3706 * CEA EDID block defines byte 2 as:
3707 * Byte number (decimal) within this block where the 18-byte
3708 * DTDs begin. If no non-DTD data is present in this extension
3709 * block, the value should be set to 04h (the byte after next).
3710 * If set to 00h, there are no DTDs present in this block and
3713 if (cea[0] == DATA_BLOCK_CTA) {
3715 *end = *start + cea[2];
3716 } else if (cea[0] == CEA_EXT) {
3717 /* Data block offset in CEA extension block */
3722 if (*end < 4 || *end > 127)
3731 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3735 if (cea_db_tag(db) != VENDOR_BLOCK)
3738 if (cea_db_payload_len(db) < 5)
3741 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3743 return hdmi_id == HDMI_IEEE_OUI;
3746 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3750 if (cea_db_tag(db) != VENDOR_BLOCK)
3753 if (cea_db_payload_len(db) < 7)
3756 oui = db[3] << 16 | db[2] << 8 | db[1];
3758 return oui == HDMI_FORUM_IEEE_OUI;
3761 static bool cea_db_is_vcdb(const u8 *db)
3763 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3766 if (cea_db_payload_len(db) != 2)
3769 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
3775 static bool cea_db_is_y420cmdb(const u8 *db)
3777 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3780 if (!cea_db_payload_len(db))
3783 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3789 static bool cea_db_is_y420vdb(const u8 *db)
3791 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3794 if (!cea_db_payload_len(db))
3797 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3803 #define for_each_cea_db(cea, i, start, end) \
3804 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3806 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3809 struct drm_display_info *info = &connector->display_info;
3810 struct drm_hdmi_info *hdmi = &info->hdmi;
3811 u8 map_len = cea_db_payload_len(db) - 1;
3816 /* All CEA modes support ycbcr420 sampling also.*/
3817 hdmi->y420_cmdb_map = U64_MAX;
3818 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3823 * This map indicates which of the existing CEA block modes
3824 * from VDB can support YCBCR420 output too. So if bit=0 is
3825 * set, first mode from VDB can support YCBCR420 output too.
3826 * We will parse and keep this map, before parsing VDB itself
3827 * to avoid going through the same block again and again.
3829 * Spec is not clear about max possible size of this block.
3830 * Clamping max bitmap block size at 8 bytes. Every byte can
3831 * address 8 CEA modes, in this way this map can address
3832 * 8*8 = first 64 SVDs.
3834 if (WARN_ON_ONCE(map_len > 8))
3837 for (count = 0; count < map_len; count++)
3838 map |= (u64)db[2 + count] << (8 * count);
3841 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3843 hdmi->y420_cmdb_map = map;
3847 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3849 const u8 *cea = drm_find_cea_extension(edid);
3850 const u8 *db, *hdmi = NULL, *video = NULL;
3851 u8 dbl, hdmi_len, video_len = 0;
3854 if (cea && cea_revision(cea) >= 3) {
3857 if (cea_db_offsets(cea, &start, &end))
3860 for_each_cea_db(cea, i, start, end) {
3862 dbl = cea_db_payload_len(db);
3864 if (cea_db_tag(db) == VIDEO_BLOCK) {
3867 modes += do_cea_modes(connector, video, dbl);
3868 } else if (cea_db_is_hdmi_vsdb(db)) {
3871 } else if (cea_db_is_y420vdb(db)) {
3872 const u8 *vdb420 = &db[2];
3874 /* Add 4:2:0(only) modes present in EDID */
3875 modes += do_y420vdb_modes(connector,
3883 * We parse the HDMI VSDB after having added the cea modes as we will
3884 * be patching their flags when the sink supports stereo 3D.
3887 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3893 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3895 const struct drm_display_mode *cea_mode;
3896 int clock1, clock2, clock;
3901 * allow 5kHz clock difference either way to account for
3902 * the 10kHz clock resolution limit of detailed timings.
3904 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3905 if (drm_valid_cea_vic(vic)) {
3907 cea_mode = &edid_cea_modes[vic];
3908 clock1 = cea_mode->clock;
3909 clock2 = cea_mode_alternate_clock(cea_mode);
3911 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3912 if (drm_valid_hdmi_vic(vic)) {
3914 cea_mode = &edid_4k_modes[vic];
3915 clock1 = cea_mode->clock;
3916 clock2 = hdmi_mode_alternate_clock(cea_mode);
3922 /* pick whichever is closest */
3923 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3928 if (mode->clock == clock)
3931 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3932 type, vic, mode->clock, clock);
3933 mode->clock = clock;
3936 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
3938 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3941 if (db[1] != HDR_STATIC_METADATA_BLOCK)
3944 if (cea_db_payload_len(db) < 3)
3950 static uint8_t eotf_supported(const u8 *edid_ext)
3952 return edid_ext[2] &
3953 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
3954 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
3955 BIT(HDMI_EOTF_SMPTE_ST2084) |
3956 BIT(HDMI_EOTF_BT_2100_HLG));
3959 static uint8_t hdr_metadata_type(const u8 *edid_ext)
3961 return edid_ext[3] &
3962 BIT(HDMI_STATIC_METADATA_TYPE1);
3966 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
3970 len = cea_db_payload_len(db);
3972 connector->hdr_sink_metadata.hdmi_type1.eotf =
3974 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
3975 hdr_metadata_type(db);
3978 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
3980 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
3982 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
3986 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3988 u8 len = cea_db_payload_len(db);
3990 if (len >= 6 && (db[6] & (1 << 7)))
3991 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
3993 connector->latency_present[0] = db[8] >> 7;
3994 connector->latency_present[1] = (db[8] >> 6) & 1;
3997 connector->video_latency[0] = db[9];
3999 connector->audio_latency[0] = db[10];
4001 connector->video_latency[1] = db[11];
4003 connector->audio_latency[1] = db[12];
4005 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4006 "video latency %d %d, "
4007 "audio latency %d %d\n",
4008 connector->latency_present[0],
4009 connector->latency_present[1],
4010 connector->video_latency[0],
4011 connector->video_latency[1],
4012 connector->audio_latency[0],
4013 connector->audio_latency[1]);
4017 monitor_name(struct detailed_timing *t, void *data)
4019 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
4020 *(u8 **)data = t->data.other_data.data.str.str;
4023 static int get_monitor_name(struct edid *edid, char name[13])
4025 char *edid_name = NULL;
4031 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
4032 for (mnl = 0; edid_name && mnl < 13; mnl++) {
4033 if (edid_name[mnl] == 0x0a)
4036 name[mnl] = edid_name[mnl];
4043 * drm_edid_get_monitor_name - fetch the monitor name from the edid
4044 * @edid: monitor EDID information
4045 * @name: pointer to a character array to hold the name of the monitor
4046 * @bufsize: The size of the name buffer (should be at least 14 chars.)
4049 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
4057 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4058 memcpy(name, buf, name_length);
4059 name[name_length] = '\0';
4061 EXPORT_SYMBOL(drm_edid_get_monitor_name);
4063 static void clear_eld(struct drm_connector *connector)
4065 memset(connector->eld, 0, sizeof(connector->eld));
4067 connector->latency_present[0] = false;
4068 connector->latency_present[1] = false;
4069 connector->video_latency[0] = 0;
4070 connector->audio_latency[0] = 0;
4071 connector->video_latency[1] = 0;
4072 connector->audio_latency[1] = 0;
4076 * drm_edid_to_eld - build ELD from EDID
4077 * @connector: connector corresponding to the HDMI/DP sink
4078 * @edid: EDID to parse
4080 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
4081 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
4083 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
4085 uint8_t *eld = connector->eld;
4088 int total_sad_count = 0;
4092 clear_eld(connector);
4097 cea = drm_find_cea_extension(edid);
4099 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4103 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4104 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
4106 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4107 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
4109 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
4111 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4112 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4113 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4114 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
4116 if (cea_revision(cea) >= 3) {
4119 if (cea_db_offsets(cea, &start, &end)) {
4124 for_each_cea_db(cea, i, start, end) {
4126 dbl = cea_db_payload_len(db);
4128 switch (cea_db_tag(db)) {
4132 /* Audio Data Block, contains SADs */
4133 sad_count = min(dbl / 3, 15 - total_sad_count);
4135 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
4136 &db[1], sad_count * 3);
4137 total_sad_count += sad_count;
4140 /* Speaker Allocation Data Block */
4142 eld[DRM_ELD_SPEAKER] = db[1];
4145 /* HDMI Vendor-Specific Data Block */
4146 if (cea_db_is_hdmi_vsdb(db))
4147 drm_parse_hdmi_vsdb_audio(connector, db);
4154 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
4156 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4157 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4158 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4160 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
4162 eld[DRM_ELD_BASELINE_ELD_LEN] =
4163 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4165 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
4166 drm_eld_size(eld), total_sad_count);
4170 * drm_edid_to_sad - extracts SADs from EDID
4171 * @edid: EDID to parse
4172 * @sads: pointer that will be set to the extracted SADs
4174 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
4176 * Note: The returned pointer needs to be freed using kfree().
4178 * Return: The number of found SADs or negative number on error.
4180 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4183 int i, start, end, dbl;
4186 cea = drm_find_cea_extension(edid);
4188 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4192 if (cea_revision(cea) < 3) {
4193 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4197 if (cea_db_offsets(cea, &start, &end)) {
4198 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4202 for_each_cea_db(cea, i, start, end) {
4205 if (cea_db_tag(db) == AUDIO_BLOCK) {
4207 dbl = cea_db_payload_len(db);
4209 count = dbl / 3; /* SAD is 3B */
4210 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4213 for (j = 0; j < count; j++) {
4214 u8 *sad = &db[1 + j * 3];
4216 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4217 (*sads)[j].channels = sad[0] & 0x7;
4218 (*sads)[j].freq = sad[1] & 0x7F;
4219 (*sads)[j].byte2 = sad[2];
4227 EXPORT_SYMBOL(drm_edid_to_sad);
4230 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4231 * @edid: EDID to parse
4232 * @sadb: pointer to the speaker block
4234 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4236 * Note: The returned pointer needs to be freed using kfree().
4238 * Return: The number of found Speaker Allocation Blocks or negative number on
4241 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4244 int i, start, end, dbl;
4247 cea = drm_find_cea_extension(edid);
4249 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4253 if (cea_revision(cea) < 3) {
4254 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4258 if (cea_db_offsets(cea, &start, &end)) {
4259 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4263 for_each_cea_db(cea, i, start, end) {
4264 const u8 *db = &cea[i];
4266 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4267 dbl = cea_db_payload_len(db);
4269 /* Speaker Allocation Data Block */
4271 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4282 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4285 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4286 * @connector: connector associated with the HDMI/DP sink
4287 * @mode: the display mode
4289 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4290 * the sink doesn't support audio or video.
4292 int drm_av_sync_delay(struct drm_connector *connector,
4293 const struct drm_display_mode *mode)
4295 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4298 if (!connector->latency_present[0])
4300 if (!connector->latency_present[1])
4303 a = connector->audio_latency[i];
4304 v = connector->video_latency[i];
4307 * HDMI/DP sink doesn't support audio or video?
4309 if (a == 255 || v == 255)
4313 * Convert raw EDID values to millisecond.
4314 * Treat unknown latency as 0ms.
4317 a = min(2 * (a - 1), 500);
4319 v = min(2 * (v - 1), 500);
4321 return max(v - a, 0);
4323 EXPORT_SYMBOL(drm_av_sync_delay);
4326 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4327 * @edid: monitor EDID information
4329 * Parse the CEA extension according to CEA-861-B.
4331 * Return: True if the monitor is HDMI, false if not or unknown.
4333 bool drm_detect_hdmi_monitor(struct edid *edid)
4337 int start_offset, end_offset;
4339 edid_ext = drm_find_cea_extension(edid);
4343 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4347 * Because HDMI identifier is in Vendor Specific Block,
4348 * search it from all data blocks of CEA extension.
4350 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4351 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4357 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4360 * drm_detect_monitor_audio - check monitor audio capability
4361 * @edid: EDID block to scan
4363 * Monitor should have CEA extension block.
4364 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4365 * audio' only. If there is any audio extension block and supported
4366 * audio format, assume at least 'basic audio' support, even if 'basic
4367 * audio' is not defined in EDID.
4369 * Return: True if the monitor supports audio, false otherwise.
4371 bool drm_detect_monitor_audio(struct edid *edid)
4375 bool has_audio = false;
4376 int start_offset, end_offset;
4378 edid_ext = drm_find_cea_extension(edid);
4382 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4385 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4389 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4392 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4393 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4395 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4396 DRM_DEBUG_KMS("CEA audio format %d\n",
4397 (edid_ext[i + j] >> 3) & 0xf);
4404 EXPORT_SYMBOL(drm_detect_monitor_audio);
4408 * drm_default_rgb_quant_range - default RGB quantization range
4409 * @mode: display mode
4411 * Determine the default RGB quantization range for the mode,
4412 * as specified in CEA-861.
4414 * Return: The default RGB quantization range for the mode
4416 enum hdmi_quantization_range
4417 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4419 /* All CEA modes other than VIC 1 use limited quantization range. */
4420 return drm_match_cea_mode(mode) > 1 ?
4421 HDMI_QUANTIZATION_RANGE_LIMITED :
4422 HDMI_QUANTIZATION_RANGE_FULL;
4424 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4426 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4428 struct drm_display_info *info = &connector->display_info;
4430 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4432 if (db[2] & EDID_CEA_VCDB_QS)
4433 info->rgb_quant_range_selectable = true;
4436 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4440 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4442 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4443 hdmi->y420_dc_modes = dc_mask;
4446 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4449 struct drm_display_info *display = &connector->display_info;
4450 struct drm_hdmi_info *hdmi = &display->hdmi;
4452 display->has_hdmi_infoframe = true;
4454 if (hf_vsdb[6] & 0x80) {
4455 hdmi->scdc.supported = true;
4456 if (hf_vsdb[6] & 0x40)
4457 hdmi->scdc.read_request = true;
4461 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4462 * And as per the spec, three factors confirm this:
4463 * * Availability of a HF-VSDB block in EDID (check)
4464 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4465 * * SCDC support available (let's check)
4466 * Lets check it out.
4470 /* max clock is 5000 KHz times block value */
4471 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4472 struct drm_scdc *scdc = &hdmi->scdc;
4474 if (max_tmds_clock > 340000) {
4475 display->max_tmds_clock = max_tmds_clock;
4476 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4477 display->max_tmds_clock);
4480 if (scdc->supported) {
4481 scdc->scrambling.supported = true;
4483 /* Few sinks support scrambling for cloks < 340M */
4484 if ((hf_vsdb[6] & 0x8))
4485 scdc->scrambling.low_rates = true;
4489 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4492 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4495 struct drm_display_info *info = &connector->display_info;
4496 unsigned int dc_bpc = 0;
4498 /* HDMI supports at least 8 bpc */
4501 if (cea_db_payload_len(hdmi) < 6)
4504 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4506 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4507 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4511 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4513 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4514 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4518 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4520 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4521 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4526 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4531 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4532 connector->name, dc_bpc);
4536 * Deep color support mandates RGB444 support for all video
4537 * modes and forbids YCRCB422 support for all video modes per
4540 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4542 /* YCRCB444 is optional according to spec. */
4543 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4544 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4545 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4550 * Spec says that if any deep color mode is supported at all,
4551 * then deep color 36 bit must be supported.
4553 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4554 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4560 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4562 struct drm_display_info *info = &connector->display_info;
4563 u8 len = cea_db_payload_len(db);
4566 info->dvi_dual = db[6] & 1;
4568 info->max_tmds_clock = db[7] * 5000;
4570 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4571 "max TMDS clock %d kHz\n",
4573 info->max_tmds_clock);
4575 drm_parse_hdmi_deep_color_info(connector, db);
4578 static void drm_parse_cea_ext(struct drm_connector *connector,
4579 const struct edid *edid)
4581 struct drm_display_info *info = &connector->display_info;
4585 edid_ext = drm_find_cea_extension(edid);
4589 info->cea_rev = edid_ext[1];
4591 /* The existence of a CEA block should imply RGB support */
4592 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4593 if (edid_ext[3] & EDID_CEA_YCRCB444)
4594 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4595 if (edid_ext[3] & EDID_CEA_YCRCB422)
4596 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4598 if (cea_db_offsets(edid_ext, &start, &end))
4601 for_each_cea_db(edid_ext, i, start, end) {
4602 const u8 *db = &edid_ext[i];
4604 if (cea_db_is_hdmi_vsdb(db))
4605 drm_parse_hdmi_vsdb_video(connector, db);
4606 if (cea_db_is_hdmi_forum_vsdb(db))
4607 drm_parse_hdmi_forum_vsdb(connector, db);
4608 if (cea_db_is_y420cmdb(db))
4609 drm_parse_y420cmdb_bitmap(connector, db);
4610 if (cea_db_is_vcdb(db))
4611 drm_parse_vcdb(connector, db);
4612 if (cea_db_is_hdmi_hdr_metadata_block(db))
4613 drm_parse_hdr_metadata_block(connector, db);
4617 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4618 * all of the values which would have been set from EDID
4621 drm_reset_display_info(struct drm_connector *connector)
4623 struct drm_display_info *info = &connector->display_info;
4626 info->height_mm = 0;
4629 info->color_formats = 0;
4631 info->max_tmds_clock = 0;
4632 info->dvi_dual = false;
4633 info->has_hdmi_infoframe = false;
4634 info->rgb_quant_range_selectable = false;
4635 memset(&info->hdmi, 0, sizeof(info->hdmi));
4637 info->non_desktop = 0;
4640 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
4642 struct drm_display_info *info = &connector->display_info;
4644 u32 quirks = edid_get_quirks(edid);
4646 drm_reset_display_info(connector);
4648 info->width_mm = edid->width_cm * 10;
4649 info->height_mm = edid->height_cm * 10;
4651 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4653 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4655 if (edid->revision < 3)
4658 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4661 drm_parse_cea_ext(connector, edid);
4664 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4666 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4667 * tells us to assume 8 bpc color depth if the EDID doesn't have
4668 * extensions which tell otherwise.
4670 if (info->bpc == 0 && edid->revision == 3 &&
4671 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
4673 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4674 connector->name, info->bpc);
4677 /* Only defined for 1.4 with digital displays */
4678 if (edid->revision < 4)
4681 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4682 case DRM_EDID_DIGITAL_DEPTH_6:
4685 case DRM_EDID_DIGITAL_DEPTH_8:
4688 case DRM_EDID_DIGITAL_DEPTH_10:
4691 case DRM_EDID_DIGITAL_DEPTH_12:
4694 case DRM_EDID_DIGITAL_DEPTH_14:
4697 case DRM_EDID_DIGITAL_DEPTH_16:
4700 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4706 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4707 connector->name, info->bpc);
4709 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4710 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4711 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4712 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4713 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4717 static int validate_displayid(u8 *displayid, int length, int idx)
4721 struct displayid_hdr *base;
4723 base = (struct displayid_hdr *)&displayid[idx];
4725 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4726 base->rev, base->bytes, base->prod_id, base->ext_count);
4728 if (base->bytes + 5 > length - idx)
4730 for (i = idx; i <= base->bytes + 5; i++) {
4731 csum += displayid[i];
4734 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
4740 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4741 struct displayid_detailed_timings_1 *timings)
4743 struct drm_display_mode *mode;
4744 unsigned pixel_clock = (timings->pixel_clock[0] |
4745 (timings->pixel_clock[1] << 8) |
4746 (timings->pixel_clock[2] << 16));
4747 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4748 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4749 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4750 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4751 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4752 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4753 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4754 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4755 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4756 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4757 mode = drm_mode_create(dev);
4761 mode->clock = pixel_clock * 10;
4762 mode->hdisplay = hactive;
4763 mode->hsync_start = mode->hdisplay + hsync;
4764 mode->hsync_end = mode->hsync_start + hsync_width;
4765 mode->htotal = mode->hdisplay + hblank;
4767 mode->vdisplay = vactive;
4768 mode->vsync_start = mode->vdisplay + vsync;
4769 mode->vsync_end = mode->vsync_start + vsync_width;
4770 mode->vtotal = mode->vdisplay + vblank;
4773 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4774 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4775 mode->type = DRM_MODE_TYPE_DRIVER;
4777 if (timings->flags & 0x80)
4778 mode->type |= DRM_MODE_TYPE_PREFERRED;
4779 mode->vrefresh = drm_mode_vrefresh(mode);
4780 drm_mode_set_name(mode);
4785 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4786 struct displayid_block *block)
4788 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4791 struct drm_display_mode *newmode;
4793 /* blocks must be multiple of 20 bytes length */
4794 if (block->num_bytes % 20)
4797 num_timings = block->num_bytes / 20;
4798 for (i = 0; i < num_timings; i++) {
4799 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4801 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4805 drm_mode_probed_add(connector, newmode);
4811 static int add_displayid_detailed_modes(struct drm_connector *connector,
4817 int length = EDID_LENGTH;
4818 struct displayid_block *block;
4821 displayid = drm_find_displayid_extension(edid);
4825 ret = validate_displayid(displayid, length, idx);
4829 idx += sizeof(struct displayid_hdr);
4830 for_each_displayid_db(displayid, block, idx, length) {
4831 switch (block->tag) {
4832 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4833 num_modes += add_displayid_detailed_1_modes(connector, block);
4841 * drm_add_edid_modes - add modes from EDID data, if available
4842 * @connector: connector we're probing
4845 * Add the specified modes to the connector's mode list. Also fills out the
4846 * &drm_display_info structure and ELD in @connector with any information which
4847 * can be derived from the edid.
4849 * Return: The number of modes added or 0 if we couldn't find any.
4851 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4857 clear_eld(connector);
4860 if (!drm_edid_is_valid(edid)) {
4861 clear_eld(connector);
4862 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4867 drm_edid_to_eld(connector, edid);
4870 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4871 * To avoid multiple parsing of same block, lets parse that map
4872 * from sink info, before parsing CEA modes.
4874 quirks = drm_add_display_info(connector, edid);
4877 * EDID spec says modes should be preferred in this order:
4878 * - preferred detailed mode
4879 * - other detailed modes from base block
4880 * - detailed modes from extension blocks
4881 * - CVT 3-byte code modes
4882 * - standard timing codes
4883 * - established timing codes
4884 * - modes inferred from GTF or CVT range information
4886 * We get this pretty much right.
4888 * XXX order for additional mode types in extension blocks?
4890 num_modes += add_detailed_modes(connector, edid, quirks);
4891 num_modes += add_cvt_modes(connector, edid);
4892 num_modes += add_standard_modes(connector, edid);
4893 num_modes += add_established_modes(connector, edid);
4894 num_modes += add_cea_modes(connector, edid);
4895 num_modes += add_alternate_cea_modes(connector, edid);
4896 num_modes += add_displayid_detailed_modes(connector, edid);
4897 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4898 num_modes += add_inferred_modes(connector, edid);
4900 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4901 edid_fixup_preferred(connector, quirks);
4903 if (quirks & EDID_QUIRK_FORCE_6BPC)
4904 connector->display_info.bpc = 6;
4906 if (quirks & EDID_QUIRK_FORCE_8BPC)
4907 connector->display_info.bpc = 8;
4909 if (quirks & EDID_QUIRK_FORCE_10BPC)
4910 connector->display_info.bpc = 10;
4912 if (quirks & EDID_QUIRK_FORCE_12BPC)
4913 connector->display_info.bpc = 12;
4917 EXPORT_SYMBOL(drm_add_edid_modes);
4920 * drm_add_modes_noedid - add modes for the connectors without EDID
4921 * @connector: connector we're probing
4922 * @hdisplay: the horizontal display limit
4923 * @vdisplay: the vertical display limit
4925 * Add the specified modes to the connector's mode list. Only when the
4926 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4928 * Return: The number of modes added or 0 if we couldn't find any.
4930 int drm_add_modes_noedid(struct drm_connector *connector,
4931 int hdisplay, int vdisplay)
4933 int i, count, num_modes = 0;
4934 struct drm_display_mode *mode;
4935 struct drm_device *dev = connector->dev;
4937 count = ARRAY_SIZE(drm_dmt_modes);
4943 for (i = 0; i < count; i++) {
4944 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4945 if (hdisplay && vdisplay) {
4947 * Only when two are valid, they will be used to check
4948 * whether the mode should be added to the mode list of
4951 if (ptr->hdisplay > hdisplay ||
4952 ptr->vdisplay > vdisplay)
4955 if (drm_mode_vrefresh(ptr) > 61)
4957 mode = drm_mode_duplicate(dev, ptr);
4959 drm_mode_probed_add(connector, mode);
4965 EXPORT_SYMBOL(drm_add_modes_noedid);
4968 * drm_set_preferred_mode - Sets the preferred mode of a connector
4969 * @connector: connector whose mode list should be processed
4970 * @hpref: horizontal resolution of preferred mode
4971 * @vpref: vertical resolution of preferred mode
4973 * Marks a mode as preferred if it matches the resolution specified by @hpref
4976 void drm_set_preferred_mode(struct drm_connector *connector,
4977 int hpref, int vpref)
4979 struct drm_display_mode *mode;
4981 list_for_each_entry(mode, &connector->probed_modes, head) {
4982 if (mode->hdisplay == hpref &&
4983 mode->vdisplay == vpref)
4984 mode->type |= DRM_MODE_TYPE_PREFERRED;
4987 EXPORT_SYMBOL(drm_set_preferred_mode);
4989 static bool is_hdmi2_sink(struct drm_connector *connector)
4992 * FIXME: sil-sii8620 doesn't have a connector around when
4993 * we need one, so we have to be prepared for a NULL connector.
4998 return connector->display_info.hdmi.scdc.supported ||
4999 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
5002 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5004 return sink_eotf & BIT(output_eotf);
5008 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5009 * HDR metadata from userspace
5010 * @frame: HDMI DRM infoframe
5011 * @conn_state: Connector state containing HDR metadata
5013 * Return: 0 on success or a negative error code on failure.
5016 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5017 const struct drm_connector_state *conn_state)
5019 struct drm_connector *connector;
5020 struct hdr_output_metadata *hdr_metadata;
5023 if (!frame || !conn_state)
5026 connector = conn_state->connector;
5028 if (!conn_state->hdr_output_metadata)
5031 hdr_metadata = conn_state->hdr_output_metadata->data;
5033 if (!hdr_metadata || !connector)
5036 /* Sink EOTF is Bit map while infoframe is absolute values */
5037 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5038 connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5039 DRM_DEBUG_KMS("EOTF Not Supported\n");
5043 err = hdmi_drm_infoframe_init(frame);
5047 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5048 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5050 BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5051 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5052 BUILD_BUG_ON(sizeof(frame->white_point) !=
5053 sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5055 memcpy(&frame->display_primaries,
5056 &hdr_metadata->hdmi_metadata_type1.display_primaries,
5057 sizeof(frame->display_primaries));
5059 memcpy(&frame->white_point,
5060 &hdr_metadata->hdmi_metadata_type1.white_point,
5061 sizeof(frame->white_point));
5063 frame->max_display_mastering_luminance =
5064 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5065 frame->min_display_mastering_luminance =
5066 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5067 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5068 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5072 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5075 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5076 * data from a DRM display mode
5077 * @frame: HDMI AVI infoframe
5078 * @connector: the connector
5079 * @mode: DRM display mode
5081 * Return: 0 on success or a negative error code on failure.
5084 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
5085 struct drm_connector *connector,
5086 const struct drm_display_mode *mode)
5088 enum hdmi_picture_aspect picture_aspect;
5091 if (!frame || !mode)
5094 err = hdmi_avi_infoframe_init(frame);
5098 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5099 frame->pixel_repeat = 1;
5101 frame->video_code = drm_match_cea_mode(mode);
5104 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5105 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5106 * have to make sure we dont break HDMI 1.4 sinks.
5108 if (!is_hdmi2_sink(connector) && frame->video_code > 64)
5109 frame->video_code = 0;
5112 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5113 * we should send its VIC in vendor infoframes, else send the
5114 * VIC in AVI infoframes. Lets check if this mode is present in
5115 * HDMI 1.4b 4K modes
5117 if (frame->video_code) {
5118 u8 vendor_if_vic = drm_match_hdmi_mode(mode);
5119 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
5121 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
5122 frame->video_code = 0;
5125 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5128 * As some drivers don't support atomic, we can't use connector state.
5129 * So just initialize the frame with default values, just the same way
5130 * as it's done with other properties here.
5132 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5136 * Populate picture aspect ratio from either
5137 * user input (if specified) or from the CEA mode list.
5139 picture_aspect = mode->picture_aspect_ratio;
5140 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE)
5141 picture_aspect = drm_get_cea_aspect_ratio(frame->video_code);
5144 * The infoframe can't convey anything but none, 4:3
5145 * and 16:9, so if the user has asked for anything else
5146 * we can only satisfy it by specifying the right VIC.
5148 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
5149 if (picture_aspect !=
5150 drm_get_cea_aspect_ratio(frame->video_code))
5152 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5155 frame->picture_aspect = picture_aspect;
5156 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
5157 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
5161 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
5163 /* HDMI Colorspace Spec Definitions */
5164 #define FULL_COLORIMETRY_MASK 0x1FF
5165 #define NORMAL_COLORIMETRY_MASK 0x3
5166 #define EXTENDED_COLORIMETRY_MASK 0x7
5167 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF
5169 #define C(x) ((x) << 0)
5170 #define EC(x) ((x) << 2)
5171 #define ACE(x) ((x) << 5)
5173 #define HDMI_COLORIMETRY_NO_DATA 0x0
5174 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
5175 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
5176 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
5177 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
5178 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
5179 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
5180 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
5181 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
5182 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
5183 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
5184 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
5185 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
5187 static const u32 hdmi_colorimetry_val[] = {
5188 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
5189 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
5190 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
5191 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
5192 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
5193 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
5194 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
5195 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
5196 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
5197 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
5198 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
5206 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
5207 * colorspace information
5208 * @frame: HDMI AVI infoframe
5209 * @conn_state: connector state
5212 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
5213 const struct drm_connector_state *conn_state)
5215 u32 colorimetry_val;
5216 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
5218 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
5219 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
5221 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5223 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5225 * ToDo: Extend it for ACE formats as well. Modify the infoframe
5226 * structure and extend it in drivers/video/hdmi
5228 frame->extended_colorimetry = (colorimetry_val >> 2) &
5229 EXTENDED_COLORIMETRY_MASK;
5231 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
5234 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5235 * quantization range information
5236 * @frame: HDMI AVI infoframe
5237 * @connector: the connector
5238 * @mode: DRM display mode
5239 * @rgb_quant_range: RGB quantization range (Q)
5242 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
5243 struct drm_connector *connector,
5244 const struct drm_display_mode *mode,
5245 enum hdmi_quantization_range rgb_quant_range)
5247 const struct drm_display_info *info = &connector->display_info;
5251 * "A Source shall not send a non-zero Q value that does not correspond
5252 * to the default RGB Quantization Range for the transmitted Picture
5253 * unless the Sink indicates support for the Q bit in a Video
5254 * Capabilities Data Block."
5256 * HDMI 2.0 recommends sending non-zero Q when it does match the
5257 * default RGB quantization range for the mode, even when QS=0.
5259 if (info->rgb_quant_range_selectable ||
5260 rgb_quant_range == drm_default_rgb_quant_range(mode))
5261 frame->quantization_range = rgb_quant_range;
5263 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
5267 * "When transmitting any RGB colorimetry, the Source should set the
5268 * YQ-field to match the RGB Quantization Range being transmitted
5269 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5270 * set YQ=1) and the Sink shall ignore the YQ-field."
5272 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5273 * by non-zero YQ when receiving RGB. There doesn't seem to be any
5274 * good way to tell which version of CEA-861 the sink supports, so
5275 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5278 if (!is_hdmi2_sink(connector) ||
5279 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
5280 frame->ycc_quantization_range =
5281 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5283 frame->ycc_quantization_range =
5284 HDMI_YCC_QUANTIZATION_RANGE_FULL;
5286 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
5288 static enum hdmi_3d_structure
5289 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
5291 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
5294 case DRM_MODE_FLAG_3D_FRAME_PACKING:
5295 return HDMI_3D_STRUCTURE_FRAME_PACKING;
5296 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
5297 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
5298 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
5299 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
5300 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
5301 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
5302 case DRM_MODE_FLAG_3D_L_DEPTH:
5303 return HDMI_3D_STRUCTURE_L_DEPTH;
5304 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
5305 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
5306 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
5307 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
5308 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
5309 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5311 return HDMI_3D_STRUCTURE_INVALID;
5316 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5317 * data from a DRM display mode
5318 * @frame: HDMI vendor infoframe
5319 * @connector: the connector
5320 * @mode: DRM display mode
5322 * Note that there's is a need to send HDMI vendor infoframes only when using a
5323 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5324 * function will return -EINVAL, error that can be safely ignored.
5326 * Return: 0 on success or a negative error code on failure.
5329 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
5330 struct drm_connector *connector,
5331 const struct drm_display_mode *mode)
5334 * FIXME: sil-sii8620 doesn't have a connector around when
5335 * we need one, so we have to be prepared for a NULL connector.
5337 bool has_hdmi_infoframe = connector ?
5338 connector->display_info.has_hdmi_infoframe : false;
5343 if (!frame || !mode)
5346 if (!has_hdmi_infoframe)
5349 vic = drm_match_hdmi_mode(mode);
5350 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
5353 * Even if it's not absolutely necessary to send the infoframe
5354 * (ie.vic==0 and s3d_struct==0) we will still send it if we
5355 * know that the sink can handle it. This is based on a
5356 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5357 * have trouble realizing that they shuld switch from 3D to 2D
5358 * mode if the source simply stops sending the infoframe when
5359 * it wants to switch from 3D to 2D.
5362 if (vic && s3d_flags)
5365 err = hdmi_vendor_infoframe_init(frame);
5370 frame->s3d_struct = s3d_structure_from_display_mode(mode);
5374 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
5376 static int drm_parse_tiled_block(struct drm_connector *connector,
5377 struct displayid_block *block)
5379 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5381 u8 tile_v_loc, tile_h_loc;
5382 u8 num_v_tile, num_h_tile;
5383 struct drm_tile_group *tg;
5385 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5386 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5388 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5389 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5390 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5391 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5393 connector->has_tile = true;
5394 if (tile->tile_cap & 0x80)
5395 connector->tile_is_single_monitor = true;
5397 connector->num_h_tile = num_h_tile + 1;
5398 connector->num_v_tile = num_v_tile + 1;
5399 connector->tile_h_loc = tile_h_loc;
5400 connector->tile_v_loc = tile_v_loc;
5401 connector->tile_h_size = w + 1;
5402 connector->tile_v_size = h + 1;
5404 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5405 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5406 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5407 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5408 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5410 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5412 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5417 if (connector->tile_group != tg) {
5418 /* if we haven't got a pointer,
5419 take the reference, drop ref to old tile group */
5420 if (connector->tile_group) {
5421 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5423 connector->tile_group = tg;
5425 /* if same tile group, then release the ref we just took. */
5426 drm_mode_put_tile_group(connector->dev, tg);
5430 static int drm_parse_display_id(struct drm_connector *connector,
5431 u8 *displayid, int length,
5432 bool is_edid_extension)
5434 /* if this is an EDID extension the first byte will be 0x70 */
5436 struct displayid_block *block;
5439 if (is_edid_extension)
5442 ret = validate_displayid(displayid, length, idx);
5446 idx += sizeof(struct displayid_hdr);
5447 for_each_displayid_db(displayid, block, idx, length) {
5448 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5449 block->tag, block->rev, block->num_bytes);
5451 switch (block->tag) {
5452 case DATA_BLOCK_TILED_DISPLAY:
5453 ret = drm_parse_tiled_block(connector, block);
5457 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5458 /* handled in mode gathering code. */
5460 case DATA_BLOCK_CTA:
5461 /* handled in the cea parser code. */
5464 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5471 static void drm_get_displayid(struct drm_connector *connector,
5474 void *displayid = NULL;
5476 connector->has_tile = false;
5477 displayid = drm_find_displayid_extension(edid);
5479 /* drop reference to any tile group we had */
5483 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5486 if (!connector->has_tile)
5490 if (connector->tile_group) {
5491 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5492 connector->tile_group = NULL;
git.samba.org / sfrench / cifs-2.6.git / blob