drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3 * Analogix DP (Display Port) core interface driver.
   4 *
   5 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   6 * Author: Jingoo Han <jg1.han@samsung.com>
   7 */
   8
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/err.h>
  12 #include <linux/gpio/consumer.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/iopoll.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/phy/phy.h>
  19 #include <linux/platform_device.h>
  20
  21 #include <drm/bridge/analogix_dp.h>
  22 #include <drm/drm_atomic.h>
  23 #include <drm/drm_atomic_helper.h>
  24 #include <drm/drm_crtc.h>
  25 #include <drm/drm_device.h>
  26 #include <drm/drm_panel.h>
  27 #include <drm/drm_print.h>
  28 #include <drm/drm_probe_helper.h>
  29
  30 #include "analogix_dp_core.h"
  31 #include "analogix_dp_reg.h"
  32
  33 #define to_dp(nm)       container_of(nm, struct analogix_dp_device, nm)
  34
  35 static const bool verify_fast_training;
  36
  37 struct bridge_init {
  38         struct i2c_client *client;
  39         struct device_node *node;
  40 };
  41
  42 static int analogix_dp_init_dp(struct analogix_dp_device *dp)
  43 {
  44         int ret;
  45
  46         analogix_dp_reset(dp);
  47
  48         analogix_dp_swreset(dp);
  49
  50         analogix_dp_init_analog_param(dp);
  51         analogix_dp_init_interrupt(dp);
  52
  53         /* SW defined function Normal operation */
  54         analogix_dp_enable_sw_function(dp);
  55
  56         analogix_dp_config_interrupt(dp);
  57         ret = analogix_dp_init_analog_func(dp);
  58         if (ret)
  59                 return ret;
  60
  61         analogix_dp_init_hpd(dp);
  62         analogix_dp_init_aux(dp);
  63         return 0;
  64 }
  65
  66 static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
  67 {
  68         int timeout_loop = 0;
  69
  70         while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
  71                 if (analogix_dp_get_plug_in_status(dp) == 0)
  72                         return 0;
  73
  74                 timeout_loop++;
  75                 usleep_range(1000, 1100);
  76         }
  77
  78         /*
  79          * Some edp screen do not have hpd signal, so we can't just
  80          * return failed when hpd plug in detect failed, DT property
  81          * "force-hpd" would indicate whether driver need this.
  82          */
  83         if (!dp->force_hpd)
  84                 return -ETIMEDOUT;
  85
  86         /*
  87          * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
  88          * will not work, so we need to give a force hpd action to
  89          * set HPD_STATUS manually.
  90          */
  91         dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
  92
  93         analogix_dp_force_hpd(dp);
  94
  95         if (analogix_dp_get_plug_in_status(dp) != 0) {
  96                 dev_err(dp->dev, "failed to get hpd plug in status\n");
  97                 return -EINVAL;
  98         }
  99
 100         dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
 101
 102         return 0;
 103 }
 104
 105 static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
 106 {
 107         unsigned char psr_version;
 108         int ret;
 109
 110         ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);
 111         if (ret != 1) {
 112                 dev_err(dp->dev, "failed to get PSR version, disable it\n");
 113                 return false;
 114         }
 115
 116         dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version);
 117         return psr_version & DP_PSR_IS_SUPPORTED;
 118 }
 119
 120 static int analogix_dp_enable_sink_psr(struct analogix_dp_device *dp)
 121 {
 122         unsigned char psr_en;
 123         int ret;
 124
 125         /* Disable psr function */
 126         ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en);
 127         if (ret != 1) {
 128                 dev_err(dp->dev, "failed to get psr config\n");
 129                 goto end;
 130         }
 131
 132         psr_en &= ~DP_PSR_ENABLE;
 133         ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
 134         if (ret != 1) {
 135                 dev_err(dp->dev, "failed to disable panel psr\n");
 136                 goto end;
 137         }
 138
 139         /* Main-Link transmitter remains active during PSR active states */
 140         psr_en = DP_PSR_CRC_VERIFICATION;
 141         ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
 142         if (ret != 1) {
 143                 dev_err(dp->dev, "failed to set panel psr\n");
 144                 goto end;
 145         }
 146
 147         /* Enable psr function */
 148         psr_en = DP_PSR_ENABLE | DP_PSR_CRC_VERIFICATION;
 149         ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
 150         if (ret != 1) {
 151                 dev_err(dp->dev, "failed to set panel psr\n");
 152                 goto end;
 153         }
 154
 155         analogix_dp_enable_psr_crc(dp);
 156
 157         dp->psr_supported = true;
 158
 159         return 0;
 160 end:
 161         dev_err(dp->dev, "enable psr fail, force to disable psr\n");
 162
 163         return ret;
 164 }
 165
 166 static int
 167 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
 168                                        bool enable)
 169 {
 170         u8 data;
 171         int ret;
 172
 173         ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);
 174         if (ret != 1)
 175                 return ret;
 176
 177         if (enable)
 178                 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
 179                                          DP_LANE_COUNT_ENHANCED_FRAME_EN |
 180                                          DPCD_LANE_COUNT_SET(data));
 181         else
 182                 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
 183                                          DPCD_LANE_COUNT_SET(data));
 184
 185         return ret < 0 ? ret : 0;
 186 }
 187
 188 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp,
 189                                                   u8 *enhanced_mode_support)
 190 {
 191         u8 data;
 192         int ret;
 193
 194         ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
 195         if (ret != 1) {
 196                 *enhanced_mode_support = 0;
 197                 return ret;
 198         }
 199
 200         *enhanced_mode_support = DPCD_ENHANCED_FRAME_CAP(data);
 201
 202         return 0;
 203 }
 204
 205 static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
 206 {
 207         u8 data;
 208         int ret;
 209
 210         ret = analogix_dp_is_enhanced_mode_available(dp, &data);
 211         if (ret < 0)
 212                 return ret;
 213
 214         ret = analogix_dp_enable_rx_to_enhanced_mode(dp, data);
 215         if (ret < 0)
 216                 return ret;
 217
 218         analogix_dp_enable_enhanced_mode(dp, data);
 219
 220         return 0;
 221 }
 222
 223 static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
 224 {
 225         int ret;
 226
 227         analogix_dp_set_training_pattern(dp, DP_NONE);
 228
 229         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 230                                  DP_TRAINING_PATTERN_DISABLE);
 231
 232         return ret < 0 ? ret : 0;
 233 }
 234
 235 static void
 236 analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
 237                                        int pre_emphasis, int lane)
 238 {
 239         switch (lane) {
 240         case 0:
 241                 analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
 242                 break;
 243         case 1:
 244                 analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
 245                 break;
 246
 247         case 2:
 248                 analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
 249                 break;
 250
 251         case 3:
 252                 analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
 253                 break;
 254         }
 255 }
 256
 257 static int analogix_dp_link_start(struct analogix_dp_device *dp)
 258 {
 259         u8 buf[4];
 260         int lane, lane_count, pll_tries, retval;
 261
 262         lane_count = dp->link_train.lane_count;
 263
 264         dp->link_train.lt_state = CLOCK_RECOVERY;
 265         dp->link_train.eq_loop = 0;
 266
 267         for (lane = 0; lane < lane_count; lane++)
 268                 dp->link_train.cr_loop[lane] = 0;
 269
 270         /* Set link rate and count as you want to establish*/
 271         analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 272         analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
 273
 274         /* Setup RX configuration */
 275         buf[0] = dp->link_train.link_rate;
 276         buf[1] = dp->link_train.lane_count;
 277         retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2);
 278         if (retval < 0)
 279                 return retval;
 280         /* set enhanced mode if available */
 281         retval = analogix_dp_set_enhanced_mode(dp);
 282         if (retval < 0) {
 283                 dev_err(dp->dev, "failed to set enhance mode\n");
 284                 return retval;
 285         }
 286
 287         /* Set TX pre-emphasis to minimum */
 288         for (lane = 0; lane < lane_count; lane++)
 289                 analogix_dp_set_lane_lane_pre_emphasis(dp,
 290                         PRE_EMPHASIS_LEVEL_0, lane);
 291
 292         /* Wait for PLL lock */
 293         pll_tries = 0;
 294         while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 295                 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
 296                         dev_err(dp->dev, "Wait for PLL lock timed out\n");
 297                         return -ETIMEDOUT;
 298                 }
 299
 300                 pll_tries++;
 301                 usleep_range(90, 120);
 302         }
 303
 304         /* Set training pattern 1 */
 305         analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
 306
 307         /* Set RX training pattern */
 308         retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 309                                     DP_LINK_SCRAMBLING_DISABLE |
 310                                         DP_TRAINING_PATTERN_1);
 311         if (retval < 0)
 312                 return retval;
 313
 314         for (lane = 0; lane < lane_count; lane++)
 315                 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
 316                             DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 317
 318         retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf,
 319                                    lane_count);
 320         if (retval < 0)
 321                 return retval;
 322
 323         return 0;
 324 }
 325
 326 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
 327 {
 328         int shift = (lane & 1) * 4;
 329         u8 link_value = link_status[lane >> 1];
 330
 331         return (link_value >> shift) & 0xf;
 332 }
 333
 334 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 335 {
 336         int lane;
 337         u8 lane_status;
 338
 339         for (lane = 0; lane < lane_count; lane++) {
 340                 lane_status = analogix_dp_get_lane_status(link_status, lane);
 341                 if ((lane_status & DP_LANE_CR_DONE) == 0)
 342                         return -EINVAL;
 343         }
 344         return 0;
 345 }
 346
 347 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 348                                      int lane_count)
 349 {
 350         int lane;
 351         u8 lane_status;
 352
 353         if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
 354                 return -EINVAL;
 355
 356         for (lane = 0; lane < lane_count; lane++) {
 357                 lane_status = analogix_dp_get_lane_status(link_status, lane);
 358                 lane_status &= DP_CHANNEL_EQ_BITS;
 359                 if (lane_status != DP_CHANNEL_EQ_BITS)
 360                         return -EINVAL;
 361         }
 362
 363         return 0;
 364 }
 365
 366 static unsigned char
 367 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
 368 {
 369         int shift = (lane & 1) * 4;
 370         u8 link_value = adjust_request[lane >> 1];
 371
 372         return (link_value >> shift) & 0x3;
 373 }
 374
 375 static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
 376                                         u8 adjust_request[2],
 377                                         int lane)
 378 {
 379         int shift = (lane & 1) * 4;
 380         u8 link_value = adjust_request[lane >> 1];
 381
 382         return ((link_value >> shift) & 0xc) >> 2;
 383 }
 384
 385 static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
 386                                                u8 training_lane_set, int lane)
 387 {
 388         switch (lane) {
 389         case 0:
 390                 analogix_dp_set_lane0_link_training(dp, training_lane_set);
 391                 break;
 392         case 1:
 393                 analogix_dp_set_lane1_link_training(dp, training_lane_set);
 394                 break;
 395
 396         case 2:
 397                 analogix_dp_set_lane2_link_training(dp, training_lane_set);
 398                 break;
 399
 400         case 3:
 401                 analogix_dp_set_lane3_link_training(dp, training_lane_set);
 402                 break;
 403         }
 404 }
 405
 406 static unsigned int
 407 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp,
 408                                    int lane)
 409 {
 410         u32 reg;
 411
 412         switch (lane) {
 413         case 0:
 414                 reg = analogix_dp_get_lane0_link_training(dp);
 415                 break;
 416         case 1:
 417                 reg = analogix_dp_get_lane1_link_training(dp);
 418                 break;
 419         case 2:
 420                 reg = analogix_dp_get_lane2_link_training(dp);
 421                 break;
 422         case 3:
 423                 reg = analogix_dp_get_lane3_link_training(dp);
 424                 break;
 425         default:
 426                 WARN_ON(1);
 427                 return 0;
 428         }
 429
 430         return reg;
 431 }
 432
 433 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
 434 {
 435         analogix_dp_training_pattern_dis(dp);
 436         analogix_dp_set_enhanced_mode(dp);
 437
 438         dp->link_train.lt_state = FAILED;
 439 }
 440
 441 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
 442                                                  u8 adjust_request[2])
 443 {
 444         int lane, lane_count;
 445         u8 voltage_swing, pre_emphasis, training_lane;
 446
 447         lane_count = dp->link_train.lane_count;
 448         for (lane = 0; lane < lane_count; lane++) {
 449                 voltage_swing = analogix_dp_get_adjust_request_voltage(
 450                                                 adjust_request, lane);
 451                 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 452                                                 adjust_request, lane);
 453                 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 454                                 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 455
 456                 if (voltage_swing == VOLTAGE_LEVEL_3)
 457                         training_lane |= DP_TRAIN_MAX_SWING_REACHED;
 458                 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 459                         training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 460
 461                 dp->link_train.training_lane[lane] = training_lane;
 462         }
 463 }
 464
 465 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
 466 {
 467         int lane, lane_count, retval;
 468         u8 voltage_swing, pre_emphasis, training_lane;
 469         u8 link_status[2], adjust_request[2];
 470
 471         usleep_range(100, 101);
 472
 473         lane_count = dp->link_train.lane_count;
 474
 475         retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
 476         if (retval < 0)
 477                 return retval;
 478
 479         retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
 480                                   adjust_request, 2);
 481         if (retval < 0)
 482                 return retval;
 483
 484         if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 485                 /* set training pattern 2 for EQ */
 486                 analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
 487
 488                 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 489                                             DP_LINK_SCRAMBLING_DISABLE |
 490                                                 DP_TRAINING_PATTERN_2);
 491                 if (retval < 0)
 492                         return retval;
 493
 494                 dev_dbg(dp->dev, "Link Training Clock Recovery success\n");
 495                 dp->link_train.lt_state = EQUALIZER_TRAINING;
 496         } else {
 497                 for (lane = 0; lane < lane_count; lane++) {
 498                         training_lane = analogix_dp_get_lane_link_training(
 499                                                         dp, lane);
 500                         voltage_swing = analogix_dp_get_adjust_request_voltage(
 501                                                         adjust_request, lane);
 502                         pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 503                                                         adjust_request, lane);
 504
 505                         if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
 506                                         voltage_swing &&
 507                             DPCD_PRE_EMPHASIS_GET(training_lane) ==
 508                                         pre_emphasis)
 509                                 dp->link_train.cr_loop[lane]++;
 510
 511                         if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
 512                             voltage_swing == VOLTAGE_LEVEL_3 ||
 513                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 514                                 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
 515                                         dp->link_train.cr_loop[lane],
 516                                         voltage_swing, pre_emphasis);
 517                                 analogix_dp_reduce_link_rate(dp);
 518                                 return -EIO;
 519                         }
 520                 }
 521         }
 522
 523         analogix_dp_get_adjust_training_lane(dp, adjust_request);
 524
 525         for (lane = 0; lane < lane_count; lane++)
 526                 analogix_dp_set_lane_link_training(dp,
 527                         dp->link_train.training_lane[lane], lane);
 528
 529         retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
 530                                    dp->link_train.training_lane, lane_count);
 531         if (retval < 0)
 532                 return retval;
 533
 534         return 0;
 535 }
 536
 537 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 538 {
 539         int lane, lane_count, retval;
 540         u32 reg;
 541         u8 link_align, link_status[2], adjust_request[2];
 542
 543         usleep_range(400, 401);
 544
 545         lane_count = dp->link_train.lane_count;
 546
 547         retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
 548         if (retval < 0)
 549                 return retval;
 550
 551         if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
 552                 analogix_dp_reduce_link_rate(dp);
 553                 return -EIO;
 554         }
 555
 556         retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
 557                                   adjust_request, 2);
 558         if (retval < 0)
 559                 return retval;
 560
 561         retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
 562                                    &link_align);
 563         if (retval < 0)
 564                 return retval;
 565
 566         analogix_dp_get_adjust_training_lane(dp, adjust_request);
 567
 568         if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
 569                 /* traing pattern Set to Normal */
 570                 retval = analogix_dp_training_pattern_dis(dp);
 571                 if (retval < 0)
 572                         return retval;
 573
 574                 dev_dbg(dp->dev, "Link Training success!\n");
 575                 analogix_dp_get_link_bandwidth(dp, &reg);
 576                 dp->link_train.link_rate = reg;
 577                 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 578                         dp->link_train.link_rate);
 579
 580                 analogix_dp_get_lane_count(dp, &reg);
 581                 dp->link_train.lane_count = reg;
 582                 dev_dbg(dp->dev, "final lane count = %.2x\n",
 583                         dp->link_train.lane_count);
 584
 585                 dp->link_train.lt_state = FINISHED;
 586
 587                 return 0;
 588         }
 589
 590         /* not all locked */
 591         dp->link_train.eq_loop++;
 592
 593         if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 594                 dev_err(dp->dev, "EQ Max loop\n");
 595                 analogix_dp_reduce_link_rate(dp);
 596                 return -EIO;
 597         }
 598
 599         for (lane = 0; lane < lane_count; lane++)
 600                 analogix_dp_set_lane_link_training(dp,
 601                         dp->link_train.training_lane[lane], lane);
 602
 603         retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
 604                                    dp->link_train.training_lane, lane_count);
 605         if (retval < 0)
 606                 return retval;
 607
 608         return 0;
 609 }
 610
 611 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 612                                              u8 *bandwidth)
 613 {
 614         u8 data;
 615
 616         /*
 617          * For DP rev.1.1, Maximum link rate of Main Link lanes
 618          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 619          * For DP rev.1.2, Maximum link rate of Main Link lanes
 620          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
 621          */
 622         drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data);
 623         *bandwidth = data;
 624 }
 625
 626 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
 627                                               u8 *lane_count)
 628 {
 629         u8 data;
 630
 631         /*
 632          * For DP rev.1.1, Maximum number of Main Link lanes
 633          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 634          */
 635         drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
 636         *lane_count = DPCD_MAX_LANE_COUNT(data);
 637 }
 638
 639 static int analogix_dp_full_link_train(struct analogix_dp_device *dp,
 640                                        u32 max_lanes, u32 max_rate)
 641 {
 642         int retval = 0;
 643         bool training_finished = false;
 644
 645         /*
 646          * MACRO_RST must be applied after the PLL_LOCK to avoid
 647          * the DP inter pair skew issue for at least 10 us
 648          */
 649         analogix_dp_reset_macro(dp);
 650
 651         /* Initialize by reading RX's DPCD */
 652         analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 653         analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 654
 655         if ((dp->link_train.link_rate != DP_LINK_BW_1_62) &&
 656             (dp->link_train.link_rate != DP_LINK_BW_2_7) &&
 657             (dp->link_train.link_rate != DP_LINK_BW_5_4)) {
 658                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 659                         dp->link_train.link_rate);
 660                 dp->link_train.link_rate = DP_LINK_BW_1_62;
 661         }
 662
 663         if (dp->link_train.lane_count == 0) {
 664                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 665                         dp->link_train.lane_count);
 666                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 667         }
 668
 669         /* Setup TX lane count & rate */
 670         if (dp->link_train.lane_count > max_lanes)
 671                 dp->link_train.lane_count = max_lanes;
 672         if (dp->link_train.link_rate > max_rate)
 673                 dp->link_train.link_rate = max_rate;
 674
 675         /* All DP analog module power up */
 676         analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
 677
 678         dp->link_train.lt_state = START;
 679
 680         /* Process here */
 681         while (!retval && !training_finished) {
 682                 switch (dp->link_train.lt_state) {
 683                 case START:
 684                         retval = analogix_dp_link_start(dp);
 685                         if (retval)
 686                                 dev_err(dp->dev, "LT link start failed!\n");
 687                         break;
 688                 case CLOCK_RECOVERY:
 689                         retval = analogix_dp_process_clock_recovery(dp);
 690                         if (retval)
 691                                 dev_err(dp->dev, "LT CR failed!\n");
 692                         break;
 693                 case EQUALIZER_TRAINING:
 694                         retval = analogix_dp_process_equalizer_training(dp);
 695                         if (retval)
 696                                 dev_err(dp->dev, "LT EQ failed!\n");
 697                         break;
 698                 case FINISHED:
 699                         training_finished = 1;
 700                         break;
 701                 case FAILED:
 702                         return -EREMOTEIO;
 703                 }
 704         }
 705         if (retval)
 706                 dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
 707
 708         return retval;
 709 }
 710
 711 static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)
 712 {
 713         int i, ret;
 714         u8 link_align, link_status[2];
 715         enum pll_status status;
 716
 717         analogix_dp_reset_macro(dp);
 718
 719         analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 720         analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
 721
 722         for (i = 0; i < dp->link_train.lane_count; i++) {
 723                 analogix_dp_set_lane_link_training(dp,
 724                         dp->link_train.training_lane[i], i);
 725         }
 726
 727         ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status,
 728                                  status != PLL_UNLOCKED, 120,
 729                                  120 * DP_TIMEOUT_LOOP_COUNT);
 730         if (ret) {
 731                 DRM_DEV_ERROR(dp->dev, "Wait for pll lock failed %d\n", ret);
 732                 return ret;
 733         }
 734
 735         /* source Set training pattern 1 */
 736         analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
 737         /* From DP spec, pattern must be on-screen for a minimum 500us */
 738         usleep_range(500, 600);
 739
 740         analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
 741         /* From DP spec, pattern must be on-screen for a minimum 500us */
 742         usleep_range(500, 600);
 743
 744         /* TODO: enhanced_mode?*/
 745         analogix_dp_set_training_pattern(dp, DP_NONE);
 746
 747         /*
 748          * Useful for debugging issues with fast link training, disable for more
 749          * speed
 750          */
 751         if (verify_fast_training) {
 752                 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
 753                                         &link_align);
 754                 if (ret < 0) {
 755                         DRM_DEV_ERROR(dp->dev, "Read align status failed %d\n",
 756                                       ret);
 757                         return ret;
 758                 }
 759
 760                 ret = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status,
 761                                        2);
 762                 if (ret < 0) {
 763                         DRM_DEV_ERROR(dp->dev, "Read link status failed %d\n",
 764                                       ret);
 765                         return ret;
 766                 }
 767
 768                 if (analogix_dp_clock_recovery_ok(link_status,
 769                                                   dp->link_train.lane_count)) {
 770                         DRM_DEV_ERROR(dp->dev, "Clock recovery failed\n");
 771                         analogix_dp_reduce_link_rate(dp);
 772                         return -EIO;
 773                 }
 774
 775                 if (analogix_dp_channel_eq_ok(link_status, link_align,
 776                                               dp->link_train.lane_count)) {
 777                         DRM_DEV_ERROR(dp->dev, "Channel EQ failed\n");
 778                         analogix_dp_reduce_link_rate(dp);
 779                         return -EIO;
 780                 }
 781         }
 782
 783         return 0;
 784 }
 785
 786 static int analogix_dp_train_link(struct analogix_dp_device *dp)
 787 {
 788         if (dp->fast_train_enable)
 789                 return analogix_dp_fast_link_train(dp);
 790
 791         return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count,
 792                                            dp->video_info.max_link_rate);
 793 }
 794
 795 static int analogix_dp_config_video(struct analogix_dp_device *dp)
 796 {
 797         int timeout_loop = 0;
 798         int done_count = 0;
 799
 800         analogix_dp_config_video_slave_mode(dp);
 801
 802         analogix_dp_set_video_color_format(dp);
 803
 804         if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 805                 dev_err(dp->dev, "PLL is not locked yet.\n");
 806                 return -EINVAL;
 807         }
 808
 809         for (;;) {
 810                 timeout_loop++;
 811                 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
 812                         break;
 813                 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 814                         dev_err(dp->dev, "Timeout of slave video streamclk ok\n");
 815                         return -ETIMEDOUT;
 816                 }
 817                 usleep_range(1000, 1001);
 818         }
 819
 820         /* Set to use the register calculated M/N video */
 821         analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 822
 823         /* For video bist, Video timing must be generated by register */
 824         analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 825
 826         /* Disable video mute */
 827         analogix_dp_enable_video_mute(dp, 0);
 828
 829         /* Configure video slave mode */
 830         analogix_dp_enable_video_master(dp, 0);
 831
 832         /* Enable video */
 833         analogix_dp_start_video(dp);
 834
 835         timeout_loop = 0;
 836
 837         for (;;) {
 838                 timeout_loop++;
 839                 if (analogix_dp_is_video_stream_on(dp) == 0) {
 840                         done_count++;
 841                         if (done_count > 10)
 842                                 break;
 843                 } else if (done_count) {
 844                         done_count = 0;
 845                 }
 846                 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 847                         dev_warn(dp->dev,
 848                                  "Ignoring timeout of video streamclk ok\n");
 849                         break;
 850                 }
 851
 852                 usleep_range(1000, 1001);
 853         }
 854
 855         return 0;
 856 }
 857
 858 static int analogix_dp_enable_scramble(struct analogix_dp_device *dp,
 859                                        bool enable)
 860 {
 861         u8 data;
 862         int ret;
 863
 864         if (enable) {
 865                 analogix_dp_enable_scrambling(dp);
 866
 867                 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
 868                                         &data);
 869                 if (ret != 1)
 870                         return ret;
 871                 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 872                                    (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 873         } else {
 874                 analogix_dp_disable_scrambling(dp);
 875
 876                 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
 877                                         &data);
 878                 if (ret != 1)
 879                         return ret;
 880                 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 881                                    (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
 882         }
 883         return ret < 0 ? ret : 0;
 884 }
 885
 886 static irqreturn_t analogix_dp_hardirq(int irq, void *arg)
 887 {
 888         struct analogix_dp_device *dp = arg;
 889         irqreturn_t ret = IRQ_NONE;
 890         enum dp_irq_type irq_type;
 891
 892         irq_type = analogix_dp_get_irq_type(dp);
 893         if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
 894                 analogix_dp_mute_hpd_interrupt(dp);
 895                 ret = IRQ_WAKE_THREAD;
 896         }
 897
 898         return ret;
 899 }
 900
 901 static irqreturn_t analogix_dp_irq_thread(int irq, void *arg)
 902 {
 903         struct analogix_dp_device *dp = arg;
 904         enum dp_irq_type irq_type;
 905
 906         irq_type = analogix_dp_get_irq_type(dp);
 907         if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN ||
 908             irq_type & DP_IRQ_TYPE_HP_CABLE_OUT) {
 909                 dev_dbg(dp->dev, "Detected cable status changed!\n");
 910                 if (dp->drm_dev)
 911                         drm_helper_hpd_irq_event(dp->drm_dev);
 912         }
 913
 914         if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
 915                 analogix_dp_clear_hotplug_interrupts(dp);
 916                 analogix_dp_unmute_hpd_interrupt(dp);
 917         }
 918
 919         return IRQ_HANDLED;
 920 }
 921
 922 static int analogix_dp_fast_link_train_detection(struct analogix_dp_device *dp)
 923 {
 924         int ret;
 925         u8 spread;
 926
 927         ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &spread);
 928         if (ret != 1) {
 929                 dev_err(dp->dev, "failed to read downspread %d\n", ret);
 930                 return ret;
 931         }
 932         dp->fast_train_enable = !!(spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
 933         dev_dbg(dp->dev, "fast link training %s\n",
 934                 dp->fast_train_enable ? "supported" : "unsupported");
 935         return 0;
 936 }
 937
 938 static int analogix_dp_commit(struct analogix_dp_device *dp)
 939 {
 940         int ret;
 941
 942         /* Keep the panel disabled while we configure video */
 943         if (dp->plat_data->panel) {
 944                 if (drm_panel_disable(dp->plat_data->panel))
 945                         DRM_ERROR("failed to disable the panel\n");
 946         }
 947
 948         ret = analogix_dp_train_link(dp);
 949         if (ret) {
 950                 dev_err(dp->dev, "unable to do link train, ret=%d\n", ret);
 951                 return ret;
 952         }
 953
 954         ret = analogix_dp_enable_scramble(dp, 1);
 955         if (ret < 0) {
 956                 dev_err(dp->dev, "can not enable scramble\n");
 957                 return ret;
 958         }
 959
 960         analogix_dp_init_video(dp);
 961         ret = analogix_dp_config_video(dp);
 962         if (ret) {
 963                 dev_err(dp->dev, "unable to config video\n");
 964                 return ret;
 965         }
 966
 967         /* Safe to enable the panel now */
 968         if (dp->plat_data->panel) {
 969                 ret = drm_panel_enable(dp->plat_data->panel);
 970                 if (ret) {
 971                         DRM_ERROR("failed to enable the panel\n");
 972                         return ret;
 973                 }
 974         }
 975
 976         /* Check whether panel supports fast training */
 977         ret = analogix_dp_fast_link_train_detection(dp);
 978         if (ret)
 979                 return ret;
 980
 981         if (analogix_dp_detect_sink_psr(dp)) {
 982                 ret = analogix_dp_enable_sink_psr(dp);
 983                 if (ret)
 984                         return ret;
 985         }
 986
 987         return ret;
 988 }
 989
 990 static int analogix_dp_enable_psr(struct analogix_dp_device *dp)
 991 {
 992         struct dp_sdp psr_vsc;
 993         int ret;
 994         u8 sink;
 995
 996         ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
 997         if (ret != 1)
 998                 DRM_DEV_ERROR(dp->dev, "Failed to read psr status %d\n", ret);
 999         else if (sink == DP_PSR_SINK_ACTIVE_RFB)
1000                 return 0;
1001
1002         /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
1003         memset(&psr_vsc, 0, sizeof(psr_vsc));
1004         psr_vsc.sdp_header.HB0 = 0;
1005         psr_vsc.sdp_header.HB1 = 0x7;
1006         psr_vsc.sdp_header.HB2 = 0x2;
1007         psr_vsc.sdp_header.HB3 = 0x8;
1008         psr_vsc.db[0] = 0;
1009         psr_vsc.db[1] = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID;
1010
1011         ret = analogix_dp_send_psr_spd(dp, &psr_vsc, true);
1012         if (!ret)
1013                 analogix_dp_set_analog_power_down(dp, POWER_ALL, true);
1014
1015         return ret;
1016 }
1017
1018 static int analogix_dp_disable_psr(struct analogix_dp_device *dp)
1019 {
1020         struct dp_sdp psr_vsc;
1021         int ret;
1022         u8 sink;
1023
1024         analogix_dp_set_analog_power_down(dp, POWER_ALL, false);
1025
1026         ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
1027         if (ret != 1) {
1028                 DRM_DEV_ERROR(dp->dev, "Failed to set DP Power0 %d\n", ret);
1029                 return ret;
1030         }
1031
1032         ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
1033         if (ret != 1) {
1034                 DRM_DEV_ERROR(dp->dev, "Failed to read psr status %d\n", ret);
1035                 return ret;
1036         } else if (sink == DP_PSR_SINK_INACTIVE) {
1037                 DRM_DEV_ERROR(dp->dev, "sink inactive, skip disable psr");
1038                 return 0;
1039         }
1040
1041         ret = analogix_dp_train_link(dp);
1042         if (ret) {
1043                 DRM_DEV_ERROR(dp->dev, "Failed to train the link %d\n", ret);
1044                 return ret;
1045         }
1046
1047         /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
1048         memset(&psr_vsc, 0, sizeof(psr_vsc));
1049         psr_vsc.sdp_header.HB0 = 0;
1050         psr_vsc.sdp_header.HB1 = 0x7;
1051         psr_vsc.sdp_header.HB2 = 0x2;
1052         psr_vsc.sdp_header.HB3 = 0x8;
1053
1054         psr_vsc.db[0] = 0;
1055         psr_vsc.db[1] = 0;
1056
1057         return analogix_dp_send_psr_spd(dp, &psr_vsc, true);
1058 }
1059
1060 /*
1061  * This function is a bit of a catch-all for panel preparation, hopefully
1062  * simplifying the logic of functions that need to prepare/unprepare the panel
1063  * below.
1064  *
1065  * If @prepare is true, this function will prepare the panel. Conversely, if it
1066  * is false, the panel will be unprepared.
1067  *
1068  * If @is_modeset_prepare is true, the function will disregard the current state
1069  * of the panel and either prepare/unprepare the panel based on @prepare. Once
1070  * it finishes, it will update dp->panel_is_modeset to reflect the current state
1071  * of the panel.
1072  */
1073 static int analogix_dp_prepare_panel(struct analogix_dp_device *dp,
1074                                      bool prepare, bool is_modeset_prepare)
1075 {
1076         int ret = 0;
1077
1078         if (!dp->plat_data->panel)
1079                 return 0;
1080
1081         mutex_lock(&dp->panel_lock);
1082
1083         /*
1084          * Exit early if this is a temporary prepare/unprepare and we're already
1085          * modeset (since we neither want to prepare twice or unprepare early).
1086          */
1087         if (dp->panel_is_modeset && !is_modeset_prepare)
1088                 goto out;
1089
1090         if (prepare)
1091                 ret = drm_panel_prepare(dp->plat_data->panel);
1092         else
1093                 ret = drm_panel_unprepare(dp->plat_data->panel);
1094
1095         if (ret)
1096                 goto out;
1097
1098         if (is_modeset_prepare)
1099                 dp->panel_is_modeset = prepare;
1100
1101 out:
1102         mutex_unlock(&dp->panel_lock);
1103         return ret;
1104 }
1105
1106 static int analogix_dp_get_modes(struct drm_connector *connector)
1107 {
1108         struct analogix_dp_device *dp = to_dp(connector);
1109         struct edid *edid;
1110         int ret, num_modes = 0;
1111
1112         if (dp->plat_data->panel) {
1113                 num_modes += drm_panel_get_modes(dp->plat_data->panel);
1114         } else {
1115                 ret = analogix_dp_prepare_panel(dp, true, false);
1116                 if (ret) {
1117                         DRM_ERROR("Failed to prepare panel (%d)\n", ret);
1118                         return 0;
1119                 }
1120
1121                 pm_runtime_get_sync(dp->dev);
1122                 edid = drm_get_edid(connector, &dp->aux.ddc);
1123                 pm_runtime_put(dp->dev);
1124                 if (edid) {
1125                         drm_connector_update_edid_property(&dp->connector,
1126                                                            edid);
1127                         num_modes += drm_add_edid_modes(&dp->connector, edid);
1128                         kfree(edid);
1129                 }
1130
1131                 ret = analogix_dp_prepare_panel(dp, false, false);
1132                 if (ret)
1133                         DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
1134         }
1135
1136         if (dp->plat_data->get_modes)
1137                 num_modes += dp->plat_data->get_modes(dp->plat_data, connector);
1138
1139         return num_modes;
1140 }
1141
1142 static struct drm_encoder *
1143 analogix_dp_best_encoder(struct drm_connector *connector)
1144 {
1145         struct analogix_dp_device *dp = to_dp(connector);
1146
1147         return dp->encoder;
1148 }
1149
1150
1151 static int analogix_dp_atomic_check(struct drm_connector *connector,
1152                                     struct drm_atomic_state *state)
1153 {
1154         struct analogix_dp_device *dp = to_dp(connector);
1155         struct drm_connector_state *conn_state;
1156         struct drm_crtc_state *crtc_state;
1157
1158         conn_state = drm_atomic_get_new_connector_state(state, connector);
1159         if (WARN_ON(!conn_state))
1160                 return -ENODEV;
1161
1162         conn_state->self_refresh_aware = true;
1163
1164         if (!conn_state->crtc)
1165                 return 0;
1166
1167         crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
1168         if (!crtc_state)
1169                 return 0;
1170
1171         if (crtc_state->self_refresh_active && !dp->psr_supported)
1172                 return -EINVAL;
1173
1174         return 0;
1175 }
1176
1177 static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
1178         .get_modes = analogix_dp_get_modes,
1179         .best_encoder = analogix_dp_best_encoder,
1180         .atomic_check = analogix_dp_atomic_check,
1181 };
1182
1183 static enum drm_connector_status
1184 analogix_dp_detect(struct drm_connector *connector, bool force)
1185 {
1186         struct analogix_dp_device *dp = to_dp(connector);
1187         enum drm_connector_status status = connector_status_disconnected;
1188         int ret;
1189
1190         if (dp->plat_data->panel)
1191                 return connector_status_connected;
1192
1193         ret = analogix_dp_prepare_panel(dp, true, false);
1194         if (ret) {
1195                 DRM_ERROR("Failed to prepare panel (%d)\n", ret);
1196                 return connector_status_disconnected;
1197         }
1198
1199         if (!analogix_dp_detect_hpd(dp))
1200                 status = connector_status_connected;
1201
1202         ret = analogix_dp_prepare_panel(dp, false, false);
1203         if (ret)
1204                 DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
1205
1206         return status;
1207 }
1208
1209 static const struct drm_connector_funcs analogix_dp_connector_funcs = {
1210         .fill_modes = drm_helper_probe_single_connector_modes,
1211         .detect = analogix_dp_detect,
1212         .destroy = drm_connector_cleanup,
1213         .reset = drm_atomic_helper_connector_reset,
1214         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1215         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1216 };
1217
1218 static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
1219 {
1220         struct analogix_dp_device *dp = bridge->driver_private;
1221         struct drm_encoder *encoder = dp->encoder;
1222         struct drm_connector *connector = NULL;
1223         int ret = 0;
1224
1225         if (!bridge->encoder) {
1226                 DRM_ERROR("Parent encoder object not found");
1227                 return -ENODEV;
1228         }
1229
1230         if (!dp->plat_data->skip_connector) {
1231                 connector = &dp->connector;
1232                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1233
1234                 ret = drm_connector_init(dp->drm_dev, connector,
1235                                          &analogix_dp_connector_funcs,
1236                                          DRM_MODE_CONNECTOR_eDP);
1237                 if (ret) {
1238                         DRM_ERROR("Failed to initialize connector with drm\n");
1239                         return ret;
1240                 }
1241
1242                 drm_connector_helper_add(connector,
1243                                          &analogix_dp_connector_helper_funcs);
1244                 drm_connector_attach_encoder(connector, encoder);
1245         }
1246
1247         /*
1248          * NOTE: the connector registration is implemented in analogix
1249          * platform driver, that to say connector would be exist after
1250          * plat_data->attch return, that's why we record the connector
1251          * point after plat attached.
1252          */
1253         if (dp->plat_data->attach) {
1254                 ret = dp->plat_data->attach(dp->plat_data, bridge, connector);
1255                 if (ret) {
1256                         DRM_ERROR("Failed at platform attach func\n");
1257                         return ret;
1258                 }
1259         }
1260
1261         if (dp->plat_data->panel) {
1262                 ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
1263                 if (ret) {
1264                         DRM_ERROR("Failed to attach panel\n");
1265                         return ret;
1266                 }
1267         }
1268
1269         return 0;
1270 }
1271
1272 static
1273 struct drm_crtc *analogix_dp_get_new_crtc(struct analogix_dp_device *dp,
1274                                           struct drm_atomic_state *state)
1275 {
1276         struct drm_encoder *encoder = dp->encoder;
1277         struct drm_connector *connector;
1278         struct drm_connector_state *conn_state;
1279
1280         connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
1281         if (!connector)
1282                 return NULL;
1283
1284         conn_state = drm_atomic_get_new_connector_state(state, connector);
1285         if (!conn_state)
1286                 return NULL;
1287
1288         return conn_state->crtc;
1289 }
1290
1291 static void analogix_dp_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1292                                                  struct drm_atomic_state *state)
1293 {
1294         struct analogix_dp_device *dp = bridge->driver_private;
1295         struct drm_crtc *crtc;
1296         struct drm_crtc_state *old_crtc_state;
1297         int ret;
1298
1299         crtc = analogix_dp_get_new_crtc(dp, state);
1300         if (!crtc)
1301                 return;
1302
1303         old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
1304         /* Don't touch the panel if we're coming back from PSR */
1305         if (old_crtc_state && old_crtc_state->self_refresh_active)
1306                 return;
1307
1308         ret = analogix_dp_prepare_panel(dp, true, true);
1309         if (ret)
1310                 DRM_ERROR("failed to setup the panel ret = %d\n", ret);
1311 }
1312
1313 static int analogix_dp_set_bridge(struct analogix_dp_device *dp)
1314 {
1315         int ret;
1316
1317         pm_runtime_get_sync(dp->dev);
1318
1319         ret = clk_prepare_enable(dp->clock);
1320         if (ret < 0) {
1321                 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1322                 goto out_dp_clk_pre;
1323         }
1324
1325         if (dp->plat_data->power_on_start)
1326                 dp->plat_data->power_on_start(dp->plat_data);
1327
1328         phy_power_on(dp->phy);
1329
1330         ret = analogix_dp_init_dp(dp);
1331         if (ret)
1332                 goto out_dp_init;
1333
1334         /*
1335          * According to DP spec v1.3 chap 3.5.1.2 Link Training,
1336          * We should first make sure the HPD signal is asserted high by device
1337          * when we want to establish a link with it.
1338          */
1339         ret = analogix_dp_detect_hpd(dp);
1340         if (ret) {
1341                 DRM_ERROR("failed to get hpd single ret = %d\n", ret);
1342                 goto out_dp_init;
1343         }
1344
1345         ret = analogix_dp_commit(dp);
1346         if (ret) {
1347                 DRM_ERROR("dp commit error, ret = %d\n", ret);
1348                 goto out_dp_init;
1349         }
1350
1351         if (dp->plat_data->power_on_end)
1352                 dp->plat_data->power_on_end(dp->plat_data);
1353
1354         enable_irq(dp->irq);
1355         return 0;
1356
1357 out_dp_init:
1358         phy_power_off(dp->phy);
1359         if (dp->plat_data->power_off)
1360                 dp->plat_data->power_off(dp->plat_data);
1361         clk_disable_unprepare(dp->clock);
1362 out_dp_clk_pre:
1363         pm_runtime_put_sync(dp->dev);
1364
1365         return ret;
1366 }
1367
1368 static void analogix_dp_bridge_atomic_enable(struct drm_bridge *bridge,
1369                                              struct drm_atomic_state *state)
1370 {
1371         struct analogix_dp_device *dp = bridge->driver_private;
1372         struct drm_crtc *crtc;
1373         struct drm_crtc_state *old_crtc_state;
1374         int timeout_loop = 0;
1375         int ret;
1376
1377         crtc = analogix_dp_get_new_crtc(dp, state);
1378         if (!crtc)
1379                 return;
1380
1381         old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
1382         /* Not a full enable, just disable PSR and continue */
1383         if (old_crtc_state && old_crtc_state->self_refresh_active) {
1384                 ret = analogix_dp_disable_psr(dp);
1385                 if (ret)
1386                         DRM_ERROR("Failed to disable psr %d\n", ret);
1387                 return;
1388         }
1389
1390         if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1391                 return;
1392
1393         while (timeout_loop < MAX_PLL_LOCK_LOOP) {
1394                 if (analogix_dp_set_bridge(dp) == 0) {
1395                         dp->dpms_mode = DRM_MODE_DPMS_ON;
1396                         return;
1397                 }
1398                 dev_err(dp->dev, "failed to set bridge, retry: %d\n",
1399                         timeout_loop);
1400                 timeout_loop++;
1401                 usleep_range(10, 11);
1402         }
1403         dev_err(dp->dev, "too many times retry set bridge, give it up\n");
1404 }
1405
1406 static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
1407 {
1408         struct analogix_dp_device *dp = bridge->driver_private;
1409         int ret;
1410
1411         if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1412                 return;
1413
1414         if (dp->plat_data->panel) {
1415                 if (drm_panel_disable(dp->plat_data->panel)) {
1416                         DRM_ERROR("failed to disable the panel\n");
1417                         return;
1418                 }
1419         }
1420
1421         disable_irq(dp->irq);
1422
1423         if (dp->plat_data->power_off)
1424                 dp->plat_data->power_off(dp->plat_data);
1425
1426         analogix_dp_set_analog_power_down(dp, POWER_ALL, 1);
1427         phy_power_off(dp->phy);
1428
1429         clk_disable_unprepare(dp->clock);
1430
1431         pm_runtime_put_sync(dp->dev);
1432
1433         ret = analogix_dp_prepare_panel(dp, false, true);
1434         if (ret)
1435                 DRM_ERROR("failed to setup the panel ret = %d\n", ret);
1436
1437         dp->fast_train_enable = false;
1438         dp->psr_supported = false;
1439         dp->dpms_mode = DRM_MODE_DPMS_OFF;
1440 }
1441
1442 static void analogix_dp_bridge_atomic_disable(struct drm_bridge *bridge,
1443                                               struct drm_atomic_state *state)
1444 {
1445         struct analogix_dp_device *dp = bridge->driver_private;
1446         struct drm_crtc *crtc;
1447         struct drm_crtc_state *new_crtc_state = NULL;
1448
1449         crtc = analogix_dp_get_new_crtc(dp, state);
1450         if (!crtc)
1451                 goto out;
1452
1453         new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1454         if (!new_crtc_state)
1455                 goto out;
1456
1457         /* Don't do a full disable on PSR transitions */
1458         if (new_crtc_state->self_refresh_active)
1459                 return;
1460
1461 out:
1462         analogix_dp_bridge_disable(bridge);
1463 }
1464
1465 static
1466 void analogix_dp_bridge_atomic_post_disable(struct drm_bridge *bridge,
1467                                             struct drm_atomic_state *state)
1468 {
1469         struct analogix_dp_device *dp = bridge->driver_private;
1470         struct drm_crtc *crtc;
1471         struct drm_crtc_state *new_crtc_state;
1472         int ret;
1473
1474         crtc = analogix_dp_get_new_crtc(dp, state);
1475         if (!crtc)
1476                 return;
1477
1478         new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1479         if (!new_crtc_state || !new_crtc_state->self_refresh_active)
1480                 return;
1481
1482         ret = analogix_dp_enable_psr(dp);
1483         if (ret)
1484                 DRM_ERROR("Failed to enable psr (%d)\n", ret);
1485 }
1486
1487 static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
1488                                 const struct drm_display_mode *orig_mode,
1489                                 const struct drm_display_mode *mode)
1490 {
1491         struct analogix_dp_device *dp = bridge->driver_private;
1492         struct drm_display_info *display_info = &dp->connector.display_info;
1493         struct video_info *video = &dp->video_info;
1494         struct device_node *dp_node = dp->dev->of_node;
1495         int vic;
1496
1497         /* Input video interlaces & hsync pol & vsync pol */
1498         video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1499         video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
1500         video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
1501
1502         /* Input video dynamic_range & colorimetry */
1503         vic = drm_match_cea_mode(mode);
1504         if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
1505             (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
1506                 video->dynamic_range = CEA;
1507                 video->ycbcr_coeff = COLOR_YCBCR601;
1508         } else if (vic) {
1509                 video->dynamic_range = CEA;
1510                 video->ycbcr_coeff = COLOR_YCBCR709;
1511         } else {
1512                 video->dynamic_range = VESA;
1513                 video->ycbcr_coeff = COLOR_YCBCR709;
1514         }
1515
1516         /* Input vide bpc and color_formats */
1517         switch (display_info->bpc) {
1518         case 12:
1519                 video->color_depth = COLOR_12;
1520                 break;
1521         case 10:
1522                 video->color_depth = COLOR_10;
1523                 break;
1524         case 8:
1525                 video->color_depth = COLOR_8;
1526                 break;
1527         case 6:
1528                 video->color_depth = COLOR_6;
1529                 break;
1530         default:
1531                 video->color_depth = COLOR_8;
1532                 break;
1533         }
1534         if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
1535                 video->color_space = COLOR_YCBCR444;
1536         else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
1537                 video->color_space = COLOR_YCBCR422;
1538         else
1539                 video->color_space = COLOR_RGB;
1540
1541         /*
1542          * NOTE: those property parsing code is used for providing backward
1543          * compatibility for samsung platform.
1544          * Due to we used the "of_property_read_u32" interfaces, when this
1545          * property isn't present, the "video_info" can keep the original
1546          * values and wouldn't be modified.
1547          */
1548         of_property_read_u32(dp_node, "samsung,color-space",
1549                              &video->color_space);
1550         of_property_read_u32(dp_node, "samsung,dynamic-range",
1551                              &video->dynamic_range);
1552         of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
1553                              &video->ycbcr_coeff);
1554         of_property_read_u32(dp_node, "samsung,color-depth",
1555                              &video->color_depth);
1556         if (of_property_read_bool(dp_node, "hsync-active-high"))
1557                 video->h_sync_polarity = true;
1558         if (of_property_read_bool(dp_node, "vsync-active-high"))
1559                 video->v_sync_polarity = true;
1560         if (of_property_read_bool(dp_node, "interlaced"))
1561                 video->interlaced = true;
1562 }
1563
1564 static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
1565         .atomic_pre_enable = analogix_dp_bridge_atomic_pre_enable,
1566         .atomic_enable = analogix_dp_bridge_atomic_enable,
1567         .atomic_disable = analogix_dp_bridge_atomic_disable,
1568         .atomic_post_disable = analogix_dp_bridge_atomic_post_disable,
1569         .mode_set = analogix_dp_bridge_mode_set,
1570         .attach = analogix_dp_bridge_attach,
1571 };
1572
1573 static int analogix_dp_create_bridge(struct drm_device *drm_dev,
1574                                      struct analogix_dp_device *dp)
1575 {
1576         struct drm_bridge *bridge;
1577         int ret;
1578
1579         bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
1580         if (!bridge) {
1581                 DRM_ERROR("failed to allocate for drm bridge\n");
1582                 return -ENOMEM;
1583         }
1584
1585         dp->bridge = bridge;
1586
1587         bridge->driver_private = dp;
1588         bridge->funcs = &analogix_dp_bridge_funcs;
1589
1590         ret = drm_bridge_attach(dp->encoder, bridge, NULL);
1591         if (ret) {
1592                 DRM_ERROR("failed to attach drm bridge\n");
1593                 return -EINVAL;
1594         }
1595
1596         return 0;
1597 }
1598
1599 static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
1600 {
1601         struct device_node *dp_node = dp->dev->of_node;
1602         struct video_info *video_info = &dp->video_info;
1603
1604         switch (dp->plat_data->dev_type) {
1605         case RK3288_DP:
1606         case RK3399_EDP:
1607                 /*
1608                  * Like Rk3288 DisplayPort TRM indicate that "Main link
1609                  * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
1610                  */
1611                 video_info->max_link_rate = 0x0A;
1612                 video_info->max_lane_count = 0x04;
1613                 break;
1614         case EXYNOS_DP:
1615                 /*
1616                  * NOTE: those property parseing code is used for
1617                  * providing backward compatibility for samsung platform.
1618                  */
1619                 of_property_read_u32(dp_node, "samsung,link-rate",
1620                                      &video_info->max_link_rate);
1621                 of_property_read_u32(dp_node, "samsung,lane-count",
1622                                      &video_info->max_lane_count);
1623                 break;
1624         }
1625
1626         return 0;
1627 }
1628
1629 static ssize_t analogix_dpaux_transfer(struct drm_dp_aux *aux,
1630                                        struct drm_dp_aux_msg *msg)
1631 {
1632         struct analogix_dp_device *dp = to_dp(aux);
1633
1634         return analogix_dp_transfer(dp, msg);
1635 }
1636
1637 struct analogix_dp_device *
1638 analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
1639                  struct analogix_dp_plat_data *plat_data)
1640 {
1641         struct platform_device *pdev = to_platform_device(dev);
1642         struct analogix_dp_device *dp;
1643         struct resource *res;
1644         unsigned int irq_flags;
1645         int ret;
1646
1647         if (!plat_data) {
1648                 dev_err(dev, "Invalided input plat_data\n");
1649                 return ERR_PTR(-EINVAL);
1650         }
1651
1652         dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
1653         if (!dp)
1654                 return ERR_PTR(-ENOMEM);
1655
1656         dp->dev = &pdev->dev;
1657         dp->dpms_mode = DRM_MODE_DPMS_OFF;
1658
1659         mutex_init(&dp->panel_lock);
1660         dp->panel_is_modeset = false;
1661
1662         /*
1663          * platform dp driver need containor_of the plat_data to get
1664          * the driver private data, so we need to store the point of
1665          * plat_data, not the context of plat_data.
1666          */
1667         dp->plat_data = plat_data;
1668
1669         ret = analogix_dp_dt_parse_pdata(dp);
1670         if (ret)
1671                 return ERR_PTR(ret);
1672
1673         dp->phy = devm_phy_get(dp->dev, "dp");
1674         if (IS_ERR(dp->phy)) {
1675                 dev_err(dp->dev, "no DP phy configured\n");
1676                 ret = PTR_ERR(dp->phy);
1677                 if (ret) {
1678                         /*
1679                          * phy itself is not enabled, so we can move forward
1680                          * assigning NULL to phy pointer.
1681                          */
1682                         if (ret == -ENOSYS || ret == -ENODEV)
1683                                 dp->phy = NULL;
1684                         else
1685                                 return ERR_PTR(ret);
1686                 }
1687         }
1688
1689         dp->clock = devm_clk_get(&pdev->dev, "dp");
1690         if (IS_ERR(dp->clock)) {
1691                 dev_err(&pdev->dev, "failed to get clock\n");
1692                 return ERR_CAST(dp->clock);
1693         }
1694
1695         clk_prepare_enable(dp->clock);
1696
1697         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1698
1699         dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
1700         if (IS_ERR(dp->reg_base))
1701                 return ERR_CAST(dp->reg_base);
1702
1703         dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd");
1704
1705         /* Try two different names */
1706         dp->hpd_gpiod = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
1707         if (!dp->hpd_gpiod)
1708                 dp->hpd_gpiod = devm_gpiod_get_optional(dev, "samsung,hpd",
1709                                                         GPIOD_IN);
1710         if (IS_ERR(dp->hpd_gpiod)) {
1711                 dev_err(dev, "error getting HDP GPIO: %ld\n",
1712                         PTR_ERR(dp->hpd_gpiod));
1713                 return ERR_CAST(dp->hpd_gpiod);
1714         }
1715
1716         if (dp->hpd_gpiod) {
1717                 /*
1718                  * Set up the hotplug GPIO from the device tree as an interrupt.
1719                  * Simply specifying a different interrupt in the device tree
1720                  * doesn't work since we handle hotplug rather differently when
1721                  * using a GPIO.  We also need the actual GPIO specifier so
1722                  * that we can get the current state of the GPIO.
1723                  */
1724                 dp->irq = gpiod_to_irq(dp->hpd_gpiod);
1725                 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1726         } else {
1727                 dp->irq = platform_get_irq(pdev, 0);
1728                 irq_flags = 0;
1729         }
1730
1731         if (dp->irq == -ENXIO) {
1732                 dev_err(&pdev->dev, "failed to get irq\n");
1733                 return ERR_PTR(-ENODEV);
1734         }
1735
1736         ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
1737                                         analogix_dp_hardirq,
1738                                         analogix_dp_irq_thread,
1739                                         irq_flags, "analogix-dp", dp);
1740         if (ret) {
1741                 dev_err(&pdev->dev, "failed to request irq\n");
1742                 goto err_disable_pm_runtime;
1743         }
1744         disable_irq(dp->irq);
1745
1746         dp->drm_dev = drm_dev;
1747         dp->encoder = dp->plat_data->encoder;
1748
1749         dp->aux.name = "DP-AUX";
1750         dp->aux.transfer = analogix_dpaux_transfer;
1751         dp->aux.dev = &pdev->dev;
1752
1753         ret = drm_dp_aux_register(&dp->aux);
1754         if (ret)
1755                 return ERR_PTR(ret);
1756
1757         pm_runtime_enable(dev);
1758
1759         ret = analogix_dp_create_bridge(drm_dev, dp);
1760         if (ret) {
1761                 DRM_ERROR("failed to create bridge (%d)\n", ret);
1762                 goto err_disable_pm_runtime;
1763         }
1764
1765         return dp;
1766
1767 err_disable_pm_runtime:
1768
1769         pm_runtime_disable(dev);
1770
1771         return ERR_PTR(ret);
1772 }
1773 EXPORT_SYMBOL_GPL(analogix_dp_bind);
1774
1775 void analogix_dp_unbind(struct analogix_dp_device *dp)
1776 {
1777         analogix_dp_bridge_disable(dp->bridge);
1778         dp->connector.funcs->destroy(&dp->connector);
1779
1780         if (dp->plat_data->panel) {
1781                 if (drm_panel_unprepare(dp->plat_data->panel))
1782                         DRM_ERROR("failed to turnoff the panel\n");
1783                 drm_panel_detach(dp->plat_data->panel);
1784         }
1785
1786         drm_dp_aux_unregister(&dp->aux);
1787         pm_runtime_disable(dp->dev);
1788         clk_disable_unprepare(dp->clock);
1789 }
1790 EXPORT_SYMBOL_GPL(analogix_dp_unbind);
1791
1792 #ifdef CONFIG_PM
1793 int analogix_dp_suspend(struct analogix_dp_device *dp)
1794 {
1795         clk_disable_unprepare(dp->clock);
1796
1797         if (dp->plat_data->panel) {
1798                 if (drm_panel_unprepare(dp->plat_data->panel))
1799                         DRM_ERROR("failed to turnoff the panel\n");
1800         }
1801
1802         return 0;
1803 }
1804 EXPORT_SYMBOL_GPL(analogix_dp_suspend);
1805
1806 int analogix_dp_resume(struct analogix_dp_device *dp)
1807 {
1808         int ret;
1809
1810         ret = clk_prepare_enable(dp->clock);
1811         if (ret < 0) {
1812                 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1813                 return ret;
1814         }
1815
1816         if (dp->plat_data->panel) {
1817                 if (drm_panel_prepare(dp->plat_data->panel)) {
1818                         DRM_ERROR("failed to setup the panel\n");
1819                         return -EBUSY;
1820                 }
1821         }
1822
1823         return 0;
1824 }
1825 EXPORT_SYMBOL_GPL(analogix_dp_resume);
1826 #endif
1827
1828 int analogix_dp_start_crc(struct drm_connector *connector)
1829 {
1830         struct analogix_dp_device *dp = to_dp(connector);
1831
1832         if (!connector->state->crtc) {
1833                 DRM_ERROR("Connector %s doesn't currently have a CRTC.\n",
1834                           connector->name);
1835                 return -EINVAL;
1836         }
1837
1838         return drm_dp_start_crc(&dp->aux, connector->state->crtc);
1839 }
1840 EXPORT_SYMBOL_GPL(analogix_dp_start_crc);
1841
1842 int analogix_dp_stop_crc(struct drm_connector *connector)
1843 {
1844         struct analogix_dp_device *dp = to_dp(connector);
1845
1846         return drm_dp_stop_crc(&dp->aux);
1847 }
1848 EXPORT_SYMBOL_GPL(analogix_dp_stop_crc);
1849
1850 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1851 MODULE_DESCRIPTION("Analogix DP Core Driver");
1852 MODULE_LICENSE("GPL v2");