2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
26 * Authors: Dave Airlie <airlied@redhat.com>
31 #include <linux/i2c.h>
32 #include <linux/i2c-algo-bit.h>
34 #include <linux/types.h>
36 #include <drm/drm_connector.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_mode.h>
40 #include <drm/drm_framebuffer.h>
41 #include <drm/drm_fb_helper.h>
43 #define DRIVER_AUTHOR "Dave Airlie"
45 #define DRIVER_NAME "ast"
46 #define DRIVER_DESC "AST"
47 #define DRIVER_DATE "20120228"
49 #define DRIVER_MAJOR 0
50 #define DRIVER_MINOR 1
51 #define DRIVER_PATCHLEVEL 0
53 #define PCI_CHIP_AST2000 0x2000
54 #define PCI_CHIP_AST2100 0x2010
76 #define AST_DRAM_512Mx16 0
77 #define AST_DRAM_1Gx16 1
78 #define AST_DRAM_512Mx32 2
79 #define AST_DRAM_1Gx32 3
80 #define AST_DRAM_2Gx16 6
81 #define AST_DRAM_4Gx16 7
82 #define AST_DRAM_8Gx16 8
88 #define AST_MAX_HWC_WIDTH 64
89 #define AST_MAX_HWC_HEIGHT 64
91 #define AST_HWC_SIZE (AST_MAX_HWC_WIDTH * AST_MAX_HWC_HEIGHT * 2)
92 #define AST_HWC_SIGNATURE_SIZE 32
94 #define AST_DEFAULT_HWC_NUM 2
96 /* define for signature structure */
97 #define AST_HWC_SIGNATURE_CHECKSUM 0x00
98 #define AST_HWC_SIGNATURE_SizeX 0x04
99 #define AST_HWC_SIGNATURE_SizeY 0x08
100 #define AST_HWC_SIGNATURE_X 0x0C
101 #define AST_HWC_SIGNATURE_Y 0x10
102 #define AST_HWC_SIGNATURE_HOTSPOTX 0x14
103 #define AST_HWC_SIGNATURE_HOTSPOTY 0x18
105 struct ast_cursor_plane {
106 struct drm_plane base;
109 struct drm_gem_vram_object *gbo;
110 } hwc[AST_DEFAULT_HWC_NUM];
112 unsigned int next_hwc_index;
115 static inline struct ast_cursor_plane *
116 to_ast_cursor_plane(struct drm_plane *plane)
118 return container_of(plane, struct ast_cursor_plane, base);
122 * Connector with i2c channel
125 struct ast_i2c_chan {
126 struct i2c_adapter adapter;
127 struct drm_device *dev;
128 struct i2c_algo_bit_data bit;
131 struct ast_connector {
132 struct drm_connector base;
133 struct ast_i2c_chan *i2c;
136 static inline struct ast_connector *
137 to_ast_connector(struct drm_connector *connector)
139 return container_of(connector, struct ast_connector, base);
147 struct drm_device base;
150 void __iomem *ioregs;
154 uint32_t dram_bus_width;
160 struct drm_plane primary_plane;
161 struct ast_cursor_plane cursor_plane;
162 struct drm_crtc crtc;
163 struct drm_encoder encoder;
164 struct ast_connector connector;
166 bool support_wide_screen;
173 enum ast_tx_chip tx_chip_type;
176 const struct firmware *dp501_fw; /* dp501 fw */
179 static inline struct ast_private *to_ast_private(struct drm_device *dev)
181 return container_of(dev, struct ast_private, base);
184 struct ast_private *ast_device_create(const struct drm_driver *drv,
185 struct pci_dev *pdev,
186 unsigned long flags);
188 #define AST_IO_AR_PORT_WRITE (0x40)
189 #define AST_IO_MISC_PORT_WRITE (0x42)
190 #define AST_IO_VGA_ENABLE_PORT (0x43)
191 #define AST_IO_SEQ_PORT (0x44)
192 #define AST_IO_DAC_INDEX_READ (0x47)
193 #define AST_IO_DAC_INDEX_WRITE (0x48)
194 #define AST_IO_DAC_DATA (0x49)
195 #define AST_IO_GR_PORT (0x4E)
196 #define AST_IO_CRTC_PORT (0x54)
197 #define AST_IO_INPUT_STATUS1_READ (0x5A)
198 #define AST_IO_MISC_PORT_READ (0x4C)
200 #define AST_IO_MM_OFFSET (0x380)
202 #define AST_IO_VGAIR1_VREFRESH BIT(3)
204 #define AST_IO_VGACRCB_HWC_ENABLED BIT(1)
205 #define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */
207 #define __ast_read(x) \
208 static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \
210 val = ioread##x(ast->regs + reg); \
218 #define __ast_io_read(x) \
219 static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \
221 val = ioread##x(ast->ioregs + reg); \
229 #define __ast_write(x) \
230 static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\
231 iowrite##x(val, ast->regs + reg);\
238 #define __ast_io_write(x) \
239 static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\
240 iowrite##x(val, ast->ioregs + reg);\
245 #undef __ast_io_write
247 static inline void ast_set_index_reg(struct ast_private *ast,
248 uint32_t base, uint8_t index,
251 ast_io_write16(ast, base, ((u16)val << 8) | index);
254 void ast_set_index_reg_mask(struct ast_private *ast,
255 uint32_t base, uint8_t index,
256 uint8_t mask, uint8_t val);
257 uint8_t ast_get_index_reg(struct ast_private *ast,
258 uint32_t base, uint8_t index);
259 uint8_t ast_get_index_reg_mask(struct ast_private *ast,
260 uint32_t base, uint8_t index, uint8_t mask);
262 static inline void ast_open_key(struct ast_private *ast)
264 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8);
267 #define AST_VIDMEM_SIZE_8M 0x00800000
268 #define AST_VIDMEM_SIZE_16M 0x01000000
269 #define AST_VIDMEM_SIZE_32M 0x02000000
270 #define AST_VIDMEM_SIZE_64M 0x04000000
271 #define AST_VIDMEM_SIZE_128M 0x08000000
273 #define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M
275 struct ast_vbios_stdtable {
283 struct ast_vbios_enhtable {
295 u32 refresh_rate_index;
299 struct ast_vbios_dclk_info {
305 struct ast_vbios_mode_info {
306 const struct ast_vbios_stdtable *std_table;
307 const struct ast_vbios_enhtable *enh_table;
310 struct ast_crtc_state {
311 struct drm_crtc_state base;
313 /* Last known format of primary plane */
314 const struct drm_format_info *format;
316 struct ast_vbios_mode_info vbios_mode_info;
319 #define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base)
321 int ast_mode_config_init(struct ast_private *ast);
323 #define AST_MM_ALIGN_SHIFT 4
324 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1)
326 int ast_mm_init(struct ast_private *ast);
329 void ast_enable_vga(struct drm_device *dev);
330 void ast_enable_mmio(struct drm_device *dev);
331 bool ast_is_vga_enabled(struct drm_device *dev);
332 void ast_post_gpu(struct drm_device *dev);
333 u32 ast_mindwm(struct ast_private *ast, u32 r);
334 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v);
336 void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
337 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
338 bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata);
339 u8 ast_get_dp501_max_clk(struct drm_device *dev);
340 void ast_init_3rdtx(struct drm_device *dev);