drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "hwmgr.h"
  24 #include "pp_debug.h"
  25 #include "ppatomctrl.h"
  26 #include "ppsmc.h"
  27 #include "atom.h"
  28
  29 uint8_t convert_to_vid(uint16_t vddc)
  30 {
  31         return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
  32 }
  33
  34 uint16_t convert_to_vddc(uint8_t vid)
  35 {
  36         return (uint16_t) ((6200 - (vid * 25)) / VOLTAGE_SCALE);
  37 }
  38
  39 uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size)
  40 {
  41         u32 mask = 0;
  42         u32 shift = 0;
  43
  44         shift = (offset % 4) << 3;
  45         if (size == sizeof(uint8_t))
  46                 mask = 0xFF << shift;
  47         else if (size == sizeof(uint16_t))
  48                 mask = 0xFFFF << shift;
  49
  50         original_data &= ~mask;
  51         original_data |= (field << shift);
  52         return original_data;
  53 }
  54
  55 /**
  56  * Returns once the part of the register indicated by the mask has
  57  * reached the given value.
  58  */
  59 int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
  60                          uint32_t value, uint32_t mask)
  61 {
  62         uint32_t i;
  63         uint32_t cur_value;
  64
  65         if (hwmgr == NULL || hwmgr->device == NULL) {
  66                 pr_err("Invalid Hardware Manager!");
  67                 return -EINVAL;
  68         }
  69
  70         for (i = 0; i < hwmgr->usec_timeout; i++) {
  71                 cur_value = cgs_read_register(hwmgr->device, index);
  72                 if ((cur_value & mask) == (value & mask))
  73                         break;
  74                 udelay(1);
  75         }
  76
  77         /* timeout means wrong logic*/
  78         if (i == hwmgr->usec_timeout)
  79                 return -1;
  80         return 0;
  81 }
  82
  83
  84 /**
  85  * Returns once the part of the register indicated by the mask has
  86  * reached the given value.The indirect space is described by giving
  87  * the memory-mapped index of the indirect index register.
  88  */
  89 int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
  90                                 uint32_t indirect_port,
  91                                 uint32_t index,
  92                                 uint32_t value,
  93                                 uint32_t mask)
  94 {
  95         if (hwmgr == NULL || hwmgr->device == NULL) {
  96                 pr_err("Invalid Hardware Manager!");
  97                 return -EINVAL;
  98         }
  99
 100         cgs_write_register(hwmgr->device, indirect_port, index);
 101         return phm_wait_on_register(hwmgr, indirect_port + 1, mask, value);
 102 }
 103
 104 int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
 105                                         uint32_t index,
 106                                         uint32_t value, uint32_t mask)
 107 {
 108         uint32_t i;
 109         uint32_t cur_value;
 110
 111         if (hwmgr == NULL || hwmgr->device == NULL)
 112                 return -EINVAL;
 113
 114         for (i = 0; i < hwmgr->usec_timeout; i++) {
 115                 cur_value = cgs_read_register(hwmgr->device,
 116                                                                         index);
 117                 if ((cur_value & mask) != (value & mask))
 118                         break;
 119                 udelay(1);
 120         }
 121
 122         /* timeout means wrong logic */
 123         if (i == hwmgr->usec_timeout)
 124                 return -ETIME;
 125         return 0;
 126 }
 127
 128 int phm_wait_for_indirect_register_unequal(struct pp_hwmgr *hwmgr,
 129                                                 uint32_t indirect_port,
 130                                                 uint32_t index,
 131                                                 uint32_t value,
 132                                                 uint32_t mask)
 133 {
 134         if (hwmgr == NULL || hwmgr->device == NULL)
 135                 return -EINVAL;
 136
 137         cgs_write_register(hwmgr->device, indirect_port, index);
 138         return phm_wait_for_register_unequal(hwmgr, indirect_port + 1,
 139                                                 value, mask);
 140 }
 141
 142 bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr)
 143 {
 144         return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDPowerGating);
 145 }
 146
 147 bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr)
 148 {
 149         return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEPowerGating);
 150 }
 151
 152
 153 int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table)
 154 {
 155         uint32_t i, j;
 156         uint16_t vvalue;
 157         bool found = false;
 158         struct pp_atomctrl_voltage_table *table;
 159
 160         PP_ASSERT_WITH_CODE((NULL != vol_table),
 161                         "Voltage Table empty.", return -EINVAL);
 162
 163         table = kzalloc(sizeof(struct pp_atomctrl_voltage_table),
 164                         GFP_KERNEL);
 165
 166         if (NULL == table)
 167                 return -EINVAL;
 168
 169         table->mask_low = vol_table->mask_low;
 170         table->phase_delay = vol_table->phase_delay;
 171
 172         for (i = 0; i < vol_table->count; i++) {
 173                 vvalue = vol_table->entries[i].value;
 174                 found = false;
 175
 176                 for (j = 0; j < table->count; j++) {
 177                         if (vvalue == table->entries[j].value) {
 178                                 found = true;
 179                                 break;
 180                         }
 181                 }
 182
 183                 if (!found) {
 184                         table->entries[table->count].value = vvalue;
 185                         table->entries[table->count].smio_low =
 186                                         vol_table->entries[i].smio_low;
 187                         table->count++;
 188                 }
 189         }
 190
 191         memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table));
 192         kfree(table);
 193         table = NULL;
 194         return 0;
 195 }
 196
 197 int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
 198                 phm_ppt_v1_clock_voltage_dependency_table *dep_table)
 199 {
 200         uint32_t i;
 201         int result;
 202
 203         PP_ASSERT_WITH_CODE((0 != dep_table->count),
 204                         "Voltage Dependency Table empty.", return -EINVAL);
 205
 206         PP_ASSERT_WITH_CODE((NULL != vol_table),
 207                         "vol_table empty.", return -EINVAL);
 208
 209         vol_table->mask_low = 0;
 210         vol_table->phase_delay = 0;
 211         vol_table->count = dep_table->count;
 212
 213         for (i = 0; i < dep_table->count; i++) {
 214                 vol_table->entries[i].value = dep_table->entries[i].mvdd;
 215                 vol_table->entries[i].smio_low = 0;
 216         }
 217
 218         result = phm_trim_voltage_table(vol_table);
 219         PP_ASSERT_WITH_CODE((0 == result),
 220                         "Failed to trim MVDD table.", return result);
 221
 222         return 0;
 223 }
 224
 225 int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
 226                 phm_ppt_v1_clock_voltage_dependency_table *dep_table)
 227 {
 228         uint32_t i;
 229         int result;
 230
 231         PP_ASSERT_WITH_CODE((0 != dep_table->count),
 232                         "Voltage Dependency Table empty.", return -EINVAL);
 233
 234         PP_ASSERT_WITH_CODE((NULL != vol_table),
 235                         "vol_table empty.", return -EINVAL);
 236
 237         vol_table->mask_low = 0;
 238         vol_table->phase_delay = 0;
 239         vol_table->count = dep_table->count;
 240
 241         for (i = 0; i < dep_table->count; i++) {
 242                 vol_table->entries[i].value = dep_table->entries[i].vddci;
 243                 vol_table->entries[i].smio_low = 0;
 244         }
 245
 246         result = phm_trim_voltage_table(vol_table);
 247         PP_ASSERT_WITH_CODE((0 == result),
 248                         "Failed to trim VDDCI table.", return result);
 249
 250         return 0;
 251 }
 252
 253 int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table,
 254                 phm_ppt_v1_voltage_lookup_table *lookup_table)
 255 {
 256         int i = 0;
 257
 258         PP_ASSERT_WITH_CODE((0 != lookup_table->count),
 259                         "Voltage Lookup Table empty.", return -EINVAL);
 260
 261         PP_ASSERT_WITH_CODE((NULL != vol_table),
 262                         "vol_table empty.", return -EINVAL);
 263
 264         vol_table->mask_low = 0;
 265         vol_table->phase_delay = 0;
 266
 267         vol_table->count = lookup_table->count;
 268
 269         for (i = 0; i < vol_table->count; i++) {
 270                 vol_table->entries[i].value = lookup_table->entries[i].us_vdd;
 271                 vol_table->entries[i].smio_low = 0;
 272         }
 273
 274         return 0;
 275 }
 276
 277 void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps,
 278                                 struct pp_atomctrl_voltage_table *vol_table)
 279 {
 280         unsigned int i, diff;
 281
 282         if (vol_table->count <= max_vol_steps)
 283                 return;
 284
 285         diff = vol_table->count - max_vol_steps;
 286
 287         for (i = 0; i < max_vol_steps; i++)
 288                 vol_table->entries[i] = vol_table->entries[i + diff];
 289
 290         vol_table->count = max_vol_steps;
 291
 292         return;
 293 }
 294
 295 int phm_reset_single_dpm_table(void *table,
 296                                 uint32_t count, int max)
 297 {
 298         int i;
 299
 300         struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
 301
 302         dpm_table->count = count > max ? max : count;
 303
 304         for (i = 0; i < dpm_table->count; i++)
 305                 dpm_table->dpm_level[i].enabled = false;
 306
 307         return 0;
 308 }
 309
 310 void phm_setup_pcie_table_entry(
 311         void *table,
 312         uint32_t index, uint32_t pcie_gen,
 313         uint32_t pcie_lanes)
 314 {
 315         struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
 316         dpm_table->dpm_level[index].value = pcie_gen;
 317         dpm_table->dpm_level[index].param1 = pcie_lanes;
 318         dpm_table->dpm_level[index].enabled = 1;
 319 }
 320
 321 int32_t phm_get_dpm_level_enable_mask_value(void *table)
 322 {
 323         int32_t i;
 324         int32_t mask = 0;
 325         struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
 326
 327         for (i = dpm_table->count; i > 0; i--) {
 328                 mask = mask << 1;
 329                 if (dpm_table->dpm_level[i - 1].enabled)
 330                         mask |= 0x1;
 331                 else
 332                         mask &= 0xFFFFFFFE;
 333         }
 334
 335         return mask;
 336 }
 337
 338 uint8_t phm_get_voltage_index(
 339                 struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage)
 340 {
 341         uint8_t count = (uint8_t) (lookup_table->count);
 342         uint8_t i;
 343
 344         PP_ASSERT_WITH_CODE((NULL != lookup_table),
 345                         "Lookup Table empty.", return 0);
 346         PP_ASSERT_WITH_CODE((0 != count),
 347                         "Lookup Table empty.", return 0);
 348
 349         for (i = 0; i < lookup_table->count; i++) {
 350                 /* find first voltage equal or bigger than requested */
 351                 if (lookup_table->entries[i].us_vdd >= voltage)
 352                         return i;
 353         }
 354         /* voltage is bigger than max voltage in the table */
 355         return i - 1;
 356 }
 357
 358 uint8_t phm_get_voltage_id(pp_atomctrl_voltage_table *voltage_table,
 359                 uint32_t voltage)
 360 {
 361         uint8_t count = (uint8_t) (voltage_table->count);
 362         uint8_t i = 0;
 363
 364         PP_ASSERT_WITH_CODE((NULL != voltage_table),
 365                 "Voltage Table empty.", return 0;);
 366         PP_ASSERT_WITH_CODE((0 != count),
 367                 "Voltage Table empty.", return 0;);
 368
 369         for (i = 0; i < count; i++) {
 370                 /* find first voltage bigger than requested */
 371                 if (voltage_table->entries[i].value >= voltage)
 372                         return i;
 373         }
 374
 375         /* voltage is bigger than max voltage in the table */
 376         return i - 1;
 377 }
 378
 379 uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci)
 380 {
 381         uint32_t  i;
 382
 383         for (i = 0; i < vddci_table->count; i++) {
 384                 if (vddci_table->entries[i].value >= vddci)
 385                         return vddci_table->entries[i].value;
 386         }
 387
 388         pr_debug("vddci is larger than max value in vddci_table\n");
 389         return vddci_table->entries[i-1].value;
 390 }
 391
 392 int phm_find_boot_level(void *table,
 393                 uint32_t value, uint32_t *boot_level)
 394 {
 395         int result = -EINVAL;
 396         uint32_t i;
 397         struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table;
 398
 399         for (i = 0; i < dpm_table->count; i++) {
 400                 if (value == dpm_table->dpm_level[i].value) {
 401                         *boot_level = i;
 402                         result = 0;
 403                 }
 404         }
 405
 406         return result;
 407 }
 408
 409 int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
 410         phm_ppt_v1_voltage_lookup_table *lookup_table,
 411         uint16_t virtual_voltage_id, int32_t *sclk)
 412 {
 413         uint8_t entry_id;
 414         uint8_t voltage_id;
 415         struct phm_ppt_v1_information *table_info =
 416                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 417
 418         PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL);
 419
 420         /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
 421         for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) {
 422                 voltage_id = table_info->vdd_dep_on_sclk->entries[entry_id].vddInd;
 423                 if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id)
 424                         break;
 425         }
 426
 427         if (entry_id >= table_info->vdd_dep_on_sclk->count) {
 428                 pr_debug("Can't find requested voltage id in vdd_dep_on_sclk table\n");
 429                 return -EINVAL;
 430         }
 431
 432         *sclk = table_info->vdd_dep_on_sclk->entries[entry_id].clk;
 433
 434         return 0;
 435 }
 436
 437 /**
 438  * Initialize Dynamic State Adjustment Rule Settings
 439  *
 440  * @param    hwmgr  the address of the powerplay hardware manager.
 441  */
 442 int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr)
 443 {
 444         uint32_t table_size;
 445         struct phm_clock_voltage_dependency_table *table_clk_vlt;
 446         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
 447
 448         /* initialize vddc_dep_on_dal_pwrl table */
 449         table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record);
 450         table_clk_vlt = kzalloc(table_size, GFP_KERNEL);
 451
 452         if (NULL == table_clk_vlt) {
 453                 pr_err("Can not allocate space for vddc_dep_on_dal_pwrl! \n");
 454                 return -ENOMEM;
 455         } else {
 456                 table_clk_vlt->count = 4;
 457                 table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW;
 458                 table_clk_vlt->entries[0].v = 0;
 459                 table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW;
 460                 table_clk_vlt->entries[1].v = 720;
 461                 table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL;
 462                 table_clk_vlt->entries[2].v = 810;
 463                 table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE;
 464                 table_clk_vlt->entries[3].v = 900;
 465                 if (pptable_info != NULL)
 466                         pptable_info->vddc_dep_on_dal_pwrl = table_clk_vlt;
 467                 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
 468         }
 469
 470         return 0;
 471 }
 472
 473 uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask)
 474 {
 475         uint32_t level = 0;
 476
 477         while (0 == (mask & (1 << level)))
 478                 level++;
 479
 480         return level;
 481 }
 482
 483 void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
 484 {
 485         struct phm_ppt_v1_information *table_info =
 486                         (struct phm_ppt_v1_information *)hwmgr->pptable;
 487         struct phm_clock_voltage_dependency_table *table =
 488                                 table_info->vddc_dep_on_dal_pwrl;
 489         struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
 490         enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
 491         uint32_t req_vddc = 0, req_volt, i;
 492
 493         if (!table || table->count <= 0
 494                 || dal_power_level < PP_DAL_POWERLEVEL_ULTRALOW
 495                 || dal_power_level > PP_DAL_POWERLEVEL_PERFORMANCE)
 496                 return;
 497
 498         for (i = 0; i < table->count; i++) {
 499                 if (dal_power_level == table->entries[i].clk) {
 500                         req_vddc = table->entries[i].v;
 501                         break;
 502                 }
 503         }
 504
 505         vddc_table = table_info->vdd_dep_on_sclk;
 506         for (i = 0; i < vddc_table->count; i++) {
 507                 if (req_vddc <= vddc_table->entries[i].vddc) {
 508                         req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE);
 509                         smum_send_msg_to_smc_with_parameter(hwmgr,
 510                                         PPSMC_MSG_VddC_Request, req_volt);
 511                         return;
 512                 }
 513         }
 514         pr_err("DAL requested level can not"
 515                         " found a available voltage in VDDC DPM Table \n");
 516 }
 517
 518 int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
 519                                 uint32_t sclk, uint16_t id, uint16_t *voltage)
 520 {
 521         uint32_t vol;
 522         int ret = 0;
 523
 524         if (hwmgr->chip_id < CHIP_TONGA) {
 525                 ret = atomctrl_get_voltage_evv(hwmgr, id, voltage);
 526         } else if (hwmgr->chip_id < CHIP_POLARIS10) {
 527                 ret = atomctrl_get_voltage_evv_on_sclk(hwmgr, voltage_type, sclk, id, voltage);
 528                 if (*voltage >= 2000 || *voltage == 0)
 529                         *voltage = 1150;
 530         } else {
 531                 ret = atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, voltage_type, sclk, id, &vol);
 532                 *voltage = (uint16_t)(vol/100);
 533         }
 534         return ret;
 535 }
 536
 537
 538 int phm_irq_process(struct amdgpu_device *adev,
 539                            struct amdgpu_irq_src *source,
 540                            struct amdgpu_iv_entry *entry)
 541 {
 542         uint32_t client_id = entry->client_id;
 543         uint32_t src_id = entry->src_id;
 544
 545         if (client_id == AMDGPU_IH_CLIENTID_LEGACY) {
 546                 if (src_id == 230)
 547                         pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
 548                                                 PCI_BUS_NUM(adev->pdev->devfn),
 549                                                 PCI_SLOT(adev->pdev->devfn),
 550                                                 PCI_FUNC(adev->pdev->devfn));
 551                 else if (src_id == 231)
 552                         pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
 553                                         PCI_BUS_NUM(adev->pdev->devfn),
 554                                         PCI_SLOT(adev->pdev->devfn),
 555                                         PCI_FUNC(adev->pdev->devfn));
 556                 else if (src_id == 83)
 557                         pr_warn("GPU Critical Temperature Fault detected on PCIe %d:%d.%d!\n",
 558                                         PCI_BUS_NUM(adev->pdev->devfn),
 559                                         PCI_SLOT(adev->pdev->devfn),
 560                                         PCI_FUNC(adev->pdev->devfn));
 561         } else if (client_id == SOC15_IH_CLIENTID_THM) {
 562                 if (src_id == 0)
 563                         pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
 564                                                 PCI_BUS_NUM(adev->pdev->devfn),
 565                                                 PCI_SLOT(adev->pdev->devfn),
 566                                                 PCI_FUNC(adev->pdev->devfn));
 567                 else
 568                         pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
 569                                         PCI_BUS_NUM(adev->pdev->devfn),
 570                                         PCI_SLOT(adev->pdev->devfn),
 571                                         PCI_FUNC(adev->pdev->devfn));
 572         } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO)
 573                 pr_warn("GPU Critical Temperature Fault detected on PCIe %d:%d.%d!\n",
 574                                 PCI_BUS_NUM(adev->pdev->devfn),
 575                                 PCI_SLOT(adev->pdev->devfn),
 576                                 PCI_FUNC(adev->pdev->devfn));
 577
 578         return 0;
 579 }
 580
 581 static const struct amdgpu_irq_src_funcs smu9_irq_funcs = {
 582         .process = phm_irq_process,
 583 };
 584
 585 int smu9_register_irq_handlers(struct pp_hwmgr *hwmgr)
 586 {
 587         struct amdgpu_irq_src *source =
 588                 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
 589
 590         if (!source)
 591                 return -ENOMEM;
 592
 593         source->funcs = &smu9_irq_funcs;
 594
 595         amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
 596                         SOC15_IH_CLIENTID_THM,
 597                         0,
 598                         source);
 599         amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
 600                         SOC15_IH_CLIENTID_THM,
 601                         1,
 602                         source);
 603
 604         /* Register CTF(GPIO_19) interrupt */
 605         amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
 606                         SOC15_IH_CLIENTID_ROM_SMUIO,
 607                         83,
 608                         source);
 609
 610         return 0;
 611 }
 612
 613 void *smu_atom_get_data_table(void *dev, uint32_t table, uint16_t *size,
 614                                                 uint8_t *frev, uint8_t *crev)
 615 {
 616         struct amdgpu_device *adev = dev;
 617         uint16_t data_start;
 618
 619         if (amdgpu_atom_parse_data_header(
 620                     adev->mode_info.atom_context, table, size,
 621                     frev, crev, &data_start))
 622                 return (uint8_t *)adev->mode_info.atom_context->bios +
 623                         data_start;
 624
 625         return NULL;
 626 }
 627
 628 int smu_get_voltage_dependency_table_ppt_v1(
 629                         const struct phm_ppt_v1_clock_voltage_dependency_table *allowed_dep_table,
 630                         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table)
 631 {
 632         uint8_t i = 0;
 633         PP_ASSERT_WITH_CODE((0 != allowed_dep_table->count),
 634                                 "Voltage Lookup Table empty",
 635                                 return -EINVAL);
 636
 637         dep_table->count = allowed_dep_table->count;
 638         for (i=0; i<dep_table->count; i++) {
 639                 dep_table->entries[i].clk = allowed_dep_table->entries[i].clk;
 640                 dep_table->entries[i].vddInd = allowed_dep_table->entries[i].vddInd;
 641                 dep_table->entries[i].vdd_offset = allowed_dep_table->entries[i].vdd_offset;
 642                 dep_table->entries[i].vddc = allowed_dep_table->entries[i].vddc;
 643                 dep_table->entries[i].vddgfx = allowed_dep_table->entries[i].vddgfx;
 644                 dep_table->entries[i].vddci = allowed_dep_table->entries[i].vddci;
 645                 dep_table->entries[i].mvdd = allowed_dep_table->entries[i].mvdd;
 646                 dep_table->entries[i].phases = allowed_dep_table->entries[i].phases;
 647                 dep_table->entries[i].cks_enable = allowed_dep_table->entries[i].cks_enable;
 648                 dep_table->entries[i].cks_voffset = allowed_dep_table->entries[i].cks_voffset;
 649         }
 650
 651         return 0;
 652 }
 653
 654 int smu_set_watermarks_for_clocks_ranges(void *wt_table,
 655                 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
 656 {
 657         uint32_t i;
 658         struct watermarks *table = wt_table;
 659
 660         if (!table || !wm_with_clock_ranges)
 661                 return -EINVAL;
 662
 663         if (wm_with_clock_ranges->num_wm_sets_dmif > 4 || wm_with_clock_ranges->num_wm_sets_mcif > 4)
 664                 return -EINVAL;
 665
 666         for (i = 0; i < wm_with_clock_ranges->num_wm_sets_dmif; i++) {
 667                 table->WatermarkRow[1][i].MinClock =
 668                         cpu_to_le16((uint16_t)
 669                         (wm_with_clock_ranges->wm_sets_dmif[i].wm_min_dcefclk_in_khz) /
 670                         100);
 671                 table->WatermarkRow[1][i].MaxClock =
 672                         cpu_to_le16((uint16_t)
 673                         (wm_with_clock_ranges->wm_sets_dmif[i].wm_max_dcefclk_in_khz) /
 674                         100);
 675                 table->WatermarkRow[1][i].MinUclk =
 676                         cpu_to_le16((uint16_t)
 677                         (wm_with_clock_ranges->wm_sets_dmif[i].wm_min_memclk_in_khz) /
 678                         100);
 679                 table->WatermarkRow[1][i].MaxUclk =
 680                         cpu_to_le16((uint16_t)
 681                         (wm_with_clock_ranges->wm_sets_dmif[i].wm_max_memclk_in_khz) /
 682                         100);
 683                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
 684                                 wm_with_clock_ranges->wm_sets_dmif[i].wm_set_id;
 685         }
 686
 687         for (i = 0; i < wm_with_clock_ranges->num_wm_sets_mcif; i++) {
 688                 table->WatermarkRow[0][i].MinClock =
 689                         cpu_to_le16((uint16_t)
 690                         (wm_with_clock_ranges->wm_sets_mcif[i].wm_min_socclk_in_khz) /
 691                         100);
 692                 table->WatermarkRow[0][i].MaxClock =
 693                         cpu_to_le16((uint16_t)
 694                         (wm_with_clock_ranges->wm_sets_mcif[i].wm_max_socclk_in_khz) /
 695                         100);
 696                 table->WatermarkRow[0][i].MinUclk =
 697                         cpu_to_le16((uint16_t)
 698                         (wm_with_clock_ranges->wm_sets_mcif[i].wm_min_memclk_in_khz) /
 699                         100);
 700                 table->WatermarkRow[0][i].MaxUclk =
 701                         cpu_to_le16((uint16_t)
 702                         (wm_with_clock_ranges->wm_sets_mcif[i].wm_max_memclk_in_khz) /
 703                         100);
 704                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
 705                                 wm_with_clock_ranges->wm_sets_mcif[i].wm_set_id;
 706         }
 707         return 0;
 708 }