drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26 #include <linux/reboot.h>
  27
  28 #define SMU_13_0_PARTIAL_PPTABLE
  29 #define SWSMU_CODE_LAYER_L3
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_smu.h"
  33 #include "atomfirmware.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_atombios.h"
  36 #include "smu_v13_0.h"
  37 #include "soc15_common.h"
  38 #include "atom.h"
  39 #include "amdgpu_ras.h"
  40 #include "smu_cmn.h"
  41
  42 #include "asic_reg/thm/thm_13_0_2_offset.h"
  43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
  44 #include "asic_reg/mp/mp_13_0_2_offset.h"
  45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
  46 #include "asic_reg/smuio/smuio_13_0_2_offset.h"
  47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
  48
  49 /*
  50  * DO NOT use these for err/warn/info/debug messages.
  51  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  52  * They are more MGPU friendly.
  53  */
  54 #undef pr_err
  55 #undef pr_warn
  56 #undef pr_info
  57 #undef pr_debug
  58
  59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
  60 MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
  61 MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
  62
  63 #define mmMP1_SMN_C2PMSG_66                                                                            0x0282
  64 #define mmMP1_SMN_C2PMSG_66_BASE_IDX                                                                   0
  65
  66 #define mmMP1_SMN_C2PMSG_82                                                                            0x0292
  67 #define mmMP1_SMN_C2PMSG_82_BASE_IDX                                                                   0
  68
  69 #define mmMP1_SMN_C2PMSG_90                                                                            0x029a
  70 #define mmMP1_SMN_C2PMSG_90_BASE_IDX                                                                   0
  71
  72 #define SMU13_VOLTAGE_SCALE 4
  73
  74 #define LINK_WIDTH_MAX                          6
  75 #define LINK_SPEED_MAX                          3
  76
  77 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  78 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
  79 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
  80 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  81 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
  82 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
  83
  84 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
  85 static const int link_speed[] = {25, 50, 80, 160};
  86
  87 static int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, void **table, uint32_t *size,
  88                                                uint32_t pptable_id);
  89
  90 int smu_v13_0_init_microcode(struct smu_context *smu)
  91 {
  92         struct amdgpu_device *adev = smu->adev;
  93         const char *chip_name;
  94         char fw_name[30];
  95         char ucode_prefix[30];
  96         int err = 0;
  97         const struct smc_firmware_header_v1_0 *hdr;
  98         const struct common_firmware_header *header;
  99         struct amdgpu_firmware_info *ucode = NULL;
 100
 101         /* doesn't need to load smu firmware in IOV mode */
 102         if (amdgpu_sriov_vf(adev))
 103                 return 0;
 104
 105         switch (adev->ip_versions[MP1_HWIP][0]) {
 106         case IP_VERSION(13, 0, 2):
 107                 chip_name = "aldebaran_smc";
 108                 break;
 109         default:
 110                 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
 111                 chip_name = ucode_prefix;
 112         }
 113
 114         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name);
 115
 116         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 117         if (err)
 118                 goto out;
 119         err = amdgpu_ucode_validate(adev->pm.fw);
 120         if (err)
 121                 goto out;
 122
 123         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 124         amdgpu_ucode_print_smc_hdr(&hdr->header);
 125         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 126
 127         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 128                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 129                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 130                 ucode->fw = adev->pm.fw;
 131                 header = (const struct common_firmware_header *)ucode->fw->data;
 132                 adev->firmware.fw_size +=
 133                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 134         }
 135
 136 out:
 137         if (err) {
 138                 DRM_ERROR("smu_v13_0: Failed to load firmware \"%s\"\n",
 139                           fw_name);
 140                 release_firmware(adev->pm.fw);
 141                 adev->pm.fw = NULL;
 142         }
 143         return err;
 144 }
 145
 146 void smu_v13_0_fini_microcode(struct smu_context *smu)
 147 {
 148         struct amdgpu_device *adev = smu->adev;
 149
 150         release_firmware(adev->pm.fw);
 151         adev->pm.fw = NULL;
 152         adev->pm.fw_version = 0;
 153 }
 154
 155 int smu_v13_0_load_microcode(struct smu_context *smu)
 156 {
 157 #if 0
 158         struct amdgpu_device *adev = smu->adev;
 159         const uint32_t *src;
 160         const struct smc_firmware_header_v1_0 *hdr;
 161         uint32_t addr_start = MP1_SRAM;
 162         uint32_t i;
 163         uint32_t smc_fw_size;
 164         uint32_t mp1_fw_flags;
 165
 166         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 167         src = (const uint32_t *)(adev->pm.fw->data +
 168                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 169         smc_fw_size = hdr->header.ucode_size_bytes;
 170
 171         for (i = 1; i < smc_fw_size/4 - 1; i++) {
 172                 WREG32_PCIE(addr_start, src[i]);
 173                 addr_start += 4;
 174         }
 175
 176         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 177                     1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 178         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 179                     1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 180
 181         for (i = 0; i < adev->usec_timeout; i++) {
 182                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 183                                            (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 184                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 185                     MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 186                         break;
 187                 udelay(1);
 188         }
 189
 190         if (i == adev->usec_timeout)
 191                 return -ETIME;
 192 #endif
 193
 194         return 0;
 195 }
 196
 197 int smu_v13_0_init_pptable_microcode(struct smu_context *smu)
 198 {
 199         struct amdgpu_device *adev = smu->adev;
 200         struct amdgpu_firmware_info *ucode = NULL;
 201         uint32_t size = 0, pptable_id = 0;
 202         int ret = 0;
 203         void *table;
 204
 205         /* doesn't need to load smu firmware in IOV mode */
 206         if (amdgpu_sriov_vf(adev))
 207                 return 0;
 208
 209         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 210                 return 0;
 211
 212         if (!adev->scpm_enabled)
 213                 return 0;
 214
 215         /* override pptable_id from driver parameter */
 216         if (amdgpu_smu_pptable_id >= 0) {
 217                 pptable_id = amdgpu_smu_pptable_id;
 218                 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
 219         } else {
 220                 pptable_id = smu->smu_table.boot_values.pp_table_id;
 221
 222                 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7) &&
 223                         pptable_id == 3667)
 224                         pptable_id = 36671;
 225
 226                 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7) &&
 227                         pptable_id == 3688)
 228                         pptable_id = 36881;
 229                 /*
 230                  * Temporary solution for SMU V13.0.0 with SCPM enabled:
 231                  *   - use 36831 signed pptable when pp_table_id is 3683
 232                  *   - use 36641 signed pptable when pp_table_id is 3664 or 0
 233                  * TODO: drop these when the pptable carried in vbios is ready.
 234                  */
 235                 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) {
 236                         switch (pptable_id) {
 237                         case 0:
 238                         case 3664:
 239                                 pptable_id = 36641;
 240                                 break;
 241                         case 3683:
 242                                 pptable_id = 36831;
 243                                 break;
 244                         default:
 245                                 dev_err(adev->dev, "Unsupported pptable id %d\n", pptable_id);
 246                                 return -EINVAL;
 247                         }
 248                 }
 249         }
 250
 251         /* "pptable_id == 0" means vbios carries the pptable. */
 252         if (!pptable_id)
 253                 return 0;
 254
 255         ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
 256         if (ret)
 257                 return ret;
 258
 259         smu->pptable_firmware.data = table;
 260         smu->pptable_firmware.size = size;
 261
 262         ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE];
 263         ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE;
 264         ucode->fw = &smu->pptable_firmware;
 265         adev->firmware.fw_size +=
 266                 ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
 267
 268         return 0;
 269 }
 270
 271 int smu_v13_0_check_fw_status(struct smu_context *smu)
 272 {
 273         struct amdgpu_device *adev = smu->adev;
 274         uint32_t mp1_fw_flags;
 275
 276         switch (adev->ip_versions[MP1_HWIP][0]) {
 277         case IP_VERSION(13, 0, 4):
 278                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 279                                            (smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff));
 280                 break;
 281         default:
 282                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 283                                            (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 284                 break;
 285         }
 286
 287         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 288             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 289                 return 0;
 290
 291         return -EIO;
 292 }
 293
 294 int smu_v13_0_check_fw_version(struct smu_context *smu)
 295 {
 296         struct amdgpu_device *adev = smu->adev;
 297         uint32_t if_version = 0xff, smu_version = 0xff;
 298         uint8_t smu_program, smu_major, smu_minor, smu_debug;
 299         int ret = 0;
 300
 301         ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
 302         if (ret)
 303                 return ret;
 304
 305         smu_program = (smu_version >> 24) & 0xff;
 306         smu_major = (smu_version >> 16) & 0xff;
 307         smu_minor = (smu_version >> 8) & 0xff;
 308         smu_debug = (smu_version >> 0) & 0xff;
 309         if (smu->is_apu)
 310                 adev->pm.fw_version = smu_version;
 311
 312         switch (adev->ip_versions[MP1_HWIP][0]) {
 313         case IP_VERSION(13, 0, 2):
 314                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
 315                 break;
 316         case IP_VERSION(13, 0, 0):
 317                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_0;
 318                 break;
 319         case IP_VERSION(13, 0, 7):
 320                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_7;
 321                 break;
 322         case IP_VERSION(13, 0, 1):
 323         case IP_VERSION(13, 0, 3):
 324         case IP_VERSION(13, 0, 8):
 325                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;
 326                 break;
 327         case IP_VERSION(13, 0, 4):
 328                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_4;
 329                 break;
 330         case IP_VERSION(13, 0, 5):
 331                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_5;
 332                 break;
 333         default:
 334                 dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
 335                         adev->ip_versions[MP1_HWIP][0]);
 336                 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;
 337                 break;
 338         }
 339
 340         /* only for dGPU w/ SMU13*/
 341         if (adev->pm.fw)
 342                 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
 343                          smu_program, smu_version, smu_major, smu_minor, smu_debug);
 344
 345         /*
 346          * 1. if_version mismatch is not critical as our fw is designed
 347          * to be backward compatible.
 348          * 2. New fw usually brings some optimizations. But that's visible
 349          * only on the paired driver.
 350          * Considering above, we just leave user a warning message instead
 351          * of halt driver loading.
 352          */
 353         if (if_version != smu->smc_driver_if_version) {
 354                 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 355                          "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
 356                          smu->smc_driver_if_version, if_version,
 357                          smu_program, smu_version, smu_major, smu_minor, smu_debug);
 358                 dev_warn(adev->dev, "SMU driver if version not matched\n");
 359         }
 360
 361         return ret;
 362 }
 363
 364 static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 365 {
 366         struct amdgpu_device *adev = smu->adev;
 367         uint32_t ppt_offset_bytes;
 368         const struct smc_firmware_header_v2_0 *v2;
 369
 370         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 371
 372         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 373         *size = le32_to_cpu(v2->ppt_size_bytes);
 374         *table = (uint8_t *)v2 + ppt_offset_bytes;
 375
 376         return 0;
 377 }
 378
 379 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 380                                       uint32_t *size, uint32_t pptable_id)
 381 {
 382         struct amdgpu_device *adev = smu->adev;
 383         const struct smc_firmware_header_v2_1 *v2_1;
 384         struct smc_soft_pptable_entry *entries;
 385         uint32_t pptable_count = 0;
 386         int i = 0;
 387
 388         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 389         entries = (struct smc_soft_pptable_entry *)
 390                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 391         pptable_count = le32_to_cpu(v2_1->pptable_count);
 392         for (i = 0; i < pptable_count; i++) {
 393                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 394                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 395                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 396                         break;
 397                 }
 398         }
 399
 400         if (i == pptable_count)
 401                 return -EINVAL;
 402
 403         return 0;
 404 }
 405
 406 static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
 407 {
 408         struct amdgpu_device *adev = smu->adev;
 409         uint16_t atom_table_size;
 410         uint8_t frev, crev;
 411         int ret, index;
 412
 413         dev_info(adev->dev, "use vbios provided pptable\n");
 414         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 415                                             powerplayinfo);
 416
 417         ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
 418                                              (uint8_t **)table);
 419         if (ret)
 420                 return ret;
 421
 422         if (size)
 423                 *size = atom_table_size;
 424
 425         return 0;
 426 }
 427
 428 static int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, void **table, uint32_t *size,
 429                                                uint32_t pptable_id)
 430 {
 431         const struct smc_firmware_header_v1_0 *hdr;
 432         struct amdgpu_device *adev = smu->adev;
 433         uint16_t version_major, version_minor;
 434         int ret;
 435
 436         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 437         if (!hdr)
 438                 return -EINVAL;
 439
 440         dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
 441
 442         version_major = le16_to_cpu(hdr->header.header_version_major);
 443         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 444         if (version_major != 2) {
 445                 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
 446                         version_major, version_minor);
 447                 return -EINVAL;
 448         }
 449
 450         switch (version_minor) {
 451         case 0:
 452                 ret = smu_v13_0_set_pptable_v2_0(smu, table, size);
 453                 break;
 454         case 1:
 455                 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
 456                 break;
 457         default:
 458                 ret = -EINVAL;
 459                 break;
 460         }
 461
 462         return ret;
 463 }
 464
 465 int smu_v13_0_setup_pptable(struct smu_context *smu)
 466 {
 467         struct amdgpu_device *adev = smu->adev;
 468         uint32_t size = 0, pptable_id = 0;
 469         void *table;
 470         int ret = 0;
 471
 472         /* override pptable_id from driver parameter */
 473         if (amdgpu_smu_pptable_id >= 0) {
 474                 pptable_id = amdgpu_smu_pptable_id;
 475                 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
 476         } else {
 477                 pptable_id = smu->smu_table.boot_values.pp_table_id;
 478
 479                 /*
 480                  * Temporary solution for SMU V13.0.0 with SCPM disabled:
 481                  *   - use 3664 or 3683 on request
 482                  *   - use 3664 when pptable_id is 0
 483                  * TODO: drop these when the pptable carried in vbios is ready.
 484                  */
 485                 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) {
 486                         switch (pptable_id) {
 487                         case 0:
 488                                 pptable_id = 3664;
 489                                 break;
 490                         case 3664:
 491                         case 3683:
 492                                 break;
 493                         default:
 494                                 dev_err(adev->dev, "Unsupported pptable id %d\n", pptable_id);
 495                                 return -EINVAL;
 496                         }
 497                 }
 498         }
 499
 500         /* force using vbios pptable in sriov mode */
 501         if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1))
 502                 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
 503         else
 504                 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
 505
 506         if (ret)
 507                 return ret;
 508
 509         if (!smu->smu_table.power_play_table)
 510                 smu->smu_table.power_play_table = table;
 511         if (!smu->smu_table.power_play_table_size)
 512                 smu->smu_table.power_play_table_size = size;
 513
 514         return 0;
 515 }
 516
 517 int smu_v13_0_init_smc_tables(struct smu_context *smu)
 518 {
 519         struct smu_table_context *smu_table = &smu->smu_table;
 520         struct smu_table *tables = smu_table->tables;
 521         int ret = 0;
 522
 523         smu_table->driver_pptable =
 524                 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
 525         if (!smu_table->driver_pptable) {
 526                 ret = -ENOMEM;
 527                 goto err0_out;
 528         }
 529
 530         smu_table->max_sustainable_clocks =
 531                 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
 532         if (!smu_table->max_sustainable_clocks) {
 533                 ret = -ENOMEM;
 534                 goto err1_out;
 535         }
 536
 537         /* Aldebaran does not support OVERDRIVE */
 538         if (tables[SMU_TABLE_OVERDRIVE].size) {
 539                 smu_table->overdrive_table =
 540                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 541                 if (!smu_table->overdrive_table) {
 542                         ret = -ENOMEM;
 543                         goto err2_out;
 544                 }
 545
 546                 smu_table->boot_overdrive_table =
 547                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 548                 if (!smu_table->boot_overdrive_table) {
 549                         ret = -ENOMEM;
 550                         goto err3_out;
 551                 }
 552         }
 553
 554         smu_table->combo_pptable =
 555                 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
 556         if (!smu_table->combo_pptable) {
 557                 ret = -ENOMEM;
 558                 goto err4_out;
 559         }
 560
 561         return 0;
 562
 563 err4_out:
 564         kfree(smu_table->boot_overdrive_table);
 565 err3_out:
 566         kfree(smu_table->overdrive_table);
 567 err2_out:
 568         kfree(smu_table->max_sustainable_clocks);
 569 err1_out:
 570         kfree(smu_table->driver_pptable);
 571 err0_out:
 572         return ret;
 573 }
 574
 575 int smu_v13_0_fini_smc_tables(struct smu_context *smu)
 576 {
 577         struct smu_table_context *smu_table = &smu->smu_table;
 578         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 579
 580         kfree(smu_table->gpu_metrics_table);
 581         kfree(smu_table->combo_pptable);
 582         kfree(smu_table->boot_overdrive_table);
 583         kfree(smu_table->overdrive_table);
 584         kfree(smu_table->max_sustainable_clocks);
 585         kfree(smu_table->driver_pptable);
 586         smu_table->gpu_metrics_table = NULL;
 587         smu_table->combo_pptable = NULL;
 588         smu_table->boot_overdrive_table = NULL;
 589         smu_table->overdrive_table = NULL;
 590         smu_table->max_sustainable_clocks = NULL;
 591         smu_table->driver_pptable = NULL;
 592         kfree(smu_table->hardcode_pptable);
 593         smu_table->hardcode_pptable = NULL;
 594
 595         kfree(smu_table->ecc_table);
 596         kfree(smu_table->metrics_table);
 597         kfree(smu_table->watermarks_table);
 598         smu_table->ecc_table = NULL;
 599         smu_table->metrics_table = NULL;
 600         smu_table->watermarks_table = NULL;
 601         smu_table->metrics_time = 0;
 602
 603         kfree(smu_dpm->dpm_context);
 604         kfree(smu_dpm->golden_dpm_context);
 605         kfree(smu_dpm->dpm_current_power_state);
 606         kfree(smu_dpm->dpm_request_power_state);
 607         smu_dpm->dpm_context = NULL;
 608         smu_dpm->golden_dpm_context = NULL;
 609         smu_dpm->dpm_context_size = 0;
 610         smu_dpm->dpm_current_power_state = NULL;
 611         smu_dpm->dpm_request_power_state = NULL;
 612
 613         return 0;
 614 }
 615
 616 int smu_v13_0_init_power(struct smu_context *smu)
 617 {
 618         struct smu_power_context *smu_power = &smu->smu_power;
 619
 620         if (smu_power->power_context || smu_power->power_context_size != 0)
 621                 return -EINVAL;
 622
 623         smu_power->power_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
 624                                            GFP_KERNEL);
 625         if (!smu_power->power_context)
 626                 return -ENOMEM;
 627         smu_power->power_context_size = sizeof(struct smu_13_0_dpm_context);
 628
 629         return 0;
 630 }
 631
 632 int smu_v13_0_fini_power(struct smu_context *smu)
 633 {
 634         struct smu_power_context *smu_power = &smu->smu_power;
 635
 636         if (!smu_power->power_context || smu_power->power_context_size == 0)
 637                 return -EINVAL;
 638
 639         kfree(smu_power->power_context);
 640         smu_power->power_context = NULL;
 641         smu_power->power_context_size = 0;
 642
 643         return 0;
 644 }
 645
 646 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
 647 {
 648         int ret, index;
 649         uint16_t size;
 650         uint8_t frev, crev;
 651         struct atom_common_table_header *header;
 652         struct atom_firmware_info_v3_4 *v_3_4;
 653         struct atom_firmware_info_v3_3 *v_3_3;
 654         struct atom_firmware_info_v3_1 *v_3_1;
 655         struct atom_smu_info_v3_6 *smu_info_v3_6;
 656         struct atom_smu_info_v4_0 *smu_info_v4_0;
 657
 658         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 659                                             firmwareinfo);
 660
 661         ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
 662                                              (uint8_t **)&header);
 663         if (ret)
 664                 return ret;
 665
 666         if (header->format_revision != 3) {
 667                 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
 668                 return -EINVAL;
 669         }
 670
 671         switch (header->content_revision) {
 672         case 0:
 673         case 1:
 674         case 2:
 675                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 676                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 677                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 678                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 679                 smu->smu_table.boot_values.socclk = 0;
 680                 smu->smu_table.boot_values.dcefclk = 0;
 681                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 682                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 683                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 684                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 685                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 686                 smu->smu_table.boot_values.pp_table_id = 0;
 687                 break;
 688         case 3:
 689                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 690                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 691                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 692                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 693                 smu->smu_table.boot_values.socclk = 0;
 694                 smu->smu_table.boot_values.dcefclk = 0;
 695                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 696                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 697                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 698                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 699                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 700                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 701                 break;
 702         case 4:
 703         default:
 704                 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
 705                 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
 706                 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
 707                 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
 708                 smu->smu_table.boot_values.socclk = 0;
 709                 smu->smu_table.boot_values.dcefclk = 0;
 710                 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
 711                 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
 712                 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
 713                 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
 714                 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
 715                 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
 716                 break;
 717         }
 718
 719         smu->smu_table.boot_values.format_revision = header->format_revision;
 720         smu->smu_table.boot_values.content_revision = header->content_revision;
 721
 722         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 723                                             smu_info);
 724         if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
 725                                             (uint8_t **)&header)) {
 726
 727                 if ((frev == 3) && (crev == 6)) {
 728                         smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
 729
 730                         smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
 731                         smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
 732                         smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
 733                         smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
 734                 } else if ((frev == 3) && (crev == 1)) {
 735                         return 0;
 736                 } else if ((frev == 4) && (crev == 0)) {
 737                         smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
 738
 739                         smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
 740                         smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
 741                         smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
 742                         smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
 743                         smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
 744                 } else {
 745                         dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
 746                                                 (uint32_t)frev, (uint32_t)crev);
 747                 }
 748         }
 749
 750         return 0;
 751 }
 752
 753
 754 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
 755 {
 756         struct smu_table_context *smu_table = &smu->smu_table;
 757         struct smu_table *memory_pool = &smu_table->memory_pool;
 758         int ret = 0;
 759         uint64_t address;
 760         uint32_t address_low, address_high;
 761
 762         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 763                 return ret;
 764
 765         address = memory_pool->mc_address;
 766         address_high = (uint32_t)upper_32_bits(address);
 767         address_low  = (uint32_t)lower_32_bits(address);
 768
 769         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 770                                               address_high, NULL);
 771         if (ret)
 772                 return ret;
 773         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 774                                               address_low, NULL);
 775         if (ret)
 776                 return ret;
 777         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 778                                               (uint32_t)memory_pool->size, NULL);
 779         if (ret)
 780                 return ret;
 781
 782         return ret;
 783 }
 784
 785 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 786 {
 787         int ret;
 788
 789         ret = smu_cmn_send_smc_msg_with_param(smu,
 790                                               SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
 791         if (ret)
 792                 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
 793
 794         return ret;
 795 }
 796
 797 int smu_v13_0_set_driver_table_location(struct smu_context *smu)
 798 {
 799         struct smu_table *driver_table = &smu->smu_table.driver_table;
 800         int ret = 0;
 801
 802         if (driver_table->mc_address) {
 803                 ret = smu_cmn_send_smc_msg_with_param(smu,
 804                                                       SMU_MSG_SetDriverDramAddrHigh,
 805                                                       upper_32_bits(driver_table->mc_address),
 806                                                       NULL);
 807                 if (!ret)
 808                         ret = smu_cmn_send_smc_msg_with_param(smu,
 809                                                               SMU_MSG_SetDriverDramAddrLow,
 810                                                               lower_32_bits(driver_table->mc_address),
 811                                                               NULL);
 812         }
 813
 814         return ret;
 815 }
 816
 817 int smu_v13_0_set_tool_table_location(struct smu_context *smu)
 818 {
 819         int ret = 0;
 820         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 821
 822         if (tool_table->mc_address) {
 823                 ret = smu_cmn_send_smc_msg_with_param(smu,
 824                                                       SMU_MSG_SetToolsDramAddrHigh,
 825                                                       upper_32_bits(tool_table->mc_address),
 826                                                       NULL);
 827                 if (!ret)
 828                         ret = smu_cmn_send_smc_msg_with_param(smu,
 829                                                               SMU_MSG_SetToolsDramAddrLow,
 830                                                               lower_32_bits(tool_table->mc_address),
 831                                                               NULL);
 832         }
 833
 834         return ret;
 835 }
 836
 837 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
 838 {
 839         int ret = 0;
 840
 841         if (!smu->pm_enabled)
 842                 return ret;
 843
 844         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
 845
 846         return ret;
 847 }
 848
 849 int smu_v13_0_set_allowed_mask(struct smu_context *smu)
 850 {
 851         struct smu_feature *feature = &smu->smu_feature;
 852         int ret = 0;
 853         uint32_t feature_mask[2];
 854
 855         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
 856             feature->feature_num < 64)
 857                 return -EINVAL;
 858
 859         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 860
 861         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 862                                               feature_mask[1], NULL);
 863         if (ret)
 864                 return ret;
 865
 866         return smu_cmn_send_smc_msg_with_param(smu,
 867                                                SMU_MSG_SetAllowedFeaturesMaskLow,
 868                                                feature_mask[0],
 869                                                NULL);
 870 }
 871
 872 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
 873 {
 874         int ret = 0;
 875         struct amdgpu_device *adev = smu->adev;
 876
 877         switch (adev->ip_versions[MP1_HWIP][0]) {
 878         case IP_VERSION(13, 0, 0):
 879         case IP_VERSION(13, 0, 1):
 880         case IP_VERSION(13, 0, 3):
 881         case IP_VERSION(13, 0, 4):
 882         case IP_VERSION(13, 0, 5):
 883         case IP_VERSION(13, 0, 7):
 884         case IP_VERSION(13, 0, 8):
 885                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
 886                         return 0;
 887                 if (enable)
 888                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
 889                 else
 890                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
 891                 break;
 892         default:
 893                 break;
 894         }
 895
 896         return ret;
 897 }
 898
 899 int smu_v13_0_system_features_control(struct smu_context *smu,
 900                                       bool en)
 901 {
 902         return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 903                                           SMU_MSG_DisableAllSmuFeatures), NULL);
 904 }
 905
 906 int smu_v13_0_notify_display_change(struct smu_context *smu)
 907 {
 908         int ret = 0;
 909
 910         if (!smu->pm_enabled)
 911                 return ret;
 912
 913         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 914             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 915                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
 916
 917         return ret;
 918 }
 919
 920         static int
 921 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 922                                     enum smu_clk_type clock_select)
 923 {
 924         int ret = 0;
 925         int clk_id;
 926
 927         if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
 928             (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
 929                 return 0;
 930
 931         clk_id = smu_cmn_to_asic_specific_index(smu,
 932                                                 CMN2ASIC_MAPPING_CLK,
 933                                                 clock_select);
 934         if (clk_id < 0)
 935                 return -EINVAL;
 936
 937         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 938                                               clk_id << 16, clock);
 939         if (ret) {
 940                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 941                 return ret;
 942         }
 943
 944         if (*clock != 0)
 945                 return 0;
 946
 947         /* if DC limit is zero, return AC limit */
 948         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 949                                               clk_id << 16, clock);
 950         if (ret) {
 951                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 952                 return ret;
 953         }
 954
 955         return 0;
 956 }
 957
 958 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
 959 {
 960         struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
 961                 smu->smu_table.max_sustainable_clocks;
 962         int ret = 0;
 963
 964         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 965         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 966         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 967         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 968         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 969         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 970
 971         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 972                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 973                                                           &(max_sustainable_clocks->uclock),
 974                                                           SMU_UCLK);
 975                 if (ret) {
 976                         dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
 977                                 __func__);
 978                         return ret;
 979                 }
 980         }
 981
 982         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 983                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 984                                                           &(max_sustainable_clocks->soc_clock),
 985                                                           SMU_SOCCLK);
 986                 if (ret) {
 987                         dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
 988                                 __func__);
 989                         return ret;
 990                 }
 991         }
 992
 993         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 994                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 995                                                           &(max_sustainable_clocks->dcef_clock),
 996                                                           SMU_DCEFCLK);
 997                 if (ret) {
 998                         dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
 999                                 __func__);
1000                         return ret;
1001                 }
1002
1003                 ret = smu_v13_0_get_max_sustainable_clock(smu,
1004                                                           &(max_sustainable_clocks->display_clock),
1005                                                           SMU_DISPCLK);
1006                 if (ret) {
1007                         dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
1008                                 __func__);
1009                         return ret;
1010                 }
1011                 ret = smu_v13_0_get_max_sustainable_clock(smu,
1012                                                           &(max_sustainable_clocks->phy_clock),
1013                                                           SMU_PHYCLK);
1014                 if (ret) {
1015                         dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
1016                                 __func__);
1017                         return ret;
1018                 }
1019                 ret = smu_v13_0_get_max_sustainable_clock(smu,
1020                                                           &(max_sustainable_clocks->pixel_clock),
1021                                                           SMU_PIXCLK);
1022                 if (ret) {
1023                         dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
1024                                 __func__);
1025                         return ret;
1026                 }
1027         }
1028
1029         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1030                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1031
1032         return 0;
1033 }
1034
1035 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
1036                                       uint32_t *power_limit)
1037 {
1038         int power_src;
1039         int ret = 0;
1040
1041         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1042                 return -EINVAL;
1043
1044         power_src = smu_cmn_to_asic_specific_index(smu,
1045                                                    CMN2ASIC_MAPPING_PWR,
1046                                                    smu->adev->pm.ac_power ?
1047                                                    SMU_POWER_SOURCE_AC :
1048                                                    SMU_POWER_SOURCE_DC);
1049         if (power_src < 0)
1050                 return -EINVAL;
1051
1052         ret = smu_cmn_send_smc_msg_with_param(smu,
1053                                               SMU_MSG_GetPptLimit,
1054                                               power_src << 16,
1055                                               power_limit);
1056         if (ret)
1057                 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
1058
1059         return ret;
1060 }
1061
1062 int smu_v13_0_set_power_limit(struct smu_context *smu,
1063                               enum smu_ppt_limit_type limit_type,
1064                               uint32_t limit)
1065 {
1066         int ret = 0;
1067
1068         if (limit_type != SMU_DEFAULT_PPT_LIMIT)
1069                 return -EINVAL;
1070
1071         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1072                 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
1073                 return -EOPNOTSUPP;
1074         }
1075
1076         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
1077         if (ret) {
1078                 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
1079                 return ret;
1080         }
1081
1082         smu->current_power_limit = limit;
1083
1084         return 0;
1085 }
1086
1087 static int smu_v13_0_allow_ih_interrupt(struct smu_context *smu)
1088 {
1089         return smu_cmn_send_smc_msg(smu,
1090                                     SMU_MSG_AllowIHHostInterrupt,
1091                                     NULL);
1092 }
1093
1094 static int smu_v13_0_process_pending_interrupt(struct smu_context *smu)
1095 {
1096         int ret = 0;
1097
1098         if (smu->dc_controlled_by_gpio &&
1099             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
1100                 ret = smu_v13_0_allow_ih_interrupt(smu);
1101
1102         return ret;
1103 }
1104
1105 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
1106 {
1107         int ret = 0;
1108
1109         if (smu->smu_table.thermal_controller_type) {
1110                 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1111                 if (ret)
1112                         return ret;
1113         }
1114
1115         return smu_v13_0_process_pending_interrupt(smu);
1116 }
1117
1118 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
1119 {
1120         return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1121 }
1122
1123 static uint16_t convert_to_vddc(uint8_t vid)
1124 {
1125         return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
1126 }
1127
1128 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1129 {
1130         struct amdgpu_device *adev = smu->adev;
1131         uint32_t vdd = 0, val_vid = 0;
1132
1133         if (!value)
1134                 return -EINVAL;
1135         val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
1136                    SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1137                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1138
1139         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1140
1141         *value = vdd;
1142
1143         return 0;
1144
1145 }
1146
1147 int
1148 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
1149                                         struct pp_display_clock_request
1150                                         *clock_req)
1151 {
1152         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1153         int ret = 0;
1154         enum smu_clk_type clk_select = 0;
1155         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1156
1157         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1158             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1159                 switch (clk_type) {
1160                 case amd_pp_dcef_clock:
1161                         clk_select = SMU_DCEFCLK;
1162                         break;
1163                 case amd_pp_disp_clock:
1164                         clk_select = SMU_DISPCLK;
1165                         break;
1166                 case amd_pp_pixel_clock:
1167                         clk_select = SMU_PIXCLK;
1168                         break;
1169                 case amd_pp_phy_clock:
1170                         clk_select = SMU_PHYCLK;
1171                         break;
1172                 case amd_pp_mem_clock:
1173                         clk_select = SMU_UCLK;
1174                         break;
1175                 default:
1176                         dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1177                         ret = -EINVAL;
1178                         break;
1179                 }
1180
1181                 if (ret)
1182                         goto failed;
1183
1184                 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1185                         return 0;
1186
1187                 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1188
1189                 if(clk_select == SMU_UCLK)
1190                         smu->hard_min_uclk_req_from_dal = clk_freq;
1191         }
1192
1193 failed:
1194         return ret;
1195 }
1196
1197 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1198 {
1199         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1200                 return AMD_FAN_CTRL_MANUAL;
1201         else
1202                 return AMD_FAN_CTRL_AUTO;
1203 }
1204
1205         static int
1206 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1207 {
1208         int ret = 0;
1209
1210         if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1211                 return 0;
1212
1213         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1214         if (ret)
1215                 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1216                         __func__, (auto_fan_control ? "Start" : "Stop"));
1217
1218         return ret;
1219 }
1220
1221         static int
1222 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1223 {
1224         struct amdgpu_device *adev = smu->adev;
1225
1226         WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1227                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1228                                    CG_FDO_CTRL2, TMIN, 0));
1229         WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1230                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1231                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1232
1233         return 0;
1234 }
1235
1236 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
1237                                 uint32_t speed)
1238 {
1239         struct amdgpu_device *adev = smu->adev;
1240         uint32_t duty100, duty;
1241         uint64_t tmp64;
1242
1243         speed = MIN(speed, 255);
1244
1245         if (smu_v13_0_auto_fan_control(smu, 0))
1246                 return -EINVAL;
1247
1248         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1249                                 CG_FDO_CTRL1, FMAX_DUTY100);
1250         if (!duty100)
1251                 return -EINVAL;
1252
1253         tmp64 = (uint64_t)speed * duty100;
1254         do_div(tmp64, 255);
1255         duty = (uint32_t)tmp64;
1256
1257         WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1258                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1259                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1260
1261         return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1262 }
1263
1264         int
1265 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1266                                uint32_t mode)
1267 {
1268         int ret = 0;
1269
1270         switch (mode) {
1271         case AMD_FAN_CTRL_NONE:
1272                 ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
1273                 break;
1274         case AMD_FAN_CTRL_MANUAL:
1275                 ret = smu_v13_0_auto_fan_control(smu, 0);
1276                 break;
1277         case AMD_FAN_CTRL_AUTO:
1278                 ret = smu_v13_0_auto_fan_control(smu, 1);
1279                 break;
1280         default:
1281                 break;
1282         }
1283
1284         if (ret) {
1285                 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1286                 return -EINVAL;
1287         }
1288
1289         return ret;
1290 }
1291
1292 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1293                                 uint32_t speed)
1294 {
1295         struct amdgpu_device *adev = smu->adev;
1296         uint32_t tach_period, crystal_clock_freq;
1297         int ret;
1298
1299         if (!speed)
1300                 return -EINVAL;
1301
1302         ret = smu_v13_0_auto_fan_control(smu, 0);
1303         if (ret)
1304                 return ret;
1305
1306         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1307         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1308         WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1309                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1310                                    CG_TACH_CTRL, TARGET_PERIOD,
1311                                    tach_period));
1312
1313         return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1314 }
1315
1316 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1317                               uint32_t pstate)
1318 {
1319         int ret = 0;
1320         ret = smu_cmn_send_smc_msg_with_param(smu,
1321                                               SMU_MSG_SetXgmiMode,
1322                                               pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1323                                               NULL);
1324         return ret;
1325 }
1326
1327 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1328                                    struct amdgpu_irq_src *source,
1329                                    unsigned tyep,
1330                                    enum amdgpu_interrupt_state state)
1331 {
1332         struct smu_context *smu = adev->powerplay.pp_handle;
1333         uint32_t low, high;
1334         uint32_t val = 0;
1335
1336         switch (state) {
1337         case AMDGPU_IRQ_STATE_DISABLE:
1338                 /* For THM irqs */
1339                 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1340                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1341                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1342                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1343
1344                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1345
1346                 /* For MP1 SW irqs */
1347                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1348                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1349                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1350
1351                 break;
1352         case AMDGPU_IRQ_STATE_ENABLE:
1353                 /* For THM irqs */
1354                 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1355                           smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1356                 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1357                            smu->thermal_range.software_shutdown_temp);
1358
1359                 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1360                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1361                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1362                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1363                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1364                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1365                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1366                 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1367                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1368
1369                 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1370                 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1371                 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1372                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1373
1374                 /* For MP1 SW irqs */
1375                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1376                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1377                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1378                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1379
1380                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1381                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1382                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1383
1384                 break;
1385         default:
1386                 break;
1387         }
1388
1389         return 0;
1390 }
1391
1392 static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1393 {
1394         return smu_cmn_send_smc_msg(smu,
1395                                     SMU_MSG_ReenableAcDcInterrupt,
1396                                     NULL);
1397 }
1398
1399 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1400 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1401 #define SMUIO_11_0__SRCID__SMUIO_GPIO19                 83
1402
1403 static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1404                                  struct amdgpu_irq_src *source,
1405                                  struct amdgpu_iv_entry *entry)
1406 {
1407         struct smu_context *smu = adev->powerplay.pp_handle;
1408         uint32_t client_id = entry->client_id;
1409         uint32_t src_id = entry->src_id;
1410         /*
1411          * ctxid is used to distinguish different
1412          * events for SMCToHost interrupt.
1413          */
1414         uint32_t ctxid = entry->src_data[0];
1415         uint32_t data;
1416
1417         if (client_id == SOC15_IH_CLIENTID_THM) {
1418                 switch (src_id) {
1419                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1420                         dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1421                         /*
1422                          * SW CTF just occurred.
1423                          * Try to do a graceful shutdown to prevent further damage.
1424                          */
1425                         dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1426                         orderly_poweroff(true);
1427                         break;
1428                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1429                         dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1430                         break;
1431                 default:
1432                         dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1433                                   src_id);
1434                         break;
1435                 }
1436         } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1437                 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1438                 /*
1439                  * HW CTF just occurred. Shutdown to prevent further damage.
1440                  */
1441                 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1442                 orderly_poweroff(true);
1443         } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1444                 if (src_id == 0xfe) {
1445                         /* ACK SMUToHost interrupt */
1446                         data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1447                         data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1448                         WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1449
1450                         switch (ctxid) {
1451                         case 0x3:
1452                                 dev_dbg(adev->dev, "Switched to AC mode!\n");
1453                                 smu_v13_0_ack_ac_dc_interrupt(smu);
1454                                 break;
1455                         case 0x4:
1456                                 dev_dbg(adev->dev, "Switched to DC mode!\n");
1457                                 smu_v13_0_ack_ac_dc_interrupt(smu);
1458                                 break;
1459                         case 0x7:
1460                                 /*
1461                                  * Increment the throttle interrupt counter
1462                                  */
1463                                 atomic64_inc(&smu->throttle_int_counter);
1464
1465                                 if (!atomic_read(&adev->throttling_logging_enabled))
1466                                         return 0;
1467
1468                                 if (__ratelimit(&adev->throttling_logging_rs))
1469                                         schedule_work(&smu->throttling_logging_work);
1470
1471                                 break;
1472                         }
1473                 }
1474         }
1475
1476         return 0;
1477 }
1478
1479 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs =
1480 {
1481         .set = smu_v13_0_set_irq_state,
1482         .process = smu_v13_0_irq_process,
1483 };
1484
1485 int smu_v13_0_register_irq_handler(struct smu_context *smu)
1486 {
1487         struct amdgpu_device *adev = smu->adev;
1488         struct amdgpu_irq_src *irq_src = &smu->irq_source;
1489         int ret = 0;
1490
1491         irq_src->num_types = 1;
1492         irq_src->funcs = &smu_v13_0_irq_funcs;
1493
1494         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1495                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1496                                 irq_src);
1497         if (ret)
1498                 return ret;
1499
1500         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1501                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1502                                 irq_src);
1503         if (ret)
1504                 return ret;
1505
1506         /* Register CTF(GPIO_19) interrupt */
1507         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1508                                 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1509                                 irq_src);
1510         if (ret)
1511                 return ret;
1512
1513         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1514                                 0xfe,
1515                                 irq_src);
1516         if (ret)
1517                 return ret;
1518
1519         return ret;
1520 }
1521
1522 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1523                                                struct pp_smu_nv_clock_table *max_clocks)
1524 {
1525         struct smu_table_context *table_context = &smu->smu_table;
1526         struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1527
1528         if (!max_clocks || !table_context->max_sustainable_clocks)
1529                 return -EINVAL;
1530
1531         sustainable_clocks = table_context->max_sustainable_clocks;
1532
1533         max_clocks->dcfClockInKhz =
1534                 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1535         max_clocks->displayClockInKhz =
1536                 (unsigned int) sustainable_clocks->display_clock * 1000;
1537         max_clocks->phyClockInKhz =
1538                 (unsigned int) sustainable_clocks->phy_clock * 1000;
1539         max_clocks->pixelClockInKhz =
1540                 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1541         max_clocks->uClockInKhz =
1542                 (unsigned int) sustainable_clocks->uclock * 1000;
1543         max_clocks->socClockInKhz =
1544                 (unsigned int) sustainable_clocks->soc_clock * 1000;
1545         max_clocks->dscClockInKhz = 0;
1546         max_clocks->dppClockInKhz = 0;
1547         max_clocks->fabricClockInKhz = 0;
1548
1549         return 0;
1550 }
1551
1552 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1553 {
1554         int ret = 0;
1555
1556         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1557
1558         return ret;
1559 }
1560
1561 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1562                                              uint64_t event_arg)
1563 {
1564         int ret = 0;
1565
1566         dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1567         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1568
1569         return ret;
1570 }
1571
1572 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1573                              uint64_t event_arg)
1574 {
1575         int ret = -EINVAL;
1576
1577         switch (event) {
1578         case SMU_EVENT_RESET_COMPLETE:
1579                 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1580                 break;
1581         default:
1582                 break;
1583         }
1584
1585         return ret;
1586 }
1587
1588 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1589                                     uint32_t *min, uint32_t *max)
1590 {
1591         int ret = 0, clk_id = 0;
1592         uint32_t param = 0;
1593         uint32_t clock_limit;
1594
1595         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1596                 switch (clk_type) {
1597                 case SMU_MCLK:
1598                 case SMU_UCLK:
1599                         clock_limit = smu->smu_table.boot_values.uclk;
1600                         break;
1601                 case SMU_GFXCLK:
1602                 case SMU_SCLK:
1603                         clock_limit = smu->smu_table.boot_values.gfxclk;
1604                         break;
1605                 case SMU_SOCCLK:
1606                         clock_limit = smu->smu_table.boot_values.socclk;
1607                         break;
1608                 default:
1609                         clock_limit = 0;
1610                         break;
1611                 }
1612
1613                 /* clock in Mhz unit */
1614                 if (min)
1615                         *min = clock_limit / 100;
1616                 if (max)
1617                         *max = clock_limit / 100;
1618
1619                 return 0;
1620         }
1621
1622         clk_id = smu_cmn_to_asic_specific_index(smu,
1623                                                 CMN2ASIC_MAPPING_CLK,
1624                                                 clk_type);
1625         if (clk_id < 0) {
1626                 ret = -EINVAL;
1627                 goto failed;
1628         }
1629         param = (clk_id & 0xffff) << 16;
1630
1631         if (max) {
1632                 if (smu->adev->pm.ac_power)
1633                         ret = smu_cmn_send_smc_msg_with_param(smu,
1634                                                               SMU_MSG_GetMaxDpmFreq,
1635                                                               param,
1636                                                               max);
1637                 else
1638                         ret = smu_cmn_send_smc_msg_with_param(smu,
1639                                                               SMU_MSG_GetDcModeMaxDpmFreq,
1640                                                               param,
1641                                                               max);
1642                 if (ret)
1643                         goto failed;
1644         }
1645
1646         if (min) {
1647                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1648                 if (ret)
1649                         goto failed;
1650         }
1651
1652 failed:
1653         return ret;
1654 }
1655
1656 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1657                                           enum smu_clk_type clk_type,
1658                                           uint32_t min,
1659                                           uint32_t max)
1660 {
1661         int ret = 0, clk_id = 0;
1662         uint32_t param;
1663
1664         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1665                 return 0;
1666
1667         clk_id = smu_cmn_to_asic_specific_index(smu,
1668                                                 CMN2ASIC_MAPPING_CLK,
1669                                                 clk_type);
1670         if (clk_id < 0)
1671                 return clk_id;
1672
1673         if (max > 0) {
1674                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1675                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1676                                                       param, NULL);
1677                 if (ret)
1678                         goto out;
1679         }
1680
1681         if (min > 0) {
1682                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1683                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1684                                                       param, NULL);
1685                 if (ret)
1686                         goto out;
1687         }
1688
1689 out:
1690         return ret;
1691 }
1692
1693 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1694                                           enum smu_clk_type clk_type,
1695                                           uint32_t min,
1696                                           uint32_t max)
1697 {
1698         int ret = 0, clk_id = 0;
1699         uint32_t param;
1700
1701         if (min <= 0 && max <= 0)
1702                 return -EINVAL;
1703
1704         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1705                 return 0;
1706
1707         clk_id = smu_cmn_to_asic_specific_index(smu,
1708                                                 CMN2ASIC_MAPPING_CLK,
1709                                                 clk_type);
1710         if (clk_id < 0)
1711                 return clk_id;
1712
1713         if (max > 0) {
1714                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1715                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1716                                                       param, NULL);
1717                 if (ret)
1718                         return ret;
1719         }
1720
1721         if (min > 0) {
1722                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1723                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1724                                                       param, NULL);
1725                 if (ret)
1726                         return ret;
1727         }
1728
1729         return ret;
1730 }
1731
1732 int smu_v13_0_set_performance_level(struct smu_context *smu,
1733                                     enum amd_dpm_forced_level level)
1734 {
1735         struct smu_13_0_dpm_context *dpm_context =
1736                 smu->smu_dpm.dpm_context;
1737         struct smu_13_0_dpm_table *gfx_table =
1738                 &dpm_context->dpm_tables.gfx_table;
1739         struct smu_13_0_dpm_table *mem_table =
1740                 &dpm_context->dpm_tables.uclk_table;
1741         struct smu_13_0_dpm_table *soc_table =
1742                 &dpm_context->dpm_tables.soc_table;
1743         struct smu_13_0_dpm_table *vclk_table =
1744                 &dpm_context->dpm_tables.vclk_table;
1745         struct smu_13_0_dpm_table *dclk_table =
1746                 &dpm_context->dpm_tables.dclk_table;
1747         struct smu_13_0_dpm_table *fclk_table =
1748                 &dpm_context->dpm_tables.fclk_table;
1749         struct smu_umd_pstate_table *pstate_table =
1750                 &smu->pstate_table;
1751         struct amdgpu_device *adev = smu->adev;
1752         uint32_t sclk_min = 0, sclk_max = 0;
1753         uint32_t mclk_min = 0, mclk_max = 0;
1754         uint32_t socclk_min = 0, socclk_max = 0;
1755         uint32_t vclk_min = 0, vclk_max = 0;
1756         uint32_t dclk_min = 0, dclk_max = 0;
1757         uint32_t fclk_min = 0, fclk_max = 0;
1758         int ret = 0, i;
1759
1760         switch (level) {
1761         case AMD_DPM_FORCED_LEVEL_HIGH:
1762                 sclk_min = sclk_max = gfx_table->max;
1763                 mclk_min = mclk_max = mem_table->max;
1764                 socclk_min = socclk_max = soc_table->max;
1765                 vclk_min = vclk_max = vclk_table->max;
1766                 dclk_min = dclk_max = dclk_table->max;
1767                 fclk_min = fclk_max = fclk_table->max;
1768                 break;
1769         case AMD_DPM_FORCED_LEVEL_LOW:
1770                 sclk_min = sclk_max = gfx_table->min;
1771                 mclk_min = mclk_max = mem_table->min;
1772                 socclk_min = socclk_max = soc_table->min;
1773                 vclk_min = vclk_max = vclk_table->min;
1774                 dclk_min = dclk_max = dclk_table->min;
1775                 fclk_min = fclk_max = fclk_table->min;
1776                 break;
1777         case AMD_DPM_FORCED_LEVEL_AUTO:
1778                 sclk_min = gfx_table->min;
1779                 sclk_max = gfx_table->max;
1780                 mclk_min = mem_table->min;
1781                 mclk_max = mem_table->max;
1782                 socclk_min = soc_table->min;
1783                 socclk_max = soc_table->max;
1784                 vclk_min = vclk_table->min;
1785                 vclk_max = vclk_table->max;
1786                 dclk_min = dclk_table->min;
1787                 dclk_max = dclk_table->max;
1788                 fclk_min = fclk_table->min;
1789                 fclk_max = fclk_table->max;
1790                 break;
1791         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1792                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1793                 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1794                 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1795                 vclk_min = vclk_max = pstate_table->vclk_pstate.standard;
1796                 dclk_min = dclk_max = pstate_table->dclk_pstate.standard;
1797                 fclk_min = fclk_max = pstate_table->fclk_pstate.standard;
1798                 break;
1799         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1800                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1801                 break;
1802         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1803                 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1804                 break;
1805         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1806                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1807                 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1808                 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1809                 vclk_min = vclk_max = pstate_table->vclk_pstate.peak;
1810                 dclk_min = dclk_max = pstate_table->dclk_pstate.peak;
1811                 fclk_min = fclk_max = pstate_table->fclk_pstate.peak;
1812                 break;
1813         case AMD_DPM_FORCED_LEVEL_MANUAL:
1814         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1815                 return 0;
1816         default:
1817                 dev_err(adev->dev, "Invalid performance level %d\n", level);
1818                 return -EINVAL;
1819         }
1820
1821         /*
1822          * Unset those settings for SMU 13.0.2. As soft limits settings
1823          * for those clock domains are not supported.
1824          */
1825         if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) {
1826                 mclk_min = mclk_max = 0;
1827                 socclk_min = socclk_max = 0;
1828                 vclk_min = vclk_max = 0;
1829                 dclk_min = dclk_max = 0;
1830                 fclk_min = fclk_max = 0;
1831         }
1832
1833         if (sclk_min && sclk_max) {
1834                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1835                                                             SMU_GFXCLK,
1836                                                             sclk_min,
1837                                                             sclk_max);
1838                 if (ret)
1839                         return ret;
1840
1841                 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1842                 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1843         }
1844
1845         if (mclk_min && mclk_max) {
1846                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1847                                                             SMU_MCLK,
1848                                                             mclk_min,
1849                                                             mclk_max);
1850                 if (ret)
1851                         return ret;
1852
1853                 pstate_table->uclk_pstate.curr.min = mclk_min;
1854                 pstate_table->uclk_pstate.curr.max = mclk_max;
1855         }
1856
1857         if (socclk_min && socclk_max) {
1858                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1859                                                             SMU_SOCCLK,
1860                                                             socclk_min,
1861                                                             socclk_max);
1862                 if (ret)
1863                         return ret;
1864
1865                 pstate_table->socclk_pstate.curr.min = socclk_min;
1866                 pstate_table->socclk_pstate.curr.max = socclk_max;
1867         }
1868
1869         if (vclk_min && vclk_max) {
1870                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1871                         if (adev->vcn.harvest_config & (1 << i))
1872                                 continue;
1873                         ret = smu_v13_0_set_soft_freq_limited_range(smu,
1874                                                                     i ? SMU_VCLK1 : SMU_VCLK,
1875                                                                     vclk_min,
1876                                                                     vclk_max);
1877                         if (ret)
1878                                 return ret;
1879                 }
1880                 pstate_table->vclk_pstate.curr.min = vclk_min;
1881                 pstate_table->vclk_pstate.curr.max = vclk_max;
1882         }
1883
1884         if (dclk_min && dclk_max) {
1885                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1886                         if (adev->vcn.harvest_config & (1 << i))
1887                                 continue;
1888                         ret = smu_v13_0_set_soft_freq_limited_range(smu,
1889                                                                     i ? SMU_DCLK1 : SMU_DCLK,
1890                                                                     dclk_min,
1891                                                                     dclk_max);
1892                         if (ret)
1893                                 return ret;
1894                 }
1895                 pstate_table->dclk_pstate.curr.min = dclk_min;
1896                 pstate_table->dclk_pstate.curr.max = dclk_max;
1897         }
1898
1899         if (fclk_min && fclk_max) {
1900                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1901                                                             SMU_FCLK,
1902                                                             fclk_min,
1903                                                             fclk_max);
1904                 if (ret)
1905                         return ret;
1906
1907                 pstate_table->fclk_pstate.curr.min = fclk_min;
1908                 pstate_table->fclk_pstate.curr.max = fclk_max;
1909         }
1910
1911         return ret;
1912 }
1913
1914 int smu_v13_0_set_power_source(struct smu_context *smu,
1915                                enum smu_power_src_type power_src)
1916 {
1917         int pwr_source;
1918
1919         pwr_source = smu_cmn_to_asic_specific_index(smu,
1920                                                     CMN2ASIC_MAPPING_PWR,
1921                                                     (uint32_t)power_src);
1922         if (pwr_source < 0)
1923                 return -EINVAL;
1924
1925         return smu_cmn_send_smc_msg_with_param(smu,
1926                                                SMU_MSG_NotifyPowerSource,
1927                                                pwr_source,
1928                                                NULL);
1929 }
1930
1931 static int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1932                                            enum smu_clk_type clk_type,
1933                                            uint16_t level,
1934                                            uint32_t *value)
1935 {
1936         int ret = 0, clk_id = 0;
1937         uint32_t param;
1938
1939         if (!value)
1940                 return -EINVAL;
1941
1942         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1943                 return 0;
1944
1945         clk_id = smu_cmn_to_asic_specific_index(smu,
1946                                                 CMN2ASIC_MAPPING_CLK,
1947                                                 clk_type);
1948         if (clk_id < 0)
1949                 return clk_id;
1950
1951         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1952
1953         ret = smu_cmn_send_smc_msg_with_param(smu,
1954                                               SMU_MSG_GetDpmFreqByIndex,
1955                                               param,
1956                                               value);
1957         if (ret)
1958                 return ret;
1959
1960         *value = *value & 0x7fffffff;
1961
1962         return ret;
1963 }
1964
1965 static int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1966                                          enum smu_clk_type clk_type,
1967                                          uint32_t *value)
1968 {
1969         int ret;
1970
1971         ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1972         /* SMU v13.0.2 FW returns 0 based max level, increment by one for it */
1973         if((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) && (!ret && value))
1974                 ++(*value);
1975
1976         return ret;
1977 }
1978
1979 static int smu_v13_0_get_fine_grained_status(struct smu_context *smu,
1980                                              enum smu_clk_type clk_type,
1981                                              bool *is_fine_grained_dpm)
1982 {
1983         int ret = 0, clk_id = 0;
1984         uint32_t param;
1985         uint32_t value;
1986
1987         if (!is_fine_grained_dpm)
1988                 return -EINVAL;
1989
1990         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1991                 return 0;
1992
1993         clk_id = smu_cmn_to_asic_specific_index(smu,
1994                                                 CMN2ASIC_MAPPING_CLK,
1995                                                 clk_type);
1996         if (clk_id < 0)
1997                 return clk_id;
1998
1999         param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);
2000
2001         ret = smu_cmn_send_smc_msg_with_param(smu,
2002                                               SMU_MSG_GetDpmFreqByIndex,
2003                                               param,
2004                                               &value);
2005         if (ret)
2006                 return ret;
2007
2008         /*
2009          * BIT31:  1 - Fine grained DPM, 0 - Dicrete DPM
2010          * now, we un-support it
2011          */
2012         *is_fine_grained_dpm = value & 0x80000000;
2013
2014         return 0;
2015 }
2016
2017 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
2018                                    enum smu_clk_type clk_type,
2019                                    struct smu_13_0_dpm_table *single_dpm_table)
2020 {
2021         int ret = 0;
2022         uint32_t clk;
2023         int i;
2024
2025         ret = smu_v13_0_get_dpm_level_count(smu,
2026                                             clk_type,
2027                                             &single_dpm_table->count);
2028         if (ret) {
2029                 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
2030                 return ret;
2031         }
2032
2033         if (smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 2)) {
2034                 ret = smu_v13_0_get_fine_grained_status(smu,
2035                                                         clk_type,
2036                                                         &single_dpm_table->is_fine_grained);
2037                 if (ret) {
2038                         dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
2039                         return ret;
2040                 }
2041         }
2042
2043         for (i = 0; i < single_dpm_table->count; i++) {
2044                 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2045                                                       clk_type,
2046                                                       i,
2047                                                       &clk);
2048                 if (ret) {
2049                         dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
2050                         return ret;
2051                 }
2052
2053                 single_dpm_table->dpm_levels[i].value = clk;
2054                 single_dpm_table->dpm_levels[i].enabled = true;
2055
2056                 if (i == 0)
2057                         single_dpm_table->min = clk;
2058                 else if (i == single_dpm_table->count - 1)
2059                         single_dpm_table->max = clk;
2060         }
2061
2062         return 0;
2063 }
2064
2065 int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
2066                                   enum smu_clk_type clk_type,
2067                                   uint32_t *min_value,
2068                                   uint32_t *max_value)
2069 {
2070         uint32_t level_count = 0;
2071         int ret = 0;
2072
2073         if (!min_value && !max_value)
2074                 return -EINVAL;
2075
2076         if (min_value) {
2077                 /* by default, level 0 clock value as min value */
2078                 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2079                                                       clk_type,
2080                                                       0,
2081                                                       min_value);
2082                 if (ret)
2083                         return ret;
2084         }
2085
2086         if (max_value) {
2087                 ret = smu_v13_0_get_dpm_level_count(smu,
2088                                                     clk_type,
2089                                                     &level_count);
2090                 if (ret)
2091                         return ret;
2092
2093                 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2094                                                       clk_type,
2095                                                       level_count - 1,
2096                                                       max_value);
2097                 if (ret)
2098                         return ret;
2099         }
2100
2101         return ret;
2102 }
2103
2104 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
2105 {
2106         struct amdgpu_device *adev = smu->adev;
2107
2108         return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2109                 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2110                 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2111 }
2112
2113 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
2114 {
2115         uint32_t width_level;
2116
2117         width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
2118         if (width_level > LINK_WIDTH_MAX)
2119                 width_level = 0;
2120
2121         return link_width[width_level];
2122 }
2123
2124 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2125 {
2126         struct amdgpu_device *adev = smu->adev;
2127
2128         return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2129                 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2130                 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2131 }
2132
2133 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
2134 {
2135         uint32_t speed_level;
2136
2137         speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
2138         if (speed_level > LINK_SPEED_MAX)
2139                 speed_level = 0;
2140
2141         return link_speed[speed_level];
2142 }
2143
2144 int smu_v13_0_set_vcn_enable(struct smu_context *smu,
2145                              bool enable)
2146 {
2147         struct amdgpu_device *adev = smu->adev;
2148         int i, ret = 0;
2149
2150         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2151                 if (adev->vcn.harvest_config & (1 << i))
2152                         continue;
2153
2154                 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
2155                                                       SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
2156                                                       i << 16U, NULL);
2157                 if (ret)
2158                         return ret;
2159         }
2160
2161         return ret;
2162 }
2163
2164 int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
2165                               bool enable)
2166 {
2167         return smu_cmn_send_smc_msg_with_param(smu, enable ?
2168                                                SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
2169                                                0, NULL);
2170 }
2171
2172 int smu_v13_0_run_btc(struct smu_context *smu)
2173 {
2174         int res;
2175
2176         res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2177         if (res)
2178                 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2179
2180         return res;
2181 }
2182
2183 int smu_v13_0_deep_sleep_control(struct smu_context *smu,
2184                                  bool enablement)
2185 {
2186         struct amdgpu_device *adev = smu->adev;
2187         int ret = 0;
2188
2189         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2190                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2191                 if (ret) {
2192                         dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2193                         return ret;
2194                 }
2195         }
2196
2197         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2198                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2199                 if (ret) {
2200                         dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2201                         return ret;
2202                 }
2203         }
2204
2205         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2206                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2207                 if (ret) {
2208                         dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2209                         return ret;
2210                 }
2211         }
2212
2213         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2214                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2215                 if (ret) {
2216                         dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2217                         return ret;
2218                 }
2219         }
2220
2221         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2222                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2223                 if (ret) {
2224                         dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2225                         return ret;
2226                 }
2227         }
2228
2229         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
2230                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
2231                 if (ret) {
2232                         dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
2233                         return ret;
2234                 }
2235         }
2236
2237         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
2238                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
2239                 if (ret) {
2240                         dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
2241                         return ret;
2242                 }
2243         }
2244
2245         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
2246                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
2247                 if (ret) {
2248                         dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
2249                         return ret;
2250                 }
2251         }
2252
2253         return ret;
2254 }
2255
2256 int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
2257                               bool enablement)
2258 {
2259         int ret = 0;
2260
2261         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2262                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2263
2264         return ret;
2265 }
2266
2267 bool smu_v13_0_baco_is_support(struct smu_context *smu)
2268 {
2269         struct smu_baco_context *smu_baco = &smu->smu_baco;
2270
2271         if (amdgpu_sriov_vf(smu->adev) ||
2272             !smu_baco->platform_support)
2273                 return false;
2274
2275         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
2276             !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
2277                 return false;
2278
2279         return true;
2280 }
2281
2282 enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu)
2283 {
2284         struct smu_baco_context *smu_baco = &smu->smu_baco;
2285
2286         return smu_baco->state;
2287 }
2288
2289 int smu_v13_0_baco_set_state(struct smu_context *smu,
2290                              enum smu_baco_state state)
2291 {
2292         struct smu_baco_context *smu_baco = &smu->smu_baco;
2293         struct amdgpu_device *adev = smu->adev;
2294         int ret = 0;
2295
2296         if (smu_v13_0_baco_get_state(smu) == state)
2297                 return 0;
2298
2299         if (state == SMU_BACO_STATE_ENTER) {
2300                 ret = smu_cmn_send_smc_msg_with_param(smu,
2301                                                       SMU_MSG_EnterBaco,
2302                                                       smu_baco->maco_support ?
2303                                                       BACO_SEQ_BAMACO : BACO_SEQ_BACO,
2304                                                       NULL);
2305         } else {
2306                 ret = smu_cmn_send_smc_msg(smu,
2307                                            SMU_MSG_ExitBaco,
2308                                            NULL);
2309                 if (ret)
2310                         return ret;
2311
2312                 /* clear vbios scratch 6 and 7 for coming asic reinit */
2313                 WREG32(adev->bios_scratch_reg_offset + 6, 0);
2314                 WREG32(adev->bios_scratch_reg_offset + 7, 0);
2315         }
2316
2317         if (!ret)
2318                 smu_baco->state = state;
2319
2320         return ret;
2321 }
2322
2323 int smu_v13_0_baco_enter(struct smu_context *smu)
2324 {
2325         int ret = 0;
2326
2327         ret = smu_v13_0_baco_set_state(smu,
2328                                        SMU_BACO_STATE_ENTER);
2329         if (ret)
2330                 return ret;
2331
2332         msleep(10);
2333
2334         return ret;
2335 }
2336
2337 int smu_v13_0_baco_exit(struct smu_context *smu)
2338 {
2339         return smu_v13_0_baco_set_state(smu,
2340                                         SMU_BACO_STATE_EXIT);
2341 }
2342
2343 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu)
2344 {
2345         uint16_t index;
2346
2347         index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2348                                                SMU_MSG_EnableGfxImu);
2349
2350         return smu_cmn_send_msg_without_waiting(smu, index, 0);
2351 }
2352
2353 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
2354                                 enum PP_OD_DPM_TABLE_COMMAND type,
2355                                 long input[], uint32_t size)
2356 {
2357         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2358         int ret = 0;
2359
2360         /* Only allowed in manual mode */
2361         if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
2362                 return -EINVAL;
2363
2364         switch (type) {
2365         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2366                 if (size != 2) {
2367                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
2368                         return -EINVAL;
2369                 }
2370
2371                 if (input[0] == 0) {
2372                         if (input[1] < smu->gfx_default_hard_min_freq) {
2373                                 dev_warn(smu->adev->dev,
2374                                          "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2375                                          input[1], smu->gfx_default_hard_min_freq);
2376                                 return -EINVAL;
2377                         }
2378                         smu->gfx_actual_hard_min_freq = input[1];
2379                 } else if (input[0] == 1) {
2380                         if (input[1] > smu->gfx_default_soft_max_freq) {
2381                                 dev_warn(smu->adev->dev,
2382                                          "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2383                                          input[1], smu->gfx_default_soft_max_freq);
2384                                 return -EINVAL;
2385                         }
2386                         smu->gfx_actual_soft_max_freq = input[1];
2387                 } else {
2388                         return -EINVAL;
2389                 }
2390                 break;
2391         case PP_OD_RESTORE_DEFAULT_TABLE:
2392                 if (size != 0) {
2393                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
2394                         return -EINVAL;
2395                 }
2396                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2397                 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2398                 break;
2399         case PP_OD_COMMIT_DPM_TABLE:
2400                 if (size != 0) {
2401                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
2402                         return -EINVAL;
2403                 }
2404                 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2405                         dev_err(smu->adev->dev,
2406                                 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2407                                 smu->gfx_actual_hard_min_freq,
2408                                 smu->gfx_actual_soft_max_freq);
2409                         return -EINVAL;
2410                 }
2411
2412                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2413                                                       smu->gfx_actual_hard_min_freq,
2414                                                       NULL);
2415                 if (ret) {
2416                         dev_err(smu->adev->dev, "Set hard min sclk failed!");
2417                         return ret;
2418                 }
2419
2420                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2421                                                       smu->gfx_actual_soft_max_freq,
2422                                                       NULL);
2423                 if (ret) {
2424                         dev_err(smu->adev->dev, "Set soft max sclk failed!");
2425                         return ret;
2426                 }
2427                 break;
2428         default:
2429                 return -ENOSYS;
2430         }
2431
2432         return ret;
2433 }
2434
2435 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu)
2436 {
2437         struct smu_table_context *smu_table = &smu->smu_table;
2438
2439         return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
2440                                     smu_table->clocks_table, false);
2441 }
2442
2443 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu)
2444 {
2445         struct amdgpu_device *adev = smu->adev;
2446
2447         smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2448         smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2449         smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2450 }
2451
2452 int smu_v13_0_mode1_reset(struct smu_context *smu)
2453 {
2454         int ret = 0;
2455
2456         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
2457         if (!ret)
2458                 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2459
2460         return ret;
2461 }