drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include <linux/pci.h>
  28 #include <linux/i2c.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_dpm.h"
  31 #include "amdgpu_smu.h"
  32 #include "atomfirmware.h"
  33 #include "amdgpu_atomfirmware.h"
  34 #include "amdgpu_atombios.h"
  35 #include "smu_v11_0.h"
  36 #include "smu11_driver_if_sienna_cichlid.h"
  37 #include "soc15_common.h"
  38 #include "atom.h"
  39 #include "sienna_cichlid_ppt.h"
  40 #include "smu_v11_0_7_pptable.h"
  41 #include "smu_v11_0_7_ppsmc.h"
  42 #include "nbio/nbio_2_3_offset.h"
  43 #include "nbio/nbio_2_3_sh_mask.h"
  44 #include "thm/thm_11_0_2_offset.h"
  45 #include "thm/thm_11_0_2_sh_mask.h"
  46 #include "mp/mp_11_0_offset.h"
  47 #include "mp/mp_11_0_sh_mask.h"
  48
  49 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  50 #include "amdgpu_ras.h"
  51 #include "smu_cmn.h"
  52
  53 /*
  54  * DO NOT use these for err/warn/info/debug messages.
  55  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  56  * They are more MGPU friendly.
  57  */
  58 #undef pr_err
  59 #undef pr_warn
  60 #undef pr_info
  61 #undef pr_debug
  62
  63 #define FEATURE_MASK(feature) (1ULL << feature)
  64 #define SMC_DPM_FEATURE ( \
  65         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  66         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  67         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  68         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  69         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  70         FEATURE_MASK(FEATURE_DPM_FCLK_BIT)       | \
  71         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)    | \
  72         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
  73
  74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
  75
  76 #define GET_PPTABLE_MEMBER(field, member)                                    \
  77         do {                                                                 \
  78                 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==             \
  79                     IP_VERSION(11, 0, 13))                                   \
  80                         (*member) = (smu->smu_table.driver_pptable +         \
  81                                      offsetof(PPTable_beige_goby_t, field)); \
  82                 else                                                         \
  83                         (*member) = (smu->smu_table.driver_pptable +         \
  84                                      offsetof(PPTable_t, field));            \
  85         } while (0)
  86
  87 /* STB FIFO depth is in 64bit units */
  88 #define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8
  89
  90 /*
  91  * SMU support ECCTABLE since version 58.70.0,
  92  * use this to check whether ECCTABLE feature is supported.
  93  */
  94 #define SUPPORT_ECCTABLE_SMU_VERSION 0x003a4600
  95
  96 static int get_table_size(struct smu_context *smu)
  97 {
  98         if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
  99                 return sizeof(PPTable_beige_goby_t);
 100         else
 101                 return sizeof(PPTable_t);
 102 }
 103
 104 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
 105         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                 1),
 106         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,               1),
 107         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,          1),
 108         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,   0),
 109         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,  0),
 110         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,        0),
 111         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,       0),
 112         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,        1),
 113         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,       1),
 114         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,       1),
 115         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,      1),
 116         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow,    1),
 117         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetRunningSmuFeaturesHigh,   1),
 118         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,             1),
 119         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                 0),
 120         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,       1),
 121         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,        1),
 122         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,        0),
 123         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,         0),
 124         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,       1),
 125         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,       0),
 126         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,           0),
 127         MSG_MAP(RunDcBtc,                       PPSMC_MSG_RunDcBtc,                    0),
 128         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                   0),
 129         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,            1),
 130         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,            1),
 131         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,            1),
 132         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,            0),
 133         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,               1),
 134         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,               1),
 135         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,           1),
 136         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode,               0),
 137         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh,       0),
 138         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow,        0),
 139         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,      0),
 140         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt,       0),
 141         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource,           0),
 142         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch,           0),
 143         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps,                 0),
 144         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,         1),
 145         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                 0),
 146         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,              0),
 147         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                 0),
 148         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,         1),
 149         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco,                    0),
 150         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                  0),
 151         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                0),
 152         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                 0),
 153         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,               0),
 154         MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME,              0),
 155         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3,                       0),
 156         MSG_MAP(Mode1Reset,                     PPSMC_MSG_Mode1Reset,                  0),
 157         MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
 158         MSG_MAP(SetGpoFeaturePMask,             PPSMC_MSG_SetGpoFeaturePMask,          0),
 159         MSG_MAP(DisallowGpo,                    PPSMC_MSG_DisallowGpo,                 0),
 160         MSG_MAP(Enable2ndUSB20Port,             PPSMC_MSG_Enable2ndUSB20Port,          0),
 161         MSG_MAP(DriverMode2Reset,               PPSMC_MSG_DriverMode2Reset,            0),
 162 };
 163
 164 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
 165         CLK_MAP(GFXCLK,         PPCLK_GFXCLK),
 166         CLK_MAP(SCLK,           PPCLK_GFXCLK),
 167         CLK_MAP(SOCCLK,         PPCLK_SOCCLK),
 168         CLK_MAP(FCLK,           PPCLK_FCLK),
 169         CLK_MAP(UCLK,           PPCLK_UCLK),
 170         CLK_MAP(MCLK,           PPCLK_UCLK),
 171         CLK_MAP(DCLK,           PPCLK_DCLK_0),
 172         CLK_MAP(DCLK1,          PPCLK_DCLK_1),
 173         CLK_MAP(VCLK,           PPCLK_VCLK_0),
 174         CLK_MAP(VCLK1,          PPCLK_VCLK_1),
 175         CLK_MAP(DCEFCLK,        PPCLK_DCEFCLK),
 176         CLK_MAP(DISPCLK,        PPCLK_DISPCLK),
 177         CLK_MAP(PIXCLK,         PPCLK_PIXCLK),
 178         CLK_MAP(PHYCLK,         PPCLK_PHYCLK),
 179 };
 180
 181 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
 182         FEA_MAP(DPM_PREFETCHER),
 183         FEA_MAP(DPM_GFXCLK),
 184         FEA_MAP(DPM_GFX_GPO),
 185         FEA_MAP(DPM_UCLK),
 186         FEA_MAP(DPM_FCLK),
 187         FEA_MAP(DPM_SOCCLK),
 188         FEA_MAP(DPM_MP0CLK),
 189         FEA_MAP(DPM_LINK),
 190         FEA_MAP(DPM_DCEFCLK),
 191         FEA_MAP(DPM_XGMI),
 192         FEA_MAP(MEM_VDDCI_SCALING),
 193         FEA_MAP(MEM_MVDD_SCALING),
 194         FEA_MAP(DS_GFXCLK),
 195         FEA_MAP(DS_SOCCLK),
 196         FEA_MAP(DS_FCLK),
 197         FEA_MAP(DS_LCLK),
 198         FEA_MAP(DS_DCEFCLK),
 199         FEA_MAP(DS_UCLK),
 200         FEA_MAP(GFX_ULV),
 201         FEA_MAP(FW_DSTATE),
 202         FEA_MAP(GFXOFF),
 203         FEA_MAP(BACO),
 204         FEA_MAP(MM_DPM_PG),
 205         FEA_MAP(RSMU_SMN_CG),
 206         FEA_MAP(PPT),
 207         FEA_MAP(TDC),
 208         FEA_MAP(APCC_PLUS),
 209         FEA_MAP(GTHR),
 210         FEA_MAP(ACDC),
 211         FEA_MAP(VR0HOT),
 212         FEA_MAP(VR1HOT),
 213         FEA_MAP(FW_CTF),
 214         FEA_MAP(FAN_CONTROL),
 215         FEA_MAP(THERMAL),
 216         FEA_MAP(GFX_DCS),
 217         FEA_MAP(RM),
 218         FEA_MAP(LED_DISPLAY),
 219         FEA_MAP(GFX_SS),
 220         FEA_MAP(OUT_OF_BAND_MONITOR),
 221         FEA_MAP(TEMP_DEPENDENT_VMIN),
 222         FEA_MAP(MMHUB_PG),
 223         FEA_MAP(ATHUB_PG),
 224         FEA_MAP(APCC_DFLL),
 225 };
 226
 227 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
 228         TAB_MAP(PPTABLE),
 229         TAB_MAP(WATERMARKS),
 230         TAB_MAP(AVFS_PSM_DEBUG),
 231         TAB_MAP(AVFS_FUSE_OVERRIDE),
 232         TAB_MAP(PMSTATUSLOG),
 233         TAB_MAP(SMU_METRICS),
 234         TAB_MAP(DRIVER_SMU_CONFIG),
 235         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 236         TAB_MAP(OVERDRIVE),
 237         TAB_MAP(I2C_COMMANDS),
 238         TAB_MAP(PACE),
 239         TAB_MAP(ECCINFO),
 240 };
 241
 242 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 243         PWR_MAP(AC),
 244         PWR_MAP(DC),
 245 };
 246
 247 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 248         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 249         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 250         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 251         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 252         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 253         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 254         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 255 };
 256
 257 static const uint8_t sienna_cichlid_throttler_map[] = {
 258         [THROTTLER_TEMP_EDGE_BIT]       = (SMU_THROTTLER_TEMP_EDGE_BIT),
 259         [THROTTLER_TEMP_HOTSPOT_BIT]    = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
 260         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 261         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 262         [THROTTLER_TEMP_VR_MEM0_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 263         [THROTTLER_TEMP_VR_MEM1_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
 264         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 265         [THROTTLER_TEMP_LIQUID0_BIT]    = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
 266         [THROTTLER_TEMP_LIQUID1_BIT]    = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
 267         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 268         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 269         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 270         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 271         [THROTTLER_PPT2_BIT]            = (SMU_THROTTLER_PPT2_BIT),
 272         [THROTTLER_PPT3_BIT]            = (SMU_THROTTLER_PPT3_BIT),
 273         [THROTTLER_FIT_BIT]             = (SMU_THROTTLER_FIT_BIT),
 274         [THROTTLER_PPM_BIT]             = (SMU_THROTTLER_PPM_BIT),
 275         [THROTTLER_APCC_BIT]            = (SMU_THROTTLER_APCC_BIT),
 276 };
 277
 278 static int
 279 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 280                                   uint32_t *feature_mask, uint32_t num)
 281 {
 282         struct amdgpu_device *adev = smu->adev;
 283
 284         if (num > 2)
 285                 return -EINVAL;
 286
 287         memset(feature_mask, 0, sizeof(uint32_t) * num);
 288
 289         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 290                                 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
 291                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 292                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 293                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 294                                 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
 295                                 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
 296                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 297                                 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
 298                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 299                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 300                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 301                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 302                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 303                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 304                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 305                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 306                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 307                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 308                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 309
 310         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
 311                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 312                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
 313         }
 314
 315         if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
 316             (amdgpu_ip_version(adev, MP1_HWIP, 0) > IP_VERSION(11, 0, 7)) &&
 317             !(adev->flags & AMD_IS_APU))
 318                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
 319
 320         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 321                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 322                                         | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 323                                         | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 324
 325         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 326                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 327
 328         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 329                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 330
 331         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 332                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 333
 334         if (adev->pm.pp_feature & PP_ULV_MASK)
 335                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 336
 337         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 338                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 339
 340         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 341                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 342
 343         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 344                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 345
 346         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 347                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 348
 349         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
 350             smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 351                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
 352
 353         if (smu->dc_controlled_by_gpio)
 354        *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
 355
 356         if (amdgpu_device_should_use_aspm(adev))
 357                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
 358
 359         return 0;
 360 }
 361
 362 static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
 363 {
 364         struct smu_table_context *table_context = &smu->smu_table;
 365         struct smu_11_0_7_powerplay_table *powerplay_table =
 366                 table_context->power_play_table;
 367         struct smu_baco_context *smu_baco = &smu->smu_baco;
 368         struct amdgpu_device *adev = smu->adev;
 369         uint32_t val;
 370
 371         if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
 372                 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
 373                 smu_baco->platform_support =
 374                         (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
 375                                                                         false;
 376
 377                 /*
 378                  * Disable BACO entry/exit completely on below SKUs to
 379                  * avoid hardware intermittent failures.
 380                  */
 381                 if (((adev->pdev->device == 0x73A1) &&
 382                     (adev->pdev->revision == 0x00)) ||
 383                     ((adev->pdev->device == 0x73BF) &&
 384                     (adev->pdev->revision == 0xCF)) ||
 385                     ((adev->pdev->device == 0x7422) &&
 386                     (adev->pdev->revision == 0x00)) ||
 387                     ((adev->pdev->device == 0x73A3) &&
 388                     (adev->pdev->revision == 0x00)) ||
 389                     ((adev->pdev->device == 0x73E3) &&
 390                     (adev->pdev->revision == 0x00)))
 391                         smu_baco->platform_support = false;
 392
 393         }
 394 }
 395
 396 static void sienna_cichlid_check_fan_support(struct smu_context *smu)
 397 {
 398         struct smu_table_context *table_context = &smu->smu_table;
 399         PPTable_t *pptable = table_context->driver_pptable;
 400         uint64_t features = *(uint64_t *) pptable->FeaturesToRun;
 401
 402         /* Fan control is not possible if PPTable has it disabled */
 403         smu->adev->pm.no_fan =
 404                 !(features & (1ULL << FEATURE_FAN_CONTROL_BIT));
 405         if (smu->adev->pm.no_fan)
 406                 dev_info_once(smu->adev->dev,
 407                               "PMFW based fan control disabled");
 408 }
 409
 410 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
 411 {
 412         struct smu_table_context *table_context = &smu->smu_table;
 413         struct smu_11_0_7_powerplay_table *powerplay_table =
 414                 table_context->power_play_table;
 415
 416         if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
 417                 smu->dc_controlled_by_gpio = true;
 418
 419         sienna_cichlid_check_bxco_support(smu);
 420         sienna_cichlid_check_fan_support(smu);
 421
 422         table_context->thermal_controller_type =
 423                 powerplay_table->thermal_controller_type;
 424
 425         /*
 426          * Instead of having its own buffer space and get overdrive_table copied,
 427          * smu->od_settings just points to the actual overdrive_table
 428          */
 429         smu->od_settings = &powerplay_table->overdrive_table;
 430
 431         return 0;
 432 }
 433
 434 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
 435 {
 436         struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
 437         int index, ret;
 438         PPTable_beige_goby_t *ppt_beige_goby;
 439         PPTable_t *ppt;
 440
 441         if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
 442                 ppt_beige_goby = smu->smu_table.driver_pptable;
 443         else
 444                 ppt = smu->smu_table.driver_pptable;
 445
 446         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 447                                             smc_dpm_info);
 448
 449         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 450                                       (uint8_t **)&smc_dpm_table);
 451         if (ret)
 452                 return ret;
 453
 454         if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
 455                 smu_memcpy_trailing(ppt_beige_goby, I2cControllers, BoardReserved,
 456                                     smc_dpm_table, I2cControllers);
 457         else
 458                 smu_memcpy_trailing(ppt, I2cControllers, BoardReserved,
 459                                     smc_dpm_table, I2cControllers);
 460
 461         return 0;
 462 }
 463
 464 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
 465 {
 466         struct smu_table_context *table_context = &smu->smu_table;
 467         struct smu_11_0_7_powerplay_table *powerplay_table =
 468                 table_context->power_play_table;
 469         int table_size;
 470
 471         table_size = get_table_size(smu);
 472         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 473                table_size);
 474
 475         return 0;
 476 }
 477
 478 static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu)
 479 {
 480         struct amdgpu_device *adev = smu->adev;
 481         uint32_t *board_reserved;
 482         uint16_t *freq_table_gfx;
 483         uint32_t i;
 484
 485         /* Fix some OEM SKU specific stability issues */
 486         GET_PPTABLE_MEMBER(BoardReserved, &board_reserved);
 487         if ((adev->pdev->device == 0x73DF) &&
 488             (adev->pdev->revision == 0XC3) &&
 489             (adev->pdev->subsystem_device == 0x16C2) &&
 490             (adev->pdev->subsystem_vendor == 0x1043))
 491                 board_reserved[0] = 1387;
 492
 493         GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx);
 494         if ((adev->pdev->device == 0x73DF) &&
 495             (adev->pdev->revision == 0XC3) &&
 496             ((adev->pdev->subsystem_device == 0x16C2) ||
 497             (adev->pdev->subsystem_device == 0x133C)) &&
 498             (adev->pdev->subsystem_vendor == 0x1043)) {
 499                 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) {
 500                         if (freq_table_gfx[i] > 2500)
 501                                 freq_table_gfx[i] = 2500;
 502                 }
 503         }
 504
 505         return 0;
 506 }
 507
 508 static int sienna_cichlid_setup_pptable(struct smu_context *smu)
 509 {
 510         int ret = 0;
 511
 512         ret = smu_v11_0_setup_pptable(smu);
 513         if (ret)
 514                 return ret;
 515
 516         ret = sienna_cichlid_store_powerplay_table(smu);
 517         if (ret)
 518                 return ret;
 519
 520         ret = sienna_cichlid_append_powerplay_table(smu);
 521         if (ret)
 522                 return ret;
 523
 524         ret = sienna_cichlid_check_powerplay_table(smu);
 525         if (ret)
 526                 return ret;
 527
 528         return sienna_cichlid_patch_pptable_quirk(smu);
 529 }
 530
 531 static int sienna_cichlid_tables_init(struct smu_context *smu)
 532 {
 533         struct smu_table_context *smu_table = &smu->smu_table;
 534         struct smu_table *tables = smu_table->tables;
 535         int table_size;
 536
 537         table_size = get_table_size(smu);
 538         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
 539                                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 540         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 541                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 542         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
 543                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 544         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 545                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 546         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 547                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 548         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 549                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 550         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 551                        sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
 552                        AMDGPU_GEM_DOMAIN_VRAM);
 553         SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
 554                         PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 555         SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfigExternal_t),
 556                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 557
 558         smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
 559         if (!smu_table->metrics_table)
 560                 goto err0_out;
 561         smu_table->metrics_time = 0;
 562
 563         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 564         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 565         if (!smu_table->gpu_metrics_table)
 566                 goto err1_out;
 567
 568         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 569         if (!smu_table->watermarks_table)
 570                 goto err2_out;
 571
 572         smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
 573         if (!smu_table->ecc_table)
 574                 goto err3_out;
 575
 576         smu_table->driver_smu_config_table =
 577                 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL);
 578         if (!smu_table->driver_smu_config_table)
 579                 goto err4_out;
 580
 581         return 0;
 582
 583 err4_out:
 584         kfree(smu_table->ecc_table);
 585 err3_out:
 586         kfree(smu_table->watermarks_table);
 587 err2_out:
 588         kfree(smu_table->gpu_metrics_table);
 589 err1_out:
 590         kfree(smu_table->metrics_table);
 591 err0_out:
 592         return -ENOMEM;
 593 }
 594
 595 static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu,
 596                                                            bool use_metrics_v3,
 597                                                            bool use_metrics_v2)
 598 {
 599         struct smu_table_context *smu_table= &smu->smu_table;
 600         SmuMetricsExternal_t *metrics_ext =
 601                 (SmuMetricsExternal_t *)(smu_table->metrics_table);
 602         uint32_t throttler_status = 0;
 603         int i;
 604
 605         if (use_metrics_v3) {
 606                 for (i = 0; i < THROTTLER_COUNT; i++)
 607                         throttler_status |=
 608                                 (metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
 609         } else if (use_metrics_v2) {
 610                 for (i = 0; i < THROTTLER_COUNT; i++)
 611                         throttler_status |=
 612                                 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
 613         } else {
 614                 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus;
 615         }
 616
 617         return throttler_status;
 618 }
 619
 620 static int sienna_cichlid_get_power_limit(struct smu_context *smu,
 621                                           uint32_t *current_power_limit,
 622                                           uint32_t *default_power_limit,
 623                                           uint32_t *max_power_limit)
 624 {
 625         struct smu_11_0_7_powerplay_table *powerplay_table =
 626                 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
 627         uint32_t power_limit, od_percent;
 628         uint16_t *table_member;
 629
 630         GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
 631
 632         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
 633                 power_limit =
 634                         table_member[PPT_THROTTLER_PPT0];
 635         }
 636
 637         if (current_power_limit)
 638                 *current_power_limit = power_limit;
 639         if (default_power_limit)
 640                 *default_power_limit = power_limit;
 641
 642         if (max_power_limit) {
 643                 if (smu->od_enabled) {
 644                         od_percent =
 645                                 le32_to_cpu(powerplay_table->overdrive_table.max[
 646                                                         SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
 647
 648                         dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n",
 649                                         od_percent, power_limit);
 650
 651                         power_limit *= (100 + od_percent);
 652                         power_limit /= 100;
 653                 }
 654                 *max_power_limit = power_limit;
 655         }
 656
 657         return 0;
 658 }
 659
 660 static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *smu,
 661                                         uint32_t *apu_percent,
 662                                         uint32_t *dgpu_percent)
 663 {
 664         struct smu_table_context *smu_table = &smu->smu_table;
 665         SmuMetrics_V4_t *metrics_v4 =
 666                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V4);
 667         uint16_t powerRatio = 0;
 668         uint16_t apu_power_limit = 0;
 669         uint16_t dgpu_power_limit = 0;
 670         uint32_t apu_boost = 0;
 671         uint32_t dgpu_boost = 0;
 672         uint32_t cur_power_limit;
 673
 674         if (metrics_v4->ApuSTAPMSmartShiftLimit != 0) {
 675                 sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL, NULL);
 676                 apu_power_limit = metrics_v4->ApuSTAPMLimit;
 677                 dgpu_power_limit = cur_power_limit;
 678                 powerRatio = (((apu_power_limit +
 679                                                   dgpu_power_limit) * 100) /
 680                                                   metrics_v4->ApuSTAPMSmartShiftLimit);
 681                 if (powerRatio > 100) {
 682                         apu_power_limit = (apu_power_limit * 100) /
 683                                                                          powerRatio;
 684                         dgpu_power_limit = (dgpu_power_limit * 100) /
 685                                                                           powerRatio;
 686                 }
 687                 if (metrics_v4->AverageApuSocketPower > apu_power_limit &&
 688                          apu_power_limit != 0) {
 689                         apu_boost = ((metrics_v4->AverageApuSocketPower -
 690                                                         apu_power_limit) * 100) /
 691                                                         apu_power_limit;
 692                         if (apu_boost > 100)
 693                                 apu_boost = 100;
 694                 }
 695
 696                 if (metrics_v4->AverageSocketPower > dgpu_power_limit &&
 697                          dgpu_power_limit != 0) {
 698                         dgpu_boost = ((metrics_v4->AverageSocketPower -
 699                                                          dgpu_power_limit) * 100) /
 700                                                          dgpu_power_limit;
 701                         if (dgpu_boost > 100)
 702                                 dgpu_boost = 100;
 703                 }
 704
 705                 if (dgpu_boost >= apu_boost)
 706                         apu_boost = 0;
 707                 else
 708                         dgpu_boost = 0;
 709         }
 710         *apu_percent = apu_boost;
 711         *dgpu_percent = dgpu_boost;
 712 }
 713
 714 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
 715                                                MetricsMember_t member,
 716                                                uint32_t *value)
 717 {
 718         struct smu_table_context *smu_table= &smu->smu_table;
 719         SmuMetrics_t *metrics =
 720                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
 721         SmuMetrics_V2_t *metrics_v2 =
 722                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
 723         SmuMetrics_V3_t *metrics_v3 =
 724                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V3);
 725         bool use_metrics_v2 = false;
 726         bool use_metrics_v3 = false;
 727         uint16_t average_gfx_activity;
 728         int ret = 0;
 729         uint32_t apu_percent = 0;
 730         uint32_t dgpu_percent = 0;
 731
 732         switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
 733         case IP_VERSION(11, 0, 7):
 734                 if (smu->smc_fw_version >= 0x3A4900)
 735                         use_metrics_v3 = true;
 736                 else if (smu->smc_fw_version >= 0x3A4300)
 737                         use_metrics_v2 = true;
 738                 break;
 739         case IP_VERSION(11, 0, 11):
 740                 if (smu->smc_fw_version >= 0x412D00)
 741                         use_metrics_v2 = true;
 742                 break;
 743         case IP_VERSION(11, 0, 12):
 744                 if (smu->smc_fw_version >= 0x3B2300)
 745                         use_metrics_v2 = true;
 746                 break;
 747         case IP_VERSION(11, 0, 13):
 748                 if (smu->smc_fw_version >= 0x491100)
 749                         use_metrics_v2 = true;
 750                 break;
 751         default:
 752                 break;
 753         }
 754
 755         ret = smu_cmn_get_metrics_table(smu,
 756                                         NULL,
 757                                         false);
 758         if (ret)
 759                 return ret;
 760
 761         switch (member) {
 762         case METRICS_CURR_GFXCLK:
 763                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
 764                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] :
 765                         metrics->CurrClock[PPCLK_GFXCLK];
 766                 break;
 767         case METRICS_CURR_SOCCLK:
 768                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
 769                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] :
 770                         metrics->CurrClock[PPCLK_SOCCLK];
 771                 break;
 772         case METRICS_CURR_UCLK:
 773                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
 774                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
 775                         metrics->CurrClock[PPCLK_UCLK];
 776                 break;
 777         case METRICS_CURR_VCLK:
 778                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
 779                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :
 780                         metrics->CurrClock[PPCLK_VCLK_0];
 781                 break;
 782         case METRICS_CURR_VCLK1:
 783                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
 784                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] :
 785                         metrics->CurrClock[PPCLK_VCLK_1];
 786                 break;
 787         case METRICS_CURR_DCLK:
 788                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
 789                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] :
 790                         metrics->CurrClock[PPCLK_DCLK_0];
 791                 break;
 792         case METRICS_CURR_DCLK1:
 793                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
 794                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
 795                         metrics->CurrClock[PPCLK_DCLK_1];
 796                 break;
 797         case METRICS_CURR_DCEFCLK:
 798                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCEFCLK] :
 799                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] :
 800                         metrics->CurrClock[PPCLK_DCEFCLK];
 801                 break;
 802         case METRICS_CURR_FCLK:
 803                 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_FCLK] :
 804                         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
 805                         metrics->CurrClock[PPCLK_FCLK];
 806                 break;
 807         case METRICS_AVERAGE_GFXCLK:
 808                 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
 809                         use_metrics_v2 ? metrics_v2->AverageGfxActivity :
 810                         metrics->AverageGfxActivity;
 811                 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
 812                         *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
 813                                 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
 814                                 metrics->AverageGfxclkFrequencyPostDs;
 815                 else
 816                         *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
 817                                 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
 818                                 metrics->AverageGfxclkFrequencyPreDs;
 819                 break;
 820         case METRICS_AVERAGE_FCLK:
 821                 *value = use_metrics_v3 ? metrics_v3->AverageFclkFrequencyPostDs :
 822                         use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs :
 823                         metrics->AverageFclkFrequencyPostDs;
 824                 break;
 825         case METRICS_AVERAGE_UCLK:
 826                 *value = use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
 827                         use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
 828                         metrics->AverageUclkFrequencyPostDs;
 829                 break;
 830         case METRICS_AVERAGE_GFXACTIVITY:
 831                 *value = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
 832                         use_metrics_v2 ? metrics_v2->AverageGfxActivity :
 833                         metrics->AverageGfxActivity;
 834                 break;
 835         case METRICS_AVERAGE_MEMACTIVITY:
 836                 *value = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
 837                         use_metrics_v2 ? metrics_v2->AverageUclkActivity :
 838                         metrics->AverageUclkActivity;
 839                 break;
 840         case METRICS_AVERAGE_SOCKETPOWER:
 841                 *value = use_metrics_v3 ? metrics_v3->AverageSocketPower << 8 :
 842                         use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 :
 843                         metrics->AverageSocketPower << 8;
 844                 break;
 845         case METRICS_TEMPERATURE_EDGE:
 846                 *value = (use_metrics_v3 ? metrics_v3->TemperatureEdge :
 847                         use_metrics_v2 ? metrics_v2->TemperatureEdge :
 848                         metrics->TemperatureEdge) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 849                 break;
 850         case METRICS_TEMPERATURE_HOTSPOT:
 851                 *value = (use_metrics_v3 ? metrics_v3->TemperatureHotspot :
 852                         use_metrics_v2 ? metrics_v2->TemperatureHotspot :
 853                         metrics->TemperatureHotspot) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 854                 break;
 855         case METRICS_TEMPERATURE_MEM:
 856                 *value = (use_metrics_v3 ? metrics_v3->TemperatureMem :
 857                         use_metrics_v2 ? metrics_v2->TemperatureMem :
 858                         metrics->TemperatureMem) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 859                 break;
 860         case METRICS_TEMPERATURE_VRGFX:
 861                 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
 862                         use_metrics_v2 ? metrics_v2->TemperatureVrGfx :
 863                         metrics->TemperatureVrGfx) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 864                 break;
 865         case METRICS_TEMPERATURE_VRSOC:
 866                 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
 867                         use_metrics_v2 ? metrics_v2->TemperatureVrSoc :
 868                         metrics->TemperatureVrSoc) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 869                 break;
 870         case METRICS_THROTTLER_STATUS:
 871                 *value = sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2);
 872                 break;
 873         case METRICS_CURR_FANSPEED:
 874                 *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
 875                         use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
 876                 break;
 877         case METRICS_UNIQUE_ID_UPPER32:
 878                 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
 879                 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumUpper32 : 0;
 880                 break;
 881         case METRICS_UNIQUE_ID_LOWER32:
 882                 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
 883                 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumLower32 : 0;
 884                 break;
 885         case METRICS_SS_APU_SHARE:
 886                 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
 887                 *value = apu_percent;
 888                 break;
 889         case METRICS_SS_DGPU_SHARE:
 890                 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
 891                 *value = dgpu_percent;
 892                 break;
 893
 894         default:
 895                 *value = UINT_MAX;
 896                 break;
 897         }
 898
 899         return ret;
 900
 901 }
 902
 903 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
 904 {
 905         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 906
 907         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 908                                        GFP_KERNEL);
 909         if (!smu_dpm->dpm_context)
 910                 return -ENOMEM;
 911
 912         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 913
 914         return 0;
 915 }
 916
 917 static void sienna_cichlid_stb_init(struct smu_context *smu);
 918
 919 static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
 920 {
 921         struct amdgpu_device *adev = smu->adev;
 922         int ret = 0;
 923
 924         ret = sienna_cichlid_tables_init(smu);
 925         if (ret)
 926                 return ret;
 927
 928         ret = sienna_cichlid_allocate_dpm_context(smu);
 929         if (ret)
 930                 return ret;
 931
 932         if (!amdgpu_sriov_vf(adev))
 933                 sienna_cichlid_stb_init(smu);
 934
 935         return smu_v11_0_init_smc_tables(smu);
 936 }
 937
 938 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 939 {
 940         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 941         struct smu_11_0_dpm_table *dpm_table;
 942         struct amdgpu_device *adev = smu->adev;
 943         int i, ret = 0;
 944         DpmDescriptor_t *table_member;
 945
 946         /* socclk dpm table setup */
 947         dpm_table = &dpm_context->dpm_tables.soc_table;
 948         GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
 949         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 950                 ret = smu_v11_0_set_single_dpm_table(smu,
 951                                                      SMU_SOCCLK,
 952                                                      dpm_table);
 953                 if (ret)
 954                         return ret;
 955                 dpm_table->is_fine_grained =
 956                         !table_member[PPCLK_SOCCLK].SnapToDiscrete;
 957         } else {
 958                 dpm_table->count = 1;
 959                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 960                 dpm_table->dpm_levels[0].enabled = true;
 961                 dpm_table->min = dpm_table->dpm_levels[0].value;
 962                 dpm_table->max = dpm_table->dpm_levels[0].value;
 963         }
 964
 965         /* gfxclk dpm table setup */
 966         dpm_table = &dpm_context->dpm_tables.gfx_table;
 967         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 968                 ret = smu_v11_0_set_single_dpm_table(smu,
 969                                                      SMU_GFXCLK,
 970                                                      dpm_table);
 971                 if (ret)
 972                         return ret;
 973                 dpm_table->is_fine_grained =
 974                         !table_member[PPCLK_GFXCLK].SnapToDiscrete;
 975         } else {
 976                 dpm_table->count = 1;
 977                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 978                 dpm_table->dpm_levels[0].enabled = true;
 979                 dpm_table->min = dpm_table->dpm_levels[0].value;
 980                 dpm_table->max = dpm_table->dpm_levels[0].value;
 981         }
 982
 983         /* uclk dpm table setup */
 984         dpm_table = &dpm_context->dpm_tables.uclk_table;
 985         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 986                 ret = smu_v11_0_set_single_dpm_table(smu,
 987                                                      SMU_UCLK,
 988                                                      dpm_table);
 989                 if (ret)
 990                         return ret;
 991                 dpm_table->is_fine_grained =
 992                         !table_member[PPCLK_UCLK].SnapToDiscrete;
 993         } else {
 994                 dpm_table->count = 1;
 995                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 996                 dpm_table->dpm_levels[0].enabled = true;
 997                 dpm_table->min = dpm_table->dpm_levels[0].value;
 998                 dpm_table->max = dpm_table->dpm_levels[0].value;
 999         }
1000
1001         /* fclk dpm table setup */
1002         dpm_table = &dpm_context->dpm_tables.fclk_table;
1003         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
1004                 ret = smu_v11_0_set_single_dpm_table(smu,
1005                                                      SMU_FCLK,
1006                                                      dpm_table);
1007                 if (ret)
1008                         return ret;
1009                 dpm_table->is_fine_grained =
1010                         !table_member[PPCLK_FCLK].SnapToDiscrete;
1011         } else {
1012                 dpm_table->count = 1;
1013                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
1014                 dpm_table->dpm_levels[0].enabled = true;
1015                 dpm_table->min = dpm_table->dpm_levels[0].value;
1016                 dpm_table->max = dpm_table->dpm_levels[0].value;
1017         }
1018
1019         /* vclk0/1 dpm table setup */
1020         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1021                 if (adev->vcn.harvest_config & (1 << i))
1022                         continue;
1023
1024                 dpm_table = &dpm_context->dpm_tables.vclk_table;
1025                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1026                         ret = smu_v11_0_set_single_dpm_table(smu,
1027                                                              i ? SMU_VCLK1 : SMU_VCLK,
1028                                                              dpm_table);
1029                         if (ret)
1030                                 return ret;
1031                         dpm_table->is_fine_grained =
1032                                 !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete;
1033                 } else {
1034                         dpm_table->count = 1;
1035                         dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
1036                         dpm_table->dpm_levels[0].enabled = true;
1037                         dpm_table->min = dpm_table->dpm_levels[0].value;
1038                         dpm_table->max = dpm_table->dpm_levels[0].value;
1039                 }
1040         }
1041
1042         /* dclk0/1 dpm table setup */
1043         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1044                 if (adev->vcn.harvest_config & (1 << i))
1045                         continue;
1046                 dpm_table = &dpm_context->dpm_tables.dclk_table;
1047                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1048                         ret = smu_v11_0_set_single_dpm_table(smu,
1049                                                              i ? SMU_DCLK1 : SMU_DCLK,
1050                                                              dpm_table);
1051                         if (ret)
1052                                 return ret;
1053                         dpm_table->is_fine_grained =
1054                                 !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete;
1055                 } else {
1056                         dpm_table->count = 1;
1057                         dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
1058                         dpm_table->dpm_levels[0].enabled = true;
1059                         dpm_table->min = dpm_table->dpm_levels[0].value;
1060                         dpm_table->max = dpm_table->dpm_levels[0].value;
1061                 }
1062         }
1063
1064         /* dcefclk dpm table setup */
1065         dpm_table = &dpm_context->dpm_tables.dcef_table;
1066         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1067                 ret = smu_v11_0_set_single_dpm_table(smu,
1068                                                      SMU_DCEFCLK,
1069                                                      dpm_table);
1070                 if (ret)
1071                         return ret;
1072                 dpm_table->is_fine_grained =
1073                         !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
1074         } else {
1075                 dpm_table->count = 1;
1076                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1077                 dpm_table->dpm_levels[0].enabled = true;
1078                 dpm_table->min = dpm_table->dpm_levels[0].value;
1079                 dpm_table->max = dpm_table->dpm_levels[0].value;
1080         }
1081
1082         /* pixelclk dpm table setup */
1083         dpm_table = &dpm_context->dpm_tables.pixel_table;
1084         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1085                 ret = smu_v11_0_set_single_dpm_table(smu,
1086                                                      SMU_PIXCLK,
1087                                                      dpm_table);
1088                 if (ret)
1089                         return ret;
1090                 dpm_table->is_fine_grained =
1091                         !table_member[PPCLK_PIXCLK].SnapToDiscrete;
1092         } else {
1093                 dpm_table->count = 1;
1094                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1095                 dpm_table->dpm_levels[0].enabled = true;
1096                 dpm_table->min = dpm_table->dpm_levels[0].value;
1097                 dpm_table->max = dpm_table->dpm_levels[0].value;
1098         }
1099
1100         /* displayclk dpm table setup */
1101         dpm_table = &dpm_context->dpm_tables.display_table;
1102         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1103                 ret = smu_v11_0_set_single_dpm_table(smu,
1104                                                      SMU_DISPCLK,
1105                                                      dpm_table);
1106                 if (ret)
1107                         return ret;
1108                 dpm_table->is_fine_grained =
1109                         !table_member[PPCLK_DISPCLK].SnapToDiscrete;
1110         } else {
1111                 dpm_table->count = 1;
1112                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1113                 dpm_table->dpm_levels[0].enabled = true;
1114                 dpm_table->min = dpm_table->dpm_levels[0].value;
1115                 dpm_table->max = dpm_table->dpm_levels[0].value;
1116         }
1117
1118         /* phyclk dpm table setup */
1119         dpm_table = &dpm_context->dpm_tables.phy_table;
1120         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1121                 ret = smu_v11_0_set_single_dpm_table(smu,
1122                                                      SMU_PHYCLK,
1123                                                      dpm_table);
1124                 if (ret)
1125                         return ret;
1126                 dpm_table->is_fine_grained =
1127                         !table_member[PPCLK_PHYCLK].SnapToDiscrete;
1128         } else {
1129                 dpm_table->count = 1;
1130                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1131                 dpm_table->dpm_levels[0].enabled = true;
1132                 dpm_table->min = dpm_table->dpm_levels[0].value;
1133                 dpm_table->max = dpm_table->dpm_levels[0].value;
1134         }
1135
1136         return 0;
1137 }
1138
1139 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1140 {
1141         struct amdgpu_device *adev = smu->adev;
1142         int i, ret = 0;
1143
1144         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1145                 if (adev->vcn.harvest_config & (1 << i))
1146                         continue;
1147                 /* vcn dpm on is a prerequisite for vcn power gate messages */
1148                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1149                         ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1150                                                               SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
1151                                                               0x10000 * i, NULL);
1152                         if (ret)
1153                                 return ret;
1154                 }
1155         }
1156
1157         return ret;
1158 }
1159
1160 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1161 {
1162         int ret = 0;
1163
1164         if (enable) {
1165                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1166                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
1167                         if (ret)
1168                                 return ret;
1169                 }
1170         } else {
1171                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1172                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
1173                         if (ret)
1174                                 return ret;
1175                 }
1176         }
1177
1178         return ret;
1179 }
1180
1181 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
1182                                        enum smu_clk_type clk_type,
1183                                        uint32_t *value)
1184 {
1185         MetricsMember_t member_type;
1186         int clk_id = 0;
1187
1188         clk_id = smu_cmn_to_asic_specific_index(smu,
1189                                                 CMN2ASIC_MAPPING_CLK,
1190                                                 clk_type);
1191         if (clk_id < 0)
1192                 return clk_id;
1193
1194         switch (clk_id) {
1195         case PPCLK_GFXCLK:
1196                 member_type = METRICS_CURR_GFXCLK;
1197                 break;
1198         case PPCLK_UCLK:
1199                 member_type = METRICS_CURR_UCLK;
1200                 break;
1201         case PPCLK_SOCCLK:
1202                 member_type = METRICS_CURR_SOCCLK;
1203                 break;
1204         case PPCLK_FCLK:
1205                 member_type = METRICS_CURR_FCLK;
1206                 break;
1207         case PPCLK_VCLK_0:
1208                 member_type = METRICS_CURR_VCLK;
1209                 break;
1210         case PPCLK_VCLK_1:
1211                 member_type = METRICS_CURR_VCLK1;
1212                 break;
1213         case PPCLK_DCLK_0:
1214                 member_type = METRICS_CURR_DCLK;
1215                 break;
1216         case PPCLK_DCLK_1:
1217                 member_type = METRICS_CURR_DCLK1;
1218                 break;
1219         case PPCLK_DCEFCLK:
1220                 member_type = METRICS_CURR_DCEFCLK;
1221                 break;
1222         default:
1223                 return -EINVAL;
1224         }
1225
1226         return sienna_cichlid_get_smu_metrics_data(smu,
1227                                                    member_type,
1228                                                    value);
1229
1230 }
1231
1232 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1233 {
1234         DpmDescriptor_t *dpm_desc = NULL;
1235         DpmDescriptor_t *table_member;
1236         uint32_t clk_index = 0;
1237
1238         GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
1239         clk_index = smu_cmn_to_asic_specific_index(smu,
1240                                                    CMN2ASIC_MAPPING_CLK,
1241                                                    clk_type);
1242         dpm_desc = &table_member[clk_index];
1243
1244         /* 0 - Fine grained DPM, 1 - Discrete DPM */
1245         return dpm_desc->SnapToDiscrete == 0;
1246 }
1247
1248 static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
1249                                                    enum SMU_11_0_7_ODFEATURE_CAP cap)
1250 {
1251         return od_table->cap[cap];
1252 }
1253
1254 static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
1255                                                 enum SMU_11_0_7_ODSETTING_ID setting,
1256                                                 uint32_t *min, uint32_t *max)
1257 {
1258         if (min)
1259                 *min = od_table->min[setting];
1260         if (max)
1261                 *max = od_table->max[setting];
1262 }
1263
1264 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1265                         enum smu_clk_type clk_type, char *buf)
1266 {
1267         struct amdgpu_device *adev = smu->adev;
1268         struct smu_table_context *table_context = &smu->smu_table;
1269         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1270         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1271         uint16_t *table_member;
1272
1273         struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1274         OverDriveTable_t *od_table =
1275                 (OverDriveTable_t *)table_context->overdrive_table;
1276         int i, size = 0, ret = 0;
1277         uint32_t cur_value = 0, value = 0, count = 0;
1278         uint32_t freq_values[3] = {0};
1279         uint32_t mark_index = 0;
1280         uint32_t gen_speed, lane_width;
1281         uint32_t min_value, max_value;
1282
1283         smu_cmn_get_sysfs_buf(&buf, &size);
1284
1285         switch (clk_type) {
1286         case SMU_GFXCLK:
1287         case SMU_SCLK:
1288         case SMU_SOCCLK:
1289         case SMU_MCLK:
1290         case SMU_UCLK:
1291         case SMU_FCLK:
1292         case SMU_VCLK:
1293         case SMU_VCLK1:
1294         case SMU_DCLK:
1295         case SMU_DCLK1:
1296         case SMU_DCEFCLK:
1297                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1298                 if (ret)
1299                         goto print_clk_out;
1300
1301                 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1302                 if (ret)
1303                         goto print_clk_out;
1304
1305                 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1306                         for (i = 0; i < count; i++) {
1307                                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1308                                 if (ret)
1309                                         goto print_clk_out;
1310
1311                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1312                                                 cur_value == value ? "*" : "");
1313                         }
1314                 } else {
1315                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1316                         if (ret)
1317                                 goto print_clk_out;
1318                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1319                         if (ret)
1320                                 goto print_clk_out;
1321
1322                         freq_values[1] = cur_value;
1323                         mark_index = cur_value == freq_values[0] ? 0 :
1324                                      cur_value == freq_values[2] ? 2 : 1;
1325
1326                         count = 3;
1327                         if (mark_index != 1) {
1328                                 count = 2;
1329                                 freq_values[1] = freq_values[2];
1330                         }
1331
1332                         for (i = 0; i < count; i++) {
1333                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
1334                                                 cur_value  == freq_values[i] ? "*" : "");
1335                         }
1336
1337                 }
1338                 break;
1339         case SMU_PCIE:
1340                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1341                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1342                 GET_PPTABLE_MEMBER(LclkFreq, &table_member);
1343                 for (i = 0; i < NUM_LINK_LEVELS; i++)
1344                         size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1345                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1346                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1347                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1348                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1349                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1350                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1351                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1352                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1353                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1354                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1355                                         table_member[i],
1356                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1357                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1358                                         "*" : "");
1359                 break;
1360         case SMU_OD_SCLK:
1361                 if (!smu->od_enabled || !od_table || !od_settings)
1362                         break;
1363
1364                 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1365                         break;
1366
1367                 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1368                 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1369                 break;
1370
1371         case SMU_OD_MCLK:
1372                 if (!smu->od_enabled || !od_table || !od_settings)
1373                         break;
1374
1375                 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1376                         break;
1377
1378                 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1379                 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
1380                 break;
1381
1382         case SMU_OD_VDDGFX_OFFSET:
1383                 if (!smu->od_enabled || !od_table || !od_settings)
1384                         break;
1385
1386                 /*
1387                  * OD GFX Voltage Offset functionality is supported only by 58.41.0
1388                  * and onwards SMU firmwares.
1389                  */
1390                 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
1391                      IP_VERSION(11, 0, 7)) &&
1392                     (smu->smc_fw_version < 0x003a2900))
1393                         break;
1394
1395                 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1396                 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset);
1397                 break;
1398
1399         case SMU_OD_RANGE:
1400                 if (!smu->od_enabled || !od_table || !od_settings)
1401                         break;
1402
1403                 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1404
1405                 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1406                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1407                                                             &min_value, NULL);
1408                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1409                                                             NULL, &max_value);
1410                         size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1411                                         min_value, max_value);
1412                 }
1413
1414                 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1415                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1416                                                             &min_value, NULL);
1417                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1418                                                             NULL, &max_value);
1419                         size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1420                                         min_value, max_value);
1421                 }
1422                 break;
1423
1424         default:
1425                 break;
1426         }
1427
1428 print_clk_out:
1429         return size;
1430 }
1431
1432 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1433                                    enum smu_clk_type clk_type, uint32_t mask)
1434 {
1435         int ret = 0;
1436         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1437
1438         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1439         soft_max_level = mask ? (fls(mask) - 1) : 0;
1440
1441         switch (clk_type) {
1442         case SMU_GFXCLK:
1443         case SMU_SCLK:
1444         case SMU_SOCCLK:
1445         case SMU_MCLK:
1446         case SMU_UCLK:
1447         case SMU_FCLK:
1448                 /* There is only 2 levels for fine grained DPM */
1449                 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1450                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1451                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1452                 }
1453
1454                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1455                 if (ret)
1456                         goto forec_level_out;
1457
1458                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1459                 if (ret)
1460                         goto forec_level_out;
1461
1462                 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1463                 if (ret)
1464                         goto forec_level_out;
1465                 break;
1466         case SMU_DCEFCLK:
1467                 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1468                 break;
1469         default:
1470                 break;
1471         }
1472
1473 forec_level_out:
1474         return 0;
1475 }
1476
1477 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1478 {
1479         struct smu_11_0_dpm_context *dpm_context =
1480                                 smu->smu_dpm.dpm_context;
1481         struct smu_11_0_dpm_table *gfx_table =
1482                                 &dpm_context->dpm_tables.gfx_table;
1483         struct smu_11_0_dpm_table *mem_table =
1484                                 &dpm_context->dpm_tables.uclk_table;
1485         struct smu_11_0_dpm_table *soc_table =
1486                                 &dpm_context->dpm_tables.soc_table;
1487         struct smu_umd_pstate_table *pstate_table =
1488                                 &smu->pstate_table;
1489         struct amdgpu_device *adev = smu->adev;
1490
1491         pstate_table->gfxclk_pstate.min = gfx_table->min;
1492         pstate_table->gfxclk_pstate.peak = gfx_table->max;
1493
1494         pstate_table->uclk_pstate.min = mem_table->min;
1495         pstate_table->uclk_pstate.peak = mem_table->max;
1496
1497         pstate_table->socclk_pstate.min = soc_table->min;
1498         pstate_table->socclk_pstate.peak = soc_table->max;
1499
1500         switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1501         case IP_VERSION(11, 0, 7):
1502         case IP_VERSION(11, 0, 11):
1503                 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1504                 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
1505                 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
1506                 break;
1507         case IP_VERSION(11, 0, 12):
1508                 pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;
1509                 pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;
1510                 pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;
1511                 break;
1512         case IP_VERSION(11, 0, 13):
1513                 pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;
1514                 pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;
1515                 pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;
1516                 break;
1517         default:
1518                 break;
1519         }
1520
1521         return 0;
1522 }
1523
1524 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1525 {
1526         int ret = 0;
1527         uint32_t max_freq = 0;
1528
1529         /* Sienna_Cichlid do not support to change display num currently */
1530         return 0;
1531 #if 0
1532         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1533         if (ret)
1534                 return ret;
1535 #endif
1536
1537         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1538                 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1539                 if (ret)
1540                         return ret;
1541                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1542                 if (ret)
1543                         return ret;
1544         }
1545
1546         return ret;
1547 }
1548
1549 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1550 {
1551         int ret = 0;
1552
1553         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1554             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1555             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1556 #if 0
1557                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1558                                                   smu->display_config->num_display,
1559                                                   NULL);
1560 #endif
1561                 if (ret)
1562                         return ret;
1563         }
1564
1565         return ret;
1566 }
1567
1568 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1569 {
1570         int ret = 0;
1571         uint64_t feature_enabled;
1572
1573         ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1574         if (ret)
1575                 return false;
1576
1577         return !!(feature_enabled & SMC_DPM_FEATURE);
1578 }
1579
1580 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1581                                             uint32_t *speed)
1582 {
1583         if (!speed)
1584                 return -EINVAL;
1585
1586         /*
1587          * For Sienna_Cichlid and later, the fan speed(rpm) reported
1588          * by pmfw is always trustable(even when the fan control feature
1589          * disabled or 0 RPM kicked in).
1590          */
1591         return sienna_cichlid_get_smu_metrics_data(smu,
1592                                                    METRICS_CURR_FANSPEED,
1593                                                    speed);
1594 }
1595
1596 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1597 {
1598         uint16_t *table_member;
1599
1600         GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1601         smu->fan_max_rpm = *table_member;
1602
1603         return 0;
1604 }
1605
1606 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1607 {
1608         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1609         DpmActivityMonitorCoeffInt_t *activity_monitor =
1610                 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1611         uint32_t i, size = 0;
1612         int16_t workload_type = 0;
1613         static const char *title[] = {
1614                         "PROFILE_INDEX(NAME)",
1615                         "CLOCK_TYPE(NAME)",
1616                         "FPS",
1617                         "MinFreqType",
1618                         "MinActiveFreqType",
1619                         "MinActiveFreq",
1620                         "BoosterFreqType",
1621                         "BoosterFreq",
1622                         "PD_Data_limit_c",
1623                         "PD_Data_error_coeff",
1624                         "PD_Data_error_rate_coeff"};
1625         int result = 0;
1626
1627         if (!buf)
1628                 return -EINVAL;
1629
1630         size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1631                         title[0], title[1], title[2], title[3], title[4], title[5],
1632                         title[6], title[7], title[8], title[9], title[10]);
1633
1634         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1635                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1636                 workload_type = smu_cmn_to_asic_specific_index(smu,
1637                                                                CMN2ASIC_MAPPING_WORKLOAD,
1638                                                                i);
1639                 if (workload_type < 0)
1640                         return -EINVAL;
1641
1642                 result = smu_cmn_update_table(smu,
1643                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1644                                           (void *)(&activity_monitor_external), false);
1645                 if (result) {
1646                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1647                         return result;
1648                 }
1649
1650                 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1651                         i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1652
1653                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1654                         " ",
1655                         0,
1656                         "GFXCLK",
1657                         activity_monitor->Gfx_FPS,
1658                         activity_monitor->Gfx_MinFreqStep,
1659                         activity_monitor->Gfx_MinActiveFreqType,
1660                         activity_monitor->Gfx_MinActiveFreq,
1661                         activity_monitor->Gfx_BoosterFreqType,
1662                         activity_monitor->Gfx_BoosterFreq,
1663                         activity_monitor->Gfx_PD_Data_limit_c,
1664                         activity_monitor->Gfx_PD_Data_error_coeff,
1665                         activity_monitor->Gfx_PD_Data_error_rate_coeff);
1666
1667                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1668                         " ",
1669                         1,
1670                         "SOCCLK",
1671                         activity_monitor->Fclk_FPS,
1672                         activity_monitor->Fclk_MinFreqStep,
1673                         activity_monitor->Fclk_MinActiveFreqType,
1674                         activity_monitor->Fclk_MinActiveFreq,
1675                         activity_monitor->Fclk_BoosterFreqType,
1676                         activity_monitor->Fclk_BoosterFreq,
1677                         activity_monitor->Fclk_PD_Data_limit_c,
1678                         activity_monitor->Fclk_PD_Data_error_coeff,
1679                         activity_monitor->Fclk_PD_Data_error_rate_coeff);
1680
1681                 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1682                         " ",
1683                         2,
1684                         "MEMLK",
1685                         activity_monitor->Mem_FPS,
1686                         activity_monitor->Mem_MinFreqStep,
1687                         activity_monitor->Mem_MinActiveFreqType,
1688                         activity_monitor->Mem_MinActiveFreq,
1689                         activity_monitor->Mem_BoosterFreqType,
1690                         activity_monitor->Mem_BoosterFreq,
1691                         activity_monitor->Mem_PD_Data_limit_c,
1692                         activity_monitor->Mem_PD_Data_error_coeff,
1693                         activity_monitor->Mem_PD_Data_error_rate_coeff);
1694         }
1695
1696         return size;
1697 }
1698
1699 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1700 {
1701
1702         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1703         DpmActivityMonitorCoeffInt_t *activity_monitor =
1704                 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1705         int workload_type, ret = 0;
1706
1707         smu->power_profile_mode = input[size];
1708
1709         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1710                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1711                 return -EINVAL;
1712         }
1713
1714         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1715
1716                 ret = smu_cmn_update_table(smu,
1717                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1718                                        (void *)(&activity_monitor_external), false);
1719                 if (ret) {
1720                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1721                         return ret;
1722                 }
1723
1724                 switch (input[0]) {
1725                 case 0: /* Gfxclk */
1726                         activity_monitor->Gfx_FPS = input[1];
1727                         activity_monitor->Gfx_MinFreqStep = input[2];
1728                         activity_monitor->Gfx_MinActiveFreqType = input[3];
1729                         activity_monitor->Gfx_MinActiveFreq = input[4];
1730                         activity_monitor->Gfx_BoosterFreqType = input[5];
1731                         activity_monitor->Gfx_BoosterFreq = input[6];
1732                         activity_monitor->Gfx_PD_Data_limit_c = input[7];
1733                         activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1734                         activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
1735                         break;
1736                 case 1: /* Socclk */
1737                         activity_monitor->Fclk_FPS = input[1];
1738                         activity_monitor->Fclk_MinFreqStep = input[2];
1739                         activity_monitor->Fclk_MinActiveFreqType = input[3];
1740                         activity_monitor->Fclk_MinActiveFreq = input[4];
1741                         activity_monitor->Fclk_BoosterFreqType = input[5];
1742                         activity_monitor->Fclk_BoosterFreq = input[6];
1743                         activity_monitor->Fclk_PD_Data_limit_c = input[7];
1744                         activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1745                         activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
1746                         break;
1747                 case 2: /* Memlk */
1748                         activity_monitor->Mem_FPS = input[1];
1749                         activity_monitor->Mem_MinFreqStep = input[2];
1750                         activity_monitor->Mem_MinActiveFreqType = input[3];
1751                         activity_monitor->Mem_MinActiveFreq = input[4];
1752                         activity_monitor->Mem_BoosterFreqType = input[5];
1753                         activity_monitor->Mem_BoosterFreq = input[6];
1754                         activity_monitor->Mem_PD_Data_limit_c = input[7];
1755                         activity_monitor->Mem_PD_Data_error_coeff = input[8];
1756                         activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
1757                         break;
1758                 }
1759
1760                 ret = smu_cmn_update_table(smu,
1761                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1762                                        (void *)(&activity_monitor_external), true);
1763                 if (ret) {
1764                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1765                         return ret;
1766                 }
1767         }
1768
1769         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1770         workload_type = smu_cmn_to_asic_specific_index(smu,
1771                                                        CMN2ASIC_MAPPING_WORKLOAD,
1772                                                        smu->power_profile_mode);
1773         if (workload_type < 0)
1774                 return -EINVAL;
1775         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1776                                     1 << workload_type, NULL);
1777
1778         return ret;
1779 }
1780
1781 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1782 {
1783         struct smu_clocks min_clocks = {0};
1784         struct pp_display_clock_request clock_req;
1785         int ret = 0;
1786
1787         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1788         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1789         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1790
1791         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1792                 clock_req.clock_type = amd_pp_dcef_clock;
1793                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1794
1795                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1796                 if (!ret) {
1797                         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1798                                 ret = smu_cmn_send_smc_msg_with_param(smu,
1799                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1800                                                                   min_clocks.dcef_clock_in_sr/100,
1801                                                                   NULL);
1802                                 if (ret) {
1803                                         dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1804                                         return ret;
1805                                 }
1806                         }
1807                 } else {
1808                         dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1809                 }
1810         }
1811
1812         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1813                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1814                 if (ret) {
1815                         dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1816                         return ret;
1817                 }
1818         }
1819
1820         return 0;
1821 }
1822
1823 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1824                                                struct pp_smu_wm_range_sets *clock_ranges)
1825 {
1826         Watermarks_t *table = smu->smu_table.watermarks_table;
1827         int ret = 0;
1828         int i;
1829
1830         if (clock_ranges) {
1831                 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1832                     clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1833                         return -EINVAL;
1834
1835                 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1836                         table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1837                                 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1838                         table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1839                                 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1840                         table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1841                                 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1842                         table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1843                                 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1844
1845                         table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1846                                 clock_ranges->reader_wm_sets[i].wm_inst;
1847                 }
1848
1849                 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1850                         table->WatermarkRow[WM_SOCCLK][i].MinClock =
1851                                 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1852                         table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1853                                 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1854                         table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1855                                 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1856                         table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1857                                 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1858
1859                         table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1860                                 clock_ranges->writer_wm_sets[i].wm_inst;
1861                 }
1862
1863                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1864         }
1865
1866         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1867              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1868                 ret = smu_cmn_write_watermarks_table(smu);
1869                 if (ret) {
1870                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1871                         return ret;
1872                 }
1873                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1874         }
1875
1876         return 0;
1877 }
1878
1879 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1880                                  enum amd_pp_sensors sensor,
1881                                  void *data, uint32_t *size)
1882 {
1883         int ret = 0;
1884         uint16_t *temp;
1885         struct amdgpu_device *adev = smu->adev;
1886
1887         if(!data || !size)
1888                 return -EINVAL;
1889
1890         switch (sensor) {
1891         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1892                 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1893                 *(uint16_t *)data = *temp;
1894                 *size = 4;
1895                 break;
1896         case AMDGPU_PP_SENSOR_MEM_LOAD:
1897                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1898                                                           METRICS_AVERAGE_MEMACTIVITY,
1899                                                           (uint32_t *)data);
1900                 *size = 4;
1901                 break;
1902         case AMDGPU_PP_SENSOR_GPU_LOAD:
1903                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1904                                                           METRICS_AVERAGE_GFXACTIVITY,
1905                                                           (uint32_t *)data);
1906                 *size = 4;
1907                 break;
1908         case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1909                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1910                                                           METRICS_AVERAGE_SOCKETPOWER,
1911                                                           (uint32_t *)data);
1912                 *size = 4;
1913                 break;
1914         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1915                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1916                                                           METRICS_TEMPERATURE_HOTSPOT,
1917                                                           (uint32_t *)data);
1918                 *size = 4;
1919                 break;
1920         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1921                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1922                                                           METRICS_TEMPERATURE_EDGE,
1923                                                           (uint32_t *)data);
1924                 *size = 4;
1925                 break;
1926         case AMDGPU_PP_SENSOR_MEM_TEMP:
1927                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1928                                                           METRICS_TEMPERATURE_MEM,
1929                                                           (uint32_t *)data);
1930                 *size = 4;
1931                 break;
1932         case AMDGPU_PP_SENSOR_GFX_MCLK:
1933                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1934                                                           METRICS_CURR_UCLK,
1935                                                           (uint32_t *)data);
1936                 *(uint32_t *)data *= 100;
1937                 *size = 4;
1938                 break;
1939         case AMDGPU_PP_SENSOR_GFX_SCLK:
1940                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1941                                                           METRICS_AVERAGE_GFXCLK,
1942                                                           (uint32_t *)data);
1943                 *(uint32_t *)data *= 100;
1944                 *size = 4;
1945                 break;
1946         case AMDGPU_PP_SENSOR_VDDGFX:
1947                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1948                 *size = 4;
1949                 break;
1950         case AMDGPU_PP_SENSOR_SS_APU_SHARE:
1951                 if (amdgpu_ip_version(adev, MP1_HWIP, 0) !=
1952                     IP_VERSION(11, 0, 7)) {
1953                         ret = sienna_cichlid_get_smu_metrics_data(smu,
1954                                                 METRICS_SS_APU_SHARE, (uint32_t *)data);
1955                         *size = 4;
1956                 } else {
1957                         ret = -EOPNOTSUPP;
1958                 }
1959                 break;
1960         case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
1961                 if (amdgpu_ip_version(adev, MP1_HWIP, 0) !=
1962                     IP_VERSION(11, 0, 7)) {
1963                         ret = sienna_cichlid_get_smu_metrics_data(smu,
1964                                                 METRICS_SS_DGPU_SHARE, (uint32_t *)data);
1965                         *size = 4;
1966                 } else {
1967                         ret = -EOPNOTSUPP;
1968                 }
1969                 break;
1970         case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1971         default:
1972                 ret = -EOPNOTSUPP;
1973                 break;
1974         }
1975
1976         return ret;
1977 }
1978
1979 static void sienna_cichlid_get_unique_id(struct smu_context *smu)
1980 {
1981         struct amdgpu_device *adev = smu->adev;
1982         uint32_t upper32 = 0, lower32 = 0;
1983
1984         /* Only supported as of version 0.58.83.0 and only on Sienna Cichlid */
1985         if (smu->smc_fw_version < 0x3A5300 ||
1986             amdgpu_ip_version(smu->adev, MP1_HWIP, 0) != IP_VERSION(11, 0, 7))
1987                 return;
1988
1989         if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
1990                 goto out;
1991         if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
1992                 goto out;
1993
1994 out:
1995
1996         adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1997 }
1998
1999 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
2000 {
2001         uint32_t num_discrete_levels = 0;
2002         uint16_t *dpm_levels = NULL;
2003         uint16_t i = 0;
2004         struct smu_table_context *table_context = &smu->smu_table;
2005         DpmDescriptor_t *table_member1;
2006         uint16_t *table_member2;
2007
2008         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
2009                 return -EINVAL;
2010
2011         GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
2012         num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
2013         GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
2014         dpm_levels = table_member2;
2015
2016         if (num_discrete_levels == 0 || dpm_levels == NULL)
2017                 return -EINVAL;
2018
2019         *num_states = num_discrete_levels;
2020         for (i = 0; i < num_discrete_levels; i++) {
2021                 /* convert to khz */
2022                 *clocks_in_khz = (*dpm_levels) * 1000;
2023                 clocks_in_khz++;
2024                 dpm_levels++;
2025         }
2026
2027         return 0;
2028 }
2029
2030 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
2031                                                 struct smu_temperature_range *range)
2032 {
2033         struct smu_table_context *table_context = &smu->smu_table;
2034         struct smu_11_0_7_powerplay_table *powerplay_table =
2035                                 table_context->power_play_table;
2036         uint16_t *table_member;
2037         uint16_t temp_edge, temp_hotspot, temp_mem;
2038
2039         if (!range)
2040                 return -EINVAL;
2041
2042         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2043
2044         GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
2045         temp_edge = table_member[TEMP_EDGE];
2046         temp_hotspot = table_member[TEMP_HOTSPOT];
2047         temp_mem = table_member[TEMP_MEM];
2048
2049         range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2050         range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
2051                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2052         range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2053         range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
2054                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2055         range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2056         range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
2057                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2058
2059         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2060
2061         return 0;
2062 }
2063
2064 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
2065                                                 bool disable_memory_clock_switch)
2066 {
2067         int ret = 0;
2068         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2069                 (struct smu_11_0_max_sustainable_clocks *)
2070                         smu->smu_table.max_sustainable_clocks;
2071         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2072         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2073
2074         if(smu->disable_uclk_switch == disable_memory_clock_switch)
2075                 return 0;
2076
2077         if(disable_memory_clock_switch)
2078                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
2079         else
2080                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
2081
2082         if(!ret)
2083                 smu->disable_uclk_switch = disable_memory_clock_switch;
2084
2085         return ret;
2086 }
2087
2088 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
2089                                                  uint8_t pcie_gen_cap,
2090                                                  uint8_t pcie_width_cap)
2091 {
2092         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2093         struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table;
2094         uint8_t *table_member1, *table_member2;
2095         uint8_t min_gen_speed, max_gen_speed;
2096         uint8_t min_lane_width, max_lane_width;
2097         uint32_t smu_pcie_arg;
2098         int ret, i;
2099
2100         GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
2101         GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
2102
2103         min_gen_speed = max_t(uint8_t, 0, table_member1[0]);
2104         max_gen_speed = min(pcie_gen_cap, table_member1[1]);
2105         min_gen_speed = min_gen_speed > max_gen_speed ?
2106                         max_gen_speed : min_gen_speed;
2107         min_lane_width = max_t(uint8_t, 1, table_member2[0]);
2108         max_lane_width = min(pcie_width_cap, table_member2[1]);
2109         min_lane_width = min_lane_width > max_lane_width ?
2110                          max_lane_width : min_lane_width;
2111
2112         if (!amdgpu_device_pcie_dynamic_switching_supported()) {
2113                 pcie_table->pcie_gen[0] = max_gen_speed;
2114                 pcie_table->pcie_lane[0] = max_lane_width;
2115         } else {
2116                 pcie_table->pcie_gen[0] = min_gen_speed;
2117                 pcie_table->pcie_lane[0] = min_lane_width;
2118         }
2119         pcie_table->pcie_gen[1] = max_gen_speed;
2120         pcie_table->pcie_lane[1] = max_lane_width;
2121
2122         for (i = 0; i < NUM_LINK_LEVELS; i++) {
2123                 smu_pcie_arg = (i << 16 |
2124                                 pcie_table->pcie_gen[i] << 8 |
2125                                 pcie_table->pcie_lane[i]);
2126
2127                 ret = smu_cmn_send_smc_msg_with_param(smu,
2128                                 SMU_MSG_OverridePcieParameters,
2129                                 smu_pcie_arg,
2130                                 NULL);
2131                 if (ret)
2132                         return ret;
2133         }
2134
2135         return 0;
2136 }
2137
2138 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
2139                                 enum smu_clk_type clk_type,
2140                                 uint32_t *min, uint32_t *max)
2141 {
2142         return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
2143 }
2144
2145 static void sienna_cichlid_dump_od_table(struct smu_context *smu,
2146                                          OverDriveTable_t *od_table)
2147 {
2148         struct amdgpu_device *adev = smu->adev;
2149
2150         dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
2151                                                           od_table->GfxclkFmax);
2152         dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
2153                                                         od_table->UclkFmax);
2154
2155         if (!((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7)) &&
2156               (smu->smc_fw_version < 0x003a2900)))
2157                 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
2158 }
2159
2160 static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
2161 {
2162         OverDriveTable_t *od_table =
2163                 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2164         OverDriveTable_t *boot_od_table =
2165                 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2166         OverDriveTable_t *user_od_table =
2167                 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
2168         OverDriveTable_t user_od_table_bak;
2169         int ret = 0;
2170
2171         ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
2172                                    0, (void *)boot_od_table, false);
2173         if (ret) {
2174                 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2175                 return ret;
2176         }
2177
2178         sienna_cichlid_dump_od_table(smu, boot_od_table);
2179
2180         memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
2181
2182         /*
2183          * For S3/S4/Runpm resume, we need to setup those overdrive tables again,
2184          * but we have to preserve user defined values in "user_od_table".
2185          */
2186         if (!smu->adev->in_suspend) {
2187                 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2188                 smu->user_dpm_profile.user_od = false;
2189         } else if (smu->user_dpm_profile.user_od) {
2190                 memcpy(&user_od_table_bak, user_od_table, sizeof(OverDriveTable_t));
2191                 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2192                 user_od_table->GfxclkFmin = user_od_table_bak.GfxclkFmin;
2193                 user_od_table->GfxclkFmax = user_od_table_bak.GfxclkFmax;
2194                 user_od_table->UclkFmin = user_od_table_bak.UclkFmin;
2195                 user_od_table->UclkFmax = user_od_table_bak.UclkFmax;
2196                 user_od_table->VddGfxOffset = user_od_table_bak.VddGfxOffset;
2197         }
2198
2199         return 0;
2200 }
2201
2202 static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
2203                                                  struct smu_11_0_7_overdrive_table *od_table,
2204                                                  enum SMU_11_0_7_ODSETTING_ID setting,
2205                                                  uint32_t value)
2206 {
2207         if (value < od_table->min[setting]) {
2208                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
2209                                           setting, value, od_table->min[setting]);
2210                 return -EINVAL;
2211         }
2212         if (value > od_table->max[setting]) {
2213                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
2214                                           setting, value, od_table->max[setting]);
2215                 return -EINVAL;
2216         }
2217
2218         return 0;
2219 }
2220
2221 static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
2222                                             enum PP_OD_DPM_TABLE_COMMAND type,
2223                                             long input[], uint32_t size)
2224 {
2225         struct smu_table_context *table_context = &smu->smu_table;
2226         OverDriveTable_t *od_table =
2227                 (OverDriveTable_t *)table_context->overdrive_table;
2228         struct smu_11_0_7_overdrive_table *od_settings =
2229                 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
2230         struct amdgpu_device *adev = smu->adev;
2231         enum SMU_11_0_7_ODSETTING_ID freq_setting;
2232         uint16_t *freq_ptr;
2233         int i, ret = 0;
2234
2235         if (!smu->od_enabled) {
2236                 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2237                 return -EINVAL;
2238         }
2239
2240         if (!smu->od_settings) {
2241                 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2242                 return -ENOENT;
2243         }
2244
2245         if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2246                 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2247                 return -EINVAL;
2248         }
2249
2250         switch (type) {
2251         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2252                 if (!sienna_cichlid_is_od_feature_supported(od_settings,
2253                                                             SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
2254                         dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2255                         return -ENOTSUPP;
2256                 }
2257
2258                 for (i = 0; i < size; i += 2) {
2259                         if (i + 2 > size) {
2260                                 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2261                                 return -EINVAL;
2262                         }
2263
2264                         switch (input[i]) {
2265                         case 0:
2266                                 if (input[i + 1] > od_table->GfxclkFmax) {
2267                                         dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2268                                                 input[i + 1], od_table->GfxclkFmax);
2269                                         return -EINVAL;
2270                                 }
2271
2272                                 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2273                                 freq_ptr = &od_table->GfxclkFmin;
2274                                 break;
2275
2276                         case 1:
2277                                 if (input[i + 1] < od_table->GfxclkFmin) {
2278                                         dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2279                                                 input[i + 1], od_table->GfxclkFmin);
2280                                         return -EINVAL;
2281                                 }
2282
2283                                 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2284                                 freq_ptr = &od_table->GfxclkFmax;
2285                                 break;
2286
2287                         default:
2288                                 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2289                                 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2290                                 return -EINVAL;
2291                         }
2292
2293                         ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2294                                                                     freq_setting, input[i + 1]);
2295                         if (ret)
2296                                 return ret;
2297
2298                         *freq_ptr = (uint16_t)input[i + 1];
2299                 }
2300                 break;
2301
2302         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2303                 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2304                         dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2305                         return -ENOTSUPP;
2306                 }
2307
2308                 for (i = 0; i < size; i += 2) {
2309                         if (i + 2 > size) {
2310                                 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2311                                 return -EINVAL;
2312                         }
2313
2314                         switch (input[i]) {
2315                         case 0:
2316                                 if (input[i + 1] > od_table->UclkFmax) {
2317                                         dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2318                                                 input[i + 1], od_table->UclkFmax);
2319                                         return -EINVAL;
2320                                 }
2321
2322                                 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2323                                 freq_ptr = &od_table->UclkFmin;
2324                                 break;
2325
2326                         case 1:
2327                                 if (input[i + 1] < od_table->UclkFmin) {
2328                                         dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2329                                                 input[i + 1], od_table->UclkFmin);
2330                                         return -EINVAL;
2331                                 }
2332
2333                                 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2334                                 freq_ptr = &od_table->UclkFmax;
2335                                 break;
2336
2337                         default:
2338                                 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2339                                 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2340                                 return -EINVAL;
2341                         }
2342
2343                         ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2344                                                                     freq_setting, input[i + 1]);
2345                         if (ret)
2346                                 return ret;
2347
2348                         *freq_ptr = (uint16_t)input[i + 1];
2349                 }
2350                 break;
2351
2352         case PP_OD_RESTORE_DEFAULT_TABLE:
2353                 memcpy(table_context->overdrive_table,
2354                                 table_context->boot_overdrive_table,
2355                                 sizeof(OverDriveTable_t));
2356                 fallthrough;
2357
2358         case PP_OD_COMMIT_DPM_TABLE:
2359                 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2360                         sienna_cichlid_dump_od_table(smu, od_table);
2361                         ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2362                         if (ret) {
2363                                 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2364                                 return ret;
2365                         }
2366                         memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2367                         smu->user_dpm_profile.user_od = true;
2368
2369                         if (!memcmp(table_context->user_overdrive_table,
2370                                     table_context->boot_overdrive_table,
2371                                     sizeof(OverDriveTable_t)))
2372                                 smu->user_dpm_profile.user_od = false;
2373                 }
2374                 break;
2375
2376         case PP_OD_EDIT_VDDGFX_OFFSET:
2377                 if (size != 1) {
2378                         dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2379                         return -EINVAL;
2380                 }
2381
2382                 /*
2383                  * OD GFX Voltage Offset functionality is supported only by 58.41.0
2384                  * and onwards SMU firmwares.
2385                  */
2386                 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
2387                      IP_VERSION(11, 0, 7)) &&
2388                     (smu->smc_fw_version < 0x003a2900)) {
2389                         dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2390                                                 "only by 58.41.0 and onwards SMU firmwares!\n");
2391                         return -EOPNOTSUPP;
2392                 }
2393
2394                 od_table->VddGfxOffset = (int16_t)input[0];
2395
2396                 sienna_cichlid_dump_od_table(smu, od_table);
2397                 break;
2398
2399         default:
2400                 return -ENOSYS;
2401         }
2402
2403         return ret;
2404 }
2405
2406 static int sienna_cichlid_restore_user_od_settings(struct smu_context *smu)
2407 {
2408         struct smu_table_context *table_context = &smu->smu_table;
2409         OverDriveTable_t *od_table = table_context->overdrive_table;
2410         OverDriveTable_t *user_od_table = table_context->user_overdrive_table;
2411         int res;
2412
2413         res = smu_v11_0_restore_user_od_settings(smu);
2414         if (res == 0)
2415                 memcpy(od_table, user_od_table, sizeof(OverDriveTable_t));
2416
2417         return res;
2418 }
2419
2420 static int sienna_cichlid_run_btc(struct smu_context *smu)
2421 {
2422         int res;
2423
2424         res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2425         if (res)
2426                 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2427
2428         return res;
2429 }
2430
2431 static int sienna_cichlid_baco_enter(struct smu_context *smu)
2432 {
2433         struct amdgpu_device *adev = smu->adev;
2434
2435         if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
2436                 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2437         else
2438                 return smu_v11_0_baco_enter(smu);
2439 }
2440
2441 static int sienna_cichlid_baco_exit(struct smu_context *smu)
2442 {
2443         struct amdgpu_device *adev = smu->adev;
2444
2445         if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2446                 /* Wait for PMFW handling for the Dstate change */
2447                 msleep(10);
2448                 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2449         } else {
2450                 return smu_v11_0_baco_exit(smu);
2451         }
2452 }
2453
2454 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2455 {
2456         struct amdgpu_device *adev = smu->adev;
2457         uint32_t val;
2458
2459         /**
2460          * SRIOV env will not support SMU mode1 reset
2461          * PM FW support mode1 reset from 58.26
2462          */
2463         if (amdgpu_sriov_vf(adev) || (smu->smc_fw_version < 0x003a1a00))
2464                 return false;
2465
2466         /**
2467          * mode1 reset relies on PSP, so we should check if
2468          * PSP is alive.
2469          */
2470         val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2471         return val != 0x0;
2472 }
2473
2474 static void beige_goby_dump_pptable(struct smu_context *smu)
2475 {
2476         struct smu_table_context *table_context = &smu->smu_table;
2477         PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2478         int i;
2479
2480         dev_info(smu->adev->dev, "Dumped PPTable:\n");
2481
2482         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2483         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2484         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2485
2486         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2487                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2488                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2489                 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2490                 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2491         }
2492
2493         for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2494                 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2495                 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2496         }
2497
2498         for (i = 0; i < TEMP_COUNT; i++) {
2499                 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2500         }
2501
2502         dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2503         dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2504         dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2505         dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2506         dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2507
2508         dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2509         for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2510                 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2511                 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2512         }
2513         dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2514
2515         dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2516
2517         dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2518         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2519         dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2520         dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2521
2522         dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2523
2524         dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2525
2526         dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2527         dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2528         dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2529         dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2530
2531         dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2532         dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2533
2534         dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2535         dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2536         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2537         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2538         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2539         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2540         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2541         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2542
2543         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2544                         "  .VoltageMode          = 0x%02x\n"
2545                         "  .SnapToDiscrete       = 0x%02x\n"
2546                         "  .NumDiscreteLevels    = 0x%02x\n"
2547                         "  .padding              = 0x%02x\n"
2548                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2549                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2550                         "  .SsFmin               = 0x%04x\n"
2551                         "  .Padding_16           = 0x%04x\n",
2552                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2553                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2554                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2555                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2556                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2557                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2558                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2559                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2560                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2561                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2562                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2563
2564         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2565                         "  .VoltageMode          = 0x%02x\n"
2566                         "  .SnapToDiscrete       = 0x%02x\n"
2567                         "  .NumDiscreteLevels    = 0x%02x\n"
2568                         "  .padding              = 0x%02x\n"
2569                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2570                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2571                         "  .SsFmin               = 0x%04x\n"
2572                         "  .Padding_16           = 0x%04x\n",
2573                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2574                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2575                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2576                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2577                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2578                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2579                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2580                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2581                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2582                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2583                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2584
2585         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2586                         "  .VoltageMode          = 0x%02x\n"
2587                         "  .SnapToDiscrete       = 0x%02x\n"
2588                         "  .NumDiscreteLevels    = 0x%02x\n"
2589                         "  .padding              = 0x%02x\n"
2590                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2591                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2592                         "  .SsFmin               = 0x%04x\n"
2593                         "  .Padding_16           = 0x%04x\n",
2594                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2595                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2596                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2597                         pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2598                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2599                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2600                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2601                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2602                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2603                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2604                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2605
2606         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2607                         "  .VoltageMode          = 0x%02x\n"
2608                         "  .SnapToDiscrete       = 0x%02x\n"
2609                         "  .NumDiscreteLevels    = 0x%02x\n"
2610                         "  .padding              = 0x%02x\n"
2611                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2612                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2613                         "  .SsFmin               = 0x%04x\n"
2614                         "  .Padding_16           = 0x%04x\n",
2615                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2616                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2617                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2618                         pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2619                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2620                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2621                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2622                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2623                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2624                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2625                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2626
2627         dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2628                         "  .VoltageMode          = 0x%02x\n"
2629                         "  .SnapToDiscrete       = 0x%02x\n"
2630                         "  .NumDiscreteLevels    = 0x%02x\n"
2631                         "  .padding              = 0x%02x\n"
2632                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2633                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2634                         "  .SsFmin               = 0x%04x\n"
2635                         "  .Padding_16           = 0x%04x\n",
2636                         pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2637                         pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2638                         pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2639                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2640                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2641                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2642                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2643                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2644                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2645                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2646                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2647
2648         dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2649                         "  .VoltageMode          = 0x%02x\n"
2650                         "  .SnapToDiscrete       = 0x%02x\n"
2651                         "  .NumDiscreteLevels    = 0x%02x\n"
2652                         "  .padding              = 0x%02x\n"
2653                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2654                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2655                         "  .SsFmin               = 0x%04x\n"
2656                         "  .Padding_16           = 0x%04x\n",
2657                         pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2658                         pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2659                         pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2660                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2661                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2662                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2663                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2664                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2665                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2666                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2667                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2668
2669         dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2670                         "  .VoltageMode          = 0x%02x\n"
2671                         "  .SnapToDiscrete       = 0x%02x\n"
2672                         "  .NumDiscreteLevels    = 0x%02x\n"
2673                         "  .padding              = 0x%02x\n"
2674                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2675                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2676                         "  .SsFmin               = 0x%04x\n"
2677                         "  .Padding_16           = 0x%04x\n",
2678                         pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2679                         pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2680                         pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2681                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2682                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2683                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2684                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2685                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2686                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2687                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2688                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2689
2690         dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2691                         "  .VoltageMode          = 0x%02x\n"
2692                         "  .SnapToDiscrete       = 0x%02x\n"
2693                         "  .NumDiscreteLevels    = 0x%02x\n"
2694                         "  .padding              = 0x%02x\n"
2695                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2696                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2697                         "  .SsFmin               = 0x%04x\n"
2698                         "  .Padding_16           = 0x%04x\n",
2699                         pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2700                         pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2701                         pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2702                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2703                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2704                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2705                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2706                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2707                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2708                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2709                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2710
2711         dev_info(smu->adev->dev, "FreqTableGfx\n");
2712         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2713                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2714
2715         dev_info(smu->adev->dev, "FreqTableVclk\n");
2716         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2717                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2718
2719         dev_info(smu->adev->dev, "FreqTableDclk\n");
2720         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2721                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2722
2723         dev_info(smu->adev->dev, "FreqTableSocclk\n");
2724         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2725                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2726
2727         dev_info(smu->adev->dev, "FreqTableUclk\n");
2728         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2729                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2730
2731         dev_info(smu->adev->dev, "FreqTableFclk\n");
2732         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2733                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2734
2735         dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2736         dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2737         dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2738         dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2739         dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2740         dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2741         dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2742         dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2743         dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2744
2745         dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2746         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2747                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2748
2749         dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2750         dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2751
2752         dev_info(smu->adev->dev, "Mp0clkFreq\n");
2753         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2754                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2755
2756         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2757         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2758                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2759
2760         dev_info(smu->adev->dev, "MemVddciVoltage\n");
2761         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2762                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2763
2764         dev_info(smu->adev->dev, "MemMvddVoltage\n");
2765         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2766                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2767
2768         dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2769         dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2770         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2771         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2772         dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2773
2774         dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2775
2776         dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2777         dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2778         dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2779         dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2780         dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2781         dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2782         dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2783         dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2784         dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2785         dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2786         dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2787
2788         dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2789         dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2790         dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2791         dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2792         dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2793         dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2794
2795         dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2796         dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2797         dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2798         dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2799         dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2800
2801         dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2802         for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2803                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2804
2805         dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2806         dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2807         dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2808         dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2809
2810         dev_info(smu->adev->dev, "UclkDpmPstates\n");
2811         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2812                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2813
2814         dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2815         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2816                 pptable->UclkDpmSrcFreqRange.Fmin);
2817         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2818                 pptable->UclkDpmSrcFreqRange.Fmax);
2819         dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2820         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2821                 pptable->UclkDpmTargFreqRange.Fmin);
2822         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2823                 pptable->UclkDpmTargFreqRange.Fmax);
2824         dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2825         dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2826
2827         dev_info(smu->adev->dev, "PcieGenSpeed\n");
2828         for (i = 0; i < NUM_LINK_LEVELS; i++)
2829                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2830
2831         dev_info(smu->adev->dev, "PcieLaneCount\n");
2832         for (i = 0; i < NUM_LINK_LEVELS; i++)
2833                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2834
2835         dev_info(smu->adev->dev, "LclkFreq\n");
2836         for (i = 0; i < NUM_LINK_LEVELS; i++)
2837                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2838
2839         dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2840         dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2841
2842         dev_info(smu->adev->dev, "FanGain\n");
2843         for (i = 0; i < TEMP_COUNT; i++)
2844                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2845
2846         dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2847         dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2848         dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2849         dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2850         dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2851         dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2852         dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2853         dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2854         dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2855         dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2856         dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2857         dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2858
2859         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2860         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2861         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2862         dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2863
2864         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2865         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2866         dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2867         dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2868
2869         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2870                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2871                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2872                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2873         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2874                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2875                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2876                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2877         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2878                         pptable->dBtcGbGfxPll.a,
2879                         pptable->dBtcGbGfxPll.b,
2880                         pptable->dBtcGbGfxPll.c);
2881         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2882                         pptable->dBtcGbGfxDfll.a,
2883                         pptable->dBtcGbGfxDfll.b,
2884                         pptable->dBtcGbGfxDfll.c);
2885         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2886                         pptable->dBtcGbSoc.a,
2887                         pptable->dBtcGbSoc.b,
2888                         pptable->dBtcGbSoc.c);
2889         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2890                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2891                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2892         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2893                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2894                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2895
2896         dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2897         for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2898                 dev_info(smu->adev->dev, "              Fset[%d] = 0x%x\n",
2899                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2900                 dev_info(smu->adev->dev, "              Vdroop[%d] = 0x%x\n",
2901                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2902         }
2903
2904         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2905                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2906                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2907                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2908         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2909                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2910                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2911                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2912
2913         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2914         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2915
2916         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2917         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2918         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2919         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2920
2921         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2922         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2923         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2924         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2925
2926         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2927         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2928
2929         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2930         for (i = 0; i < NUM_XGMI_LEVELS; i++)
2931                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2932         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2933         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2934
2935         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2936         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2937                         pptable->ReservedEquation0.a,
2938                         pptable->ReservedEquation0.b,
2939                         pptable->ReservedEquation0.c);
2940         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2941                         pptable->ReservedEquation1.a,
2942                         pptable->ReservedEquation1.b,
2943                         pptable->ReservedEquation1.c);
2944         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2945                         pptable->ReservedEquation2.a,
2946                         pptable->ReservedEquation2.b,
2947                         pptable->ReservedEquation2.c);
2948         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2949                         pptable->ReservedEquation3.a,
2950                         pptable->ReservedEquation3.b,
2951                         pptable->ReservedEquation3.c);
2952
2953         dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2954         dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2955         dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2956         dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2957         dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2958         dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2959         dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2960         dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2961
2962         dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2963         dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2964         dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2965         dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2966         dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2967         dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2968
2969         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2970                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2971                 dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
2972                                 pptable->I2cControllers[i].Enabled);
2973                 dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
2974                                 pptable->I2cControllers[i].Speed);
2975                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
2976                                 pptable->I2cControllers[i].SlaveAddress);
2977                 dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
2978                                 pptable->I2cControllers[i].ControllerPort);
2979                 dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
2980                                 pptable->I2cControllers[i].ControllerName);
2981                 dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
2982                                 pptable->I2cControllers[i].ThermalThrotter);
2983                 dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
2984                                 pptable->I2cControllers[i].I2cProtocol);
2985                 dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
2986                                 pptable->I2cControllers[i].PaddingConfig);
2987         }
2988
2989         dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2990         dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2991         dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2992         dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2993
2994         dev_info(smu->adev->dev, "Board Parameters:\n");
2995         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2996         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2997         dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2998         dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2999         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3000         dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3001         dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3002         dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3003
3004         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3005         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3006         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3007
3008         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3009         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3010         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3011
3012         dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3013         dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3014         dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3015
3016         dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3017         dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3018         dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3019
3020         dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3021
3022         dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3023         dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3024         dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3025         dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3026         dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3027         dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3028         dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3029         dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3030         dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3031         dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3032         dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3033         dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3034         dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3035         dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3036         dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3037         dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3038
3039         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3040         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3041         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
3042
3043         dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3044         dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3045         dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
3046
3047         dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3048         dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3049
3050         dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3051         dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3052         dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3053
3054         dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3055         dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3056         dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3057         dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3058         dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3059
3060         dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3061         dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3062
3063         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3064         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3065                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3066         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3067         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3068                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3069         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3070         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3071                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3072         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3073         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3074                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3075
3076         dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3077         dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3078         dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3079         dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3080
3081         dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3082         dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3083         dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3084         dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3085         dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3086         dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3087         dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3088         dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3089         dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3090         dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3091         dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3092
3093         dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3094         dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3095         dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3096         dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3097         dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3098         dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3099         dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3100         dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3101 }
3102
3103 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
3104 {
3105         struct smu_table_context *table_context = &smu->smu_table;
3106         PPTable_t *pptable = table_context->driver_pptable;
3107         int i;
3108
3109         if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
3110             IP_VERSION(11, 0, 13)) {
3111                 beige_goby_dump_pptable(smu);
3112                 return;
3113         }
3114
3115         dev_info(smu->adev->dev, "Dumped PPTable:\n");
3116
3117         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
3118         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
3119         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
3120
3121         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
3122                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
3123                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
3124                 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
3125                 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
3126         }
3127
3128         for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
3129                 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
3130                 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
3131         }
3132
3133         for (i = 0; i < TEMP_COUNT; i++) {
3134                 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
3135         }
3136
3137         dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
3138         dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
3139         dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
3140         dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
3141         dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
3142
3143         dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
3144         for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
3145                 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
3146                 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
3147         }
3148         dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
3149
3150         dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
3151
3152         dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
3153         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
3154         dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
3155         dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
3156
3157         dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
3158         dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
3159
3160         dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
3161         dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
3162         dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
3163         dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
3164
3165         dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
3166         dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
3167         dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
3168         dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
3169
3170         dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
3171         dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
3172
3173         dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
3174         dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
3175         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
3176         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
3177         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
3178         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
3179         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
3180         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
3181
3182         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
3183                         "  .VoltageMode          = 0x%02x\n"
3184                         "  .SnapToDiscrete       = 0x%02x\n"
3185                         "  .NumDiscreteLevels    = 0x%02x\n"
3186                         "  .padding              = 0x%02x\n"
3187                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3188                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3189                         "  .SsFmin               = 0x%04x\n"
3190                         "  .Padding_16           = 0x%04x\n",
3191                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
3192                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
3193                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
3194                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
3195                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
3196                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
3197                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
3198                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
3199                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
3200                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
3201                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
3202
3203         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
3204                         "  .VoltageMode          = 0x%02x\n"
3205                         "  .SnapToDiscrete       = 0x%02x\n"
3206                         "  .NumDiscreteLevels    = 0x%02x\n"
3207                         "  .padding              = 0x%02x\n"
3208                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3209                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3210                         "  .SsFmin               = 0x%04x\n"
3211                         "  .Padding_16           = 0x%04x\n",
3212                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
3213                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
3214                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
3215                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
3216                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
3217                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
3218                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
3219                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
3220                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
3221                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
3222                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
3223
3224         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
3225                         "  .VoltageMode          = 0x%02x\n"
3226                         "  .SnapToDiscrete       = 0x%02x\n"
3227                         "  .NumDiscreteLevels    = 0x%02x\n"
3228                         "  .padding              = 0x%02x\n"
3229                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3230                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3231                         "  .SsFmin               = 0x%04x\n"
3232                         "  .Padding_16           = 0x%04x\n",
3233                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
3234                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
3235                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
3236                         pptable->DpmDescriptor[PPCLK_UCLK].Padding,
3237                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
3238                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
3239                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
3240                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
3241                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
3242                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
3243                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
3244
3245         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
3246                         "  .VoltageMode          = 0x%02x\n"
3247                         "  .SnapToDiscrete       = 0x%02x\n"
3248                         "  .NumDiscreteLevels    = 0x%02x\n"
3249                         "  .padding              = 0x%02x\n"
3250                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3251                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3252                         "  .SsFmin               = 0x%04x\n"
3253                         "  .Padding_16           = 0x%04x\n",
3254                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
3255                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
3256                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
3257                         pptable->DpmDescriptor[PPCLK_FCLK].Padding,
3258                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
3259                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
3260                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
3261                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
3262                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
3263                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
3264                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
3265
3266         dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
3267                         "  .VoltageMode          = 0x%02x\n"
3268                         "  .SnapToDiscrete       = 0x%02x\n"
3269                         "  .NumDiscreteLevels    = 0x%02x\n"
3270                         "  .padding              = 0x%02x\n"
3271                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3272                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3273                         "  .SsFmin               = 0x%04x\n"
3274                         "  .Padding_16           = 0x%04x\n",
3275                         pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
3276                         pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
3277                         pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
3278                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
3279                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
3280                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
3281                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
3282                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
3283                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
3284                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
3285                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
3286
3287         dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
3288                         "  .VoltageMode          = 0x%02x\n"
3289                         "  .SnapToDiscrete       = 0x%02x\n"
3290                         "  .NumDiscreteLevels    = 0x%02x\n"
3291                         "  .padding              = 0x%02x\n"
3292                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3293                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3294                         "  .SsFmin               = 0x%04x\n"
3295                         "  .Padding_16           = 0x%04x\n",
3296                         pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3297                         pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3298                         pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3299                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3300                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3301                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3302                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3303                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3304                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3305                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3306                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3307
3308         dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
3309                         "  .VoltageMode          = 0x%02x\n"
3310                         "  .SnapToDiscrete       = 0x%02x\n"
3311                         "  .NumDiscreteLevels    = 0x%02x\n"
3312                         "  .padding              = 0x%02x\n"
3313                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3314                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3315                         "  .SsFmin               = 0x%04x\n"
3316                         "  .Padding_16           = 0x%04x\n",
3317                         pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3318                         pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3319                         pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3320                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3321                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3322                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3323                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3324                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3325                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3326                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3327                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3328
3329         dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
3330                         "  .VoltageMode          = 0x%02x\n"
3331                         "  .SnapToDiscrete       = 0x%02x\n"
3332                         "  .NumDiscreteLevels    = 0x%02x\n"
3333                         "  .padding              = 0x%02x\n"
3334                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3335                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3336                         "  .SsFmin               = 0x%04x\n"
3337                         "  .Padding_16           = 0x%04x\n",
3338                         pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3339                         pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3340                         pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3341                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3342                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3343                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3344                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3345                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3346                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3347                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3348                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3349
3350         dev_info(smu->adev->dev, "FreqTableGfx\n");
3351         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
3352                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
3353
3354         dev_info(smu->adev->dev, "FreqTableVclk\n");
3355         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
3356                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
3357
3358         dev_info(smu->adev->dev, "FreqTableDclk\n");
3359         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
3360                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
3361
3362         dev_info(smu->adev->dev, "FreqTableSocclk\n");
3363         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
3364                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
3365
3366         dev_info(smu->adev->dev, "FreqTableUclk\n");
3367         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3368                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
3369
3370         dev_info(smu->adev->dev, "FreqTableFclk\n");
3371         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
3372                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3373
3374         dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3375         dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3376         dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3377         dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3378         dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3379         dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3380         dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3381         dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3382         dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3383
3384         dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
3385         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3386                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
3387
3388         dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3389         dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
3390
3391         dev_info(smu->adev->dev, "Mp0clkFreq\n");
3392         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3393                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
3394
3395         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
3396         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3397                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
3398
3399         dev_info(smu->adev->dev, "MemVddciVoltage\n");
3400         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3401                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
3402
3403         dev_info(smu->adev->dev, "MemMvddVoltage\n");
3404         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3405                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3406
3407         dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3408         dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3409         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3410         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3411         dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3412
3413         dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3414
3415         dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3416         dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3417         dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3418         dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3419         dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3420         dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3421         dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3422         dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3423         dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3424         dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3425         dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3426
3427         dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3428         dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3429         dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3430         dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3431         dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3432         dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3433
3434         dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3435         dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3436         dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3437         dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3438         dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3439
3440         dev_info(smu->adev->dev, "FlopsPerByteTable\n");
3441         for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
3442                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
3443
3444         dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3445         dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3446         dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3447         dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
3448
3449         dev_info(smu->adev->dev, "UclkDpmPstates\n");
3450         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3451                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
3452
3453         dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3454         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
3455                 pptable->UclkDpmSrcFreqRange.Fmin);
3456         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
3457                 pptable->UclkDpmSrcFreqRange.Fmax);
3458         dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3459         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
3460                 pptable->UclkDpmTargFreqRange.Fmin);
3461         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
3462                 pptable->UclkDpmTargFreqRange.Fmax);
3463         dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3464         dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
3465
3466         dev_info(smu->adev->dev, "PcieGenSpeed\n");
3467         for (i = 0; i < NUM_LINK_LEVELS; i++)
3468                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
3469
3470         dev_info(smu->adev->dev, "PcieLaneCount\n");
3471         for (i = 0; i < NUM_LINK_LEVELS; i++)
3472                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
3473
3474         dev_info(smu->adev->dev, "LclkFreq\n");
3475         for (i = 0; i < NUM_LINK_LEVELS; i++)
3476                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
3477
3478         dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3479         dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
3480
3481         dev_info(smu->adev->dev, "FanGain\n");
3482         for (i = 0; i < TEMP_COUNT; i++)
3483                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3484
3485         dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3486         dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3487         dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3488         dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3489         dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3490         dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3491         dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3492         dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3493         dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3494         dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3495         dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3496         dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3497
3498         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3499         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3500         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3501         dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3502
3503         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3504         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3505         dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3506         dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3507
3508         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3509                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3510                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3511                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
3512         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3513                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3514                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3515                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
3516         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
3517                         pptable->dBtcGbGfxPll.a,
3518                         pptable->dBtcGbGfxPll.b,
3519                         pptable->dBtcGbGfxPll.c);
3520         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
3521                         pptable->dBtcGbGfxDfll.a,
3522                         pptable->dBtcGbGfxDfll.b,
3523                         pptable->dBtcGbGfxDfll.c);
3524         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
3525                         pptable->dBtcGbSoc.a,
3526                         pptable->dBtcGbSoc.b,
3527                         pptable->dBtcGbSoc.c);
3528         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
3529                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3530                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
3531         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
3532                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3533                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3534
3535         dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
3536         for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
3537                 dev_info(smu->adev->dev, "              Fset[%d] = 0x%x\n",
3538                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
3539                 dev_info(smu->adev->dev, "              Vdroop[%d] = 0x%x\n",
3540                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3541         }
3542
3543         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3544                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3545                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3546                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
3547         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3548                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3549                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3550                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3551
3552         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3553         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
3554
3555         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3556         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3557         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3558         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
3559
3560         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3561         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3562         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3563         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
3564
3565         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3566         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
3567
3568         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
3569         for (i = 0; i < NUM_XGMI_LEVELS; i++)
3570                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3571         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3572         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
3573
3574         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3575         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
3576                         pptable->ReservedEquation0.a,
3577                         pptable->ReservedEquation0.b,
3578                         pptable->ReservedEquation0.c);
3579         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
3580                         pptable->ReservedEquation1.a,
3581                         pptable->ReservedEquation1.b,
3582                         pptable->ReservedEquation1.c);
3583         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
3584                         pptable->ReservedEquation2.a,
3585                         pptable->ReservedEquation2.b,
3586                         pptable->ReservedEquation2.c);
3587         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
3588                         pptable->ReservedEquation3.a,
3589                         pptable->ReservedEquation3.b,
3590                         pptable->ReservedEquation3.c);
3591
3592         dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3593         dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3594         dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3595         dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3596         dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3597         dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3598         dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3599         dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
3600
3601         dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3602         dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3603         dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3604         dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3605         dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3606         dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
3607
3608         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
3609                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3610                 dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
3611                                 pptable->I2cControllers[i].Enabled);
3612                 dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
3613                                 pptable->I2cControllers[i].Speed);
3614                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
3615                                 pptable->I2cControllers[i].SlaveAddress);
3616                 dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
3617                                 pptable->I2cControllers[i].ControllerPort);
3618                 dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
3619                                 pptable->I2cControllers[i].ControllerName);
3620                 dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
3621                                 pptable->I2cControllers[i].ThermalThrotter);
3622                 dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
3623                                 pptable->I2cControllers[i].I2cProtocol);
3624                 dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
3625                                 pptable->I2cControllers[i].PaddingConfig);
3626         }
3627
3628         dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3629         dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3630         dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3631         dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3632
3633         dev_info(smu->adev->dev, "Board Parameters:\n");
3634         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3635         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3636         dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3637         dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3638         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3639         dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3640         dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3641         dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3642
3643         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3644         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3645         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3646
3647         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3648         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3649         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3650
3651         dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3652         dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3653         dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3654
3655         dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3656         dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3657         dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3658
3659         dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3660
3661         dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3662         dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3663         dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3664         dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3665         dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3666         dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3667         dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3668         dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3669         dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3670         dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3671         dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3672         dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3673         dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3674         dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3675         dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3676         dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3677
3678         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3679         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3680         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
3681
3682         dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3683         dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3684         dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
3685
3686         dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3687         dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3688
3689         dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3690         dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3691         dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3692
3693         dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3694         dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3695         dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3696         dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3697         dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3698
3699         dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3700         dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3701
3702         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3703         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3704                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3705         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3706         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3707                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3708         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3709         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3710                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3711         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3712         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3713                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3714
3715         dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3716         dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3717         dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3718         dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3719
3720         dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3721         dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3722         dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3723         dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3724         dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3725         dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3726         dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3727         dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3728         dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3729         dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3730         dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3731
3732         dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3733         dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3734         dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3735         dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3736         dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3737         dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3738         dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3739         dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3740 }
3741
3742 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
3743                                    struct i2c_msg *msg, int num_msgs)
3744 {
3745         struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
3746         struct amdgpu_device *adev = smu_i2c->adev;
3747         struct smu_context *smu = adev->powerplay.pp_handle;
3748         struct smu_table_context *smu_table = &smu->smu_table;
3749         struct smu_table *table = &smu_table->driver_table;
3750         SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
3751         int i, j, r, c;
3752         u16 dir;
3753
3754         if (!adev->pm.dpm_enabled)
3755                 return -EBUSY;
3756
3757         req = kzalloc(sizeof(*req), GFP_KERNEL);
3758         if (!req)
3759                 return -ENOMEM;
3760
3761         req->I2CcontrollerPort = smu_i2c->port;
3762         req->I2CSpeed = I2C_SPEED_FAST_400K;
3763         req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
3764         dir = msg[0].flags & I2C_M_RD;
3765
3766         for (c = i = 0; i < num_msgs; i++) {
3767                 for (j = 0; j < msg[i].len; j++, c++) {
3768                         SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
3769
3770                         if (!(msg[i].flags & I2C_M_RD)) {
3771                                 /* write */
3772                                 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
3773                                 cmd->ReadWriteData = msg[i].buf[j];
3774                         }
3775
3776                         if ((dir ^ msg[i].flags) & I2C_M_RD) {
3777                                 /* The direction changes.
3778                                  */
3779                                 dir = msg[i].flags & I2C_M_RD;
3780                                 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
3781                         }
3782
3783                         req->NumCmds++;
3784
3785                         /*
3786                          * Insert STOP if we are at the last byte of either last
3787                          * message for the transaction or the client explicitly
3788                          * requires a STOP at this particular message.
3789                          */
3790                         if ((j == msg[i].len - 1) &&
3791                             ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3792                                 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
3793                                 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
3794                         }
3795                 }
3796         }
3797         mutex_lock(&adev->pm.mutex);
3798         r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
3799         if (r)
3800                 goto fail;
3801
3802         for (c = i = 0; i < num_msgs; i++) {
3803                 if (!(msg[i].flags & I2C_M_RD)) {
3804                         c += msg[i].len;
3805                         continue;
3806                 }
3807                 for (j = 0; j < msg[i].len; j++, c++) {
3808                         SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
3809
3810                         msg[i].buf[j] = cmd->ReadWriteData;
3811                 }
3812         }
3813         r = num_msgs;
3814 fail:
3815         mutex_unlock(&adev->pm.mutex);
3816         kfree(req);
3817         return r;
3818 }
3819
3820 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3821 {
3822         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3823 }
3824
3825
3826 static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3827         .master_xfer = sienna_cichlid_i2c_xfer,
3828         .functionality = sienna_cichlid_i2c_func,
3829 };
3830
3831 static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
3832         .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
3833         .max_read_len  = MAX_SW_I2C_COMMANDS,
3834         .max_write_len = MAX_SW_I2C_COMMANDS,
3835         .max_comb_1st_msg_len = 2,
3836         .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
3837 };
3838
3839 static int sienna_cichlid_i2c_control_init(struct smu_context *smu)
3840 {
3841         struct amdgpu_device *adev = smu->adev;
3842         int res, i;
3843
3844         for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3845                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3846                 struct i2c_adapter *control = &smu_i2c->adapter;
3847
3848                 smu_i2c->adev = adev;
3849                 smu_i2c->port = i;
3850                 mutex_init(&smu_i2c->mutex);
3851                 control->owner = THIS_MODULE;
3852                 control->class = I2C_CLASS_HWMON;
3853                 control->dev.parent = &adev->pdev->dev;
3854                 control->algo = &sienna_cichlid_i2c_algo;
3855                 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
3856                 control->quirks = &sienna_cichlid_i2c_control_quirks;
3857                 i2c_set_adapdata(control, smu_i2c);
3858
3859                 res = i2c_add_adapter(control);
3860                 if (res) {
3861                         DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3862                         goto Out_err;
3863                 }
3864         }
3865         /* assign the buses used for the FRU EEPROM and RAS EEPROM */
3866         /* XXX ideally this would be something in a vbios data table */
3867         adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
3868         adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
3869
3870         return 0;
3871 Out_err:
3872         for ( ; i >= 0; i--) {
3873                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3874                 struct i2c_adapter *control = &smu_i2c->adapter;
3875
3876                 i2c_del_adapter(control);
3877         }
3878         return res;
3879 }
3880
3881 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu)
3882 {
3883         struct amdgpu_device *adev = smu->adev;
3884         int i;
3885
3886         for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3887                 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3888                 struct i2c_adapter *control = &smu_i2c->adapter;
3889
3890                 i2c_del_adapter(control);
3891         }
3892         adev->pm.ras_eeprom_i2c_bus = NULL;
3893         adev->pm.fru_eeprom_i2c_bus = NULL;
3894 }
3895
3896 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3897                                               void **table)
3898 {
3899         struct smu_table_context *smu_table = &smu->smu_table;
3900         struct gpu_metrics_v1_3 *gpu_metrics =
3901                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3902         SmuMetricsExternal_t metrics_external;
3903         SmuMetrics_t *metrics =
3904                 &(metrics_external.SmuMetrics);
3905         SmuMetrics_V2_t *metrics_v2 =
3906                 &(metrics_external.SmuMetrics_V2);
3907         SmuMetrics_V3_t *metrics_v3 =
3908                 &(metrics_external.SmuMetrics_V3);
3909         struct amdgpu_device *adev = smu->adev;
3910         bool use_metrics_v2 = false;
3911         bool use_metrics_v3 = false;
3912         uint16_t average_gfx_activity;
3913         int ret = 0;
3914
3915         switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
3916         case IP_VERSION(11, 0, 7):
3917                 if (smu->smc_fw_version >= 0x3A4900)
3918                         use_metrics_v3 = true;
3919                 else if (smu->smc_fw_version >= 0x3A4300)
3920                         use_metrics_v2 = true;
3921                 break;
3922         case IP_VERSION(11, 0, 11):
3923                 if (smu->smc_fw_version >= 0x412D00)
3924                         use_metrics_v2 = true;
3925                 break;
3926         case IP_VERSION(11, 0, 12):
3927                 if (smu->smc_fw_version >= 0x3B2300)
3928                         use_metrics_v2 = true;
3929                 break;
3930         case IP_VERSION(11, 0, 13):
3931                 if (smu->smc_fw_version >= 0x491100)
3932                         use_metrics_v2 = true;
3933                 break;
3934         default:
3935                 break;
3936         }
3937
3938         ret = smu_cmn_get_metrics_table(smu,
3939                                         &metrics_external,
3940                                         true);
3941         if (ret)
3942                 return ret;
3943
3944         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3945
3946         gpu_metrics->temperature_edge = use_metrics_v3 ? metrics_v3->TemperatureEdge :
3947                 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge;
3948         gpu_metrics->temperature_hotspot = use_metrics_v3 ? metrics_v3->TemperatureHotspot :
3949                 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot;
3950         gpu_metrics->temperature_mem = use_metrics_v3 ? metrics_v3->TemperatureMem :
3951                 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem;
3952         gpu_metrics->temperature_vrgfx = use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
3953                 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx;
3954         gpu_metrics->temperature_vrsoc = use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
3955                 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc;
3956         gpu_metrics->temperature_vrmem = use_metrics_v3 ? metrics_v3->TemperatureVrMem0 :
3957                 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0;
3958
3959         gpu_metrics->average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
3960                 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3961         gpu_metrics->average_umc_activity = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
3962                 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity;
3963         gpu_metrics->average_mm_activity = use_metrics_v3 ?
3964                 (metrics_v3->VcnUsagePercentage0 + metrics_v3->VcnUsagePercentage1) / 2 :
3965                 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage;
3966
3967         gpu_metrics->average_socket_power = use_metrics_v3 ? metrics_v3->AverageSocketPower :
3968                 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower;
3969         gpu_metrics->energy_accumulator = use_metrics_v3 ? metrics_v3->EnergyAccumulator :
3970                 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator;
3971
3972         if (metrics->CurrGfxVoltageOffset)
3973                 gpu_metrics->voltage_gfx =
3974                         (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100;
3975         if (metrics->CurrMemVidOffset)
3976                 gpu_metrics->voltage_mem =
3977                         (155000 - 625 * metrics->CurrMemVidOffset) / 100;
3978         if (metrics->CurrSocVoltageOffset)
3979                 gpu_metrics->voltage_soc =
3980                         (155000 - 625 * metrics->CurrSocVoltageOffset) / 100;
3981
3982         average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
3983                 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3984         if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
3985                 gpu_metrics->average_gfxclk_frequency =
3986                         use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
3987                         use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
3988                         metrics->AverageGfxclkFrequencyPostDs;
3989         else
3990                 gpu_metrics->average_gfxclk_frequency =
3991                         use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
3992                         use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
3993                         metrics->AverageGfxclkFrequencyPreDs;
3994
3995         gpu_metrics->average_uclk_frequency =
3996                 use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
3997                 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
3998                 metrics->AverageUclkFrequencyPostDs;
3999         gpu_metrics->average_vclk0_frequency = use_metrics_v3 ? metrics_v3->AverageVclk0Frequency :
4000                 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency;
4001         gpu_metrics->average_dclk0_frequency = use_metrics_v3 ? metrics_v3->AverageDclk0Frequency :
4002                 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency;
4003         gpu_metrics->average_vclk1_frequency = use_metrics_v3 ? metrics_v3->AverageVclk1Frequency :
4004                 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency;
4005         gpu_metrics->average_dclk1_frequency = use_metrics_v3 ? metrics_v3->AverageDclk1Frequency :
4006                 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency;
4007
4008         gpu_metrics->current_gfxclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
4009                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK];
4010         gpu_metrics->current_socclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
4011                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK];
4012         gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
4013                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
4014         gpu_metrics->current_vclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
4015                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];
4016         gpu_metrics->current_dclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
4017                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0];
4018         gpu_metrics->current_vclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
4019                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1];
4020         gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
4021                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
4022
4023         gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2);
4024         gpu_metrics->indep_throttle_status =
4025                         smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
4026                                                            sienna_cichlid_throttler_map);
4027
4028         gpu_metrics->current_fan_speed = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
4029                 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
4030
4031         if (((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7)) &&
4032              smu->smc_fw_version > 0x003A1E00) ||
4033             ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 11)) &&
4034              smu->smc_fw_version > 0x00410400)) {
4035                 gpu_metrics->pcie_link_width = use_metrics_v3 ? metrics_v3->PcieWidth :
4036                         use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
4037                 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v3 ? metrics_v3->PcieRate :
4038                         use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
4039         } else {
4040                 gpu_metrics->pcie_link_width =
4041                                 smu_v11_0_get_current_pcie_link_width(smu);
4042                 gpu_metrics->pcie_link_speed =
4043                                 smu_v11_0_get_current_pcie_link_speed(smu);
4044         }
4045
4046         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
4047
4048         *table = (void *)gpu_metrics;
4049
4050         return sizeof(struct gpu_metrics_v1_3);
4051 }
4052
4053 static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu)
4054 {
4055         int ret = 0;
4056
4057         if (smu->smc_fw_version < SUPPORT_ECCTABLE_SMU_VERSION)
4058                 ret = -EOPNOTSUPP;
4059
4060         return ret;
4061 }
4062
4063 static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu,
4064                                         void *table)
4065 {
4066         struct smu_table_context *smu_table = &smu->smu_table;
4067         EccInfoTable_t *ecc_table = NULL;
4068         struct ecc_info_per_ch *ecc_info_per_channel = NULL;
4069         int i, ret = 0;
4070         struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
4071
4072         ret = sienna_cichlid_check_ecc_table_support(smu);
4073         if (ret)
4074                 return ret;
4075
4076         ret = smu_cmn_update_table(smu,
4077                                 SMU_TABLE_ECCINFO,
4078                                 0,
4079                                 smu_table->ecc_table,
4080                                 false);
4081         if (ret) {
4082                 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
4083                 return ret;
4084         }
4085
4086         ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
4087
4088         for (i = 0; i < SIENNA_CICHLID_UMC_CHANNEL_NUM; i++) {
4089                 ecc_info_per_channel = &(eccinfo->ecc[i]);
4090                 ecc_info_per_channel->ce_count_lo_chip =
4091                         ecc_table->EccInfo[i].ce_count_lo_chip;
4092                 ecc_info_per_channel->ce_count_hi_chip =
4093                         ecc_table->EccInfo[i].ce_count_hi_chip;
4094                 ecc_info_per_channel->mca_umc_status =
4095                         ecc_table->EccInfo[i].mca_umc_status;
4096                 ecc_info_per_channel->mca_umc_addr =
4097                         ecc_table->EccInfo[i].mca_umc_addr;
4098         }
4099
4100         return ret;
4101 }
4102 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
4103 {
4104         uint16_t *mgpu_fan_boost_limit_rpm;
4105
4106         GET_PPTABLE_MEMBER(MGpuFanBoostLimitRpm, &mgpu_fan_boost_limit_rpm);
4107         /*
4108          * Skip the MGpuFanBoost setting for those ASICs
4109          * which do not support it
4110          */
4111         if (*mgpu_fan_boost_limit_rpm == 0)
4112                 return 0;
4113
4114         return smu_cmn_send_smc_msg_with_param(smu,
4115                                                SMU_MSG_SetMGpuFanBoostLimitRpm,
4116                                                0,
4117                                                NULL);
4118 }
4119
4120 static int sienna_cichlid_gpo_control(struct smu_context *smu,
4121                                       bool enablement)
4122 {
4123         int ret = 0;
4124
4125
4126         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
4127
4128                 if (enablement) {
4129                         if (smu->smc_fw_version < 0x003a2500) {
4130                                 ret = smu_cmn_send_smc_msg_with_param(smu,
4131                                                                       SMU_MSG_SetGpoFeaturePMask,
4132                                                                       GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
4133                                                                       NULL);
4134                         } else {
4135                                 ret = smu_cmn_send_smc_msg_with_param(smu,
4136                                                                       SMU_MSG_DisallowGpo,
4137                                                                       0,
4138                                                                       NULL);
4139                         }
4140                 } else {
4141                         if (smu->smc_fw_version < 0x003a2500) {
4142                                 ret = smu_cmn_send_smc_msg_with_param(smu,
4143                                                                       SMU_MSG_SetGpoFeaturePMask,
4144                                                                       0,
4145                                                                       NULL);
4146                         } else {
4147                                 ret = smu_cmn_send_smc_msg_with_param(smu,
4148                                                                       SMU_MSG_DisallowGpo,
4149                                                                       1,
4150                                                                       NULL);
4151                         }
4152                 }
4153         }
4154
4155         return ret;
4156 }
4157
4158 static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
4159 {
4160         /*
4161          * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
4162          * onwards PMFWs.
4163          */
4164         if (smu->smc_fw_version < 0x003A2D00)
4165                 return 0;
4166
4167         return smu_cmn_send_smc_msg_with_param(smu,
4168                                                SMU_MSG_Enable2ndUSB20Port,
4169                                                smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
4170                                                1 : 0,
4171                                                NULL);
4172 }
4173
4174 static int sienna_cichlid_system_features_control(struct smu_context *smu,
4175                                                   bool en)
4176 {
4177         int ret = 0;
4178
4179         if (en) {
4180                 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
4181                 if (ret)
4182                         return ret;
4183         }
4184
4185         return smu_v11_0_system_features_control(smu, en);
4186 }
4187
4188 static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
4189                                         enum pp_mp1_state mp1_state)
4190 {
4191         int ret;
4192
4193         switch (mp1_state) {
4194         case PP_MP1_STATE_UNLOAD:
4195                 ret = smu_cmn_set_mp1_state(smu, mp1_state);
4196                 break;
4197         default:
4198                 /* Ignore others */
4199                 ret = 0;
4200         }
4201
4202         return ret;
4203 }
4204
4205 static void sienna_cichlid_stb_init(struct smu_context *smu)
4206 {
4207         struct amdgpu_device *adev = smu->adev;
4208         uint32_t reg;
4209
4210         reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START);
4211         smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);
4212
4213         /* STB is disabled */
4214         if (!smu->stb_context.enabled)
4215                 return;
4216
4217         spin_lock_init(&smu->stb_context.lock);
4218
4219         /* STB buffer size in bytes as function of FIFO depth */
4220         reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO);
4221         smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH);
4222         smu->stb_context.stb_buf_size *=  SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES;
4223
4224         dev_info(smu->adev->dev, "STB initialized to %d entries",
4225                  smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES);
4226
4227 }
4228
4229 static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu,
4230                                                             struct config_table_setting *table)
4231 {
4232         struct amdgpu_device *adev = smu->adev;
4233
4234         if (!table)
4235                 return -EINVAL;
4236
4237         table->gfxclk_average_tau = 10;
4238         table->socclk_average_tau = 10;
4239         table->fclk_average_tau = 10;
4240         table->uclk_average_tau = 10;
4241         table->gfx_activity_average_tau = 10;
4242         table->mem_activity_average_tau = 10;
4243         table->socket_power_average_tau = 100;
4244         if (amdgpu_ip_version(adev, MP1_HWIP, 0) != IP_VERSION(11, 0, 7))
4245                 table->apu_socket_power_average_tau = 100;
4246
4247         return 0;
4248 }
4249
4250 static int sienna_cichlid_set_config_table(struct smu_context *smu,
4251                                            struct config_table_setting *table)
4252 {
4253         DriverSmuConfigExternal_t driver_smu_config_table;
4254
4255         if (!table)
4256                 return -EINVAL;
4257
4258         memset(&driver_smu_config_table,
4259                0,
4260                sizeof(driver_smu_config_table));
4261         driver_smu_config_table.DriverSmuConfig.GfxclkAverageLpfTau =
4262                                 table->gfxclk_average_tau;
4263         driver_smu_config_table.DriverSmuConfig.FclkAverageLpfTau =
4264                                 table->fclk_average_tau;
4265         driver_smu_config_table.DriverSmuConfig.UclkAverageLpfTau =
4266                                 table->uclk_average_tau;
4267         driver_smu_config_table.DriverSmuConfig.GfxActivityLpfTau =
4268                                 table->gfx_activity_average_tau;
4269         driver_smu_config_table.DriverSmuConfig.UclkActivityLpfTau =
4270                                 table->mem_activity_average_tau;
4271         driver_smu_config_table.DriverSmuConfig.SocketPowerLpfTau =
4272                                 table->socket_power_average_tau;
4273
4274         return smu_cmn_update_table(smu,
4275                                     SMU_TABLE_DRIVER_SMU_CONFIG,
4276                                     0,
4277                                     (void *)&driver_smu_config_table,
4278                                     true);
4279 }
4280
4281 static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu,
4282                                               void *buf,
4283                                               uint32_t size)
4284 {
4285         uint32_t *p = buf;
4286         struct amdgpu_device *adev = smu->adev;
4287
4288         /* No need to disable interrupts for now as we don't lock it yet from ISR */
4289         spin_lock(&smu->stb_context.lock);
4290
4291         /*
4292          * Read the STB FIFO in units of 32bit since this is the accessor window
4293          * (register width) we have.
4294          */
4295         buf = ((char *) buf) + size;
4296         while ((void *)p < buf)
4297                 *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3));
4298
4299         spin_unlock(&smu->stb_context.lock);
4300
4301         return 0;
4302 }
4303
4304 static bool sienna_cichlid_is_mode2_reset_supported(struct smu_context *smu)
4305 {
4306         return true;
4307 }
4308
4309 static int sienna_cichlid_mode2_reset(struct smu_context *smu)
4310 {
4311         int ret = 0, index;
4312         struct amdgpu_device *adev = smu->adev;
4313         int timeout = 100;
4314
4315         index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
4316                                                 SMU_MSG_DriverMode2Reset);
4317
4318         mutex_lock(&smu->message_lock);
4319
4320         ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index,
4321                                                SMU_RESET_MODE_2);
4322
4323         ret = smu_cmn_wait_for_response(smu);
4324         while (ret != 0 && timeout) {
4325                 ret = smu_cmn_wait_for_response(smu);
4326                 /* Wait a bit more time for getting ACK */
4327                 if (ret != 0) {
4328                         --timeout;
4329                         usleep_range(500, 1000);
4330                         continue;
4331                 } else {
4332                         break;
4333                 }
4334         }
4335
4336         if (!timeout) {
4337                 dev_err(adev->dev,
4338                         "failed to send mode2 message \tparam: 0x%08x response %#x\n",
4339                         SMU_RESET_MODE_2, ret);
4340                 goto out;
4341         }
4342
4343         dev_info(smu->adev->dev, "restore config space...\n");
4344         /* Restore the config space saved during init */
4345         amdgpu_device_load_pci_state(adev->pdev);
4346 out:
4347         mutex_unlock(&smu->message_lock);
4348
4349         return ret;
4350 }
4351
4352 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
4353         .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
4354         .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
4355         .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
4356         .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
4357         .i2c_init = sienna_cichlid_i2c_control_init,
4358         .i2c_fini = sienna_cichlid_i2c_control_fini,
4359         .print_clk_levels = sienna_cichlid_print_clk_levels,
4360         .force_clk_levels = sienna_cichlid_force_clk_levels,
4361         .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
4362         .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
4363         .display_config_changed = sienna_cichlid_display_config_changed,
4364         .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
4365         .is_dpm_running = sienna_cichlid_is_dpm_running,
4366         .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
4367         .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
4368         .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
4369         .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
4370         .set_watermarks_table = sienna_cichlid_set_watermarks_table,
4371         .read_sensor = sienna_cichlid_read_sensor,
4372         .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
4373         .set_performance_level = smu_v11_0_set_performance_level,
4374         .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
4375         .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
4376         .get_power_limit = sienna_cichlid_get_power_limit,
4377         .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
4378         .dump_pptable = sienna_cichlid_dump_pptable,
4379         .init_microcode = smu_v11_0_init_microcode,
4380         .load_microcode = smu_v11_0_load_microcode,
4381         .fini_microcode = smu_v11_0_fini_microcode,
4382         .init_smc_tables = sienna_cichlid_init_smc_tables,
4383         .fini_smc_tables = smu_v11_0_fini_smc_tables,
4384         .init_power = smu_v11_0_init_power,
4385         .fini_power = smu_v11_0_fini_power,
4386         .check_fw_status = smu_v11_0_check_fw_status,
4387         .setup_pptable = sienna_cichlid_setup_pptable,
4388         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
4389         .check_fw_version = smu_v11_0_check_fw_version,
4390         .write_pptable = smu_cmn_write_pptable,
4391         .set_driver_table_location = smu_v11_0_set_driver_table_location,
4392         .set_tool_table_location = smu_v11_0_set_tool_table_location,
4393         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
4394         .system_features_control = sienna_cichlid_system_features_control,
4395         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
4396         .send_smc_msg = smu_cmn_send_smc_msg,
4397         .init_display_count = NULL,
4398         .set_allowed_mask = smu_v11_0_set_allowed_mask,
4399         .get_enabled_mask = smu_cmn_get_enabled_mask,
4400         .feature_is_enabled = smu_cmn_feature_is_enabled,
4401         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
4402         .notify_display_change = NULL,
4403         .set_power_limit = smu_v11_0_set_power_limit,
4404         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
4405         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
4406         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
4407         .set_min_dcef_deep_sleep = NULL,
4408         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
4409         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
4410         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
4411         .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
4412         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
4413         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
4414         .gfx_off_control = smu_v11_0_gfx_off_control,
4415         .register_irq_handler = smu_v11_0_register_irq_handler,
4416         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
4417         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
4418         .baco_is_support = smu_v11_0_baco_is_support,
4419         .baco_get_state = smu_v11_0_baco_get_state,
4420         .baco_set_state = smu_v11_0_baco_set_state,
4421         .baco_enter = sienna_cichlid_baco_enter,
4422         .baco_exit = sienna_cichlid_baco_exit,
4423         .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
4424         .mode1_reset = smu_v11_0_mode1_reset,
4425         .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
4426         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
4427         .set_default_od_settings = sienna_cichlid_set_default_od_settings,
4428         .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
4429         .restore_user_od_settings = sienna_cichlid_restore_user_od_settings,
4430         .run_btc = sienna_cichlid_run_btc,
4431         .set_power_source = smu_v11_0_set_power_source,
4432         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
4433         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
4434         .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
4435         .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
4436         .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
4437         .deep_sleep_control = smu_v11_0_deep_sleep_control,
4438         .get_fan_parameters = sienna_cichlid_get_fan_parameters,
4439         .interrupt_work = smu_v11_0_interrupt_work,
4440         .gpo_control = sienna_cichlid_gpo_control,
4441         .set_mp1_state = sienna_cichlid_set_mp1_state,
4442         .stb_collect_info = sienna_cichlid_stb_get_data_direct,
4443         .get_ecc_info = sienna_cichlid_get_ecc_info,
4444         .get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings,
4445         .set_config_table = sienna_cichlid_set_config_table,
4446         .get_unique_id = sienna_cichlid_get_unique_id,
4447         .mode2_reset_is_support = sienna_cichlid_is_mode2_reset_supported,
4448         .mode2_reset = sienna_cichlid_mode2_reset,
4449 };
4450
4451 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
4452 {
4453         smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
4454         smu->message_map = sienna_cichlid_message_map;
4455         smu->clock_map = sienna_cichlid_clk_map;
4456         smu->feature_map = sienna_cichlid_feature_mask_map;
4457         smu->table_map = sienna_cichlid_table_map;
4458         smu->pwr_src_map = sienna_cichlid_pwr_src_map;
4459         smu->workload_map = sienna_cichlid_workload_map;
4460         smu_v11_0_set_smu_mailbox_registers(smu);
4461 }