drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "pp_debug.h"
  24 #include <linux/delay.h>
  25 #include <linux/fb.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28 #include <linux/slab.h>
  29 #include <asm/div64.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include "ppatomctrl.h"
  32 #include "atombios.h"
  33 #include "pptable_v1_0.h"
  34 #include "pppcielanes.h"
  35 #include "amd_pcie_helpers.h"
  36 #include "hardwaremanager.h"
  37 #include "process_pptables_v1_0.h"
  38 #include "cgs_common.h"
  39
  40 #include "smu7_common.h"
  41
  42 #include "hwmgr.h"
  43 #include "smu7_hwmgr.h"
  44 #include "smu_ucode_xfer_vi.h"
  45 #include "smu7_powertune.h"
  46 #include "smu7_dyn_defaults.h"
  47 #include "smu7_thermal.h"
  48 #include "smu7_clockpowergating.h"
  49 #include "processpptables.h"
  50 #include "pp_thermal.h"
  51 #include "smu7_baco.h"
  52
  53 #include "ivsrcid/ivsrcid_vislands30.h"
  54
  55 #define MC_CG_ARB_FREQ_F0           0x0a
  56 #define MC_CG_ARB_FREQ_F1           0x0b
  57 #define MC_CG_ARB_FREQ_F2           0x0c
  58 #define MC_CG_ARB_FREQ_F3           0x0d
  59
  60 #define MC_CG_SEQ_DRAMCONF_S0       0x05
  61 #define MC_CG_SEQ_DRAMCONF_S1       0x06
  62 #define MC_CG_SEQ_YCLK_SUSPEND      0x04
  63 #define MC_CG_SEQ_YCLK_RESUME       0x0a
  64
  65 #define SMC_CG_IND_START            0xc0030000
  66 #define SMC_CG_IND_END              0xc0040000
  67
  68 #define MEM_FREQ_LOW_LATENCY        25000
  69 #define MEM_FREQ_HIGH_LATENCY       80000
  70
  71 #define MEM_LATENCY_HIGH            45
  72 #define MEM_LATENCY_LOW             35
  73 #define MEM_LATENCY_ERR             0xFFFF
  74
  75 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  76 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
  77 #define MC_SEQ_MISC0_GDDR5_VALUE 5
  78
  79 #define PCIE_BUS_CLK                10000
  80 #define TCLK                        (PCIE_BUS_CLK / 10)
  81
  82 static struct profile_mode_setting smu7_profiling[7] =
  83                                         {{0, 0, 0, 0, 0, 0, 0, 0},
  84                                          {1, 0, 100, 30, 1, 0, 100, 10},
  85                                          {1, 10, 0, 30, 0, 0, 0, 0},
  86                                          {0, 0, 0, 0, 1, 10, 16, 31},
  87                                          {1, 0, 11, 50, 1, 0, 100, 10},
  88                                          {1, 0, 5, 30, 0, 0, 0, 0},
  89                                          {0, 0, 0, 0, 0, 0, 0, 0},
  90                                         };
  91
  92 #define PPSMC_MSG_SetVBITimeout_VEGAM    ((uint16_t) 0x310)
  93
  94 #define ixPWR_SVI2_PLANE1_LOAD                     0xC0200280
  95 #define PWR_SVI2_PLANE1_LOAD__PSI1_MASK                    0x00000020L
  96 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN_MASK                 0x00000040L
  97 #define PWR_SVI2_PLANE1_LOAD__PSI1__SHIFT                  0x00000005
  98 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN__SHIFT               0x00000006
  99
 100 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
 101 enum DPM_EVENT_SRC {
 102         DPM_EVENT_SRC_ANALOG = 0,
 103         DPM_EVENT_SRC_EXTERNAL = 1,
 104         DPM_EVENT_SRC_DIGITAL = 2,
 105         DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
 106         DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
 107 };
 108
 109 static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
 110 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
 111                 enum pp_clock_type type, uint32_t mask);
 112
 113 static struct smu7_power_state *cast_phw_smu7_power_state(
 114                                   struct pp_hw_power_state *hw_ps)
 115 {
 116         PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
 117                                 "Invalid Powerstate Type!",
 118                                  return NULL);
 119
 120         return (struct smu7_power_state *)hw_ps;
 121 }
 122
 123 static const struct smu7_power_state *cast_const_phw_smu7_power_state(
 124                                  const struct pp_hw_power_state *hw_ps)
 125 {
 126         PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
 127                                 "Invalid Powerstate Type!",
 128                                  return NULL);
 129
 130         return (const struct smu7_power_state *)hw_ps;
 131 }
 132
 133 /**
 134  * Find the MC microcode version and store it in the HwMgr struct
 135  *
 136  * @param    hwmgr  the address of the powerplay hardware manager.
 137  * @return   always 0
 138  */
 139 static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr)
 140 {
 141         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 142
 143         hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
 144
 145         return 0;
 146 }
 147
 148 static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
 149 {
 150         uint32_t speedCntl = 0;
 151
 152         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 153         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
 154                         ixPCIE_LC_SPEED_CNTL);
 155         return((uint16_t)PHM_GET_FIELD(speedCntl,
 156                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
 157 }
 158
 159 static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
 160 {
 161         uint32_t link_width;
 162
 163         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 164         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
 165                         PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
 166
 167         PP_ASSERT_WITH_CODE((7 >= link_width),
 168                         "Invalid PCIe lane width!", return 0);
 169
 170         return decode_pcie_lane_width(link_width);
 171 }
 172
 173 /**
 174 * Enable voltage control
 175 *
 176 * @param    pHwMgr  the address of the powerplay hardware manager.
 177 * @return   always PP_Result_OK
 178 */
 179 static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
 180 {
 181         if (hwmgr->chip_id == CHIP_VEGAM) {
 182                 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
 183                                 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI1, 0);
 184                 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
 185                                 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI0_EN, 0);
 186         }
 187
 188         if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK)
 189                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Enable, NULL);
 190
 191         return 0;
 192 }
 193
 194 /**
 195 * Checks if we want to support voltage control
 196 *
 197 * @param    hwmgr  the address of the powerplay hardware manager.
 198 */
 199 static bool smu7_voltage_control(const struct pp_hwmgr *hwmgr)
 200 {
 201         const struct smu7_hwmgr *data =
 202                         (const struct smu7_hwmgr *)(hwmgr->backend);
 203
 204         return (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control);
 205 }
 206
 207 /**
 208 * Enable voltage control
 209 *
 210 * @param    hwmgr  the address of the powerplay hardware manager.
 211 * @return   always 0
 212 */
 213 static int smu7_enable_voltage_control(struct pp_hwmgr *hwmgr)
 214 {
 215         /* enable voltage control */
 216         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 217                         GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
 218
 219         return 0;
 220 }
 221
 222 static int phm_get_svi2_voltage_table_v0(pp_atomctrl_voltage_table *voltage_table,
 223                 struct phm_clock_voltage_dependency_table *voltage_dependency_table
 224                 )
 225 {
 226         uint32_t i;
 227
 228         PP_ASSERT_WITH_CODE((NULL != voltage_table),
 229                         "Voltage Dependency Table empty.", return -EINVAL;);
 230
 231         voltage_table->mask_low = 0;
 232         voltage_table->phase_delay = 0;
 233         voltage_table->count = voltage_dependency_table->count;
 234
 235         for (i = 0; i < voltage_dependency_table->count; i++) {
 236                 voltage_table->entries[i].value =
 237                         voltage_dependency_table->entries[i].v;
 238                 voltage_table->entries[i].smio_low = 0;
 239         }
 240
 241         return 0;
 242 }
 243
 244
 245 /**
 246 * Create Voltage Tables.
 247 *
 248 * @param    hwmgr  the address of the powerplay hardware manager.
 249 * @return   always 0
 250 */
 251 static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr)
 252 {
 253         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 254         struct phm_ppt_v1_information *table_info =
 255                         (struct phm_ppt_v1_information *)hwmgr->pptable;
 256         int result = 0;
 257         uint32_t tmp;
 258
 259         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 260                 result = atomctrl_get_voltage_table_v3(hwmgr,
 261                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
 262                                 &(data->mvdd_voltage_table));
 263                 PP_ASSERT_WITH_CODE((0 == result),
 264                                 "Failed to retrieve MVDD table.",
 265                                 return result);
 266         } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
 267                 if (hwmgr->pp_table_version == PP_TABLE_V1)
 268                         result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
 269                                         table_info->vdd_dep_on_mclk);
 270                 else if (hwmgr->pp_table_version == PP_TABLE_V0)
 271                         result = phm_get_svi2_voltage_table_v0(&(data->mvdd_voltage_table),
 272                                         hwmgr->dyn_state.mvdd_dependency_on_mclk);
 273
 274                 PP_ASSERT_WITH_CODE((0 == result),
 275                                 "Failed to retrieve SVI2 MVDD table from dependency table.",
 276                                 return result;);
 277         }
 278
 279         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 280                 result = atomctrl_get_voltage_table_v3(hwmgr,
 281                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
 282                                 &(data->vddci_voltage_table));
 283                 PP_ASSERT_WITH_CODE((0 == result),
 284                                 "Failed to retrieve VDDCI table.",
 285                                 return result);
 286         } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
 287                 if (hwmgr->pp_table_version == PP_TABLE_V1)
 288                         result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
 289                                         table_info->vdd_dep_on_mclk);
 290                 else if (hwmgr->pp_table_version == PP_TABLE_V0)
 291                         result = phm_get_svi2_voltage_table_v0(&(data->vddci_voltage_table),
 292                                         hwmgr->dyn_state.vddci_dependency_on_mclk);
 293                 PP_ASSERT_WITH_CODE((0 == result),
 294                                 "Failed to retrieve SVI2 VDDCI table from dependency table.",
 295                                 return result);
 296         }
 297
 298         if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
 299                 /* VDDGFX has only SVI2 voltage control */
 300                 result = phm_get_svi2_vdd_voltage_table(&(data->vddgfx_voltage_table),
 301                                         table_info->vddgfx_lookup_table);
 302                 PP_ASSERT_WITH_CODE((0 == result),
 303                         "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;);
 304         }
 305
 306
 307         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
 308                 result = atomctrl_get_voltage_table_v3(hwmgr,
 309                                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT,
 310                                         &data->vddc_voltage_table);
 311                 PP_ASSERT_WITH_CODE((0 == result),
 312                         "Failed to retrieve VDDC table.", return result;);
 313         } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
 314
 315                 if (hwmgr->pp_table_version == PP_TABLE_V0)
 316                         result = phm_get_svi2_voltage_table_v0(&data->vddc_voltage_table,
 317                                         hwmgr->dyn_state.vddc_dependency_on_mclk);
 318                 else if (hwmgr->pp_table_version == PP_TABLE_V1)
 319                         result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
 320                                 table_info->vddc_lookup_table);
 321
 322                 PP_ASSERT_WITH_CODE((0 == result),
 323                         "Failed to retrieve SVI2 VDDC table from dependency table.", return result;);
 324         }
 325
 326         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC);
 327         PP_ASSERT_WITH_CODE(
 328                         (data->vddc_voltage_table.count <= tmp),
 329                 "Too many voltage values for VDDC. Trimming to fit state table.",
 330                         phm_trim_voltage_table_to_fit_state_table(tmp,
 331                                                 &(data->vddc_voltage_table)));
 332
 333         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
 334         PP_ASSERT_WITH_CODE(
 335                         (data->vddgfx_voltage_table.count <= tmp),
 336                 "Too many voltage values for VDDC. Trimming to fit state table.",
 337                         phm_trim_voltage_table_to_fit_state_table(tmp,
 338                                                 &(data->vddgfx_voltage_table)));
 339
 340         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI);
 341         PP_ASSERT_WITH_CODE(
 342                         (data->vddci_voltage_table.count <= tmp),
 343                 "Too many voltage values for VDDCI. Trimming to fit state table.",
 344                         phm_trim_voltage_table_to_fit_state_table(tmp,
 345                                         &(data->vddci_voltage_table)));
 346
 347         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD);
 348         PP_ASSERT_WITH_CODE(
 349                         (data->mvdd_voltage_table.count <= tmp),
 350                 "Too many voltage values for MVDD. Trimming to fit state table.",
 351                         phm_trim_voltage_table_to_fit_state_table(tmp,
 352                                                 &(data->mvdd_voltage_table)));
 353
 354         return 0;
 355 }
 356
 357 /**
 358 * Programs static screed detection parameters
 359 *
 360 * @param    hwmgr  the address of the powerplay hardware manager.
 361 * @return   always 0
 362 */
 363 static int smu7_program_static_screen_threshold_parameters(
 364                                                         struct pp_hwmgr *hwmgr)
 365 {
 366         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 367
 368         /* Set static screen threshold unit */
 369         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 370                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
 371                         data->static_screen_threshold_unit);
 372         /* Set static screen threshold */
 373         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 374                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
 375                         data->static_screen_threshold);
 376
 377         return 0;
 378 }
 379
 380 /**
 381 * Setup display gap for glitch free memory clock switching.
 382 *
 383 * @param    hwmgr  the address of the powerplay hardware manager.
 384 * @return   always  0
 385 */
 386 static int smu7_enable_display_gap(struct pp_hwmgr *hwmgr)
 387 {
 388         uint32_t display_gap =
 389                         cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 390                                         ixCG_DISPLAY_GAP_CNTL);
 391
 392         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 393                         DISP_GAP, DISPLAY_GAP_IGNORE);
 394
 395         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 396                         DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
 397
 398         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 399                         ixCG_DISPLAY_GAP_CNTL, display_gap);
 400
 401         return 0;
 402 }
 403
 404 /**
 405 * Programs activity state transition voting clients
 406 *
 407 * @param    hwmgr  the address of the powerplay hardware manager.
 408 * @return   always  0
 409 */
 410 static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr)
 411 {
 412         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 413         int i;
 414
 415         /* Clear reset for voting clients before enabling DPM */
 416         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 417                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
 418         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 419                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
 420
 421         for (i = 0; i < 8; i++)
 422                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 423                                         ixCG_FREQ_TRAN_VOTING_0 + i * 4,
 424                                         data->voting_rights_clients[i]);
 425         return 0;
 426 }
 427
 428 static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr)
 429 {
 430         int i;
 431
 432         /* Reset voting clients before disabling DPM */
 433         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 434                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
 435         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 436                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
 437
 438         for (i = 0; i < 8; i++)
 439                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 440                                 ixCG_FREQ_TRAN_VOTING_0 + i * 4, 0);
 441
 442         return 0;
 443 }
 444
 445 /* Copy one arb setting to another and then switch the active set.
 446  * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
 447  */
 448 static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
 449                 uint32_t arb_src, uint32_t arb_dest)
 450 {
 451         uint32_t mc_arb_dram_timing;
 452         uint32_t mc_arb_dram_timing2;
 453         uint32_t burst_time;
 454         uint32_t mc_cg_config;
 455
 456         switch (arb_src) {
 457         case MC_CG_ARB_FREQ_F0:
 458                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
 459                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
 460                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
 461                 break;
 462         case MC_CG_ARB_FREQ_F1:
 463                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
 464                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
 465                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
 466                 break;
 467         default:
 468                 return -EINVAL;
 469         }
 470
 471         switch (arb_dest) {
 472         case MC_CG_ARB_FREQ_F0:
 473                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
 474                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
 475                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
 476                 break;
 477         case MC_CG_ARB_FREQ_F1:
 478                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
 479                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
 480                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
 481                 break;
 482         default:
 483                 return -EINVAL;
 484         }
 485
 486         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
 487         mc_cg_config |= 0x0000000F;
 488         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
 489         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
 490
 491         return 0;
 492 }
 493
 494 static int smu7_reset_to_default(struct pp_hwmgr *hwmgr)
 495 {
 496         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ResetToDefaults, NULL);
 497 }
 498
 499 /**
 500 * Initial switch from ARB F0->F1
 501 *
 502 * @param    hwmgr  the address of the powerplay hardware manager.
 503 * @return   always 0
 504 * This function is to be called from the SetPowerState table.
 505 */
 506 static int smu7_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
 507 {
 508         return smu7_copy_and_switch_arb_sets(hwmgr,
 509                         MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
 510 }
 511
 512 static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
 513 {
 514         uint32_t tmp;
 515
 516         tmp = (cgs_read_ind_register(hwmgr->device,
 517                         CGS_IND_REG__SMC, ixSMC_SCRATCH9) &
 518                         0x0000ff00) >> 8;
 519
 520         if (tmp == MC_CG_ARB_FREQ_F0)
 521                 return 0;
 522
 523         return smu7_copy_and_switch_arb_sets(hwmgr,
 524                         tmp, MC_CG_ARB_FREQ_F0);
 525 }
 526
 527 static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
 528 {
 529         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 530
 531         struct phm_ppt_v1_information *table_info =
 532                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 533         struct phm_ppt_v1_pcie_table *pcie_table = NULL;
 534
 535         uint32_t i, max_entry;
 536         uint32_t tmp;
 537
 538         PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
 539                         data->use_pcie_power_saving_levels), "No pcie performance levels!",
 540                         return -EINVAL);
 541
 542         if (table_info != NULL)
 543                 pcie_table = table_info->pcie_table;
 544
 545         if (data->use_pcie_performance_levels &&
 546                         !data->use_pcie_power_saving_levels) {
 547                 data->pcie_gen_power_saving = data->pcie_gen_performance;
 548                 data->pcie_lane_power_saving = data->pcie_lane_performance;
 549         } else if (!data->use_pcie_performance_levels &&
 550                         data->use_pcie_power_saving_levels) {
 551                 data->pcie_gen_performance = data->pcie_gen_power_saving;
 552                 data->pcie_lane_performance = data->pcie_lane_power_saving;
 553         }
 554         tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_LINK);
 555         phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
 556                                         tmp,
 557                                         MAX_REGULAR_DPM_NUMBER);
 558
 559         if (pcie_table != NULL) {
 560                 /* max_entry is used to make sure we reserve one PCIE level
 561                  * for boot level (fix for A+A PSPP issue).
 562                  * If PCIE table from PPTable have ULV entry + 8 entries,
 563                  * then ignore the last entry.*/
 564                 max_entry = (tmp < pcie_table->count) ? tmp : pcie_table->count;
 565                 for (i = 1; i < max_entry; i++) {
 566                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
 567                                         get_pcie_gen_support(data->pcie_gen_cap,
 568                                                         pcie_table->entries[i].gen_speed),
 569                                         get_pcie_lane_support(data->pcie_lane_cap,
 570                                                         pcie_table->entries[i].lane_width));
 571                 }
 572                 data->dpm_table.pcie_speed_table.count = max_entry - 1;
 573                 smum_update_smc_table(hwmgr, SMU_BIF_TABLE);
 574         } else {
 575                 /* Hardcode Pcie Table */
 576                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
 577                                 get_pcie_gen_support(data->pcie_gen_cap,
 578                                                 PP_Min_PCIEGen),
 579                                 get_pcie_lane_support(data->pcie_lane_cap,
 580                                                 PP_Max_PCIELane));
 581                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
 582                                 get_pcie_gen_support(data->pcie_gen_cap,
 583                                                 PP_Min_PCIEGen),
 584                                 get_pcie_lane_support(data->pcie_lane_cap,
 585                                                 PP_Max_PCIELane));
 586                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
 587                                 get_pcie_gen_support(data->pcie_gen_cap,
 588                                                 PP_Max_PCIEGen),
 589                                 get_pcie_lane_support(data->pcie_lane_cap,
 590                                                 PP_Max_PCIELane));
 591                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
 592                                 get_pcie_gen_support(data->pcie_gen_cap,
 593                                                 PP_Max_PCIEGen),
 594                                 get_pcie_lane_support(data->pcie_lane_cap,
 595                                                 PP_Max_PCIELane));
 596                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
 597                                 get_pcie_gen_support(data->pcie_gen_cap,
 598                                                 PP_Max_PCIEGen),
 599                                 get_pcie_lane_support(data->pcie_lane_cap,
 600                                                 PP_Max_PCIELane));
 601                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
 602                                 get_pcie_gen_support(data->pcie_gen_cap,
 603                                                 PP_Max_PCIEGen),
 604                                 get_pcie_lane_support(data->pcie_lane_cap,
 605                                                 PP_Max_PCIELane));
 606
 607                 data->dpm_table.pcie_speed_table.count = 6;
 608         }
 609         /* Populate last level for boot PCIE level, but do not increment count. */
 610         if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
 611                 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++)
 612                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i,
 613                                 get_pcie_gen_support(data->pcie_gen_cap,
 614                                                 PP_Max_PCIEGen),
 615                                 data->vbios_boot_state.pcie_lane_bootup_value);
 616         } else {
 617                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
 618                         data->dpm_table.pcie_speed_table.count,
 619                         get_pcie_gen_support(data->pcie_gen_cap,
 620                                         PP_Min_PCIEGen),
 621                         get_pcie_lane_support(data->pcie_lane_cap,
 622                                         PP_Max_PCIELane));
 623         }
 624         return 0;
 625 }
 626
 627 static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr)
 628 {
 629         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 630
 631         memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table));
 632
 633         phm_reset_single_dpm_table(
 634                         &data->dpm_table.sclk_table,
 635                                 smum_get_mac_definition(hwmgr,
 636                                         SMU_MAX_LEVELS_GRAPHICS),
 637                                         MAX_REGULAR_DPM_NUMBER);
 638         phm_reset_single_dpm_table(
 639                         &data->dpm_table.mclk_table,
 640                         smum_get_mac_definition(hwmgr,
 641                                 SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER);
 642
 643         phm_reset_single_dpm_table(
 644                         &data->dpm_table.vddc_table,
 645                                 smum_get_mac_definition(hwmgr,
 646                                         SMU_MAX_LEVELS_VDDC),
 647                                         MAX_REGULAR_DPM_NUMBER);
 648         phm_reset_single_dpm_table(
 649                         &data->dpm_table.vddci_table,
 650                         smum_get_mac_definition(hwmgr,
 651                                 SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER);
 652
 653         phm_reset_single_dpm_table(
 654                         &data->dpm_table.mvdd_table,
 655                                 smum_get_mac_definition(hwmgr,
 656                                         SMU_MAX_LEVELS_MVDD),
 657                                         MAX_REGULAR_DPM_NUMBER);
 658         return 0;
 659 }
 660 /*
 661  * This function is to initialize all DPM state tables
 662  * for SMU7 based on the dependency table.
 663  * Dynamic state patching function will then trim these
 664  * state tables to the allowed range based
 665  * on the power policy or external client requests,
 666  * such as UVD request, etc.
 667  */
 668
 669 static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr)
 670 {
 671         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 672         struct phm_clock_voltage_dependency_table *allowed_vdd_sclk_table =
 673                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 674         struct phm_clock_voltage_dependency_table *allowed_vdd_mclk_table =
 675                 hwmgr->dyn_state.vddc_dependency_on_mclk;
 676         struct phm_cac_leakage_table *std_voltage_table =
 677                 hwmgr->dyn_state.cac_leakage_table;
 678         uint32_t i;
 679
 680         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
 681                 "SCLK dependency table is missing. This table is mandatory", return -EINVAL);
 682         PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,
 683                 "SCLK dependency table has to have is missing. This table is mandatory", return -EINVAL);
 684
 685         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
 686                 "MCLK dependency table is missing. This table is mandatory", return -EINVAL);
 687         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,
 688                 "VMCLK dependency table has to have is missing. This table is mandatory", return -EINVAL);
 689
 690
 691         /* Initialize Sclk DPM table based on allow Sclk values*/
 692         data->dpm_table.sclk_table.count = 0;
 693
 694         for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
 695                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
 696                                 allowed_vdd_sclk_table->entries[i].clk) {
 697                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
 698                                 allowed_vdd_sclk_table->entries[i].clk;
 699                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0;
 700                         data->dpm_table.sclk_table.count++;
 701                 }
 702         }
 703
 704         PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
 705                 "MCLK dependency table is missing. This table is mandatory", return -EINVAL);
 706         /* Initialize Mclk DPM table based on allow Mclk values */
 707         data->dpm_table.mclk_table.count = 0;
 708         for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
 709                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value !=
 710                         allowed_vdd_mclk_table->entries[i].clk) {
 711                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
 712                                 allowed_vdd_mclk_table->entries[i].clk;
 713                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0;
 714                         data->dpm_table.mclk_table.count++;
 715                 }
 716         }
 717
 718         /* Initialize Vddc DPM table based on allow Vddc values.  And populate corresponding std values. */
 719         for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
 720                 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
 721                 data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage;
 722                 /* param1 is for corresponding std voltage */
 723                 data->dpm_table.vddc_table.dpm_levels[i].enabled = true;
 724         }
 725
 726         data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
 727         allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
 728
 729         if (NULL != allowed_vdd_mclk_table) {
 730                 /* Initialize Vddci DPM table based on allow Mclk values */
 731                 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
 732                         data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
 733                         data->dpm_table.vddci_table.dpm_levels[i].enabled = true;
 734                 }
 735                 data->dpm_table.vddci_table.count = allowed_vdd_mclk_table->count;
 736         }
 737
 738         allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk;
 739
 740         if (NULL != allowed_vdd_mclk_table) {
 741                 /*
 742                  * Initialize MVDD DPM table based on allow Mclk
 743                  * values
 744                  */
 745                 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
 746                         data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
 747                         data->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
 748                 }
 749                 data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
 750         }
 751
 752         return 0;
 753 }
 754
 755 static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr)
 756 {
 757         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 758         struct phm_ppt_v1_information *table_info =
 759                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 760         uint32_t i;
 761
 762         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
 763         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
 764
 765         if (table_info == NULL)
 766                 return -EINVAL;
 767
 768         dep_sclk_table = table_info->vdd_dep_on_sclk;
 769         dep_mclk_table = table_info->vdd_dep_on_mclk;
 770
 771         PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
 772                         "SCLK dependency table is missing.",
 773                         return -EINVAL);
 774         PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
 775                         "SCLK dependency table count is 0.",
 776                         return -EINVAL);
 777
 778         PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
 779                         "MCLK dependency table is missing.",
 780                         return -EINVAL);
 781         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
 782                         "MCLK dependency table count is 0",
 783                         return -EINVAL);
 784
 785         /* Initialize Sclk DPM table based on allow Sclk values */
 786         data->dpm_table.sclk_table.count = 0;
 787         for (i = 0; i < dep_sclk_table->count; i++) {
 788                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
 789                                                 dep_sclk_table->entries[i].clk) {
 790
 791                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
 792                                         dep_sclk_table->entries[i].clk;
 793
 794                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
 795                                         (i == 0) ? true : false;
 796                         data->dpm_table.sclk_table.count++;
 797                 }
 798         }
 799         if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0)
 800                 hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk;
 801         /* Initialize Mclk DPM table based on allow Mclk values */
 802         data->dpm_table.mclk_table.count = 0;
 803         for (i = 0; i < dep_mclk_table->count; i++) {
 804                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
 805                                 [data->dpm_table.mclk_table.count - 1].value !=
 806                                                 dep_mclk_table->entries[i].clk) {
 807                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
 808                                                         dep_mclk_table->entries[i].clk;
 809                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
 810                                                         (i == 0) ? true : false;
 811                         data->dpm_table.mclk_table.count++;
 812                 }
 813         }
 814
 815         if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)
 816                 hwmgr->platform_descriptor.overdriveLimit.memoryClock = dep_mclk_table->entries[i-1].clk;
 817         return 0;
 818 }
 819
 820 static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
 821 {
 822         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 823         struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
 824         struct phm_ppt_v1_information *table_info =
 825                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 826         uint32_t i;
 827
 828         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
 829         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
 830         struct phm_odn_performance_level *entries;
 831
 832         if (table_info == NULL)
 833                 return -EINVAL;
 834
 835         dep_sclk_table = table_info->vdd_dep_on_sclk;
 836         dep_mclk_table = table_info->vdd_dep_on_mclk;
 837
 838         odn_table->odn_core_clock_dpm_levels.num_of_pl =
 839                                                 data->golden_dpm_table.sclk_table.count;
 840         entries = odn_table->odn_core_clock_dpm_levels.entries;
 841         for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) {
 842                 entries[i].clock = data->golden_dpm_table.sclk_table.dpm_levels[i].value;
 843                 entries[i].enabled = true;
 844                 entries[i].vddc = dep_sclk_table->entries[i].vddc;
 845         }
 846
 847         smu_get_voltage_dependency_table_ppt_v1(dep_sclk_table,
 848                 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk));
 849
 850         odn_table->odn_memory_clock_dpm_levels.num_of_pl =
 851                                                 data->golden_dpm_table.mclk_table.count;
 852         entries = odn_table->odn_memory_clock_dpm_levels.entries;
 853         for (i=0; i<data->golden_dpm_table.mclk_table.count; i++) {
 854                 entries[i].clock = data->golden_dpm_table.mclk_table.dpm_levels[i].value;
 855                 entries[i].enabled = true;
 856                 entries[i].vddc = dep_mclk_table->entries[i].vddc;
 857         }
 858
 859         smu_get_voltage_dependency_table_ppt_v1(dep_mclk_table,
 860                 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk));
 861
 862         return 0;
 863 }
 864
 865 static void smu7_setup_voltage_range_from_vbios(struct pp_hwmgr *hwmgr)
 866 {
 867         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 868         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
 869         struct phm_ppt_v1_information *table_info =
 870                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 871         uint32_t min_vddc = 0;
 872         uint32_t max_vddc = 0;
 873
 874         if (!table_info)
 875                 return;
 876
 877         dep_sclk_table = table_info->vdd_dep_on_sclk;
 878
 879         atomctrl_get_voltage_range(hwmgr, &max_vddc, &min_vddc);
 880
 881         if (min_vddc == 0 || min_vddc > 2000
 882                 || min_vddc > dep_sclk_table->entries[0].vddc)
 883                 min_vddc = dep_sclk_table->entries[0].vddc;
 884
 885         if (max_vddc == 0 || max_vddc > 2000
 886                 || max_vddc < dep_sclk_table->entries[dep_sclk_table->count-1].vddc)
 887                 max_vddc = dep_sclk_table->entries[dep_sclk_table->count-1].vddc;
 888
 889         data->odn_dpm_table.min_vddc = min_vddc;
 890         data->odn_dpm_table.max_vddc = max_vddc;
 891 }
 892
 893 static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
 894 {
 895         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 896         struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
 897         struct phm_ppt_v1_information *table_info =
 898                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 899         uint32_t i;
 900
 901         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
 902         struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
 903
 904         if (table_info == NULL)
 905                 return;
 906
 907         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
 908                 if (odn_table->odn_core_clock_dpm_levels.entries[i].clock !=
 909                                         data->dpm_table.sclk_table.dpm_levels[i].value) {
 910                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
 911                         break;
 912                 }
 913         }
 914
 915         for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
 916                 if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock !=
 917                                         data->dpm_table.mclk_table.dpm_levels[i].value) {
 918                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
 919                         break;
 920                 }
 921         }
 922
 923         dep_table = table_info->vdd_dep_on_mclk;
 924         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk);
 925
 926         for (i = 0; i < dep_table->count; i++) {
 927                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
 928                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK;
 929                         return;
 930                 }
 931         }
 932
 933         dep_table = table_info->vdd_dep_on_sclk;
 934         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk);
 935         for (i = 0; i < dep_table->count; i++) {
 936                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
 937                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK;
 938                         return;
 939                 }
 940         }
 941         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
 942                 data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
 943                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
 944         }
 945 }
 946
 947 static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 948 {
 949         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 950
 951         smu7_reset_dpm_tables(hwmgr);
 952
 953         if (hwmgr->pp_table_version == PP_TABLE_V1)
 954                 smu7_setup_dpm_tables_v1(hwmgr);
 955         else if (hwmgr->pp_table_version == PP_TABLE_V0)
 956                 smu7_setup_dpm_tables_v0(hwmgr);
 957
 958         smu7_setup_default_pcie_table(hwmgr);
 959
 960         /* save a copy of the default DPM table */
 961         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
 962                         sizeof(struct smu7_dpm_table));
 963
 964         /* initialize ODN table */
 965         if (hwmgr->od_enabled) {
 966                 if (data->odn_dpm_table.max_vddc) {
 967                         smu7_check_dpm_table_updated(hwmgr);
 968                 } else {
 969                         smu7_setup_voltage_range_from_vbios(hwmgr);
 970                         smu7_odn_initial_default_setting(hwmgr);
 971                 }
 972         }
 973         return 0;
 974 }
 975
 976 static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
 977 {
 978
 979         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 980                         PHM_PlatformCaps_RegulatorHot))
 981                 return smum_send_msg_to_smc(hwmgr,
 982                                 PPSMC_MSG_EnableVRHotGPIOInterrupt,
 983                                 NULL);
 984
 985         return 0;
 986 }
 987
 988 static int smu7_enable_sclk_control(struct pp_hwmgr *hwmgr)
 989 {
 990         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
 991                         SCLK_PWRMGT_OFF, 0);
 992         return 0;
 993 }
 994
 995 static int smu7_enable_ulv(struct pp_hwmgr *hwmgr)
 996 {
 997         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 998
 999         if (data->ulv_supported)
1000                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableULV, NULL);
1001
1002         return 0;
1003 }
1004
1005 static int smu7_disable_ulv(struct pp_hwmgr *hwmgr)
1006 {
1007         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1008
1009         if (data->ulv_supported)
1010                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableULV, NULL);
1011
1012         return 0;
1013 }
1014
1015 static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
1016 {
1017         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1018                         PHM_PlatformCaps_SclkDeepSleep)) {
1019                 if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_ON, NULL))
1020                         PP_ASSERT_WITH_CODE(false,
1021                                         "Attempt to enable Master Deep Sleep switch failed!",
1022                                         return -EINVAL);
1023         } else {
1024                 if (smum_send_msg_to_smc(hwmgr,
1025                                 PPSMC_MSG_MASTER_DeepSleep_OFF,
1026                                 NULL)) {
1027                         PP_ASSERT_WITH_CODE(false,
1028                                         "Attempt to disable Master Deep Sleep switch failed!",
1029                                         return -EINVAL);
1030                 }
1031         }
1032
1033         return 0;
1034 }
1035
1036 static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
1037 {
1038         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1039                         PHM_PlatformCaps_SclkDeepSleep)) {
1040                 if (smum_send_msg_to_smc(hwmgr,
1041                                 PPSMC_MSG_MASTER_DeepSleep_OFF,
1042                                 NULL)) {
1043                         PP_ASSERT_WITH_CODE(false,
1044                                         "Attempt to disable Master Deep Sleep switch failed!",
1045                                         return -EINVAL);
1046                 }
1047         }
1048
1049         return 0;
1050 }
1051
1052 static int smu7_disable_sclk_vce_handshake(struct pp_hwmgr *hwmgr)
1053 {
1054         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1055         uint32_t soft_register_value = 0;
1056         uint32_t handshake_disables_offset = data->soft_regs_start
1057                                 + smum_get_offsetof(hwmgr,
1058                                         SMU_SoftRegisters, HandshakeDisables);
1059
1060         soft_register_value = cgs_read_ind_register(hwmgr->device,
1061                                 CGS_IND_REG__SMC, handshake_disables_offset);
1062         soft_register_value |= SMU7_VCE_SCLK_HANDSHAKE_DISABLE;
1063         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1064                         handshake_disables_offset, soft_register_value);
1065         return 0;
1066 }
1067
1068 static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr)
1069 {
1070         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1071         uint32_t soft_register_value = 0;
1072         uint32_t handshake_disables_offset = data->soft_regs_start
1073                                 + smum_get_offsetof(hwmgr,
1074                                         SMU_SoftRegisters, HandshakeDisables);
1075
1076         soft_register_value = cgs_read_ind_register(hwmgr->device,
1077                                 CGS_IND_REG__SMC, handshake_disables_offset);
1078         soft_register_value |= smum_get_mac_definition(hwmgr,
1079                                         SMU_UVD_MCLK_HANDSHAKE_DISABLE);
1080         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1081                         handshake_disables_offset, soft_register_value);
1082         return 0;
1083 }
1084
1085 static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1086 {
1087         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1088
1089         /* enable SCLK dpm */
1090         if (!data->sclk_dpm_key_disabled) {
1091                 if (hwmgr->chip_id == CHIP_VEGAM)
1092                         smu7_disable_sclk_vce_handshake(hwmgr);
1093
1094                 PP_ASSERT_WITH_CODE(
1095                 (0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable, NULL)),
1096                 "Failed to enable SCLK DPM during DPM Start Function!",
1097                 return -EINVAL);
1098         }
1099
1100         /* enable MCLK dpm */
1101         if (0 == data->mclk_dpm_key_disabled) {
1102                 if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK))
1103                         smu7_disable_handshake_uvd(hwmgr);
1104
1105                 PP_ASSERT_WITH_CODE(
1106                                 (0 == smum_send_msg_to_smc(hwmgr,
1107                                                 PPSMC_MSG_MCLKDPM_Enable,
1108                                                 NULL)),
1109                                 "Failed to enable MCLK DPM during DPM Start Function!",
1110                                 return -EINVAL);
1111
1112                 if (hwmgr->chip_family != CHIP_VEGAM)
1113                         PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
1114
1115
1116                 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
1117                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x5);
1118                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x5);
1119                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x100005);
1120                         udelay(10);
1121                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x400005);
1122                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x400005);
1123                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x500005);
1124                 } else {
1125                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
1126                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
1127                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
1128                         udelay(10);
1129                         if (hwmgr->chip_id == CHIP_VEGAM) {
1130                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400009);
1131                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400009);
1132                         } else {
1133                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
1134                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
1135                         }
1136                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
1137                 }
1138         }
1139
1140         return 0;
1141 }
1142
1143 static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
1144 {
1145         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1146
1147         /*enable general power management */
1148
1149         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1150                         GLOBAL_PWRMGT_EN, 1);
1151
1152         /* enable sclk deep sleep */
1153
1154         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1155                         DYNAMIC_PM_EN, 1);
1156
1157         /* prepare for PCIE DPM */
1158
1159         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1160                         data->soft_regs_start +
1161                         smum_get_offsetof(hwmgr, SMU_SoftRegisters,
1162                                                 VoltageChangeTimeout), 0x1000);
1163         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
1164                         SWRST_COMMAND_1, RESETLC, 0x0);
1165
1166         if (hwmgr->chip_family == AMDGPU_FAMILY_CI)
1167                 cgs_write_register(hwmgr->device, 0x1488,
1168                         (cgs_read_register(hwmgr->device, 0x1488) & ~0x1));
1169
1170         if (smu7_enable_sclk_mclk_dpm(hwmgr)) {
1171                 pr_err("Failed to enable Sclk DPM and Mclk DPM!");
1172                 return -EINVAL;
1173         }
1174
1175         /* enable PCIE dpm */
1176         if (0 == data->pcie_dpm_key_disabled) {
1177                 PP_ASSERT_WITH_CODE(
1178                                 (0 == smum_send_msg_to_smc(hwmgr,
1179                                                 PPSMC_MSG_PCIeDPM_Enable,
1180                                                 NULL)),
1181                                 "Failed to enable pcie DPM during DPM Start Function!",
1182                                 return -EINVAL);
1183         }
1184
1185         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1186                                 PHM_PlatformCaps_Falcon_QuickTransition)) {
1187                 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr,
1188                                 PPSMC_MSG_EnableACDCGPIOInterrupt,
1189                                 NULL)),
1190                                 "Failed to enable AC DC GPIO Interrupt!",
1191                                 );
1192         }
1193
1194         return 0;
1195 }
1196
1197 static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1198 {
1199         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1200
1201         /* disable SCLK dpm */
1202         if (!data->sclk_dpm_key_disabled) {
1203                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1204                                 "Trying to disable SCLK DPM when DPM is disabled",
1205                                 return 0);
1206                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Disable, NULL);
1207         }
1208
1209         /* disable MCLK dpm */
1210         if (!data->mclk_dpm_key_disabled) {
1211                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1212                                 "Trying to disable MCLK DPM when DPM is disabled",
1213                                 return 0);
1214                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_Disable, NULL);
1215         }
1216
1217         return 0;
1218 }
1219
1220 static int smu7_stop_dpm(struct pp_hwmgr *hwmgr)
1221 {
1222         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1223
1224         /* disable general power management */
1225         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1226                         GLOBAL_PWRMGT_EN, 0);
1227         /* disable sclk deep sleep */
1228         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1229                         DYNAMIC_PM_EN, 0);
1230
1231         /* disable PCIE dpm */
1232         if (!data->pcie_dpm_key_disabled) {
1233                 PP_ASSERT_WITH_CODE(
1234                                 (smum_send_msg_to_smc(hwmgr,
1235                                                 PPSMC_MSG_PCIeDPM_Disable,
1236                                                 NULL) == 0),
1237                                 "Failed to disable pcie DPM during DPM Stop Function!",
1238                                 return -EINVAL);
1239         }
1240
1241         smu7_disable_sclk_mclk_dpm(hwmgr);
1242
1243         PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1244                         "Trying to disable voltage DPM when DPM is disabled",
1245                         return 0);
1246
1247         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Disable, NULL);
1248
1249         return 0;
1250 }
1251
1252 static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
1253 {
1254         bool protection;
1255         enum DPM_EVENT_SRC src;
1256
1257         switch (sources) {
1258         default:
1259                 pr_err("Unknown throttling event sources.");
1260                 fallthrough;
1261         case 0:
1262                 protection = false;
1263                 /* src is unused */
1264                 break;
1265         case (1 << PHM_AutoThrottleSource_Thermal):
1266                 protection = true;
1267                 src = DPM_EVENT_SRC_DIGITAL;
1268                 break;
1269         case (1 << PHM_AutoThrottleSource_External):
1270                 protection = true;
1271                 src = DPM_EVENT_SRC_EXTERNAL;
1272                 break;
1273         case (1 << PHM_AutoThrottleSource_External) |
1274                         (1 << PHM_AutoThrottleSource_Thermal):
1275                 protection = true;
1276                 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
1277                 break;
1278         }
1279         /* Order matters - don't enable thermal protection for the wrong source. */
1280         if (protection) {
1281                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
1282                                 DPM_EVENT_SRC, src);
1283                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1284                                 THERMAL_PROTECTION_DIS,
1285                                 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1286                                                 PHM_PlatformCaps_ThermalController));
1287         } else
1288                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1289                                 THERMAL_PROTECTION_DIS, 1);
1290 }
1291
1292 static int smu7_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
1293                 PHM_AutoThrottleSource source)
1294 {
1295         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1296
1297         if (!(data->active_auto_throttle_sources & (1 << source))) {
1298                 data->active_auto_throttle_sources |= 1 << source;
1299                 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
1300         }
1301         return 0;
1302 }
1303
1304 static int smu7_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
1305 {
1306         return smu7_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
1307 }
1308
1309 static int smu7_disable_auto_throttle_source(struct pp_hwmgr *hwmgr,
1310                 PHM_AutoThrottleSource source)
1311 {
1312         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1313
1314         if (data->active_auto_throttle_sources & (1 << source)) {
1315                 data->active_auto_throttle_sources &= ~(1 << source);
1316                 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
1317         }
1318         return 0;
1319 }
1320
1321 static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
1322 {
1323         return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
1324 }
1325
1326 static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
1327 {
1328         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1329         data->pcie_performance_request = true;
1330
1331         return 0;
1332 }
1333
1334 static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1335 {
1336         int tmp_result = 0;
1337         int result = 0;
1338
1339         if (smu7_voltage_control(hwmgr)) {
1340                 tmp_result = smu7_enable_voltage_control(hwmgr);
1341                 PP_ASSERT_WITH_CODE(tmp_result == 0,
1342                                 "Failed to enable voltage control!",
1343                                 result = tmp_result);
1344
1345                 tmp_result = smu7_construct_voltage_tables(hwmgr);
1346                 PP_ASSERT_WITH_CODE((0 == tmp_result),
1347                                 "Failed to construct voltage tables!",
1348                                 result = tmp_result);
1349         }
1350         smum_initialize_mc_reg_table(hwmgr);
1351
1352         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1353                         PHM_PlatformCaps_EngineSpreadSpectrumSupport))
1354                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1355                                 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
1356
1357         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1358                         PHM_PlatformCaps_ThermalController))
1359                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1360                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
1361
1362         tmp_result = smu7_program_static_screen_threshold_parameters(hwmgr);
1363         PP_ASSERT_WITH_CODE((0 == tmp_result),
1364                         "Failed to program static screen threshold parameters!",
1365                         result = tmp_result);
1366
1367         tmp_result = smu7_enable_display_gap(hwmgr);
1368         PP_ASSERT_WITH_CODE((0 == tmp_result),
1369                         "Failed to enable display gap!", result = tmp_result);
1370
1371         tmp_result = smu7_program_voting_clients(hwmgr);
1372         PP_ASSERT_WITH_CODE((0 == tmp_result),
1373                         "Failed to program voting clients!", result = tmp_result);
1374
1375         tmp_result = smum_process_firmware_header(hwmgr);
1376         PP_ASSERT_WITH_CODE((0 == tmp_result),
1377                         "Failed to process firmware header!", result = tmp_result);
1378
1379         if (hwmgr->chip_id != CHIP_VEGAM) {
1380                 tmp_result = smu7_initial_switch_from_arbf0_to_f1(hwmgr);
1381                 PP_ASSERT_WITH_CODE((0 == tmp_result),
1382                                 "Failed to initialize switch from ArbF0 to F1!",
1383                                 result = tmp_result);
1384         }
1385
1386         result = smu7_setup_default_dpm_tables(hwmgr);
1387         PP_ASSERT_WITH_CODE(0 == result,
1388                         "Failed to setup default DPM tables!", return result);
1389
1390         tmp_result = smum_init_smc_table(hwmgr);
1391         PP_ASSERT_WITH_CODE((0 == tmp_result),
1392                         "Failed to initialize SMC table!", result = tmp_result);
1393
1394         tmp_result = smu7_enable_vrhot_gpio_interrupt(hwmgr);
1395         PP_ASSERT_WITH_CODE((0 == tmp_result),
1396                         "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
1397
1398         smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay, NULL);
1399
1400         tmp_result = smu7_enable_sclk_control(hwmgr);
1401         PP_ASSERT_WITH_CODE((0 == tmp_result),
1402                         "Failed to enable SCLK control!", result = tmp_result);
1403
1404         tmp_result = smu7_enable_smc_voltage_controller(hwmgr);
1405         PP_ASSERT_WITH_CODE((0 == tmp_result),
1406                         "Failed to enable voltage control!", result = tmp_result);
1407
1408         tmp_result = smu7_enable_ulv(hwmgr);
1409         PP_ASSERT_WITH_CODE((0 == tmp_result),
1410                         "Failed to enable ULV!", result = tmp_result);
1411
1412         tmp_result = smu7_enable_deep_sleep_master_switch(hwmgr);
1413         PP_ASSERT_WITH_CODE((0 == tmp_result),
1414                         "Failed to enable deep sleep master switch!", result = tmp_result);
1415
1416         tmp_result = smu7_enable_didt_config(hwmgr);
1417         PP_ASSERT_WITH_CODE((tmp_result == 0),
1418                         "Failed to enable deep sleep master switch!", result = tmp_result);
1419
1420         tmp_result = smu7_start_dpm(hwmgr);
1421         PP_ASSERT_WITH_CODE((0 == tmp_result),
1422                         "Failed to start DPM!", result = tmp_result);
1423
1424         tmp_result = smu7_enable_smc_cac(hwmgr);
1425         PP_ASSERT_WITH_CODE((0 == tmp_result),
1426                         "Failed to enable SMC CAC!", result = tmp_result);
1427
1428         tmp_result = smu7_enable_power_containment(hwmgr);
1429         PP_ASSERT_WITH_CODE((0 == tmp_result),
1430                         "Failed to enable power containment!", result = tmp_result);
1431
1432         tmp_result = smu7_power_control_set_level(hwmgr);
1433         PP_ASSERT_WITH_CODE((0 == tmp_result),
1434                         "Failed to power control set level!", result = tmp_result);
1435
1436         tmp_result = smu7_enable_thermal_auto_throttle(hwmgr);
1437         PP_ASSERT_WITH_CODE((0 == tmp_result),
1438                         "Failed to enable thermal auto throttle!", result = tmp_result);
1439
1440         tmp_result = smu7_pcie_performance_request(hwmgr);
1441         PP_ASSERT_WITH_CODE((0 == tmp_result),
1442                         "pcie performance request failed!", result = tmp_result);
1443
1444         return 0;
1445 }
1446
1447 static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
1448 {
1449         if (!hwmgr->avfs_supported)
1450                 return 0;
1451
1452         if (enable) {
1453                 if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
1454                                 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
1455                         PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
1456                                         hwmgr, PPSMC_MSG_EnableAvfs, NULL),
1457                                         "Failed to enable AVFS!",
1458                                         return -EINVAL);
1459                 }
1460         } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
1461                         CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
1462                 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
1463                                 hwmgr, PPSMC_MSG_DisableAvfs, NULL),
1464                                 "Failed to disable AVFS!",
1465                                 return -EINVAL);
1466         }
1467
1468         return 0;
1469 }
1470
1471 static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
1472 {
1473         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1474
1475         if (!hwmgr->avfs_supported)
1476                 return 0;
1477
1478         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
1479                 smu7_avfs_control(hwmgr, false);
1480         } else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
1481                 smu7_avfs_control(hwmgr, false);
1482                 smu7_avfs_control(hwmgr, true);
1483         } else {
1484                 smu7_avfs_control(hwmgr, true);
1485         }
1486
1487         return 0;
1488 }
1489
1490 static int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
1491 {
1492         int tmp_result, result = 0;
1493
1494         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1495                         PHM_PlatformCaps_ThermalController))
1496                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1497                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1);
1498
1499         tmp_result = smu7_disable_power_containment(hwmgr);
1500         PP_ASSERT_WITH_CODE((tmp_result == 0),
1501                         "Failed to disable power containment!", result = tmp_result);
1502
1503         tmp_result = smu7_disable_smc_cac(hwmgr);
1504         PP_ASSERT_WITH_CODE((tmp_result == 0),
1505                         "Failed to disable SMC CAC!", result = tmp_result);
1506
1507         tmp_result = smu7_disable_didt_config(hwmgr);
1508         PP_ASSERT_WITH_CODE((tmp_result == 0),
1509                         "Failed to disable DIDT!", result = tmp_result);
1510
1511         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1512                         CG_SPLL_SPREAD_SPECTRUM, SSEN, 0);
1513         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1514                         GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0);
1515
1516         tmp_result = smu7_disable_thermal_auto_throttle(hwmgr);
1517         PP_ASSERT_WITH_CODE((tmp_result == 0),
1518                         "Failed to disable thermal auto throttle!", result = tmp_result);
1519
1520         tmp_result = smu7_avfs_control(hwmgr, false);
1521         PP_ASSERT_WITH_CODE((tmp_result == 0),
1522                         "Failed to disable AVFS!", result = tmp_result);
1523
1524         tmp_result = smu7_stop_dpm(hwmgr);
1525         PP_ASSERT_WITH_CODE((tmp_result == 0),
1526                         "Failed to stop DPM!", result = tmp_result);
1527
1528         tmp_result = smu7_disable_deep_sleep_master_switch(hwmgr);
1529         PP_ASSERT_WITH_CODE((tmp_result == 0),
1530                         "Failed to disable deep sleep master switch!", result = tmp_result);
1531
1532         tmp_result = smu7_disable_ulv(hwmgr);
1533         PP_ASSERT_WITH_CODE((tmp_result == 0),
1534                         "Failed to disable ULV!", result = tmp_result);
1535
1536         tmp_result = smu7_clear_voting_clients(hwmgr);
1537         PP_ASSERT_WITH_CODE((tmp_result == 0),
1538                         "Failed to clear voting clients!", result = tmp_result);
1539
1540         tmp_result = smu7_reset_to_default(hwmgr);
1541         PP_ASSERT_WITH_CODE((tmp_result == 0),
1542                         "Failed to reset to default!", result = tmp_result);
1543
1544         tmp_result = smum_stop_smc(hwmgr);
1545         PP_ASSERT_WITH_CODE((tmp_result == 0),
1546                         "Failed to stop smc!", result = tmp_result);
1547
1548         tmp_result = smu7_force_switch_to_arbf0(hwmgr);
1549         PP_ASSERT_WITH_CODE((tmp_result == 0),
1550                         "Failed to force to switch arbf0!", result = tmp_result);
1551
1552         return result;
1553 }
1554
1555 static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
1556 {
1557         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1558         struct phm_ppt_v1_information *table_info =
1559                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1560         struct amdgpu_device *adev = hwmgr->adev;
1561
1562         data->dll_default_on = false;
1563         data->mclk_dpm0_activity_target = 0xa;
1564         data->vddc_vddgfx_delta = 300;
1565         data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT;
1566         data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT;
1567         data->voting_rights_clients[0] = SMU7_VOTINGRIGHTSCLIENTS_DFLT0;
1568         data->voting_rights_clients[1]= SMU7_VOTINGRIGHTSCLIENTS_DFLT1;
1569         data->voting_rights_clients[2] = SMU7_VOTINGRIGHTSCLIENTS_DFLT2;
1570         data->voting_rights_clients[3]= SMU7_VOTINGRIGHTSCLIENTS_DFLT3;
1571         data->voting_rights_clients[4]= SMU7_VOTINGRIGHTSCLIENTS_DFLT4;
1572         data->voting_rights_clients[5]= SMU7_VOTINGRIGHTSCLIENTS_DFLT5;
1573         data->voting_rights_clients[6]= SMU7_VOTINGRIGHTSCLIENTS_DFLT6;
1574         data->voting_rights_clients[7]= SMU7_VOTINGRIGHTSCLIENTS_DFLT7;
1575
1576         data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
1577         data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
1578         data->pcie_dpm_key_disabled = hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
1579         /* need to set voltage control types before EVV patching */
1580         data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE;
1581         data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE;
1582         data->mvdd_control = SMU7_VOLTAGE_CONTROL_NONE;
1583         data->enable_tdc_limit_feature = true;
1584         data->enable_pkg_pwr_tracking_feature = true;
1585         data->force_pcie_gen = PP_PCIEGenInvalid;
1586         data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;
1587         data->current_profile_setting.bupdate_sclk = 1;
1588         data->current_profile_setting.sclk_up_hyst = 0;
1589         data->current_profile_setting.sclk_down_hyst = 100;
1590         data->current_profile_setting.sclk_activity = SMU7_SCLK_TARGETACTIVITY_DFLT;
1591         data->current_profile_setting.bupdate_mclk = 1;
1592         if (hwmgr->chip_id >= CHIP_POLARIS10) {
1593                 if (adev->gmc.vram_width == 256) {
1594                         data->current_profile_setting.mclk_up_hyst = 10;
1595                         data->current_profile_setting.mclk_down_hyst = 60;
1596                         data->current_profile_setting.mclk_activity = 25;
1597                 } else if (adev->gmc.vram_width == 128) {
1598                         data->current_profile_setting.mclk_up_hyst = 5;
1599                         data->current_profile_setting.mclk_down_hyst = 16;
1600                         data->current_profile_setting.mclk_activity = 20;
1601                 } else if (adev->gmc.vram_width == 64) {
1602                         data->current_profile_setting.mclk_up_hyst = 3;
1603                         data->current_profile_setting.mclk_down_hyst = 16;
1604                         data->current_profile_setting.mclk_activity = 20;
1605                 }
1606         } else {
1607                 data->current_profile_setting.mclk_up_hyst = 0;
1608                 data->current_profile_setting.mclk_down_hyst = 100;
1609                 data->current_profile_setting.mclk_activity = SMU7_MCLK_TARGETACTIVITY_DFLT;
1610         }
1611         hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
1612         hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1613         hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1614
1615         if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) {
1616                 uint8_t tmp1, tmp2;
1617                 uint16_t tmp3 = 0;
1618                 atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2,
1619                                                 &tmp3);
1620                 tmp3 = (tmp3 >> 5) & 0x3;
1621                 data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3;
1622         } else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
1623                 data->vddc_phase_shed_control = 1;
1624         } else {
1625                 data->vddc_phase_shed_control = 0;
1626         }
1627
1628         if (hwmgr->chip_id  == CHIP_HAWAII) {
1629                 data->thermal_temp_setting.temperature_low = 94500;
1630                 data->thermal_temp_setting.temperature_high = 95000;
1631                 data->thermal_temp_setting.temperature_shutdown = 104000;
1632         } else {
1633                 data->thermal_temp_setting.temperature_low = 99500;
1634                 data->thermal_temp_setting.temperature_high = 100000;
1635                 data->thermal_temp_setting.temperature_shutdown = 104000;
1636         }
1637
1638         data->fast_watermark_threshold = 100;
1639         if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1640                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
1641                 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1642         else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1643                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
1644                 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1645
1646         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1647                         PHM_PlatformCaps_ControlVDDGFX)) {
1648                 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1649                         VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
1650                         data->vdd_gfx_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1651                 }
1652         }
1653
1654         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1655                         PHM_PlatformCaps_EnableMVDDControl)) {
1656                 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1657                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
1658                         data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1659                 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1660                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
1661                         data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1662         }
1663
1664         if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control)
1665                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1666                         PHM_PlatformCaps_ControlVDDGFX);
1667
1668         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1669                         PHM_PlatformCaps_ControlVDDCI)) {
1670                 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1671                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
1672                         data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1673                 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1674                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
1675                         data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1676         }
1677
1678         if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE)
1679                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1680                                 PHM_PlatformCaps_EnableMVDDControl);
1681
1682         if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE)
1683                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1684                                 PHM_PlatformCaps_ControlVDDCI);
1685
1686         if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK)
1687                 && (table_info->cac_dtp_table->usClockStretchAmount != 0))
1688                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1689                                         PHM_PlatformCaps_ClockStretcher);
1690
1691         data->pcie_gen_performance.max = PP_PCIEGen1;
1692         data->pcie_gen_performance.min = PP_PCIEGen3;
1693         data->pcie_gen_power_saving.max = PP_PCIEGen1;
1694         data->pcie_gen_power_saving.min = PP_PCIEGen3;
1695         data->pcie_lane_performance.max = 0;
1696         data->pcie_lane_performance.min = 16;
1697         data->pcie_lane_power_saving.max = 0;
1698         data->pcie_lane_power_saving.min = 16;
1699
1700
1701         if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
1702                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1703                               PHM_PlatformCaps_UVDPowerGating);
1704         if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
1705                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1706                               PHM_PlatformCaps_VCEPowerGating);
1707 }
1708
1709 /**
1710 * Get Leakage VDDC based on leakage ID.
1711 *
1712 * @param    hwmgr  the address of the powerplay hardware manager.
1713 * @return   always 0
1714 */
1715 static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr)
1716 {
1717         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1718         uint16_t vv_id;
1719         uint16_t vddc = 0;
1720         uint16_t vddgfx = 0;
1721         uint16_t i, j;
1722         uint32_t sclk = 0;
1723         struct phm_ppt_v1_information *table_info =
1724                         (struct phm_ppt_v1_information *)hwmgr->pptable;
1725         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL;
1726
1727
1728         for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
1729                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1730
1731                 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1732                         if ((hwmgr->pp_table_version == PP_TABLE_V1)
1733                             && !phm_get_sclk_for_voltage_evv(hwmgr,
1734                                                 table_info->vddgfx_lookup_table, vv_id, &sclk)) {
1735                                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1736                                                         PHM_PlatformCaps_ClockStretcher)) {
1737                                         sclk_table = table_info->vdd_dep_on_sclk;
1738
1739                                         for (j = 1; j < sclk_table->count; j++) {
1740                                                 if (sclk_table->entries[j].clk == sclk &&
1741                                                                 sclk_table->entries[j].cks_enable == 0) {
1742                                                         sclk += 5000;
1743                                                         break;
1744                                                 }
1745                                         }
1746                                 }
1747                                 if (0 == atomctrl_get_voltage_evv_on_sclk
1748                                     (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
1749                                      vv_id, &vddgfx)) {
1750                                         /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
1751                                         PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -EINVAL);
1752
1753                                         /* the voltage should not be zero nor equal to leakage ID */
1754                                         if (vddgfx != 0 && vddgfx != vv_id) {
1755                                                 data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx;
1756                                                 data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = vv_id;
1757                                                 data->vddcgfx_leakage.count++;
1758                                         }
1759                                 } else {
1760                                         pr_info("Error retrieving EVV voltage value!\n");
1761                                 }
1762                         }
1763                 } else {
1764                         if ((hwmgr->pp_table_version == PP_TABLE_V0)
1765                                 || !phm_get_sclk_for_voltage_evv(hwmgr,
1766                                         table_info->vddc_lookup_table, vv_id, &sclk)) {
1767                                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1768                                                 PHM_PlatformCaps_ClockStretcher)) {
1769                                         if (table_info == NULL)
1770                                                 return -EINVAL;
1771                                         sclk_table = table_info->vdd_dep_on_sclk;
1772
1773                                         for (j = 1; j < sclk_table->count; j++) {
1774                                                 if (sclk_table->entries[j].clk == sclk &&
1775                                                                 sclk_table->entries[j].cks_enable == 0) {
1776                                                         sclk += 5000;
1777                                                         break;
1778                                                 }
1779                                         }
1780                                 }
1781
1782                                 if (phm_get_voltage_evv_on_sclk(hwmgr,
1783                                                         VOLTAGE_TYPE_VDDC,
1784                                                         sclk, vv_id, &vddc) == 0) {
1785                                         if (vddc >= 2000 || vddc == 0)
1786                                                 return -EINVAL;
1787                                 } else {
1788                                         pr_debug("failed to retrieving EVV voltage!\n");
1789                                         continue;
1790                                 }
1791
1792                                 /* the voltage should not be zero nor equal to leakage ID */
1793                                 if (vddc != 0 && vddc != vv_id) {
1794                                         data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc);
1795                                         data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
1796                                         data->vddc_leakage.count++;
1797                                 }
1798                         }
1799                 }
1800         }
1801
1802         return 0;
1803 }
1804
1805 /**
1806  * Change virtual leakage voltage to actual value.
1807  *
1808  * @param     hwmgr  the address of the powerplay hardware manager.
1809  * @param     pointer to changing voltage
1810  * @param     pointer to leakage table
1811  */
1812 static void smu7_patch_ppt_v1_with_vdd_leakage(struct pp_hwmgr *hwmgr,
1813                 uint16_t *voltage, struct smu7_leakage_voltage *leakage_table)
1814 {
1815         uint32_t index;
1816
1817         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
1818         for (index = 0; index < leakage_table->count; index++) {
1819                 /* if this voltage matches a leakage voltage ID */
1820                 /* patch with actual leakage voltage */
1821                 if (leakage_table->leakage_id[index] == *voltage) {
1822                         *voltage = leakage_table->actual_voltage[index];
1823                         break;
1824                 }
1825         }
1826
1827         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
1828                 pr_err("Voltage value looks like a Leakage ID but it's not patched \n");
1829 }
1830
1831 /**
1832 * Patch voltage lookup table by EVV leakages.
1833 *
1834 * @param     hwmgr  the address of the powerplay hardware manager.
1835 * @param     pointer to voltage lookup table
1836 * @param     pointer to leakage table
1837 * @return     always 0
1838 */
1839 static int smu7_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
1840                 phm_ppt_v1_voltage_lookup_table *lookup_table,
1841                 struct smu7_leakage_voltage *leakage_table)
1842 {
1843         uint32_t i;
1844
1845         for (i = 0; i < lookup_table->count; i++)
1846                 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
1847                                 &lookup_table->entries[i].us_vdd, leakage_table);
1848
1849         return 0;
1850 }
1851
1852 static int smu7_patch_clock_voltage_limits_with_vddc_leakage(
1853                 struct pp_hwmgr *hwmgr, struct smu7_leakage_voltage *leakage_table,
1854                 uint16_t *vddc)
1855 {
1856         struct phm_ppt_v1_information *table_info =
1857                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1858         smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
1859         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
1860                         table_info->max_clock_voltage_on_dc.vddc;
1861         return 0;
1862 }
1863
1864 static int smu7_patch_voltage_dependency_tables_with_lookup_table(
1865                 struct pp_hwmgr *hwmgr)
1866 {
1867         uint8_t entry_id;
1868         uint8_t voltage_id;
1869         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1870         struct phm_ppt_v1_information *table_info =
1871                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1872
1873         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1874                         table_info->vdd_dep_on_sclk;
1875         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
1876                         table_info->vdd_dep_on_mclk;
1877         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1878                         table_info->mm_dep_table;
1879
1880         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1881                 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1882                         voltage_id = sclk_table->entries[entry_id].vddInd;
1883                         sclk_table->entries[entry_id].vddgfx =
1884                                 table_info->vddgfx_lookup_table->entries[voltage_id].us_vdd;
1885                 }
1886         } else {
1887                 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1888                         voltage_id = sclk_table->entries[entry_id].vddInd;
1889                         sclk_table->entries[entry_id].vddc =
1890                                 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1891                 }
1892         }
1893
1894         for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
1895                 voltage_id = mclk_table->entries[entry_id].vddInd;
1896                 mclk_table->entries[entry_id].vddc =
1897                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1898         }
1899
1900         for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
1901                 voltage_id = mm_table->entries[entry_id].vddcInd;
1902                 mm_table->entries[entry_id].vddc =
1903                         table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1904         }
1905
1906         return 0;
1907
1908 }
1909
1910 static int phm_add_voltage(struct pp_hwmgr *hwmgr,
1911                         phm_ppt_v1_voltage_lookup_table *look_up_table,
1912                         phm_ppt_v1_voltage_lookup_record *record)
1913 {
1914         uint32_t i;
1915
1916         PP_ASSERT_WITH_CODE((NULL != look_up_table),
1917                 "Lookup Table empty.", return -EINVAL);
1918         PP_ASSERT_WITH_CODE((0 != look_up_table->count),
1919                 "Lookup Table empty.", return -EINVAL);
1920
1921         i = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
1922         PP_ASSERT_WITH_CODE((i >= look_up_table->count),
1923                 "Lookup Table is full.", return -EINVAL);
1924
1925         /* This is to avoid entering duplicate calculated records. */
1926         for (i = 0; i < look_up_table->count; i++) {
1927                 if (look_up_table->entries[i].us_vdd == record->us_vdd) {
1928                         if (look_up_table->entries[i].us_calculated == 1)
1929                                 return 0;
1930                         break;
1931                 }
1932         }
1933
1934         look_up_table->entries[i].us_calculated = 1;
1935         look_up_table->entries[i].us_vdd = record->us_vdd;
1936         look_up_table->entries[i].us_cac_low = record->us_cac_low;
1937         look_up_table->entries[i].us_cac_mid = record->us_cac_mid;
1938         look_up_table->entries[i].us_cac_high = record->us_cac_high;
1939         /* Only increment the count when we're appending, not replacing duplicate entry. */
1940         if (i == look_up_table->count)
1941                 look_up_table->count++;
1942
1943         return 0;
1944 }
1945
1946
1947 static int smu7_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
1948 {
1949         uint8_t entry_id;
1950         struct phm_ppt_v1_voltage_lookup_record v_record;
1951         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1952         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1953
1954         phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
1955         phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
1956
1957         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1958                 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1959                         if (sclk_table->entries[entry_id].vdd_offset & (1 << 15))
1960                                 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx +
1961                                         sclk_table->entries[entry_id].vdd_offset - 0xFFFF;
1962                         else
1963                                 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx +
1964                                         sclk_table->entries[entry_id].vdd_offset;
1965
1966                         sclk_table->entries[entry_id].vddc =
1967                                 v_record.us_cac_low = v_record.us_cac_mid =
1968                                 v_record.us_cac_high = v_record.us_vdd;
1969
1970                         phm_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record);
1971                 }
1972
1973                 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
1974                         if (mclk_table->entries[entry_id].vdd_offset & (1 << 15))
1975                                 v_record.us_vdd = mclk_table->entries[entry_id].vddc +
1976                                         mclk_table->entries[entry_id].vdd_offset - 0xFFFF;
1977                         else
1978                                 v_record.us_vdd = mclk_table->entries[entry_id].vddc +
1979                                         mclk_table->entries[entry_id].vdd_offset;
1980
1981                         mclk_table->entries[entry_id].vddgfx = v_record.us_cac_low =
1982                                 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
1983                         phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
1984                 }
1985         }
1986         return 0;
1987 }
1988
1989 static int smu7_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
1990 {
1991         uint8_t entry_id;
1992         struct phm_ppt_v1_voltage_lookup_record v_record;
1993         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1994         struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1995         phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1996
1997         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1998                 for (entry_id = 0; entry_id < mm_table->count; entry_id++) {
1999                         if (mm_table->entries[entry_id].vddgfx_offset & (1 << 15))
2000                                 v_record.us_vdd = mm_table->entries[entry_id].vddc +
2001                                         mm_table->entries[entry_id].vddgfx_offset - 0xFFFF;
2002                         else
2003                                 v_record.us_vdd = mm_table->entries[entry_id].vddc +
2004                                         mm_table->entries[entry_id].vddgfx_offset;
2005
2006                         /* Add the calculated VDDGFX to the VDDGFX lookup table */
2007                         mm_table->entries[entry_id].vddgfx = v_record.us_cac_low =
2008                                 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
2009                         phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
2010                 }
2011         }
2012         return 0;
2013 }
2014
2015 static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr,
2016                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
2017 {
2018         uint32_t table_size, i, j;
2019         table_size = lookup_table->count;
2020
2021         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
2022                 "Lookup table is empty", return -EINVAL);
2023
2024         /* Sorting voltages */
2025         for (i = 0; i < table_size - 1; i++) {
2026                 for (j = i + 1; j > 0; j--) {
2027                         if (lookup_table->entries[j].us_vdd <
2028                                         lookup_table->entries[j - 1].us_vdd) {
2029                                 swap(lookup_table->entries[j - 1],
2030                                      lookup_table->entries[j]);
2031                         }
2032                 }
2033         }
2034
2035         return 0;
2036 }
2037
2038 static int smu7_complete_dependency_tables(struct pp_hwmgr *hwmgr)
2039 {
2040         int result = 0;
2041         int tmp_result;
2042         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2043         struct phm_ppt_v1_information *table_info =
2044                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2045
2046         if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
2047                 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
2048                         table_info->vddgfx_lookup_table, &(data->vddcgfx_leakage));
2049                 if (tmp_result != 0)
2050                         result = tmp_result;
2051
2052                 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
2053                         &table_info->max_clock_voltage_on_dc.vddgfx, &(data->vddcgfx_leakage));
2054         } else {
2055
2056                 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
2057                                 table_info->vddc_lookup_table, &(data->vddc_leakage));
2058                 if (tmp_result)
2059                         result = tmp_result;
2060
2061                 tmp_result = smu7_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
2062                                 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
2063                 if (tmp_result)
2064                         result = tmp_result;
2065         }
2066
2067         tmp_result = smu7_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
2068         if (tmp_result)
2069                 result = tmp_result;
2070
2071         tmp_result = smu7_calc_voltage_dependency_tables(hwmgr);
2072         if (tmp_result)
2073                 result = tmp_result;
2074
2075         tmp_result = smu7_calc_mm_voltage_dependency_table(hwmgr);
2076         if (tmp_result)
2077                 result = tmp_result;
2078
2079         tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddgfx_lookup_table);
2080         if (tmp_result)
2081                 result = tmp_result;
2082
2083         tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
2084         if (tmp_result)
2085                 result = tmp_result;
2086
2087         return result;
2088 }
2089
2090 static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr)
2091 {
2092         struct phm_ppt_v1_information *table_info =
2093                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2094
2095         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2096                                                 table_info->vdd_dep_on_sclk;
2097         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
2098                                                 table_info->vdd_dep_on_mclk;
2099
2100         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
2101                 "VDD dependency on SCLK table is missing.",
2102                 return -EINVAL);
2103         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
2104                 "VDD dependency on SCLK table has to have is missing.",
2105                 return -EINVAL);
2106
2107         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
2108                 "VDD dependency on MCLK table is missing",
2109                 return -EINVAL);
2110         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
2111                 "VDD dependency on MCLK table has to have is missing.",
2112                 return -EINVAL);
2113
2114         table_info->max_clock_voltage_on_ac.sclk =
2115                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
2116         table_info->max_clock_voltage_on_ac.mclk =
2117                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
2118         table_info->max_clock_voltage_on_ac.vddc =
2119                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2120         table_info->max_clock_voltage_on_ac.vddci =
2121                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
2122
2123         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
2124         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
2125         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
2126         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = table_info->max_clock_voltage_on_ac.vddci;
2127
2128         return 0;
2129 }
2130
2131 static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
2132 {
2133         struct phm_ppt_v1_information *table_info =
2134                        (struct phm_ppt_v1_information *)(hwmgr->pptable);
2135         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
2136         struct phm_ppt_v1_voltage_lookup_table *lookup_table;
2137         uint32_t i;
2138         uint32_t hw_revision, sub_vendor_id, sub_sys_id;
2139         struct amdgpu_device *adev = hwmgr->adev;
2140
2141         if (table_info != NULL) {
2142                 dep_mclk_table = table_info->vdd_dep_on_mclk;
2143                 lookup_table = table_info->vddc_lookup_table;
2144         } else
2145                 return 0;
2146
2147         hw_revision = adev->pdev->revision;
2148         sub_sys_id = adev->pdev->subsystem_device;
2149         sub_vendor_id = adev->pdev->subsystem_vendor;
2150
2151         if (hwmgr->chip_id == CHIP_POLARIS10 && hw_revision == 0xC7 &&
2152                         ((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) ||
2153                     (sub_sys_id == 0x4a8 && sub_vendor_id == 0x1043) ||
2154                     (sub_sys_id == 0x9480 && sub_vendor_id == 0x1682))) {
2155                 if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000)
2156                         return 0;
2157
2158                 for (i = 0; i < lookup_table->count; i++) {
2159                         if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) {
2160                                 dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i;
2161                                 return 0;
2162                         }
2163                 }
2164         }
2165         return 0;
2166 }
2167
2168 static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr)
2169 {
2170         struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2171         uint32_t temp_reg;
2172         struct phm_ppt_v1_information *table_info =
2173                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2174
2175
2176         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
2177                 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
2178                 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
2179                 case 0:
2180                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
2181                         break;
2182                 case 1:
2183                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
2184                         break;
2185                 case 2:
2186                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
2187                         break;
2188                 case 3:
2189                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
2190                         break;
2191                 case 4:
2192                         temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
2193                         break;
2194                 default:
2195                         break;
2196                 }
2197                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
2198         }
2199
2200         if (table_info == NULL)
2201                 return 0;
2202
2203         if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
2204                 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
2205                 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
2206                         (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
2207
2208                 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
2209                         (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
2210
2211                 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
2212
2213                 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
2214
2215                 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
2216                         (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
2217
2218                 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
2219
2220                 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
2221                                                                 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp - 50) : 0;
2222
2223                 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
2224                 table_info->cac_dtp_table->usOperatingTempStep = 1;
2225                 table_info->cac_dtp_table->usOperatingTempHyst = 1;
2226
2227                 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
2228                                hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
2229
2230                 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
2231                                hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
2232
2233                 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
2234                                table_info->cac_dtp_table->usOperatingTempMinLimit;
2235
2236                 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
2237                                table_info->cac_dtp_table->usOperatingTempMaxLimit;
2238
2239                 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
2240                                table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
2241
2242                 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
2243                                table_info->cac_dtp_table->usOperatingTempStep;
2244
2245                 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
2246                                table_info->cac_dtp_table->usTargetOperatingTemp;
2247                 if (hwmgr->feature_mask & PP_OD_FUZZY_FAN_CONTROL_MASK)
2248                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2249                                         PHM_PlatformCaps_ODFuzzyFanControlSupport);
2250         }
2251
2252         return 0;
2253 }
2254
2255 /**
2256  * Change virtual leakage voltage to actual value.
2257  *
2258  * @param     hwmgr  the address of the powerplay hardware manager.
2259  * @param     pointer to changing voltage
2260  * @param     pointer to leakage table
2261  */
2262 static void smu7_patch_ppt_v0_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2263                 uint32_t *voltage, struct smu7_leakage_voltage *leakage_table)
2264 {
2265         uint32_t index;
2266
2267         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2268         for (index = 0; index < leakage_table->count; index++) {
2269                 /* if this voltage matches a leakage voltage ID */
2270                 /* patch with actual leakage voltage */
2271                 if (leakage_table->leakage_id[index] == *voltage) {
2272                         *voltage = leakage_table->actual_voltage[index];
2273                         break;
2274                 }
2275         }
2276
2277         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2278                 pr_err("Voltage value looks like a Leakage ID but it's not patched \n");
2279 }
2280
2281
2282 static int smu7_patch_vddc(struct pp_hwmgr *hwmgr,
2283                               struct phm_clock_voltage_dependency_table *tab)
2284 {
2285         uint16_t i;
2286         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2287
2288         if (tab)
2289                 for (i = 0; i < tab->count; i++)
2290                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2291                                                 &data->vddc_leakage);
2292
2293         return 0;
2294 }
2295
2296 static int smu7_patch_vddci(struct pp_hwmgr *hwmgr,
2297                                struct phm_clock_voltage_dependency_table *tab)
2298 {
2299         uint16_t i;
2300         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2301
2302         if (tab)
2303                 for (i = 0; i < tab->count; i++)
2304                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2305                                                         &data->vddci_leakage);
2306
2307         return 0;
2308 }
2309
2310 static int smu7_patch_vce_vddc(struct pp_hwmgr *hwmgr,
2311                                   struct phm_vce_clock_voltage_dependency_table *tab)
2312 {
2313         uint16_t i;
2314         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2315
2316         if (tab)
2317                 for (i = 0; i < tab->count; i++)
2318                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2319                                                         &data->vddc_leakage);
2320
2321         return 0;
2322 }
2323
2324
2325 static int smu7_patch_uvd_vddc(struct pp_hwmgr *hwmgr,
2326                                   struct phm_uvd_clock_voltage_dependency_table *tab)
2327 {
2328         uint16_t i;
2329         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2330
2331         if (tab)
2332                 for (i = 0; i < tab->count; i++)
2333                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2334                                                         &data->vddc_leakage);
2335
2336         return 0;
2337 }
2338
2339 static int smu7_patch_vddc_shed_limit(struct pp_hwmgr *hwmgr,
2340                                          struct phm_phase_shedding_limits_table *tab)
2341 {
2342         uint16_t i;
2343         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2344
2345         if (tab)
2346                 for (i = 0; i < tab->count; i++)
2347                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].Voltage,
2348                                                         &data->vddc_leakage);
2349
2350         return 0;
2351 }
2352
2353 static int smu7_patch_samu_vddc(struct pp_hwmgr *hwmgr,
2354                                    struct phm_samu_clock_voltage_dependency_table *tab)
2355 {
2356         uint16_t i;
2357         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2358
2359         if (tab)
2360                 for (i = 0; i < tab->count; i++)
2361                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2362                                                         &data->vddc_leakage);
2363
2364         return 0;
2365 }
2366
2367 static int smu7_patch_acp_vddc(struct pp_hwmgr *hwmgr,
2368                                   struct phm_acp_clock_voltage_dependency_table *tab)
2369 {
2370         uint16_t i;
2371         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2372
2373         if (tab)
2374                 for (i = 0; i < tab->count; i++)
2375                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2376                                         &data->vddc_leakage);
2377
2378         return 0;
2379 }
2380
2381 static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr,
2382                                   struct phm_clock_and_voltage_limits *tab)
2383 {
2384         uint32_t vddc, vddci;
2385         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2386
2387         if (tab) {
2388                 vddc = tab->vddc;
2389                 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc,
2390                                                    &data->vddc_leakage);
2391                 tab->vddc = vddc;
2392                 vddci = tab->vddci;
2393                 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddci,
2394                                                    &data->vddci_leakage);
2395                 tab->vddci = vddci;
2396         }
2397
2398         return 0;
2399 }
2400
2401 static int smu7_patch_cac_vddc(struct pp_hwmgr *hwmgr, struct phm_cac_leakage_table *tab)
2402 {
2403         uint32_t i;
2404         uint32_t vddc;
2405         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2406
2407         if (tab) {
2408                 for (i = 0; i < tab->count; i++) {
2409                         vddc = (uint32_t)(tab->entries[i].Vddc);
2410                         smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, &data->vddc_leakage);
2411                         tab->entries[i].Vddc = (uint16_t)vddc;
2412                 }
2413         }
2414
2415         return 0;
2416 }
2417
2418 static int smu7_patch_dependency_tables_with_leakage(struct pp_hwmgr *hwmgr)
2419 {
2420         int tmp;
2421
2422         tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk);
2423         if (tmp)
2424                 return -EINVAL;
2425
2426         tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk);
2427         if (tmp)
2428                 return -EINVAL;
2429
2430         tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
2431         if (tmp)
2432                 return -EINVAL;
2433
2434         tmp = smu7_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk);
2435         if (tmp)
2436                 return -EINVAL;
2437
2438         tmp = smu7_patch_vce_vddc(hwmgr, hwmgr->dyn_state.vce_clock_voltage_dependency_table);
2439         if (tmp)
2440                 return -EINVAL;
2441
2442         tmp = smu7_patch_uvd_vddc(hwmgr, hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
2443         if (tmp)
2444                 return -EINVAL;
2445
2446         tmp = smu7_patch_samu_vddc(hwmgr, hwmgr->dyn_state.samu_clock_voltage_dependency_table);
2447         if (tmp)
2448                 return -EINVAL;
2449
2450         tmp = smu7_patch_acp_vddc(hwmgr, hwmgr->dyn_state.acp_clock_voltage_dependency_table);
2451         if (tmp)
2452                 return -EINVAL;
2453
2454         tmp = smu7_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table);
2455         if (tmp)
2456                 return -EINVAL;
2457
2458         tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_ac);
2459         if (tmp)
2460                 return -EINVAL;
2461
2462         tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc);
2463         if (tmp)
2464                 return -EINVAL;
2465
2466         tmp = smu7_patch_cac_vddc(hwmgr, hwmgr->dyn_state.cac_leakage_table);
2467         if (tmp)
2468                 return -EINVAL;
2469
2470         return 0;
2471 }
2472
2473
2474 static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr)
2475 {
2476         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2477
2478         struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
2479         struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
2480         struct phm_clock_voltage_dependency_table *allowed_mclk_vddci_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
2481
2482         PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL,
2483                 "VDDC dependency on SCLK table is missing. This table is mandatory",
2484                 return -EINVAL);
2485         PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1,
2486                 "VDDC dependency on SCLK table has to have is missing. This table is mandatory",
2487                 return -EINVAL);
2488
2489         PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL,
2490                 "VDDC dependency on MCLK table is missing. This table is mandatory",
2491                 return -EINVAL);
2492         PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1,
2493                 "VDD dependency on MCLK table has to have is missing. This table is mandatory",
2494                 return -EINVAL);
2495
2496         data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v;
2497         data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2498
2499         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
2500                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
2501         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
2502                 allowed_mclk_vddc_table->entries[allowed_mclk_vddc_table->count - 1].clk;
2503         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
2504                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2505
2506         if (allowed_mclk_vddci_table != NULL && allowed_mclk_vddci_table->count >= 1) {
2507                 data->min_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[0].v;
2508                 data->max_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
2509         }
2510
2511         if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count >= 1)
2512                 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v;
2513
2514         return 0;
2515 }
2516
2517 static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2518 {
2519         kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
2520         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
2521         kfree(hwmgr->backend);
2522         hwmgr->backend = NULL;
2523
2524         return 0;
2525 }
2526
2527 static int smu7_get_elb_voltages(struct pp_hwmgr *hwmgr)
2528 {
2529         uint16_t virtual_voltage_id, vddc, vddci, efuse_voltage_id;
2530         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2531         int i;
2532
2533         if (atomctrl_get_leakage_id_from_efuse(hwmgr, &efuse_voltage_id) == 0) {
2534                 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
2535                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2536                         if (atomctrl_get_leakage_vddc_base_on_leakage(hwmgr, &vddc, &vddci,
2537                                                                 virtual_voltage_id,
2538                                                                 efuse_voltage_id) == 0) {
2539                                 if (vddc != 0 && vddc != virtual_voltage_id) {
2540                                         data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
2541                                         data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
2542                                         data->vddc_leakage.count++;
2543                                 }
2544                                 if (vddci != 0 && vddci != virtual_voltage_id) {
2545                                         data->vddci_leakage.actual_voltage[data->vddci_leakage.count] = vddci;
2546                                         data->vddci_leakage.leakage_id[data->vddci_leakage.count] = virtual_voltage_id;
2547                                         data->vddci_leakage.count++;
2548                                 }
2549                         }
2550                 }
2551         }
2552         return 0;
2553 }
2554
2555 static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2556 {
2557         struct smu7_hwmgr *data;
2558         int result = 0;
2559
2560         data = kzalloc(sizeof(struct smu7_hwmgr), GFP_KERNEL);
2561         if (data == NULL)
2562                 return -ENOMEM;
2563
2564         hwmgr->backend = data;
2565         smu7_patch_voltage_workaround(hwmgr);
2566         smu7_init_dpm_defaults(hwmgr);
2567
2568         /* Get leakage voltage based on leakage ID. */
2569         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2570                         PHM_PlatformCaps_EVV)) {
2571                 result = smu7_get_evv_voltages(hwmgr);
2572                 if (result) {
2573                         pr_info("Get EVV Voltage Failed.  Abort Driver loading!\n");
2574                         return -EINVAL;
2575                 }
2576         } else {
2577                 smu7_get_elb_voltages(hwmgr);
2578         }
2579
2580         if (hwmgr->pp_table_version == PP_TABLE_V1) {
2581                 smu7_complete_dependency_tables(hwmgr);
2582                 smu7_set_private_data_based_on_pptable_v1(hwmgr);
2583         } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
2584                 smu7_patch_dependency_tables_with_leakage(hwmgr);
2585                 smu7_set_private_data_based_on_pptable_v0(hwmgr);
2586         }
2587
2588         /* Initalize Dynamic State Adjustment Rule Settings */
2589         result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
2590
2591         if (0 == result) {
2592                 struct amdgpu_device *adev = hwmgr->adev;
2593
2594                 data->is_tlu_enabled = false;
2595
2596                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
2597                                                         SMU7_MAX_HARDWARE_POWERLEVELS;
2598                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
2599                 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
2600
2601                 data->pcie_gen_cap = adev->pm.pcie_gen_mask;
2602                 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
2603                         data->pcie_spc_cap = 20;
2604                 data->pcie_lane_cap = adev->pm.pcie_mlw_mask;
2605
2606                 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
2607 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
2608                 hwmgr->platform_descriptor.clockStep.engineClock = 500;
2609                 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
2610                 smu7_thermal_parameter_init(hwmgr);
2611         } else {
2612                 /* Ignore return value in here, we are cleaning up a mess. */
2613                 smu7_hwmgr_backend_fini(hwmgr);
2614         }
2615
2616         return 0;
2617 }
2618
2619 static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
2620 {
2621         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2622         uint32_t level, tmp;
2623
2624         if (!data->pcie_dpm_key_disabled) {
2625                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
2626                         level = 0;
2627                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
2628                         while (tmp >>= 1)
2629                                 level++;
2630
2631                         if (level)
2632                                 smum_send_msg_to_smc_with_parameter(hwmgr,
2633                                                 PPSMC_MSG_PCIeDPM_ForceLevel, level,
2634                                                 NULL);
2635                 }
2636         }
2637
2638         if (!data->sclk_dpm_key_disabled) {
2639                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
2640                         level = 0;
2641                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
2642                         while (tmp >>= 1)
2643                                 level++;
2644
2645                         if (level)
2646                                 smum_send_msg_to_smc_with_parameter(hwmgr,
2647                                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2648                                                 (1 << level),
2649                                                 NULL);
2650                 }
2651         }
2652
2653         if (!data->mclk_dpm_key_disabled) {
2654                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
2655                         level = 0;
2656                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
2657                         while (tmp >>= 1)
2658                                 level++;
2659
2660                         if (level)
2661                                 smum_send_msg_to_smc_with_parameter(hwmgr,
2662                                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
2663                                                 (1 << level),
2664                                                 NULL);
2665                 }
2666         }
2667
2668         return 0;
2669 }
2670
2671 static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
2672 {
2673         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2674
2675         if (hwmgr->pp_table_version == PP_TABLE_V1)
2676                 phm_apply_dal_min_voltage_request(hwmgr);
2677 /* TO DO  for v0 iceland and Ci*/
2678
2679         if (!data->sclk_dpm_key_disabled) {
2680                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
2681                         smum_send_msg_to_smc_with_parameter(hwmgr,
2682                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
2683                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask,
2684                                         NULL);
2685         }
2686
2687         if (!data->mclk_dpm_key_disabled) {
2688                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
2689                         smum_send_msg_to_smc_with_parameter(hwmgr,
2690                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
2691                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask,
2692                                         NULL);
2693         }
2694
2695         return 0;
2696 }
2697
2698 static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2699 {
2700         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2701
2702         if (!smum_is_dpm_running(hwmgr))
2703                 return -EINVAL;
2704
2705         if (!data->pcie_dpm_key_disabled) {
2706                 smum_send_msg_to_smc(hwmgr,
2707                                 PPSMC_MSG_PCIeDPM_UnForceLevel,
2708                                 NULL);
2709         }
2710
2711         return smu7_upload_dpm_level_enable_mask(hwmgr);
2712 }
2713
2714 static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2715 {
2716         struct smu7_hwmgr *data =
2717                         (struct smu7_hwmgr *)(hwmgr->backend);
2718         uint32_t level;
2719
2720         if (!data->sclk_dpm_key_disabled)
2721                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
2722                         level = phm_get_lowest_enabled_level(hwmgr,
2723                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
2724                         smum_send_msg_to_smc_with_parameter(hwmgr,
2725                                                             PPSMC_MSG_SCLKDPM_SetEnabledMask,
2726                                                             (1 << level),
2727                                                             NULL);
2728
2729         }
2730
2731         if (!data->mclk_dpm_key_disabled) {
2732                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
2733                         level = phm_get_lowest_enabled_level(hwmgr,
2734                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
2735                         smum_send_msg_to_smc_with_parameter(hwmgr,
2736                                                             PPSMC_MSG_MCLKDPM_SetEnabledMask,
2737                                                             (1 << level),
2738                                                             NULL);
2739                 }
2740         }
2741
2742         if (!data->pcie_dpm_key_disabled) {
2743                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
2744                         level = phm_get_lowest_enabled_level(hwmgr,
2745                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
2746                         smum_send_msg_to_smc_with_parameter(hwmgr,
2747                                                             PPSMC_MSG_PCIeDPM_ForceLevel,
2748                                                             (level),
2749                                                             NULL);
2750                 }
2751         }
2752
2753         return 0;
2754 }
2755
2756 static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
2757                                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask)
2758 {
2759         uint32_t percentage;
2760         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2761         struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;
2762         int32_t tmp_mclk;
2763         int32_t tmp_sclk;
2764         int32_t count;
2765
2766         if (golden_dpm_table->mclk_table.count < 1)
2767                 return -EINVAL;
2768
2769         percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value /
2770                         golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
2771
2772         if (golden_dpm_table->mclk_table.count == 1) {
2773                 percentage = 70;
2774                 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
2775                 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
2776         } else {
2777                 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value;
2778                 *mclk_mask = golden_dpm_table->mclk_table.count - 2;
2779         }
2780
2781         tmp_sclk = tmp_mclk * percentage / 100;
2782
2783         if (hwmgr->pp_table_version == PP_TABLE_V0) {
2784                 for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
2785                         count >= 0; count--) {
2786                         if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) {
2787                                 tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk;
2788                                 *sclk_mask = count;
2789                                 break;
2790                         }
2791                 }
2792                 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2793                         *sclk_mask = 0;
2794                         tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk;
2795                 }
2796
2797                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2798                         *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
2799         } else if (hwmgr->pp_table_version == PP_TABLE_V1) {
2800                 struct phm_ppt_v1_information *table_info =
2801                                 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2802
2803                 for (count = table_info->vdd_dep_on_sclk->count-1; count >= 0; count--) {
2804                         if (tmp_sclk >= table_info->vdd_dep_on_sclk->entries[count].clk) {
2805                                 tmp_sclk = table_info->vdd_dep_on_sclk->entries[count].clk;
2806                                 *sclk_mask = count;
2807                                 break;
2808                         }
2809                 }
2810                 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2811                         *sclk_mask = 0;
2812                         tmp_sclk =  table_info->vdd_dep_on_sclk->entries[0].clk;
2813                 }
2814
2815                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2816                         *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
2817         }
2818
2819         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
2820                 *mclk_mask = 0;
2821         else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2822                 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
2823
2824         *pcie_mask = data->dpm_table.pcie_speed_table.count - 1;
2825         hwmgr->pstate_sclk = tmp_sclk;
2826         hwmgr->pstate_mclk = tmp_mclk;
2827
2828         return 0;
2829 }
2830
2831 static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
2832                                 enum amd_dpm_forced_level level)
2833 {
2834         int ret = 0;
2835         uint32_t sclk_mask = 0;
2836         uint32_t mclk_mask = 0;
2837         uint32_t pcie_mask = 0;
2838
2839         if (hwmgr->pstate_sclk == 0)
2840                 smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
2841
2842         switch (level) {
2843         case AMD_DPM_FORCED_LEVEL_HIGH:
2844                 ret = smu7_force_dpm_highest(hwmgr);
2845                 break;
2846         case AMD_DPM_FORCED_LEVEL_LOW:
2847                 ret = smu7_force_dpm_lowest(hwmgr);
2848                 break;
2849         case AMD_DPM_FORCED_LEVEL_AUTO:
2850                 ret = smu7_unforce_dpm_levels(hwmgr);
2851                 break;
2852         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
2853         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
2854         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
2855         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
2856                 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
2857                 if (ret)
2858                         return ret;
2859                 smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
2860                 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
2861                 smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask);
2862                 break;
2863         case AMD_DPM_FORCED_LEVEL_MANUAL:
2864         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
2865         default:
2866                 break;
2867         }
2868
2869         if (!ret) {
2870                 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2871                         smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
2872                 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2873                         smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr);
2874         }
2875         return ret;
2876 }
2877
2878 static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr)
2879 {
2880         return sizeof(struct smu7_power_state);
2881 }
2882
2883 static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr,
2884                                  uint32_t vblank_time_us)
2885 {
2886         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2887         uint32_t switch_limit_us;
2888
2889         switch (hwmgr->chip_id) {
2890         case CHIP_POLARIS10:
2891         case CHIP_POLARIS11:
2892         case CHIP_POLARIS12:
2893                 if (hwmgr->is_kicker)
2894                         switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
2895                 else
2896                         switch_limit_us = data->is_memory_gddr5 ? 200 : 150;
2897                 break;
2898         case CHIP_VEGAM:
2899                 switch_limit_us = 30;
2900                 break;
2901         default:
2902                 switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
2903                 break;
2904         }
2905
2906         if (vblank_time_us < switch_limit_us)
2907                 return true;
2908         else
2909                 return false;
2910 }
2911
2912 static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
2913                                 struct pp_power_state *request_ps,
2914                         const struct pp_power_state *current_ps)
2915 {
2916         struct amdgpu_device *adev = hwmgr->adev;
2917         struct smu7_power_state *smu7_ps =
2918                                 cast_phw_smu7_power_state(&request_ps->hardware);
2919         uint32_t sclk;
2920         uint32_t mclk;
2921         struct PP_Clocks minimum_clocks = {0};
2922         bool disable_mclk_switching;
2923         bool disable_mclk_switching_for_frame_lock;
2924         const struct phm_clock_and_voltage_limits *max_limits;
2925         uint32_t i;
2926         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2927         struct phm_ppt_v1_information *table_info =
2928                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2929         int32_t count;
2930         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
2931
2932         data->battery_state = (PP_StateUILabel_Battery ==
2933                         request_ps->classification.ui_label);
2934
2935         PP_ASSERT_WITH_CODE(smu7_ps->performance_level_count == 2,
2936                                  "VI should always have 2 performance levels",
2937                                 );
2938
2939         max_limits = adev->pm.ac_power ?
2940                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
2941                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
2942
2943         /* Cap clock DPM tables at DC MAX if it is in DC. */
2944         if (!adev->pm.ac_power) {
2945                 for (i = 0; i < smu7_ps->performance_level_count; i++) {
2946                         if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk)
2947                                 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk;
2948                         if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk)
2949                                 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk;
2950                 }
2951         }
2952
2953         minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
2954         minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2955
2956         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2957                         PHM_PlatformCaps_StablePState)) {
2958                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
2959                 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
2960
2961                 for (count = table_info->vdd_dep_on_sclk->count - 1;
2962                                 count >= 0; count--) {
2963                         if (stable_pstate_sclk >=
2964                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
2965                                 stable_pstate_sclk =
2966                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
2967                                 break;
2968                         }
2969                 }
2970
2971                 if (count < 0)
2972                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
2973
2974                 stable_pstate_mclk = max_limits->mclk;
2975
2976                 minimum_clocks.engineClock = stable_pstate_sclk;
2977                 minimum_clocks.memoryClock = stable_pstate_mclk;
2978         }
2979
2980         disable_mclk_switching_for_frame_lock = phm_cap_enabled(
2981                                     hwmgr->platform_descriptor.platformCaps,
2982                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
2983
2984
2985         if (hwmgr->display_config->num_display == 0)
2986                 disable_mclk_switching = false;
2987         else
2988                 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
2989                                           !hwmgr->display_config->multi_monitor_in_sync) ||
2990                         disable_mclk_switching_for_frame_lock ||
2991                         smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time);
2992
2993         sclk = smu7_ps->performance_levels[0].engine_clock;
2994         mclk = smu7_ps->performance_levels[0].memory_clock;
2995
2996         if (disable_mclk_switching)
2997                 mclk = smu7_ps->performance_levels
2998                 [smu7_ps->performance_level_count - 1].memory_clock;
2999
3000         if (sclk < minimum_clocks.engineClock)
3001                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3002                                 max_limits->sclk : minimum_clocks.engineClock;
3003
3004         if (mclk < minimum_clocks.memoryClock)
3005                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3006                                 max_limits->mclk : minimum_clocks.memoryClock;
3007
3008         smu7_ps->performance_levels[0].engine_clock = sclk;
3009         smu7_ps->performance_levels[0].memory_clock = mclk;
3010
3011         smu7_ps->performance_levels[1].engine_clock =
3012                 (smu7_ps->performance_levels[1].engine_clock >=
3013                                 smu7_ps->performance_levels[0].engine_clock) ?
3014                                                 smu7_ps->performance_levels[1].engine_clock :
3015                                                 smu7_ps->performance_levels[0].engine_clock;
3016
3017         if (disable_mclk_switching) {
3018                 if (mclk < smu7_ps->performance_levels[1].memory_clock)
3019                         mclk = smu7_ps->performance_levels[1].memory_clock;
3020
3021                 smu7_ps->performance_levels[0].memory_clock = mclk;
3022                 smu7_ps->performance_levels[1].memory_clock = mclk;
3023         } else {
3024                 if (smu7_ps->performance_levels[1].memory_clock <
3025                                 smu7_ps->performance_levels[0].memory_clock)
3026                         smu7_ps->performance_levels[1].memory_clock =
3027                                         smu7_ps->performance_levels[0].memory_clock;
3028         }
3029
3030         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3031                         PHM_PlatformCaps_StablePState)) {
3032                 for (i = 0; i < smu7_ps->performance_level_count; i++) {
3033                         smu7_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3034                         smu7_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3035                         smu7_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3036                         smu7_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3037                 }
3038         }
3039         return 0;
3040 }
3041
3042
3043 static uint32_t smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3044 {
3045         struct pp_power_state  *ps;
3046         struct smu7_power_state  *smu7_ps;
3047
3048         if (hwmgr == NULL)
3049                 return -EINVAL;
3050
3051         ps = hwmgr->request_ps;
3052
3053         if (ps == NULL)
3054                 return -EINVAL;
3055
3056         smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
3057
3058         if (low)
3059                 return smu7_ps->performance_levels[0].memory_clock;
3060         else
3061                 return smu7_ps->performance_levels
3062                                 [smu7_ps->performance_level_count-1].memory_clock;
3063 }
3064
3065 static uint32_t smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3066 {
3067         struct pp_power_state  *ps;
3068         struct smu7_power_state  *smu7_ps;
3069
3070         if (hwmgr == NULL)
3071                 return -EINVAL;
3072
3073         ps = hwmgr->request_ps;
3074
3075         if (ps == NULL)
3076                 return -EINVAL;
3077
3078         smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
3079
3080         if (low)
3081                 return smu7_ps->performance_levels[0].engine_clock;
3082         else
3083                 return smu7_ps->performance_levels
3084                                 [smu7_ps->performance_level_count-1].engine_clock;
3085 }
3086
3087 static int smu7_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3088                                         struct pp_hw_power_state *hw_ps)
3089 {
3090         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3091         struct smu7_power_state *ps = (struct smu7_power_state *)hw_ps;
3092         ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3093         uint16_t size;
3094         uint8_t frev, crev;
3095         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3096
3097         /* First retrieve the Boot clocks and VDDC from the firmware info table.
3098          * We assume here that fw_info is unchanged if this call fails.
3099          */
3100         fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)smu_atom_get_data_table(hwmgr->adev, index,
3101                         &size, &frev, &crev);
3102         if (!fw_info)
3103                 /* During a test, there is no firmware info table. */
3104                 return 0;
3105
3106         /* Patch the state. */
3107         data->vbios_boot_state.sclk_bootup_value =
3108                         le32_to_cpu(fw_info->ulDefaultEngineClock);
3109         data->vbios_boot_state.mclk_bootup_value =
3110                         le32_to_cpu(fw_info->ulDefaultMemoryClock);
3111         data->vbios_boot_state.mvdd_bootup_value =
3112                         le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3113         data->vbios_boot_state.vddc_bootup_value =
3114                         le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3115         data->vbios_boot_state.vddci_bootup_value =
3116                         le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3117         data->vbios_boot_state.pcie_gen_bootup_value =
3118                         smu7_get_current_pcie_speed(hwmgr);
3119
3120         data->vbios_boot_state.pcie_lane_bootup_value =
3121                         (uint16_t)smu7_get_current_pcie_lane_number(hwmgr);
3122
3123         /* set boot power state */
3124         ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3125         ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3126         ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3127         ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3128
3129         return 0;
3130 }
3131
3132 static int smu7_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr)
3133 {
3134         int result;
3135         unsigned long ret = 0;
3136
3137         if (hwmgr->pp_table_version == PP_TABLE_V0) {
3138                 result = pp_tables_get_num_of_entries(hwmgr, &ret);
3139                 return result ? 0 : ret;
3140         } else if (hwmgr->pp_table_version == PP_TABLE_V1) {
3141                 result = get_number_of_powerplay_table_entries_v1_0(hwmgr);
3142                 return result;
3143         }
3144         return 0;
3145 }
3146
3147 static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr,
3148                 void *state, struct pp_power_state *power_state,
3149                 void *pp_table, uint32_t classification_flag)
3150 {
3151         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3152         struct smu7_power_state  *smu7_power_state =
3153                         (struct smu7_power_state *)(&(power_state->hardware));
3154         struct smu7_performance_level *performance_level;
3155         ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3156         ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3157                         (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3158         PPTable_Generic_SubTable_Header *sclk_dep_table =
3159                         (PPTable_Generic_SubTable_Header *)
3160                         (((unsigned long)powerplay_table) +
3161                                 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3162
3163         ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3164                         (ATOM_Tonga_MCLK_Dependency_Table *)
3165                         (((unsigned long)powerplay_table) +
3166                                 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3167
3168         /* The following fields are not initialized here: id orderedList allStatesList */
3169         power_state->classification.ui_label =
3170                         (le16_to_cpu(state_entry->usClassification) &
3171                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3172                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3173         power_state->classification.flags = classification_flag;
3174         /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3175
3176         power_state->classification.temporary_state = false;
3177         power_state->classification.to_be_deleted = false;
3178
3179         power_state->validation.disallowOnDC =
3180                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3181                                         ATOM_Tonga_DISALLOW_ON_DC));
3182
3183         power_state->pcie.lanes = 0;
3184
3185         power_state->display.disableFrameModulation = false;
3186         power_state->display.limitRefreshrate = false;
3187         power_state->display.enableVariBright =
3188                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3189                                         ATOM_Tonga_ENABLE_VARIBRIGHT));
3190
3191         power_state->validation.supportedPowerLevels = 0;
3192         power_state->uvd_clocks.VCLK = 0;
3193         power_state->uvd_clocks.DCLK = 0;
3194         power_state->temperatures.min = 0;
3195         power_state->temperatures.max = 0;
3196
3197         performance_level = &(smu7_power_state->performance_levels
3198                         [smu7_power_state->performance_level_count++]);
3199
3200         PP_ASSERT_WITH_CODE(
3201                         (smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
3202                         "Performance levels exceeds SMC limit!",
3203                         return -EINVAL);
3204
3205         PP_ASSERT_WITH_CODE(
3206                         (smu7_power_state->performance_level_count <=
3207                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3208                         "Performance levels exceeds Driver limit!",
3209                         return -EINVAL);
3210
3211         /* Performance levels are arranged from low to high. */
3212         performance_level->memory_clock = mclk_dep_table->entries
3213                         [state_entry->ucMemoryClockIndexLow].ulMclk;
3214         if (sclk_dep_table->ucRevId == 0)
3215                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3216                         [state_entry->ucEngineClockIndexLow].ulSclk;
3217         else if (sclk_dep_table->ucRevId == 1)
3218                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3219                         [state_entry->ucEngineClockIndexLow].ulSclk;
3220         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3221                         state_entry->ucPCIEGenLow);
3222         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3223                         state_entry->ucPCIELaneLow);
3224
3225         performance_level = &(smu7_power_state->performance_levels
3226                         [smu7_power_state->performance_level_count++]);
3227         performance_level->memory_clock = mclk_dep_table->entries
3228                         [state_entry->ucMemoryClockIndexHigh].ulMclk;
3229
3230         if (sclk_dep_table->ucRevId == 0)
3231                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3232                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3233         else if (sclk_dep_table->ucRevId == 1)
3234                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3235                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3236
3237         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3238                         state_entry->ucPCIEGenHigh);
3239         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3240                         state_entry->ucPCIELaneHigh);
3241
3242         return 0;
3243 }
3244
3245 static int smu7_get_pp_table_entry_v1(struct pp_hwmgr *hwmgr,
3246                 unsigned long entry_index, struct pp_power_state *state)
3247 {
3248         int result;
3249         struct smu7_power_state *ps;
3250         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3251         struct phm_ppt_v1_information *table_info =
3252                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3253         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3254                         table_info->vdd_dep_on_mclk;
3255
3256         state->hardware.magic = PHM_VIslands_Magic;
3257
3258         ps = (struct smu7_power_state *)(&state->hardware);
3259
3260         result = get_powerplay_table_entry_v1_0(hwmgr, entry_index, state,
3261                         smu7_get_pp_table_entry_callback_func_v1);
3262
3263         /* This is the earliest time we have all the dependency table and the VBIOS boot state
3264          * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3265          * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3266          */
3267         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3268                 if (dep_mclk_table->entries[0].clk !=
3269                                 data->vbios_boot_state.mclk_bootup_value)
3270                         pr_debug("Single MCLK entry VDDCI/MCLK dependency table "
3271                                         "does not match VBIOS boot MCLK level");
3272                 if (dep_mclk_table->entries[0].vddci !=
3273                                 data->vbios_boot_state.vddci_bootup_value)
3274                         pr_debug("Single VDDCI entry VDDCI/MCLK dependency table "
3275                                         "does not match VBIOS boot VDDCI level");
3276         }
3277
3278         /* set DC compatible flag if this state supports DC */
3279         if (!state->validation.disallowOnDC)
3280                 ps->dc_compatible = true;
3281
3282         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3283                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3284
3285         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3286         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3287
3288         if (!result) {
3289                 uint32_t i;
3290
3291                 switch (state->classification.ui_label) {
3292                 case PP_StateUILabel_Performance:
3293                         data->use_pcie_performance_levels = true;
3294                         for (i = 0; i < ps->performance_level_count; i++) {
3295                                 if (data->pcie_gen_performance.max <
3296                                                 ps->performance_levels[i].pcie_gen)
3297                                         data->pcie_gen_performance.max =
3298                                                         ps->performance_levels[i].pcie_gen;
3299
3300                                 if (data->pcie_gen_performance.min >
3301                                                 ps->performance_levels[i].pcie_gen)
3302                                         data->pcie_gen_performance.min =
3303                                                         ps->performance_levels[i].pcie_gen;
3304
3305                                 if (data->pcie_lane_performance.max <
3306                                                 ps->performance_levels[i].pcie_lane)
3307                                         data->pcie_lane_performance.max =
3308                                                         ps->performance_levels[i].pcie_lane;
3309                                 if (data->pcie_lane_performance.min >
3310                                                 ps->performance_levels[i].pcie_lane)
3311                                         data->pcie_lane_performance.min =
3312                                                         ps->performance_levels[i].pcie_lane;
3313                         }
3314                         break;
3315                 case PP_StateUILabel_Battery:
3316                         data->use_pcie_power_saving_levels = true;
3317
3318                         for (i = 0; i < ps->performance_level_count; i++) {
3319                                 if (data->pcie_gen_power_saving.max <
3320                                                 ps->performance_levels[i].pcie_gen)
3321                                         data->pcie_gen_power_saving.max =
3322                                                         ps->performance_levels[i].pcie_gen;
3323
3324                                 if (data->pcie_gen_power_saving.min >
3325                                                 ps->performance_levels[i].pcie_gen)
3326                                         data->pcie_gen_power_saving.min =
3327                                                         ps->performance_levels[i].pcie_gen;
3328
3329                                 if (data->pcie_lane_power_saving.max <
3330                                                 ps->performance_levels[i].pcie_lane)
3331                                         data->pcie_lane_power_saving.max =
3332                                                         ps->performance_levels[i].pcie_lane;
3333
3334                                 if (data->pcie_lane_power_saving.min >
3335                                                 ps->performance_levels[i].pcie_lane)
3336                                         data->pcie_lane_power_saving.min =
3337                                                         ps->performance_levels[i].pcie_lane;
3338                         }
3339                         break;
3340                 default:
3341                         break;
3342                 }
3343         }
3344         return 0;
3345 }
3346
3347 static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr,
3348                                         struct pp_hw_power_state *power_state,
3349                                         unsigned int index, const void *clock_info)
3350 {
3351         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3352         struct smu7_power_state  *ps = cast_phw_smu7_power_state(power_state);
3353         const ATOM_PPLIB_CI_CLOCK_INFO *visland_clk_info = clock_info;
3354         struct smu7_performance_level *performance_level;
3355         uint32_t engine_clock, memory_clock;
3356         uint16_t pcie_gen_from_bios;
3357
3358         engine_clock = visland_clk_info->ucEngineClockHigh << 16 | visland_clk_info->usEngineClockLow;
3359         memory_clock = visland_clk_info->ucMemoryClockHigh << 16 | visland_clk_info->usMemoryClockLow;
3360
3361         if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk)
3362                 data->highest_mclk = memory_clock;
3363
3364         PP_ASSERT_WITH_CODE(
3365                         (ps->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
3366                         "Performance levels exceeds SMC limit!",
3367                         return -EINVAL);
3368
3369         PP_ASSERT_WITH_CODE(
3370                         (ps->performance_level_count <
3371                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3372                         "Performance levels exceeds Driver limit, Skip!",
3373                         return 0);
3374
3375         performance_level = &(ps->performance_levels
3376                         [ps->performance_level_count++]);
3377
3378         /* Performance levels are arranged from low to high. */
3379         performance_level->memory_clock = memory_clock;
3380         performance_level->engine_clock = engine_clock;
3381
3382         pcie_gen_from_bios = visland_clk_info->ucPCIEGen;
3383
3384         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, pcie_gen_from_bios);
3385         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, visland_clk_info->usPCIELane);
3386
3387         return 0;
3388 }
3389
3390 static int smu7_get_pp_table_entry_v0(struct pp_hwmgr *hwmgr,
3391                 unsigned long entry_index, struct pp_power_state *state)
3392 {
3393         int result;
3394         struct smu7_power_state *ps;
3395         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3396         struct phm_clock_voltage_dependency_table *dep_mclk_table =
3397                         hwmgr->dyn_state.vddci_dependency_on_mclk;
3398
3399         memset(&state->hardware, 0x00, sizeof(struct pp_hw_power_state));
3400
3401         state->hardware.magic = PHM_VIslands_Magic;
3402
3403         ps = (struct smu7_power_state *)(&state->hardware);
3404
3405         result = pp_tables_get_entry(hwmgr, entry_index, state,
3406                         smu7_get_pp_table_entry_callback_func_v0);
3407
3408         /*
3409          * This is the earliest time we have all the dependency table
3410          * and the VBIOS boot state as
3411          * PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot
3412          * state if there is only one VDDCI/MCLK level, check if it's
3413          * the same as VBIOS boot state
3414          */
3415         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3416                 if (dep_mclk_table->entries[0].clk !=
3417                                 data->vbios_boot_state.mclk_bootup_value)
3418                         pr_debug("Single MCLK entry VDDCI/MCLK dependency table "
3419                                         "does not match VBIOS boot MCLK level");
3420                 if (dep_mclk_table->entries[0].v !=
3421                                 data->vbios_boot_state.vddci_bootup_value)
3422                         pr_debug("Single VDDCI entry VDDCI/MCLK dependency table "
3423                                         "does not match VBIOS boot VDDCI level");
3424         }
3425
3426         /* set DC compatible flag if this state supports DC */
3427         if (!state->validation.disallowOnDC)
3428                 ps->dc_compatible = true;
3429
3430         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3431                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3432
3433         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3434         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3435
3436         if (!result) {
3437                 uint32_t i;
3438
3439                 switch (state->classification.ui_label) {
3440                 case PP_StateUILabel_Performance:
3441                         data->use_pcie_performance_levels = true;
3442
3443                         for (i = 0; i < ps->performance_level_count; i++) {
3444                                 if (data->pcie_gen_performance.max <
3445                                                 ps->performance_levels[i].pcie_gen)
3446                                         data->pcie_gen_performance.max =
3447                                                         ps->performance_levels[i].pcie_gen;
3448
3449                                 if (data->pcie_gen_performance.min >
3450                                                 ps->performance_levels[i].pcie_gen)
3451                                         data->pcie_gen_performance.min =
3452                                                         ps->performance_levels[i].pcie_gen;
3453
3454                                 if (data->pcie_lane_performance.max <
3455                                                 ps->performance_levels[i].pcie_lane)
3456                                         data->pcie_lane_performance.max =
3457                                                         ps->performance_levels[i].pcie_lane;
3458
3459                                 if (data->pcie_lane_performance.min >
3460                                                 ps->performance_levels[i].pcie_lane)
3461                                         data->pcie_lane_performance.min =
3462                                                         ps->performance_levels[i].pcie_lane;
3463                         }
3464                         break;
3465                 case PP_StateUILabel_Battery:
3466                         data->use_pcie_power_saving_levels = true;
3467
3468                         for (i = 0; i < ps->performance_level_count; i++) {
3469                                 if (data->pcie_gen_power_saving.max <
3470                                                 ps->performance_levels[i].pcie_gen)
3471                                         data->pcie_gen_power_saving.max =
3472                                                         ps->performance_levels[i].pcie_gen;
3473
3474                                 if (data->pcie_gen_power_saving.min >
3475                                                 ps->performance_levels[i].pcie_gen)
3476                                         data->pcie_gen_power_saving.min =
3477                                                         ps->performance_levels[i].pcie_gen;
3478
3479                                 if (data->pcie_lane_power_saving.max <
3480                                                 ps->performance_levels[i].pcie_lane)
3481                                         data->pcie_lane_power_saving.max =
3482                                                         ps->performance_levels[i].pcie_lane;
3483
3484                                 if (data->pcie_lane_power_saving.min >
3485                                                 ps->performance_levels[i].pcie_lane)
3486                                         data->pcie_lane_power_saving.min =
3487                                                         ps->performance_levels[i].pcie_lane;
3488                         }
3489                         break;
3490                 default:
3491                         break;
3492                 }
3493         }
3494         return 0;
3495 }
3496
3497 static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3498                 unsigned long entry_index, struct pp_power_state *state)
3499 {
3500         if (hwmgr->pp_table_version == PP_TABLE_V0)
3501                 return smu7_get_pp_table_entry_v0(hwmgr, entry_index, state);
3502         else if (hwmgr->pp_table_version == PP_TABLE_V1)
3503                 return smu7_get_pp_table_entry_v1(hwmgr, entry_index, state);
3504
3505         return 0;
3506 }
3507
3508 static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query)
3509 {
3510         struct amdgpu_device *adev = hwmgr->adev;
3511         int i;
3512         u32 tmp = 0;
3513
3514         if (!query)
3515                 return -EINVAL;
3516
3517         /*
3518          * PPSMC_MSG_GetCurrPkgPwr is not supported on:
3519          *  - Hawaii
3520          *  - Bonaire
3521          *  - Fiji
3522          *  - Tonga
3523          */
3524         if ((adev->asic_type != CHIP_HAWAII) &&
3525             (adev->asic_type != CHIP_BONAIRE) &&
3526             (adev->asic_type != CHIP_FIJI) &&
3527             (adev->asic_type != CHIP_TONGA)) {
3528                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0, &tmp);
3529                 *query = tmp;
3530
3531                 if (tmp != 0)
3532                         return 0;
3533         }
3534
3535         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart, NULL);
3536         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3537                                                         ixSMU_PM_STATUS_95, 0);
3538
3539         for (i = 0; i < 10; i++) {
3540                 msleep(500);
3541                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample, NULL);
3542                 tmp = cgs_read_ind_register(hwmgr->device,
3543                                                 CGS_IND_REG__SMC,
3544                                                 ixSMU_PM_STATUS_95);
3545                 if (tmp != 0)
3546                         break;
3547         }
3548         *query = tmp;
3549
3550         return 0;
3551 }
3552
3553 static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx,
3554                             void *value, int *size)
3555 {
3556         uint32_t sclk, mclk, activity_percent;
3557         uint32_t offset, val_vid;
3558         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3559
3560         /* size must be at least 4 bytes for all sensors */
3561         if (*size < 4)
3562                 return -EINVAL;
3563
3564         switch (idx) {
3565         case AMDGPU_PP_SENSOR_GFX_SCLK:
3566                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency, &sclk);
3567                 *((uint32_t *)value) = sclk;
3568                 *size = 4;
3569                 return 0;
3570         case AMDGPU_PP_SENSOR_GFX_MCLK:
3571                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency, &mclk);
3572                 *((uint32_t *)value) = mclk;
3573                 *size = 4;
3574                 return 0;
3575         case AMDGPU_PP_SENSOR_GPU_LOAD:
3576         case AMDGPU_PP_SENSOR_MEM_LOAD:
3577                 offset = data->soft_regs_start + smum_get_offsetof(hwmgr,
3578                                                                 SMU_SoftRegisters,
3579                                                                 (idx == AMDGPU_PP_SENSOR_GPU_LOAD) ?
3580                                                                 AverageGraphicsActivity:
3581                                                                 AverageMemoryActivity);
3582
3583                 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3584                 activity_percent += 0x80;
3585                 activity_percent >>= 8;
3586                 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
3587                 *size = 4;
3588                 return 0;
3589         case AMDGPU_PP_SENSOR_GPU_TEMP:
3590                 *((uint32_t *)value) = smu7_thermal_get_temperature(hwmgr);
3591                 *size = 4;
3592                 return 0;
3593         case AMDGPU_PP_SENSOR_UVD_POWER:
3594                 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
3595                 *size = 4;
3596                 return 0;
3597         case AMDGPU_PP_SENSOR_VCE_POWER:
3598                 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
3599                 *size = 4;
3600                 return 0;
3601         case AMDGPU_PP_SENSOR_GPU_POWER:
3602                 return smu7_get_gpu_power(hwmgr, (uint32_t *)value);
3603         case AMDGPU_PP_SENSOR_VDDGFX:
3604                 if ((data->vr_config & VRCONF_VDDGFX_MASK) ==
3605                     (VR_SVI2_PLANE_2 << VRCONF_VDDGFX_SHIFT))
3606                         val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
3607                                         CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE2_VID);
3608                 else
3609                         val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
3610                                         CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE1_VID);
3611
3612                 *((uint32_t *)value) = (uint32_t)convert_to_vddc(val_vid);
3613                 return 0;
3614         default:
3615                 return -EINVAL;
3616         }
3617 }
3618
3619 static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3620 {
3621         const struct phm_set_power_state_input *states =
3622                         (const struct phm_set_power_state_input *)input;
3623         const struct smu7_power_state *smu7_ps =
3624                         cast_const_phw_smu7_power_state(states->pnew_state);
3625         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3626         struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
3627         uint32_t sclk = smu7_ps->performance_levels
3628                         [smu7_ps->performance_level_count - 1].engine_clock;
3629         struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
3630         uint32_t mclk = smu7_ps->performance_levels
3631                         [smu7_ps->performance_level_count - 1].memory_clock;
3632         struct PP_Clocks min_clocks = {0};
3633         uint32_t i;
3634
3635         for (i = 0; i < sclk_table->count; i++) {
3636                 if (sclk == sclk_table->dpm_levels[i].value)
3637                         break;
3638         }
3639
3640         if (i >= sclk_table->count) {
3641                 if (sclk > sclk_table->dpm_levels[i-1].value) {
3642                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3643                         sclk_table->dpm_levels[i-1].value = sclk;
3644                 }
3645         } else {
3646         /* TODO: Check SCLK in DAL's minimum clocks
3647          * in case DeepSleep divider update is required.
3648          */
3649                 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3650                         (min_clocks.engineClockInSR >= SMU7_MINIMUM_ENGINE_CLOCK ||
3651                                 data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
3652                         data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3653         }
3654
3655         for (i = 0; i < mclk_table->count; i++) {
3656                 if (mclk == mclk_table->dpm_levels[i].value)
3657                         break;
3658         }
3659
3660         if (i >= mclk_table->count) {
3661                 if (mclk > mclk_table->dpm_levels[i-1].value) {
3662                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3663                         mclk_table->dpm_levels[i-1].value = mclk;
3664                 }
3665         }
3666
3667         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
3668                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3669
3670         return 0;
3671 }
3672
3673 static uint16_t smu7_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
3674                 const struct smu7_power_state *smu7_ps)
3675 {
3676         uint32_t i;
3677         uint32_t sclk, max_sclk = 0;
3678         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3679         struct smu7_dpm_table *dpm_table = &data->dpm_table;
3680
3681         for (i = 0; i < smu7_ps->performance_level_count; i++) {
3682                 sclk = smu7_ps->performance_levels[i].engine_clock;
3683                 if (max_sclk < sclk)
3684                         max_sclk = sclk;
3685         }
3686
3687         for (i = 0; i < dpm_table->sclk_table.count; i++) {
3688                 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
3689                         return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
3690                                         dpm_table->pcie_speed_table.dpm_levels
3691                                         [dpm_table->pcie_speed_table.count - 1].value :
3692                                         dpm_table->pcie_speed_table.dpm_levels[i].value);
3693         }
3694
3695         return 0;
3696 }
3697
3698 static int smu7_request_link_speed_change_before_state_change(
3699                 struct pp_hwmgr *hwmgr, const void *input)
3700 {
3701         const struct phm_set_power_state_input *states =
3702                         (const struct phm_set_power_state_input *)input;
3703         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3704         const struct smu7_power_state *smu7_nps =
3705                         cast_const_phw_smu7_power_state(states->pnew_state);
3706         const struct smu7_power_state *polaris10_cps =
3707                         cast_const_phw_smu7_power_state(states->pcurrent_state);
3708
3709         uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_nps);
3710         uint16_t current_link_speed;
3711
3712         if (data->force_pcie_gen == PP_PCIEGenInvalid)
3713                 current_link_speed = smu7_get_maximum_link_speed(hwmgr, polaris10_cps);
3714         else
3715                 current_link_speed = data->force_pcie_gen;
3716
3717         data->force_pcie_gen = PP_PCIEGenInvalid;
3718         data->pspp_notify_required = false;
3719
3720         if (target_link_speed > current_link_speed) {
3721                 switch (target_link_speed) {
3722 #ifdef CONFIG_ACPI
3723                 case PP_PCIEGen3:
3724                         if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN3, false))
3725                                 break;
3726                         data->force_pcie_gen = PP_PCIEGen2;
3727                         if (current_link_speed == PP_PCIEGen2)
3728                                 break;
3729                         fallthrough;
3730                 case PP_PCIEGen2:
3731                         if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN2, false))
3732                                 break;
3733                         fallthrough;
3734 #endif
3735                 default:
3736                         data->force_pcie_gen = smu7_get_current_pcie_speed(hwmgr);
3737                         break;
3738                 }
3739         } else {
3740                 if (target_link_speed < current_link_speed)
3741                         data->pspp_notify_required = true;
3742         }
3743
3744         return 0;
3745 }
3746
3747 static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3748 {
3749         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3750
3751         if (0 == data->need_update_smu7_dpm_table)
3752                 return 0;
3753
3754         if ((0 == data->sclk_dpm_key_disabled) &&
3755                 (data->need_update_smu7_dpm_table &
3756                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
3757                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3758                                 "Trying to freeze SCLK DPM when DPM is disabled",
3759                                 );
3760                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3761                                 PPSMC_MSG_SCLKDPM_FreezeLevel,
3762                                 NULL),
3763                                 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
3764                                 return -EINVAL);
3765         }
3766
3767         if ((0 == data->mclk_dpm_key_disabled) &&
3768                 (data->need_update_smu7_dpm_table &
3769                  DPMTABLE_OD_UPDATE_MCLK)) {
3770                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3771                                 "Trying to freeze MCLK DPM when DPM is disabled",
3772                                 );
3773                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3774                                 PPSMC_MSG_MCLKDPM_FreezeLevel,
3775                                 NULL),
3776                                 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
3777                                 return -EINVAL);
3778         }
3779
3780         return 0;
3781 }
3782
3783 static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
3784                 struct pp_hwmgr *hwmgr, const void *input)
3785 {
3786         int result = 0;
3787         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3788         struct smu7_dpm_table *dpm_table = &data->dpm_table;
3789         uint32_t count;
3790         struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
3791         struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
3792         struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
3793
3794         if (0 == data->need_update_smu7_dpm_table)
3795                 return 0;
3796
3797         if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3798                 for (count = 0; count < dpm_table->sclk_table.count; count++) {
3799                         dpm_table->sclk_table.dpm_levels[count].enabled = odn_sclk_table->entries[count].enabled;
3800                         dpm_table->sclk_table.dpm_levels[count].value = odn_sclk_table->entries[count].clock;
3801                 }
3802         }
3803
3804         if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3805                 for (count = 0; count < dpm_table->mclk_table.count; count++) {
3806                         dpm_table->mclk_table.dpm_levels[count].enabled = odn_mclk_table->entries[count].enabled;
3807                         dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock;
3808                 }
3809         }
3810
3811         if (data->need_update_smu7_dpm_table &
3812                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
3813                 result = smum_populate_all_graphic_levels(hwmgr);
3814                 PP_ASSERT_WITH_CODE((0 == result),
3815                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
3816                                 return result);
3817         }
3818
3819         if (data->need_update_smu7_dpm_table &
3820                         (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
3821                 /*populate MCLK dpm table to SMU7 */
3822                 result = smum_populate_all_memory_levels(hwmgr);
3823                 PP_ASSERT_WITH_CODE((0 == result),
3824                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
3825                                 return result);
3826         }
3827
3828         return result;
3829 }
3830
3831 static int smu7_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
3832                           struct smu7_single_dpm_table *dpm_table,
3833                         uint32_t low_limit, uint32_t high_limit)
3834 {
3835         uint32_t i;
3836
3837         /* force the trim if mclk_switching is disabled to prevent flicker */
3838         bool force_trim = (low_limit == high_limit);
3839         for (i = 0; i < dpm_table->count; i++) {
3840         /*skip the trim if od is enabled*/
3841                 if ((!hwmgr->od_enabled || force_trim)
3842                         && (dpm_table->dpm_levels[i].value < low_limit
3843                         || dpm_table->dpm_levels[i].value > high_limit))
3844                         dpm_table->dpm_levels[i].enabled = false;
3845                 else
3846                         dpm_table->dpm_levels[i].enabled = true;
3847         }
3848
3849         return 0;
3850 }
3851
3852 static int smu7_trim_dpm_states(struct pp_hwmgr *hwmgr,
3853                 const struct smu7_power_state *smu7_ps)
3854 {
3855         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3856         uint32_t high_limit_count;
3857
3858         PP_ASSERT_WITH_CODE((smu7_ps->performance_level_count >= 1),
3859                         "power state did not have any performance level",
3860                         return -EINVAL);
3861
3862         high_limit_count = (1 == smu7_ps->performance_level_count) ? 0 : 1;
3863
3864         smu7_trim_single_dpm_states(hwmgr,
3865                         &(data->dpm_table.sclk_table),
3866                         smu7_ps->performance_levels[0].engine_clock,
3867                         smu7_ps->performance_levels[high_limit_count].engine_clock);
3868
3869         smu7_trim_single_dpm_states(hwmgr,
3870                         &(data->dpm_table.mclk_table),
3871                         smu7_ps->performance_levels[0].memory_clock,
3872                         smu7_ps->performance_levels[high_limit_count].memory_clock);
3873
3874         return 0;
3875 }
3876
3877 static int smu7_generate_dpm_level_enable_mask(
3878                 struct pp_hwmgr *hwmgr, const void *input)
3879 {
3880         int result = 0;
3881         const struct phm_set_power_state_input *states =
3882                         (const struct phm_set_power_state_input *)input;
3883         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3884         const struct smu7_power_state *smu7_ps =
3885                         cast_const_phw_smu7_power_state(states->pnew_state);
3886
3887
3888         result = smu7_trim_dpm_states(hwmgr, smu7_ps);
3889         if (result)
3890                 return result;
3891
3892         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
3893                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
3894         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
3895                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
3896         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
3897                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
3898
3899         return 0;
3900 }
3901
3902 static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3903 {
3904         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3905
3906         if (0 == data->need_update_smu7_dpm_table)
3907                 return 0;
3908
3909         if ((0 == data->sclk_dpm_key_disabled) &&
3910                 (data->need_update_smu7_dpm_table &
3911                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
3912
3913                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3914                                 "Trying to Unfreeze SCLK DPM when DPM is disabled",
3915                                 );
3916                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3917                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel,
3918                                 NULL),
3919                         "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
3920                         return -EINVAL);
3921         }
3922
3923         if ((0 == data->mclk_dpm_key_disabled) &&
3924                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
3925
3926                 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3927                                 "Trying to Unfreeze MCLK DPM when DPM is disabled",
3928                                 );
3929                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3930                                 PPSMC_MSG_MCLKDPM_UnfreezeLevel,
3931                                 NULL),
3932                     "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
3933                     return -EINVAL);
3934         }
3935
3936         data->need_update_smu7_dpm_table &= DPMTABLE_OD_UPDATE_VDDC;
3937
3938         return 0;
3939 }
3940
3941 static int smu7_notify_link_speed_change_after_state_change(
3942                 struct pp_hwmgr *hwmgr, const void *input)
3943 {
3944         const struct phm_set_power_state_input *states =
3945                         (const struct phm_set_power_state_input *)input;
3946         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3947         const struct smu7_power_state *smu7_ps =
3948                         cast_const_phw_smu7_power_state(states->pnew_state);
3949         uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_ps);
3950         uint8_t  request;
3951
3952         if (data->pspp_notify_required) {
3953                 if (target_link_speed == PP_PCIEGen3)
3954                         request = PCIE_PERF_REQ_GEN3;
3955                 else if (target_link_speed == PP_PCIEGen2)
3956                         request = PCIE_PERF_REQ_GEN2;
3957                 else
3958                         request = PCIE_PERF_REQ_GEN1;
3959
3960                 if (request == PCIE_PERF_REQ_GEN1 &&
3961                                 smu7_get_current_pcie_speed(hwmgr) > 0)
3962                         return 0;
3963
3964 #ifdef CONFIG_ACPI
3965                 if (amdgpu_acpi_pcie_performance_request(hwmgr->adev, request, false)) {
3966                         if (PP_PCIEGen2 == target_link_speed)
3967                                 pr_info("PSPP request to switch to Gen2 from Gen3 Failed!");
3968                         else
3969                                 pr_info("PSPP request to switch to Gen1 from Gen2 Failed!");
3970                 }
3971 #endif
3972         }
3973
3974         return 0;
3975 }
3976
3977 static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr)
3978 {
3979         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3980
3981         if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) {
3982                 if (hwmgr->chip_id == CHIP_VEGAM)
3983                         smum_send_msg_to_smc_with_parameter(hwmgr,
3984                                         (PPSMC_Msg)PPSMC_MSG_SetVBITimeout_VEGAM, data->frame_time_x2,
3985                                         NULL);
3986                 else
3987                         smum_send_msg_to_smc_with_parameter(hwmgr,
3988                                         (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2,
3989                                         NULL);
3990         }
3991         return (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_HasDisplay, NULL) == 0) ?  0 : -EINVAL;
3992 }
3993
3994 static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
3995 {
3996         int tmp_result, result = 0;
3997         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3998
3999         tmp_result = smu7_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4000         PP_ASSERT_WITH_CODE((0 == tmp_result),
4001                         "Failed to find DPM states clocks in DPM table!",
4002                         result = tmp_result);
4003
4004         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4005                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4006                 tmp_result =
4007                         smu7_request_link_speed_change_before_state_change(hwmgr, input);
4008                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4009                                 "Failed to request link speed change before state change!",
4010                                 result = tmp_result);
4011         }
4012
4013         tmp_result = smu7_freeze_sclk_mclk_dpm(hwmgr);
4014         PP_ASSERT_WITH_CODE((0 == tmp_result),
4015                         "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4016
4017         tmp_result = smu7_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4018         PP_ASSERT_WITH_CODE((0 == tmp_result),
4019                         "Failed to populate and upload SCLK MCLK DPM levels!",
4020                         result = tmp_result);
4021
4022         /*
4023          * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag.
4024          * That effectively disables AVFS feature.
4025          */
4026         if (hwmgr->hardcode_pp_table != NULL)
4027                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
4028
4029         tmp_result = smu7_update_avfs(hwmgr);
4030         PP_ASSERT_WITH_CODE((0 == tmp_result),
4031                         "Failed to update avfs voltages!",
4032                         result = tmp_result);
4033
4034         tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input);
4035         PP_ASSERT_WITH_CODE((0 == tmp_result),
4036                         "Failed to generate DPM level enabled mask!",
4037                         result = tmp_result);
4038
4039         tmp_result = smum_update_sclk_threshold(hwmgr);
4040         PP_ASSERT_WITH_CODE((0 == tmp_result),
4041                         "Failed to update SCLK threshold!",
4042                         result = tmp_result);
4043
4044         tmp_result = smu7_notify_smc_display(hwmgr);
4045         PP_ASSERT_WITH_CODE((0 == tmp_result),
4046                         "Failed to notify smc display settings!",
4047                         result = tmp_result);
4048
4049         tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr);
4050         PP_ASSERT_WITH_CODE((0 == tmp_result),
4051                         "Failed to unfreeze SCLK MCLK DPM!",
4052                         result = tmp_result);
4053
4054         tmp_result = smu7_upload_dpm_level_enable_mask(hwmgr);
4055         PP_ASSERT_WITH_CODE((0 == tmp_result),
4056                         "Failed to upload DPM level enabled mask!",
4057                         result = tmp_result);
4058
4059         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4060                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4061                 tmp_result =
4062                         smu7_notify_link_speed_change_after_state_change(hwmgr, input);
4063                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4064                                 "Failed to notify link speed change after state change!",
4065                                 result = tmp_result);
4066         }
4067         data->apply_optimized_settings = false;
4068         return result;
4069 }
4070
4071 static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4072 {
4073         hwmgr->thermal_controller.
4074         advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4075
4076         return smum_send_msg_to_smc_with_parameter(hwmgr,
4077                         PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm,
4078                         NULL);
4079 }
4080
4081 static int
4082 smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
4083 {
4084         PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4085
4086         return (smum_send_msg_to_smc(hwmgr, msg, NULL) == 0) ?  0 : -1;
4087 }
4088
4089 static int
4090 smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4091 {
4092         if (hwmgr->display_config->num_display > 1 &&
4093                         !hwmgr->display_config->multi_monitor_in_sync)
4094                 smu7_notify_smc_display_change(hwmgr, false);
4095
4096         return 0;
4097 }
4098
4099 /**
4100 * Programs the display gap
4101 *
4102 * @param    hwmgr  the address of the powerplay hardware manager.
4103 * @return   always OK
4104 */
4105 static int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
4106 {
4107         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4108         uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4109         uint32_t display_gap2;
4110         uint32_t pre_vbi_time_in_us;
4111         uint32_t frame_time_in_us;
4112         uint32_t ref_clock, refresh_rate;
4113
4114         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->num_display > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4115         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4116
4117         ref_clock =  amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
4118         refresh_rate = hwmgr->display_config->vrefresh;
4119
4120         if (0 == refresh_rate)
4121                 refresh_rate = 60;
4122
4123         frame_time_in_us = 1000000 / refresh_rate;
4124
4125         pre_vbi_time_in_us = frame_time_in_us - 200 - hwmgr->display_config->min_vblank_time;
4126
4127         data->frame_time_x2 = frame_time_in_us * 2 / 100;
4128
4129         if (data->frame_time_x2 < 280) {
4130                 pr_debug("%s: enforce minimal VBITimeout: %d -> 280\n", __func__, data->frame_time_x2);
4131                 data->frame_time_x2 = 280;
4132         }
4133
4134         display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4135
4136         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4137
4138         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4139                         data->soft_regs_start + smum_get_offsetof(hwmgr,
4140                                                         SMU_SoftRegisters,
4141                                                         PreVBlankGap), 0x64);
4142
4143         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4144                         data->soft_regs_start + smum_get_offsetof(hwmgr,
4145                                                         SMU_SoftRegisters,
4146                                                         VBlankTimeout),
4147                                         (frame_time_in_us - pre_vbi_time_in_us));
4148
4149         return 0;
4150 }
4151
4152 static int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4153 {
4154         return smu7_program_display_gap(hwmgr);
4155 }
4156
4157 /**
4158 *  Set maximum target operating fan output RPM
4159 *
4160 * @param    hwmgr:  the address of the powerplay hardware manager.
4161 * @param    usMaxFanRpm:  max operating fan RPM value.
4162 * @return   The response that came from the SMC.
4163 */
4164 static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4165 {
4166         hwmgr->thermal_controller.
4167         advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4168
4169         return smum_send_msg_to_smc_with_parameter(hwmgr,
4170                         PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm,
4171                         NULL);
4172 }
4173
4174 static const struct amdgpu_irq_src_funcs smu7_irq_funcs = {
4175         .process = phm_irq_process,
4176 };
4177
4178 static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr)
4179 {
4180         struct amdgpu_irq_src *source =
4181                 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
4182
4183         if (!source)
4184                 return -ENOMEM;
4185
4186         source->funcs = &smu7_irq_funcs;
4187
4188         amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
4189                         AMDGPU_IRQ_CLIENTID_LEGACY,
4190                         VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH,
4191                         source);
4192         amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
4193                         AMDGPU_IRQ_CLIENTID_LEGACY,
4194                         VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW,
4195                         source);
4196
4197         /* Register CTF(GPIO_19) interrupt */
4198         amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
4199                         AMDGPU_IRQ_CLIENTID_LEGACY,
4200                         VISLANDS30_IV_SRCID_GPIO_19,
4201                         source);
4202
4203         return 0;
4204 }
4205
4206 static bool
4207 smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4208 {
4209         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4210         bool is_update_required = false;
4211
4212         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
4213                 is_update_required = true;
4214
4215         if (data->display_timing.vrefresh != hwmgr->display_config->vrefresh)
4216                 is_update_required = true;
4217
4218         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4219                 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr &&
4220                         (data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK ||
4221                         hwmgr->display_config->min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
4222                         is_update_required = true;
4223         }
4224         return is_update_required;
4225 }
4226
4227 static inline bool smu7_are_power_levels_equal(const struct smu7_performance_level *pl1,
4228                                                            const struct smu7_performance_level *pl2)
4229 {
4230         return ((pl1->memory_clock == pl2->memory_clock) &&
4231                   (pl1->engine_clock == pl2->engine_clock) &&
4232                   (pl1->pcie_gen == pl2->pcie_gen) &&
4233                   (pl1->pcie_lane == pl2->pcie_lane));
4234 }
4235
4236 static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
4237                 const struct pp_hw_power_state *pstate1,
4238                 const struct pp_hw_power_state *pstate2, bool *equal)
4239 {
4240         const struct smu7_power_state *psa;
4241         const struct smu7_power_state *psb;
4242         int i;
4243         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4244
4245         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4246                 return -EINVAL;
4247
4248         psa = cast_const_phw_smu7_power_state(pstate1);
4249         psb = cast_const_phw_smu7_power_state(pstate2);
4250         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4251         if (psa->performance_level_count != psb->performance_level_count) {
4252                 *equal = false;
4253                 return 0;
4254         }
4255
4256         for (i = 0; i < psa->performance_level_count; i++) {
4257                 if (!smu7_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4258                         /* If we have found even one performance level pair that is different the states are different. */
4259                         *equal = false;
4260                         return 0;
4261                 }
4262         }
4263
4264         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4265         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4266         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4267         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4268         /* For OD call, set value based on flag */
4269         *equal &= !(data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK |
4270                                                         DPMTABLE_OD_UPDATE_MCLK |
4271                                                         DPMTABLE_OD_UPDATE_VDDC));
4272
4273         return 0;
4274 }
4275
4276 static int smu7_check_mc_firmware(struct pp_hwmgr *hwmgr)
4277 {
4278         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4279
4280         uint32_t tmp;
4281
4282         /* Read MC indirect register offset 0x9F bits [3:0] to see
4283          * if VBIOS has already loaded a full version of MC ucode
4284          * or not.
4285          */
4286
4287         smu7_get_mc_microcode_version(hwmgr);
4288
4289         data->need_long_memory_training = false;
4290
4291         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX,
4292                                                         ixMC_IO_DEBUG_UP_13);
4293         tmp = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
4294
4295         if (tmp & (1 << 23)) {
4296                 data->mem_latency_high = MEM_LATENCY_HIGH;
4297                 data->mem_latency_low = MEM_LATENCY_LOW;
4298                 if ((hwmgr->chip_id == CHIP_POLARIS10) ||
4299                     (hwmgr->chip_id == CHIP_POLARIS11) ||
4300                     (hwmgr->chip_id == CHIP_POLARIS12))
4301                         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableFFC, NULL);
4302         } else {
4303                 data->mem_latency_high = 330;
4304                 data->mem_latency_low = 330;
4305                 if ((hwmgr->chip_id == CHIP_POLARIS10) ||
4306                     (hwmgr->chip_id == CHIP_POLARIS11) ||
4307                     (hwmgr->chip_id == CHIP_POLARIS12))
4308                         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableFFC, NULL);
4309         }
4310
4311         return 0;
4312 }
4313
4314 static int smu7_read_clock_registers(struct pp_hwmgr *hwmgr)
4315 {
4316         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4317
4318         data->clock_registers.vCG_SPLL_FUNC_CNTL         =
4319                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL);
4320         data->clock_registers.vCG_SPLL_FUNC_CNTL_2       =
4321                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2);
4322         data->clock_registers.vCG_SPLL_FUNC_CNTL_3       =
4323                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3);
4324         data->clock_registers.vCG_SPLL_FUNC_CNTL_4       =
4325                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4);
4326         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM   =
4327                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM);
4328         data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
4329                 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2);
4330         data->clock_registers.vDLL_CNTL                  =
4331                 cgs_read_register(hwmgr->device, mmDLL_CNTL);
4332         data->clock_registers.vMCLK_PWRMGT_CNTL          =
4333                 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL);
4334         data->clock_registers.vMPLL_AD_FUNC_CNTL         =
4335                 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL);
4336         data->clock_registers.vMPLL_DQ_FUNC_CNTL         =
4337                 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL);
4338         data->clock_registers.vMPLL_FUNC_CNTL            =
4339                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL);
4340         data->clock_registers.vMPLL_FUNC_CNTL_1          =
4341                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1);
4342         data->clock_registers.vMPLL_FUNC_CNTL_2          =
4343                 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2);
4344         data->clock_registers.vMPLL_SS1                  =
4345                 cgs_read_register(hwmgr->device, mmMPLL_SS1);
4346         data->clock_registers.vMPLL_SS2                  =
4347                 cgs_read_register(hwmgr->device, mmMPLL_SS2);
4348         return 0;
4349
4350 }
4351
4352 /**
4353  * Find out if memory is GDDR5.
4354  *
4355  * @param    hwmgr  the address of the powerplay hardware manager.
4356  * @return   always 0
4357  */
4358 static int smu7_get_memory_type(struct pp_hwmgr *hwmgr)
4359 {
4360         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4361         struct amdgpu_device *adev = hwmgr->adev;
4362
4363         data->is_memory_gddr5 = (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5);
4364
4365         return 0;
4366 }
4367
4368 /**
4369  * Enables Dynamic Power Management by SMC
4370  *
4371  * @param    hwmgr  the address of the powerplay hardware manager.
4372  * @return   always 0
4373  */
4374 static int smu7_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4375 {
4376         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4377                         GENERAL_PWRMGT, STATIC_PM_EN, 1);
4378
4379         return 0;
4380 }
4381
4382 /**
4383  * Initialize PowerGating States for different engines
4384  *
4385  * @param    hwmgr  the address of the powerplay hardware manager.
4386  * @return   always 0
4387  */
4388 static int smu7_init_power_gate_state(struct pp_hwmgr *hwmgr)
4389 {
4390         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4391
4392         data->uvd_power_gated = false;
4393         data->vce_power_gated = false;
4394
4395         return 0;
4396 }
4397
4398 static int smu7_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4399 {
4400         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4401
4402         data->low_sclk_interrupt_threshold = 0;
4403         return 0;
4404 }
4405
4406 static int smu7_setup_asic_task(struct pp_hwmgr *hwmgr)
4407 {
4408         int tmp_result, result = 0;
4409
4410         smu7_check_mc_firmware(hwmgr);
4411
4412         tmp_result = smu7_read_clock_registers(hwmgr);
4413         PP_ASSERT_WITH_CODE((0 == tmp_result),
4414                         "Failed to read clock registers!", result = tmp_result);
4415
4416         tmp_result = smu7_get_memory_type(hwmgr);
4417         PP_ASSERT_WITH_CODE((0 == tmp_result),
4418                         "Failed to get memory type!", result = tmp_result);
4419
4420         tmp_result = smu7_enable_acpi_power_management(hwmgr);
4421         PP_ASSERT_WITH_CODE((0 == tmp_result),
4422                         "Failed to enable ACPI power management!", result = tmp_result);
4423
4424         tmp_result = smu7_init_power_gate_state(hwmgr);
4425         PP_ASSERT_WITH_CODE((0 == tmp_result),
4426                         "Failed to init power gate state!", result = tmp_result);
4427
4428         tmp_result = smu7_get_mc_microcode_version(hwmgr);
4429         PP_ASSERT_WITH_CODE((0 == tmp_result),
4430                         "Failed to get MC microcode version!", result = tmp_result);
4431
4432         tmp_result = smu7_init_sclk_threshold(hwmgr);
4433         PP_ASSERT_WITH_CODE((0 == tmp_result),
4434                         "Failed to init sclk threshold!", result = tmp_result);
4435
4436         return result;
4437 }
4438
4439 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
4440                 enum pp_clock_type type, uint32_t mask)
4441 {
4442         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4443
4444         if (mask == 0)
4445                 return -EINVAL;
4446
4447         switch (type) {
4448         case PP_SCLK:
4449                 if (!data->sclk_dpm_key_disabled)
4450                         smum_send_msg_to_smc_with_parameter(hwmgr,
4451                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
4452                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask,
4453                                         NULL);
4454                 break;
4455         case PP_MCLK:
4456                 if (!data->mclk_dpm_key_disabled)
4457                         smum_send_msg_to_smc_with_parameter(hwmgr,
4458                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
4459                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask,
4460                                         NULL);
4461                 break;
4462         case PP_PCIE:
4463         {
4464                 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
4465
4466                 if (!data->pcie_dpm_key_disabled) {
4467                         if (fls(tmp) != ffs(tmp))
4468                                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PCIeDPM_UnForceLevel,
4469                                                 NULL);
4470                         else
4471                                 smum_send_msg_to_smc_with_parameter(hwmgr,
4472                                         PPSMC_MSG_PCIeDPM_ForceLevel,
4473                                         fls(tmp) - 1,
4474                                         NULL);
4475                 }
4476                 break;
4477         }
4478         default:
4479                 break;
4480         }
4481
4482         return 0;
4483 }
4484
4485 static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
4486                 enum pp_clock_type type, char *buf)
4487 {
4488         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4489         struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4490         struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4491         struct smu7_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
4492         struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
4493         struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
4494         struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
4495         int i, now, size = 0;
4496         uint32_t clock, pcie_speed;
4497
4498         switch (type) {
4499         case PP_SCLK:
4500                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency, &clock);
4501
4502                 for (i = 0; i < sclk_table->count; i++) {
4503                         if (clock > sclk_table->dpm_levels[i].value)
4504                                 continue;
4505                         break;
4506                 }
4507                 now = i;
4508
4509                 for (i = 0; i < sclk_table->count; i++)
4510                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4511                                         i, sclk_table->dpm_levels[i].value / 100,
4512                                         (i == now) ? "*" : "");
4513                 break;
4514         case PP_MCLK:
4515                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency, &clock);
4516
4517                 for (i = 0; i < mclk_table->count; i++) {
4518                         if (clock > mclk_table->dpm_levels[i].value)
4519                                 continue;
4520                         break;
4521                 }
4522                 now = i;
4523
4524                 for (i = 0; i < mclk_table->count; i++)
4525                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4526                                         i, mclk_table->dpm_levels[i].value / 100,
4527                                         (i == now) ? "*" : "");
4528                 break;
4529         case PP_PCIE:
4530                 pcie_speed = smu7_get_current_pcie_speed(hwmgr);
4531                 for (i = 0; i < pcie_table->count; i++) {
4532                         if (pcie_speed != pcie_table->dpm_levels[i].value)
4533                                 continue;
4534                         break;
4535                 }
4536                 now = i;
4537
4538                 for (i = 0; i < pcie_table->count; i++)
4539                         size += sprintf(buf + size, "%d: %s %s\n", i,
4540                                         (pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x8" :
4541                                         (pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" :
4542                                         (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "",
4543                                         (i == now) ? "*" : "");
4544                 break;
4545         case OD_SCLK:
4546                 if (hwmgr->od_enabled) {
4547                         size = sprintf(buf, "%s:\n", "OD_SCLK");
4548                         for (i = 0; i < odn_sclk_table->num_of_pl; i++)
4549                                 size += sprintf(buf + size, "%d: %10uMHz %10umV\n",
4550                                         i, odn_sclk_table->entries[i].clock/100,
4551                                         odn_sclk_table->entries[i].vddc);
4552                 }
4553                 break;
4554         case OD_MCLK:
4555                 if (hwmgr->od_enabled) {
4556                         size = sprintf(buf, "%s:\n", "OD_MCLK");
4557                         for (i = 0; i < odn_mclk_table->num_of_pl; i++)
4558                                 size += sprintf(buf + size, "%d: %10uMHz %10umV\n",
4559                                         i, odn_mclk_table->entries[i].clock/100,
4560                                         odn_mclk_table->entries[i].vddc);
4561                 }
4562                 break;
4563         case OD_RANGE:
4564                 if (hwmgr->od_enabled) {
4565                         size = sprintf(buf, "%s:\n", "OD_RANGE");
4566                         size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
4567                                 data->golden_dpm_table.sclk_table.dpm_levels[0].value/100,
4568                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4569                         size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n",
4570                                 data->golden_dpm_table.mclk_table.dpm_levels[0].value/100,
4571                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4572                         size += sprintf(buf + size, "VDDC: %7umV %11umV\n",
4573                                 data->odn_dpm_table.min_vddc,
4574                                 data->odn_dpm_table.max_vddc);
4575                 }
4576                 break;
4577         default:
4578                 break;
4579         }
4580         return size;
4581 }
4582
4583 static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4584 {
4585         switch (mode) {
4586         case AMD_FAN_CTRL_NONE:
4587                 smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
4588                 break;
4589         case AMD_FAN_CTRL_MANUAL:
4590                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4591                         PHM_PlatformCaps_MicrocodeFanControl))
4592                         smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
4593                 break;
4594         case AMD_FAN_CTRL_AUTO:
4595                 if (!smu7_fan_ctrl_set_static_mode(hwmgr, mode))
4596                         smu7_fan_ctrl_start_smc_fan_control(hwmgr);
4597                 break;
4598         default:
4599                 break;
4600         }
4601 }
4602
4603 static uint32_t smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4604 {
4605         return hwmgr->fan_ctrl_enabled ? AMD_FAN_CTRL_AUTO : AMD_FAN_CTRL_MANUAL;
4606 }
4607
4608 static int smu7_get_sclk_od(struct pp_hwmgr *hwmgr)
4609 {
4610         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4611         struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4612         struct smu7_single_dpm_table *golden_sclk_table =
4613                         &(data->golden_dpm_table.sclk_table);
4614         int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
4615         int golden_value = golden_sclk_table->dpm_levels
4616                         [golden_sclk_table->count - 1].value;
4617
4618         value -= golden_value;
4619         value = DIV_ROUND_UP(value * 100, golden_value);
4620
4621         return value;
4622 }
4623
4624 static int smu7_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4625 {
4626         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4627         struct smu7_single_dpm_table *golden_sclk_table =
4628                         &(data->golden_dpm_table.sclk_table);
4629         struct pp_power_state  *ps;
4630         struct smu7_power_state  *smu7_ps;
4631
4632         if (value > 20)
4633                 value = 20;
4634
4635         ps = hwmgr->request_ps;
4636
4637         if (ps == NULL)
4638                 return -EINVAL;
4639
4640         smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
4641
4642         smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].engine_clock =
4643                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
4644                         value / 100 +
4645                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
4646
4647         return 0;
4648 }
4649
4650 static int smu7_get_mclk_od(struct pp_hwmgr *hwmgr)
4651 {
4652         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4653         struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4654         struct smu7_single_dpm_table *golden_mclk_table =
4655                         &(data->golden_dpm_table.mclk_table);
4656         int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
4657         int golden_value = golden_mclk_table->dpm_levels
4658                         [golden_mclk_table->count - 1].value;
4659
4660         value -= golden_value;
4661         value = DIV_ROUND_UP(value * 100, golden_value);
4662
4663         return value;
4664 }
4665
4666 static int smu7_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4667 {
4668         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4669         struct smu7_single_dpm_table *golden_mclk_table =
4670                         &(data->golden_dpm_table.mclk_table);
4671         struct pp_power_state  *ps;
4672         struct smu7_power_state  *smu7_ps;
4673
4674         if (value > 20)
4675                 value = 20;
4676
4677         ps = hwmgr->request_ps;
4678
4679         if (ps == NULL)
4680                 return -EINVAL;
4681
4682         smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
4683
4684         smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].memory_clock =
4685                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
4686                         value / 100 +
4687                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
4688
4689         return 0;
4690 }
4691
4692
4693 static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
4694 {
4695         struct phm_ppt_v1_information *table_info =
4696                         (struct phm_ppt_v1_information *)hwmgr->pptable;
4697         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = NULL;
4698         struct phm_clock_voltage_dependency_table *sclk_table;
4699         int i;
4700
4701         if (hwmgr->pp_table_version == PP_TABLE_V1) {
4702                 if (table_info == NULL || table_info->vdd_dep_on_sclk == NULL)
4703                         return -EINVAL;
4704                 dep_sclk_table = table_info->vdd_dep_on_sclk;
4705                 for (i = 0; i < dep_sclk_table->count; i++)
4706                         clocks->clock[i] = dep_sclk_table->entries[i].clk * 10;
4707                 clocks->count = dep_sclk_table->count;
4708         } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
4709                 sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
4710                 for (i = 0; i < sclk_table->count; i++)
4711                         clocks->clock[i] = sclk_table->entries[i].clk * 10;
4712                 clocks->count = sclk_table->count;
4713         }
4714
4715         return 0;
4716 }
4717
4718 static uint32_t smu7_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t clk)
4719 {
4720         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4721
4722         if (clk >= MEM_FREQ_LOW_LATENCY && clk < MEM_FREQ_HIGH_LATENCY)
4723                 return data->mem_latency_high;
4724         else if (clk >= MEM_FREQ_HIGH_LATENCY)
4725                 return data->mem_latency_low;
4726         else
4727                 return MEM_LATENCY_ERR;
4728 }
4729
4730 static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
4731 {
4732         struct phm_ppt_v1_information *table_info =
4733                         (struct phm_ppt_v1_information *)hwmgr->pptable;
4734         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
4735         int i;
4736         struct phm_clock_voltage_dependency_table *mclk_table;
4737
4738         if (hwmgr->pp_table_version == PP_TABLE_V1) {
4739                 if (table_info == NULL)
4740                         return -EINVAL;
4741                 dep_mclk_table = table_info->vdd_dep_on_mclk;
4742                 for (i = 0; i < dep_mclk_table->count; i++) {
4743                         clocks->clock[i] = dep_mclk_table->entries[i].clk * 10;
4744                         clocks->latency[i] = smu7_get_mem_latency(hwmgr,
4745                                                 dep_mclk_table->entries[i].clk);
4746                 }
4747                 clocks->count = dep_mclk_table->count;
4748         } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
4749                 mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
4750                 for (i = 0; i < mclk_table->count; i++)
4751                         clocks->clock[i] = mclk_table->entries[i].clk * 10;
4752                 clocks->count = mclk_table->count;
4753         }
4754         return 0;
4755 }
4756
4757 static int smu7_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
4758                                                 struct amd_pp_clocks *clocks)
4759 {
4760         switch (type) {
4761         case amd_pp_sys_clock:
4762                 smu7_get_sclks(hwmgr, clocks);
4763                 break;
4764         case amd_pp_mem_clock:
4765                 smu7_get_mclks(hwmgr, clocks);
4766                 break;
4767         default:
4768                 return -EINVAL;
4769         }
4770
4771         return 0;
4772 }
4773
4774 static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
4775                                         uint32_t virtual_addr_low,
4776                                         uint32_t virtual_addr_hi,
4777                                         uint32_t mc_addr_low,
4778                                         uint32_t mc_addr_hi,
4779                                         uint32_t size)
4780 {
4781         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4782
4783         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4784                                         data->soft_regs_start +
4785                                         smum_get_offsetof(hwmgr,
4786                                         SMU_SoftRegisters, DRAM_LOG_ADDR_H),
4787                                         mc_addr_hi);
4788
4789         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4790                                         data->soft_regs_start +
4791                                         smum_get_offsetof(hwmgr,
4792                                         SMU_SoftRegisters, DRAM_LOG_ADDR_L),
4793                                         mc_addr_low);
4794
4795         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4796                                         data->soft_regs_start +
4797                                         smum_get_offsetof(hwmgr,
4798                                         SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_H),
4799                                         virtual_addr_hi);
4800
4801         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4802                                         data->soft_regs_start +
4803                                         smum_get_offsetof(hwmgr,
4804                                         SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_L),
4805                                         virtual_addr_low);
4806
4807         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4808                                         data->soft_regs_start +
4809                                         smum_get_offsetof(hwmgr,
4810                                         SMU_SoftRegisters, DRAM_LOG_BUFF_SIZE),
4811                                         size);
4812         return 0;
4813 }
4814
4815 static int smu7_get_max_high_clocks(struct pp_hwmgr *hwmgr,
4816                                         struct amd_pp_simple_clock_info *clocks)
4817 {
4818         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4819         struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4820         struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4821
4822         if (clocks == NULL)
4823                 return -EINVAL;
4824
4825         clocks->memory_max_clock = mclk_table->count > 1 ?
4826                                 mclk_table->dpm_levels[mclk_table->count-1].value :
4827                                 mclk_table->dpm_levels[0].value;
4828         clocks->engine_max_clock = sclk_table->count > 1 ?
4829                                 sclk_table->dpm_levels[sclk_table->count-1].value :
4830                                 sclk_table->dpm_levels[0].value;
4831         return 0;
4832 }
4833
4834 static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
4835                 struct PP_TemperatureRange *thermal_data)
4836 {
4837         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4838         struct phm_ppt_v1_information *table_info =
4839                         (struct phm_ppt_v1_information *)hwmgr->pptable;
4840
4841         memcpy(thermal_data, &SMU7ThermalPolicy[0], sizeof(struct PP_TemperatureRange));
4842
4843         if (hwmgr->pp_table_version == PP_TABLE_V1)
4844                 thermal_data->max = table_info->cac_dtp_table->usSoftwareShutdownTemp *
4845                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4846         else if (hwmgr->pp_table_version == PP_TABLE_V0)
4847                 thermal_data->max = data->thermal_temp_setting.temperature_shutdown *
4848                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4849
4850         return 0;
4851 }
4852
4853 static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
4854                                         enum PP_OD_DPM_TABLE_COMMAND type,
4855                                         uint32_t clk,
4856                                         uint32_t voltage)
4857 {
4858         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4859
4860         if (voltage < data->odn_dpm_table.min_vddc || voltage > data->odn_dpm_table.max_vddc) {
4861                 pr_info("OD voltage is out of range [%d - %d] mV\n",
4862                                                 data->odn_dpm_table.min_vddc,
4863                                                 data->odn_dpm_table.max_vddc);
4864                 return false;
4865         }
4866
4867         if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
4868                 if (data->golden_dpm_table.sclk_table.dpm_levels[0].value > clk ||
4869                         hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
4870                         pr_info("OD engine clock is out of range [%d - %d] MHz\n",
4871                                 data->golden_dpm_table.sclk_table.dpm_levels[0].value/100,
4872                                 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4873                         return false;
4874                 }
4875         } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
4876                 if (data->golden_dpm_table.mclk_table.dpm_levels[0].value > clk ||
4877                         hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
4878                         pr_info("OD memory clock is out of range [%d - %d] MHz\n",
4879                                 data->golden_dpm_table.mclk_table.dpm_levels[0].value/100,
4880                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4881                         return false;
4882                 }
4883         } else {
4884                 return false;
4885         }
4886
4887         return true;
4888 }
4889
4890 static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
4891                                         enum PP_OD_DPM_TABLE_COMMAND type,
4892                                         long *input, uint32_t size)
4893 {
4894         uint32_t i;
4895         struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL;
4896         struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend = NULL;
4897         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4898
4899         uint32_t input_clk;
4900         uint32_t input_vol;
4901         uint32_t input_level;
4902
4903         PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
4904                                 return -EINVAL);
4905
4906         if (!hwmgr->od_enabled) {
4907                 pr_info("OverDrive feature not enabled\n");
4908                 return -EINVAL;
4909         }
4910
4911         if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) {
4912                 podn_dpm_table_in_backend = &data->odn_dpm_table.odn_core_clock_dpm_levels;
4913                 podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_sclk;
4914                 PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
4915                                 "Failed to get ODN SCLK and Voltage tables",
4916                                 return -EINVAL);
4917         } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) {
4918                 podn_dpm_table_in_backend = &data->odn_dpm_table.odn_memory_clock_dpm_levels;
4919                 podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_mclk;
4920
4921                 PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
4922                         "Failed to get ODN MCLK and Voltage tables",
4923                         return -EINVAL);
4924         } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
4925                 smu7_odn_initial_default_setting(hwmgr);
4926                 return 0;
4927         } else if (PP_OD_COMMIT_DPM_TABLE == type) {
4928                 smu7_check_dpm_table_updated(hwmgr);
4929                 return 0;
4930         } else {
4931                 return -EINVAL;
4932         }
4933
4934         for (i = 0; i < size; i += 3) {
4935                 if (i + 3 > size || input[i] >= podn_dpm_table_in_backend->num_of_pl) {
4936                         pr_info("invalid clock voltage input \n");
4937                         return 0;
4938                 }
4939                 input_level = input[i];
4940                 input_clk = input[i+1] * 100;
4941                 input_vol = input[i+2];
4942
4943                 if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
4944                         podn_dpm_table_in_backend->entries[input_level].clock = input_clk;
4945                         podn_vdd_dep_in_backend->entries[input_level].clk = input_clk;
4946                         podn_dpm_table_in_backend->entries[input_level].vddc = input_vol;
4947                         podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol;
4948                         podn_vdd_dep_in_backend->entries[input_level].vddgfx = input_vol;
4949                 } else {
4950                         return -EINVAL;
4951                 }
4952         }
4953
4954         return 0;
4955 }
4956
4957 static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
4958 {
4959         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4960         uint32_t i, size = 0;
4961         uint32_t len;
4962
4963         static const char *profile_name[7] = {"BOOTUP_DEFAULT",
4964                                         "3D_FULL_SCREEN",
4965                                         "POWER_SAVING",
4966                                         "VIDEO",
4967                                         "VR",
4968                                         "COMPUTE",
4969                                         "CUSTOM"};
4970
4971         static const char *title[8] = {"NUM",
4972                         "MODE_NAME",
4973                         "SCLK_UP_HYST",
4974                         "SCLK_DOWN_HYST",
4975                         "SCLK_ACTIVE_LEVEL",
4976                         "MCLK_UP_HYST",
4977                         "MCLK_DOWN_HYST",
4978                         "MCLK_ACTIVE_LEVEL"};
4979
4980         if (!buf)
4981                 return -EINVAL;
4982
4983         size += sprintf(buf + size, "%s %16s %16s %16s %16s %16s %16s %16s\n",
4984                         title[0], title[1], title[2], title[3],
4985                         title[4], title[5], title[6], title[7]);
4986
4987         len = ARRAY_SIZE(smu7_profiling);
4988
4989         for (i = 0; i < len; i++) {
4990                 if (i == hwmgr->power_profile_mode) {
4991                         size += sprintf(buf + size, "%3d %14s %s: %8d %16d %16d %16d %16d %16d\n",
4992                         i, profile_name[i], "*",
4993                         data->current_profile_setting.sclk_up_hyst,
4994                         data->current_profile_setting.sclk_down_hyst,
4995                         data->current_profile_setting.sclk_activity,
4996                         data->current_profile_setting.mclk_up_hyst,
4997                         data->current_profile_setting.mclk_down_hyst,
4998                         data->current_profile_setting.mclk_activity);
4999                         continue;
5000                 }
5001                 if (smu7_profiling[i].bupdate_sclk)
5002                         size += sprintf(buf + size, "%3d %16s: %8d %16d %16d ",
5003                         i, profile_name[i], smu7_profiling[i].sclk_up_hyst,
5004                         smu7_profiling[i].sclk_down_hyst,
5005                         smu7_profiling[i].sclk_activity);
5006                 else
5007                         size += sprintf(buf + size, "%3d %16s: %8s %16s %16s ",
5008                         i, profile_name[i], "-", "-", "-");
5009
5010                 if (smu7_profiling[i].bupdate_mclk)
5011                         size += sprintf(buf + size, "%16d %16d %16d\n",
5012                         smu7_profiling[i].mclk_up_hyst,
5013                         smu7_profiling[i].mclk_down_hyst,
5014                         smu7_profiling[i].mclk_activity);
5015                 else
5016                         size += sprintf(buf + size, "%16s %16s %16s\n",
5017                         "-", "-", "-");
5018         }
5019
5020         return size;
5021 }
5022
5023 static void smu7_patch_compute_profile_mode(struct pp_hwmgr *hwmgr,
5024                                         enum PP_SMC_POWER_PROFILE requst)
5025 {
5026         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5027         uint32_t tmp, level;
5028
5029         if (requst == PP_SMC_POWER_PROFILE_COMPUTE) {
5030                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
5031                         level = 0;
5032                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
5033                         while (tmp >>= 1)
5034                                 level++;
5035                         if (level > 0)
5036                                 smu7_force_clock_level(hwmgr, PP_SCLK, 3 << (level-1));
5037                 }
5038         } else if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE) {
5039                 smu7_force_clock_level(hwmgr, PP_SCLK, data->dpm_level_enable_mask.sclk_dpm_enable_mask);
5040         }
5041 }
5042
5043 static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
5044 {
5045         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
5046         struct profile_mode_setting tmp;
5047         enum PP_SMC_POWER_PROFILE mode;
5048
5049         if (input == NULL)
5050                 return -EINVAL;
5051
5052         mode = input[size];
5053         switch (mode) {
5054         case PP_SMC_POWER_PROFILE_CUSTOM:
5055                 if (size < 8 && size != 0)
5056                         return -EINVAL;
5057                 /* If only CUSTOM is passed in, use the saved values. Check
5058                  * that we actually have a CUSTOM profile by ensuring that
5059                  * the "use sclk" or the "use mclk" bits are set
5060                  */
5061                 tmp = smu7_profiling[PP_SMC_POWER_PROFILE_CUSTOM];
5062                 if (size == 0) {
5063                         if (tmp.bupdate_sclk == 0 && tmp.bupdate_mclk == 0)
5064                                 return -EINVAL;
5065                 } else {
5066                         tmp.bupdate_sclk = input[0];
5067                         tmp.sclk_up_hyst = input[1];
5068                         tmp.sclk_down_hyst = input[2];
5069                         tmp.sclk_activity = input[3];
5070                         tmp.bupdate_mclk = input[4];
5071                         tmp.mclk_up_hyst = input[5];
5072                         tmp.mclk_down_hyst = input[6];
5073                         tmp.mclk_activity = input[7];
5074                         smu7_profiling[PP_SMC_POWER_PROFILE_CUSTOM] = tmp;
5075                 }
5076                 if (!smum_update_dpm_settings(hwmgr, &tmp)) {
5077                         memcpy(&data->current_profile_setting, &tmp, sizeof(struct profile_mode_setting));
5078                         hwmgr->power_profile_mode = mode;
5079                 }
5080                 break;
5081         case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
5082         case PP_SMC_POWER_PROFILE_POWERSAVING:
5083         case PP_SMC_POWER_PROFILE_VIDEO:
5084         case PP_SMC_POWER_PROFILE_VR:
5085         case PP_SMC_POWER_PROFILE_COMPUTE:
5086                 if (mode == hwmgr->power_profile_mode)
5087                         return 0;
5088
5089                 memcpy(&tmp, &smu7_profiling[mode], sizeof(struct profile_mode_setting));
5090                 if (!smum_update_dpm_settings(hwmgr, &tmp)) {
5091                         if (tmp.bupdate_sclk) {
5092                                 data->current_profile_setting.bupdate_sclk = tmp.bupdate_sclk;
5093                                 data->current_profile_setting.sclk_up_hyst = tmp.sclk_up_hyst;
5094                                 data->current_profile_setting.sclk_down_hyst = tmp.sclk_down_hyst;
5095                                 data->current_profile_setting.sclk_activity = tmp.sclk_activity;
5096                         }
5097                         if (tmp.bupdate_mclk) {
5098                                 data->current_profile_setting.bupdate_mclk = tmp.bupdate_mclk;
5099                                 data->current_profile_setting.mclk_up_hyst = tmp.mclk_up_hyst;
5100                                 data->current_profile_setting.mclk_down_hyst = tmp.mclk_down_hyst;
5101                                 data->current_profile_setting.mclk_activity = tmp.mclk_activity;
5102                         }
5103                         smu7_patch_compute_profile_mode(hwmgr, mode);
5104                         hwmgr->power_profile_mode = mode;
5105                 }
5106                 break;
5107         default:
5108                 return -EINVAL;
5109         }
5110
5111         return 0;
5112 }
5113
5114 static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
5115                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
5116                                 PHM_PerformanceLevel *level)
5117 {
5118         const struct smu7_power_state *ps;
5119         uint32_t i;
5120
5121         if (level == NULL || hwmgr == NULL || state == NULL)
5122                 return -EINVAL;
5123
5124         ps = cast_const_phw_smu7_power_state(state);
5125
5126         i = index > ps->performance_level_count - 1 ?
5127                         ps->performance_level_count - 1 : index;
5128
5129         level->coreClock = ps->performance_levels[i].engine_clock;
5130         level->memory_clock = ps->performance_levels[i].memory_clock;
5131
5132         return 0;
5133 }
5134
5135 static int smu7_power_off_asic(struct pp_hwmgr *hwmgr)
5136 {
5137         int result;
5138
5139         result = smu7_disable_dpm_tasks(hwmgr);
5140         PP_ASSERT_WITH_CODE((0 == result),
5141                         "[disable_dpm_tasks] Failed to disable DPM!",
5142                         );
5143
5144         return result;
5145 }
5146
5147 static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
5148         .backend_init = &smu7_hwmgr_backend_init,
5149         .backend_fini = &smu7_hwmgr_backend_fini,
5150         .asic_setup = &smu7_setup_asic_task,
5151         .dynamic_state_management_enable = &smu7_enable_dpm_tasks,
5152         .apply_state_adjust_rules = smu7_apply_state_adjust_rules,
5153         .force_dpm_level = &smu7_force_dpm_level,
5154         .power_state_set = smu7_set_power_state_tasks,
5155         .get_power_state_size = smu7_get_power_state_size,
5156         .get_mclk = smu7_dpm_get_mclk,
5157         .get_sclk = smu7_dpm_get_sclk,
5158         .patch_boot_state = smu7_dpm_patch_boot_state,
5159         .get_pp_table_entry = smu7_get_pp_table_entry,
5160         .get_num_of_pp_table_entries = smu7_get_number_of_powerplay_table_entries,
5161         .powerdown_uvd = smu7_powerdown_uvd,
5162         .powergate_uvd = smu7_powergate_uvd,
5163         .powergate_vce = smu7_powergate_vce,
5164         .disable_clock_power_gating = smu7_disable_clock_power_gating,
5165         .update_clock_gatings = smu7_update_clock_gatings,
5166         .notify_smc_display_config_after_ps_adjustment = smu7_notify_smc_display_config_after_ps_adjustment,
5167         .display_config_changed = smu7_display_configuration_changed_task,
5168         .set_max_fan_pwm_output = smu7_set_max_fan_pwm_output,
5169         .set_max_fan_rpm_output = smu7_set_max_fan_rpm_output,
5170         .stop_thermal_controller = smu7_thermal_stop_thermal_controller,
5171         .get_fan_speed_info = smu7_fan_ctrl_get_fan_speed_info,
5172         .get_fan_speed_percent = smu7_fan_ctrl_get_fan_speed_percent,
5173         .set_fan_speed_percent = smu7_fan_ctrl_set_fan_speed_percent,
5174         .reset_fan_speed_to_default = smu7_fan_ctrl_reset_fan_speed_to_default,
5175         .get_fan_speed_rpm = smu7_fan_ctrl_get_fan_speed_rpm,
5176         .set_fan_speed_rpm = smu7_fan_ctrl_set_fan_speed_rpm,
5177         .uninitialize_thermal_controller = smu7_thermal_ctrl_uninitialize_thermal_controller,
5178         .register_irq_handlers = smu7_register_irq_handlers,
5179         .check_smc_update_required_for_display_configuration = smu7_check_smc_update_required_for_display_configuration,
5180         .check_states_equal = smu7_check_states_equal,
5181         .set_fan_control_mode = smu7_set_fan_control_mode,
5182         .get_fan_control_mode = smu7_get_fan_control_mode,
5183         .force_clock_level = smu7_force_clock_level,
5184         .print_clock_levels = smu7_print_clock_levels,
5185         .powergate_gfx = smu7_powergate_gfx,
5186         .get_sclk_od = smu7_get_sclk_od,
5187         .set_sclk_od = smu7_set_sclk_od,
5188         .get_mclk_od = smu7_get_mclk_od,
5189         .set_mclk_od = smu7_set_mclk_od,
5190         .get_clock_by_type = smu7_get_clock_by_type,
5191         .read_sensor = smu7_read_sensor,
5192         .dynamic_state_management_disable = smu7_disable_dpm_tasks,
5193         .avfs_control = smu7_avfs_control,
5194         .disable_smc_firmware_ctf = smu7_thermal_disable_alert,
5195         .start_thermal_controller = smu7_start_thermal_controller,
5196         .notify_cac_buffer_info = smu7_notify_cac_buffer_info,
5197         .get_max_high_clocks = smu7_get_max_high_clocks,
5198         .get_thermal_temperature_range = smu7_get_thermal_temperature_range,
5199         .odn_edit_dpm_table = smu7_odn_edit_dpm_table,
5200         .set_power_limit = smu7_set_power_limit,
5201         .get_power_profile_mode = smu7_get_power_profile_mode,
5202         .set_power_profile_mode = smu7_set_power_profile_mode,
5203         .get_performance_level = smu7_get_performance_level,
5204         .get_asic_baco_capability = smu7_baco_get_capability,
5205         .get_asic_baco_state = smu7_baco_get_state,
5206         .set_asic_baco_state = smu7_baco_set_state,
5207         .power_off_asic = smu7_power_off_asic,
5208 };
5209
5210 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
5211                 uint32_t clock_insr)
5212 {
5213         uint8_t i;
5214         uint32_t temp;
5215         uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK);
5216
5217         PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0);
5218         for (i = SMU7_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
5219                 temp = clock >> i;
5220
5221                 if (temp >= min || i == 0)
5222                         break;
5223         }
5224         return i;
5225 }
5226
5227 int smu7_init_function_pointers(struct pp_hwmgr *hwmgr)
5228 {
5229         hwmgr->hwmgr_func = &smu7_hwmgr_funcs;
5230         if (hwmgr->pp_table_version == PP_TABLE_V0)
5231                 hwmgr->pptable_func = &pptable_funcs;
5232         else if (hwmgr->pp_table_version == PP_TABLE_V1)
5233                 hwmgr->pptable_func = &pptable_v1_0_funcs;
5234
5235         return 0;
5236 }