drivers/gpu/drm/amd/pm/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <zajec5@gmail.com>
  23  *          Alex Deucher <alexdeucher@gmail.com>
  24  */
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "atom.h"
  31 #include <linux/pci.h>
  32 #include <linux/hwmon.h>
  33 #include <linux/hwmon-sysfs.h>
  34 #include <linux/nospec.h>
  35 #include <linux/pm_runtime.h>
  36 #include <asm/processor.h>
  37
  38 static const struct cg_flag_name clocks[] = {
  39         {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
  40         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  41         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  42         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  43         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  44         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  45         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  46         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  48         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  49         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  50         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  51         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  52         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  53         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  54         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  55         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  56         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  58         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  59         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  61         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  62         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  63         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  64         {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"},
  65         {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"},
  66         {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"},
  67         {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
  68         {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},
  69         {AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"},
  70         {AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"},
  71         {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
  72         {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
  73         {0, NULL},
  74 };
  75
  76 static const struct hwmon_temp_label {
  77         enum PP_HWMON_TEMP channel;
  78         const char *label;
  79 } temp_label[] = {
  80         {PP_TEMP_EDGE, "edge"},
  81         {PP_TEMP_JUNCTION, "junction"},
  82         {PP_TEMP_MEM, "mem"},
  83 };
  84
  85 const char * const amdgpu_pp_profile_name[] = {
  86         "BOOTUP_DEFAULT",
  87         "3D_FULL_SCREEN",
  88         "POWER_SAVING",
  89         "VIDEO",
  90         "VR",
  91         "COMPUTE",
  92         "CUSTOM",
  93         "WINDOW_3D",
  94         "CAPPED",
  95         "UNCAPPED",
  96 };
  97
  98 /**
  99  * DOC: power_dpm_state
 100  *
 101  * The power_dpm_state file is a legacy interface and is only provided for
 102  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 103  * certain power related parameters.  The file power_dpm_state is used for this.
 104  * It accepts the following arguments:
 105  *
 106  * - battery
 107  *
 108  * - balanced
 109  *
 110  * - performance
 111  *
 112  * battery
 113  *
 114  * On older GPUs, the vbios provided a special power state for battery
 115  * operation.  Selecting battery switched to this state.  This is no
 116  * longer provided on newer GPUs so the option does nothing in that case.
 117  *
 118  * balanced
 119  *
 120  * On older GPUs, the vbios provided a special power state for balanced
 121  * operation.  Selecting balanced switched to this state.  This is no
 122  * longer provided on newer GPUs so the option does nothing in that case.
 123  *
 124  * performance
 125  *
 126  * On older GPUs, the vbios provided a special power state for performance
 127  * operation.  Selecting performance switched to this state.  This is no
 128  * longer provided on newer GPUs so the option does nothing in that case.
 129  *
 130  */
 131
 132 static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
 133                                           struct device_attribute *attr,
 134                                           char *buf)
 135 {
 136         struct drm_device *ddev = dev_get_drvdata(dev);
 137         struct amdgpu_device *adev = drm_to_adev(ddev);
 138         enum amd_pm_state_type pm;
 139         int ret;
 140
 141         if (amdgpu_in_reset(adev))
 142                 return -EPERM;
 143         if (adev->in_suspend && !adev->in_runpm)
 144                 return -EPERM;
 145
 146         ret = pm_runtime_get_sync(ddev->dev);
 147         if (ret < 0) {
 148                 pm_runtime_put_autosuspend(ddev->dev);
 149                 return ret;
 150         }
 151
 152         amdgpu_dpm_get_current_power_state(adev, &pm);
 153
 154         pm_runtime_mark_last_busy(ddev->dev);
 155         pm_runtime_put_autosuspend(ddev->dev);
 156
 157         return sysfs_emit(buf, "%s\n",
 158                           (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 159                           (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 160 }
 161
 162 static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
 163                                           struct device_attribute *attr,
 164                                           const char *buf,
 165                                           size_t count)
 166 {
 167         struct drm_device *ddev = dev_get_drvdata(dev);
 168         struct amdgpu_device *adev = drm_to_adev(ddev);
 169         enum amd_pm_state_type  state;
 170         int ret;
 171
 172         if (amdgpu_in_reset(adev))
 173                 return -EPERM;
 174         if (adev->in_suspend && !adev->in_runpm)
 175                 return -EPERM;
 176
 177         if (strncmp("battery", buf, strlen("battery")) == 0)
 178                 state = POWER_STATE_TYPE_BATTERY;
 179         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 180                 state = POWER_STATE_TYPE_BALANCED;
 181         else if (strncmp("performance", buf, strlen("performance")) == 0)
 182                 state = POWER_STATE_TYPE_PERFORMANCE;
 183         else
 184                 return -EINVAL;
 185
 186         ret = pm_runtime_get_sync(ddev->dev);
 187         if (ret < 0) {
 188                 pm_runtime_put_autosuspend(ddev->dev);
 189                 return ret;
 190         }
 191
 192         amdgpu_dpm_set_power_state(adev, state);
 193
 194         pm_runtime_mark_last_busy(ddev->dev);
 195         pm_runtime_put_autosuspend(ddev->dev);
 196
 197         return count;
 198 }
 199
 200
 201 /**
 202  * DOC: power_dpm_force_performance_level
 203  *
 204  * The amdgpu driver provides a sysfs API for adjusting certain power
 205  * related parameters.  The file power_dpm_force_performance_level is
 206  * used for this.  It accepts the following arguments:
 207  *
 208  * - auto
 209  *
 210  * - low
 211  *
 212  * - high
 213  *
 214  * - manual
 215  *
 216  * - profile_standard
 217  *
 218  * - profile_min_sclk
 219  *
 220  * - profile_min_mclk
 221  *
 222  * - profile_peak
 223  *
 224  * auto
 225  *
 226  * When auto is selected, the driver will attempt to dynamically select
 227  * the optimal power profile for current conditions in the driver.
 228  *
 229  * low
 230  *
 231  * When low is selected, the clocks are forced to the lowest power state.
 232  *
 233  * high
 234  *
 235  * When high is selected, the clocks are forced to the highest power state.
 236  *
 237  * manual
 238  *
 239  * When manual is selected, the user can manually adjust which power states
 240  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 241  * and pp_dpm_pcie files and adjust the power state transition heuristics
 242  * via the pp_power_profile_mode sysfs file.
 243  *
 244  * profile_standard
 245  * profile_min_sclk
 246  * profile_min_mclk
 247  * profile_peak
 248  *
 249  * When the profiling modes are selected, clock and power gating are
 250  * disabled and the clocks are set for different profiling cases. This
 251  * mode is recommended for profiling specific work loads where you do
 252  * not want clock or power gating for clock fluctuation to interfere
 253  * with your results. profile_standard sets the clocks to a fixed clock
 254  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 255  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 256  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 257  *
 258  */
 259
 260 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
 261                                                             struct device_attribute *attr,
 262                                                             char *buf)
 263 {
 264         struct drm_device *ddev = dev_get_drvdata(dev);
 265         struct amdgpu_device *adev = drm_to_adev(ddev);
 266         enum amd_dpm_forced_level level = 0xff;
 267         int ret;
 268
 269         if (amdgpu_in_reset(adev))
 270                 return -EPERM;
 271         if (adev->in_suspend && !adev->in_runpm)
 272                 return -EPERM;
 273
 274         ret = pm_runtime_get_sync(ddev->dev);
 275         if (ret < 0) {
 276                 pm_runtime_put_autosuspend(ddev->dev);
 277                 return ret;
 278         }
 279
 280         level = amdgpu_dpm_get_performance_level(adev);
 281
 282         pm_runtime_mark_last_busy(ddev->dev);
 283         pm_runtime_put_autosuspend(ddev->dev);
 284
 285         return sysfs_emit(buf, "%s\n",
 286                           (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 287                           (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 288                           (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 289                           (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 290                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 291                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 292                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 293                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 294                           (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" :
 295                           "unknown");
 296 }
 297
 298 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
 299                                                             struct device_attribute *attr,
 300                                                             const char *buf,
 301                                                             size_t count)
 302 {
 303         struct drm_device *ddev = dev_get_drvdata(dev);
 304         struct amdgpu_device *adev = drm_to_adev(ddev);
 305         enum amd_dpm_forced_level level;
 306         int ret = 0;
 307
 308         if (amdgpu_in_reset(adev))
 309                 return -EPERM;
 310         if (adev->in_suspend && !adev->in_runpm)
 311                 return -EPERM;
 312
 313         if (strncmp("low", buf, strlen("low")) == 0) {
 314                 level = AMD_DPM_FORCED_LEVEL_LOW;
 315         } else if (strncmp("high", buf, strlen("high")) == 0) {
 316                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 317         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 318                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 319         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 320                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 321         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 322                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 323         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 324                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 325         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 326                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 327         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 328                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 329         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 330                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 331         } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) {
 332                 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM;
 333         }  else {
 334                 return -EINVAL;
 335         }
 336
 337         ret = pm_runtime_get_sync(ddev->dev);
 338         if (ret < 0) {
 339                 pm_runtime_put_autosuspend(ddev->dev);
 340                 return ret;
 341         }
 342
 343         mutex_lock(&adev->pm.stable_pstate_ctx_lock);
 344         if (amdgpu_dpm_force_performance_level(adev, level)) {
 345                 pm_runtime_mark_last_busy(ddev->dev);
 346                 pm_runtime_put_autosuspend(ddev->dev);
 347                 mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
 348                 return -EINVAL;
 349         }
 350         /* override whatever a user ctx may have set */
 351         adev->pm.stable_pstate_ctx = NULL;
 352         mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
 353
 354         pm_runtime_mark_last_busy(ddev->dev);
 355         pm_runtime_put_autosuspend(ddev->dev);
 356
 357         return count;
 358 }
 359
 360 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 361                 struct device_attribute *attr,
 362                 char *buf)
 363 {
 364         struct drm_device *ddev = dev_get_drvdata(dev);
 365         struct amdgpu_device *adev = drm_to_adev(ddev);
 366         struct pp_states_info data;
 367         uint32_t i;
 368         int buf_len, ret;
 369
 370         if (amdgpu_in_reset(adev))
 371                 return -EPERM;
 372         if (adev->in_suspend && !adev->in_runpm)
 373                 return -EPERM;
 374
 375         ret = pm_runtime_get_sync(ddev->dev);
 376         if (ret < 0) {
 377                 pm_runtime_put_autosuspend(ddev->dev);
 378                 return ret;
 379         }
 380
 381         if (amdgpu_dpm_get_pp_num_states(adev, &data))
 382                 memset(&data, 0, sizeof(data));
 383
 384         pm_runtime_mark_last_busy(ddev->dev);
 385         pm_runtime_put_autosuspend(ddev->dev);
 386
 387         buf_len = sysfs_emit(buf, "states: %d\n", data.nums);
 388         for (i = 0; i < data.nums; i++)
 389                 buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i,
 390                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 391                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 392                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 393                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 394
 395         return buf_len;
 396 }
 397
 398 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 399                 struct device_attribute *attr,
 400                 char *buf)
 401 {
 402         struct drm_device *ddev = dev_get_drvdata(dev);
 403         struct amdgpu_device *adev = drm_to_adev(ddev);
 404         struct pp_states_info data = {0};
 405         enum amd_pm_state_type pm = 0;
 406         int i = 0, ret = 0;
 407
 408         if (amdgpu_in_reset(adev))
 409                 return -EPERM;
 410         if (adev->in_suspend && !adev->in_runpm)
 411                 return -EPERM;
 412
 413         ret = pm_runtime_get_sync(ddev->dev);
 414         if (ret < 0) {
 415                 pm_runtime_put_autosuspend(ddev->dev);
 416                 return ret;
 417         }
 418
 419         amdgpu_dpm_get_current_power_state(adev, &pm);
 420
 421         ret = amdgpu_dpm_get_pp_num_states(adev, &data);
 422
 423         pm_runtime_mark_last_busy(ddev->dev);
 424         pm_runtime_put_autosuspend(ddev->dev);
 425
 426         if (ret)
 427                 return ret;
 428
 429         for (i = 0; i < data.nums; i++) {
 430                 if (pm == data.states[i])
 431                         break;
 432         }
 433
 434         if (i == data.nums)
 435                 i = -EINVAL;
 436
 437         return sysfs_emit(buf, "%d\n", i);
 438 }
 439
 440 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 441                 struct device_attribute *attr,
 442                 char *buf)
 443 {
 444         struct drm_device *ddev = dev_get_drvdata(dev);
 445         struct amdgpu_device *adev = drm_to_adev(ddev);
 446
 447         if (amdgpu_in_reset(adev))
 448                 return -EPERM;
 449         if (adev->in_suspend && !adev->in_runpm)
 450                 return -EPERM;
 451
 452         if (adev->pm.pp_force_state_enabled)
 453                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 454         else
 455                 return sysfs_emit(buf, "\n");
 456 }
 457
 458 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 459                 struct device_attribute *attr,
 460                 const char *buf,
 461                 size_t count)
 462 {
 463         struct drm_device *ddev = dev_get_drvdata(dev);
 464         struct amdgpu_device *adev = drm_to_adev(ddev);
 465         enum amd_pm_state_type state = 0;
 466         struct pp_states_info data;
 467         unsigned long idx;
 468         int ret;
 469
 470         if (amdgpu_in_reset(adev))
 471                 return -EPERM;
 472         if (adev->in_suspend && !adev->in_runpm)
 473                 return -EPERM;
 474
 475         adev->pm.pp_force_state_enabled = false;
 476
 477         if (strlen(buf) == 1)
 478                 return count;
 479
 480         ret = kstrtoul(buf, 0, &idx);
 481         if (ret || idx >= ARRAY_SIZE(data.states))
 482                 return -EINVAL;
 483
 484         idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 485
 486         ret = pm_runtime_get_sync(ddev->dev);
 487         if (ret < 0) {
 488                 pm_runtime_put_autosuspend(ddev->dev);
 489                 return ret;
 490         }
 491
 492         ret = amdgpu_dpm_get_pp_num_states(adev, &data);
 493         if (ret)
 494                 goto err_out;
 495
 496         state = data.states[idx];
 497
 498         /* only set user selected power states */
 499         if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 500             state != POWER_STATE_TYPE_DEFAULT) {
 501                 ret = amdgpu_dpm_dispatch_task(adev,
 502                                 AMD_PP_TASK_ENABLE_USER_STATE, &state);
 503                 if (ret)
 504                         goto err_out;
 505
 506                 adev->pm.pp_force_state_enabled = true;
 507         }
 508
 509         pm_runtime_mark_last_busy(ddev->dev);
 510         pm_runtime_put_autosuspend(ddev->dev);
 511
 512         return count;
 513
 514 err_out:
 515         pm_runtime_mark_last_busy(ddev->dev);
 516         pm_runtime_put_autosuspend(ddev->dev);
 517         return ret;
 518 }
 519
 520 /**
 521  * DOC: pp_table
 522  *
 523  * The amdgpu driver provides a sysfs API for uploading new powerplay
 524  * tables.  The file pp_table is used for this.  Reading the file
 525  * will dump the current power play table.  Writing to the file
 526  * will attempt to upload a new powerplay table and re-initialize
 527  * powerplay using that new table.
 528  *
 529  */
 530
 531 static ssize_t amdgpu_get_pp_table(struct device *dev,
 532                 struct device_attribute *attr,
 533                 char *buf)
 534 {
 535         struct drm_device *ddev = dev_get_drvdata(dev);
 536         struct amdgpu_device *adev = drm_to_adev(ddev);
 537         char *table = NULL;
 538         int size, ret;
 539
 540         if (amdgpu_in_reset(adev))
 541                 return -EPERM;
 542         if (adev->in_suspend && !adev->in_runpm)
 543                 return -EPERM;
 544
 545         ret = pm_runtime_get_sync(ddev->dev);
 546         if (ret < 0) {
 547                 pm_runtime_put_autosuspend(ddev->dev);
 548                 return ret;
 549         }
 550
 551         size = amdgpu_dpm_get_pp_table(adev, &table);
 552
 553         pm_runtime_mark_last_busy(ddev->dev);
 554         pm_runtime_put_autosuspend(ddev->dev);
 555
 556         if (size <= 0)
 557                 return size;
 558
 559         if (size >= PAGE_SIZE)
 560                 size = PAGE_SIZE - 1;
 561
 562         memcpy(buf, table, size);
 563
 564         return size;
 565 }
 566
 567 static ssize_t amdgpu_set_pp_table(struct device *dev,
 568                 struct device_attribute *attr,
 569                 const char *buf,
 570                 size_t count)
 571 {
 572         struct drm_device *ddev = dev_get_drvdata(dev);
 573         struct amdgpu_device *adev = drm_to_adev(ddev);
 574         int ret = 0;
 575
 576         if (amdgpu_in_reset(adev))
 577                 return -EPERM;
 578         if (adev->in_suspend && !adev->in_runpm)
 579                 return -EPERM;
 580
 581         ret = pm_runtime_get_sync(ddev->dev);
 582         if (ret < 0) {
 583                 pm_runtime_put_autosuspend(ddev->dev);
 584                 return ret;
 585         }
 586
 587         ret = amdgpu_dpm_set_pp_table(adev, buf, count);
 588
 589         pm_runtime_mark_last_busy(ddev->dev);
 590         pm_runtime_put_autosuspend(ddev->dev);
 591
 592         if (ret)
 593                 return ret;
 594
 595         return count;
 596 }
 597
 598 /**
 599  * DOC: pp_od_clk_voltage
 600  *
 601  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 602  * in each power level within a power state.  The pp_od_clk_voltage is used for
 603  * this.
 604  *
 605  * Note that the actual memory controller clock rate are exposed, not
 606  * the effective memory clock of the DRAMs. To translate it, use the
 607  * following formula:
 608  *
 609  * Clock conversion (Mhz):
 610  *
 611  * HBM: effective_memory_clock = memory_controller_clock * 1
 612  *
 613  * G5: effective_memory_clock = memory_controller_clock * 1
 614  *
 615  * G6: effective_memory_clock = memory_controller_clock * 2
 616  *
 617  * DRAM data rate (MT/s):
 618  *
 619  * HBM: effective_memory_clock * 2 = data_rate
 620  *
 621  * G5: effective_memory_clock * 4 = data_rate
 622  *
 623  * G6: effective_memory_clock * 8 = data_rate
 624  *
 625  * Bandwidth (MB/s):
 626  *
 627  * data_rate * vram_bit_width / 8 = memory_bandwidth
 628  *
 629  * Some examples:
 630  *
 631  * G5 on RX460:
 632  *
 633  * memory_controller_clock = 1750 Mhz
 634  *
 635  * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
 636  *
 637  * data rate = 1750 * 4 = 7000 MT/s
 638  *
 639  * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s
 640  *
 641  * G6 on RX5700:
 642  *
 643  * memory_controller_clock = 875 Mhz
 644  *
 645  * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz
 646  *
 647  * data rate = 1750 * 8 = 14000 MT/s
 648  *
 649  * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s
 650  *
 651  * < For Vega10 and previous ASICs >
 652  *
 653  * Reading the file will display:
 654  *
 655  * - a list of engine clock levels and voltages labeled OD_SCLK
 656  *
 657  * - a list of memory clock levels and voltages labeled OD_MCLK
 658  *
 659  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 660  *
 661  * To manually adjust these settings, first select manual using
 662  * power_dpm_force_performance_level. Enter a new value for each
 663  * level by writing a string that contains "s/m level clock voltage" to
 664  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 665  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 666  * 810 mV.  When you have edited all of the states as needed, write
 667  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 668  * default power levels, write "r" (reset) to the file to reset them.
 669  *
 670  *
 671  * < For Vega20 and newer ASICs >
 672  *
 673  * Reading the file will display:
 674  *
 675  * - minimum and maximum engine clock labeled OD_SCLK
 676  *
 677  * - minimum(not available for Vega20 and Navi1x) and maximum memory
 678  *   clock labeled OD_MCLK
 679  *
 680  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 681  *   They can be used to calibrate the sclk voltage curve. This is
 682  *   available for Vega20 and NV1X.
 683  *
 684  * - voltage offset for the six anchor points of the v/f curve labeled
 685  *   OD_VDDC_CURVE. They can be used to calibrate the v/f curve. This
 686  *   is only availabe for some SMU13 ASICs.
 687  *
 688  * - voltage offset(in mV) applied on target voltage calculation.
 689  *   This is available for Sienna Cichlid, Navy Flounder and Dimgrey
 690  *   Cavefish. For these ASICs, the target voltage calculation can be
 691  *   illustrated by "voltage = voltage calculated from v/f curve +
 692  *   overdrive vddgfx offset"
 693  *
 694  * - a list of valid ranges for sclk, mclk, and voltage curve points
 695  *   labeled OD_RANGE
 696  *
 697  * < For APUs >
 698  *
 699  * Reading the file will display:
 700  *
 701  * - minimum and maximum engine clock labeled OD_SCLK
 702  *
 703  * - a list of valid ranges for sclk labeled OD_RANGE
 704  *
 705  * < For VanGogh >
 706  *
 707  * Reading the file will display:
 708  *
 709  * - minimum and maximum engine clock labeled OD_SCLK
 710  * - minimum and maximum core clocks labeled OD_CCLK
 711  *
 712  * - a list of valid ranges for sclk and cclk labeled OD_RANGE
 713  *
 714  * To manually adjust these settings:
 715  *
 716  * - First select manual using power_dpm_force_performance_level
 717  *
 718  * - For clock frequency setting, enter a new value by writing a
 719  *   string that contains "s/m index clock" to the file. The index
 720  *   should be 0 if to set minimum clock. And 1 if to set maximum
 721  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 722  *   "m 1 800" will update maximum mclk to be 800Mhz. For core
 723  *   clocks on VanGogh, the string contains "p core index clock".
 724  *   E.g., "p 2 0 800" would set the minimum core clock on core
 725  *   2 to 800Mhz.
 726  *
 727  *   For sclk voltage curve,
 728  *     - For NV1X, enter the new values by writing a string that
 729  *       contains "vc point clock voltage" to the file. The points
 730  *       are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will update
 731  *       point1 with clock set as 300Mhz and voltage as 600mV. "vc 2
 732  *       1000 1000" will update point3 with clock set as 1000Mhz and
 733  *       voltage 1000mV.
 734  *     - For SMU13 ASICs, enter the new values by writing a string that
 735  *       contains "vc anchor_point_index voltage_offset" to the file.
 736  *       There are total six anchor points defined on the v/f curve with
 737  *       index as 0 - 5.
 738  *       - "vc 0 10" will update the voltage offset for point1 as 10mv.
 739  *       - "vc 5 -10" will update the voltage offset for point6 as -10mv.
 740  *
 741  *   To update the voltage offset applied for gfxclk/voltage calculation,
 742  *   enter the new value by writing a string that contains "vo offset".
 743  *   This is supported by Sienna Cichlid, Navy Flounder and Dimgrey Cavefish.
 744  *   And the offset can be a positive or negative value.
 745  *
 746  * - When you have edited all of the states as needed, write "c" (commit)
 747  *   to the file to commit your changes
 748  *
 749  * - If you want to reset to the default power levels, write "r" (reset)
 750  *   to the file to reset them
 751  *
 752  */
 753
 754 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 755                 struct device_attribute *attr,
 756                 const char *buf,
 757                 size_t count)
 758 {
 759         struct drm_device *ddev = dev_get_drvdata(dev);
 760         struct amdgpu_device *adev = drm_to_adev(ddev);
 761         int ret;
 762         uint32_t parameter_size = 0;
 763         long parameter[64];
 764         char buf_cpy[128];
 765         char *tmp_str;
 766         char *sub_str;
 767         const char delimiter[3] = {' ', '\n', '\0'};
 768         uint32_t type;
 769
 770         if (amdgpu_in_reset(adev))
 771                 return -EPERM;
 772         if (adev->in_suspend && !adev->in_runpm)
 773                 return -EPERM;
 774
 775         if (count > 127)
 776                 return -EINVAL;
 777
 778         if (*buf == 's')
 779                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 780         else if (*buf == 'p')
 781                 type = PP_OD_EDIT_CCLK_VDDC_TABLE;
 782         else if (*buf == 'm')
 783                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 784         else if(*buf == 'r')
 785                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 786         else if (*buf == 'c')
 787                 type = PP_OD_COMMIT_DPM_TABLE;
 788         else if (!strncmp(buf, "vc", 2))
 789                 type = PP_OD_EDIT_VDDC_CURVE;
 790         else if (!strncmp(buf, "vo", 2))
 791                 type = PP_OD_EDIT_VDDGFX_OFFSET;
 792         else
 793                 return -EINVAL;
 794
 795         memcpy(buf_cpy, buf, count+1);
 796
 797         tmp_str = buf_cpy;
 798
 799         if ((type == PP_OD_EDIT_VDDC_CURVE) ||
 800              (type == PP_OD_EDIT_VDDGFX_OFFSET))
 801                 tmp_str++;
 802         while (isspace(*++tmp_str));
 803
 804         while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
 805                 if (strlen(sub_str) == 0)
 806                         continue;
 807                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 808                 if (ret)
 809                         return -EINVAL;
 810                 parameter_size++;
 811
 812                 while (isspace(*tmp_str))
 813                         tmp_str++;
 814         }
 815
 816         ret = pm_runtime_get_sync(ddev->dev);
 817         if (ret < 0) {
 818                 pm_runtime_put_autosuspend(ddev->dev);
 819                 return ret;
 820         }
 821
 822         if (amdgpu_dpm_set_fine_grain_clk_vol(adev,
 823                                               type,
 824                                               parameter,
 825                                               parameter_size))
 826                 goto err_out;
 827
 828         if (amdgpu_dpm_odn_edit_dpm_table(adev, type,
 829                                           parameter, parameter_size))
 830                 goto err_out;
 831
 832         if (type == PP_OD_COMMIT_DPM_TABLE) {
 833                 if (amdgpu_dpm_dispatch_task(adev,
 834                                              AMD_PP_TASK_READJUST_POWER_STATE,
 835                                              NULL))
 836                         goto err_out;
 837         }
 838
 839         pm_runtime_mark_last_busy(ddev->dev);
 840         pm_runtime_put_autosuspend(ddev->dev);
 841
 842         return count;
 843
 844 err_out:
 845         pm_runtime_mark_last_busy(ddev->dev);
 846         pm_runtime_put_autosuspend(ddev->dev);
 847         return -EINVAL;
 848 }
 849
 850 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 851                 struct device_attribute *attr,
 852                 char *buf)
 853 {
 854         struct drm_device *ddev = dev_get_drvdata(dev);
 855         struct amdgpu_device *adev = drm_to_adev(ddev);
 856         int size = 0;
 857         int ret;
 858         enum pp_clock_type od_clocks[6] = {
 859                 OD_SCLK,
 860                 OD_MCLK,
 861                 OD_VDDC_CURVE,
 862                 OD_RANGE,
 863                 OD_VDDGFX_OFFSET,
 864                 OD_CCLK,
 865         };
 866         uint clk_index;
 867
 868         if (amdgpu_in_reset(adev))
 869                 return -EPERM;
 870         if (adev->in_suspend && !adev->in_runpm)
 871                 return -EPERM;
 872
 873         ret = pm_runtime_get_sync(ddev->dev);
 874         if (ret < 0) {
 875                 pm_runtime_put_autosuspend(ddev->dev);
 876                 return ret;
 877         }
 878
 879         for (clk_index = 0 ; clk_index < 6 ; clk_index++) {
 880                 ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size);
 881                 if (ret)
 882                         break;
 883         }
 884         if (ret == -ENOENT) {
 885                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 886                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size);
 887                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size);
 888                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size);
 889                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size);
 890                 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size);
 891         }
 892
 893         if (size == 0)
 894                 size = sysfs_emit(buf, "\n");
 895
 896         pm_runtime_mark_last_busy(ddev->dev);
 897         pm_runtime_put_autosuspend(ddev->dev);
 898
 899         return size;
 900 }
 901
 902 /**
 903  * DOC: pp_features
 904  *
 905  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 906  * features to be enabled. The file pp_features is used for this. And
 907  * this is only available for Vega10 and later dGPUs.
 908  *
 909  * Reading back the file will show you the followings:
 910  * - Current ppfeature masks
 911  * - List of the all supported powerplay features with their naming,
 912  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 913  *
 914  * To manually enable or disable a specific feature, just set or clear
 915  * the corresponding bit from original ppfeature masks and input the
 916  * new ppfeature masks.
 917  */
 918 static ssize_t amdgpu_set_pp_features(struct device *dev,
 919                                       struct device_attribute *attr,
 920                                       const char *buf,
 921                                       size_t count)
 922 {
 923         struct drm_device *ddev = dev_get_drvdata(dev);
 924         struct amdgpu_device *adev = drm_to_adev(ddev);
 925         uint64_t featuremask;
 926         int ret;
 927
 928         if (amdgpu_in_reset(adev))
 929                 return -EPERM;
 930         if (adev->in_suspend && !adev->in_runpm)
 931                 return -EPERM;
 932
 933         ret = kstrtou64(buf, 0, &featuremask);
 934         if (ret)
 935                 return -EINVAL;
 936
 937         ret = pm_runtime_get_sync(ddev->dev);
 938         if (ret < 0) {
 939                 pm_runtime_put_autosuspend(ddev->dev);
 940                 return ret;
 941         }
 942
 943         ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 944
 945         pm_runtime_mark_last_busy(ddev->dev);
 946         pm_runtime_put_autosuspend(ddev->dev);
 947
 948         if (ret)
 949                 return -EINVAL;
 950
 951         return count;
 952 }
 953
 954 static ssize_t amdgpu_get_pp_features(struct device *dev,
 955                                       struct device_attribute *attr,
 956                                       char *buf)
 957 {
 958         struct drm_device *ddev = dev_get_drvdata(dev);
 959         struct amdgpu_device *adev = drm_to_adev(ddev);
 960         ssize_t size;
 961         int ret;
 962
 963         if (amdgpu_in_reset(adev))
 964                 return -EPERM;
 965         if (adev->in_suspend && !adev->in_runpm)
 966                 return -EPERM;
 967
 968         ret = pm_runtime_get_sync(ddev->dev);
 969         if (ret < 0) {
 970                 pm_runtime_put_autosuspend(ddev->dev);
 971                 return ret;
 972         }
 973
 974         size = amdgpu_dpm_get_ppfeature_status(adev, buf);
 975         if (size <= 0)
 976                 size = sysfs_emit(buf, "\n");
 977
 978         pm_runtime_mark_last_busy(ddev->dev);
 979         pm_runtime_put_autosuspend(ddev->dev);
 980
 981         return size;
 982 }
 983
 984 /**
 985  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
 986  *
 987  * The amdgpu driver provides a sysfs API for adjusting what power levels
 988  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 989  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 990  * this.
 991  *
 992  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 993  * Vega10 and later ASICs.
 994  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 995  *
 996  * Reading back the files will show you the available power levels within
 997  * the power state and the clock information for those levels.
 998  *
 999  * To manually adjust these states, first select manual using
1000  * power_dpm_force_performance_level.
1001  * Secondly, enter a new value for each level by inputing a string that
1002  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
1003  * E.g.,
1004  *
1005  * .. code-block:: bash
1006  *
1007  *      echo "4 5 6" > pp_dpm_sclk
1008  *
1009  * will enable sclk levels 4, 5, and 6.
1010  *
1011  * NOTE: change to the dcefclk max dpm level is not supported now
1012  */
1013
1014 static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev,
1015                 enum pp_clock_type type,
1016                 char *buf)
1017 {
1018         struct drm_device *ddev = dev_get_drvdata(dev);
1019         struct amdgpu_device *adev = drm_to_adev(ddev);
1020         int size = 0;
1021         int ret = 0;
1022
1023         if (amdgpu_in_reset(adev))
1024                 return -EPERM;
1025         if (adev->in_suspend && !adev->in_runpm)
1026                 return -EPERM;
1027
1028         ret = pm_runtime_get_sync(ddev->dev);
1029         if (ret < 0) {
1030                 pm_runtime_put_autosuspend(ddev->dev);
1031                 return ret;
1032         }
1033
1034         ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size);
1035         if (ret == -ENOENT)
1036                 size = amdgpu_dpm_print_clock_levels(adev, type, buf);
1037
1038         if (size == 0)
1039                 size = sysfs_emit(buf, "\n");
1040
1041         pm_runtime_mark_last_busy(ddev->dev);
1042         pm_runtime_put_autosuspend(ddev->dev);
1043
1044         return size;
1045 }
1046
1047 /*
1048  * Worst case: 32 bits individually specified, in octal at 12 characters
1049  * per line (+1 for \n).
1050  */
1051 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
1052
1053 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1054 {
1055         int ret;
1056         unsigned long level;
1057         char *sub_str = NULL;
1058         char *tmp;
1059         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1060         const char delimiter[3] = {' ', '\n', '\0'};
1061         size_t bytes;
1062
1063         *mask = 0;
1064
1065         bytes = min(count, sizeof(buf_cpy) - 1);
1066         memcpy(buf_cpy, buf, bytes);
1067         buf_cpy[bytes] = '\0';
1068         tmp = buf_cpy;
1069         while ((sub_str = strsep(&tmp, delimiter)) != NULL) {
1070                 if (strlen(sub_str)) {
1071                         ret = kstrtoul(sub_str, 0, &level);
1072                         if (ret || level > 31)
1073                                 return -EINVAL;
1074                         *mask |= 1 << level;
1075                 } else
1076                         break;
1077         }
1078
1079         return 0;
1080 }
1081
1082 static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev,
1083                 enum pp_clock_type type,
1084                 const char *buf,
1085                 size_t count)
1086 {
1087         struct drm_device *ddev = dev_get_drvdata(dev);
1088         struct amdgpu_device *adev = drm_to_adev(ddev);
1089         int ret;
1090         uint32_t mask = 0;
1091
1092         if (amdgpu_in_reset(adev))
1093                 return -EPERM;
1094         if (adev->in_suspend && !adev->in_runpm)
1095                 return -EPERM;
1096
1097         ret = amdgpu_read_mask(buf, count, &mask);
1098         if (ret)
1099                 return ret;
1100
1101         ret = pm_runtime_get_sync(ddev->dev);
1102         if (ret < 0) {
1103                 pm_runtime_put_autosuspend(ddev->dev);
1104                 return ret;
1105         }
1106
1107         ret = amdgpu_dpm_force_clock_level(adev, type, mask);
1108
1109         pm_runtime_mark_last_busy(ddev->dev);
1110         pm_runtime_put_autosuspend(ddev->dev);
1111
1112         if (ret)
1113                 return -EINVAL;
1114
1115         return count;
1116 }
1117
1118 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
1119                 struct device_attribute *attr,
1120                 char *buf)
1121 {
1122         return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf);
1123 }
1124
1125 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1126                 struct device_attribute *attr,
1127                 const char *buf,
1128                 size_t count)
1129 {
1130         return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count);
1131 }
1132
1133 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1134                 struct device_attribute *attr,
1135                 char *buf)
1136 {
1137         return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf);
1138 }
1139
1140 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1141                 struct device_attribute *attr,
1142                 const char *buf,
1143                 size_t count)
1144 {
1145         return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count);
1146 }
1147
1148 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1149                 struct device_attribute *attr,
1150                 char *buf)
1151 {
1152         return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf);
1153 }
1154
1155 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1156                 struct device_attribute *attr,
1157                 const char *buf,
1158                 size_t count)
1159 {
1160         return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count);
1161 }
1162
1163 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1164                 struct device_attribute *attr,
1165                 char *buf)
1166 {
1167         return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf);
1168 }
1169
1170 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1171                 struct device_attribute *attr,
1172                 const char *buf,
1173                 size_t count)
1174 {
1175         return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count);
1176 }
1177
1178 static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev,
1179                 struct device_attribute *attr,
1180                 char *buf)
1181 {
1182         return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf);
1183 }
1184
1185 static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev,
1186                 struct device_attribute *attr,
1187                 const char *buf,
1188                 size_t count)
1189 {
1190         return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count);
1191 }
1192
1193 static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev,
1194                 struct device_attribute *attr,
1195                 char *buf)
1196 {
1197         return amdgpu_get_pp_dpm_clock(dev, PP_VCLK1, buf);
1198 }
1199
1200 static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev,
1201                 struct device_attribute *attr,
1202                 const char *buf,
1203                 size_t count)
1204 {
1205         return amdgpu_set_pp_dpm_clock(dev, PP_VCLK1, buf, count);
1206 }
1207
1208 static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev,
1209                 struct device_attribute *attr,
1210                 char *buf)
1211 {
1212         return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf);
1213 }
1214
1215 static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev,
1216                 struct device_attribute *attr,
1217                 const char *buf,
1218                 size_t count)
1219 {
1220         return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count);
1221 }
1222
1223 static ssize_t amdgpu_get_pp_dpm_dclk1(struct device *dev,
1224                 struct device_attribute *attr,
1225                 char *buf)
1226 {
1227         return amdgpu_get_pp_dpm_clock(dev, PP_DCLK1, buf);
1228 }
1229
1230 static ssize_t amdgpu_set_pp_dpm_dclk1(struct device *dev,
1231                 struct device_attribute *attr,
1232                 const char *buf,
1233                 size_t count)
1234 {
1235         return amdgpu_set_pp_dpm_clock(dev, PP_DCLK1, buf, count);
1236 }
1237
1238 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1239                 struct device_attribute *attr,
1240                 char *buf)
1241 {
1242         return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf);
1243 }
1244
1245 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1246                 struct device_attribute *attr,
1247                 const char *buf,
1248                 size_t count)
1249 {
1250         return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count);
1251 }
1252
1253 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1254                 struct device_attribute *attr,
1255                 char *buf)
1256 {
1257         return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf);
1258 }
1259
1260 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1261                 struct device_attribute *attr,
1262                 const char *buf,
1263                 size_t count)
1264 {
1265         return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count);
1266 }
1267
1268 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1269                 struct device_attribute *attr,
1270                 char *buf)
1271 {
1272         struct drm_device *ddev = dev_get_drvdata(dev);
1273         struct amdgpu_device *adev = drm_to_adev(ddev);
1274         uint32_t value = 0;
1275         int ret;
1276
1277         if (amdgpu_in_reset(adev))
1278                 return -EPERM;
1279         if (adev->in_suspend && !adev->in_runpm)
1280                 return -EPERM;
1281
1282         ret = pm_runtime_get_sync(ddev->dev);
1283         if (ret < 0) {
1284                 pm_runtime_put_autosuspend(ddev->dev);
1285                 return ret;
1286         }
1287
1288         value = amdgpu_dpm_get_sclk_od(adev);
1289
1290         pm_runtime_mark_last_busy(ddev->dev);
1291         pm_runtime_put_autosuspend(ddev->dev);
1292
1293         return sysfs_emit(buf, "%d\n", value);
1294 }
1295
1296 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1297                 struct device_attribute *attr,
1298                 const char *buf,
1299                 size_t count)
1300 {
1301         struct drm_device *ddev = dev_get_drvdata(dev);
1302         struct amdgpu_device *adev = drm_to_adev(ddev);
1303         int ret;
1304         long int value;
1305
1306         if (amdgpu_in_reset(adev))
1307                 return -EPERM;
1308         if (adev->in_suspend && !adev->in_runpm)
1309                 return -EPERM;
1310
1311         ret = kstrtol(buf, 0, &value);
1312
1313         if (ret)
1314                 return -EINVAL;
1315
1316         ret = pm_runtime_get_sync(ddev->dev);
1317         if (ret < 0) {
1318                 pm_runtime_put_autosuspend(ddev->dev);
1319                 return ret;
1320         }
1321
1322         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1323
1324         pm_runtime_mark_last_busy(ddev->dev);
1325         pm_runtime_put_autosuspend(ddev->dev);
1326
1327         return count;
1328 }
1329
1330 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1331                 struct device_attribute *attr,
1332                 char *buf)
1333 {
1334         struct drm_device *ddev = dev_get_drvdata(dev);
1335         struct amdgpu_device *adev = drm_to_adev(ddev);
1336         uint32_t value = 0;
1337         int ret;
1338
1339         if (amdgpu_in_reset(adev))
1340                 return -EPERM;
1341         if (adev->in_suspend && !adev->in_runpm)
1342                 return -EPERM;
1343
1344         ret = pm_runtime_get_sync(ddev->dev);
1345         if (ret < 0) {
1346                 pm_runtime_put_autosuspend(ddev->dev);
1347                 return ret;
1348         }
1349
1350         value = amdgpu_dpm_get_mclk_od(adev);
1351
1352         pm_runtime_mark_last_busy(ddev->dev);
1353         pm_runtime_put_autosuspend(ddev->dev);
1354
1355         return sysfs_emit(buf, "%d\n", value);
1356 }
1357
1358 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1359                 struct device_attribute *attr,
1360                 const char *buf,
1361                 size_t count)
1362 {
1363         struct drm_device *ddev = dev_get_drvdata(dev);
1364         struct amdgpu_device *adev = drm_to_adev(ddev);
1365         int ret;
1366         long int value;
1367
1368         if (amdgpu_in_reset(adev))
1369                 return -EPERM;
1370         if (adev->in_suspend && !adev->in_runpm)
1371                 return -EPERM;
1372
1373         ret = kstrtol(buf, 0, &value);
1374
1375         if (ret)
1376                 return -EINVAL;
1377
1378         ret = pm_runtime_get_sync(ddev->dev);
1379         if (ret < 0) {
1380                 pm_runtime_put_autosuspend(ddev->dev);
1381                 return ret;
1382         }
1383
1384         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1385
1386         pm_runtime_mark_last_busy(ddev->dev);
1387         pm_runtime_put_autosuspend(ddev->dev);
1388
1389         return count;
1390 }
1391
1392 /**
1393  * DOC: pp_power_profile_mode
1394  *
1395  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1396  * related to switching between power levels in a power state.  The file
1397  * pp_power_profile_mode is used for this.
1398  *
1399  * Reading this file outputs a list of all of the predefined power profiles
1400  * and the relevant heuristics settings for that profile.
1401  *
1402  * To select a profile or create a custom profile, first select manual using
1403  * power_dpm_force_performance_level.  Writing the number of a predefined
1404  * profile to pp_power_profile_mode will enable those heuristics.  To
1405  * create a custom set of heuristics, write a string of numbers to the file
1406  * starting with the number of the custom profile along with a setting
1407  * for each heuristic parameter.  Due to differences across asic families
1408  * the heuristic parameters vary from family to family.
1409  *
1410  */
1411
1412 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1413                 struct device_attribute *attr,
1414                 char *buf)
1415 {
1416         struct drm_device *ddev = dev_get_drvdata(dev);
1417         struct amdgpu_device *adev = drm_to_adev(ddev);
1418         ssize_t size;
1419         int ret;
1420
1421         if (amdgpu_in_reset(adev))
1422                 return -EPERM;
1423         if (adev->in_suspend && !adev->in_runpm)
1424                 return -EPERM;
1425
1426         ret = pm_runtime_get_sync(ddev->dev);
1427         if (ret < 0) {
1428                 pm_runtime_put_autosuspend(ddev->dev);
1429                 return ret;
1430         }
1431
1432         size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1433         if (size <= 0)
1434                 size = sysfs_emit(buf, "\n");
1435
1436         pm_runtime_mark_last_busy(ddev->dev);
1437         pm_runtime_put_autosuspend(ddev->dev);
1438
1439         return size;
1440 }
1441
1442
1443 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1444                 struct device_attribute *attr,
1445                 const char *buf,
1446                 size_t count)
1447 {
1448         int ret;
1449         struct drm_device *ddev = dev_get_drvdata(dev);
1450         struct amdgpu_device *adev = drm_to_adev(ddev);
1451         uint32_t parameter_size = 0;
1452         long parameter[64];
1453         char *sub_str, buf_cpy[128];
1454         char *tmp_str;
1455         uint32_t i = 0;
1456         char tmp[2];
1457         long int profile_mode = 0;
1458         const char delimiter[3] = {' ', '\n', '\0'};
1459
1460         if (amdgpu_in_reset(adev))
1461                 return -EPERM;
1462         if (adev->in_suspend && !adev->in_runpm)
1463                 return -EPERM;
1464
1465         tmp[0] = *(buf);
1466         tmp[1] = '\0';
1467         ret = kstrtol(tmp, 0, &profile_mode);
1468         if (ret)
1469                 return -EINVAL;
1470
1471         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1472                 if (count < 2 || count > 127)
1473                         return -EINVAL;
1474                 while (isspace(*++buf))
1475                         i++;
1476                 memcpy(buf_cpy, buf, count-i);
1477                 tmp_str = buf_cpy;
1478                 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
1479                         if (strlen(sub_str) == 0)
1480                                 continue;
1481                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1482                         if (ret)
1483                                 return -EINVAL;
1484                         parameter_size++;
1485                         while (isspace(*tmp_str))
1486                                 tmp_str++;
1487                 }
1488         }
1489         parameter[parameter_size] = profile_mode;
1490
1491         ret = pm_runtime_get_sync(ddev->dev);
1492         if (ret < 0) {
1493                 pm_runtime_put_autosuspend(ddev->dev);
1494                 return ret;
1495         }
1496
1497         ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1498
1499         pm_runtime_mark_last_busy(ddev->dev);
1500         pm_runtime_put_autosuspend(ddev->dev);
1501
1502         if (!ret)
1503                 return count;
1504
1505         return -EINVAL;
1506 }
1507
1508 /**
1509  * DOC: gpu_busy_percent
1510  *
1511  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1512  * is as a percentage.  The file gpu_busy_percent is used for this.
1513  * The SMU firmware computes a percentage of load based on the
1514  * aggregate activity level in the IP cores.
1515  */
1516 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
1517                                            struct device_attribute *attr,
1518                                            char *buf)
1519 {
1520         struct drm_device *ddev = dev_get_drvdata(dev);
1521         struct amdgpu_device *adev = drm_to_adev(ddev);
1522         int r, value, size = sizeof(value);
1523
1524         if (amdgpu_in_reset(adev))
1525                 return -EPERM;
1526         if (adev->in_suspend && !adev->in_runpm)
1527                 return -EPERM;
1528
1529         r = pm_runtime_get_sync(ddev->dev);
1530         if (r < 0) {
1531                 pm_runtime_put_autosuspend(ddev->dev);
1532                 return r;
1533         }
1534
1535         /* read the IP busy sensor */
1536         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1537                                    (void *)&value, &size);
1538
1539         pm_runtime_mark_last_busy(ddev->dev);
1540         pm_runtime_put_autosuspend(ddev->dev);
1541
1542         if (r)
1543                 return r;
1544
1545         return sysfs_emit(buf, "%d\n", value);
1546 }
1547
1548 /**
1549  * DOC: mem_busy_percent
1550  *
1551  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1552  * is as a percentage.  The file mem_busy_percent is used for this.
1553  * The SMU firmware computes a percentage of load based on the
1554  * aggregate activity level in the IP cores.
1555  */
1556 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
1557                                            struct device_attribute *attr,
1558                                            char *buf)
1559 {
1560         struct drm_device *ddev = dev_get_drvdata(dev);
1561         struct amdgpu_device *adev = drm_to_adev(ddev);
1562         int r, value, size = sizeof(value);
1563
1564         if (amdgpu_in_reset(adev))
1565                 return -EPERM;
1566         if (adev->in_suspend && !adev->in_runpm)
1567                 return -EPERM;
1568
1569         r = pm_runtime_get_sync(ddev->dev);
1570         if (r < 0) {
1571                 pm_runtime_put_autosuspend(ddev->dev);
1572                 return r;
1573         }
1574
1575         /* read the IP busy sensor */
1576         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1577                                    (void *)&value, &size);
1578
1579         pm_runtime_mark_last_busy(ddev->dev);
1580         pm_runtime_put_autosuspend(ddev->dev);
1581
1582         if (r)
1583                 return r;
1584
1585         return sysfs_emit(buf, "%d\n", value);
1586 }
1587
1588 /**
1589  * DOC: pcie_bw
1590  *
1591  * The amdgpu driver provides a sysfs API for estimating how much data
1592  * has been received and sent by the GPU in the last second through PCIe.
1593  * The file pcie_bw is used for this.
1594  * The Perf counters count the number of received and sent messages and return
1595  * those values, as well as the maximum payload size of a PCIe packet (mps).
1596  * Note that it is not possible to easily and quickly obtain the size of each
1597  * packet transmitted, so we output the max payload size (mps) to allow for
1598  * quick estimation of the PCIe bandwidth usage
1599  */
1600 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1601                 struct device_attribute *attr,
1602                 char *buf)
1603 {
1604         struct drm_device *ddev = dev_get_drvdata(dev);
1605         struct amdgpu_device *adev = drm_to_adev(ddev);
1606         uint64_t count0 = 0, count1 = 0;
1607         int ret;
1608
1609         if (amdgpu_in_reset(adev))
1610                 return -EPERM;
1611         if (adev->in_suspend && !adev->in_runpm)
1612                 return -EPERM;
1613
1614         if (adev->flags & AMD_IS_APU)
1615                 return -ENODATA;
1616
1617         if (!adev->asic_funcs->get_pcie_usage)
1618                 return -ENODATA;
1619
1620         ret = pm_runtime_get_sync(ddev->dev);
1621         if (ret < 0) {
1622                 pm_runtime_put_autosuspend(ddev->dev);
1623                 return ret;
1624         }
1625
1626         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1627
1628         pm_runtime_mark_last_busy(ddev->dev);
1629         pm_runtime_put_autosuspend(ddev->dev);
1630
1631         return sysfs_emit(buf, "%llu %llu %i\n",
1632                           count0, count1, pcie_get_mps(adev->pdev));
1633 }
1634
1635 /**
1636  * DOC: unique_id
1637  *
1638  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1639  * The file unique_id is used for this.
1640  * This will provide a Unique ID that will persist from machine to machine
1641  *
1642  * NOTE: This will only work for GFX9 and newer. This file will be absent
1643  * on unsupported ASICs (GFX8 and older)
1644  */
1645 static ssize_t amdgpu_get_unique_id(struct device *dev,
1646                 struct device_attribute *attr,
1647                 char *buf)
1648 {
1649         struct drm_device *ddev = dev_get_drvdata(dev);
1650         struct amdgpu_device *adev = drm_to_adev(ddev);
1651
1652         if (amdgpu_in_reset(adev))
1653                 return -EPERM;
1654         if (adev->in_suspend && !adev->in_runpm)
1655                 return -EPERM;
1656
1657         if (adev->unique_id)
1658                 return sysfs_emit(buf, "%016llx\n", adev->unique_id);
1659
1660         return 0;
1661 }
1662
1663 /**
1664  * DOC: thermal_throttling_logging
1665  *
1666  * Thermal throttling pulls down the clock frequency and thus the performance.
1667  * It's an useful mechanism to protect the chip from overheating. Since it
1668  * impacts performance, the user controls whether it is enabled and if so,
1669  * the log frequency.
1670  *
1671  * Reading back the file shows you the status(enabled or disabled) and
1672  * the interval(in seconds) between each thermal logging.
1673  *
1674  * Writing an integer to the file, sets a new logging interval, in seconds.
1675  * The value should be between 1 and 3600. If the value is less than 1,
1676  * thermal logging is disabled. Values greater than 3600 are ignored.
1677  */
1678 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev,
1679                                                      struct device_attribute *attr,
1680                                                      char *buf)
1681 {
1682         struct drm_device *ddev = dev_get_drvdata(dev);
1683         struct amdgpu_device *adev = drm_to_adev(ddev);
1684
1685         return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n",
1686                           adev_to_drm(adev)->unique,
1687                           atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled",
1688                           adev->throttling_logging_rs.interval / HZ + 1);
1689 }
1690
1691 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev,
1692                                                      struct device_attribute *attr,
1693                                                      const char *buf,
1694                                                      size_t count)
1695 {
1696         struct drm_device *ddev = dev_get_drvdata(dev);
1697         struct amdgpu_device *adev = drm_to_adev(ddev);
1698         long throttling_logging_interval;
1699         unsigned long flags;
1700         int ret = 0;
1701
1702         ret = kstrtol(buf, 0, &throttling_logging_interval);
1703         if (ret)
1704                 return ret;
1705
1706         if (throttling_logging_interval > 3600)
1707                 return -EINVAL;
1708
1709         if (throttling_logging_interval > 0) {
1710                 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags);
1711                 /*
1712                  * Reset the ratelimit timer internals.
1713                  * This can effectively restart the timer.
1714                  */
1715                 adev->throttling_logging_rs.interval =
1716                         (throttling_logging_interval - 1) * HZ;
1717                 adev->throttling_logging_rs.begin = 0;
1718                 adev->throttling_logging_rs.printed = 0;
1719                 adev->throttling_logging_rs.missed = 0;
1720                 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags);
1721
1722                 atomic_set(&adev->throttling_logging_enabled, 1);
1723         } else {
1724                 atomic_set(&adev->throttling_logging_enabled, 0);
1725         }
1726
1727         return count;
1728 }
1729
1730 /**
1731  * DOC: apu_thermal_cap
1732  *
1733  * The amdgpu driver provides a sysfs API for retrieving/updating thermal
1734  * limit temperature in millidegrees Celsius
1735  *
1736  * Reading back the file shows you core limit value
1737  *
1738  * Writing an integer to the file, sets a new thermal limit. The value
1739  * should be between 0 and 100. If the value is less than 0 or greater
1740  * than 100, then the write request will be ignored.
1741  */
1742 static ssize_t amdgpu_get_apu_thermal_cap(struct device *dev,
1743                                          struct device_attribute *attr,
1744                                          char *buf)
1745 {
1746         int ret, size;
1747         u32 limit;
1748         struct drm_device *ddev = dev_get_drvdata(dev);
1749         struct amdgpu_device *adev = drm_to_adev(ddev);
1750
1751         ret = pm_runtime_get_sync(ddev->dev);
1752         if (ret < 0) {
1753                 pm_runtime_put_autosuspend(ddev->dev);
1754                 return ret;
1755         }
1756
1757         ret = amdgpu_dpm_get_apu_thermal_limit(adev, &limit);
1758         if (!ret)
1759                 size = sysfs_emit(buf, "%u\n", limit);
1760         else
1761                 size = sysfs_emit(buf, "failed to get thermal limit\n");
1762
1763         pm_runtime_mark_last_busy(ddev->dev);
1764         pm_runtime_put_autosuspend(ddev->dev);
1765
1766         return size;
1767 }
1768
1769 static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev,
1770                                          struct device_attribute *attr,
1771                                          const char *buf,
1772                                          size_t count)
1773 {
1774         int ret;
1775         u32 value;
1776         struct drm_device *ddev = dev_get_drvdata(dev);
1777         struct amdgpu_device *adev = drm_to_adev(ddev);
1778
1779         ret = kstrtou32(buf, 10, &value);
1780         if (ret)
1781                 return ret;
1782
1783         if (value > 100) {
1784                 dev_err(dev, "Invalid argument !\n");
1785                 return -EINVAL;
1786         }
1787
1788         ret = pm_runtime_get_sync(ddev->dev);
1789         if (ret < 0) {
1790                 pm_runtime_put_autosuspend(ddev->dev);
1791                 return ret;
1792         }
1793
1794         ret = amdgpu_dpm_set_apu_thermal_limit(adev, value);
1795         if (ret) {
1796                 dev_err(dev, "failed to update thermal limit\n");
1797                 return ret;
1798         }
1799
1800         pm_runtime_mark_last_busy(ddev->dev);
1801         pm_runtime_put_autosuspend(ddev->dev);
1802
1803         return count;
1804 }
1805
1806 /**
1807  * DOC: gpu_metrics
1808  *
1809  * The amdgpu driver provides a sysfs API for retrieving current gpu
1810  * metrics data. The file gpu_metrics is used for this. Reading the
1811  * file will dump all the current gpu metrics data.
1812  *
1813  * These data include temperature, frequency, engines utilization,
1814  * power consume, throttler status, fan speed and cpu core statistics(
1815  * available for APU only). That's it will give a snapshot of all sensors
1816  * at the same time.
1817  */
1818 static ssize_t amdgpu_get_gpu_metrics(struct device *dev,
1819                                       struct device_attribute *attr,
1820                                       char *buf)
1821 {
1822         struct drm_device *ddev = dev_get_drvdata(dev);
1823         struct amdgpu_device *adev = drm_to_adev(ddev);
1824         void *gpu_metrics;
1825         ssize_t size = 0;
1826         int ret;
1827
1828         if (amdgpu_in_reset(adev))
1829                 return -EPERM;
1830         if (adev->in_suspend && !adev->in_runpm)
1831                 return -EPERM;
1832
1833         ret = pm_runtime_get_sync(ddev->dev);
1834         if (ret < 0) {
1835                 pm_runtime_put_autosuspend(ddev->dev);
1836                 return ret;
1837         }
1838
1839         size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics);
1840         if (size <= 0)
1841                 goto out;
1842
1843         if (size >= PAGE_SIZE)
1844                 size = PAGE_SIZE - 1;
1845
1846         memcpy(buf, gpu_metrics, size);
1847
1848 out:
1849         pm_runtime_mark_last_busy(ddev->dev);
1850         pm_runtime_put_autosuspend(ddev->dev);
1851
1852         return size;
1853 }
1854
1855 static int amdgpu_device_read_powershift(struct amdgpu_device *adev,
1856                                                 uint32_t *ss_power, bool dgpu_share)
1857 {
1858         struct drm_device *ddev = adev_to_drm(adev);
1859         uint32_t size;
1860         int r = 0;
1861
1862         if (amdgpu_in_reset(adev))
1863                 return -EPERM;
1864         if (adev->in_suspend && !adev->in_runpm)
1865                 return -EPERM;
1866
1867         r = pm_runtime_get_sync(ddev->dev);
1868         if (r < 0) {
1869                 pm_runtime_put_autosuspend(ddev->dev);
1870                 return r;
1871         }
1872
1873         if (dgpu_share)
1874                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
1875                                    (void *)ss_power, &size);
1876         else
1877                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
1878                                    (void *)ss_power, &size);
1879
1880         pm_runtime_mark_last_busy(ddev->dev);
1881         pm_runtime_put_autosuspend(ddev->dev);
1882         return r;
1883 }
1884
1885 static int amdgpu_show_powershift_percent(struct device *dev,
1886                                         char *buf, bool dgpu_share)
1887 {
1888         struct drm_device *ddev = dev_get_drvdata(dev);
1889         struct amdgpu_device *adev = drm_to_adev(ddev);
1890         uint32_t ss_power;
1891         int r = 0, i;
1892
1893         r = amdgpu_device_read_powershift(adev, &ss_power, dgpu_share);
1894         if (r == -EOPNOTSUPP) {
1895                 /* sensor not available on dGPU, try to read from APU */
1896                 adev = NULL;
1897                 mutex_lock(&mgpu_info.mutex);
1898                 for (i = 0; i < mgpu_info.num_gpu; i++) {
1899                         if (mgpu_info.gpu_ins[i].adev->flags & AMD_IS_APU) {
1900                                 adev = mgpu_info.gpu_ins[i].adev;
1901                                 break;
1902                         }
1903                 }
1904                 mutex_unlock(&mgpu_info.mutex);
1905                 if (adev)
1906                         r = amdgpu_device_read_powershift(adev, &ss_power, dgpu_share);
1907         }
1908
1909         if (!r)
1910                 r = sysfs_emit(buf, "%u%%\n", ss_power);
1911
1912         return r;
1913 }
1914 /**
1915  * DOC: smartshift_apu_power
1916  *
1917  * The amdgpu driver provides a sysfs API for reporting APU power
1918  * shift in percentage if platform supports smartshift. Value 0 means that
1919  * there is no powershift and values between [1-100] means that the power
1920  * is shifted to APU, the percentage of boost is with respect to APU power
1921  * limit on the platform.
1922  */
1923
1924 static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr,
1925                                                char *buf)
1926 {
1927         return amdgpu_show_powershift_percent(dev, buf, false);
1928 }
1929
1930 /**
1931  * DOC: smartshift_dgpu_power
1932  *
1933  * The amdgpu driver provides a sysfs API for reporting dGPU power
1934  * shift in percentage if platform supports smartshift. Value 0 means that
1935  * there is no powershift and values between [1-100] means that the power is
1936  * shifted to dGPU, the percentage of boost is with respect to dGPU power
1937  * limit on the platform.
1938  */
1939
1940 static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr,
1941                                                 char *buf)
1942 {
1943         return amdgpu_show_powershift_percent(dev, buf, true);
1944 }
1945
1946 /**
1947  * DOC: smartshift_bias
1948  *
1949  * The amdgpu driver provides a sysfs API for reporting the
1950  * smartshift(SS2.0) bias level. The value ranges from -100 to 100
1951  * and the default is 0. -100 sets maximum preference to APU
1952  * and 100 sets max perference to dGPU.
1953  */
1954
1955 static ssize_t amdgpu_get_smartshift_bias(struct device *dev,
1956                                           struct device_attribute *attr,
1957                                           char *buf)
1958 {
1959         int r = 0;
1960
1961         r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias);
1962
1963         return r;
1964 }
1965
1966 static ssize_t amdgpu_set_smartshift_bias(struct device *dev,
1967                                           struct device_attribute *attr,
1968                                           const char *buf, size_t count)
1969 {
1970         struct drm_device *ddev = dev_get_drvdata(dev);
1971         struct amdgpu_device *adev = drm_to_adev(ddev);
1972         int r = 0;
1973         int bias = 0;
1974
1975         if (amdgpu_in_reset(adev))
1976                 return -EPERM;
1977         if (adev->in_suspend && !adev->in_runpm)
1978                 return -EPERM;
1979
1980         r = pm_runtime_get_sync(ddev->dev);
1981         if (r < 0) {
1982                 pm_runtime_put_autosuspend(ddev->dev);
1983                 return r;
1984         }
1985
1986         r = kstrtoint(buf, 10, &bias);
1987         if (r)
1988                 goto out;
1989
1990         if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS)
1991                 bias = AMDGPU_SMARTSHIFT_MAX_BIAS;
1992         else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS)
1993                 bias = AMDGPU_SMARTSHIFT_MIN_BIAS;
1994
1995         amdgpu_smartshift_bias = bias;
1996         r = count;
1997
1998         /* TODO: update bias level with SMU message */
1999
2000 out:
2001         pm_runtime_mark_last_busy(ddev->dev);
2002         pm_runtime_put_autosuspend(ddev->dev);
2003         return r;
2004 }
2005
2006
2007 static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2008                                 uint32_t mask, enum amdgpu_device_attr_states *states)
2009 {
2010         if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
2011                 *states = ATTR_STATE_UNSUPPORTED;
2012
2013         return 0;
2014 }
2015
2016 static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2017                                uint32_t mask, enum amdgpu_device_attr_states *states)
2018 {
2019         uint32_t ss_power, size;
2020
2021         if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
2022                 *states = ATTR_STATE_UNSUPPORTED;
2023         else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
2024                  (void *)&ss_power, &size))
2025                 *states = ATTR_STATE_UNSUPPORTED;
2026         else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
2027                  (void *)&ss_power, &size))
2028                 *states = ATTR_STATE_UNSUPPORTED;
2029
2030         return 0;
2031 }
2032
2033 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
2034         AMDGPU_DEVICE_ATTR_RW(power_dpm_state,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2035         AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,        ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2036         AMDGPU_DEVICE_ATTR_RO(pp_num_states,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2037         AMDGPU_DEVICE_ATTR_RO(pp_cur_state,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2038         AMDGPU_DEVICE_ATTR_RW(pp_force_state,                           ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2039         AMDGPU_DEVICE_ATTR_RW(pp_table,                                 ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2040         AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2041         AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2042         AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2043         AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2044         AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2045         AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk1,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2046         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2047         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk1,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2048         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk,                           ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2049         AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2050         AMDGPU_DEVICE_ATTR_RW(pp_sclk_od,                               ATTR_FLAG_BASIC),
2051         AMDGPU_DEVICE_ATTR_RW(pp_mclk_od,                               ATTR_FLAG_BASIC),
2052         AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode,                    ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2053         AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage,                        ATTR_FLAG_BASIC),
2054         AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent,                         ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2055         AMDGPU_DEVICE_ATTR_RO(mem_busy_percent,                         ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2056         AMDGPU_DEVICE_ATTR_RO(pcie_bw,                                  ATTR_FLAG_BASIC),
2057         AMDGPU_DEVICE_ATTR_RW(pp_features,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2058         AMDGPU_DEVICE_ATTR_RO(unique_id,                                ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2059         AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging,               ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2060         AMDGPU_DEVICE_ATTR_RW(apu_thermal_cap,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2061         AMDGPU_DEVICE_ATTR_RO(gpu_metrics,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2062         AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power,                     ATTR_FLAG_BASIC,
2063                               .attr_update = ss_power_attr_update),
2064         AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power,                    ATTR_FLAG_BASIC,
2065                               .attr_update = ss_power_attr_update),
2066         AMDGPU_DEVICE_ATTR_RW(smartshift_bias,                          ATTR_FLAG_BASIC,
2067                               .attr_update = ss_bias_attr_update),
2068 };
2069
2070 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2071                                uint32_t mask, enum amdgpu_device_attr_states *states)
2072 {
2073         struct device_attribute *dev_attr = &attr->dev_attr;
2074         uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0];
2075         uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
2076         const char *attr_name = dev_attr->attr.name;
2077
2078         if (!(attr->flags & mask)) {
2079                 *states = ATTR_STATE_UNSUPPORTED;
2080                 return 0;
2081         }
2082
2083 #define DEVICE_ATTR_IS(_name)   (!strcmp(attr_name, #_name))
2084
2085         if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
2086                 if (gc_ver < IP_VERSION(9, 0, 0))
2087                         *states = ATTR_STATE_UNSUPPORTED;
2088         } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2089                 if (gc_ver < IP_VERSION(9, 0, 0) ||
2090                     gc_ver == IP_VERSION(9, 4, 1) ||
2091                     gc_ver == IP_VERSION(9, 4, 2))
2092                         *states = ATTR_STATE_UNSUPPORTED;
2093         } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
2094                 if (mp1_ver < IP_VERSION(10, 0, 0))
2095                         *states = ATTR_STATE_UNSUPPORTED;
2096         } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
2097                 *states = ATTR_STATE_UNSUPPORTED;
2098                 if (amdgpu_dpm_is_overdrive_supported(adev))
2099                         *states = ATTR_STATE_SUPPORTED;
2100         } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
2101                 if (adev->flags & AMD_IS_APU || gc_ver == IP_VERSION(9, 0, 1))
2102                         *states = ATTR_STATE_UNSUPPORTED;
2103         } else if (DEVICE_ATTR_IS(pcie_bw)) {
2104                 /* PCIe Perf counters won't work on APU nodes */
2105                 if (adev->flags & AMD_IS_APU)
2106                         *states = ATTR_STATE_UNSUPPORTED;
2107         } else if (DEVICE_ATTR_IS(unique_id)) {
2108                 switch (gc_ver) {
2109                 case IP_VERSION(9, 0, 1):
2110                 case IP_VERSION(9, 4, 0):
2111                 case IP_VERSION(9, 4, 1):
2112                 case IP_VERSION(9, 4, 2):
2113                 case IP_VERSION(10, 3, 0):
2114                 case IP_VERSION(11, 0, 0):
2115                 case IP_VERSION(11, 0, 1):
2116                 case IP_VERSION(11, 0, 2):
2117                         *states = ATTR_STATE_SUPPORTED;
2118                         break;
2119                 default:
2120                         *states = ATTR_STATE_UNSUPPORTED;
2121                 }
2122         } else if (DEVICE_ATTR_IS(pp_features)) {
2123                 if (adev->flags & AMD_IS_APU || gc_ver < IP_VERSION(9, 0, 0))
2124                         *states = ATTR_STATE_UNSUPPORTED;
2125         } else if (DEVICE_ATTR_IS(gpu_metrics)) {
2126                 if (gc_ver < IP_VERSION(9, 1, 0))
2127                         *states = ATTR_STATE_UNSUPPORTED;
2128         } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
2129                 if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2130                       gc_ver == IP_VERSION(10, 3, 0) ||
2131                       gc_ver == IP_VERSION(10, 1, 2) ||
2132                       gc_ver == IP_VERSION(11, 0, 0) ||
2133                       gc_ver == IP_VERSION(11, 0, 2) ||
2134                       gc_ver == IP_VERSION(11, 0, 3)))
2135                         *states = ATTR_STATE_UNSUPPORTED;
2136         } else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) {
2137                 if (!((gc_ver == IP_VERSION(10, 3, 1) ||
2138                            gc_ver == IP_VERSION(10, 3, 0) ||
2139                            gc_ver == IP_VERSION(11, 0, 2) ||
2140                            gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
2141                         *states = ATTR_STATE_UNSUPPORTED;
2142         } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
2143                 if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2144                       gc_ver == IP_VERSION(10, 3, 0) ||
2145                       gc_ver == IP_VERSION(10, 1, 2) ||
2146                       gc_ver == IP_VERSION(11, 0, 0) ||
2147                       gc_ver == IP_VERSION(11, 0, 2) ||
2148                       gc_ver == IP_VERSION(11, 0, 3)))
2149                         *states = ATTR_STATE_UNSUPPORTED;
2150         } else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) {
2151                 if (!((gc_ver == IP_VERSION(10, 3, 1) ||
2152                            gc_ver == IP_VERSION(10, 3, 0) ||
2153                            gc_ver == IP_VERSION(11, 0, 2) ||
2154                            gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
2155                         *states = ATTR_STATE_UNSUPPORTED;
2156         } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
2157                 if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP)
2158                         *states = ATTR_STATE_UNSUPPORTED;
2159                 else if (gc_ver == IP_VERSION(10, 3, 0) && amdgpu_sriov_vf(adev))
2160                         *states = ATTR_STATE_UNSUPPORTED;
2161         }
2162
2163         switch (gc_ver) {
2164         case IP_VERSION(9, 4, 1):
2165         case IP_VERSION(9, 4, 2):
2166                 /* the Mi series card does not support standalone mclk/socclk/fclk level setting */
2167                 if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
2168                     DEVICE_ATTR_IS(pp_dpm_socclk) ||
2169                     DEVICE_ATTR_IS(pp_dpm_fclk)) {
2170                         dev_attr->attr.mode &= ~S_IWUGO;
2171                         dev_attr->store = NULL;
2172                 }
2173                 break;
2174         case IP_VERSION(10, 3, 0):
2175                 if (DEVICE_ATTR_IS(power_dpm_force_performance_level) &&
2176                     amdgpu_sriov_vf(adev)) {
2177                         dev_attr->attr.mode &= ~0222;
2178                         dev_attr->store = NULL;
2179                 }
2180                 break;
2181         default:
2182                 break;
2183         }
2184
2185         if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2186                 /* SMU MP1 does not support dcefclk level setting */
2187                 if (gc_ver >= IP_VERSION(10, 0, 0)) {
2188                         dev_attr->attr.mode &= ~S_IWUGO;
2189                         dev_attr->store = NULL;
2190                 }
2191         }
2192
2193         /* setting should not be allowed from VF if not in one VF mode */
2194         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
2195                 dev_attr->attr.mode &= ~S_IWUGO;
2196                 dev_attr->store = NULL;
2197         }
2198
2199 #undef DEVICE_ATTR_IS
2200
2201         return 0;
2202 }
2203
2204
2205 static int amdgpu_device_attr_create(struct amdgpu_device *adev,
2206                                      struct amdgpu_device_attr *attr,
2207                                      uint32_t mask, struct list_head *attr_list)
2208 {
2209         int ret = 0;
2210         struct device_attribute *dev_attr = &attr->dev_attr;
2211         const char *name = dev_attr->attr.name;
2212         enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
2213         struct amdgpu_device_attr_entry *attr_entry;
2214
2215         int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2216                            uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
2217
2218         BUG_ON(!attr);
2219
2220         attr_update = attr->attr_update ? attr->attr_update : default_attr_update;
2221
2222         ret = attr_update(adev, attr, mask, &attr_states);
2223         if (ret) {
2224                 dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
2225                         name, ret);
2226                 return ret;
2227         }
2228
2229         if (attr_states == ATTR_STATE_UNSUPPORTED)
2230                 return 0;
2231
2232         ret = device_create_file(adev->dev, dev_attr);
2233         if (ret) {
2234                 dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
2235                         name, ret);
2236         }
2237
2238         attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
2239         if (!attr_entry)
2240                 return -ENOMEM;
2241
2242         attr_entry->attr = attr;
2243         INIT_LIST_HEAD(&attr_entry->entry);
2244
2245         list_add_tail(&attr_entry->entry, attr_list);
2246
2247         return ret;
2248 }
2249
2250 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
2251 {
2252         struct device_attribute *dev_attr = &attr->dev_attr;
2253
2254         device_remove_file(adev->dev, dev_attr);
2255 }
2256
2257 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2258                                              struct list_head *attr_list);
2259
2260 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
2261                                             struct amdgpu_device_attr *attrs,
2262                                             uint32_t counts,
2263                                             uint32_t mask,
2264                                             struct list_head *attr_list)
2265 {
2266         int ret = 0;
2267         uint32_t i = 0;
2268
2269         for (i = 0; i < counts; i++) {
2270                 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
2271                 if (ret)
2272                         goto failed;
2273         }
2274
2275         return 0;
2276
2277 failed:
2278         amdgpu_device_attr_remove_groups(adev, attr_list);
2279
2280         return ret;
2281 }
2282
2283 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2284                                              struct list_head *attr_list)
2285 {
2286         struct amdgpu_device_attr_entry *entry, *entry_tmp;
2287
2288         if (list_empty(attr_list))
2289                 return ;
2290
2291         list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
2292                 amdgpu_device_attr_remove(adev, entry->attr);
2293                 list_del(&entry->entry);
2294                 kfree(entry);
2295         }
2296 }
2297
2298 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
2299                                       struct device_attribute *attr,
2300                                       char *buf)
2301 {
2302         struct amdgpu_device *adev = dev_get_drvdata(dev);
2303         int channel = to_sensor_dev_attr(attr)->index;
2304         int r, temp = 0, size = sizeof(temp);
2305
2306         if (amdgpu_in_reset(adev))
2307                 return -EPERM;
2308         if (adev->in_suspend && !adev->in_runpm)
2309                 return -EPERM;
2310
2311         if (channel >= PP_TEMP_MAX)
2312                 return -EINVAL;
2313
2314         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2315         if (r < 0) {
2316                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2317                 return r;
2318         }
2319
2320         switch (channel) {
2321         case PP_TEMP_JUNCTION:
2322                 /* get current junction temperature */
2323                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
2324                                            (void *)&temp, &size);
2325                 break;
2326         case PP_TEMP_EDGE:
2327                 /* get current edge temperature */
2328                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
2329                                            (void *)&temp, &size);
2330                 break;
2331         case PP_TEMP_MEM:
2332                 /* get current memory temperature */
2333                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
2334                                            (void *)&temp, &size);
2335                 break;
2336         default:
2337                 r = -EINVAL;
2338                 break;
2339         }
2340
2341         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2342         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2343
2344         if (r)
2345                 return r;
2346
2347         return sysfs_emit(buf, "%d\n", temp);
2348 }
2349
2350 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
2351                                              struct device_attribute *attr,
2352                                              char *buf)
2353 {
2354         struct amdgpu_device *adev = dev_get_drvdata(dev);
2355         int hyst = to_sensor_dev_attr(attr)->index;
2356         int temp;
2357
2358         if (hyst)
2359                 temp = adev->pm.dpm.thermal.min_temp;
2360         else
2361                 temp = adev->pm.dpm.thermal.max_temp;
2362
2363         return sysfs_emit(buf, "%d\n", temp);
2364 }
2365
2366 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
2367                                              struct device_attribute *attr,
2368                                              char *buf)
2369 {
2370         struct amdgpu_device *adev = dev_get_drvdata(dev);
2371         int hyst = to_sensor_dev_attr(attr)->index;
2372         int temp;
2373
2374         if (hyst)
2375                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
2376         else
2377                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
2378
2379         return sysfs_emit(buf, "%d\n", temp);
2380 }
2381
2382 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
2383                                              struct device_attribute *attr,
2384                                              char *buf)
2385 {
2386         struct amdgpu_device *adev = dev_get_drvdata(dev);
2387         int hyst = to_sensor_dev_attr(attr)->index;
2388         int temp;
2389
2390         if (hyst)
2391                 temp = adev->pm.dpm.thermal.min_mem_temp;
2392         else
2393                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
2394
2395         return sysfs_emit(buf, "%d\n", temp);
2396 }
2397
2398 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
2399                                              struct device_attribute *attr,
2400                                              char *buf)
2401 {
2402         int channel = to_sensor_dev_attr(attr)->index;
2403
2404         if (channel >= PP_TEMP_MAX)
2405                 return -EINVAL;
2406
2407         return sysfs_emit(buf, "%s\n", temp_label[channel].label);
2408 }
2409
2410 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
2411                                              struct device_attribute *attr,
2412                                              char *buf)
2413 {
2414         struct amdgpu_device *adev = dev_get_drvdata(dev);
2415         int channel = to_sensor_dev_attr(attr)->index;
2416         int temp = 0;
2417
2418         if (channel >= PP_TEMP_MAX)
2419                 return -EINVAL;
2420
2421         switch (channel) {
2422         case PP_TEMP_JUNCTION:
2423                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
2424                 break;
2425         case PP_TEMP_EDGE:
2426                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
2427                 break;
2428         case PP_TEMP_MEM:
2429                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
2430                 break;
2431         }
2432
2433         return sysfs_emit(buf, "%d\n", temp);
2434 }
2435
2436 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
2437                                             struct device_attribute *attr,
2438                                             char *buf)
2439 {
2440         struct amdgpu_device *adev = dev_get_drvdata(dev);
2441         u32 pwm_mode = 0;
2442         int ret;
2443
2444         if (amdgpu_in_reset(adev))
2445                 return -EPERM;
2446         if (adev->in_suspend && !adev->in_runpm)
2447                 return -EPERM;
2448
2449         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2450         if (ret < 0) {
2451                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2452                 return ret;
2453         }
2454
2455         ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2456
2457         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2458         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2459
2460         if (ret)
2461                 return -EINVAL;
2462
2463         return sysfs_emit(buf, "%u\n", pwm_mode);
2464 }
2465
2466 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2467                                             struct device_attribute *attr,
2468                                             const char *buf,
2469                                             size_t count)
2470 {
2471         struct amdgpu_device *adev = dev_get_drvdata(dev);
2472         int err, ret;
2473         int value;
2474
2475         if (amdgpu_in_reset(adev))
2476                 return -EPERM;
2477         if (adev->in_suspend && !adev->in_runpm)
2478                 return -EPERM;
2479
2480         err = kstrtoint(buf, 10, &value);
2481         if (err)
2482                 return err;
2483
2484         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2485         if (ret < 0) {
2486                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2487                 return ret;
2488         }
2489
2490         ret = amdgpu_dpm_set_fan_control_mode(adev, value);
2491
2492         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2493         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2494
2495         if (ret)
2496                 return -EINVAL;
2497
2498         return count;
2499 }
2500
2501 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2502                                          struct device_attribute *attr,
2503                                          char *buf)
2504 {
2505         return sysfs_emit(buf, "%i\n", 0);
2506 }
2507
2508 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2509                                          struct device_attribute *attr,
2510                                          char *buf)
2511 {
2512         return sysfs_emit(buf, "%i\n", 255);
2513 }
2514
2515 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2516                                      struct device_attribute *attr,
2517                                      const char *buf, size_t count)
2518 {
2519         struct amdgpu_device *adev = dev_get_drvdata(dev);
2520         int err;
2521         u32 value;
2522         u32 pwm_mode;
2523
2524         if (amdgpu_in_reset(adev))
2525                 return -EPERM;
2526         if (adev->in_suspend && !adev->in_runpm)
2527                 return -EPERM;
2528
2529         err = kstrtou32(buf, 10, &value);
2530         if (err)
2531                 return err;
2532
2533         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2534         if (err < 0) {
2535                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2536                 return err;
2537         }
2538
2539         err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2540         if (err)
2541                 goto out;
2542
2543         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2544                 pr_info("manual fan speed control should be enabled first\n");
2545                 err = -EINVAL;
2546                 goto out;
2547         }
2548
2549         err = amdgpu_dpm_set_fan_speed_pwm(adev, value);
2550
2551 out:
2552         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2553         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2554
2555         if (err)
2556                 return err;
2557
2558         return count;
2559 }
2560
2561 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2562                                      struct device_attribute *attr,
2563                                      char *buf)
2564 {
2565         struct amdgpu_device *adev = dev_get_drvdata(dev);
2566         int err;
2567         u32 speed = 0;
2568
2569         if (amdgpu_in_reset(adev))
2570                 return -EPERM;
2571         if (adev->in_suspend && !adev->in_runpm)
2572                 return -EPERM;
2573
2574         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2575         if (err < 0) {
2576                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2577                 return err;
2578         }
2579
2580         err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed);
2581
2582         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2583         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2584
2585         if (err)
2586                 return err;
2587
2588         return sysfs_emit(buf, "%i\n", speed);
2589 }
2590
2591 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2592                                            struct device_attribute *attr,
2593                                            char *buf)
2594 {
2595         struct amdgpu_device *adev = dev_get_drvdata(dev);
2596         int err;
2597         u32 speed = 0;
2598
2599         if (amdgpu_in_reset(adev))
2600                 return -EPERM;
2601         if (adev->in_suspend && !adev->in_runpm)
2602                 return -EPERM;
2603
2604         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2605         if (err < 0) {
2606                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2607                 return err;
2608         }
2609
2610         err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2611
2612         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2613         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2614
2615         if (err)
2616                 return err;
2617
2618         return sysfs_emit(buf, "%i\n", speed);
2619 }
2620
2621 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2622                                          struct device_attribute *attr,
2623                                          char *buf)
2624 {
2625         struct amdgpu_device *adev = dev_get_drvdata(dev);
2626         u32 min_rpm = 0;
2627         u32 size = sizeof(min_rpm);
2628         int r;
2629
2630         if (amdgpu_in_reset(adev))
2631                 return -EPERM;
2632         if (adev->in_suspend && !adev->in_runpm)
2633                 return -EPERM;
2634
2635         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2636         if (r < 0) {
2637                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2638                 return r;
2639         }
2640
2641         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2642                                    (void *)&min_rpm, &size);
2643
2644         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2645         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2646
2647         if (r)
2648                 return r;
2649
2650         return sysfs_emit(buf, "%d\n", min_rpm);
2651 }
2652
2653 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2654                                          struct device_attribute *attr,
2655                                          char *buf)
2656 {
2657         struct amdgpu_device *adev = dev_get_drvdata(dev);
2658         u32 max_rpm = 0;
2659         u32 size = sizeof(max_rpm);
2660         int r;
2661
2662         if (amdgpu_in_reset(adev))
2663                 return -EPERM;
2664         if (adev->in_suspend && !adev->in_runpm)
2665                 return -EPERM;
2666
2667         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2668         if (r < 0) {
2669                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2670                 return r;
2671         }
2672
2673         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2674                                    (void *)&max_rpm, &size);
2675
2676         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2677         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2678
2679         if (r)
2680                 return r;
2681
2682         return sysfs_emit(buf, "%d\n", max_rpm);
2683 }
2684
2685 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2686                                            struct device_attribute *attr,
2687                                            char *buf)
2688 {
2689         struct amdgpu_device *adev = dev_get_drvdata(dev);
2690         int err;
2691         u32 rpm = 0;
2692
2693         if (amdgpu_in_reset(adev))
2694                 return -EPERM;
2695         if (adev->in_suspend && !adev->in_runpm)
2696                 return -EPERM;
2697
2698         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2699         if (err < 0) {
2700                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2701                 return err;
2702         }
2703
2704         err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2705
2706         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2707         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2708
2709         if (err)
2710                 return err;
2711
2712         return sysfs_emit(buf, "%i\n", rpm);
2713 }
2714
2715 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2716                                      struct device_attribute *attr,
2717                                      const char *buf, size_t count)
2718 {
2719         struct amdgpu_device *adev = dev_get_drvdata(dev);
2720         int err;
2721         u32 value;
2722         u32 pwm_mode;
2723
2724         if (amdgpu_in_reset(adev))
2725                 return -EPERM;
2726         if (adev->in_suspend && !adev->in_runpm)
2727                 return -EPERM;
2728
2729         err = kstrtou32(buf, 10, &value);
2730         if (err)
2731                 return err;
2732
2733         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2734         if (err < 0) {
2735                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2736                 return err;
2737         }
2738
2739         err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2740         if (err)
2741                 goto out;
2742
2743         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2744                 err = -ENODATA;
2745                 goto out;
2746         }
2747
2748         err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2749
2750 out:
2751         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2752         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2753
2754         if (err)
2755                 return err;
2756
2757         return count;
2758 }
2759
2760 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2761                                             struct device_attribute *attr,
2762                                             char *buf)
2763 {
2764         struct amdgpu_device *adev = dev_get_drvdata(dev);
2765         u32 pwm_mode = 0;
2766         int ret;
2767
2768         if (amdgpu_in_reset(adev))
2769                 return -EPERM;
2770         if (adev->in_suspend && !adev->in_runpm)
2771                 return -EPERM;
2772
2773         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2774         if (ret < 0) {
2775                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2776                 return ret;
2777         }
2778
2779         ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2780
2781         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2782         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2783
2784         if (ret)
2785                 return -EINVAL;
2786
2787         return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2788 }
2789
2790 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2791                                             struct device_attribute *attr,
2792                                             const char *buf,
2793                                             size_t count)
2794 {
2795         struct amdgpu_device *adev = dev_get_drvdata(dev);
2796         int err;
2797         int value;
2798         u32 pwm_mode;
2799
2800         if (amdgpu_in_reset(adev))
2801                 return -EPERM;
2802         if (adev->in_suspend && !adev->in_runpm)
2803                 return -EPERM;
2804
2805         err = kstrtoint(buf, 10, &value);
2806         if (err)
2807                 return err;
2808
2809         if (value == 0)
2810                 pwm_mode = AMD_FAN_CTRL_AUTO;
2811         else if (value == 1)
2812                 pwm_mode = AMD_FAN_CTRL_MANUAL;
2813         else
2814                 return -EINVAL;
2815
2816         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2817         if (err < 0) {
2818                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2819                 return err;
2820         }
2821
2822         err = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2823
2824         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2825         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2826
2827         if (err)
2828                 return -EINVAL;
2829
2830         return count;
2831 }
2832
2833 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2834                                         struct device_attribute *attr,
2835                                         char *buf)
2836 {
2837         struct amdgpu_device *adev = dev_get_drvdata(dev);
2838         u32 vddgfx;
2839         int r, size = sizeof(vddgfx);
2840
2841         if (amdgpu_in_reset(adev))
2842                 return -EPERM;
2843         if (adev->in_suspend && !adev->in_runpm)
2844                 return -EPERM;
2845
2846         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2847         if (r < 0) {
2848                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2849                 return r;
2850         }
2851
2852         /* get the voltage */
2853         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
2854                                    (void *)&vddgfx, &size);
2855
2856         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2857         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2858
2859         if (r)
2860                 return r;
2861
2862         return sysfs_emit(buf, "%d\n", vddgfx);
2863 }
2864
2865 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2866                                               struct device_attribute *attr,
2867                                               char *buf)
2868 {
2869         return sysfs_emit(buf, "vddgfx\n");
2870 }
2871
2872 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2873                                        struct device_attribute *attr,
2874                                        char *buf)
2875 {
2876         struct amdgpu_device *adev = dev_get_drvdata(dev);
2877         u32 vddnb;
2878         int r, size = sizeof(vddnb);
2879
2880         if (amdgpu_in_reset(adev))
2881                 return -EPERM;
2882         if (adev->in_suspend && !adev->in_runpm)
2883                 return -EPERM;
2884
2885         /* only APUs have vddnb */
2886         if  (!(adev->flags & AMD_IS_APU))
2887                 return -EINVAL;
2888
2889         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2890         if (r < 0) {
2891                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2892                 return r;
2893         }
2894
2895         /* get the voltage */
2896         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
2897                                    (void *)&vddnb, &size);
2898
2899         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2900         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2901
2902         if (r)
2903                 return r;
2904
2905         return sysfs_emit(buf, "%d\n", vddnb);
2906 }
2907
2908 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2909                                               struct device_attribute *attr,
2910                                               char *buf)
2911 {
2912         return sysfs_emit(buf, "vddnb\n");
2913 }
2914
2915 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
2916                                            struct device_attribute *attr,
2917                                            char *buf)
2918 {
2919         struct amdgpu_device *adev = dev_get_drvdata(dev);
2920         u32 query = 0;
2921         int r, size = sizeof(u32);
2922         unsigned uw;
2923
2924         if (amdgpu_in_reset(adev))
2925                 return -EPERM;
2926         if (adev->in_suspend && !adev->in_runpm)
2927                 return -EPERM;
2928
2929         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2930         if (r < 0) {
2931                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2932                 return r;
2933         }
2934
2935         /* get the voltage */
2936         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
2937                                    (void *)&query, &size);
2938
2939         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2940         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2941
2942         if (r)
2943                 return r;
2944
2945         /* convert to microwatts */
2946         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2947
2948         return sysfs_emit(buf, "%u\n", uw);
2949 }
2950
2951 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
2952                                          struct device_attribute *attr,
2953                                          char *buf)
2954 {
2955         return sysfs_emit(buf, "%i\n", 0);
2956 }
2957
2958
2959 static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev,
2960                                         struct device_attribute *attr,
2961                                         char *buf,
2962                                         enum pp_power_limit_level pp_limit_level)
2963 {
2964         struct amdgpu_device *adev = dev_get_drvdata(dev);
2965         enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
2966         uint32_t limit;
2967         ssize_t size;
2968         int r;
2969
2970         if (amdgpu_in_reset(adev))
2971                 return -EPERM;
2972         if (adev->in_suspend && !adev->in_runpm)
2973                 return -EPERM;
2974
2975         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2976         if (r < 0) {
2977                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2978                 return r;
2979         }
2980
2981         r = amdgpu_dpm_get_power_limit(adev, &limit,
2982                                       pp_limit_level, power_type);
2983
2984         if (!r)
2985                 size = sysfs_emit(buf, "%u\n", limit * 1000000);
2986         else
2987                 size = sysfs_emit(buf, "\n");
2988
2989         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2990         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2991
2992         return size;
2993 }
2994
2995
2996 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2997                                          struct device_attribute *attr,
2998                                          char *buf)
2999 {
3000         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX);
3001
3002 }
3003
3004 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
3005                                          struct device_attribute *attr,
3006                                          char *buf)
3007 {
3008         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT);
3009
3010 }
3011
3012 static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
3013                                          struct device_attribute *attr,
3014                                          char *buf)
3015 {
3016         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT);
3017
3018 }
3019
3020 static ssize_t amdgpu_hwmon_show_power_label(struct device *dev,
3021                                          struct device_attribute *attr,
3022                                          char *buf)
3023 {
3024         struct amdgpu_device *adev = dev_get_drvdata(dev);
3025         uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
3026
3027         if (gc_ver == IP_VERSION(10, 3, 1))
3028                 return sysfs_emit(buf, "%s\n",
3029                                   to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ?
3030                                   "fastPPT" : "slowPPT");
3031         else
3032                 return sysfs_emit(buf, "PPT\n");
3033 }
3034
3035 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
3036                 struct device_attribute *attr,
3037                 const char *buf,
3038                 size_t count)
3039 {
3040         struct amdgpu_device *adev = dev_get_drvdata(dev);
3041         int limit_type = to_sensor_dev_attr(attr)->index;
3042         int err;
3043         u32 value;
3044
3045         if (amdgpu_in_reset(adev))
3046                 return -EPERM;
3047         if (adev->in_suspend && !adev->in_runpm)
3048                 return -EPERM;
3049
3050         if (amdgpu_sriov_vf(adev))
3051                 return -EINVAL;
3052
3053         err = kstrtou32(buf, 10, &value);
3054         if (err)
3055                 return err;
3056
3057         value = value / 1000000; /* convert to Watt */
3058         value |= limit_type << 24;
3059
3060         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3061         if (err < 0) {
3062                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3063                 return err;
3064         }
3065
3066         err = amdgpu_dpm_set_power_limit(adev, value);
3067
3068         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3069         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3070
3071         if (err)
3072                 return err;
3073
3074         return count;
3075 }
3076
3077 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
3078                                       struct device_attribute *attr,
3079                                       char *buf)
3080 {
3081         struct amdgpu_device *adev = dev_get_drvdata(dev);
3082         uint32_t sclk;
3083         int r, size = sizeof(sclk);
3084
3085         if (amdgpu_in_reset(adev))
3086                 return -EPERM;
3087         if (adev->in_suspend && !adev->in_runpm)
3088                 return -EPERM;
3089
3090         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3091         if (r < 0) {
3092                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3093                 return r;
3094         }
3095
3096         /* get the sclk */
3097         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
3098                                    (void *)&sclk, &size);
3099
3100         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3101         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3102
3103         if (r)
3104                 return r;
3105
3106         return sysfs_emit(buf, "%u\n", sclk * 10 * 1000);
3107 }
3108
3109 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
3110                                             struct device_attribute *attr,
3111                                             char *buf)
3112 {
3113         return sysfs_emit(buf, "sclk\n");
3114 }
3115
3116 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
3117                                       struct device_attribute *attr,
3118                                       char *buf)
3119 {
3120         struct amdgpu_device *adev = dev_get_drvdata(dev);
3121         uint32_t mclk;
3122         int r, size = sizeof(mclk);
3123
3124         if (amdgpu_in_reset(adev))
3125                 return -EPERM;
3126         if (adev->in_suspend && !adev->in_runpm)
3127                 return -EPERM;
3128
3129         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3130         if (r < 0) {
3131                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3132                 return r;
3133         }
3134
3135         /* get the sclk */
3136         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
3137                                    (void *)&mclk, &size);
3138
3139         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3140         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3141
3142         if (r)
3143                 return r;
3144
3145         return sysfs_emit(buf, "%u\n", mclk * 10 * 1000);
3146 }
3147
3148 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
3149                                             struct device_attribute *attr,
3150                                             char *buf)
3151 {
3152         return sysfs_emit(buf, "mclk\n");
3153 }
3154
3155 /**
3156  * DOC: hwmon
3157  *
3158  * The amdgpu driver exposes the following sensor interfaces:
3159  *
3160  * - GPU temperature (via the on-die sensor)
3161  *
3162  * - GPU voltage
3163  *
3164  * - Northbridge voltage (APUs only)
3165  *
3166  * - GPU power
3167  *
3168  * - GPU fan
3169  *
3170  * - GPU gfx/compute engine clock
3171  *
3172  * - GPU memory clock (dGPU only)
3173  *
3174  * hwmon interfaces for GPU temperature:
3175  *
3176  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
3177  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
3178  *
3179  * - temp[1-3]_label: temperature channel label
3180  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
3181  *
3182  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
3183  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
3184  *
3185  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
3186  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
3187  *
3188  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
3189  *   - these are supported on SOC15 dGPUs only
3190  *
3191  * hwmon interfaces for GPU voltage:
3192  *
3193  * - in0_input: the voltage on the GPU in millivolts
3194  *
3195  * - in1_input: the voltage on the Northbridge in millivolts
3196  *
3197  * hwmon interfaces for GPU power:
3198  *
3199  * - power1_average: average power used by the SoC in microWatts.  On APUs this includes the CPU.
3200  *
3201  * - power1_cap_min: minimum cap supported in microWatts
3202  *
3203  * - power1_cap_max: maximum cap supported in microWatts
3204  *
3205  * - power1_cap: selected power cap in microWatts
3206  *
3207  * hwmon interfaces for GPU fan:
3208  *
3209  * - pwm1: pulse width modulation fan level (0-255)
3210  *
3211  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
3212  *
3213  * - pwm1_min: pulse width modulation fan control minimum level (0)
3214  *
3215  * - pwm1_max: pulse width modulation fan control maximum level (255)
3216  *
3217  * - fan1_min: a minimum value Unit: revolution/min (RPM)
3218  *
3219  * - fan1_max: a maximum value Unit: revolution/max (RPM)
3220  *
3221  * - fan1_input: fan speed in RPM
3222  *
3223  * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
3224  *
3225  * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
3226  *
3227  * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time.
3228  *       That will get the former one overridden.
3229  *
3230  * hwmon interfaces for GPU clocks:
3231  *
3232  * - freq1_input: the gfx/compute clock in hertz
3233  *
3234  * - freq2_input: the memory clock in hertz
3235  *
3236  * You can use hwmon tools like sensors to view this information on your system.
3237  *
3238  */
3239
3240 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
3241 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
3242 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
3243 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
3244 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
3245 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
3246 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
3247 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
3248 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
3249 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
3250 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
3251 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
3252 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
3253 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
3254 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
3255 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
3256 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
3257 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
3258 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
3259 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
3260 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
3261 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
3262 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
3263 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
3264 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
3265 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
3266 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
3267 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
3268 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
3269 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
3270 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
3271 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
3272 static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0);
3273 static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0);
3274 static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1);
3275 static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1);
3276 static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1);
3277 static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1);
3278 static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1);
3279 static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1);
3280 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
3281 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
3282 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
3283 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
3284
3285 static struct attribute *hwmon_attributes[] = {
3286         &sensor_dev_attr_temp1_input.dev_attr.attr,
3287         &sensor_dev_attr_temp1_crit.dev_attr.attr,
3288         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
3289         &sensor_dev_attr_temp2_input.dev_attr.attr,
3290         &sensor_dev_attr_temp2_crit.dev_attr.attr,
3291         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
3292         &sensor_dev_attr_temp3_input.dev_attr.attr,
3293         &sensor_dev_attr_temp3_crit.dev_attr.attr,
3294         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
3295         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
3296         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
3297         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
3298         &sensor_dev_attr_temp1_label.dev_attr.attr,
3299         &sensor_dev_attr_temp2_label.dev_attr.attr,
3300         &sensor_dev_attr_temp3_label.dev_attr.attr,
3301         &sensor_dev_attr_pwm1.dev_attr.attr,
3302         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
3303         &sensor_dev_attr_pwm1_min.dev_attr.attr,
3304         &sensor_dev_attr_pwm1_max.dev_attr.attr,
3305         &sensor_dev_attr_fan1_input.dev_attr.attr,
3306         &sensor_dev_attr_fan1_min.dev_attr.attr,
3307         &sensor_dev_attr_fan1_max.dev_attr.attr,
3308         &sensor_dev_attr_fan1_target.dev_attr.attr,
3309         &sensor_dev_attr_fan1_enable.dev_attr.attr,
3310         &sensor_dev_attr_in0_input.dev_attr.attr,
3311         &sensor_dev_attr_in0_label.dev_attr.attr,
3312         &sensor_dev_attr_in1_input.dev_attr.attr,
3313         &sensor_dev_attr_in1_label.dev_attr.attr,
3314         &sensor_dev_attr_power1_average.dev_attr.attr,
3315         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
3316         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
3317         &sensor_dev_attr_power1_cap.dev_attr.attr,
3318         &sensor_dev_attr_power1_cap_default.dev_attr.attr,
3319         &sensor_dev_attr_power1_label.dev_attr.attr,
3320         &sensor_dev_attr_power2_average.dev_attr.attr,
3321         &sensor_dev_attr_power2_cap_max.dev_attr.attr,
3322         &sensor_dev_attr_power2_cap_min.dev_attr.attr,
3323         &sensor_dev_attr_power2_cap.dev_attr.attr,
3324         &sensor_dev_attr_power2_cap_default.dev_attr.attr,
3325         &sensor_dev_attr_power2_label.dev_attr.attr,
3326         &sensor_dev_attr_freq1_input.dev_attr.attr,
3327         &sensor_dev_attr_freq1_label.dev_attr.attr,
3328         &sensor_dev_attr_freq2_input.dev_attr.attr,
3329         &sensor_dev_attr_freq2_label.dev_attr.attr,
3330         NULL
3331 };
3332
3333 static umode_t hwmon_attributes_visible(struct kobject *kobj,
3334                                         struct attribute *attr, int index)
3335 {
3336         struct device *dev = kobj_to_dev(kobj);
3337         struct amdgpu_device *adev = dev_get_drvdata(dev);
3338         umode_t effective_mode = attr->mode;
3339         uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
3340
3341         /* under multi-vf mode, the hwmon attributes are all not supported */
3342         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
3343                 return 0;
3344
3345         /* under pp one vf mode manage of hwmon attributes is not supported */
3346         if (amdgpu_sriov_is_pp_one_vf(adev))
3347                 effective_mode &= ~S_IWUSR;
3348
3349         /* Skip fan attributes if fan is not present */
3350         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3351             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3352             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3353             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3354             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3355             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3356             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3357             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3358             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3359                 return 0;
3360
3361         /* Skip fan attributes on APU */
3362         if ((adev->flags & AMD_IS_APU) &&
3363             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3364              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3365              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3366              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3367              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3368              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3369              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3370              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3371              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3372                 return 0;
3373
3374         /* Skip crit temp on APU */
3375         if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) ||
3376             (gc_ver == IP_VERSION(9, 4, 3))) &&
3377             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3378              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
3379                 return 0;
3380
3381         /* Skip limit attributes if DPM is not enabled */
3382         if (!adev->pm.dpm_enabled &&
3383             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3384              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
3385              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3386              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3387              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3388              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3389              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3390              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3391              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3392              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3393              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3394                 return 0;
3395
3396         /* mask fan attributes if we have no bindings for this asic to expose */
3397         if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3398               attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
3399             ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) &&
3400              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
3401                 effective_mode &= ~S_IRUGO;
3402
3403         if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3404               attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
3405               ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) &&
3406               attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
3407                 effective_mode &= ~S_IWUSR;
3408
3409         /* not implemented yet for APUs other than GC 10.3.1 (vangogh) and 9.4.3 */
3410         if (((adev->family == AMDGPU_FAMILY_SI) ||
3411              ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)) &&
3412               (gc_ver != IP_VERSION(9, 4, 3)))) &&
3413             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3414              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr ||
3415              attr == &sensor_dev_attr_power1_cap.dev_attr.attr ||
3416              attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr))
3417                 return 0;
3418
3419         /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */
3420         if (((adev->family == AMDGPU_FAMILY_SI) ||
3421              ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) &&
3422             (attr == &sensor_dev_attr_power1_average.dev_attr.attr))
3423                 return 0;
3424
3425         /* hide max/min values if we can't both query and manage the fan */
3426         if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3427               (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3428               (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3429               (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) &&
3430             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3431              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
3432                 return 0;
3433
3434         if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3435              (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) &&
3436              (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3437              attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
3438                 return 0;
3439
3440         if ((adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
3441              adev->family == AMDGPU_FAMILY_KV ||        /* not implemented yet */
3442              (gc_ver == IP_VERSION(9, 4, 3))) &&
3443             (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
3444              attr == &sensor_dev_attr_in0_label.dev_attr.attr))
3445                 return 0;
3446
3447         /* only APUs other than gc 9,4,3 have vddnb */
3448         if ((!(adev->flags & AMD_IS_APU) || (gc_ver == IP_VERSION(9, 4, 3))) &&
3449             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
3450              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
3451                 return 0;
3452
3453         /* no mclk on APUs other than gc 9,4,3*/
3454         if (((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(9, 4, 3))) &&
3455             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
3456              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
3457                 return 0;
3458
3459         if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) &&
3460             (gc_ver != IP_VERSION(9, 4, 3)) &&
3461             (attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
3462              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
3463              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
3464              attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
3465                 return 0;
3466
3467         /* hotspot temperature for gc 9,4,3*/
3468         if ((gc_ver == IP_VERSION(9, 4, 3)) &&
3469             (attr == &sensor_dev_attr_temp1_input.dev_attr.attr ||
3470              attr == &sensor_dev_attr_temp1_label.dev_attr.attr))
3471                 return 0;
3472
3473         /* only SOC15 dGPUs support hotspot and mem temperatures */
3474         if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0) ||
3475             (gc_ver == IP_VERSION(9, 4, 3))) &&
3476             (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
3477              attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
3478              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
3479              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
3480              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3481              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3482              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr))
3483                 return 0;
3484
3485         /* only Vangogh has fast PPT limit and power labels */
3486         if (!(gc_ver == IP_VERSION(10, 3, 1)) &&
3487             (attr == &sensor_dev_attr_power2_average.dev_attr.attr ||
3488              attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr ||
3489              attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr ||
3490              attr == &sensor_dev_attr_power2_cap.dev_attr.attr ||
3491              attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr ||
3492              attr == &sensor_dev_attr_power2_label.dev_attr.attr))
3493                 return 0;
3494
3495         return effective_mode;
3496 }
3497
3498 static const struct attribute_group hwmon_attrgroup = {
3499         .attrs = hwmon_attributes,
3500         .is_visible = hwmon_attributes_visible,
3501 };
3502
3503 static const struct attribute_group *hwmon_groups[] = {
3504         &hwmon_attrgroup,
3505         NULL
3506 };
3507
3508 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
3509 {
3510         int ret;
3511         uint32_t mask = 0;
3512
3513         if (adev->pm.sysfs_initialized)
3514                 return 0;
3515
3516         INIT_LIST_HEAD(&adev->pm.pm_attr_list);
3517
3518         if (adev->pm.dpm_enabled == 0)
3519                 return 0;
3520
3521         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
3522                                                                    DRIVER_NAME, adev,
3523                                                                    hwmon_groups);
3524         if (IS_ERR(adev->pm.int_hwmon_dev)) {
3525                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
3526                 dev_err(adev->dev,
3527                         "Unable to register hwmon device: %d\n", ret);
3528                 return ret;
3529         }
3530
3531         switch (amdgpu_virt_get_sriov_vf_mode(adev)) {
3532         case SRIOV_VF_MODE_ONE_VF:
3533                 mask = ATTR_FLAG_ONEVF;
3534                 break;
3535         case SRIOV_VF_MODE_MULTI_VF:
3536                 mask = 0;
3537                 break;
3538         case SRIOV_VF_MODE_BARE_METAL:
3539         default:
3540                 mask = ATTR_FLAG_MASK_ALL;
3541                 break;
3542         }
3543
3544         ret = amdgpu_device_attr_create_groups(adev,
3545                                                amdgpu_device_attrs,
3546                                                ARRAY_SIZE(amdgpu_device_attrs),
3547                                                mask,
3548                                                &adev->pm.pm_attr_list);
3549         if (ret)
3550                 return ret;
3551
3552         adev->pm.sysfs_initialized = true;
3553
3554         return 0;
3555 }
3556
3557 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
3558 {
3559         if (adev->pm.int_hwmon_dev)
3560                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
3561
3562         amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
3563 }
3564
3565 /*
3566  * Debugfs info
3567  */
3568 #if defined(CONFIG_DEBUG_FS)
3569
3570 static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m,
3571                                            struct amdgpu_device *adev) {
3572         uint16_t *p_val;
3573         uint32_t size;
3574         int i;
3575         uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev);
3576
3577         if (amdgpu_dpm_is_cclk_dpm_supported(adev)) {
3578                 p_val = kcalloc(num_cpu_cores, sizeof(uint16_t),
3579                                 GFP_KERNEL);
3580
3581                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK,
3582                                             (void *)p_val, &size)) {
3583                         for (i = 0; i < num_cpu_cores; i++)
3584                                 seq_printf(m, "\t%u MHz (CPU%d)\n",
3585                                            *(p_val + i), i);
3586                 }
3587
3588                 kfree(p_val);
3589         }
3590 }
3591
3592 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3593 {
3594         uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0];
3595         uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
3596         uint32_t value;
3597         uint64_t value64 = 0;
3598         uint32_t query = 0;
3599         int size;
3600
3601         /* GPU Clocks */
3602         size = sizeof(value);
3603         seq_printf(m, "GFX Clocks and Power:\n");
3604
3605         amdgpu_debugfs_prints_cpu_info(m, adev);
3606
3607         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3608                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3609         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3610                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3611         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3612                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3613         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3614                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3615         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3616                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3617         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3618                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3619         size = sizeof(uint32_t);
3620         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
3621                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3622         size = sizeof(value);
3623         seq_printf(m, "\n");
3624
3625         /* GPU Temp */
3626         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3627                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3628
3629         /* GPU Load */
3630         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3631                 seq_printf(m, "GPU Load: %u %%\n", value);
3632         /* MEM Load */
3633         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3634                 seq_printf(m, "MEM Load: %u %%\n", value);
3635
3636         seq_printf(m, "\n");
3637
3638         /* SMC feature mask */
3639         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3640                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3641
3642         /* ASICs greater than CHIP_VEGA20 supports these sensors */
3643         if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) {
3644                 /* VCN clocks */
3645                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
3646                         if (!value) {
3647                                 seq_printf(m, "VCN: Disabled\n");
3648                         } else {
3649                                 seq_printf(m, "VCN: Enabled\n");
3650                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3651                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3652                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3653                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3654                         }
3655                 }
3656                 seq_printf(m, "\n");
3657         } else {
3658                 /* UVD clocks */
3659                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3660                         if (!value) {
3661                                 seq_printf(m, "UVD: Disabled\n");
3662                         } else {
3663                                 seq_printf(m, "UVD: Enabled\n");
3664                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3665                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3666                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3667                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3668                         }
3669                 }
3670                 seq_printf(m, "\n");
3671
3672                 /* VCE clocks */
3673                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3674                         if (!value) {
3675                                 seq_printf(m, "VCE: Disabled\n");
3676                         } else {
3677                                 seq_printf(m, "VCE: Enabled\n");
3678                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3679                                         seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3680                         }
3681                 }
3682         }
3683
3684         return 0;
3685 }
3686
3687 static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags)
3688 {
3689         int i;
3690
3691         for (i = 0; clocks[i].flag; i++)
3692                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3693                            (flags & clocks[i].flag) ? "On" : "Off");
3694 }
3695
3696 static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused)
3697 {
3698         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3699         struct drm_device *dev = adev_to_drm(adev);
3700         u64 flags = 0;
3701         int r;
3702
3703         if (amdgpu_in_reset(adev))
3704                 return -EPERM;
3705         if (adev->in_suspend && !adev->in_runpm)
3706                 return -EPERM;
3707
3708         r = pm_runtime_get_sync(dev->dev);
3709         if (r < 0) {
3710                 pm_runtime_put_autosuspend(dev->dev);
3711                 return r;
3712         }
3713
3714         if (amdgpu_dpm_debugfs_print_current_performance_level(adev, m)) {
3715                 r = amdgpu_debugfs_pm_info_pp(m, adev);
3716                 if (r)
3717                         goto out;
3718         }
3719
3720         amdgpu_device_ip_get_clockgating_state(adev, &flags);
3721
3722         seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags);
3723         amdgpu_parse_cg_state(m, flags);
3724         seq_printf(m, "\n");
3725
3726 out:
3727         pm_runtime_mark_last_busy(dev->dev);
3728         pm_runtime_put_autosuspend(dev->dev);
3729
3730         return r;
3731 }
3732
3733 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info);
3734
3735 /*
3736  * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW
3737  *
3738  * Reads debug memory region allocated to PMFW
3739  */
3740 static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf,
3741                                          size_t size, loff_t *pos)
3742 {
3743         struct amdgpu_device *adev = file_inode(f)->i_private;
3744         size_t smu_prv_buf_size;
3745         void *smu_prv_buf;
3746         int ret = 0;
3747
3748         if (amdgpu_in_reset(adev))
3749                 return -EPERM;
3750         if (adev->in_suspend && !adev->in_runpm)
3751                 return -EPERM;
3752
3753         ret = amdgpu_dpm_get_smu_prv_buf_details(adev, &smu_prv_buf, &smu_prv_buf_size);
3754         if (ret)
3755                 return ret;
3756
3757         if (!smu_prv_buf || !smu_prv_buf_size)
3758                 return -EINVAL;
3759
3760         return simple_read_from_buffer(buf, size, pos, smu_prv_buf,
3761                                        smu_prv_buf_size);
3762 }
3763
3764 static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = {
3765         .owner = THIS_MODULE,
3766         .open = simple_open,
3767         .read = amdgpu_pm_prv_buffer_read,
3768         .llseek = default_llseek,
3769 };
3770
3771 #endif
3772
3773 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3774 {
3775 #if defined(CONFIG_DEBUG_FS)
3776         struct drm_minor *minor = adev_to_drm(adev)->primary;
3777         struct dentry *root = minor->debugfs_root;
3778
3779         if (!adev->pm.dpm_enabled)
3780                 return;
3781
3782         debugfs_create_file("amdgpu_pm_info", 0444, root, adev,
3783                             &amdgpu_debugfs_pm_info_fops);
3784
3785         if (adev->pm.smu_prv_buffer_size > 0)
3786                 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root,
3787                                          adev,
3788                                          &amdgpu_debugfs_pm_prv_buffer_fops,
3789                                          adev->pm.smu_prv_buffer_size);
3790
3791         amdgpu_dpm_stb_debug_fs_init(adev);
3792 #endif
3793 }