2 * Copyright 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef __KGD_PP_INTERFACE_H__
25 #define __KGD_PP_INTERFACE_H__
27 extern const struct amdgpu_ip_block_version pp_smu_ip_block;
29 struct amd_vce_state {
41 enum amd_dpm_forced_level {
42 AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
43 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
44 AMD_DPM_FORCED_LEVEL_LOW = 0x4,
45 AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
46 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
47 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
48 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
49 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
50 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
51 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200,
54 enum amd_pm_state_type {
55 /* not used for dpm */
56 POWER_STATE_TYPE_DEFAULT,
57 POWER_STATE_TYPE_POWERSAVE,
58 /* user selectable states */
59 POWER_STATE_TYPE_BATTERY,
60 POWER_STATE_TYPE_BALANCED,
61 POWER_STATE_TYPE_PERFORMANCE,
63 POWER_STATE_TYPE_INTERNAL_UVD,
64 POWER_STATE_TYPE_INTERNAL_UVD_SD,
65 POWER_STATE_TYPE_INTERNAL_UVD_HD,
66 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
67 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
68 POWER_STATE_TYPE_INTERNAL_BOOT,
69 POWER_STATE_TYPE_INTERNAL_THERMAL,
70 POWER_STATE_TYPE_INTERNAL_ACPI,
71 POWER_STATE_TYPE_INTERNAL_ULV,
72 POWER_STATE_TYPE_INTERNAL_3DPERF,
75 #define AMD_MAX_VCE_LEVELS 6
78 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
79 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
80 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
81 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
82 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
83 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
86 enum amd_fan_ctrl_mode {
87 AMD_FAN_CTRL_NONE = 0,
88 AMD_FAN_CTRL_MANUAL = 1,
89 AMD_FAN_CTRL_AUTO = 2,
109 enum amd_pp_sensors {
110 AMDGPU_PP_SENSOR_GFX_SCLK = 0,
111 AMDGPU_PP_SENSOR_CPU_CLK,
112 AMDGPU_PP_SENSOR_VDDNB,
113 AMDGPU_PP_SENSOR_VDDGFX,
114 AMDGPU_PP_SENSOR_UVD_VCLK,
115 AMDGPU_PP_SENSOR_UVD_DCLK,
116 AMDGPU_PP_SENSOR_VCE_ECCLK,
117 AMDGPU_PP_SENSOR_GPU_LOAD,
118 AMDGPU_PP_SENSOR_MEM_LOAD,
119 AMDGPU_PP_SENSOR_GFX_MCLK,
120 AMDGPU_PP_SENSOR_GPU_TEMP,
121 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
122 AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
123 AMDGPU_PP_SENSOR_MEM_TEMP,
124 AMDGPU_PP_SENSOR_VCE_POWER,
125 AMDGPU_PP_SENSOR_UVD_POWER,
126 AMDGPU_PP_SENSOR_GPU_POWER,
127 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
128 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
129 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
130 AMDGPU_PP_SENSOR_MIN_FAN_RPM,
131 AMDGPU_PP_SENSOR_MAX_FAN_RPM,
132 AMDGPU_PP_SENSOR_VCN_POWER_STATE,
136 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
137 AMD_PP_TASK_ENABLE_USER_STATE,
138 AMD_PP_TASK_READJUST_POWER_STATE,
139 AMD_PP_TASK_COMPLETE_INIT,
143 enum PP_SMC_POWER_PROFILE {
144 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
145 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
146 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2,
147 PP_SMC_POWER_PROFILE_VIDEO = 0x3,
148 PP_SMC_POWER_PROFILE_VR = 0x4,
149 PP_SMC_POWER_PROFILE_COMPUTE = 0x5,
150 PP_SMC_POWER_PROFILE_CUSTOM = 0x6,
151 PP_SMC_POWER_PROFILE_COUNT,
155 PP_GROUP_UNKNOWN = 0,
161 enum PP_OD_DPM_TABLE_COMMAND {
162 PP_OD_EDIT_SCLK_VDDC_TABLE,
163 PP_OD_EDIT_MCLK_VDDC_TABLE,
164 PP_OD_EDIT_CCLK_VDDC_TABLE,
165 PP_OD_EDIT_VDDC_CURVE,
166 PP_OD_RESTORE_DEFAULT_TABLE,
167 PP_OD_COMMIT_DPM_TABLE,
168 PP_OD_EDIT_VDDGFX_OFFSET
171 struct pp_states_info {
185 PP_MP1_STATE_SHUTDOWN,
191 DF_CSTATE_DISALLOW = 0,
195 #define PP_GROUP_MASK 0xF0000000
196 #define PP_GROUP_SHIFT 28
198 #define PP_BLOCK_MASK 0x0FFFFF00
199 #define PP_BLOCK_SHIFT 8
201 #define PP_BLOCK_GFX_CG 0x01
202 #define PP_BLOCK_GFX_MG 0x02
203 #define PP_BLOCK_GFX_3D 0x04
204 #define PP_BLOCK_GFX_RLC 0x08
205 #define PP_BLOCK_GFX_CP 0x10
206 #define PP_BLOCK_SYS_BIF 0x01
207 #define PP_BLOCK_SYS_MC 0x02
208 #define PP_BLOCK_SYS_ROM 0x04
209 #define PP_BLOCK_SYS_DRM 0x08
210 #define PP_BLOCK_SYS_HDP 0x10
211 #define PP_BLOCK_SYS_SDMA 0x20
213 #define PP_STATE_MASK 0x0000000F
214 #define PP_STATE_SHIFT 0
215 #define PP_STATE_SUPPORT_MASK 0x000000F0
216 #define PP_STATE_SUPPORT_SHIFT 0
218 #define PP_STATE_CG 0x01
219 #define PP_STATE_LS 0x02
220 #define PP_STATE_DS 0x04
221 #define PP_STATE_SD 0x08
222 #define PP_STATE_SUPPORT_CG 0x10
223 #define PP_STATE_SUPPORT_LS 0x20
224 #define PP_STATE_SUPPORT_DS 0x40
225 #define PP_STATE_SUPPORT_SD 0x80
227 #define PP_CG_MSG_ID(group, block, support, state) \
228 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
229 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
231 #define XGMI_MODE_PSTATE_D3 0
232 #define XGMI_MODE_PSTATE_D0 1
234 #define NUM_HBM_INSTANCES 4
237 enum amd_pp_clock_type;
238 struct amd_pp_simple_clock_info;
239 struct amd_pp_display_configuration;
240 struct amd_pp_clock_info;
241 struct pp_display_clock_request;
242 struct pp_clock_levels_with_voltage;
243 struct pp_clock_levels_with_latency;
244 struct amd_pp_clocks;
246 struct amd_pm_funcs {
247 /* export for dpm on ci and si */
248 int (*pre_set_power_state)(void *handle);
249 int (*set_power_state)(void *handle);
250 void (*post_set_power_state)(void *handle);
251 void (*display_configuration_changed)(void *handle);
252 void (*print_power_state)(void *handle, void *ps);
253 bool (*vblank_too_short)(void *handle);
254 void (*enable_bapm)(void *handle, bool enable);
255 int (*check_state_equal)(void *handle,
259 /* export for sysfs */
260 void (*set_fan_control_mode)(void *handle, u32 mode);
261 u32 (*get_fan_control_mode)(void *handle);
262 int (*set_fan_speed_percent)(void *handle, u32 speed);
263 int (*get_fan_speed_percent)(void *handle, u32 *speed);
264 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
265 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
266 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
267 int (*get_sclk_od)(void *handle);
268 int (*set_sclk_od)(void *handle, uint32_t value);
269 int (*get_mclk_od)(void *handle);
270 int (*set_mclk_od)(void *handle, uint32_t value);
271 int (*read_sensor)(void *handle, int idx, void *value, int *size);
272 enum amd_dpm_forced_level (*get_performance_level)(void *handle);
273 enum amd_pm_state_type (*get_current_power_state)(void *handle);
274 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
275 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
276 int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
277 int (*get_pp_table)(void *handle, char **table);
278 int (*set_pp_table)(void *handle, const char *buf, size_t size);
279 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
280 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
281 /* export to amdgpu */
282 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
283 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
284 enum amd_pm_state_type *user_state);
285 int (*load_firmware)(void *handle);
286 int (*wait_for_fw_loading_complete)(void *handle);
287 int (*set_powergating_by_smu)(void *handle,
288 uint32_t block_type, bool gate);
289 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
290 int (*set_power_limit)(void *handle, uint32_t n);
291 int (*get_power_limit)(void *handle, uint32_t *limit, uint32_t *max_limit,
293 int (*get_power_profile_mode)(void *handle, char *buf);
294 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
295 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
296 int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
297 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
298 int (*smu_i2c_bus_access)(void *handle, bool acquire);
299 int (*gfx_state_change_set)(void *handle, uint32_t state);
301 u32 (*get_sclk)(void *handle, bool low);
302 u32 (*get_mclk)(void *handle, bool low);
303 int (*display_configuration_change)(void *handle,
304 const struct amd_pp_display_configuration *input);
305 int (*get_display_power_level)(void *handle,
306 struct amd_pp_simple_clock_info *output);
307 int (*get_current_clocks)(void *handle,
308 struct amd_pp_clock_info *clocks);
309 int (*get_clock_by_type)(void *handle,
310 enum amd_pp_clock_type type,
311 struct amd_pp_clocks *clocks);
312 int (*get_clock_by_type_with_latency)(void *handle,
313 enum amd_pp_clock_type type,
314 struct pp_clock_levels_with_latency *clocks);
315 int (*get_clock_by_type_with_voltage)(void *handle,
316 enum amd_pp_clock_type type,
317 struct pp_clock_levels_with_voltage *clocks);
318 int (*set_watermarks_for_clocks_ranges)(void *handle,
320 int (*display_clock_voltage_request)(void *handle,
321 struct pp_display_clock_request *clock);
322 int (*get_display_mode_validation_clocks)(void *handle,
323 struct amd_pp_simple_clock_info *clocks);
324 int (*notify_smu_enable_pwe)(void *handle);
325 int (*enable_mgpu_fan_boost)(void *handle);
326 int (*set_active_display_count)(void *handle, uint32_t count);
327 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
328 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
329 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
330 int (*get_asic_baco_capability)(void *handle, bool *cap);
331 int (*get_asic_baco_state)(void *handle, int *state);
332 int (*set_asic_baco_state)(void *handle, int state);
333 int (*get_ppfeature_status)(void *handle, char *buf);
334 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
335 int (*asic_reset_mode_2)(void *handle);
336 int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
337 int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
338 ssize_t (*get_gpu_metrics)(void *handle, void **table);
341 struct metrics_table_header {
342 uint16_t structure_size;
343 uint8_t format_revision;
344 uint8_t content_revision;
348 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned.
349 * Use gpu_metrics_v1_1 or later instead.
351 struct gpu_metrics_v1_0 {
352 struct metrics_table_header common_header;
354 /* Driver attached timestamp (in ns) */
355 uint64_t system_clock_counter;
358 uint16_t temperature_edge;
359 uint16_t temperature_hotspot;
360 uint16_t temperature_mem;
361 uint16_t temperature_vrgfx;
362 uint16_t temperature_vrsoc;
363 uint16_t temperature_vrmem;
366 uint16_t average_gfx_activity;
367 uint16_t average_umc_activity; // memory controller
368 uint16_t average_mm_activity; // UVD or VCN
371 uint16_t average_socket_power;
372 uint32_t energy_accumulator;
375 uint16_t average_gfxclk_frequency;
376 uint16_t average_socclk_frequency;
377 uint16_t average_uclk_frequency;
378 uint16_t average_vclk0_frequency;
379 uint16_t average_dclk0_frequency;
380 uint16_t average_vclk1_frequency;
381 uint16_t average_dclk1_frequency;
384 uint16_t current_gfxclk;
385 uint16_t current_socclk;
386 uint16_t current_uclk;
387 uint16_t current_vclk0;
388 uint16_t current_dclk0;
389 uint16_t current_vclk1;
390 uint16_t current_dclk1;
392 /* Throttle status */
393 uint32_t throttle_status;
396 uint16_t current_fan_speed;
398 /* Link width/speed */
399 uint8_t pcie_link_width;
400 uint8_t pcie_link_speed; // in 0.1 GT/s
403 struct gpu_metrics_v1_1 {
404 struct metrics_table_header common_header;
407 uint16_t temperature_edge;
408 uint16_t temperature_hotspot;
409 uint16_t temperature_mem;
410 uint16_t temperature_vrgfx;
411 uint16_t temperature_vrsoc;
412 uint16_t temperature_vrmem;
415 uint16_t average_gfx_activity;
416 uint16_t average_umc_activity; // memory controller
417 uint16_t average_mm_activity; // UVD or VCN
420 uint16_t average_socket_power;
421 uint64_t energy_accumulator;
423 /* Driver attached timestamp (in ns) */
424 uint64_t system_clock_counter;
427 uint16_t average_gfxclk_frequency;
428 uint16_t average_socclk_frequency;
429 uint16_t average_uclk_frequency;
430 uint16_t average_vclk0_frequency;
431 uint16_t average_dclk0_frequency;
432 uint16_t average_vclk1_frequency;
433 uint16_t average_dclk1_frequency;
436 uint16_t current_gfxclk;
437 uint16_t current_socclk;
438 uint16_t current_uclk;
439 uint16_t current_vclk0;
440 uint16_t current_dclk0;
441 uint16_t current_vclk1;
442 uint16_t current_dclk1;
444 /* Throttle status */
445 uint32_t throttle_status;
448 uint16_t current_fan_speed;
450 /* Link width/speed */
451 uint16_t pcie_link_width;
452 uint16_t pcie_link_speed; // in 0.1 GT/s
456 uint32_t gfx_activity_acc;
457 uint32_t mem_activity_acc;
459 uint16_t temperature_hbm[NUM_HBM_INSTANCES];
463 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
464 * Use gpu_metrics_v2_1 or later instead.
466 struct gpu_metrics_v2_0 {
467 struct metrics_table_header common_header;
469 /* Driver attached timestamp (in ns) */
470 uint64_t system_clock_counter;
473 uint16_t temperature_gfx; // gfx temperature on APUs
474 uint16_t temperature_soc; // soc temperature on APUs
475 uint16_t temperature_core[8]; // CPU core temperature on APUs
476 uint16_t temperature_l3[2];
479 uint16_t average_gfx_activity;
480 uint16_t average_mm_activity; // UVD or VCN
483 uint16_t average_socket_power; // dGPU + APU power on A + A platform
484 uint16_t average_cpu_power;
485 uint16_t average_soc_power;
486 uint16_t average_gfx_power;
487 uint16_t average_core_power[8]; // CPU core power on APUs
490 uint16_t average_gfxclk_frequency;
491 uint16_t average_socclk_frequency;
492 uint16_t average_uclk_frequency;
493 uint16_t average_fclk_frequency;
494 uint16_t average_vclk_frequency;
495 uint16_t average_dclk_frequency;
498 uint16_t current_gfxclk;
499 uint16_t current_socclk;
500 uint16_t current_uclk;
501 uint16_t current_fclk;
502 uint16_t current_vclk;
503 uint16_t current_dclk;
504 uint16_t current_coreclk[8]; // CPU core clocks
505 uint16_t current_l3clk[2];
507 /* Throttle status */
508 uint32_t throttle_status;
516 struct gpu_metrics_v2_1 {
517 struct metrics_table_header common_header;
520 uint16_t temperature_gfx; // gfx temperature on APUs
521 uint16_t temperature_soc; // soc temperature on APUs
522 uint16_t temperature_core[8]; // CPU core temperature on APUs
523 uint16_t temperature_l3[2];
526 uint16_t average_gfx_activity;
527 uint16_t average_mm_activity; // UVD or VCN
529 /* Driver attached timestamp (in ns) */
530 uint64_t system_clock_counter;
533 uint16_t average_socket_power; // dGPU + APU power on A + A platform
534 uint16_t average_cpu_power;
535 uint16_t average_soc_power;
536 uint16_t average_gfx_power;
537 uint16_t average_core_power[8]; // CPU core power on APUs
540 uint16_t average_gfxclk_frequency;
541 uint16_t average_socclk_frequency;
542 uint16_t average_uclk_frequency;
543 uint16_t average_fclk_frequency;
544 uint16_t average_vclk_frequency;
545 uint16_t average_dclk_frequency;
548 uint16_t current_gfxclk;
549 uint16_t current_socclk;
550 uint16_t current_uclk;
551 uint16_t current_fclk;
552 uint16_t current_vclk;
553 uint16_t current_dclk;
554 uint16_t current_coreclk[8]; // CPU core clocks
555 uint16_t current_l3clk[2];
557 /* Throttle status */
558 uint32_t throttle_status;