drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DC_HW_SEQUENCER_PRIVATE_H__
  27 #define __DC_HW_SEQUENCER_PRIVATE_H__
  28
  29 #include "dc_types.h"
  30
  31 enum pipe_gating_control {
  32         PIPE_GATING_CONTROL_DISABLE = 0,
  33         PIPE_GATING_CONTROL_ENABLE,
  34         PIPE_GATING_CONTROL_INIT
  35 };
  36
  37 struct dce_hwseq_wa {
  38         bool blnd_crtc_trigger;
  39         bool DEGVIDCN10_253;
  40         bool false_optc_underflow;
  41         bool DEGVIDCN10_254;
  42         bool DEGVIDCN21;
  43         bool disallow_self_refresh_during_multi_plane_transition;
  44         bool dp_hpo_and_otg_sequence;
  45         bool wait_hubpret_read_start_during_mpo_transition;
  46 };
  47
  48 struct hwseq_wa_state {
  49         bool DEGVIDCN10_253_applied;
  50         bool disallow_self_refresh_during_multi_plane_transition_applied;
  51         unsigned int disallow_self_refresh_during_multi_plane_transition_applied_on_frame;
  52 };
  53
  54 struct pipe_ctx;
  55 struct dc_state;
  56 struct dc_stream_status;
  57 struct dc_writeback_info;
  58 struct dchub_init_data;
  59 struct dc_static_screen_params;
  60 struct resource_pool;
  61 struct resource_context;
  62 struct stream_resource;
  63 struct dc_phy_addr_space_config;
  64 struct dc_virtual_addr_space_config;
  65 struct hubp;
  66 struct dpp;
  67 struct dce_hwseq;
  68 struct timing_generator;
  69 struct tg_color;
  70 struct output_pixel_processor;
  71 struct mpcc_blnd_cfg;
  72
  73 struct hwseq_private_funcs {
  74
  75         void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
  76         void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
  77         void (*init_pipes)(struct dc *dc, struct dc_state *context);
  78         void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);
  79         void (*update_plane_addr)(const struct dc *dc,
  80                         struct pipe_ctx *pipe_ctx);
  81         void (*plane_atomic_disconnect)(struct dc *dc,
  82                         struct dc_state *state,
  83                         struct pipe_ctx *pipe_ctx);
  84         void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);
  85         bool (*set_input_transfer_func)(struct dc *dc,
  86                                 struct pipe_ctx *pipe_ctx,
  87                                 const struct dc_plane_state *plane_state);
  88         bool (*set_output_transfer_func)(struct dc *dc,
  89                                 struct pipe_ctx *pipe_ctx,
  90                                 const struct dc_stream_state *stream);
  91         void (*power_down)(struct dc *dc);
  92         void (*enable_display_pipe_clock_gating)(struct dc_context *ctx,
  93                                         bool clock_gating);
  94         bool (*enable_display_power_gating)(struct dc *dc,
  95                                         uint8_t controller_id,
  96                                         struct dc_bios *dcb,
  97                                         enum pipe_gating_control power_gating);
  98         void (*blank_pixel_data)(struct dc *dc,
  99                         struct pipe_ctx *pipe_ctx,
 100                         bool blank);
 101         enum dc_status (*enable_stream_timing)(
 102                         struct pipe_ctx *pipe_ctx,
 103                         struct dc_state *context,
 104                         struct dc *dc);
 105         void (*edp_backlight_control)(struct dc_link *link,
 106                         bool enable);
 107         void (*setup_vupdate_interrupt)(struct dc *dc,
 108                         struct pipe_ctx *pipe_ctx);
 109         bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
 110         void (*init_blank)(struct dc *dc, struct timing_generator *tg);
 111         void (*disable_vga)(struct dce_hwseq *hws);
 112         void (*bios_golden_init)(struct dc *dc);
 113         void (*plane_atomic_power_down)(struct dc *dc,
 114                         struct dpp *dpp,
 115                         struct hubp *hubp);
 116         void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx);
 117         void (*enable_power_gating_plane)(struct dce_hwseq *hws,
 118                 bool enable);
 119         void (*dpp_root_clock_control)(
 120                         struct dce_hwseq *hws,
 121                         unsigned int dpp_inst,
 122                         bool clock_on);
 123         void (*dpp_pg_control)(struct dce_hwseq *hws,
 124                         unsigned int dpp_inst,
 125                         bool power_on);
 126         void (*hubp_pg_control)(struct dce_hwseq *hws,
 127                         unsigned int hubp_inst,
 128                         bool power_on);
 129         void (*dsc_pg_control)(struct dce_hwseq *hws,
 130                         unsigned int dsc_inst,
 131                         bool power_on);
 132         bool (*dsc_pg_status)(struct dce_hwseq *hws,
 133                         unsigned int dsc_inst);
 134         void (*update_odm)(struct dc *dc, struct dc_state *context,
 135                         struct pipe_ctx *pipe_ctx);
 136         void (*program_all_writeback_pipes_in_tree)(struct dc *dc,
 137                         const struct dc_stream_state *stream,
 138                         struct dc_state *context);
 139         bool (*s0i3_golden_init_wa)(struct dc *dc);
 140         void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx);
 141         void (*verify_allow_pstate_change_high)(struct dc *dc);
 142         void (*program_pipe)(struct dc *dc,
 143                         struct pipe_ctx *pipe_ctx,
 144                         struct dc_state *context);
 145         bool (*wait_for_blank_complete)(struct output_pixel_processor *opp);
 146         void (*dccg_init)(struct dce_hwseq *hws);
 147         bool (*set_blend_lut)(struct pipe_ctx *pipe_ctx,
 148                         const struct dc_plane_state *plane_state);
 149         bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx,
 150                         const struct dc_plane_state *plane_state);
 151         bool (*set_mcm_luts)(struct pipe_ctx *pipe_ctx,
 152                         const struct dc_plane_state *plane_state);
 153         void (*PLAT_58856_wa)(struct dc_state *context,
 154                         struct pipe_ctx *pipe_ctx);
 155         void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);
 156         void (*enable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx,
 157                                struct dc_state *context);
 158 #ifdef CONFIG_DRM_AMD_DC_FP
 159         void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context);
 160         void (*update_force_pstate)(struct dc *dc, struct dc_state *context);
 161         void (*update_mall_sel)(struct dc *dc, struct dc_state *context);
 162         unsigned int (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx,
 163                         unsigned int *k1_div,
 164                         unsigned int *k2_div);
 165         void (*set_pixels_per_cycle)(struct pipe_ctx *pipe_ctx);
 166         void (*resync_fifo_dccg_dio)(struct dce_hwseq *hws, struct dc *dc,
 167                         struct dc_state *context);
 168         enum dc_status (*apply_single_controller_ctx_to_hw)(
 169                         struct pipe_ctx *pipe_ctx,
 170                         struct dc_state *context,
 171                         struct dc *dc);
 172         bool (*is_dp_dig_pixel_rate_div_policy)(struct pipe_ctx *pipe_ctx);
 173 #endif
 174         void (*reset_back_end_for_pipe)(struct dc *dc,
 175                         struct pipe_ctx *pipe_ctx,
 176                         struct dc_state *context);
 177 };
 178
 179 struct dce_hwseq {
 180         struct dc_context *ctx;
 181         const struct dce_hwseq_registers *regs;
 182         const struct dce_hwseq_shift *shifts;
 183         const struct dce_hwseq_mask *masks;
 184         struct dce_hwseq_wa wa;
 185         struct hwseq_wa_state wa_state;
 186         struct hwseq_private_funcs funcs;
 187
 188         PHYSICAL_ADDRESS_LOC fb_base;
 189         PHYSICAL_ADDRESS_LOC fb_top;
 190         PHYSICAL_ADDRESS_LOC fb_offset;
 191         PHYSICAL_ADDRESS_LOC uma_top;
 192 };
 193
 194 #endif /* __DC_HW_SEQUENCER_PRIVATE_H__ */