drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dce110/dce110_hwseq.h"
  27 #include "dcn10/dcn10_hwseq.h"
  28 #include "dcn20/dcn20_hwseq.h"
  29 #include "dcn21/dcn21_hwseq.h"
  30 #include "dcn30/dcn30_hwseq.h"
  31 #include "dcn31/dcn31_hwseq.h"
  32 #include "dcn32/dcn32_hwseq.h"
  33 #include "dcn32_init.h"
  34
  35 static const struct hw_sequencer_funcs dcn32_funcs = {
  36         .program_gamut_remap = dcn30_program_gamut_remap,
  37         .init_hw = dcn32_init_hw,
  38         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
  39         .apply_ctx_for_surface = NULL,
  40         .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
  41         .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
  42         .post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
  43         .update_plane_addr = dcn20_update_plane_addr,
  44         .update_dchub = dcn10_update_dchub,
  45         .update_pending_status = dcn10_update_pending_status,
  46         .program_output_csc = dcn20_program_output_csc,
  47         .enable_accelerated_mode = dce110_enable_accelerated_mode,
  48         .enable_timing_synchronization = dcn10_enable_timing_synchronization,
  49         .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
  50         .update_info_frame = dcn31_update_info_frame,
  51         .send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
  52         .enable_stream = dcn20_enable_stream,
  53         .disable_stream = dce110_disable_stream,
  54         .unblank_stream = dcn32_unblank_stream,
  55         .blank_stream = dce110_blank_stream,
  56         .enable_audio_stream = dce110_enable_audio_stream,
  57         .disable_audio_stream = dce110_disable_audio_stream,
  58         .disable_plane = dcn20_disable_plane,
  59         .disable_pixel_data = dcn20_disable_pixel_data,
  60         .pipe_control_lock = dcn20_pipe_control_lock,
  61         .interdependent_update_lock = dcn10_lock_all_pipes,
  62         .cursor_lock = dcn10_cursor_lock,
  63         .prepare_bandwidth = dcn32_prepare_bandwidth,
  64         .optimize_bandwidth = dcn20_optimize_bandwidth,
  65         .update_bandwidth = dcn20_update_bandwidth,
  66         .set_drr = dcn10_set_drr,
  67         .get_position = dcn10_get_position,
  68         .set_static_screen_control = dcn30_set_static_screen_control,
  69         .setup_stereo = dcn10_setup_stereo,
  70         .set_avmute = dcn30_set_avmute,
  71         .log_hw_state = dcn10_log_hw_state,
  72         .get_hw_state = dcn10_get_hw_state,
  73         .clear_status_bits = dcn10_clear_status_bits,
  74         .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
  75         .edp_backlight_control = dce110_edp_backlight_control,
  76         .edp_power_control = dce110_edp_power_control,
  77         .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
  78         .edp_wait_for_T12 = dce110_edp_wait_for_T12,
  79         .set_cursor_position = dcn10_set_cursor_position,
  80         .set_cursor_attribute = dcn10_set_cursor_attribute,
  81         .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
  82         .setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
  83         .set_clock = dcn10_set_clock,
  84         .get_clock = dcn10_get_clock,
  85         .program_triplebuffer = dcn20_program_triple_buffer,
  86         .enable_writeback = dcn30_enable_writeback,
  87         .disable_writeback = dcn30_disable_writeback,
  88         .update_writeback = dcn30_update_writeback,
  89         .mmhubbub_warmup = dcn30_mmhubbub_warmup,
  90         .dmdata_status_done = dcn20_dmdata_status_done,
  91         .program_dmdata_engine = dcn30_program_dmdata_engine,
  92         .set_dmdata_attributes = dcn20_set_dmdata_attributes,
  93         .init_sys_ctx = dcn20_init_sys_ctx,
  94         .init_vm_ctx = dcn20_init_vm_ctx,
  95         .set_flip_control_gsl = dcn20_set_flip_control_gsl,
  96         .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
  97         .calc_vupdate_position = dcn10_calc_vupdate_position,
  98         .apply_idle_power_optimizations = dcn32_apply_idle_power_optimizations,
  99         .does_plane_fit_in_mall = NULL,
 100         .set_backlight_level = dcn21_set_backlight_level,
 101         .set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
 102         .hardware_release = dcn30_hardware_release,
 103         .set_pipe = dcn21_set_pipe,
 104         .enable_lvds_link_output = dce110_enable_lvds_link_output,
 105         .enable_tmds_link_output = dce110_enable_tmds_link_output,
 106         .enable_dp_link_output = dce110_enable_dp_link_output,
 107         .disable_link_output = dcn32_disable_link_output,
 108         .set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
 109         .get_dcc_en_bits = dcn10_get_dcc_en_bits,
 110         .commit_subvp_config = dcn32_commit_subvp_config,
 111         .enable_phantom_streams = dcn32_enable_phantom_streams,
 112         .subvp_pipe_control_lock = dcn32_subvp_pipe_control_lock,
 113         .update_visual_confirm_color = dcn10_update_visual_confirm_color,
 114         .subvp_pipe_control_lock_fast = dcn32_subvp_pipe_control_lock_fast,
 115         .update_phantom_vp_position = dcn32_update_phantom_vp_position,
 116         .update_dsc_pg = dcn32_update_dsc_pg,
 117         .apply_update_flags_for_phantom = dcn32_apply_update_flags_for_phantom,
 118         .blank_phantom = dcn32_blank_phantom,
 119         .is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless,
 120 };
 121
 122 static const struct hwseq_private_funcs dcn32_private_funcs = {
 123         .init_pipes = dcn10_init_pipes,
 124         .update_plane_addr = dcn20_update_plane_addr,
 125         .plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
 126         .update_mpcc = dcn20_update_mpcc,
 127         .set_input_transfer_func = dcn32_set_input_transfer_func,
 128         .set_output_transfer_func = dcn32_set_output_transfer_func,
 129         .power_down = dce110_power_down,
 130         .enable_display_power_gating = dcn10_dummy_display_power_gating,
 131         .blank_pixel_data = dcn20_blank_pixel_data,
 132         .reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
 133         .enable_stream_timing = dcn20_enable_stream_timing,
 134         .edp_backlight_control = dce110_edp_backlight_control,
 135         .disable_stream_gating = dcn20_disable_stream_gating,
 136         .enable_stream_gating = dcn20_enable_stream_gating,
 137         .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
 138         .did_underflow_occur = dcn10_did_underflow_occur,
 139         .init_blank = dcn32_init_blank,
 140         .disable_vga = dcn20_disable_vga,
 141         .bios_golden_init = dcn10_bios_golden_init,
 142         .plane_atomic_disable = dcn20_plane_atomic_disable,
 143         .plane_atomic_power_down = dcn10_plane_atomic_power_down,
 144         .enable_power_gating_plane = dcn32_enable_power_gating_plane,
 145         .hubp_pg_control = dcn32_hubp_pg_control,
 146         .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
 147         .update_odm = dcn32_update_odm,
 148         .dsc_pg_control = dcn32_dsc_pg_control,
 149         .dsc_pg_status = dcn32_dsc_pg_status,
 150         .set_hdr_multiplier = dcn10_set_hdr_multiplier,
 151         .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
 152         .wait_for_blank_complete = dcn20_wait_for_blank_complete,
 153         .dccg_init = dcn20_dccg_init,
 154         .set_mcm_luts = dcn32_set_mcm_luts,
 155         .program_mall_pipe_config = dcn32_program_mall_pipe_config,
 156         .update_force_pstate = dcn32_update_force_pstate,
 157         .update_mall_sel = dcn32_update_mall_sel,
 158         .calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,
 159         .set_pixels_per_cycle = dcn32_set_pixels_per_cycle,
 160         .resync_fifo_dccg_dio = dcn32_resync_fifo_dccg_dio,
 161         .is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy,
 162 };
 163
 164 void dcn32_hw_sequencer_init_functions(struct dc *dc)
 165 {
 166         dc->hwss = dcn32_funcs;
 167         dc->hwseq->funcs = dcn32_private_funcs;
 168
 169 }