drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright 2022 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26 #include "dcn32_fpu.h"
  27 #include "dcn32/dcn32_resource.h"
  28 #include "dcn20/dcn20_resource.h"
  29 #include "display_mode_vba_util_32.h"
  30 #include "dml/dcn32/display_mode_vba_32.h"
  31 // We need this includes for WATERMARKS_* defines
  32 #include "clk_mgr/dcn32/dcn32_smu13_driver_if.h"
  33 #include "dcn30/dcn30_resource.h"
  34 #include "link.h"
  35 #include "dc_state_priv.h"
  36
  37 #define DC_LOGGER_INIT(logger)
  38
  39 static const struct subvp_high_refresh_list subvp_high_refresh_list = {
  40                         .min_refresh = 120,
  41                         .max_refresh = 175,
  42                         .res = {
  43                                 {.width = 3840, .height = 2160, },
  44                                 {.width = 3440, .height = 1440, },
  45                                 {.width = 2560, .height = 1440, },
  46                                 {.width = 1920, .height = 1080, }},
  47 };
  48
  49 static const struct subvp_active_margin_list subvp_active_margin_list = {
  50                         .min_refresh = 55,
  51                         .max_refresh = 65,
  52                         .res = {
  53                                 {.width = 2560, .height = 1440, },
  54                                 {.width = 1920, .height = 1080, }},
  55 };
  56
  57 struct _vcs_dpi_ip_params_st dcn3_2_ip = {
  58         .gpuvm_enable = 0,
  59         .gpuvm_max_page_table_levels = 4,
  60         .hostvm_enable = 0,
  61         .rob_buffer_size_kbytes = 128,
  62         .det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE,
  63         .config_return_buffer_size_in_kbytes = 1280,
  64         .compressed_buffer_segment_size_in_kbytes = 64,
  65         .meta_fifo_size_in_kentries = 22,
  66         .zero_size_buffer_entries = 512,
  67         .compbuf_reserved_space_64b = 256,
  68         .compbuf_reserved_space_zs = 64,
  69         .dpp_output_buffer_pixels = 2560,
  70         .opp_output_buffer_lines = 1,
  71         .pixel_chunk_size_kbytes = 8,
  72         .alpha_pixel_chunk_size_kbytes = 4,
  73         .min_pixel_chunk_size_bytes = 1024,
  74         .dcc_meta_buffer_size_bytes = 6272,
  75         .meta_chunk_size_kbytes = 2,
  76         .min_meta_chunk_size_bytes = 256,
  77         .writeback_chunk_size_kbytes = 8,
  78         .ptoi_supported = false,
  79         .num_dsc = 4,
  80         .maximum_dsc_bits_per_component = 12,
  81         .maximum_pixels_per_line_per_dsc_unit = 6016,
  82         .dsc422_native_support = true,
  83         .is_line_buffer_bpp_fixed = true,
  84         .line_buffer_fixed_bpp = 57,
  85         .line_buffer_size_bits = 1171920,
  86         .max_line_buffer_lines = 32,
  87         .writeback_interface_buffer_size_kbytes = 90,
  88         .max_num_dpp = 4,
  89         .max_num_otg = 4,
  90         .max_num_hdmi_frl_outputs = 1,
  91         .max_num_wb = 1,
  92         .max_dchub_pscl_bw_pix_per_clk = 4,
  93         .max_pscl_lb_bw_pix_per_clk = 2,
  94         .max_lb_vscl_bw_pix_per_clk = 4,
  95         .max_vscl_hscl_bw_pix_per_clk = 4,
  96         .max_hscl_ratio = 6,
  97         .max_vscl_ratio = 6,
  98         .max_hscl_taps = 8,
  99         .max_vscl_taps = 8,
 100         .dpte_buffer_size_in_pte_reqs_luma = 64,
 101         .dpte_buffer_size_in_pte_reqs_chroma = 34,
 102         .dispclk_ramp_margin_percent = 1,
 103         .max_inter_dcn_tile_repeaters = 8,
 104         .cursor_buffer_size = 16,
 105         .cursor_chunk_size = 2,
 106         .writeback_line_buffer_buffer_size = 0,
 107         .writeback_min_hscl_ratio = 1,
 108         .writeback_min_vscl_ratio = 1,
 109         .writeback_max_hscl_ratio = 1,
 110         .writeback_max_vscl_ratio = 1,
 111         .writeback_max_hscl_taps = 1,
 112         .writeback_max_vscl_taps = 1,
 113         .dppclk_delay_subtotal = 47,
 114         .dppclk_delay_scl = 50,
 115         .dppclk_delay_scl_lb_only = 16,
 116         .dppclk_delay_cnvc_formatter = 28,
 117         .dppclk_delay_cnvc_cursor = 6,
 118         .dispclk_delay_subtotal = 125,
 119         .dynamic_metadata_vm_enabled = false,
 120         .odm_combine_4to1_supported = false,
 121         .dcc_supported = true,
 122         .max_num_dp2p0_outputs = 2,
 123         .max_num_dp2p0_streams = 4,
 124 };
 125
 126 struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
 127         .clock_limits = {
 128                 {
 129                         .state = 0,
 130                         .dcfclk_mhz = 1564.0,
 131                         .fabricclk_mhz = 2500.0,
 132                         .dispclk_mhz = 2150.0,
 133                         .dppclk_mhz = 2150.0,
 134                         .phyclk_mhz = 810.0,
 135                         .phyclk_d18_mhz = 667.0,
 136                         .phyclk_d32_mhz = 625.0,
 137                         .socclk_mhz = 1200.0,
 138                         .dscclk_mhz = 716.667,
 139                         .dram_speed_mts = 18000.0,
 140                         .dtbclk_mhz = 1564.0,
 141                 },
 142         },
 143         .num_states = 1,
 144         .sr_exit_time_us = 42.97,
 145         .sr_enter_plus_exit_time_us = 49.94,
 146         .sr_exit_z8_time_us = 285.0,
 147         .sr_enter_plus_exit_z8_time_us = 320,
 148         .writeback_latency_us = 12.0,
 149         .round_trip_ping_latency_dcfclk_cycles = 263,
 150         .urgent_latency_pixel_data_only_us = 4.0,
 151         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 152         .urgent_latency_vm_data_only_us = 4.0,
 153         .fclk_change_latency_us = 25,
 154         .usr_retraining_latency_us = 2,
 155         .smn_latency_us = 2,
 156         .mall_allocated_for_dcn_mbytes = 64,
 157         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 158         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 159         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 160         .pct_ideal_sdp_bw_after_urgent = 90.0,
 161         .pct_ideal_fabric_bw_after_urgent = 67.0,
 162         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0,
 163         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented
 164         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented
 165         .pct_ideal_dram_bw_after_urgent_strobe = 67.0,
 166         .max_avg_sdp_bw_use_normal_percent = 80.0,
 167         .max_avg_fabric_bw_use_normal_percent = 60.0,
 168         .max_avg_dram_bw_use_normal_strobe_percent = 50.0,
 169         .max_avg_dram_bw_use_normal_percent = 15.0,
 170         .num_chans = 24,
 171         .dram_channel_width_bytes = 2,
 172         .fabric_datapath_to_dcn_data_return_bytes = 64,
 173         .return_bus_width_bytes = 64,
 174         .downspread_percent = 0.38,
 175         .dcn_downspread_percent = 0.5,
 176         .dram_clock_change_latency_us = 400,
 177         .dispclk_dppclk_vco_speed_mhz = 4300.0,
 178         .do_urgent_latency_adjustment = true,
 179         .urgent_latency_adjustment_fabric_clock_component_us = 1.0,
 180         .urgent_latency_adjustment_fabric_clock_reference_mhz = 3000,
 181 };
 182
 183 void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr)
 184 {
 185         /* defaults */
 186         double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us;
 187         double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us;
 188         double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;
 189         double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
 190         /* For min clocks use as reported by PM FW and report those as min */
 191         uint16_t min_uclk_mhz                   = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
 192         uint16_t min_dcfclk_mhz                 = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
 193         uint16_t setb_min_uclk_mhz              = min_uclk_mhz;
 194         uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;
 195
 196         dc_assert_fp_enabled();
 197
 198         /* For Set B ranges use min clocks state 2 when available, and report those to PM FW */
 199         if (dcfclk_mhz_for_the_second_state)
 200                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state;
 201         else
 202                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
 203
 204         if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz)
 205                 setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz;
 206
 207         /* Set A - Normal - default values */
 208         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
 209         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
 210         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 211         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;
 212         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 213         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
 214         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
 215         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
 216         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
 217         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
 218
 219         /* Set B - Performance - higher clocks, using DPM[2] DCFCLK and UCLK */
 220         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true;
 221         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us;
 222         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 223         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us;
 224         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 225         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
 226         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF;
 227         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = setb_min_uclk_mhz;
 228         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF;
 229
 230         /* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */
 231         /* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */
 232         if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {
 233                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;
 234                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 50;
 235                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 236                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;
 237                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 238                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
 239                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
 240                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;
 241                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;
 242                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
 243                 clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16;
 244                 clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 50;
 245                 clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16;
 246                 clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9;
 247                 clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16;
 248                 clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8;
 249                 clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memclk_mhz * 16;
 250                 clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5;
 251         }
 252         /* Set D - MALL - SR enter and exit time specific to MALL, TBD after bringup or later phase for now use DRAM values / 2 */
 253         /* For MALL DRAM clock change latency is N/A, for watermak calculations use lowest value dummy P state latency */
 254         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;
 255         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us;
 256         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 257         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us / 2; // TBD
 258         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us / 2; // TBD
 259         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;
 260         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
 261         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;
 262         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;
 263         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;
 264 }
 265
 266 /*
 267  * Finds dummy_latency_index when MCLK switching using firmware based
 268  * vblank stretch is enabled. This function will iterate through the
 269  * table of dummy pstate latencies until the lowest value that allows
 270  * dm_allow_self_refresh_and_mclk_switch to happen is found
 271  */
 272 int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,
 273                                                             struct dc_state *context,
 274                                                             display_e2e_pipe_params_st *pipes,
 275                                                             int pipe_cnt,
 276                                                             int vlevel)
 277 {
 278         const int max_latency_table_entries = 4;
 279         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 280         int dummy_latency_index = 0;
 281         enum clock_change_support temp_clock_change_support = vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
 282
 283         dc_assert_fp_enabled();
 284
 285         while (dummy_latency_index < max_latency_table_entries) {
 286                 if (temp_clock_change_support != dm_dram_clock_change_unsupported)
 287                         vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support;
 288                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
 289                                 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
 290                 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
 291
 292                 /* for subvp + DRR case, if subvp pipes are still present we support pstate */
 293                 if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported &&
 294                                 dcn32_subvp_in_use(dc, context))
 295                         vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support;
 296
 297                 if (vlevel < context->bw_ctx.dml.vba.soc.num_states &&
 298                                 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported)
 299                         break;
 300
 301                 dummy_latency_index++;
 302         }
 303
 304         if (dummy_latency_index == max_latency_table_entries) {
 305                 ASSERT(dummy_latency_index != max_latency_table_entries);
 306                 /* If the execution gets here, it means dummy p_states are
 307                  * not possible. This should never happen and would mean
 308                  * something is severely wrong.
 309                  * Here we reset dummy_latency_index to 3, because it is
 310                  * better to have underflows than system crashes.
 311                  */
 312                 dummy_latency_index = max_latency_table_entries - 1;
 313         }
 314
 315         return dummy_latency_index;
 316 }
 317
 318 /**
 319  * dcn32_helper_populate_phantom_dlg_params - Get DLG params for phantom pipes
 320  * and populate pipe_ctx with those params.
 321  * @dc: [in] current dc state
 322  * @context: [in] new dc state
 323  * @pipes: [in] DML pipe params array
 324  * @pipe_cnt: [in] DML pipe count
 325  *
 326  * This function must be called AFTER the phantom pipes are added to context
 327  * and run through DML (so that the DLG params for the phantom pipes can be
 328  * populated), and BEFORE we program the timing for the phantom pipes.
 329  */
 330 void dcn32_helper_populate_phantom_dlg_params(struct dc *dc,
 331                                               struct dc_state *context,
 332                                               display_e2e_pipe_params_st *pipes,
 333                                               int pipe_cnt)
 334 {
 335         uint32_t i, pipe_idx;
 336
 337         dc_assert_fp_enabled();
 338
 339         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 340                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 341
 342                 if (!pipe->stream)
 343                         continue;
 344
 345                 if (pipe->plane_state && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {
 346                         pipes[pipe_idx].pipe.dest.vstartup_start =
 347                                 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 348                         pipes[pipe_idx].pipe.dest.vupdate_offset =
 349                                 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 350                         pipes[pipe_idx].pipe.dest.vupdate_width =
 351                                 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 352                         pipes[pipe_idx].pipe.dest.vready_offset =
 353                                 get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 354                         pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest;
 355                 }
 356                 pipe_idx++;
 357         }
 358 }
 359
 360 static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *entry)
 361 {
 362         float memory_bw_kbytes_sec;
 363         float fabric_bw_kbytes_sec;
 364         float sdp_bw_kbytes_sec;
 365         float limiting_bw_kbytes_sec;
 366
 367         memory_bw_kbytes_sec = entry->dram_speed_mts *
 368                                 dcn3_2_soc.num_chans *
 369                                 dcn3_2_soc.dram_channel_width_bytes *
 370                                 ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100);
 371
 372         fabric_bw_kbytes_sec = entry->fabricclk_mhz *
 373                                 dcn3_2_soc.return_bus_width_bytes *
 374                                 ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100);
 375
 376         sdp_bw_kbytes_sec = entry->dcfclk_mhz *
 377                                 dcn3_2_soc.return_bus_width_bytes *
 378                                 ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100);
 379
 380         limiting_bw_kbytes_sec = memory_bw_kbytes_sec;
 381
 382         if (fabric_bw_kbytes_sec < limiting_bw_kbytes_sec)
 383                 limiting_bw_kbytes_sec = fabric_bw_kbytes_sec;
 384
 385         if (sdp_bw_kbytes_sec < limiting_bw_kbytes_sec)
 386                 limiting_bw_kbytes_sec = sdp_bw_kbytes_sec;
 387
 388         return limiting_bw_kbytes_sec;
 389 }
 390
 391 static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry)
 392 {
 393         if (entry->dcfclk_mhz > 0) {
 394                 float bw_on_sdp = entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100);
 395
 396                 entry->fabricclk_mhz = bw_on_sdp / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100));
 397                 entry->dram_speed_mts = bw_on_sdp / (dcn3_2_soc.num_chans *
 398                                 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100));
 399         } else if (entry->fabricclk_mhz > 0) {
 400                 float bw_on_fabric = entry->fabricclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100);
 401
 402                 entry->dcfclk_mhz = bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100));
 403                 entry->dram_speed_mts = bw_on_fabric / (dcn3_2_soc.num_chans *
 404                                 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100));
 405         } else if (entry->dram_speed_mts > 0) {
 406                 float bw_on_dram = entry->dram_speed_mts * dcn3_2_soc.num_chans *
 407                                 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100);
 408
 409                 entry->fabricclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100));
 410                 entry->dcfclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100));
 411         }
 412 }
 413
 414 static void insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table,
 415                                     unsigned int *num_entries,
 416                                     struct _vcs_dpi_voltage_scaling_st *entry)
 417 {
 418         int i = 0;
 419         int index = 0;
 420
 421         dc_assert_fp_enabled();
 422
 423         if (*num_entries == 0) {
 424                 table[0] = *entry;
 425                 (*num_entries)++;
 426         } else {
 427                 while (entry->net_bw_in_kbytes_sec > table[index].net_bw_in_kbytes_sec) {
 428                         index++;
 429                         if (index >= *num_entries)
 430                                 break;
 431                 }
 432
 433                 for (i = *num_entries; i > index; i--)
 434                         table[i] = table[i - 1];
 435
 436                 table[index] = *entry;
 437                 (*num_entries)++;
 438         }
 439 }
 440
 441 /**
 442  * dcn32_set_phantom_stream_timing - Set timing params for the phantom stream
 443  * @dc: current dc state
 444  * @context: new dc state
 445  * @ref_pipe: Main pipe for the phantom stream
 446  * @phantom_stream: target phantom stream state
 447  * @pipes: DML pipe params
 448  * @pipe_cnt: number of DML pipes
 449  * @dc_pipe_idx: DC pipe index for the main pipe (i.e. ref_pipe)
 450  *
 451  * Set timing params of the phantom stream based on calculated output from DML.
 452  * This function first gets the DML pipe index using the DC pipe index, then
 453  * calls into DML (get_subviewport_lines_needed_in_mall) to get the number of
 454  * lines required for SubVP MCLK switching and assigns to the phantom stream
 455  * accordingly.
 456  *
 457  * - The number of SubVP lines calculated in DML does not take into account
 458  * FW processing delays and required pstate allow width, so we must include
 459  * that separately.
 460  *
 461  * - Set phantom backporch = vstartup of main pipe
 462  */
 463 void dcn32_set_phantom_stream_timing(struct dc *dc,
 464                                      struct dc_state *context,
 465                                      struct pipe_ctx *ref_pipe,
 466                                      struct dc_stream_state *phantom_stream,
 467                                      display_e2e_pipe_params_st *pipes,
 468                                      unsigned int pipe_cnt,
 469                                      unsigned int dc_pipe_idx)
 470 {
 471         unsigned int i, pipe_idx;
 472         struct pipe_ctx *pipe;
 473         uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines;
 474         unsigned int num_dpp;
 475         unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel;
 476         unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
 477         unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel];
 478         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 479         struct dc_stream_state *main_stream = ref_pipe->stream;
 480
 481         dc_assert_fp_enabled();
 482
 483         // Find DML pipe index (pipe_idx) using dc_pipe_idx
 484         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 485                 pipe = &context->res_ctx.pipe_ctx[i];
 486
 487                 if (!pipe->stream)
 488                         continue;
 489
 490                 if (i == dc_pipe_idx)
 491                         break;
 492
 493                 pipe_idx++;
 494         }
 495
 496         // Calculate lines required for pstate allow width and FW processing delays
 497         pstate_width_fw_delay_lines = ((double)(dc->caps.subvp_fw_processing_delay_us +
 498                         dc->caps.subvp_pstate_allow_width_us) / 1000000) *
 499                         (ref_pipe->stream->timing.pix_clk_100hz * 100) /
 500                         (double)ref_pipe->stream->timing.h_total;
 501
 502         // Update clks_cfg for calling into recalculate
 503         pipes[0].clks_cfg.voltage = vlevel;
 504         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
 505         pipes[0].clks_cfg.socclk_mhz = socclk;
 506
 507         // DML calculation for MALL region doesn't take into account FW delay
 508         // and required pstate allow width for multi-display cases
 509         /* Add 16 lines margin to the MALL REGION because SUB_VP_START_LINE must be aligned
 510          * to 2 swaths (i.e. 16 lines)
 511          */
 512         phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) +
 513                                 pstate_width_fw_delay_lines + dc->caps.subvp_swath_height_margin_lines;
 514
 515         // W/A for DCC corruption with certain high resolution timings.
 516         // Determing if pipesplit is used. If so, add meta_row_height to the phantom vactive.
 517         num_dpp = vba->NoOfDPP[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]];
 518         phantom_vactive += num_dpp > 1 ? vba->meta_row_height[vba->pipe_plane[pipe_idx]] : 0;
 519
 520         /* dc->debug.subvp_extra_lines 0 by default*/
 521         phantom_vactive += dc->debug.subvp_extra_lines;
 522
 523         // For backporch of phantom pipe, use vstartup of the main pipe
 524         phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 525
 526         phantom_stream->dst.y = 0;
 527         phantom_stream->dst.height = phantom_vactive;
 528         /* When scaling, DML provides the end to end required number of lines for MALL.
 529          * dst.height is always correct for this case, but src.height is not which causes a
 530          * delta between main and phantom pipe scaling outputs. Need to adjust src.height on
 531          * phantom for this case.
 532          */
 533         phantom_stream->src.y = 0;
 534         phantom_stream->src.height = (double)phantom_vactive * (double)main_stream->src.height / (double)main_stream->dst.height;
 535
 536         phantom_stream->timing.v_addressable = phantom_vactive;
 537         phantom_stream->timing.v_front_porch = 1;
 538         phantom_stream->timing.v_total = phantom_stream->timing.v_addressable +
 539                                                 phantom_stream->timing.v_front_porch +
 540                                                 phantom_stream->timing.v_sync_width +
 541                                                 phantom_bp;
 542         phantom_stream->timing.flags.DSC = 0; // Don't need DSC for phantom timing
 543 }
 544
 545 /**
 546  * dcn32_get_num_free_pipes - Calculate number of free pipes
 547  * @dc: current dc state
 548  * @context: new dc state
 549  *
 550  * This function assumes that a "used" pipe is a pipe that has
 551  * both a stream and a plane assigned to it.
 552  *
 553  * Return: Number of free pipes available in the context
 554  */
 555 static unsigned int dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context)
 556 {
 557         unsigned int i;
 558         unsigned int free_pipes = 0;
 559         unsigned int num_pipes = 0;
 560
 561         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 562                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 563
 564                 if (pipe->stream && !pipe->top_pipe) {
 565                         while (pipe) {
 566                                 num_pipes++;
 567                                 pipe = pipe->bottom_pipe;
 568                         }
 569                 }
 570         }
 571
 572         free_pipes = dc->res_pool->pipe_count - num_pipes;
 573         return free_pipes;
 574 }
 575
 576 /**
 577  * dcn32_assign_subvp_pipe - Function to decide which pipe will use Sub-VP.
 578  * @dc: current dc state
 579  * @context: new dc state
 580  * @index: [out] dc pipe index for the pipe chosen to have phantom pipes assigned
 581  *
 582  * We enter this function if we are Sub-VP capable (i.e. enough pipes available)
 583  * and regular P-State switching (i.e. VACTIVE/VBLANK) is not supported, or if
 584  * we are forcing SubVP P-State switching on the current config.
 585  *
 586  * The number of pipes used for the chosen surface must be less than or equal to the
 587  * number of free pipes available.
 588  *
 589  * In general we choose surfaces with the longest frame time first (better for SubVP + VBLANK).
 590  * For multi-display cases the ActiveDRAMClockChangeMargin doesn't provide enough info on its own
 591  * for determining which should be the SubVP pipe (need a way to determine if a pipe / plane doesn't
 592  * support MCLK switching naturally [i.e. ACTIVE or VBLANK]).
 593  *
 594  * Return: True if a valid pipe assignment was found for Sub-VP. Otherwise false.
 595  */
 596 static bool dcn32_assign_subvp_pipe(struct dc *dc,
 597                                     struct dc_state *context,
 598                                     unsigned int *index)
 599 {
 600         unsigned int i, pipe_idx;
 601         unsigned int max_frame_time = 0;
 602         bool valid_assignment_found = false;
 603         unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context);
 604         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 605
 606         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 607                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 608                 unsigned int num_pipes = 0;
 609                 unsigned int refresh_rate = 0;
 610
 611                 if (!pipe->stream)
 612                         continue;
 613
 614                 // Round up
 615                 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
 616                                 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
 617                                 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
 618                 /* SubVP pipe candidate requirements:
 619                  * - Refresh rate < 120hz
 620                  * - Not able to switch in vactive naturally (switching in active means the
 621                  *   DET provides enough buffer to hide the P-State switch latency -- trying
 622                  *   to combine this with SubVP can cause issues with the scheduling).
 623                  * - Not TMZ surface
 624                  */
 625                 if (pipe->plane_state && !pipe->top_pipe && !dcn32_is_center_timing(pipe) &&
 626                                 (!dcn32_is_psr_capable(pipe) || (context->stream_count == 1 && dc->caps.dmub_caps.subvp_psr)) &&
 627                                 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_NONE &&
 628                                 (refresh_rate < 120 || dcn32_allow_subvp_high_refresh_rate(dc, context, pipe)) &&
 629                                 !pipe->plane_state->address.tmz_surface &&
 630                                 (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0 ||
 631                                 (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 &&
 632                                                 dcn32_allow_subvp_with_active_margin(pipe)))) {
 633                         while (pipe) {
 634                                 num_pipes++;
 635                                 pipe = pipe->bottom_pipe;
 636                         }
 637
 638                         pipe = &context->res_ctx.pipe_ctx[i];
 639                         if (num_pipes <= free_pipes) {
 640                                 struct dc_stream_state *stream = pipe->stream;
 641                                 unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total /
 642                                                 (double)(stream->timing.pix_clk_100hz * 100)) * 1000000;
 643                                 if (frame_us > max_frame_time) {
 644                                         *index = i;
 645                                         max_frame_time = frame_us;
 646                                         valid_assignment_found = true;
 647                                 }
 648                         }
 649                 }
 650                 pipe_idx++;
 651         }
 652         return valid_assignment_found;
 653 }
 654
 655 /**
 656  * dcn32_enough_pipes_for_subvp - Function to check if there are "enough" pipes for SubVP.
 657  * @dc: current dc state
 658  * @context: new dc state
 659  *
 660  * This function returns true if there are enough free pipes
 661  * to create the required phantom pipes for any given stream
 662  * (that does not already have phantom pipe assigned).
 663  *
 664  * e.g. For a 2 stream config where the first stream uses one
 665  * pipe and the second stream uses 2 pipes (i.e. pipe split),
 666  * this function will return true because there is 1 remaining
 667  * pipe which can be used as the phantom pipe for the non pipe
 668  * split pipe.
 669  *
 670  * Return:
 671  * True if there are enough free pipes to assign phantom pipes to at least one
 672  * stream that does not already have phantom pipes assigned. Otherwise false.
 673  */
 674 static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context)
 675 {
 676         unsigned int i, split_cnt, free_pipes;
 677         unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1
 678         bool subvp_possible = false;
 679
 680         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 681                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 682
 683                 // Find the minimum pipe split count for non SubVP pipes
 684                 if (resource_is_pipe_type(pipe, OPP_HEAD) &&
 685                         dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_NONE) {
 686                         split_cnt = 0;
 687                         while (pipe) {
 688                                 split_cnt++;
 689                                 pipe = pipe->bottom_pipe;
 690                         }
 691
 692                         if (split_cnt < min_pipe_split)
 693                                 min_pipe_split = split_cnt;
 694                 }
 695         }
 696
 697         free_pipes = dcn32_get_num_free_pipes(dc, context);
 698
 699         // SubVP only possible if at least one pipe is being used (i.e. free_pipes
 700         // should not equal to the pipe_count)
 701         if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count)
 702                 subvp_possible = true;
 703
 704         return subvp_possible;
 705 }
 706
 707 /**
 708  * subvp_subvp_schedulable - Determine if SubVP + SubVP config is schedulable
 709  * @dc: current dc state
 710  * @context: new dc state
 711  *
 712  * High level algorithm:
 713  * 1. Find longest microschedule length (in us) between the two SubVP pipes
 714  * 2. Check if the worst case overlap (VBLANK in middle of ACTIVE) for both
 715  * pipes still allows for the maximum microschedule to fit in the active
 716  * region for both pipes.
 717  *
 718  * Return: True if the SubVP + SubVP config is schedulable, false otherwise
 719  */
 720 static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context)
 721 {
 722         struct pipe_ctx *subvp_pipes[2];
 723         struct dc_stream_state *phantom = NULL;
 724         uint32_t microschedule_lines = 0;
 725         uint32_t index = 0;
 726         uint32_t i;
 727         uint32_t max_microschedule_us = 0;
 728         int32_t vactive1_us, vactive2_us, vblank1_us, vblank2_us;
 729
 730         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 731                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 732                 uint32_t time_us = 0;
 733
 734                 /* Loop to calculate the maximum microschedule time between the two SubVP pipes,
 735                  * and also to store the two main SubVP pipe pointers in subvp_pipes[2].
 736                  */
 737                 if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
 738                         dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {
 739                         phantom = dc_state_get_paired_subvp_stream(context, pipe->stream);
 740                         microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) +
 741                                         phantom->timing.v_addressable;
 742
 743                         // Round up when calculating microschedule time (+ 1 at the end)
 744                         time_us = (microschedule_lines * phantom->timing.h_total) /
 745                                         (double)(phantom->timing.pix_clk_100hz * 100) * 1000000 +
 746                                                 dc->caps.subvp_prefetch_end_to_mall_start_us +
 747                                                 dc->caps.subvp_fw_processing_delay_us + 1;
 748                         if (time_us > max_microschedule_us)
 749                                 max_microschedule_us = time_us;
 750
 751                         subvp_pipes[index] = pipe;
 752                         index++;
 753
 754                         // Maximum 2 SubVP pipes
 755                         if (index == 2)
 756                                 break;
 757                 }
 758         }
 759         vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) /
 760                         (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 761         vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) /
 762                                 (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 763         vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) *
 764                         subvp_pipes[0]->stream->timing.h_total) /
 765                         (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 766         vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) *
 767                         subvp_pipes[1]->stream->timing.h_total) /
 768                         (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 769
 770         if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us &&
 771             (vactive2_us - vblank1_us) / 2 > max_microschedule_us)
 772                 return true;
 773
 774         return false;
 775 }
 776
 777 /**
 778  * subvp_drr_schedulable() - Determine if SubVP + DRR config is schedulable
 779  * @dc: current dc state
 780  * @context: new dc state
 781  *
 782  * High level algorithm:
 783  * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe
 784  * 2. Determine the frame time for the DRR display when adding required margin for MCLK switching
 785  * (the margin is equal to the MALL region + DRR margin (500us))
 786  * 3.If (SubVP Active - Prefetch > Stretched DRR frame + max(MALL region, Stretched DRR frame))
 787  * then report the configuration as supported
 788  *
 789  * Return: True if the SubVP + DRR config is schedulable, false otherwise
 790  */
 791 static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context)
 792 {
 793         bool schedulable = false;
 794         uint32_t i;
 795         struct pipe_ctx *pipe = NULL;
 796         struct pipe_ctx *drr_pipe = NULL;
 797         struct dc_crtc_timing *main_timing = NULL;
 798         struct dc_crtc_timing *phantom_timing = NULL;
 799         struct dc_crtc_timing *drr_timing = NULL;
 800         int16_t prefetch_us = 0;
 801         int16_t mall_region_us = 0;
 802         int16_t drr_frame_us = 0;       // nominal frame time
 803         int16_t subvp_active_us = 0;
 804         int16_t stretched_drr_us = 0;
 805         int16_t drr_stretched_vblank_us = 0;
 806         int16_t max_vblank_mallregion = 0;
 807         struct dc_stream_state *phantom_stream;
 808         bool subvp_found = false;
 809         bool drr_found = false;
 810
 811         // Find SubVP pipe
 812         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 813                 pipe = &context->res_ctx.pipe_ctx[i];
 814
 815                 // We check for master pipe, but it shouldn't matter since we only need
 816                 // the pipe for timing info (stream should be same for any pipe splits)
 817                 if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
 818                                 !resource_is_pipe_type(pipe, DPP_PIPE))
 819                         continue;
 820
 821                 // Find the SubVP pipe
 822                 if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {
 823                         subvp_found = true;
 824                         break;
 825                 }
 826         }
 827
 828         // Find the DRR pipe
 829         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 830                 drr_pipe = &context->res_ctx.pipe_ctx[i];
 831
 832                 // We check for master pipe only
 833                 if (!resource_is_pipe_type(drr_pipe, OTG_MASTER) ||
 834                                 !resource_is_pipe_type(drr_pipe, DPP_PIPE))
 835                         continue;
 836
 837                 if (dc_state_get_pipe_subvp_type(context, drr_pipe) == SUBVP_NONE && drr_pipe->stream->ignore_msa_timing_param &&
 838                                 (drr_pipe->stream->allow_freesync || drr_pipe->stream->vrr_active_variable || drr_pipe->stream->vrr_active_fixed)) {
 839                         drr_found = true;
 840                         break;
 841                 }
 842         }
 843
 844         if (subvp_found && drr_found) {
 845                 phantom_stream = dc_state_get_paired_subvp_stream(context, pipe->stream);
 846                 main_timing = &pipe->stream->timing;
 847                 phantom_timing = &phantom_stream->timing;
 848                 drr_timing = &drr_pipe->stream->timing;
 849                 prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
 850                                 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
 851                                 dc->caps.subvp_prefetch_end_to_mall_start_us;
 852                 subvp_active_us = main_timing->v_addressable * main_timing->h_total /
 853                                 (double)(main_timing->pix_clk_100hz * 100) * 1000000;
 854                 drr_frame_us = drr_timing->v_total * drr_timing->h_total /
 855                                 (double)(drr_timing->pix_clk_100hz * 100) * 1000000;
 856                 // P-State allow width and FW delays already included phantom_timing->v_addressable
 857                 mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
 858                                 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
 859                 stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
 860                 drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total /
 861                                 (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us);
 862                 max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us;
 863         }
 864
 865         /* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the
 866          * highest refresh rate + margin that can support UCLK P-State switch) passes the static analysis
 867          * for VBLANK: (VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
 868          * and the max of (VBLANK blanking time, MALL region)).
 869          */
 870         if (stretched_drr_us < (1 / (double)drr_timing->min_refresh_in_uhz) * 1000000 * 1000000 &&
 871                         subvp_active_us - prefetch_us - stretched_drr_us - max_vblank_mallregion > 0)
 872                 schedulable = true;
 873
 874         return schedulable;
 875 }
 876
 877
 878 /**
 879  * subvp_vblank_schedulable - Determine if SubVP + VBLANK config is schedulable
 880  * @dc: current dc state
 881  * @context: new dc state
 882  *
 883  * High level algorithm:
 884  * 1. Get timing for SubVP pipe, phantom pipe, and VBLANK pipe
 885  * 2. If (SubVP Active - Prefetch > Vblank Frame Time + max(MALL region, Vblank blanking time))
 886  * then report the configuration as supported
 887  * 3. If the VBLANK display is DRR, then take the DRR static schedulability path
 888  *
 889  * Return: True if the SubVP + VBLANK/DRR config is schedulable, false otherwise
 890  */
 891 static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)
 892 {
 893         struct pipe_ctx *pipe = NULL;
 894         struct pipe_ctx *subvp_pipe = NULL;
 895         bool found = false;
 896         bool schedulable = false;
 897         uint32_t i = 0;
 898         uint8_t vblank_index = 0;
 899         uint16_t prefetch_us = 0;
 900         uint16_t mall_region_us = 0;
 901         uint16_t vblank_frame_us = 0;
 902         uint16_t subvp_active_us = 0;
 903         uint16_t vblank_blank_us = 0;
 904         uint16_t max_vblank_mallregion = 0;
 905         struct dc_crtc_timing *main_timing = NULL;
 906         struct dc_crtc_timing *phantom_timing = NULL;
 907         struct dc_crtc_timing *vblank_timing = NULL;
 908         struct dc_stream_state *phantom_stream;
 909         enum mall_stream_type pipe_mall_type;
 910
 911         /* For SubVP + VBLANK/DRR cases, we assume there can only be
 912          * a single VBLANK/DRR display. If DML outputs SubVP + VBLANK
 913          * is supported, it is either a single VBLANK case or two VBLANK
 914          * displays which are synchronized (in which case they have identical
 915          * timings).
 916          */
 917         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 918                 pipe = &context->res_ctx.pipe_ctx[i];
 919                 pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);
 920
 921                 // We check for master pipe, but it shouldn't matter since we only need
 922                 // the pipe for timing info (stream should be same for any pipe splits)
 923                 if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
 924                                 !resource_is_pipe_type(pipe, DPP_PIPE))
 925                         continue;
 926
 927                 if (!found && pipe_mall_type == SUBVP_NONE) {
 928                         // Found pipe which is not SubVP or Phantom (i.e. the VBLANK pipe).
 929                         vblank_index = i;
 930                         found = true;
 931                 }
 932
 933                 if (!subvp_pipe && pipe_mall_type == SUBVP_MAIN)
 934                         subvp_pipe = pipe;
 935         }
 936         if (found) {
 937                 phantom_stream = dc_state_get_paired_subvp_stream(context, subvp_pipe->stream);
 938                 main_timing = &subvp_pipe->stream->timing;
 939                 phantom_timing = &phantom_stream->timing;
 940                 vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;
 941                 // Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe
 942                 // Also include the prefetch end to mallstart delay time
 943                 prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
 944                                 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
 945                                 dc->caps.subvp_prefetch_end_to_mall_start_us;
 946                 // P-State allow width and FW delays already included phantom_timing->v_addressable
 947                 mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
 948                                 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
 949                 vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total /
 950                                 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
 951                 vblank_blank_us =  (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total /
 952                                 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
 953                 subvp_active_us = main_timing->v_addressable * main_timing->h_total /
 954                                 (double)(main_timing->pix_clk_100hz * 100) * 1000000;
 955                 max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us;
 956
 957                 // Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
 958                 // and the max of (VBLANK blanking time, MALL region)
 959                 // TODO: Possibly add some margin (i.e. the below conditions should be [...] > X instead of [...] > 0)
 960                 if (subvp_active_us - prefetch_us - vblank_frame_us - max_vblank_mallregion > 0)
 961                         schedulable = true;
 962         }
 963         return schedulable;
 964 }
 965
 966 /**
 967  * subvp_subvp_admissable() - Determine if subvp + subvp config is admissible
 968  *
 969  * @dc: Current DC state
 970  * @context: New DC state to be programmed
 971  *
 972  * SubVP + SubVP is admissible under the following conditions:
 973  * - All SubVP pipes are < 120Hz OR
 974  * - All SubVP pipes are >= 120hz
 975  *
 976  * Return: True if admissible, false otherwise
 977  */
 978 static bool subvp_subvp_admissable(struct dc *dc,
 979                                 struct dc_state *context)
 980 {
 981         bool result = false;
 982         uint32_t i;
 983         uint8_t subvp_count = 0;
 984         uint32_t min_refresh = subvp_high_refresh_list.min_refresh, max_refresh = 0;
 985         uint64_t refresh_rate = 0;
 986
 987         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 988                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 989
 990                 if (!pipe->stream)
 991                         continue;
 992
 993                 if (pipe->plane_state && !pipe->top_pipe &&
 994                                 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {
 995                         refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +
 996                                 pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1);
 997                         refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
 998                         refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);
 999
1000                         if ((uint32_t)refresh_rate < min_refresh)
1001                                 min_refresh = (uint32_t)refresh_rate;
1002                         if ((uint32_t)refresh_rate > max_refresh)
1003                                 max_refresh = (uint32_t)refresh_rate;
1004                         subvp_count++;
1005                 }
1006         }
1007
1008         if (subvp_count == 2 && ((min_refresh < 120 && max_refresh < 120) ||
1009                 (min_refresh >= subvp_high_refresh_list.min_refresh &&
1010                                 max_refresh <= subvp_high_refresh_list.max_refresh)))
1011                 result = true;
1012
1013         return result;
1014 }
1015
1016 /**
1017  * subvp_validate_static_schedulability - Check which SubVP case is calculated
1018  * and handle static analysis based on the case.
1019  * @dc: current dc state
1020  * @context: new dc state
1021  * @vlevel: Voltage level calculated by DML
1022  *
1023  * Three cases:
1024  * 1. SubVP + SubVP
1025  * 2. SubVP + VBLANK (DRR checked internally)
1026  * 3. SubVP + VACTIVE (currently unsupported)
1027  *
1028  * Return: True if statically schedulable, false otherwise
1029  */
1030 static bool subvp_validate_static_schedulability(struct dc *dc,
1031                                 struct dc_state *context,
1032                                 int vlevel)
1033 {
1034         bool schedulable = false;
1035         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1036         uint32_t i, pipe_idx;
1037         uint8_t subvp_count = 0;
1038         uint8_t vactive_count = 0;
1039         uint8_t non_subvp_pipes = 0;
1040
1041         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1042                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1043                 enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);
1044
1045                 if (!pipe->stream)
1046                         continue;
1047
1048                 if (pipe->plane_state && !pipe->top_pipe) {
1049                         if (pipe_mall_type == SUBVP_MAIN)
1050                                 subvp_count++;
1051                         if (pipe_mall_type == SUBVP_NONE)
1052                                 non_subvp_pipes++;
1053                 }
1054
1055                 // Count how many planes that aren't SubVP/phantom are capable of VACTIVE
1056                 // switching (SubVP + VACTIVE unsupported). In situations where we force
1057                 // SubVP for a VACTIVE plane, we don't want to increment the vactive_count.
1058                 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vlevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 &&
1059                                 pipe_mall_type == SUBVP_NONE) {
1060                         vactive_count++;
1061                 }
1062                 pipe_idx++;
1063         }
1064
1065         if (subvp_count == 2) {
1066                 // Static schedulability check for SubVP + SubVP case
1067                 schedulable = subvp_subvp_admissable(dc, context) && subvp_subvp_schedulable(dc, context);
1068         } else if (subvp_count == 1 && non_subvp_pipes == 0) {
1069                 // Single SubVP configs will be supported by default as long as it's suppported by DML
1070                 schedulable = true;
1071         } else if (subvp_count == 1 && non_subvp_pipes == 1) {
1072                 if (dcn32_subvp_drr_admissable(dc, context))
1073                         schedulable = subvp_drr_schedulable(dc, context);
1074                 else if (dcn32_subvp_vblank_admissable(dc, context, vlevel))
1075                         schedulable = subvp_vblank_schedulable(dc, context);
1076         } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_mall_sub_vp &&
1077                         vactive_count > 0) {
1078                 // For single display SubVP cases, DML will output dm_dram_clock_change_vactive_w_mall_sub_vp by default.
1079                 // We tell the difference between SubVP vs. SubVP + VACTIVE by checking the vactive_count.
1080                 // SubVP + VACTIVE currently unsupported
1081                 schedulable = false;
1082         }
1083         return schedulable;
1084 }
1085
1086 static void assign_subvp_index(struct dc *dc, struct dc_state *context)
1087 {
1088         int i;
1089         int index = 0;
1090
1091         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1092                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1093
1094                 if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) &&
1095                                 dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) {
1096                         pipe_ctx->subvp_index = index++;
1097                 } else {
1098                         pipe_ctx->subvp_index = 0;
1099                 }
1100         }
1101 }
1102
1103 struct pipe_slice_table {
1104         struct {
1105                 struct dc_stream_state *stream;
1106                 int slice_count;
1107         } odm_combines[MAX_STREAMS];
1108         int odm_combine_count;
1109
1110         struct {
1111                 struct pipe_ctx *pri_pipe;
1112                 struct dc_plane_state *plane;
1113                 int slice_count;
1114         } mpc_combines[MAX_PLANES];
1115         int mpc_combine_count;
1116 };
1117
1118
1119 static void update_slice_table_for_stream(struct pipe_slice_table *table,
1120                 struct dc_stream_state *stream, int diff)
1121 {
1122         int i;
1123
1124         for (i = 0; i < table->odm_combine_count; i++) {
1125                 if (table->odm_combines[i].stream == stream) {
1126                         table->odm_combines[i].slice_count += diff;
1127                         break;
1128                 }
1129         }
1130
1131         if (i == table->odm_combine_count) {
1132                 table->odm_combine_count++;
1133                 table->odm_combines[i].stream = stream;
1134                 table->odm_combines[i].slice_count = diff;
1135         }
1136 }
1137
1138 static void update_slice_table_for_plane(struct pipe_slice_table *table,
1139                 struct pipe_ctx *dpp_pipe, struct dc_plane_state *plane, int diff)
1140 {
1141         int i;
1142         struct pipe_ctx *pri_dpp_pipe = resource_get_primary_dpp_pipe(dpp_pipe);
1143
1144         for (i = 0; i < table->mpc_combine_count; i++) {
1145                 if (table->mpc_combines[i].plane == plane &&
1146                                 table->mpc_combines[i].pri_pipe == pri_dpp_pipe) {
1147                         table->mpc_combines[i].slice_count += diff;
1148                         break;
1149                 }
1150         }
1151
1152         if (i == table->mpc_combine_count) {
1153                 table->mpc_combine_count++;
1154                 table->mpc_combines[i].plane = plane;
1155                 table->mpc_combines[i].pri_pipe = pri_dpp_pipe;
1156                 table->mpc_combines[i].slice_count = diff;
1157         }
1158 }
1159
1160 static void init_pipe_slice_table_from_context(
1161                 struct pipe_slice_table *table,
1162                 struct dc_state *context)
1163 {
1164         int i, j;
1165         struct pipe_ctx *otg_master;
1166         struct pipe_ctx *dpp_pipes[MAX_PIPES];
1167         struct dc_stream_state *stream;
1168         int count;
1169
1170         memset(table, 0, sizeof(*table));
1171
1172         for (i = 0; i < context->stream_count; i++) {
1173                 stream = context->streams[i];
1174                 otg_master = resource_get_otg_master_for_stream(
1175                                 &context->res_ctx, stream);
1176                 count = resource_get_odm_slice_count(otg_master);
1177                 update_slice_table_for_stream(table, stream, count);
1178
1179                 count = resource_get_dpp_pipes_for_opp_head(otg_master,
1180                                 &context->res_ctx, dpp_pipes);
1181                 for (j = 0; j < count; j++)
1182                         if (dpp_pipes[j]->plane_state)
1183                                 update_slice_table_for_plane(table, dpp_pipes[j],
1184                                                 dpp_pipes[j]->plane_state, 1);
1185         }
1186 }
1187
1188 static bool update_pipe_slice_table_with_split_flags(
1189                 struct pipe_slice_table *table,
1190                 struct dc *dc,
1191                 struct dc_state *context,
1192                 struct vba_vars_st *vba,
1193                 int split[MAX_PIPES],
1194                 bool merge[MAX_PIPES])
1195 {
1196         /* NOTE: we are deprecating the support for the concept of pipe splitting
1197          * or pipe merging. Instead we append slices to the end and remove
1198          * slices from the end. The following code converts a pipe split or
1199          * merge to an append or remove operation.
1200          *
1201          * For example:
1202          * When split flags describe the following pipe connection transition
1203          *
1204          * from:
1205          *  pipe 0 (split=2) -> pipe 1 (split=2)
1206          * to: (old behavior)
1207          *  pipe 0 -> pipe 2 -> pipe 1 -> pipe 3
1208          *
1209          * the code below actually does:
1210          *  pipe 0 -> pipe 1 -> pipe 2 -> pipe 3
1211          *
1212          * This is the new intended behavior and for future DCNs we will retire
1213          * the old concept completely.
1214          */
1215         struct pipe_ctx *pipe;
1216         bool odm;
1217         int dc_pipe_idx, dml_pipe_idx = 0;
1218         bool updated = false;
1219
1220         for (dc_pipe_idx = 0;
1221                         dc_pipe_idx < dc->res_pool->pipe_count; dc_pipe_idx++) {
1222                 pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
1223                 if (resource_is_pipe_type(pipe, FREE_PIPE))
1224                         continue;
1225
1226                 if (merge[dc_pipe_idx]) {
1227                         if (resource_is_pipe_type(pipe, OPP_HEAD))
1228                                 /* merging OPP head means reducing ODM slice
1229                                  * count by 1
1230                                  */
1231                                 update_slice_table_for_stream(table, pipe->stream, -1);
1232                         else if (resource_is_pipe_type(pipe, DPP_PIPE) &&
1233                                         resource_get_odm_slice_index(resource_get_opp_head(pipe)) == 0)
1234                                 /* merging DPP pipe of the first ODM slice means
1235                                  * reducing MPC slice count by 1
1236                                  */
1237                                 update_slice_table_for_plane(table, pipe, pipe->plane_state, -1);
1238                         updated = true;
1239                 }
1240
1241                 if (split[dc_pipe_idx]) {
1242                         odm = vba->ODMCombineEnabled[vba->pipe_plane[dml_pipe_idx]] !=
1243                                         dm_odm_combine_mode_disabled;
1244                         if (odm && resource_is_pipe_type(pipe, OPP_HEAD))
1245                                 update_slice_table_for_stream(
1246                                                 table, pipe->stream, split[dc_pipe_idx] - 1);
1247                         else if (!odm && resource_is_pipe_type(pipe, DPP_PIPE))
1248                                 update_slice_table_for_plane(table, pipe,
1249                                                 pipe->plane_state, split[dc_pipe_idx] - 1);
1250                         updated = true;
1251                 }
1252                 dml_pipe_idx++;
1253         }
1254         return updated;
1255 }
1256
1257 static void update_pipes_with_slice_table(struct dc *dc, struct dc_state *context,
1258                 struct pipe_slice_table *table)
1259 {
1260         int i;
1261
1262         for (i = 0; i < table->odm_combine_count; i++)
1263                 resource_update_pipes_for_stream_with_slice_count(context,
1264                                 dc->current_state, dc->res_pool,
1265                                 table->odm_combines[i].stream,
1266                                 table->odm_combines[i].slice_count);
1267
1268         for (i = 0; i < table->mpc_combine_count; i++)
1269                 resource_update_pipes_for_plane_with_slice_count(context,
1270                                 dc->current_state, dc->res_pool,
1271                                 table->mpc_combines[i].plane,
1272                                 table->mpc_combines[i].slice_count);
1273 }
1274
1275 static bool update_pipes_with_split_flags(struct dc *dc, struct dc_state *context,
1276                 struct vba_vars_st *vba, int split[MAX_PIPES],
1277                 bool merge[MAX_PIPES])
1278 {
1279         struct pipe_slice_table slice_table;
1280         bool updated;
1281
1282         init_pipe_slice_table_from_context(&slice_table, context);
1283         updated = update_pipe_slice_table_with_split_flags(
1284                         &slice_table, dc, context, vba,
1285                         split, merge);
1286         update_pipes_with_slice_table(dc, context, &slice_table);
1287         return updated;
1288 }
1289
1290 static bool should_apply_odm_power_optimization(struct dc *dc,
1291                 struct dc_state *context, struct vba_vars_st *v, int *split,
1292                 bool *merge)
1293 {
1294         struct dc_stream_state *stream = context->streams[0];
1295         struct pipe_slice_table slice_table;
1296         int i;
1297
1298         /*
1299          * this debug flag allows us to disable ODM power optimization feature
1300          * unconditionally. we force the feature off if this is set to false.
1301          */
1302         if (!dc->debug.enable_single_display_2to1_odm_policy)
1303                 return false;
1304
1305         /* current design and test coverage is only limited to allow ODM power
1306          * optimization for single stream. Supporting it for multiple streams
1307          * use case would require additional algorithm to decide how to
1308          * optimize power consumption when there are not enough free pipes to
1309          * allocate for all the streams. This level of optimization would
1310          * require multiple attempts of revalidation to make an optimized
1311          * decision. Unfortunately We do not support revalidation flow in
1312          * current version of DML.
1313          */
1314         if (context->stream_count != 1)
1315                 return false;
1316
1317         /*
1318          * Our hardware doesn't support ODM for HDMI TMDS
1319          */
1320         if (dc_is_hdmi_signal(stream->signal))
1321                 return false;
1322
1323         /*
1324          * ODM Combine 2:1 requires horizontal timing divisible by 2 so each
1325          * ODM segment has the same size.
1326          */
1327         if (!is_h_timing_divisible_by_2(stream))
1328                 return false;
1329
1330         /*
1331          * No power benefits if the timing's pixel clock is not high enough to
1332          * raise display clock from minimum power state.
1333          */
1334         if (stream->timing.pix_clk_100hz * 100 <= DCN3_2_VMIN_DISPCLK_HZ)
1335                 return false;
1336
1337         if (dc->config.enable_windowed_mpo_odm) {
1338                 /*
1339                  * ODM power optimization should only be allowed if the feature
1340                  * can be seamlessly toggled off within an update. This would
1341                  * require that the feature is applied on top of a minimal
1342                  * state. A minimal state is defined as a state validated
1343                  * without the need of pipe split. Therefore, when transition to
1344                  * toggle the feature off, the same stream and plane
1345                  * configuration can be supported by the pipe resource in the
1346                  * first ODM slice alone without the need to acquire extra
1347                  * resources.
1348                  */
1349                 init_pipe_slice_table_from_context(&slice_table, context);
1350                 update_pipe_slice_table_with_split_flags(
1351                                 &slice_table, dc, context, v,
1352                                 split, merge);
1353                 for (i = 0; i < slice_table.mpc_combine_count; i++)
1354                         if (slice_table.mpc_combines[i].slice_count > 1)
1355                                 return false;
1356
1357                 for (i = 0; i < slice_table.odm_combine_count; i++)
1358                         if (slice_table.odm_combines[i].slice_count > 1)
1359                                 return false;
1360         } else {
1361                 /*
1362                  * the new ODM power optimization feature reduces software
1363                  * design limitation and allows ODM power optimization to be
1364                  * supported even with presence of overlay planes. The new
1365                  * feature is enabled based on enable_windowed_mpo_odm flag. If
1366                  * the flag is not set, we limit our feature scope due to
1367                  * previous software design limitation
1368                  */
1369                 if (context->stream_status[0].plane_count != 1)
1370                         return false;
1371
1372                 if (memcmp(&context->stream_status[0].plane_states[0]->clip_rect,
1373                                 &stream->src, sizeof(struct rect)) != 0)
1374                         return false;
1375
1376                 if (stream->src.width >= 5120 &&
1377                                 stream->src.width > stream->dst.width)
1378                         return false;
1379         }
1380         return true;
1381 }
1382
1383 static void try_odm_power_optimization_and_revalidate(
1384                 struct dc *dc,
1385                 struct dc_state *context,
1386                 display_e2e_pipe_params_st *pipes,
1387                 int *split,
1388                 bool *merge,
1389                 unsigned int *vlevel,
1390                 int pipe_cnt)
1391 {
1392         int i;
1393         unsigned int new_vlevel;
1394         unsigned int cur_policy[MAX_PIPES];
1395
1396         for (i = 0; i < pipe_cnt; i++) {
1397                 cur_policy[i] = pipes[i].pipe.dest.odm_combine_policy;
1398                 pipes[i].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;
1399         }
1400
1401         new_vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1402
1403         if (new_vlevel < context->bw_ctx.dml.soc.num_states) {
1404                 memset(split, 0, MAX_PIPES * sizeof(int));
1405                 memset(merge, 0, MAX_PIPES * sizeof(bool));
1406                 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, new_vlevel, split, merge);
1407                 context->bw_ctx.dml.vba.VoltageLevel = *vlevel;
1408         } else {
1409                 for (i = 0; i < pipe_cnt; i++)
1410                         pipes[i].pipe.dest.odm_combine_policy = cur_policy[i];
1411         }
1412 }
1413
1414 static bool is_test_pattern_enabled(
1415                 struct dc_state *context)
1416 {
1417         int i;
1418
1419         for (i = 0; i < context->stream_count; i++) {
1420                 if (context->streams[i]->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE)
1421                         return true;
1422         }
1423
1424         return false;
1425 }
1426
1427 static void dcn32_full_validate_bw_helper(struct dc *dc,
1428                                    struct dc_state *context,
1429                                    display_e2e_pipe_params_st *pipes,
1430                                    int *vlevel,
1431                                    int *split,
1432                                    bool *merge,
1433                                    int *pipe_cnt)
1434 {
1435         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1436         unsigned int dc_pipe_idx = 0;
1437         int i = 0;
1438         bool found_supported_config = false;
1439         int vlevel_temp = 0;
1440
1441         dc_assert_fp_enabled();
1442
1443         /*
1444          * DML favors voltage over p-state, but we're more interested in
1445          * supporting p-state over voltage. We can't support p-state in
1446          * prefetch mode > 0 so try capping the prefetch mode to start.
1447          * Override present for testing.
1448          */
1449         if (dc->debug.dml_disallow_alternate_prefetch_modes)
1450                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1451                         dm_prefetch_support_uclk_fclk_and_stutter;
1452         else
1453                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1454                         dm_prefetch_support_uclk_fclk_and_stutter_if_possible;
1455
1456         *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1457         /* This may adjust vlevel and maxMpcComb */
1458         if (*vlevel < context->bw_ctx.dml.soc.num_states) {
1459                 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
1460                 vba->VoltageLevel = *vlevel;
1461         }
1462
1463         /* Conditions for setting up phantom pipes for SubVP:
1464          * 1. Not force disable SubVP
1465          * 2. Full update (i.e. !fast_validate)
1466          * 3. Enough pipes are available to support SubVP (TODO: Which pipes will use VACTIVE / VBLANK / SUBVP?)
1467          * 4. Display configuration passes validation
1468          * 5. (Config doesn't support MCLK in VACTIVE/VBLANK || dc->debug.force_subvp_mclk_switch)
1469          */
1470         if (!dc->debug.force_disable_subvp && !dc->caps.dmub_caps.gecc_enable && dcn32_all_pipes_have_stream_and_plane(dc, context) &&
1471             !dcn32_mpo_in_use(context) && !dcn32_any_surfaces_rotated(dc, context) && !is_test_pattern_enabled(context) &&
1472                 (*vlevel == context->bw_ctx.dml.soc.num_states || (vba->DRAMSpeedPerState[*vlevel] != vba->DRAMSpeedPerState[0] &&
1473                                 vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported) ||
1474             vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported ||
1475             dc->debug.force_subvp_mclk_switch)) {
1476
1477                 dcn32_merge_pipes_for_subvp(dc, context);
1478                 memset(merge, 0, MAX_PIPES * sizeof(bool));
1479
1480                 vlevel_temp = *vlevel;
1481                 /* to re-initialize viewport after the pipe merge */
1482                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1483                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1484
1485                         if (!pipe_ctx->plane_state || !pipe_ctx->stream)
1486                                 continue;
1487
1488                         resource_build_scaling_params(pipe_ctx);
1489                 }
1490
1491                 while (!found_supported_config && dcn32_enough_pipes_for_subvp(dc, context) &&
1492                         dcn32_assign_subvp_pipe(dc, context, &dc_pipe_idx)) {
1493                         /* For the case where *vlevel = num_states, bandwidth validation has failed for this config.
1494                          * Adding phantom pipes won't change the validation result, so change the DML input param
1495                          * for P-State support before adding phantom pipes and recalculating the DML result.
1496                          * However, this case is only applicable for SubVP + DRR cases because the prefetch mode
1497                          * will not allow for switch in VBLANK. The DRR display must have it's VBLANK stretched
1498                          * enough to support MCLK switching.
1499                          */
1500                         if (*vlevel == context->bw_ctx.dml.soc.num_states &&
1501                                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final ==
1502                                         dm_prefetch_support_uclk_fclk_and_stutter) {
1503                                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1504                                                                 dm_prefetch_support_fclk_and_stutter;
1505                                 /* There are params (such as FabricClock) that need to be recalculated
1506                                  * after validation fails (otherwise it will be 0). Calculation for
1507                                  * phantom vactive requires call into DML, so we must ensure all the
1508                                  * vba params are valid otherwise we'll get incorrect phantom vactive.
1509                                  */
1510                                 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1511                         }
1512
1513                         dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx);
1514
1515                         *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
1516                         // Populate dppclk to trigger a recalculate in dml_get_voltage_level
1517                         // so the phantom pipe DLG params can be assigned correctly.
1518                         pipes[0].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, *pipe_cnt, 0);
1519                         *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1520
1521                         /* Check that vlevel requested supports pstate or not
1522                          * if not, select the lowest vlevel that supports it
1523                          */
1524                         for (i = *vlevel; i < context->bw_ctx.dml.soc.num_states; i++) {
1525                                 if (vba->DRAMClockChangeSupport[i][vba->maxMpcComb] != dm_dram_clock_change_unsupported) {
1526                                         *vlevel = i;
1527                                         break;
1528                                 }
1529                         }
1530
1531                         if (*vlevel < context->bw_ctx.dml.soc.num_states
1532                             && subvp_validate_static_schedulability(dc, context, *vlevel))
1533                                 found_supported_config = true;
1534                         if (found_supported_config) {
1535                                 // For SubVP + DRR cases, we can force the lowest vlevel that supports the mode
1536                                 if (dcn32_subvp_drr_admissable(dc, context) && subvp_drr_schedulable(dc, context)) {
1537                                         /* find lowest vlevel that supports the config */
1538                                         for (i = *vlevel; i >= 0; i--) {
1539                                                 if (vba->ModeSupport[i][vba->maxMpcComb]) {
1540                                                         *vlevel = i;
1541                                                 } else {
1542                                                         break;
1543                                                 }
1544                                         }
1545                                 }
1546                         }
1547                 }
1548
1549                 if (vba->DRAMSpeedPerState[*vlevel] >= vba->DRAMSpeedPerState[vlevel_temp])
1550                         found_supported_config = false;
1551
1552                 // If SubVP pipe config is unsupported (or cannot be used for UCLK switching)
1553                 // remove phantom pipes and repopulate dml pipes
1554                 if (!found_supported_config) {
1555                         dc_state_remove_phantom_streams_and_planes(dc, context);
1556                         dc_state_release_phantom_streams_and_planes(dc, context);
1557                         vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] = dm_dram_clock_change_unsupported;
1558                         *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
1559
1560                         *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1561                         /* This may adjust vlevel and maxMpcComb */
1562                         if (*vlevel < context->bw_ctx.dml.soc.num_states) {
1563                                 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
1564                                 vba->VoltageLevel = *vlevel;
1565                         }
1566                 } else {
1567                         // Most populate phantom DLG params before programming hardware / timing for phantom pipe
1568                         dcn32_helper_populate_phantom_dlg_params(dc, context, pipes, *pipe_cnt);
1569
1570                         /* Call validate_apply_pipe_split flags after calling DML getters for
1571                          * phantom dlg params, or some of the VBA params indicating pipe split
1572                          * can be overwritten by the getters.
1573                          *
1574                          * When setting up SubVP config, all pipes are merged before attempting to
1575                          * add phantom pipes. If pipe split (ODM / MPC) is required, both the main
1576                          * and phantom pipes will be split in the regular pipe splitting sequence.
1577                          */
1578                         memset(split, 0, MAX_PIPES * sizeof(int));
1579                         memset(merge, 0, MAX_PIPES * sizeof(bool));
1580                         *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
1581                         vba->VoltageLevel = *vlevel;
1582                         // Note: We can't apply the phantom pipes to hardware at this time. We have to wait
1583                         // until driver has acquired the DMCUB lock to do it safely.
1584                         assign_subvp_index(dc, context);
1585                 }
1586         }
1587
1588         if (should_apply_odm_power_optimization(dc, context, vba, split, merge))
1589                 try_odm_power_optimization_and_revalidate(
1590                                 dc, context, pipes, split, merge, vlevel, *pipe_cnt);
1591
1592 }
1593
1594 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
1595 {
1596         int i;
1597
1598         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1599                 if (!context->res_ctx.pipe_ctx[i].stream)
1600                         continue;
1601                 if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))
1602                         return true;
1603         }
1604         return false;
1605 }
1606
1607 static void dcn20_adjust_freesync_v_startup(const struct dc_crtc_timing *dc_crtc_timing, int *vstartup_start)
1608 {
1609         struct dc_crtc_timing patched_crtc_timing;
1610         uint32_t asic_blank_end   = 0;
1611         uint32_t asic_blank_start = 0;
1612         uint32_t newVstartup      = 0;
1613
1614         patched_crtc_timing = *dc_crtc_timing;
1615
1616         if (patched_crtc_timing.flags.INTERLACE == 1) {
1617                 if (patched_crtc_timing.v_front_porch < 2)
1618                         patched_crtc_timing.v_front_porch = 2;
1619         } else {
1620                 if (patched_crtc_timing.v_front_porch < 1)
1621                         patched_crtc_timing.v_front_porch = 1;
1622         }
1623
1624         /* blank_start = frame end - front porch */
1625         asic_blank_start = patched_crtc_timing.v_total -
1626                                         patched_crtc_timing.v_front_porch;
1627
1628         /* blank_end = blank_start - active */
1629         asic_blank_end = asic_blank_start -
1630                                         patched_crtc_timing.v_border_bottom -
1631                                         patched_crtc_timing.v_addressable -
1632                                         patched_crtc_timing.v_border_top;
1633
1634         newVstartup = asic_blank_end + (patched_crtc_timing.v_total - asic_blank_start);
1635
1636         *vstartup_start = ((newVstartup > *vstartup_start) ? newVstartup : *vstartup_start);
1637 }
1638
1639 static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context,
1640                                        display_e2e_pipe_params_st *pipes,
1641                                        int pipe_cnt, int vlevel)
1642 {
1643         int i, pipe_idx, active_hubp_count = 0;
1644         bool usr_retraining_support = false;
1645         bool unbounded_req_enabled = false;
1646         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1647
1648         dc_assert_fp_enabled();
1649
1650         /* Writeback MCIF_WB arbitration parameters */
1651         dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
1652
1653         context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
1654         context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
1655         context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
1656         context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
1657         context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
1658         context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
1659         context->bw_ctx.bw.dcn.clk.p_state_change_support =
1660                         context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
1661                                         != dm_dram_clock_change_unsupported;
1662
1663         /* Pstate change might not be supported by hardware, but it might be
1664          * possible with firmware driven vertical blank stretching.
1665          */
1666         context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching;
1667
1668         context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
1669         context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
1670         context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000;
1671         if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported)
1672                 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false;
1673         else
1674                 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;
1675
1676         usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1677         ASSERT(usr_retraining_support);
1678
1679         if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
1680                 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
1681
1682         unbounded_req_enabled = get_unbounded_request_enabled(&context->bw_ctx.dml, pipes, pipe_cnt);
1683
1684         if (unbounded_req_enabled && pipe_cnt > 1) {
1685                 // Unbounded requesting should not ever be used when more than 1 pipe is enabled.
1686                 ASSERT(false);
1687                 unbounded_req_enabled = false;
1688         }
1689
1690         context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0;
1691         context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0;
1692         context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0;
1693
1694         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1695                 if (!context->res_ctx.pipe_ctx[i].stream)
1696                         continue;
1697                 if (context->res_ctx.pipe_ctx[i].plane_state)
1698                         active_hubp_count++;
1699                 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt,
1700                                 pipe_idx);
1701                 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
1702                                 pipe_idx);
1703                 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt,
1704                                 pipe_idx);
1705                 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
1706                                 pipe_idx);
1707
1708                 if (dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) == SUBVP_PHANTOM) {
1709                         // Phantom pipe requires that DET_SIZE = 0 and no unbounded requests
1710                         context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;
1711                         context->res_ctx.pipe_ctx[i].unbounded_req = false;
1712                 } else {
1713                         context->res_ctx.pipe_ctx[i].det_buffer_size_kb = get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt,
1714                                                         pipe_idx);
1715                         context->res_ctx.pipe_ctx[i].unbounded_req = unbounded_req_enabled;
1716                 }
1717
1718                 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1719                         context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1720                 if (context->res_ctx.pipe_ctx[i].plane_state)
1721                         context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1722                 else
1723                         context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0;
1724                 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
1725
1726                 context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes = get_surface_size_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1727
1728                 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0)
1729                         context->res_ctx.pipe_ctx[i].has_vactive_margin = true;
1730                 else
1731                         context->res_ctx.pipe_ctx[i].has_vactive_margin = false;
1732
1733                 /* MALL Allocation Sizes */
1734                 /* count from active, top pipes per plane only */
1735                 if (context->res_ctx.pipe_ctx[i].stream && context->res_ctx.pipe_ctx[i].plane_state &&
1736                                 (context->res_ctx.pipe_ctx[i].top_pipe == NULL ||
1737                                 context->res_ctx.pipe_ctx[i].plane_state != context->res_ctx.pipe_ctx[i].top_pipe->plane_state) &&
1738                                 context->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1739                         /* SS: all active surfaces stored in MALL */
1740                         if (dc_state_get_pipe_subvp_type(context, &context->res_ctx.pipe_ctx[i]) != SUBVP_PHANTOM) {
1741                                 context->bw_ctx.bw.dcn.mall_ss_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;
1742
1743                                 if (context->res_ctx.pipe_ctx[i].stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED) {
1744                                         /* SS PSR On: all active surfaces part of streams not supporting PSR stored in MALL */
1745                                         context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;
1746                                 }
1747                         } else {
1748                                 /* SUBVP: phantom surfaces only stored in MALL */
1749                                 context->bw_ctx.bw.dcn.mall_subvp_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;
1750                         }
1751                 }
1752
1753                 if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
1754                         dcn20_adjust_freesync_v_startup(
1755                                 &context->res_ctx.pipe_ctx[i].stream->timing,
1756                                 &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);
1757
1758                 pipe_idx++;
1759         }
1760         /* If DCN isn't making memory requests we can allow pstate change and lower clocks */
1761         if (!active_hubp_count) {
1762                 context->bw_ctx.bw.dcn.clk.socclk_khz = 0;
1763                 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
1764                 context->bw_ctx.bw.dcn.clk.dcfclk_khz = 0;
1765                 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = 0;
1766                 context->bw_ctx.bw.dcn.clk.dramclk_khz = 0;
1767                 context->bw_ctx.bw.dcn.clk.fclk_khz = 0;
1768                 context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
1769                 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;
1770         }
1771         /*save a original dppclock copy*/
1772         context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
1773         context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
1774         context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz
1775                         * 1000;
1776         context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz
1777                         * 1000;
1778
1779         context->bw_ctx.bw.dcn.clk.num_ways = dcn32_helper_calculate_num_ways_for_subvp(dc, context);
1780
1781         context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes;
1782
1783         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1784                 if (context->res_ctx.pipe_ctx[i].stream)
1785                         context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[i].det_buffer_size_kb;
1786         }
1787
1788         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1789
1790                 if (!context->res_ctx.pipe_ctx[i].stream)
1791                         continue;
1792
1793                 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml,
1794                                 &context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes,
1795                                 pipe_cnt, pipe_idx);
1796
1797                 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg_v2(&context->res_ctx.pipe_ctx[i].rq_regs,
1798                                 &context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1799                 pipe_idx++;
1800         }
1801 }
1802
1803 static struct pipe_ctx *dcn32_find_split_pipe(
1804                 struct dc *dc,
1805                 struct dc_state *context,
1806                 int old_index)
1807 {
1808         struct pipe_ctx *pipe = NULL;
1809         int i;
1810
1811         if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
1812                 pipe = &context->res_ctx.pipe_ctx[old_index];
1813                 pipe->pipe_idx = old_index;
1814         }
1815
1816         if (!pipe)
1817                 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1818                         if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
1819                                         && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1820                                 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1821                                         pipe = &context->res_ctx.pipe_ctx[i];
1822                                         pipe->pipe_idx = i;
1823                                         break;
1824                                 }
1825                         }
1826                 }
1827
1828         /*
1829          * May need to fix pipes getting tossed from 1 opp to another on flip
1830          * Add for debugging transient underflow during topology updates:
1831          * ASSERT(pipe);
1832          */
1833         if (!pipe)
1834                 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1835                         if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1836                                 pipe = &context->res_ctx.pipe_ctx[i];
1837                                 pipe->pipe_idx = i;
1838                                 break;
1839                         }
1840                 }
1841
1842         return pipe;
1843 }
1844
1845 static bool dcn32_split_stream_for_mpc_or_odm(
1846                 const struct dc *dc,
1847                 struct resource_context *res_ctx,
1848                 struct pipe_ctx *pri_pipe,
1849                 struct pipe_ctx *sec_pipe,
1850                 bool odm)
1851 {
1852         int pipe_idx = sec_pipe->pipe_idx;
1853         const struct resource_pool *pool = dc->res_pool;
1854
1855         DC_LOGGER_INIT(dc->ctx->logger);
1856
1857         if (odm && pri_pipe->plane_state) {
1858                 /* ODM + window MPO, where MPO window is on left half only */
1859                 if (pri_pipe->plane_state->clip_rect.x + pri_pipe->plane_state->clip_rect.width <=
1860                                 pri_pipe->stream->src.x + pri_pipe->stream->src.width/2) {
1861
1862                         DC_LOG_SCALER("%s - ODM + window MPO(left). pri_pipe:%d\n",
1863                                         __func__,
1864                                         pri_pipe->pipe_idx);
1865                         return true;
1866                 }
1867
1868                 /* ODM + window MPO, where MPO window is on right half only */
1869                 if (pri_pipe->plane_state->clip_rect.x >= pri_pipe->stream->src.x +  pri_pipe->stream->src.width/2) {
1870
1871                         DC_LOG_SCALER("%s - ODM + window MPO(right). pri_pipe:%d\n",
1872                                         __func__,
1873                                         pri_pipe->pipe_idx);
1874                         return true;
1875                 }
1876         }
1877
1878         *sec_pipe = *pri_pipe;
1879
1880         sec_pipe->pipe_idx = pipe_idx;
1881         sec_pipe->plane_res.mi = pool->mis[pipe_idx];
1882         sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
1883         sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
1884         sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
1885         sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
1886         sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
1887         sec_pipe->stream_res.dsc = NULL;
1888         if (odm) {
1889                 if (pri_pipe->next_odm_pipe) {
1890                         ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
1891                         sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
1892                         sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
1893                 }
1894                 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
1895                         pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
1896                         sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
1897                 }
1898                 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
1899                         pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
1900                         sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
1901                 }
1902                 pri_pipe->next_odm_pipe = sec_pipe;
1903                 sec_pipe->prev_odm_pipe = pri_pipe;
1904                 ASSERT(sec_pipe->top_pipe == NULL);
1905
1906                 if (!sec_pipe->top_pipe)
1907                         sec_pipe->stream_res.opp = pool->opps[pipe_idx];
1908                 else
1909                         sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
1910                 if (sec_pipe->stream->timing.flags.DSC == 1) {
1911                         dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
1912                         ASSERT(sec_pipe->stream_res.dsc);
1913                         if (sec_pipe->stream_res.dsc == NULL)
1914                                 return false;
1915                 }
1916         } else {
1917                 if (pri_pipe->bottom_pipe) {
1918                         ASSERT(pri_pipe->bottom_pipe != sec_pipe);
1919                         sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
1920                         sec_pipe->bottom_pipe->top_pipe = sec_pipe;
1921                 }
1922                 pri_pipe->bottom_pipe = sec_pipe;
1923                 sec_pipe->top_pipe = pri_pipe;
1924
1925                 ASSERT(pri_pipe->plane_state);
1926         }
1927
1928         return true;
1929 }
1930
1931 bool dcn32_internal_validate_bw(struct dc *dc,
1932                                 struct dc_state *context,
1933                                 display_e2e_pipe_params_st *pipes,
1934                                 int *pipe_cnt_out,
1935                                 int *vlevel_out,
1936                                 bool fast_validate)
1937 {
1938         bool out = false;
1939         bool repopulate_pipes = false;
1940         int split[MAX_PIPES] = { 0 };
1941         bool merge[MAX_PIPES] = { false };
1942         bool newly_split[MAX_PIPES] = { false };
1943         int pipe_cnt, i, pipe_idx;
1944         int vlevel = context->bw_ctx.dml.soc.num_states;
1945         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1946
1947         dc_assert_fp_enabled();
1948
1949         ASSERT(pipes);
1950         if (!pipes)
1951                 return false;
1952
1953         // For each full update, remove all existing phantom pipes first
1954         dc_state_remove_phantom_streams_and_planes(dc, context);
1955         dc_state_release_phantom_streams_and_planes(dc, context);
1956
1957         dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1958
1959         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1960
1961         if (!pipe_cnt) {
1962                 out = true;
1963                 goto validate_out;
1964         }
1965
1966         dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
1967         context->bw_ctx.dml.soc.max_vratio_pre = dcn32_determine_max_vratio_prefetch(dc, context);
1968
1969         if (!fast_validate)
1970                 dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge, &pipe_cnt);
1971
1972         if (fast_validate ||
1973                         (dc->debug.dml_disallow_alternate_prefetch_modes &&
1974                         (vlevel == context->bw_ctx.dml.soc.num_states ||
1975                                 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported))) {
1976                 /*
1977                  * If dml_disallow_alternate_prefetch_modes is false, then we have already
1978                  * tried alternate prefetch modes during full validation.
1979                  *
1980                  * If mode is unsupported or there is no p-state support, then
1981                  * fall back to favouring voltage.
1982                  *
1983                  * If Prefetch mode 0 failed for this config, or passed with Max UCLK, then try
1984                  * to support with Prefetch mode 1 (dm_prefetch_support_fclk_and_stutter == 2)
1985                  */
1986                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1987                         dm_prefetch_support_none;
1988
1989                 context->bw_ctx.dml.validate_max_state = fast_validate;
1990                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1991
1992                 context->bw_ctx.dml.validate_max_state = false;
1993
1994                 if (vlevel < context->bw_ctx.dml.soc.num_states) {
1995                         memset(split, 0, sizeof(split));
1996                         memset(merge, 0, sizeof(merge));
1997                         vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1998                         // dcn20_validate_apply_pipe_split_flags can modify voltage level outside of DML
1999                         vba->VoltageLevel = vlevel;
2000                 }
2001         }
2002
2003         dml_log_mode_support_params(&context->bw_ctx.dml);
2004
2005         if (vlevel == context->bw_ctx.dml.soc.num_states)
2006                 goto validate_fail;
2007
2008         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2009                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2010                 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
2011
2012                 if (!pipe->stream)
2013                         continue;
2014
2015                 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
2016                                 && !dc->config.enable_windowed_mpo_odm
2017                                 && pipe->plane_state && mpo_pipe
2018                                 && memcmp(&mpo_pipe->plane_state->clip_rect,
2019                                                 &pipe->stream->src,
2020                                                 sizeof(struct rect)) != 0) {
2021                         ASSERT(mpo_pipe->plane_state != pipe->plane_state);
2022                         goto validate_fail;
2023                 }
2024                 pipe_idx++;
2025         }
2026
2027         if (dc->config.enable_windowed_mpo_odm) {
2028                 repopulate_pipes = update_pipes_with_split_flags(
2029                                 dc, context, vba, split, merge);
2030         } else {
2031                 /* the code below will be removed once windowed mpo odm is fully
2032                  * enabled.
2033                  */
2034                 /* merge pipes if necessary */
2035                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2036                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2037
2038                         /*skip pipes that don't need merging*/
2039                         if (!merge[i])
2040                                 continue;
2041
2042                         /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
2043                         if (pipe->prev_odm_pipe) {
2044                                 /*split off odm pipe*/
2045                                 pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
2046                                 if (pipe->next_odm_pipe)
2047                                         pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
2048
2049                                 /*2:1ODM+MPC Split MPO to Single Pipe + MPC Split MPO*/
2050                                 if (pipe->bottom_pipe) {
2051                                         if (pipe->bottom_pipe->prev_odm_pipe || pipe->bottom_pipe->next_odm_pipe) {
2052                                                 /*MPC split rules will handle this case*/
2053                                                 pipe->bottom_pipe->top_pipe = NULL;
2054                                         } else {
2055                                                 /* when merging an ODM pipes, the bottom MPC pipe must now point to
2056                                                  * the previous ODM pipe and its associated stream assets
2057                                                  */
2058                                                 if (pipe->prev_odm_pipe->bottom_pipe) {
2059                                                         /* 3 plane MPO*/
2060                                                         pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe->bottom_pipe;
2061                                                         pipe->prev_odm_pipe->bottom_pipe->bottom_pipe = pipe->bottom_pipe;
2062                                                 } else {
2063                                                         /* 2 plane MPO*/
2064                                                         pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe;
2065                                                         pipe->prev_odm_pipe->bottom_pipe = pipe->bottom_pipe;
2066                                                 }
2067
2068                                                 memcpy(&pipe->bottom_pipe->stream_res, &pipe->bottom_pipe->top_pipe->stream_res, sizeof(struct stream_resource));
2069                                         }
2070                                 }
2071
2072                                 if (pipe->top_pipe) {
2073                                         pipe->top_pipe->bottom_pipe = NULL;
2074                                 }
2075
2076                                 pipe->bottom_pipe = NULL;
2077                                 pipe->next_odm_pipe = NULL;
2078                                 pipe->plane_state = NULL;
2079                                 pipe->stream = NULL;
2080                                 pipe->top_pipe = NULL;
2081                                 pipe->prev_odm_pipe = NULL;
2082                                 if (pipe->stream_res.dsc)
2083                                         dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
2084                                 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
2085                                 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
2086                                 memset(&pipe->link_res, 0, sizeof(pipe->link_res));
2087                                 repopulate_pipes = true;
2088                         } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
2089                                 struct pipe_ctx *top_pipe = pipe->top_pipe;
2090                                 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
2091
2092                                 top_pipe->bottom_pipe = bottom_pipe;
2093                                 if (bottom_pipe)
2094                                         bottom_pipe->top_pipe = top_pipe;
2095
2096                                 pipe->top_pipe = NULL;
2097                                 pipe->bottom_pipe = NULL;
2098                                 pipe->plane_state = NULL;
2099                                 pipe->stream = NULL;
2100                                 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
2101                                 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
2102                                 memset(&pipe->link_res, 0, sizeof(pipe->link_res));
2103                                 repopulate_pipes = true;
2104                         } else
2105                                 ASSERT(0); /* Should never try to merge master pipe */
2106
2107                 }
2108
2109                 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2110                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2111                         struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2112                         struct pipe_ctx *hsplit_pipe = NULL;
2113                         bool odm;
2114                         int old_index = -1;
2115
2116                         if (!pipe->stream || newly_split[i])
2117                                 continue;
2118
2119                         pipe_idx++;
2120                         odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
2121
2122                         if (!pipe->plane_state && !odm)
2123                                 continue;
2124
2125                         if (split[i]) {
2126                                 if (odm) {
2127                                         if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
2128                                                 old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
2129                                         else if (old_pipe->next_odm_pipe)
2130                                                 old_index = old_pipe->next_odm_pipe->pipe_idx;
2131                                 } else {
2132                                         if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
2133                                                         old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2134                                                 old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2135                                         else if (old_pipe->bottom_pipe &&
2136                                                         old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2137                                                 old_index = old_pipe->bottom_pipe->pipe_idx;
2138                                 }
2139                                 hsplit_pipe = dcn32_find_split_pipe(dc, context, old_index);
2140                                 ASSERT(hsplit_pipe);
2141                                 if (!hsplit_pipe)
2142                                         goto validate_fail;
2143
2144                                 if (!dcn32_split_stream_for_mpc_or_odm(
2145                                                 dc, &context->res_ctx,
2146                                                 pipe, hsplit_pipe, odm))
2147                                         goto validate_fail;
2148
2149                                 newly_split[hsplit_pipe->pipe_idx] = true;
2150                                 repopulate_pipes = true;
2151                         }
2152                         if (split[i] == 4) {
2153                                 struct pipe_ctx *pipe_4to1;
2154
2155                                 if (odm && old_pipe->next_odm_pipe)
2156                                         old_index = old_pipe->next_odm_pipe->pipe_idx;
2157                                 else if (!odm && old_pipe->bottom_pipe &&
2158                                                         old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2159                                         old_index = old_pipe->bottom_pipe->pipe_idx;
2160                                 else
2161                                         old_index = -1;
2162                                 pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
2163                                 ASSERT(pipe_4to1);
2164                                 if (!pipe_4to1)
2165                                         goto validate_fail;
2166                                 if (!dcn32_split_stream_for_mpc_or_odm(
2167                                                 dc, &context->res_ctx,
2168                                                 pipe, pipe_4to1, odm))
2169                                         goto validate_fail;
2170                                 newly_split[pipe_4to1->pipe_idx] = true;
2171
2172                                 if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
2173                                                 && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
2174                                         old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
2175                                 else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
2176                                                 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
2177                                                 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2178                                         old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2179                                 else
2180                                         old_index = -1;
2181                                 pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
2182                                 ASSERT(pipe_4to1);
2183                                 if (!pipe_4to1)
2184                                         goto validate_fail;
2185                                 if (!dcn32_split_stream_for_mpc_or_odm(
2186                                                 dc, &context->res_ctx,
2187                                                 hsplit_pipe, pipe_4to1, odm))
2188                                         goto validate_fail;
2189                                 newly_split[pipe_4to1->pipe_idx] = true;
2190                         }
2191                         if (odm)
2192                                 dcn20_build_mapped_resource(dc, context, pipe->stream);
2193                 }
2194
2195                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2196                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2197
2198                         if (pipe->plane_state) {
2199                                 if (!resource_build_scaling_params(pipe))
2200                                         goto validate_fail;
2201                         }
2202                 }
2203         }
2204
2205         /* Actual dsc count per stream dsc validation*/
2206         if (!dcn20_validate_dsc(dc, context)) {
2207                 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
2208                 goto validate_fail;
2209         }
2210
2211         if (repopulate_pipes) {
2212                 int flag_max_mpc_comb = vba->maxMpcComb;
2213                 int flag_vlevel = vlevel;
2214                 int i;
2215
2216                 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2217                 if (!dc->config.enable_windowed_mpo_odm)
2218                         dcn32_update_dml_pipes_odm_policy_based_on_context(dc, context, pipes);
2219
2220                 /* repopulate_pipes = 1 means the pipes were either split or merged. In this case
2221                  * we have to re-calculate the DET allocation and run through DML once more to
2222                  * ensure all the params are calculated correctly. We do not need to run the
2223                  * pipe split check again after this call (pipes are already split / merged).
2224                  * */
2225                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
2226                                         dm_prefetch_support_uclk_fclk_and_stutter_if_possible;
2227
2228                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2229
2230                 if (vlevel == context->bw_ctx.dml.soc.num_states) {
2231                         /* failed after DET size changes */
2232                         goto validate_fail;
2233                 } else if (flag_max_mpc_comb == 0 &&
2234                                 flag_max_mpc_comb != context->bw_ctx.dml.vba.maxMpcComb) {
2235                         /* check the context constructed with pipe split flags is still valid*/
2236                         bool flags_valid = false;
2237                         for (i = flag_vlevel; i < context->bw_ctx.dml.soc.num_states; i++) {
2238                                 if (vba->ModeSupport[i][flag_max_mpc_comb]) {
2239                                         vba->maxMpcComb = flag_max_mpc_comb;
2240                                         vba->VoltageLevel = i;
2241                                         vlevel = i;
2242                                         flags_valid = true;
2243                                         break;
2244                                 }
2245                         }
2246
2247                         /* this should never happen */
2248                         if (!flags_valid)
2249                                 goto validate_fail;
2250                 }
2251         }
2252         *vlevel_out = vlevel;
2253         *pipe_cnt_out = pipe_cnt;
2254
2255         out = true;
2256         goto validate_out;
2257
2258 validate_fail:
2259         out = false;
2260
2261 validate_out:
2262         return out;
2263 }
2264
2265
2266 void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,
2267                                 display_e2e_pipe_params_st *pipes,
2268                                 int pipe_cnt,
2269                                 int vlevel)
2270 {
2271         int i, pipe_idx, vlevel_temp = 0;
2272         double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
2273         double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2274         double dram_speed_from_validation = context->bw_ctx.dml.vba.DRAMSpeed;
2275         double dcfclk_from_fw_based_mclk_switching = dcfclk_from_validation;
2276         bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=
2277                         dm_dram_clock_change_unsupported;
2278         unsigned int dummy_latency_index = 0;
2279         int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
2280         unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
2281         bool subvp_in_use = dcn32_subvp_in_use(dc, context);
2282         unsigned int min_dram_speed_mts_margin;
2283         bool need_fclk_lat_as_dummy = false;
2284         bool is_subvp_p_drr = false;
2285         struct dc_stream_state *fpo_candidate_stream = NULL;
2286
2287         dc_assert_fp_enabled();
2288
2289         /* need to find dummy latency index for subvp */
2290         if (subvp_in_use) {
2291                 /* Override DRAMClockChangeSupport for SubVP + DRR case where the DRR cannot switch without stretching it's VBLANK */
2292                 if (!pstate_en) {
2293                         context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp;
2294                         context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = dm_prefetch_support_fclk_and_stutter;
2295                         pstate_en = true;
2296                         is_subvp_p_drr = true;
2297                 }
2298                 dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc,
2299                                                 context, pipes, pipe_cnt, vlevel);
2300
2301                 /* For DCN32/321 need to validate with fclk pstate change latency equal to dummy so prefetch is
2302                  * scheduled correctly to account for dummy pstate.
2303                  */
2304                 if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) {
2305                         need_fclk_lat_as_dummy = true;
2306                         context->bw_ctx.dml.soc.fclk_change_latency_us =
2307                                         dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
2308                 }
2309                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2310                                                         dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2311                 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
2312                 maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
2313                 if (is_subvp_p_drr) {
2314                         context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp;
2315                 }
2316         }
2317
2318         context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;
2319         for (i = 0; i < context->stream_count; i++) {
2320                 if (context->streams[i])
2321                         context->streams[i]->fpo_in_use = false;
2322         }
2323
2324         if (!pstate_en || (!dc->debug.disable_fpo_optimizations &&
2325                         pstate_en && vlevel != 0)) {
2326                 /* only when the mclk switch can not be natural, is the fw based vblank stretch attempted */
2327                 fpo_candidate_stream = dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context);
2328                 if (fpo_candidate_stream) {
2329                         fpo_candidate_stream->fpo_in_use = true;
2330                         context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = true;
2331                 }
2332
2333                 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
2334                         dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc,
2335                                 context, pipes, pipe_cnt, vlevel);
2336
2337                         /* After calling dcn30_find_dummy_latency_index_for_fw_based_mclk_switch
2338                          * we reinstate the original dram_clock_change_latency_us on the context
2339                          * and all variables that may have changed up to this point, except the
2340                          * newly found dummy_latency_index
2341                          */
2342                         context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2343                                         dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2344                         /* For DCN32/321 need to validate with fclk pstate change latency equal to dummy so
2345                          * prefetch is scheduled correctly to account for dummy pstate.
2346                          */
2347                         if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) {
2348                                 need_fclk_lat_as_dummy = true;
2349                                 context->bw_ctx.dml.soc.fclk_change_latency_us =
2350                                                 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
2351                         }
2352                         dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel_temp, false);
2353                         if (vlevel_temp < vlevel) {
2354                                 vlevel = vlevel_temp;
2355                                 maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
2356                                 dcfclk_from_fw_based_mclk_switching = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2357                                 pstate_en = true;
2358                                 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank;
2359                         } else {
2360                                 /* Restore FCLK latency and re-run validation to go back to original validation
2361                                  * output if we find that enabling FPO does not give us any benefit (i.e. lower
2362                                  * voltage level)
2363                                  */
2364                                 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;
2365                                 for (i = 0; i < context->stream_count; i++) {
2366                                         if (context->streams[i])
2367                                                 context->streams[i]->fpo_in_use = false;
2368                                 }
2369                                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;
2370                                 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
2371                         }
2372                 }
2373         }
2374
2375         /* Set B:
2376          * For Set B calculations use clocks from clock_limits[2] when available i.e. when SMU is present,
2377          * otherwise use arbitrary low value from spreadsheet for DCFCLK as lower is safer for watermark
2378          * calculations to cover bootup clocks.
2379          * DCFCLK: soc.clock_limits[2] when available
2380          * UCLK: soc.clock_limits[2] when available
2381          */
2382         if (dcn3_2_soc.num_states > 2) {
2383                 vlevel_temp = 2;
2384                 dcfclk = dcn3_2_soc.clock_limits[2].dcfclk_mhz;
2385         } else
2386                 dcfclk = 615; //DCFCLK Vmin_lv
2387
2388         pipes[0].clks_cfg.voltage = vlevel_temp;
2389         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2390         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;
2391
2392         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
2393                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
2394                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us;
2395                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
2396                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
2397         }
2398         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2399         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2400         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2401         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2402         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2403         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2404         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2405         context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2406         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2407         context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2408
2409         /* Set D:
2410          * All clocks min.
2411          * DCFCLK: Min, as reported by PM FW when available
2412          * UCLK  : Min, as reported by PM FW when available
2413          * sr_enter_exit/sr_exit should be lower than used for DRAM (TBD after bringup or later, use as decided in Clk Mgr)
2414          */
2415
2416         /*
2417         if (dcn3_2_soc.num_states > 2) {
2418                 vlevel_temp = 0;
2419                 dcfclk = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
2420         } else
2421                 dcfclk = 615; //DCFCLK Vmin_lv
2422
2423         pipes[0].clks_cfg.voltage = vlevel_temp;
2424         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2425         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;
2426
2427         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
2428                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
2429                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us;
2430                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
2431                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
2432         }
2433         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2434         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2435         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2436         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2437         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2438         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2439         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2440         context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2441         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2442         context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2443         */
2444
2445         /* Set C, for Dummy P-State:
2446          * All clocks min.
2447          * DCFCLK: Min, as reported by PM FW, when available
2448          * UCLK  : Min,  as reported by PM FW, when available
2449          * pstate latency as per UCLK state dummy pstate latency
2450          */
2451
2452         // For Set A and Set C use values from validation
2453         pipes[0].clks_cfg.voltage = vlevel;
2454         pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_validation;
2455         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2456
2457         if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
2458                 pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_fw_based_mclk_switching;
2459         }
2460
2461         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
2462                 min_dram_speed_mts = dram_speed_from_validation;
2463                 min_dram_speed_mts_margin = 160;
2464
2465                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2466                         dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us;
2467
2468                 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] ==
2469                         dm_dram_clock_change_unsupported) {
2470                         int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1;
2471
2472                         min_dram_speed_mts =
2473                                 dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16;
2474                 }
2475
2476                 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !subvp_in_use) {
2477                         /* find largest table entry that is lower than dram speed,
2478                          * but lower than DPM0 still uses DPM0
2479                          */
2480                         for (dummy_latency_index = 3; dummy_latency_index > 0; dummy_latency_index--)
2481                                 if (min_dram_speed_mts + min_dram_speed_mts_margin >
2482                                         dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts)
2483                                         break;
2484                 }
2485
2486                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2487                         dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
2488
2489                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us;
2490                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
2491                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
2492         }
2493
2494         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2495         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2496         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2497         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2498         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2499         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2500         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2501         context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2502         /* On DCN32/321, PMFW will set PSTATE_CHANGE_TYPE = 1 (FCLK) for UCLK dummy p-state.
2503          * In this case we must program FCLK WM Set C to use the UCLK dummy p-state WM
2504          * value.
2505          */
2506         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2507         context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2508
2509         if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) {
2510                 /* The only difference between A and C is p-state latency, if p-state is not supported
2511                  * with full p-state latency we want to calculate DLG based on dummy p-state latency,
2512                  * Set A p-state watermark set to 0 on DCN30, when p-state unsupported, for now keep as DCN30.
2513                  */
2514                 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;
2515                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;
2516                 /* Calculate FCLK p-state change watermark based on FCLK pstate change latency in case
2517                  * UCLK p-state is not supported, to avoid underflow in case FCLK pstate is supported
2518                  */
2519                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2520         } else {
2521                 /* Set A:
2522                  * All clocks min.
2523                  * DCFCLK: Min, as reported by PM FW, when available
2524                  * UCLK: Min, as reported by PM FW, when available
2525                  */
2526
2527                 /* For set A set the correct latency values (i.e. non-dummy values) unconditionally
2528                  */
2529                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2530                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
2531                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
2532
2533                 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2534                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2535                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2536                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2537                 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2538                 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2539                 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2540                 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2541                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2542                 context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2543         }
2544
2545         /* Make set D = set A since we do not optimized watermarks for MALL */
2546         context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
2547
2548         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2549                 if (!context->res_ctx.pipe_ctx[i].stream)
2550                         continue;
2551
2552                 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
2553                 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
2554
2555                 if (dc->config.forced_clocks) {
2556                         pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2557                         pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2558                 }
2559                 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
2560                         pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2561                 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2562                         pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2563
2564                 pipe_idx++;
2565         }
2566
2567         context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod;
2568
2569         /* for proper prefetch calculations, if dummy lat > fclk lat, use fclk lat = dummy lat */
2570         if (need_fclk_lat_as_dummy)
2571                 context->bw_ctx.dml.soc.fclk_change_latency_us =
2572                                 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
2573
2574         dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2575
2576         if (!pstate_en)
2577                 /* Restore full p-state latency */
2578                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2579                                 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2580
2581         /* revert fclk lat changes if required */
2582         if (need_fclk_lat_as_dummy)
2583                 context->bw_ctx.dml.soc.fclk_change_latency_us =
2584                                 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;
2585 }
2586
2587 static void dcn32_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
2588                 unsigned int *optimal_dcfclk,
2589                 unsigned int *optimal_fclk)
2590 {
2591         double bw_from_dram, bw_from_dram1, bw_from_dram2;
2592
2593         bw_from_dram1 = uclk_mts * dcn3_2_soc.num_chans *
2594                 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_dram_bw_use_normal_percent / 100);
2595         bw_from_dram2 = uclk_mts * dcn3_2_soc.num_chans *
2596                 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100);
2597
2598         bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
2599
2600         if (optimal_fclk)
2601                 *optimal_fclk = bw_from_dram /
2602                 (dcn3_2_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100));
2603
2604         if (optimal_dcfclk)
2605                 *optimal_dcfclk =  bw_from_dram /
2606                 (dcn3_2_soc.return_bus_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100));
2607 }
2608
2609 static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries,
2610                 unsigned int index)
2611 {
2612         int i;
2613
2614         if (*num_entries == 0)
2615                 return;
2616
2617         for (i = index; i < *num_entries - 1; i++) {
2618                 table[i] = table[i + 1];
2619         }
2620         memset(&table[--(*num_entries)], 0, sizeof(struct _vcs_dpi_voltage_scaling_st));
2621 }
2622
2623 void dcn32_patch_dpm_table(struct clk_bw_params *bw_params)
2624 {
2625         int i;
2626         unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0,
2627                         max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0;
2628
2629         for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2630                 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
2631                         max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2632                 if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz)
2633                         max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
2634                 if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz)
2635                         max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz;
2636                 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
2637                         max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2638                 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
2639                         max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2640                 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
2641                         max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2642                 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz)
2643                         max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
2644         }
2645
2646         /* Scan through clock values we currently have and if they are 0,
2647          *  then populate it with dcn3_2_soc.clock_limits[] value.
2648          *
2649          * Do it for DCFCLK, DISPCLK, DTBCLK and UCLK as any of those being
2650          *  0, will cause it to skip building the clock table.
2651          */
2652         if (max_dcfclk_mhz == 0)
2653                 bw_params->clk_table.entries[0].dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
2654         if (max_dispclk_mhz == 0)
2655                 bw_params->clk_table.entries[0].dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz;
2656         if (max_dtbclk_mhz == 0)
2657                 bw_params->clk_table.entries[0].dtbclk_mhz = dcn3_2_soc.clock_limits[0].dtbclk_mhz;
2658         if (max_uclk_mhz == 0)
2659                 bw_params->clk_table.entries[0].memclk_mhz = dcn3_2_soc.clock_limits[0].dram_speed_mts / 16;
2660 }
2661
2662 static void swap_table_entries(struct _vcs_dpi_voltage_scaling_st *first_entry,
2663                 struct _vcs_dpi_voltage_scaling_st *second_entry)
2664 {
2665         struct _vcs_dpi_voltage_scaling_st temp_entry = *first_entry;
2666         *first_entry = *second_entry;
2667         *second_entry = temp_entry;
2668 }
2669
2670 /*
2671  * sort_entries_with_same_bw - Sort entries sharing the same bandwidth by DCFCLK
2672  */
2673 static void sort_entries_with_same_bw(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
2674 {
2675         unsigned int start_index = 0;
2676         unsigned int end_index = 0;
2677         unsigned int current_bw = 0;
2678
2679         for (int i = 0; i < (*num_entries - 1); i++) {
2680                 if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) {
2681                         current_bw = table[i].net_bw_in_kbytes_sec;
2682                         start_index = i;
2683                         end_index = ++i;
2684
2685                         while ((i < (*num_entries - 1)) && (table[i+1].net_bw_in_kbytes_sec == current_bw))
2686                                 end_index = ++i;
2687                 }
2688
2689                 if (start_index != end_index) {
2690                         for (int j = start_index; j < end_index; j++) {
2691                                 for (int k = start_index; k < end_index; k++) {
2692                                         if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz)
2693                                                 swap_table_entries(&table[k], &table[k+1]);
2694                                 }
2695                         }
2696                 }
2697
2698                 start_index = 0;
2699                 end_index = 0;
2700
2701         }
2702 }
2703
2704 /*
2705  * remove_inconsistent_entries - Ensure entries with the same bandwidth have MEMCLK and FCLK monotonically increasing
2706  *                               and remove entries that do not
2707  */
2708 static void remove_inconsistent_entries(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
2709 {
2710         for (int i = 0; i < (*num_entries - 1); i++) {
2711                 if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) {
2712                         if ((table[i].dram_speed_mts > table[i+1].dram_speed_mts) ||
2713                                 (table[i].fabricclk_mhz > table[i+1].fabricclk_mhz))
2714                                 remove_entry_from_table_at_index(table, num_entries, i);
2715                 }
2716         }
2717 }
2718
2719 /*
2720  * override_max_clk_values - Overwrite the max clock frequencies with the max DC mode timings
2721  * Input:
2722  *      max_clk_limit - struct containing the desired clock timings
2723  * Output:
2724  *      curr_clk_limit  - struct containing the timings that need to be overwritten
2725  * Return: 0 upon success, non-zero for failure
2726  */
2727 static int override_max_clk_values(struct clk_limit_table_entry *max_clk_limit,
2728                 struct clk_limit_table_entry *curr_clk_limit)
2729 {
2730         if (NULL == max_clk_limit || NULL == curr_clk_limit)
2731                 return -1; //invalid parameters
2732
2733         //only overwrite if desired max clock frequency is initialized
2734         if (max_clk_limit->dcfclk_mhz != 0)
2735                 curr_clk_limit->dcfclk_mhz = max_clk_limit->dcfclk_mhz;
2736
2737         if (max_clk_limit->fclk_mhz != 0)
2738                 curr_clk_limit->fclk_mhz = max_clk_limit->fclk_mhz;
2739
2740         if (max_clk_limit->memclk_mhz != 0)
2741                 curr_clk_limit->memclk_mhz = max_clk_limit->memclk_mhz;
2742
2743         if (max_clk_limit->socclk_mhz != 0)
2744                 curr_clk_limit->socclk_mhz = max_clk_limit->socclk_mhz;
2745
2746         if (max_clk_limit->dtbclk_mhz != 0)
2747                 curr_clk_limit->dtbclk_mhz = max_clk_limit->dtbclk_mhz;
2748
2749         if (max_clk_limit->dispclk_mhz != 0)
2750                 curr_clk_limit->dispclk_mhz = max_clk_limit->dispclk_mhz;
2751
2752         return 0;
2753 }
2754
2755 static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params,
2756                 struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
2757 {
2758         int i, j;
2759         struct _vcs_dpi_voltage_scaling_st entry = {0};
2760         struct clk_limit_table_entry max_clk_data = {0};
2761
2762         unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299;
2763
2764         static const unsigned int num_dcfclk_stas = 5;
2765         unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};
2766
2767         unsigned int num_uclk_dpms = 0;
2768         unsigned int num_fclk_dpms = 0;
2769         unsigned int num_dcfclk_dpms = 0;
2770
2771         unsigned int num_dc_uclk_dpms = 0;
2772         unsigned int num_dc_fclk_dpms = 0;
2773         unsigned int num_dc_dcfclk_dpms = 0;
2774
2775         for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2776                 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_clk_data.dcfclk_mhz)
2777                         max_clk_data.dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2778                 if (bw_params->clk_table.entries[i].fclk_mhz > max_clk_data.fclk_mhz)
2779                         max_clk_data.fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
2780                 if (bw_params->clk_table.entries[i].memclk_mhz > max_clk_data.memclk_mhz)
2781                         max_clk_data.memclk_mhz = bw_params->clk_table.entries[i].memclk_mhz;
2782                 if (bw_params->clk_table.entries[i].dispclk_mhz > max_clk_data.dispclk_mhz)
2783                         max_clk_data.dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2784                 if (bw_params->clk_table.entries[i].dppclk_mhz > max_clk_data.dppclk_mhz)
2785                         max_clk_data.dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2786                 if (bw_params->clk_table.entries[i].phyclk_mhz > max_clk_data.phyclk_mhz)
2787                         max_clk_data.phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2788                 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_clk_data.dtbclk_mhz)
2789                         max_clk_data.dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
2790
2791                 if (bw_params->clk_table.entries[i].memclk_mhz > 0) {
2792                         num_uclk_dpms++;
2793                         if (bw_params->clk_table.entries[i].memclk_mhz <= bw_params->dc_mode_limit.memclk_mhz)
2794                                 num_dc_uclk_dpms++;
2795                 }
2796                 if (bw_params->clk_table.entries[i].fclk_mhz > 0) {
2797                         num_fclk_dpms++;
2798                         if (bw_params->clk_table.entries[i].fclk_mhz <= bw_params->dc_mode_limit.fclk_mhz)
2799                                 num_dc_fclk_dpms++;
2800                 }
2801                 if (bw_params->clk_table.entries[i].dcfclk_mhz > 0) {
2802                         num_dcfclk_dpms++;
2803                         if (bw_params->clk_table.entries[i].dcfclk_mhz <= bw_params->dc_mode_limit.dcfclk_mhz)
2804                                 num_dc_dcfclk_dpms++;
2805                 }
2806         }
2807
2808         if (!disable_dc_mode_overwrite) {
2809                 //Overwrite max frequencies with max DC mode frequencies for DC mode systems
2810                 override_max_clk_values(&bw_params->dc_mode_limit, &max_clk_data);
2811                 num_uclk_dpms = num_dc_uclk_dpms;
2812                 num_fclk_dpms = num_dc_fclk_dpms;
2813                 num_dcfclk_dpms = num_dc_dcfclk_dpms;
2814                 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = num_uclk_dpms;
2815                 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = num_fclk_dpms;
2816         }
2817
2818         if (num_dcfclk_dpms > 0 && bw_params->clk_table.entries[0].fclk_mhz > min_fclk_mhz)
2819                 min_fclk_mhz = bw_params->clk_table.entries[0].fclk_mhz;
2820
2821         if (!max_clk_data.dcfclk_mhz || !max_clk_data.dispclk_mhz || !max_clk_data.dtbclk_mhz)
2822                 return -1;
2823
2824         if (max_clk_data.dppclk_mhz == 0)
2825                 max_clk_data.dppclk_mhz = max_clk_data.dispclk_mhz;
2826
2827         if (max_clk_data.fclk_mhz == 0)
2828                 max_clk_data.fclk_mhz = max_clk_data.dcfclk_mhz *
2829                                 dcn3_2_soc.pct_ideal_sdp_bw_after_urgent /
2830                                 dcn3_2_soc.pct_ideal_fabric_bw_after_urgent;
2831
2832         if (max_clk_data.phyclk_mhz == 0)
2833                 max_clk_data.phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz;
2834
2835         *num_entries = 0;
2836         entry.dispclk_mhz = max_clk_data.dispclk_mhz;
2837         entry.dscclk_mhz = max_clk_data.dispclk_mhz / 3;
2838         entry.dppclk_mhz = max_clk_data.dppclk_mhz;
2839         entry.dtbclk_mhz = max_clk_data.dtbclk_mhz;
2840         entry.phyclk_mhz = max_clk_data.phyclk_mhz;
2841         entry.phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;
2842         entry.phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;
2843
2844         // Insert all the DCFCLK STAs
2845         for (i = 0; i < num_dcfclk_stas; i++) {
2846                 entry.dcfclk_mhz = dcfclk_sta_targets[i];
2847                 entry.fabricclk_mhz = 0;
2848                 entry.dram_speed_mts = 0;
2849
2850                 get_optimal_ntuple(&entry);
2851                 entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
2852                 insert_entry_into_table_sorted(table, num_entries, &entry);
2853         }
2854
2855         // Insert the max DCFCLK
2856         entry.dcfclk_mhz = max_clk_data.dcfclk_mhz;
2857         entry.fabricclk_mhz = 0;
2858         entry.dram_speed_mts = 0;
2859
2860         get_optimal_ntuple(&entry);
2861         entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
2862         insert_entry_into_table_sorted(table, num_entries, &entry);
2863
2864         // Insert the UCLK DPMS
2865         for (i = 0; i < num_uclk_dpms; i++) {
2866                 entry.dcfclk_mhz = 0;
2867                 entry.fabricclk_mhz = 0;
2868                 entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;
2869
2870                 get_optimal_ntuple(&entry);
2871                 entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
2872                 insert_entry_into_table_sorted(table, num_entries, &entry);
2873         }
2874
2875         // If FCLK is coarse grained, insert individual DPMs.
2876         if (num_fclk_dpms > 2) {
2877                 for (i = 0; i < num_fclk_dpms; i++) {
2878                         entry.dcfclk_mhz = 0;
2879                         entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
2880                         entry.dram_speed_mts = 0;
2881
2882                         get_optimal_ntuple(&entry);
2883                         entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
2884                         insert_entry_into_table_sorted(table, num_entries, &entry);
2885                 }
2886         }
2887         // If FCLK fine grained, only insert max
2888         else {
2889                 entry.dcfclk_mhz = 0;
2890                 entry.fabricclk_mhz = max_clk_data.fclk_mhz;
2891                 entry.dram_speed_mts = 0;
2892
2893                 get_optimal_ntuple(&entry);
2894                 entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
2895                 insert_entry_into_table_sorted(table, num_entries, &entry);
2896         }
2897
2898         // At this point, the table contains all "points of interest" based on
2899         // DPMs from PMFW, and STAs.  Table is sorted by BW, and all clock
2900         // ratios (by derate, are exact).
2901
2902         // Remove states that require higher clocks than are supported
2903         for (i = *num_entries - 1; i >= 0 ; i--) {
2904                 if (table[i].dcfclk_mhz > max_clk_data.dcfclk_mhz ||
2905                                 table[i].fabricclk_mhz > max_clk_data.fclk_mhz ||
2906                                 table[i].dram_speed_mts > max_clk_data.memclk_mhz * 16)
2907                         remove_entry_from_table_at_index(table, num_entries, i);
2908         }
2909
2910         // Insert entry with all max dc limits without bandwidth matching
2911         if (!disable_dc_mode_overwrite) {
2912                 struct _vcs_dpi_voltage_scaling_st max_dc_limits_entry = entry;
2913
2914                 max_dc_limits_entry.dcfclk_mhz = max_clk_data.dcfclk_mhz;
2915                 max_dc_limits_entry.fabricclk_mhz = max_clk_data.fclk_mhz;
2916                 max_dc_limits_entry.dram_speed_mts = max_clk_data.memclk_mhz * 16;
2917
2918                 max_dc_limits_entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&max_dc_limits_entry);
2919                 insert_entry_into_table_sorted(table, num_entries, &max_dc_limits_entry);
2920
2921                 sort_entries_with_same_bw(table, num_entries);
2922                 remove_inconsistent_entries(table, num_entries);
2923         }
2924
2925         // At this point, the table only contains supported points of interest
2926         // it could be used as is, but some states may be redundant due to
2927         // coarse grained nature of some clocks, so we want to round up to
2928         // coarse grained DPMs and remove duplicates.
2929
2930         // Round up UCLKs
2931         for (i = *num_entries - 1; i >= 0 ; i--) {
2932                 for (j = 0; j < num_uclk_dpms; j++) {
2933                         if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) {
2934                                 table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16;
2935                                 break;
2936                         }
2937                 }
2938         }
2939
2940         // If FCLK is coarse grained, round up to next DPMs
2941         if (num_fclk_dpms > 2) {
2942                 for (i = *num_entries - 1; i >= 0 ; i--) {
2943                         for (j = 0; j < num_fclk_dpms; j++) {
2944                                 if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) {
2945                                         table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz;
2946                                         break;
2947                                 }
2948                         }
2949                 }
2950         }
2951         // Otherwise, round up to minimum.
2952         else {
2953                 for (i = *num_entries - 1; i >= 0 ; i--) {
2954                         if (table[i].fabricclk_mhz < min_fclk_mhz) {
2955                                 table[i].fabricclk_mhz = min_fclk_mhz;
2956                         }
2957                 }
2958         }
2959
2960         // Round DCFCLKs up to minimum
2961         for (i = *num_entries - 1; i >= 0 ; i--) {
2962                 if (table[i].dcfclk_mhz < min_dcfclk_mhz) {
2963                         table[i].dcfclk_mhz = min_dcfclk_mhz;
2964                 }
2965         }
2966
2967         // Remove duplicate states, note duplicate states are always neighbouring since table is sorted.
2968         i = 0;
2969         while (i < *num_entries - 1) {
2970                 if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz &&
2971                                 table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz &&
2972                                 table[i].dram_speed_mts == table[i + 1].dram_speed_mts)
2973                         remove_entry_from_table_at_index(table, num_entries, i + 1);
2974                 else
2975                         i++;
2976         }
2977
2978         // Fix up the state indicies
2979         for (i = *num_entries - 1; i >= 0 ; i--) {
2980                 table[i].state = i;
2981         }
2982
2983         return 0;
2984 }
2985
2986 /*
2987  * dcn32_update_bw_bounding_box
2988  *
2989  * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from
2990  * spreadsheet with actual values as per dGPU SKU:
2991  * - with passed few options from dc->config
2992  * - with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might
2993  *   need to get it from PM FW)
2994  * - with passed latency values (passed in ns units) in dc-> bb override for
2995  *   debugging purposes
2996  * - with passed latencies from VBIOS (in 100_ns units) if available for
2997  *   certain dGPU SKU
2998  * - with number of DRAM channels from VBIOS (which differ for certain dGPU SKU
2999  *   of the same ASIC)
3000  * - clocks levels with passed clk_table entries from Clk Mgr as reported by PM
3001  *   FW for different clocks (which might differ for certain dGPU SKU of the
3002  *   same ASIC)
3003  */
3004 void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)
3005 {
3006         dc_assert_fp_enabled();
3007
3008         /* Overrides from dc->config options */
3009         dcn3_2_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
3010
3011         /* Override from passed dc->bb_overrides if available*/
3012         if ((int)(dcn3_2_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
3013                         && dc->bb_overrides.sr_exit_time_ns) {
3014                 dc->dml2_options.bbox_overrides.sr_exit_latency_us =
3015                 dcn3_2_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
3016         }
3017
3018         if ((int)(dcn3_2_soc.sr_enter_plus_exit_time_us * 1000)
3019                         != dc->bb_overrides.sr_enter_plus_exit_time_ns
3020                         && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
3021                 dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us =
3022                 dcn3_2_soc.sr_enter_plus_exit_time_us =
3023                         dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
3024         }
3025
3026         if ((int)(dcn3_2_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
3027                 && dc->bb_overrides.urgent_latency_ns) {
3028                 dcn3_2_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
3029                 dc->dml2_options.bbox_overrides.urgent_latency_us =
3030                 dcn3_2_soc.urgent_latency_pixel_data_only_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
3031         }
3032
3033         if ((int)(dcn3_2_soc.dram_clock_change_latency_us * 1000)
3034                         != dc->bb_overrides.dram_clock_change_latency_ns
3035                         && dc->bb_overrides.dram_clock_change_latency_ns) {
3036                 dc->dml2_options.bbox_overrides.dram_clock_change_latency_us =
3037                 dcn3_2_soc.dram_clock_change_latency_us =
3038                         dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
3039         }
3040
3041         if ((int)(dcn3_2_soc.fclk_change_latency_us * 1000)
3042                         != dc->bb_overrides.fclk_clock_change_latency_ns
3043                         && dc->bb_overrides.fclk_clock_change_latency_ns) {
3044                 dc->dml2_options.bbox_overrides.fclk_change_latency_us =
3045                 dcn3_2_soc.fclk_change_latency_us =
3046                         dc->bb_overrides.fclk_clock_change_latency_ns / 1000;
3047         }
3048
3049         if ((int)(dcn3_2_soc.dummy_pstate_latency_us * 1000)
3050                         != dc->bb_overrides.dummy_clock_change_latency_ns
3051                         && dc->bb_overrides.dummy_clock_change_latency_ns) {
3052                 dcn3_2_soc.dummy_pstate_latency_us =
3053                         dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
3054         }
3055
3056         /* Override from VBIOS if VBIOS bb_info available */
3057         if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
3058                 struct bp_soc_bb_info bb_info = {0};
3059
3060                 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
3061                         if (bb_info.dram_clock_change_latency_100ns > 0)
3062                                 dc->dml2_options.bbox_overrides.dram_clock_change_latency_us =
3063                                 dcn3_2_soc.dram_clock_change_latency_us =
3064                                         bb_info.dram_clock_change_latency_100ns * 10;
3065
3066                         if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
3067                                 dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us =
3068                                 dcn3_2_soc.sr_enter_plus_exit_time_us =
3069                                         bb_info.dram_sr_enter_exit_latency_100ns * 10;
3070
3071                         if (bb_info.dram_sr_exit_latency_100ns > 0)
3072                                 dc->dml2_options.bbox_overrides.sr_exit_latency_us =
3073                                 dcn3_2_soc.sr_exit_time_us =
3074                                         bb_info.dram_sr_exit_latency_100ns * 10;
3075                 }
3076         }
3077
3078         /* Override from VBIOS for num_chan */
3079         if (dc->ctx->dc_bios->vram_info.num_chans) {
3080                 dc->dml2_options.bbox_overrides.dram_num_chan =
3081                 dcn3_2_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
3082                 dcn3_2_soc.mall_allocated_for_dcn_mbytes = (double)(dcn32_calc_num_avail_chans_for_mall(dc,
3083                         dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel);
3084         }
3085
3086         if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
3087                 dc->dml2_options.bbox_overrides.dram_chanel_width_bytes =
3088                 dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
3089
3090         /* DML DSC delay factor workaround */
3091         dcn3_2_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;
3092
3093         dcn3_2_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0;
3094
3095         /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */
3096         dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
3097         dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
3098         dc->dml2_options.bbox_overrides.disp_pll_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
3099         dc->dml2_options.bbox_overrides.xtalclk_mhz = dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000.0;
3100         dc->dml2_options.bbox_overrides.dchub_refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
3101         dc->dml2_options.bbox_overrides.dprefclk_mhz = dc->clk_mgr->dprefclk_khz / 1000.0;
3102
3103         /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */
3104         if (bw_params->clk_table.entries[0].memclk_mhz) {
3105                 if (dc->debug.use_legacy_soc_bb_mechanism) {
3106                         unsigned int i = 0, j = 0, num_states = 0;
3107
3108                         unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
3109                         unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
3110                         unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
3111                         unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
3112                         unsigned int min_dcfclk = UINT_MAX;
3113                         /* Set 199 as first value in STA target array to have a minimum DCFCLK value.
3114                          * For DCN32 we set min to 199 so minimum FCLK DPM0 (300Mhz can be achieved) */
3115                         unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};
3116                         unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0;
3117                         unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
3118
3119                         for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
3120                                 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
3121                                         max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
3122                                 if (bw_params->clk_table.entries[i].dcfclk_mhz != 0 &&
3123                                                 bw_params->clk_table.entries[i].dcfclk_mhz < min_dcfclk)
3124                                         min_dcfclk = bw_params->clk_table.entries[i].dcfclk_mhz;
3125                                 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
3126                                         max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
3127                                 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
3128                                         max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
3129                                 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
3130                                         max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
3131                         }
3132                         if (min_dcfclk > dcfclk_sta_targets[0])
3133                                 dcfclk_sta_targets[0] = min_dcfclk;
3134                         if (!max_dcfclk_mhz)
3135                                 max_dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
3136                         if (!max_dispclk_mhz)
3137                                 max_dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz;
3138                         if (!max_dppclk_mhz)
3139                                 max_dppclk_mhz = dcn3_2_soc.clock_limits[0].dppclk_mhz;
3140                         if (!max_phyclk_mhz)
3141                                 max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz;
3142
3143                         if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
3144                                 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
3145                                 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
3146                                 num_dcfclk_sta_targets++;
3147                         } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
3148                                 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
3149                                 for (i = 0; i < num_dcfclk_sta_targets; i++) {
3150                                         if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
3151                                                 dcfclk_sta_targets[i] = max_dcfclk_mhz;
3152                                                 break;
3153                                         }
3154                                 }
3155                                 // Update size of array since we "removed" duplicates
3156                                 num_dcfclk_sta_targets = i + 1;
3157                         }
3158
3159                         num_uclk_states = bw_params->clk_table.num_entries;
3160
3161                         // Calculate optimal dcfclk for each uclk
3162                         for (i = 0; i < num_uclk_states; i++) {
3163                                 dcn32_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
3164                                                 &optimal_dcfclk_for_uclk[i], NULL);
3165                                 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
3166                                         optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
3167                                 }
3168                         }
3169
3170                         // Calculate optimal uclk for each dcfclk sta target
3171                         for (i = 0; i < num_dcfclk_sta_targets; i++) {
3172                                 for (j = 0; j < num_uclk_states; j++) {
3173                                         if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
3174                                                 optimal_uclk_for_dcfclk_sta_targets[i] =
3175                                                                 bw_params->clk_table.entries[j].memclk_mhz * 16;
3176                                                 break;
3177                                         }
3178                                 }
3179                         }
3180
3181                         i = 0;
3182                         j = 0;
3183                         // create the final dcfclk and uclk table
3184                         while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
3185                                 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
3186                                         dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
3187                                         dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
3188                                 } else {
3189                                         if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
3190                                                 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
3191                                                 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
3192                                         } else {
3193                                                 j = num_uclk_states;
3194                                         }
3195                                 }
3196                         }
3197
3198                         while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
3199                                 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
3200                                 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
3201                         }
3202
3203                         while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
3204                                         optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
3205                                 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
3206                                 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
3207                         }
3208
3209                         dcn3_2_soc.num_states = num_states;
3210                         for (i = 0; i < dcn3_2_soc.num_states; i++) {
3211                                 dcn3_2_soc.clock_limits[i].state = i;
3212                                 dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
3213                                 dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
3214
3215                                 /* Fill all states with max values of all these clocks */
3216                                 dcn3_2_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
3217                                 dcn3_2_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
3218                                 dcn3_2_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
3219                                 dcn3_2_soc.clock_limits[i].dscclk_mhz  = max_dispclk_mhz / 3;
3220
3221                                 /* Populate from bw_params for DTBCLK, SOCCLK */
3222                                 if (i > 0) {
3223                                         if (!bw_params->clk_table.entries[i].dtbclk_mhz) {
3224                                                 dcn3_2_soc.clock_limits[i].dtbclk_mhz  = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz;
3225                                         } else {
3226                                                 dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
3227                                         }
3228                                 } else if (bw_params->clk_table.entries[i].dtbclk_mhz) {
3229                                         dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
3230                                 }
3231
3232                                 if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
3233                                         dcn3_2_soc.clock_limits[i].socclk_mhz = dcn3_2_soc.clock_limits[i-1].socclk_mhz;
3234                                 else
3235                                         dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
3236
3237                                 if (!dram_speed_mts[i] && i > 0)
3238                                         dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts;
3239                                 else
3240                                         dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
3241
3242                                 /* These clocks cannot come from bw_params, always fill from dcn3_2_soc[0] */
3243                                 /* PHYCLK_D18, PHYCLK_D32 */
3244                                 dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;
3245                                 dcn3_2_soc.clock_limits[i].phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;
3246                         }
3247                 } else {
3248                         build_synthetic_soc_states(dc->debug.disable_dc_mode_overwrite, bw_params,
3249                                         dcn3_2_soc.clock_limits, &dcn3_2_soc.num_states);
3250                 }
3251
3252                 /* Re-init DML with updated bb */
3253                 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
3254                 if (dc->current_state)
3255                         dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
3256         }
3257
3258         if (dc->clk_mgr->bw_params->clk_table.num_entries > 1) {
3259                 unsigned int i = 0;
3260
3261                 dc->dml2_options.bbox_overrides.clks_table.num_states = dc->clk_mgr->bw_params->clk_table.num_entries;
3262
3263                 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =
3264                         dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels;
3265
3266                 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =
3267                         dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels;
3268
3269                 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =
3270                         dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels;
3271
3272                 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels =
3273                         dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels;
3274
3275                 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels =
3276                         dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels;
3277
3278                 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels =
3279                         dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels;
3280
3281                 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels =
3282                         dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dppclk_levels;
3283
3284                 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; i++) {
3285                         if (dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz)
3286                                 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz =
3287                                         dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz;
3288                 }
3289
3290                 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels; i++) {
3291                         if (dc->clk_mgr->bw_params->clk_table.entries[i].fclk_mhz)
3292                                 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz =
3293                                         dc->clk_mgr->bw_params->clk_table.entries[i].fclk_mhz;
3294                 }
3295
3296                 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) {
3297                         if (dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)
3298                                 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =
3299                                         dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz;
3300                 }
3301
3302                 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels; i++) {
3303                         if (dc->clk_mgr->bw_params->clk_table.entries[i].socclk_mhz)
3304                                 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz =
3305                                         dc->clk_mgr->bw_params->clk_table.entries[i].socclk_mhz;
3306                 }
3307
3308                 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels; i++) {
3309                         if (dc->clk_mgr->bw_params->clk_table.entries[i].dtbclk_mhz)
3310                                 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =
3311                                         dc->clk_mgr->bw_params->clk_table.entries[i].dtbclk_mhz;
3312                 }
3313
3314                 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; i++) {
3315                         if (dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz) {
3316                                 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz =
3317                                         dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz;
3318                                 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz =
3319                                         dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz;
3320                         }
3321                 }
3322         }
3323 }
3324
3325 void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
3326                                   int pipe_cnt)
3327 {
3328         dc_assert_fp_enabled();
3329
3330         pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
3331         pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
3332 }
3333
3334 bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe)
3335 {
3336         bool allow = false;
3337         uint32_t refresh_rate = 0;
3338         uint32_t min_refresh = subvp_active_margin_list.min_refresh;
3339         uint32_t max_refresh = subvp_active_margin_list.max_refresh;
3340         uint32_t i;
3341
3342         for (i = 0; i < SUBVP_ACTIVE_MARGIN_LIST_LEN; i++) {
3343                 uint32_t width = subvp_active_margin_list.res[i].width;
3344                 uint32_t height = subvp_active_margin_list.res[i].height;
3345
3346                 refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +
3347                         pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1);
3348                 refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
3349                 refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);
3350
3351                 if (refresh_rate >= min_refresh && refresh_rate <= max_refresh &&
3352                                 dcn32_check_native_scaling_for_res(pipe, width, height)) {
3353                         allow = true;
3354                         break;
3355                 }
3356         }
3357         return allow;
3358 }
3359
3360 /**
3361  * dcn32_allow_subvp_high_refresh_rate: Determine if the high refresh rate config will allow subvp
3362  *
3363  * @dc: Current DC state
3364  * @context: New DC state to be programmed
3365  * @pipe: Pipe to be considered for use in subvp
3366  *
3367  * On high refresh rate display configs, we will allow subvp under the following conditions:
3368  * 1. Resolution is 3840x2160, 3440x1440, or 2560x1440
3369  * 2. Refresh rate is between 120hz - 165hz
3370  * 3. No scaling
3371  * 4. Freesync is inactive
3372  * 5. For single display cases, freesync must be disabled
3373  *
3374  * Return: True if pipe can be used for subvp, false otherwise
3375  */
3376 bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe)
3377 {
3378         bool allow = false;
3379         uint32_t refresh_rate = 0;
3380         uint32_t subvp_min_refresh = subvp_high_refresh_list.min_refresh;
3381         uint32_t subvp_max_refresh = subvp_high_refresh_list.max_refresh;
3382         uint32_t min_refresh = subvp_max_refresh;
3383         uint32_t i;
3384
3385         /* Only allow SubVP on high refresh displays if all connected displays
3386          * are considered "high refresh" (i.e. >= 120hz). We do not want to
3387          * allow combinations such as 120hz (SubVP) + 60hz (SubVP).
3388          */
3389         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3390                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
3391
3392                 if (!pipe_ctx->stream)
3393                         continue;
3394                 refresh_rate = (pipe_ctx->stream->timing.pix_clk_100hz * 100 +
3395                                 pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total - 1)
3396                                                 / (double)(pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total);
3397
3398                 if (refresh_rate < min_refresh)
3399                         min_refresh = refresh_rate;
3400         }
3401
3402         if (!dc->debug.disable_subvp_high_refresh && min_refresh >= subvp_min_refresh && pipe->stream &&
3403                         pipe->plane_state && !(pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) {
3404                 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
3405                                                 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
3406                                                 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
3407                 if (refresh_rate >= subvp_min_refresh && refresh_rate <= subvp_max_refresh) {
3408                         for (i = 0; i < SUBVP_HIGH_REFRESH_LIST_LEN; i++) {
3409                                 uint32_t width = subvp_high_refresh_list.res[i].width;
3410                                 uint32_t height = subvp_high_refresh_list.res[i].height;
3411
3412                                 if (dcn32_check_native_scaling_for_res(pipe, width, height)) {
3413                                         if ((context->stream_count == 1 && !pipe->stream->allow_freesync) || context->stream_count > 1) {
3414                                                 allow = true;
3415                                                 break;
3416                                         }
3417                                 }
3418                         }
3419                 }
3420         }
3421         return allow;
3422 }
3423
3424 /**
3425  * dcn32_determine_max_vratio_prefetch: Determine max Vratio for prefetch by driver policy
3426  *
3427  * @dc: Current DC state
3428  * @context: New DC state to be programmed
3429  *
3430  * Return: Max vratio for prefetch
3431  */
3432 double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *context)
3433 {
3434         double max_vratio_pre = __DML_MAX_BW_RATIO_PRE__; // Default value is 4
3435         int i;
3436
3437         /* For single display MPO configs, allow the max vratio to be 8
3438          * if any plane is YUV420 format
3439          */
3440         if (context->stream_count == 1 && context->stream_status[0].plane_count > 1) {
3441                 for (i = 0; i < context->stream_status[0].plane_count; i++) {
3442                         if (context->stream_status[0].plane_states[i]->format == SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr ||
3443                                         context->stream_status[0].plane_states[i]->format == SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb) {
3444                                 max_vratio_pre = __DML_MAX_VRATIO_PRE__;
3445                         }
3446                 }
3447         }
3448         return max_vratio_pre;
3449 }
3450
3451 /**
3452  * dcn32_assign_fpo_vactive_candidate - Assign the FPO stream candidate for FPO + VActive case
3453  *
3454  * This function chooses the FPO candidate stream for FPO + VActive cases (2 stream config).
3455  * For FPO + VAtive cases, the assumption is that one display has ActiveMargin > 0, and the
3456  * other display has ActiveMargin <= 0. This function will choose the pipe/stream that has
3457  * ActiveMargin <= 0 to be the FPO stream candidate if found.
3458  *
3459  *
3460  * @dc: current dc state
3461  * @context: new dc state
3462  * @fpo_candidate_stream: pointer to FPO stream candidate if one is found
3463  *
3464  * Return: void
3465  */
3466 void dcn32_assign_fpo_vactive_candidate(struct dc *dc, const struct dc_state *context, struct dc_stream_state **fpo_candidate_stream)
3467 {
3468         unsigned int i, pipe_idx;
3469         const struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
3470
3471         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3472                 const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3473
3474                 /* In DCN32/321, FPO uses per-pipe P-State force.
3475                  * If there's no planes, HUBP is power gated and
3476                  * therefore programming UCLK_PSTATE_FORCE does
3477                  * nothing (P-State will always be asserted naturally
3478                  * on a pipe that has HUBP power gated. Therefore we
3479                  * only want to enable FPO if the FPO pipe has both
3480                  * a stream and a plane.
3481                  */
3482                 if (!pipe->stream || !pipe->plane_state)
3483                         continue;
3484
3485                 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0) {
3486                         *fpo_candidate_stream = pipe->stream;
3487                         break;
3488                 }
3489                 pipe_idx++;
3490         }
3491 }
3492
3493 /**
3494  * dcn32_find_vactive_pipe - Determines if the config has a pipe that can switch in VACTIVE
3495  *
3496  * @dc: current dc state
3497  * @context: new dc state
3498  * @vactive_margin_req_us: The vactive marign required for a vactive pipe to be considered "found"
3499  *
3500  * Return: True if VACTIVE display is found, false otherwise
3501  */
3502 bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, uint32_t vactive_margin_req_us)
3503 {
3504         unsigned int i, pipe_idx;
3505         const struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
3506         bool vactive_found = false;
3507         unsigned int blank_us = 0;
3508
3509         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3510                 const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3511
3512                 if (!pipe->stream)
3513                         continue;
3514
3515                 blank_us = ((pipe->stream->timing.v_total - pipe->stream->timing.v_addressable) * pipe->stream->timing.h_total /
3516                                 (double)(pipe->stream->timing.pix_clk_100hz * 100)) * 1000000;
3517                 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] >= vactive_margin_req_us &&
3518                                 !(pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed) && blank_us < dc->debug.fpo_vactive_max_blank_us) {
3519                         vactive_found = true;
3520                         break;
3521                 }
3522                 pipe_idx++;
3523         }
3524         return vactive_found;
3525 }
3526
3527 void dcn32_set_clock_limits(const struct _vcs_dpi_soc_bounding_box_st *soc_bb)
3528 {
3529         dc_assert_fp_enabled();
3530         dcn3_2_soc.clock_limits[0].dcfclk_mhz = 1200.0;
3531 }
3532
3533 void dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context)
3534 {
3535         // WA: restrict FPO and SubVP to use first non-strobe mode (DCN32 BW issue)
3536         if ((context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dcn32_subvp_in_use(dc, context)) &&
3537                         dc->dml.soc.num_chans <= 8) {
3538                 int num_mclk_levels = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels;
3539
3540                 if (context->bw_ctx.dml.vba.DRAMSpeed <= dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 16 &&
3541                                 num_mclk_levels > 1) {
3542                         context->bw_ctx.dml.vba.DRAMSpeed = dc->clk_mgr->bw_params->clk_table.entries[1].memclk_mhz * 16;
3543                         context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
3544                 }
3545         }
3546 }