drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright 2022 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26 #include "dcn32_fpu.h"
  27 #include "dcn32/dcn32_resource.h"
  28 #include "dcn20/dcn20_resource.h"
  29 #include "display_mode_vba_util_32.h"
  30 #include "dml/dcn32/display_mode_vba_32.h"
  31 // We need this includes for WATERMARKS_* defines
  32 #include "clk_mgr/dcn32/dcn32_smu13_driver_if.h"
  33 #include "dcn30/dcn30_resource.h"
  34 #include "link.h"
  35
  36 #define DC_LOGGER_INIT(logger)
  37
  38 static const struct subvp_high_refresh_list subvp_high_refresh_list = {
  39                         .min_refresh = 120,
  40                         .max_refresh = 175,
  41                         .res = {
  42                                 {.width = 3840, .height = 2160, },
  43                                 {.width = 3440, .height = 1440, },
  44                                 {.width = 2560, .height = 1440, },
  45                                 {.width = 1920, .height = 1080, }},
  46 };
  47
  48 struct _vcs_dpi_ip_params_st dcn3_2_ip = {
  49         .gpuvm_enable = 0,
  50         .gpuvm_max_page_table_levels = 4,
  51         .hostvm_enable = 0,
  52         .rob_buffer_size_kbytes = 128,
  53         .det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE,
  54         .config_return_buffer_size_in_kbytes = 1280,
  55         .compressed_buffer_segment_size_in_kbytes = 64,
  56         .meta_fifo_size_in_kentries = 22,
  57         .zero_size_buffer_entries = 512,
  58         .compbuf_reserved_space_64b = 256,
  59         .compbuf_reserved_space_zs = 64,
  60         .dpp_output_buffer_pixels = 2560,
  61         .opp_output_buffer_lines = 1,
  62         .pixel_chunk_size_kbytes = 8,
  63         .alpha_pixel_chunk_size_kbytes = 4,
  64         .min_pixel_chunk_size_bytes = 1024,
  65         .dcc_meta_buffer_size_bytes = 6272,
  66         .meta_chunk_size_kbytes = 2,
  67         .min_meta_chunk_size_bytes = 256,
  68         .writeback_chunk_size_kbytes = 8,
  69         .ptoi_supported = false,
  70         .num_dsc = 4,
  71         .maximum_dsc_bits_per_component = 12,
  72         .maximum_pixels_per_line_per_dsc_unit = 6016,
  73         .dsc422_native_support = true,
  74         .is_line_buffer_bpp_fixed = true,
  75         .line_buffer_fixed_bpp = 57,
  76         .line_buffer_size_bits = 1171920,
  77         .max_line_buffer_lines = 32,
  78         .writeback_interface_buffer_size_kbytes = 90,
  79         .max_num_dpp = 4,
  80         .max_num_otg = 4,
  81         .max_num_hdmi_frl_outputs = 1,
  82         .max_num_wb = 1,
  83         .max_dchub_pscl_bw_pix_per_clk = 4,
  84         .max_pscl_lb_bw_pix_per_clk = 2,
  85         .max_lb_vscl_bw_pix_per_clk = 4,
  86         .max_vscl_hscl_bw_pix_per_clk = 4,
  87         .max_hscl_ratio = 6,
  88         .max_vscl_ratio = 6,
  89         .max_hscl_taps = 8,
  90         .max_vscl_taps = 8,
  91         .dpte_buffer_size_in_pte_reqs_luma = 64,
  92         .dpte_buffer_size_in_pte_reqs_chroma = 34,
  93         .dispclk_ramp_margin_percent = 1,
  94         .max_inter_dcn_tile_repeaters = 8,
  95         .cursor_buffer_size = 16,
  96         .cursor_chunk_size = 2,
  97         .writeback_line_buffer_buffer_size = 0,
  98         .writeback_min_hscl_ratio = 1,
  99         .writeback_min_vscl_ratio = 1,
 100         .writeback_max_hscl_ratio = 1,
 101         .writeback_max_vscl_ratio = 1,
 102         .writeback_max_hscl_taps = 1,
 103         .writeback_max_vscl_taps = 1,
 104         .dppclk_delay_subtotal = 47,
 105         .dppclk_delay_scl = 50,
 106         .dppclk_delay_scl_lb_only = 16,
 107         .dppclk_delay_cnvc_formatter = 28,
 108         .dppclk_delay_cnvc_cursor = 6,
 109         .dispclk_delay_subtotal = 125,
 110         .dynamic_metadata_vm_enabled = false,
 111         .odm_combine_4to1_supported = false,
 112         .dcc_supported = true,
 113         .max_num_dp2p0_outputs = 2,
 114         .max_num_dp2p0_streams = 4,
 115 };
 116
 117 struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
 118         .clock_limits = {
 119                 {
 120                         .state = 0,
 121                         .dcfclk_mhz = 1564.0,
 122                         .fabricclk_mhz = 2500.0,
 123                         .dispclk_mhz = 2150.0,
 124                         .dppclk_mhz = 2150.0,
 125                         .phyclk_mhz = 810.0,
 126                         .phyclk_d18_mhz = 667.0,
 127                         .phyclk_d32_mhz = 625.0,
 128                         .socclk_mhz = 1200.0,
 129                         .dscclk_mhz = 716.667,
 130                         .dram_speed_mts = 18000.0,
 131                         .dtbclk_mhz = 1564.0,
 132                 },
 133         },
 134         .num_states = 1,
 135         .sr_exit_time_us = 42.97,
 136         .sr_enter_plus_exit_time_us = 49.94,
 137         .sr_exit_z8_time_us = 285.0,
 138         .sr_enter_plus_exit_z8_time_us = 320,
 139         .writeback_latency_us = 12.0,
 140         .round_trip_ping_latency_dcfclk_cycles = 263,
 141         .urgent_latency_pixel_data_only_us = 4.0,
 142         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 143         .urgent_latency_vm_data_only_us = 4.0,
 144         .fclk_change_latency_us = 25,
 145         .usr_retraining_latency_us = 2,
 146         .smn_latency_us = 2,
 147         .mall_allocated_for_dcn_mbytes = 64,
 148         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 149         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 150         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 151         .pct_ideal_sdp_bw_after_urgent = 90.0,
 152         .pct_ideal_fabric_bw_after_urgent = 67.0,
 153         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0,
 154         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented
 155         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented
 156         .pct_ideal_dram_bw_after_urgent_strobe = 67.0,
 157         .max_avg_sdp_bw_use_normal_percent = 80.0,
 158         .max_avg_fabric_bw_use_normal_percent = 60.0,
 159         .max_avg_dram_bw_use_normal_strobe_percent = 50.0,
 160         .max_avg_dram_bw_use_normal_percent = 15.0,
 161         .num_chans = 24,
 162         .dram_channel_width_bytes = 2,
 163         .fabric_datapath_to_dcn_data_return_bytes = 64,
 164         .return_bus_width_bytes = 64,
 165         .downspread_percent = 0.38,
 166         .dcn_downspread_percent = 0.5,
 167         .dram_clock_change_latency_us = 400,
 168         .dispclk_dppclk_vco_speed_mhz = 4300.0,
 169         .do_urgent_latency_adjustment = true,
 170         .urgent_latency_adjustment_fabric_clock_component_us = 1.0,
 171         .urgent_latency_adjustment_fabric_clock_reference_mhz = 3000,
 172 };
 173
 174 void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr)
 175 {
 176         /* defaults */
 177         double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us;
 178         double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us;
 179         double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;
 180         double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
 181         /* For min clocks use as reported by PM FW and report those as min */
 182         uint16_t min_uclk_mhz                   = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
 183         uint16_t min_dcfclk_mhz                 = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
 184         uint16_t setb_min_uclk_mhz              = min_uclk_mhz;
 185         uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;
 186
 187         dc_assert_fp_enabled();
 188
 189         /* For Set B ranges use min clocks state 2 when available, and report those to PM FW */
 190         if (dcfclk_mhz_for_the_second_state)
 191                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state;
 192         else
 193                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
 194
 195         if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz)
 196                 setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz;
 197
 198         /* Set A - Normal - default values */
 199         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
 200         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
 201         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 202         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;
 203         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 204         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
 205         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
 206         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
 207         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
 208         clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
 209
 210         /* Set B - Performance - higher clocks, using DPM[2] DCFCLK and UCLK */
 211         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true;
 212         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us;
 213         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 214         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us;
 215         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 216         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
 217         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF;
 218         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = setb_min_uclk_mhz;
 219         clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF;
 220
 221         /* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */
 222         /* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */
 223         if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {
 224                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;
 225                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 50;
 226                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 227                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;
 228                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
 229                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
 230                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
 231                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;
 232                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;
 233                 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
 234                 clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16;
 235                 clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 50;
 236                 clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16;
 237                 clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9;
 238                 clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16;
 239                 clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8;
 240                 clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memclk_mhz * 16;
 241                 clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5;
 242         }
 243         /* Set D - MALL - SR enter and exit time specific to MALL, TBD after bringup or later phase for now use DRAM values / 2 */
 244         /* For MALL DRAM clock change latency is N/A, for watermak calculations use lowest value dummy P state latency */
 245         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;
 246         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us;
 247         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us = fclk_change_latency_us;
 248         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us / 2; // TBD
 249         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us / 2; // TBD
 250         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;
 251         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
 252         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;
 253         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;
 254         clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;
 255 }
 256
 257 /*
 258  * Finds dummy_latency_index when MCLK switching using firmware based
 259  * vblank stretch is enabled. This function will iterate through the
 260  * table of dummy pstate latencies until the lowest value that allows
 261  * dm_allow_self_refresh_and_mclk_switch to happen is found
 262  */
 263 int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,
 264                                                             struct dc_state *context,
 265                                                             display_e2e_pipe_params_st *pipes,
 266                                                             int pipe_cnt,
 267                                                             int vlevel)
 268 {
 269         const int max_latency_table_entries = 4;
 270         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 271         int dummy_latency_index = 0;
 272         enum clock_change_support temp_clock_change_support = vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
 273
 274         dc_assert_fp_enabled();
 275
 276         while (dummy_latency_index < max_latency_table_entries) {
 277                 if (temp_clock_change_support != dm_dram_clock_change_unsupported)
 278                         vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support;
 279                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
 280                                 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
 281                 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
 282
 283                 /* for subvp + DRR case, if subvp pipes are still present we support pstate */
 284                 if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported &&
 285                                 dcn32_subvp_in_use(dc, context))
 286                         vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support;
 287
 288                 if (vlevel < context->bw_ctx.dml.vba.soc.num_states &&
 289                                 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported)
 290                         break;
 291
 292                 dummy_latency_index++;
 293         }
 294
 295         if (dummy_latency_index == max_latency_table_entries) {
 296                 ASSERT(dummy_latency_index != max_latency_table_entries);
 297                 /* If the execution gets here, it means dummy p_states are
 298                  * not possible. This should never happen and would mean
 299                  * something is severely wrong.
 300                  * Here we reset dummy_latency_index to 3, because it is
 301                  * better to have underflows than system crashes.
 302                  */
 303                 dummy_latency_index = max_latency_table_entries - 1;
 304         }
 305
 306         return dummy_latency_index;
 307 }
 308
 309 /**
 310  * dcn32_helper_populate_phantom_dlg_params - Get DLG params for phantom pipes
 311  * and populate pipe_ctx with those params.
 312  * @dc: [in] current dc state
 313  * @context: [in] new dc state
 314  * @pipes: [in] DML pipe params array
 315  * @pipe_cnt: [in] DML pipe count
 316  *
 317  * This function must be called AFTER the phantom pipes are added to context
 318  * and run through DML (so that the DLG params for the phantom pipes can be
 319  * populated), and BEFORE we program the timing for the phantom pipes.
 320  */
 321 void dcn32_helper_populate_phantom_dlg_params(struct dc *dc,
 322                                               struct dc_state *context,
 323                                               display_e2e_pipe_params_st *pipes,
 324                                               int pipe_cnt)
 325 {
 326         uint32_t i, pipe_idx;
 327
 328         dc_assert_fp_enabled();
 329
 330         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 331                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 332
 333                 if (!pipe->stream)
 334                         continue;
 335
 336                 if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
 337                         pipes[pipe_idx].pipe.dest.vstartup_start =
 338                                 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 339                         pipes[pipe_idx].pipe.dest.vupdate_offset =
 340                                 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 341                         pipes[pipe_idx].pipe.dest.vupdate_width =
 342                                 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 343                         pipes[pipe_idx].pipe.dest.vready_offset =
 344                                 get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 345                         pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest;
 346                 }
 347                 pipe_idx++;
 348         }
 349 }
 350
 351 static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *entry)
 352 {
 353         float memory_bw_kbytes_sec;
 354         float fabric_bw_kbytes_sec;
 355         float sdp_bw_kbytes_sec;
 356         float limiting_bw_kbytes_sec;
 357
 358         memory_bw_kbytes_sec = entry->dram_speed_mts *
 359                                 dcn3_2_soc.num_chans *
 360                                 dcn3_2_soc.dram_channel_width_bytes *
 361                                 ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100);
 362
 363         fabric_bw_kbytes_sec = entry->fabricclk_mhz *
 364                                 dcn3_2_soc.return_bus_width_bytes *
 365                                 ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100);
 366
 367         sdp_bw_kbytes_sec = entry->dcfclk_mhz *
 368                                 dcn3_2_soc.return_bus_width_bytes *
 369                                 ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100);
 370
 371         limiting_bw_kbytes_sec = memory_bw_kbytes_sec;
 372
 373         if (fabric_bw_kbytes_sec < limiting_bw_kbytes_sec)
 374                 limiting_bw_kbytes_sec = fabric_bw_kbytes_sec;
 375
 376         if (sdp_bw_kbytes_sec < limiting_bw_kbytes_sec)
 377                 limiting_bw_kbytes_sec = sdp_bw_kbytes_sec;
 378
 379         return limiting_bw_kbytes_sec;
 380 }
 381
 382 static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry)
 383 {
 384         if (entry->dcfclk_mhz > 0) {
 385                 float bw_on_sdp = entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100);
 386
 387                 entry->fabricclk_mhz = bw_on_sdp / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100));
 388                 entry->dram_speed_mts = bw_on_sdp / (dcn3_2_soc.num_chans *
 389                                 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100));
 390         } else if (entry->fabricclk_mhz > 0) {
 391                 float bw_on_fabric = entry->fabricclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100);
 392
 393                 entry->dcfclk_mhz = bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100));
 394                 entry->dram_speed_mts = bw_on_fabric / (dcn3_2_soc.num_chans *
 395                                 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100));
 396         } else if (entry->dram_speed_mts > 0) {
 397                 float bw_on_dram = entry->dram_speed_mts * dcn3_2_soc.num_chans *
 398                                 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100);
 399
 400                 entry->fabricclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100));
 401                 entry->dcfclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100));
 402         }
 403 }
 404
 405 static void insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table,
 406                                     unsigned int *num_entries,
 407                                     struct _vcs_dpi_voltage_scaling_st *entry)
 408 {
 409         int i = 0;
 410         int index = 0;
 411
 412         dc_assert_fp_enabled();
 413
 414         if (*num_entries == 0) {
 415                 table[0] = *entry;
 416                 (*num_entries)++;
 417         } else {
 418                 while (entry->net_bw_in_kbytes_sec > table[index].net_bw_in_kbytes_sec) {
 419                         index++;
 420                         if (index >= *num_entries)
 421                                 break;
 422                 }
 423
 424                 for (i = *num_entries; i > index; i--)
 425                         table[i] = table[i - 1];
 426
 427                 table[index] = *entry;
 428                 (*num_entries)++;
 429         }
 430 }
 431
 432 /**
 433  * dcn32_set_phantom_stream_timing - Set timing params for the phantom stream
 434  * @dc: current dc state
 435  * @context: new dc state
 436  * @ref_pipe: Main pipe for the phantom stream
 437  * @phantom_stream: target phantom stream state
 438  * @pipes: DML pipe params
 439  * @pipe_cnt: number of DML pipes
 440  * @dc_pipe_idx: DC pipe index for the main pipe (i.e. ref_pipe)
 441  *
 442  * Set timing params of the phantom stream based on calculated output from DML.
 443  * This function first gets the DML pipe index using the DC pipe index, then
 444  * calls into DML (get_subviewport_lines_needed_in_mall) to get the number of
 445  * lines required for SubVP MCLK switching and assigns to the phantom stream
 446  * accordingly.
 447  *
 448  * - The number of SubVP lines calculated in DML does not take into account
 449  * FW processing delays and required pstate allow width, so we must include
 450  * that separately.
 451  *
 452  * - Set phantom backporch = vstartup of main pipe
 453  */
 454 void dcn32_set_phantom_stream_timing(struct dc *dc,
 455                                      struct dc_state *context,
 456                                      struct pipe_ctx *ref_pipe,
 457                                      struct dc_stream_state *phantom_stream,
 458                                      display_e2e_pipe_params_st *pipes,
 459                                      unsigned int pipe_cnt,
 460                                      unsigned int dc_pipe_idx)
 461 {
 462         unsigned int i, pipe_idx;
 463         struct pipe_ctx *pipe;
 464         uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines;
 465         unsigned int num_dpp;
 466         unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel;
 467         unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
 468         unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel];
 469         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 470         struct dc_stream_state *main_stream = ref_pipe->stream;
 471
 472         dc_assert_fp_enabled();
 473
 474         // Find DML pipe index (pipe_idx) using dc_pipe_idx
 475         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 476                 pipe = &context->res_ctx.pipe_ctx[i];
 477
 478                 if (!pipe->stream)
 479                         continue;
 480
 481                 if (i == dc_pipe_idx)
 482                         break;
 483
 484                 pipe_idx++;
 485         }
 486
 487         // Calculate lines required for pstate allow width and FW processing delays
 488         pstate_width_fw_delay_lines = ((double)(dc->caps.subvp_fw_processing_delay_us +
 489                         dc->caps.subvp_pstate_allow_width_us) / 1000000) *
 490                         (ref_pipe->stream->timing.pix_clk_100hz * 100) /
 491                         (double)ref_pipe->stream->timing.h_total;
 492
 493         // Update clks_cfg for calling into recalculate
 494         pipes[0].clks_cfg.voltage = vlevel;
 495         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
 496         pipes[0].clks_cfg.socclk_mhz = socclk;
 497
 498         // DML calculation for MALL region doesn't take into account FW delay
 499         // and required pstate allow width for multi-display cases
 500         /* Add 16 lines margin to the MALL REGION because SUB_VP_START_LINE must be aligned
 501          * to 2 swaths (i.e. 16 lines)
 502          */
 503         phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) +
 504                                 pstate_width_fw_delay_lines + dc->caps.subvp_swath_height_margin_lines;
 505
 506         // W/A for DCC corruption with certain high resolution timings.
 507         // Determing if pipesplit is used. If so, add meta_row_height to the phantom vactive.
 508         num_dpp = vba->NoOfDPP[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]];
 509         phantom_vactive += num_dpp > 1 ? vba->meta_row_height[vba->pipe_plane[pipe_idx]] : 0;
 510
 511         /* dc->debug.subvp_extra_lines 0 by default*/
 512         phantom_vactive += dc->debug.subvp_extra_lines;
 513
 514         // For backporch of phantom pipe, use vstartup of the main pipe
 515         phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 516
 517         phantom_stream->dst.y = 0;
 518         phantom_stream->dst.height = phantom_vactive;
 519         /* When scaling, DML provides the end to end required number of lines for MALL.
 520          * dst.height is always correct for this case, but src.height is not which causes a
 521          * delta between main and phantom pipe scaling outputs. Need to adjust src.height on
 522          * phantom for this case.
 523          */
 524         phantom_stream->src.y = 0;
 525         phantom_stream->src.height = (double)phantom_vactive * (double)main_stream->src.height / (double)main_stream->dst.height;
 526
 527         phantom_stream->timing.v_addressable = phantom_vactive;
 528         phantom_stream->timing.v_front_porch = 1;
 529         phantom_stream->timing.v_total = phantom_stream->timing.v_addressable +
 530                                                 phantom_stream->timing.v_front_porch +
 531                                                 phantom_stream->timing.v_sync_width +
 532                                                 phantom_bp;
 533         phantom_stream->timing.flags.DSC = 0; // Don't need DSC for phantom timing
 534 }
 535
 536 /**
 537  * dcn32_get_num_free_pipes - Calculate number of free pipes
 538  * @dc: current dc state
 539  * @context: new dc state
 540  *
 541  * This function assumes that a "used" pipe is a pipe that has
 542  * both a stream and a plane assigned to it.
 543  *
 544  * Return: Number of free pipes available in the context
 545  */
 546 static unsigned int dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context)
 547 {
 548         unsigned int i;
 549         unsigned int free_pipes = 0;
 550         unsigned int num_pipes = 0;
 551
 552         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 553                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 554
 555                 if (pipe->stream && !pipe->top_pipe) {
 556                         while (pipe) {
 557                                 num_pipes++;
 558                                 pipe = pipe->bottom_pipe;
 559                         }
 560                 }
 561         }
 562
 563         free_pipes = dc->res_pool->pipe_count - num_pipes;
 564         return free_pipes;
 565 }
 566
 567 /**
 568  * dcn32_assign_subvp_pipe - Function to decide which pipe will use Sub-VP.
 569  * @dc: current dc state
 570  * @context: new dc state
 571  * @index: [out] dc pipe index for the pipe chosen to have phantom pipes assigned
 572  *
 573  * We enter this function if we are Sub-VP capable (i.e. enough pipes available)
 574  * and regular P-State switching (i.e. VACTIVE/VBLANK) is not supported, or if
 575  * we are forcing SubVP P-State switching on the current config.
 576  *
 577  * The number of pipes used for the chosen surface must be less than or equal to the
 578  * number of free pipes available.
 579  *
 580  * In general we choose surfaces with the longest frame time first (better for SubVP + VBLANK).
 581  * For multi-display cases the ActiveDRAMClockChangeMargin doesn't provide enough info on its own
 582  * for determining which should be the SubVP pipe (need a way to determine if a pipe / plane doesn't
 583  * support MCLK switching naturally [i.e. ACTIVE or VBLANK]).
 584  *
 585  * Return: True if a valid pipe assignment was found for Sub-VP. Otherwise false.
 586  */
 587 static bool dcn32_assign_subvp_pipe(struct dc *dc,
 588                                     struct dc_state *context,
 589                                     unsigned int *index)
 590 {
 591         unsigned int i, pipe_idx;
 592         unsigned int max_frame_time = 0;
 593         bool valid_assignment_found = false;
 594         unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context);
 595         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 596
 597         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 598                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 599                 unsigned int num_pipes = 0;
 600                 unsigned int refresh_rate = 0;
 601
 602                 if (!pipe->stream)
 603                         continue;
 604
 605                 // Round up
 606                 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
 607                                 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
 608                                 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
 609                 /* SubVP pipe candidate requirements:
 610                  * - Refresh rate < 120hz
 611                  * - Not able to switch in vactive naturally (switching in active means the
 612                  *   DET provides enough buffer to hide the P-State switch latency -- trying
 613                  *   to combine this with SubVP can cause issues with the scheduling).
 614                  * - Not TMZ surface
 615                  */
 616                 if (pipe->plane_state && !pipe->top_pipe && !dcn32_is_center_timing(pipe) &&
 617                                 !(pipe->stream->timing.pix_clk_100hz / 10000 > DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ) &&
 618                                 (!dcn32_is_psr_capable(pipe) || (context->stream_count == 1 && dc->caps.dmub_caps.subvp_psr)) &&
 619                                 pipe->stream->mall_stream_config.type == SUBVP_NONE &&
 620                                 (refresh_rate < 120 || dcn32_allow_subvp_high_refresh_rate(dc, context, pipe)) &&
 621                                 !pipe->plane_state->address.tmz_surface &&
 622                                 (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0 ||
 623                                 (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 &&
 624                                                 dcn32_allow_subvp_with_active_margin(pipe)))) {
 625                         while (pipe) {
 626                                 num_pipes++;
 627                                 pipe = pipe->bottom_pipe;
 628                         }
 629
 630                         pipe = &context->res_ctx.pipe_ctx[i];
 631                         if (num_pipes <= free_pipes) {
 632                                 struct dc_stream_state *stream = pipe->stream;
 633                                 unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total /
 634                                                 (double)(stream->timing.pix_clk_100hz * 100)) * 1000000;
 635                                 if (frame_us > max_frame_time) {
 636                                         *index = i;
 637                                         max_frame_time = frame_us;
 638                                         valid_assignment_found = true;
 639                                 }
 640                         }
 641                 }
 642                 pipe_idx++;
 643         }
 644         return valid_assignment_found;
 645 }
 646
 647 /**
 648  * dcn32_enough_pipes_for_subvp - Function to check if there are "enough" pipes for SubVP.
 649  * @dc: current dc state
 650  * @context: new dc state
 651  *
 652  * This function returns true if there are enough free pipes
 653  * to create the required phantom pipes for any given stream
 654  * (that does not already have phantom pipe assigned).
 655  *
 656  * e.g. For a 2 stream config where the first stream uses one
 657  * pipe and the second stream uses 2 pipes (i.e. pipe split),
 658  * this function will return true because there is 1 remaining
 659  * pipe which can be used as the phantom pipe for the non pipe
 660  * split pipe.
 661  *
 662  * Return:
 663  * True if there are enough free pipes to assign phantom pipes to at least one
 664  * stream that does not already have phantom pipes assigned. Otherwise false.
 665  */
 666 static bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context)
 667 {
 668         unsigned int i, split_cnt, free_pipes;
 669         unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1
 670         bool subvp_possible = false;
 671
 672         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 673                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 674
 675                 // Find the minimum pipe split count for non SubVP pipes
 676                 if (resource_is_pipe_type(pipe, OPP_HEAD) &&
 677                     pipe->stream->mall_stream_config.type == SUBVP_NONE) {
 678                         split_cnt = 0;
 679                         while (pipe) {
 680                                 split_cnt++;
 681                                 pipe = pipe->bottom_pipe;
 682                         }
 683
 684                         if (split_cnt < min_pipe_split)
 685                                 min_pipe_split = split_cnt;
 686                 }
 687         }
 688
 689         free_pipes = dcn32_get_num_free_pipes(dc, context);
 690
 691         // SubVP only possible if at least one pipe is being used (i.e. free_pipes
 692         // should not equal to the pipe_count)
 693         if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count)
 694                 subvp_possible = true;
 695
 696         return subvp_possible;
 697 }
 698
 699 /**
 700  * subvp_subvp_schedulable - Determine if SubVP + SubVP config is schedulable
 701  * @dc: current dc state
 702  * @context: new dc state
 703  *
 704  * High level algorithm:
 705  * 1. Find longest microschedule length (in us) between the two SubVP pipes
 706  * 2. Check if the worst case overlap (VBLANK in middle of ACTIVE) for both
 707  * pipes still allows for the maximum microschedule to fit in the active
 708  * region for both pipes.
 709  *
 710  * Return: True if the SubVP + SubVP config is schedulable, false otherwise
 711  */
 712 static bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context)
 713 {
 714         struct pipe_ctx *subvp_pipes[2];
 715         struct dc_stream_state *phantom = NULL;
 716         uint32_t microschedule_lines = 0;
 717         uint32_t index = 0;
 718         uint32_t i;
 719         uint32_t max_microschedule_us = 0;
 720         int32_t vactive1_us, vactive2_us, vblank1_us, vblank2_us;
 721
 722         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 723                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 724                 uint32_t time_us = 0;
 725
 726                 /* Loop to calculate the maximum microschedule time between the two SubVP pipes,
 727                  * and also to store the two main SubVP pipe pointers in subvp_pipes[2].
 728                  */
 729                 if (pipe->stream && pipe->plane_state && !pipe->top_pipe &&
 730                     pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
 731                         phantom = pipe->stream->mall_stream_config.paired_stream;
 732                         microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) +
 733                                         phantom->timing.v_addressable;
 734
 735                         // Round up when calculating microschedule time (+ 1 at the end)
 736                         time_us = (microschedule_lines * phantom->timing.h_total) /
 737                                         (double)(phantom->timing.pix_clk_100hz * 100) * 1000000 +
 738                                                 dc->caps.subvp_prefetch_end_to_mall_start_us +
 739                                                 dc->caps.subvp_fw_processing_delay_us + 1;
 740                         if (time_us > max_microschedule_us)
 741                                 max_microschedule_us = time_us;
 742
 743                         subvp_pipes[index] = pipe;
 744                         index++;
 745
 746                         // Maximum 2 SubVP pipes
 747                         if (index == 2)
 748                                 break;
 749                 }
 750         }
 751         vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) /
 752                         (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 753         vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) /
 754                                 (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 755         vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) *
 756                         subvp_pipes[0]->stream->timing.h_total) /
 757                         (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 758         vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) *
 759                         subvp_pipes[1]->stream->timing.h_total) /
 760                         (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
 761
 762         if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us &&
 763             (vactive2_us - vblank1_us) / 2 > max_microschedule_us)
 764                 return true;
 765
 766         return false;
 767 }
 768
 769 /**
 770  * subvp_drr_schedulable() - Determine if SubVP + DRR config is schedulable
 771  * @dc: current dc state
 772  * @context: new dc state
 773  *
 774  * High level algorithm:
 775  * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe
 776  * 2. Determine the frame time for the DRR display when adding required margin for MCLK switching
 777  * (the margin is equal to the MALL region + DRR margin (500us))
 778  * 3.If (SubVP Active - Prefetch > Stretched DRR frame + max(MALL region, Stretched DRR frame))
 779  * then report the configuration as supported
 780  *
 781  * Return: True if the SubVP + DRR config is schedulable, false otherwise
 782  */
 783 static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context)
 784 {
 785         bool schedulable = false;
 786         uint32_t i;
 787         struct pipe_ctx *pipe = NULL;
 788         struct pipe_ctx *drr_pipe = NULL;
 789         struct dc_crtc_timing *main_timing = NULL;
 790         struct dc_crtc_timing *phantom_timing = NULL;
 791         struct dc_crtc_timing *drr_timing = NULL;
 792         int16_t prefetch_us = 0;
 793         int16_t mall_region_us = 0;
 794         int16_t drr_frame_us = 0;       // nominal frame time
 795         int16_t subvp_active_us = 0;
 796         int16_t stretched_drr_us = 0;
 797         int16_t drr_stretched_vblank_us = 0;
 798         int16_t max_vblank_mallregion = 0;
 799
 800         // Find SubVP pipe
 801         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 802                 pipe = &context->res_ctx.pipe_ctx[i];
 803
 804                 // We check for master pipe, but it shouldn't matter since we only need
 805                 // the pipe for timing info (stream should be same for any pipe splits)
 806                 if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
 807                                 !resource_is_pipe_type(pipe, DPP_PIPE))
 808                         continue;
 809
 810                 // Find the SubVP pipe
 811                 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
 812                         break;
 813         }
 814
 815         // Find the DRR pipe
 816         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 817                 drr_pipe = &context->res_ctx.pipe_ctx[i];
 818
 819                 // We check for master pipe only
 820                 if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
 821                                 !resource_is_pipe_type(pipe, DPP_PIPE))
 822                         continue;
 823
 824                 if (drr_pipe->stream->mall_stream_config.type == SUBVP_NONE && drr_pipe->stream->ignore_msa_timing_param &&
 825                                 (drr_pipe->stream->allow_freesync || drr_pipe->stream->vrr_active_variable || drr_pipe->stream->vrr_active_fixed))
 826                         break;
 827         }
 828
 829         main_timing = &pipe->stream->timing;
 830         phantom_timing = &pipe->stream->mall_stream_config.paired_stream->timing;
 831         drr_timing = &drr_pipe->stream->timing;
 832         prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
 833                         (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
 834                         dc->caps.subvp_prefetch_end_to_mall_start_us;
 835         subvp_active_us = main_timing->v_addressable * main_timing->h_total /
 836                         (double)(main_timing->pix_clk_100hz * 100) * 1000000;
 837         drr_frame_us = drr_timing->v_total * drr_timing->h_total /
 838                         (double)(drr_timing->pix_clk_100hz * 100) * 1000000;
 839         // P-State allow width and FW delays already included phantom_timing->v_addressable
 840         mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
 841                         (double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
 842         stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
 843         drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total /
 844                         (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us);
 845         max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us;
 846
 847         /* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the
 848          * highest refresh rate + margin that can support UCLK P-State switch) passes the static analysis
 849          * for VBLANK: (VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
 850          * and the max of (VBLANK blanking time, MALL region)).
 851          */
 852         if (stretched_drr_us < (1 / (double)drr_timing->min_refresh_in_uhz) * 1000000 * 1000000 &&
 853                         subvp_active_us - prefetch_us - stretched_drr_us - max_vblank_mallregion > 0)
 854                 schedulable = true;
 855
 856         return schedulable;
 857 }
 858
 859
 860 /**
 861  * subvp_vblank_schedulable - Determine if SubVP + VBLANK config is schedulable
 862  * @dc: current dc state
 863  * @context: new dc state
 864  *
 865  * High level algorithm:
 866  * 1. Get timing for SubVP pipe, phantom pipe, and VBLANK pipe
 867  * 2. If (SubVP Active - Prefetch > Vblank Frame Time + max(MALL region, Vblank blanking time))
 868  * then report the configuration as supported
 869  * 3. If the VBLANK display is DRR, then take the DRR static schedulability path
 870  *
 871  * Return: True if the SubVP + VBLANK/DRR config is schedulable, false otherwise
 872  */
 873 static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)
 874 {
 875         struct pipe_ctx *pipe = NULL;
 876         struct pipe_ctx *subvp_pipe = NULL;
 877         bool found = false;
 878         bool schedulable = false;
 879         uint32_t i = 0;
 880         uint8_t vblank_index = 0;
 881         uint16_t prefetch_us = 0;
 882         uint16_t mall_region_us = 0;
 883         uint16_t vblank_frame_us = 0;
 884         uint16_t subvp_active_us = 0;
 885         uint16_t vblank_blank_us = 0;
 886         uint16_t max_vblank_mallregion = 0;
 887         struct dc_crtc_timing *main_timing = NULL;
 888         struct dc_crtc_timing *phantom_timing = NULL;
 889         struct dc_crtc_timing *vblank_timing = NULL;
 890
 891         /* For SubVP + VBLANK/DRR cases, we assume there can only be
 892          * a single VBLANK/DRR display. If DML outputs SubVP + VBLANK
 893          * is supported, it is either a single VBLANK case or two VBLANK
 894          * displays which are synchronized (in which case they have identical
 895          * timings).
 896          */
 897         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 898                 pipe = &context->res_ctx.pipe_ctx[i];
 899
 900                 // We check for master pipe, but it shouldn't matter since we only need
 901                 // the pipe for timing info (stream should be same for any pipe splits)
 902                 if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
 903                                 !resource_is_pipe_type(pipe, DPP_PIPE))
 904                         continue;
 905
 906                 if (!found && pipe->stream->mall_stream_config.type == SUBVP_NONE) {
 907                         // Found pipe which is not SubVP or Phantom (i.e. the VBLANK pipe).
 908                         vblank_index = i;
 909                         found = true;
 910                 }
 911
 912                 if (!subvp_pipe && pipe->stream->mall_stream_config.type == SUBVP_MAIN)
 913                         subvp_pipe = pipe;
 914         }
 915         if (found) {
 916                 main_timing = &subvp_pipe->stream->timing;
 917                 phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing;
 918                 vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;
 919                 // Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe
 920                 // Also include the prefetch end to mallstart delay time
 921                 prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
 922                                 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
 923                                 dc->caps.subvp_prefetch_end_to_mall_start_us;
 924                 // P-State allow width and FW delays already included phantom_timing->v_addressable
 925                 mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
 926                                 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
 927                 vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total /
 928                                 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
 929                 vblank_blank_us =  (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total /
 930                                 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
 931                 subvp_active_us = main_timing->v_addressable * main_timing->h_total /
 932                                 (double)(main_timing->pix_clk_100hz * 100) * 1000000;
 933                 max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us;
 934
 935                 // Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
 936                 // and the max of (VBLANK blanking time, MALL region)
 937                 // TODO: Possibly add some margin (i.e. the below conditions should be [...] > X instead of [...] > 0)
 938                 if (subvp_active_us - prefetch_us - vblank_frame_us - max_vblank_mallregion > 0)
 939                         schedulable = true;
 940         }
 941         return schedulable;
 942 }
 943
 944 /**
 945  * subvp_subvp_admissable() - Determine if subvp + subvp config is admissible
 946  *
 947  * @dc: Current DC state
 948  * @context: New DC state to be programmed
 949  *
 950  * SubVP + SubVP is admissible under the following conditions:
 951  * - All SubVP pipes are < 120Hz OR
 952  * - All SubVP pipes are >= 120hz
 953  *
 954  * Return: True if admissible, false otherwise
 955  */
 956 static bool subvp_subvp_admissable(struct dc *dc,
 957                                 struct dc_state *context)
 958 {
 959         bool result = false;
 960         uint32_t i;
 961         uint8_t subvp_count = 0;
 962         uint32_t min_refresh = subvp_high_refresh_list.min_refresh, max_refresh = 0;
 963         uint64_t refresh_rate = 0;
 964
 965         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 966                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 967
 968                 if (!pipe->stream)
 969                         continue;
 970
 971                 if (pipe->plane_state && !pipe->top_pipe &&
 972                                 pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
 973                         refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +
 974                                 pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1);
 975                         refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
 976                         refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);
 977
 978                         if ((uint32_t)refresh_rate < min_refresh)
 979                                 min_refresh = (uint32_t)refresh_rate;
 980                         if ((uint32_t)refresh_rate > max_refresh)
 981                                 max_refresh = (uint32_t)refresh_rate;
 982                         subvp_count++;
 983                 }
 984         }
 985
 986         if (subvp_count == 2 && ((min_refresh < 120 && max_refresh < 120) ||
 987                 (min_refresh >= subvp_high_refresh_list.min_refresh &&
 988                                 max_refresh <= subvp_high_refresh_list.max_refresh)))
 989                 result = true;
 990
 991         return result;
 992 }
 993
 994 /**
 995  * subvp_validate_static_schedulability - Check which SubVP case is calculated
 996  * and handle static analysis based on the case.
 997  * @dc: current dc state
 998  * @context: new dc state
 999  * @vlevel: Voltage level calculated by DML
1000  *
1001  * Three cases:
1002  * 1. SubVP + SubVP
1003  * 2. SubVP + VBLANK (DRR checked internally)
1004  * 3. SubVP + VACTIVE (currently unsupported)
1005  *
1006  * Return: True if statically schedulable, false otherwise
1007  */
1008 static bool subvp_validate_static_schedulability(struct dc *dc,
1009                                 struct dc_state *context,
1010                                 int vlevel)
1011 {
1012         bool schedulable = false;
1013         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1014         uint32_t i, pipe_idx;
1015         uint8_t subvp_count = 0;
1016         uint8_t vactive_count = 0;
1017         uint8_t non_subvp_pipes = 0;
1018
1019         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1020                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1021
1022                 if (!pipe->stream)
1023                         continue;
1024
1025                 if (pipe->plane_state && !pipe->top_pipe) {
1026                         if (pipe->stream->mall_stream_config.type == SUBVP_MAIN)
1027                                 subvp_count++;
1028                         if (pipe->stream->mall_stream_config.type == SUBVP_NONE) {
1029                                 non_subvp_pipes++;
1030                         }
1031                 }
1032
1033                 // Count how many planes that aren't SubVP/phantom are capable of VACTIVE
1034                 // switching (SubVP + VACTIVE unsupported). In situations where we force
1035                 // SubVP for a VACTIVE plane, we don't want to increment the vactive_count.
1036                 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vlevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 &&
1037                     pipe->stream->mall_stream_config.type == SUBVP_NONE) {
1038                         vactive_count++;
1039                 }
1040                 pipe_idx++;
1041         }
1042
1043         if (subvp_count == 2) {
1044                 // Static schedulability check for SubVP + SubVP case
1045                 schedulable = subvp_subvp_admissable(dc, context) && subvp_subvp_schedulable(dc, context);
1046         } else if (subvp_count == 1 && non_subvp_pipes == 0) {
1047                 // Single SubVP configs will be supported by default as long as it's suppported by DML
1048                 schedulable = true;
1049         } else if (subvp_count == 1 && non_subvp_pipes == 1) {
1050                 if (dcn32_subvp_drr_admissable(dc, context))
1051                         schedulable = subvp_drr_schedulable(dc, context);
1052                 else if (dcn32_subvp_vblank_admissable(dc, context, vlevel))
1053                         schedulable = subvp_vblank_schedulable(dc, context);
1054         } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_mall_sub_vp &&
1055                         vactive_count > 0) {
1056                 // For single display SubVP cases, DML will output dm_dram_clock_change_vactive_w_mall_sub_vp by default.
1057                 // We tell the difference between SubVP vs. SubVP + VACTIVE by checking the vactive_count.
1058                 // SubVP + VACTIVE currently unsupported
1059                 schedulable = false;
1060         }
1061         return schedulable;
1062 }
1063
1064 static void assign_subvp_index(struct dc *dc, struct dc_state *context)
1065 {
1066         int i;
1067         int index = 0;
1068
1069         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1070                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1071
1072                 if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) &&
1073                                 pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) {
1074                         pipe_ctx->subvp_index = index++;
1075                 } else {
1076                         pipe_ctx->subvp_index = 0;
1077                 }
1078         }
1079 }
1080
1081 struct pipe_slice_table {
1082         struct {
1083                 struct dc_stream_state *stream;
1084                 int slice_count;
1085         } odm_combines[MAX_STREAMS];
1086         int odm_combine_count;
1087
1088         struct {
1089                 struct pipe_ctx *pri_pipe;
1090                 struct dc_plane_state *plane;
1091                 int slice_count;
1092         } mpc_combines[MAX_SURFACES];
1093         int mpc_combine_count;
1094 };
1095
1096
1097 static void update_slice_table_for_stream(struct pipe_slice_table *table,
1098                 struct dc_stream_state *stream, int diff)
1099 {
1100         int i;
1101
1102         for (i = 0; i < table->odm_combine_count; i++) {
1103                 if (table->odm_combines[i].stream == stream) {
1104                         table->odm_combines[i].slice_count += diff;
1105                         break;
1106                 }
1107         }
1108
1109         if (i == table->odm_combine_count) {
1110                 table->odm_combine_count++;
1111                 table->odm_combines[i].stream = stream;
1112                 table->odm_combines[i].slice_count = diff;
1113         }
1114 }
1115
1116 static void update_slice_table_for_plane(struct pipe_slice_table *table,
1117                 struct pipe_ctx *dpp_pipe, struct dc_plane_state *plane, int diff)
1118 {
1119         int i;
1120         struct pipe_ctx *pri_dpp_pipe = resource_get_primary_dpp_pipe(dpp_pipe);
1121
1122         for (i = 0; i < table->mpc_combine_count; i++) {
1123                 if (table->mpc_combines[i].plane == plane &&
1124                                 table->mpc_combines[i].pri_pipe == pri_dpp_pipe) {
1125                         table->mpc_combines[i].slice_count += diff;
1126                         break;
1127                 }
1128         }
1129
1130         if (i == table->mpc_combine_count) {
1131                 table->mpc_combine_count++;
1132                 table->mpc_combines[i].plane = plane;
1133                 table->mpc_combines[i].pri_pipe = pri_dpp_pipe;
1134                 table->mpc_combines[i].slice_count = diff;
1135         }
1136 }
1137
1138 static void init_pipe_slice_table_from_context(
1139                 struct pipe_slice_table *table,
1140                 struct dc_state *context)
1141 {
1142         int i, j;
1143         struct pipe_ctx *otg_master;
1144         struct pipe_ctx *dpp_pipes[MAX_PIPES];
1145         struct dc_stream_state *stream;
1146         int count;
1147
1148         memset(table, 0, sizeof(*table));
1149
1150         for (i = 0; i < context->stream_count; i++) {
1151                 stream = context->streams[i];
1152                 otg_master = resource_get_otg_master_for_stream(
1153                                 &context->res_ctx, stream);
1154                 count = resource_get_odm_slice_count(otg_master);
1155                 update_slice_table_for_stream(table, stream, count);
1156
1157                 count = resource_get_dpp_pipes_for_opp_head(otg_master,
1158                                 &context->res_ctx, dpp_pipes);
1159                 for (j = 0; j < count; j++)
1160                         if (dpp_pipes[j]->plane_state)
1161                                 update_slice_table_for_plane(table, dpp_pipes[j],
1162                                                 dpp_pipes[j]->plane_state, 1);
1163         }
1164 }
1165
1166 static bool update_pipe_slice_table_with_split_flags(
1167                 struct pipe_slice_table *table,
1168                 struct dc *dc,
1169                 struct dc_state *context,
1170                 struct vba_vars_st *vba,
1171                 int split[MAX_PIPES],
1172                 bool merge[MAX_PIPES])
1173 {
1174         /* NOTE: we are deprecating the support for the concept of pipe splitting
1175          * or pipe merging. Instead we append slices to the end and remove
1176          * slices from the end. The following code converts a pipe split or
1177          * merge to an append or remove operation.
1178          *
1179          * For example:
1180          * When split flags describe the following pipe connection transition
1181          *
1182          * from:
1183          *  pipe 0 (split=2) -> pipe 1 (split=2)
1184          * to: (old behavior)
1185          *  pipe 0 -> pipe 2 -> pipe 1 -> pipe 3
1186          *
1187          * the code below actually does:
1188          *  pipe 0 -> pipe 1 -> pipe 2 -> pipe 3
1189          *
1190          * This is the new intended behavior and for future DCNs we will retire
1191          * the old concept completely.
1192          */
1193         struct pipe_ctx *pipe;
1194         bool odm;
1195         int i;
1196         bool updated = false;
1197
1198         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1199                 pipe = &context->res_ctx.pipe_ctx[i];
1200
1201                 if (merge[i]) {
1202                         if (resource_is_pipe_type(pipe, OPP_HEAD))
1203                                 /* merging OPP head means reducing ODM slice
1204                                  * count by 1
1205                                  */
1206                                 update_slice_table_for_stream(table, pipe->stream, -1);
1207                         else if (resource_is_pipe_type(pipe, DPP_PIPE) &&
1208                                         resource_get_odm_slice_index(resource_get_opp_head(pipe)) == 0)
1209                                 /* merging DPP pipe of the first ODM slice means
1210                                  * reducing MPC slice count by 1
1211                                  */
1212                                 update_slice_table_for_plane(table, pipe, pipe->plane_state, -1);
1213                         updated = true;
1214                 }
1215
1216                 if (split[i]) {
1217                         odm = vba->ODMCombineEnabled[vba->pipe_plane[i]] !=
1218                                         dm_odm_combine_mode_disabled;
1219                         if (odm && resource_is_pipe_type(pipe, OPP_HEAD))
1220                                 update_slice_table_for_stream(
1221                                                 table, pipe->stream, split[i] - 1);
1222                         else if (!odm && resource_is_pipe_type(pipe, DPP_PIPE))
1223                                 update_slice_table_for_plane(table, pipe,
1224                                                 pipe->plane_state, split[i] - 1);
1225                         updated = true;
1226                 }
1227         }
1228         return updated;
1229 }
1230
1231 static void update_pipes_with_slice_table(struct dc *dc, struct dc_state *context,
1232                 struct pipe_slice_table *table)
1233 {
1234         int i;
1235
1236         for (i = 0; i < table->odm_combine_count; i++) {
1237                 resource_update_pipes_for_stream_with_slice_count(context,
1238                                 dc->current_state, dc->res_pool,
1239                                 table->odm_combines[i].stream,
1240                                 table->odm_combines[i].slice_count);
1241                 /* TODO: move this into the function above */
1242                 dcn20_build_mapped_resource(dc, context,
1243                                 table->odm_combines[i].stream);
1244         }
1245
1246         for (i = 0; i < table->mpc_combine_count; i++)
1247                 resource_update_pipes_for_plane_with_slice_count(context,
1248                                 dc->current_state, dc->res_pool,
1249                                 table->mpc_combines[i].plane,
1250                                 table->mpc_combines[i].slice_count);
1251 }
1252
1253 static bool update_pipes_with_split_flags(struct dc *dc, struct dc_state *context,
1254                 struct vba_vars_st *vba, int split[MAX_PIPES],
1255                 bool merge[MAX_PIPES])
1256 {
1257         struct pipe_slice_table slice_table;
1258         bool updated;
1259
1260         init_pipe_slice_table_from_context(&slice_table, context);
1261         updated = update_pipe_slice_table_with_split_flags(
1262                         &slice_table, dc, context, vba,
1263                         split, merge);
1264         update_pipes_with_slice_table(dc, context, &slice_table);
1265         return updated;
1266 }
1267
1268 static bool should_allow_odm_power_optimization(struct dc *dc,
1269                 struct dc_state *context, struct vba_vars_st *v, int *split,
1270                 bool *merge)
1271 {
1272         struct dc_stream_state *stream = context->streams[0];
1273         struct pipe_slice_table slice_table;
1274         int i;
1275
1276         /*
1277          * this debug flag allows us to disable ODM power optimization feature
1278          * unconditionally. we force the feature off if this is set to false.
1279          */
1280         if (!dc->debug.enable_single_display_2to1_odm_policy)
1281                 return false;
1282
1283         /* current design and test coverage is only limited to allow ODM power
1284          * optimization for single stream. Supporting it for multiple streams
1285          * use case would require additional algorithm to decide how to
1286          * optimize power consumption when there are not enough free pipes to
1287          * allocate for all the streams. This level of optimization would
1288          * require multiple attempts of revalidation to make an optimized
1289          * decision. Unfortunately We do not support revalidation flow in
1290          * current version of DML.
1291          */
1292         if (context->stream_count != 1)
1293                 return false;
1294
1295         /*
1296          * Our hardware doesn't support ODM for HDMI TMDS
1297          */
1298         if (dc_is_hdmi_signal(stream->signal))
1299                 return false;
1300
1301         /*
1302          * ODM Combine 2:1 requires horizontal timing divisible by 2 so each
1303          * ODM segment has the same size.
1304          */
1305         if (!is_h_timing_divisible_by_2(stream))
1306                 return false;
1307
1308         /*
1309          * No power benefits if the timing's pixel clock is not high enough to
1310          * raise display clock from minimum power state.
1311          */
1312         if (stream->timing.pix_clk_100hz * 100 <= DCN3_2_VMIN_DISPCLK_HZ)
1313                 return false;
1314
1315         if (dc->config.enable_windowed_mpo_odm) {
1316                 /*
1317                  * ODM power optimization should only be allowed if the feature
1318                  * can be seamlessly toggled off within an update. This would
1319                  * require that the feature is applied on top of a minimal
1320                  * state. A minimal state is defined as a state validated
1321                  * without the need of pipe split. Therefore, when transition to
1322                  * toggle the feature off, the same stream and plane
1323                  * configuration can be supported by the pipe resource in the
1324                  * first ODM slice alone without the need to acquire extra
1325                  * resources.
1326                  */
1327                 init_pipe_slice_table_from_context(&slice_table, context);
1328                 update_pipe_slice_table_with_split_flags(
1329                                 &slice_table, dc, context, v,
1330                                 split, merge);
1331                 for (i = 0; i < slice_table.mpc_combine_count; i++)
1332                         if (slice_table.mpc_combines[i].slice_count > 1)
1333                                 return false;
1334
1335                 for (i = 0; i < slice_table.odm_combine_count; i++)
1336                         if (slice_table.odm_combines[i].slice_count > 1)
1337                                 return false;
1338         } else {
1339                 /*
1340                  * the new ODM power optimization feature reduces software
1341                  * design limitation and allows ODM power optimization to be
1342                  * supported even with presence of overlay planes. The new
1343                  * feature is enabled based on enable_windowed_mpo_odm flag. If
1344                  * the flag is not set, we limit our feature scope due to
1345                  * previous software design limitation
1346                  */
1347                 if (context->stream_status[0].plane_count != 1)
1348                         return false;
1349
1350                 if (memcmp(&context->stream_status[0].plane_states[0]->clip_rect,
1351                                 &stream->src, sizeof(struct rect)) != 0)
1352                         return false;
1353
1354                 if (stream->src.width >= 5120 &&
1355                                 stream->src.width > stream->dst.width)
1356                         return false;
1357         }
1358         return true;
1359 }
1360
1361 static void try_odm_power_optimization_and_revalidate(
1362                 struct dc *dc,
1363                 struct dc_state *context,
1364                 display_e2e_pipe_params_st *pipes,
1365                 int *split,
1366                 bool *merge,
1367                 unsigned int *vlevel,
1368                 int pipe_cnt)
1369 {
1370         int i;
1371         unsigned int new_vlevel;
1372
1373         for (i = 0; i < pipe_cnt; i++)
1374                 pipes[i].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;
1375
1376         new_vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1377
1378         if (new_vlevel < context->bw_ctx.dml.soc.num_states) {
1379                 memset(split, 0, MAX_PIPES * sizeof(int));
1380                 memset(merge, 0, MAX_PIPES * sizeof(bool));
1381                 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, new_vlevel, split, merge);
1382                 context->bw_ctx.dml.vba.VoltageLevel = *vlevel;
1383         }
1384 }
1385
1386 static bool is_test_pattern_enabled(
1387                 struct dc_state *context)
1388 {
1389         int i;
1390
1391         for (i = 0; i < context->stream_count; i++) {
1392                 if (context->streams[i]->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE)
1393                         return true;
1394         }
1395
1396         return false;
1397 }
1398
1399 static void dcn32_full_validate_bw_helper(struct dc *dc,
1400                                    struct dc_state *context,
1401                                    display_e2e_pipe_params_st *pipes,
1402                                    int *vlevel,
1403                                    int *split,
1404                                    bool *merge,
1405                                    int *pipe_cnt)
1406 {
1407         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1408         unsigned int dc_pipe_idx = 0;
1409         int i = 0;
1410         bool found_supported_config = false;
1411
1412         dc_assert_fp_enabled();
1413
1414         /*
1415          * DML favors voltage over p-state, but we're more interested in
1416          * supporting p-state over voltage. We can't support p-state in
1417          * prefetch mode > 0 so try capping the prefetch mode to start.
1418          * Override present for testing.
1419          */
1420         if (dc->debug.dml_disallow_alternate_prefetch_modes)
1421                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1422                         dm_prefetch_support_uclk_fclk_and_stutter;
1423         else
1424                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1425                         dm_prefetch_support_uclk_fclk_and_stutter_if_possible;
1426
1427         *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1428         /* This may adjust vlevel and maxMpcComb */
1429         if (*vlevel < context->bw_ctx.dml.soc.num_states) {
1430                 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
1431                 vba->VoltageLevel = *vlevel;
1432         }
1433
1434         /* Conditions for setting up phantom pipes for SubVP:
1435          * 1. Not force disable SubVP
1436          * 2. Full update (i.e. !fast_validate)
1437          * 3. Enough pipes are available to support SubVP (TODO: Which pipes will use VACTIVE / VBLANK / SUBVP?)
1438          * 4. Display configuration passes validation
1439          * 5. (Config doesn't support MCLK in VACTIVE/VBLANK || dc->debug.force_subvp_mclk_switch)
1440          */
1441         if (!dc->debug.force_disable_subvp && !dc->caps.dmub_caps.gecc_enable && dcn32_all_pipes_have_stream_and_plane(dc, context) &&
1442             !dcn32_mpo_in_use(context) && !dcn32_any_surfaces_rotated(dc, context) && !is_test_pattern_enabled(context) &&
1443                 (*vlevel == context->bw_ctx.dml.soc.num_states ||
1444             vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported ||
1445             dc->debug.force_subvp_mclk_switch)) {
1446
1447                 dcn32_merge_pipes_for_subvp(dc, context);
1448                 memset(merge, 0, MAX_PIPES * sizeof(bool));
1449
1450                 /* to re-initialize viewport after the pipe merge */
1451                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1452                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1453
1454                         if (!pipe_ctx->plane_state || !pipe_ctx->stream)
1455                                 continue;
1456
1457                         resource_build_scaling_params(pipe_ctx);
1458                 }
1459
1460                 while (!found_supported_config && dcn32_enough_pipes_for_subvp(dc, context) &&
1461                         dcn32_assign_subvp_pipe(dc, context, &dc_pipe_idx)) {
1462                         /* For the case where *vlevel = num_states, bandwidth validation has failed for this config.
1463                          * Adding phantom pipes won't change the validation result, so change the DML input param
1464                          * for P-State support before adding phantom pipes and recalculating the DML result.
1465                          * However, this case is only applicable for SubVP + DRR cases because the prefetch mode
1466                          * will not allow for switch in VBLANK. The DRR display must have it's VBLANK stretched
1467                          * enough to support MCLK switching.
1468                          */
1469                         if (*vlevel == context->bw_ctx.dml.soc.num_states &&
1470                                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final ==
1471                                         dm_prefetch_support_uclk_fclk_and_stutter) {
1472                                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1473                                                                 dm_prefetch_support_fclk_and_stutter;
1474                                 /* There are params (such as FabricClock) that need to be recalculated
1475                                  * after validation fails (otherwise it will be 0). Calculation for
1476                                  * phantom vactive requires call into DML, so we must ensure all the
1477                                  * vba params are valid otherwise we'll get incorrect phantom vactive.
1478                                  */
1479                                 *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1480                         }
1481
1482                         dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx);
1483
1484                         *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
1485                         // Populate dppclk to trigger a recalculate in dml_get_voltage_level
1486                         // so the phantom pipe DLG params can be assigned correctly.
1487                         pipes[0].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, *pipe_cnt, 0);
1488                         *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1489
1490                         /* Check that vlevel requested supports pstate or not
1491                          * if not, select the lowest vlevel that supports it
1492                          */
1493                         for (i = *vlevel; i < context->bw_ctx.dml.soc.num_states; i++) {
1494                                 if (vba->DRAMClockChangeSupport[i][vba->maxMpcComb] != dm_dram_clock_change_unsupported) {
1495                                         *vlevel = i;
1496                                         break;
1497                                 }
1498                         }
1499
1500                         if (*vlevel < context->bw_ctx.dml.soc.num_states
1501                             && subvp_validate_static_schedulability(dc, context, *vlevel))
1502                                 found_supported_config = true;
1503                         if (found_supported_config) {
1504                                 // For SubVP + DRR cases, we can force the lowest vlevel that supports the mode
1505                                 if (dcn32_subvp_drr_admissable(dc, context) && subvp_drr_schedulable(dc, context)) {
1506                                         /* find lowest vlevel that supports the config */
1507                                         for (i = *vlevel; i >= 0; i--) {
1508                                                 if (vba->ModeSupport[i][vba->maxMpcComb]) {
1509                                                         *vlevel = i;
1510                                                 } else {
1511                                                         break;
1512                                                 }
1513                                         }
1514                                 }
1515                         }
1516                 }
1517
1518                 // If SubVP pipe config is unsupported (or cannot be used for UCLK switching)
1519                 // remove phantom pipes and repopulate dml pipes
1520                 if (!found_supported_config) {
1521                         dc->res_pool->funcs->remove_phantom_pipes(dc, context, false);
1522                         vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] = dm_dram_clock_change_unsupported;
1523                         *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
1524
1525                         *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1526                         /* This may adjust vlevel and maxMpcComb */
1527                         if (*vlevel < context->bw_ctx.dml.soc.num_states) {
1528                                 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
1529                                 vba->VoltageLevel = *vlevel;
1530                         }
1531                 } else {
1532                         // Most populate phantom DLG params before programming hardware / timing for phantom pipe
1533                         dcn32_helper_populate_phantom_dlg_params(dc, context, pipes, *pipe_cnt);
1534
1535                         /* Call validate_apply_pipe_split flags after calling DML getters for
1536                          * phantom dlg params, or some of the VBA params indicating pipe split
1537                          * can be overwritten by the getters.
1538                          *
1539                          * When setting up SubVP config, all pipes are merged before attempting to
1540                          * add phantom pipes. If pipe split (ODM / MPC) is required, both the main
1541                          * and phantom pipes will be split in the regular pipe splitting sequence.
1542                          */
1543                         memset(split, 0, MAX_PIPES * sizeof(int));
1544                         memset(merge, 0, MAX_PIPES * sizeof(bool));
1545                         *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
1546                         vba->VoltageLevel = *vlevel;
1547                         // Note: We can't apply the phantom pipes to hardware at this time. We have to wait
1548                         // until driver has acquired the DMCUB lock to do it safely.
1549                         assign_subvp_index(dc, context);
1550                 }
1551         }
1552
1553         if (should_allow_odm_power_optimization(dc, context, vba, split, merge))
1554                 try_odm_power_optimization_and_revalidate(
1555                                 dc, context, pipes, split, merge, vlevel, *pipe_cnt);
1556
1557 }
1558
1559 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
1560 {
1561         int i;
1562
1563         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1564                 if (!context->res_ctx.pipe_ctx[i].stream)
1565                         continue;
1566                 if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))
1567                         return true;
1568         }
1569         return false;
1570 }
1571
1572 static void dcn20_adjust_freesync_v_startup(const struct dc_crtc_timing *dc_crtc_timing, int *vstartup_start)
1573 {
1574         struct dc_crtc_timing patched_crtc_timing;
1575         uint32_t asic_blank_end   = 0;
1576         uint32_t asic_blank_start = 0;
1577         uint32_t newVstartup      = 0;
1578
1579         patched_crtc_timing = *dc_crtc_timing;
1580
1581         if (patched_crtc_timing.flags.INTERLACE == 1) {
1582                 if (patched_crtc_timing.v_front_porch < 2)
1583                         patched_crtc_timing.v_front_porch = 2;
1584         } else {
1585                 if (patched_crtc_timing.v_front_porch < 1)
1586                         patched_crtc_timing.v_front_porch = 1;
1587         }
1588
1589         /* blank_start = frame end - front porch */
1590         asic_blank_start = patched_crtc_timing.v_total -
1591                                         patched_crtc_timing.v_front_porch;
1592
1593         /* blank_end = blank_start - active */
1594         asic_blank_end = asic_blank_start -
1595                                         patched_crtc_timing.v_border_bottom -
1596                                         patched_crtc_timing.v_addressable -
1597                                         patched_crtc_timing.v_border_top;
1598
1599         newVstartup = asic_blank_end + (patched_crtc_timing.v_total - asic_blank_start);
1600
1601         *vstartup_start = ((newVstartup > *vstartup_start) ? newVstartup : *vstartup_start);
1602 }
1603
1604 static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context,
1605                                        display_e2e_pipe_params_st *pipes,
1606                                        int pipe_cnt, int vlevel)
1607 {
1608         int i, pipe_idx, active_hubp_count = 0;
1609         bool usr_retraining_support = false;
1610         bool unbounded_req_enabled = false;
1611         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1612
1613         dc_assert_fp_enabled();
1614
1615         /* Writeback MCIF_WB arbitration parameters */
1616         dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
1617
1618         context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
1619         context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
1620         context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
1621         context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
1622         context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
1623         context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
1624         context->bw_ctx.bw.dcn.clk.p_state_change_support =
1625                         context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
1626                                         != dm_dram_clock_change_unsupported;
1627
1628         /* Pstate change might not be supported by hardware, but it might be
1629          * possible with firmware driven vertical blank stretching.
1630          */
1631         context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching;
1632
1633         context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
1634         context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
1635         context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000;
1636         if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported)
1637                 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false;
1638         else
1639                 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;
1640
1641         usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1642         ASSERT(usr_retraining_support);
1643
1644         if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
1645                 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
1646
1647         unbounded_req_enabled = get_unbounded_request_enabled(&context->bw_ctx.dml, pipes, pipe_cnt);
1648
1649         if (unbounded_req_enabled && pipe_cnt > 1) {
1650                 // Unbounded requesting should not ever be used when more than 1 pipe is enabled.
1651                 ASSERT(false);
1652                 unbounded_req_enabled = false;
1653         }
1654
1655         context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0;
1656         context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0;
1657         context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0;
1658
1659         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1660                 if (!context->res_ctx.pipe_ctx[i].stream)
1661                         continue;
1662                 if (context->res_ctx.pipe_ctx[i].plane_state)
1663                         active_hubp_count++;
1664                 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt,
1665                                 pipe_idx);
1666                 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
1667                                 pipe_idx);
1668                 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt,
1669                                 pipe_idx);
1670                 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
1671                                 pipe_idx);
1672
1673                 if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
1674                         // Phantom pipe requires that DET_SIZE = 0 and no unbounded requests
1675                         context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0;
1676                         context->res_ctx.pipe_ctx[i].unbounded_req = false;
1677                 } else {
1678                         context->res_ctx.pipe_ctx[i].det_buffer_size_kb = get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt,
1679                                                         pipe_idx);
1680                         context->res_ctx.pipe_ctx[i].unbounded_req = unbounded_req_enabled;
1681                 }
1682
1683                 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1684                         context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1685                 if (context->res_ctx.pipe_ctx[i].plane_state)
1686                         context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1687                 else
1688                         context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0;
1689                 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
1690
1691                 context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes = get_surface_size_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1692
1693                 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0)
1694                         context->res_ctx.pipe_ctx[i].has_vactive_margin = true;
1695                 else
1696                         context->res_ctx.pipe_ctx[i].has_vactive_margin = false;
1697
1698                 /* MALL Allocation Sizes */
1699                 /* count from active, top pipes per plane only */
1700                 if (context->res_ctx.pipe_ctx[i].stream && context->res_ctx.pipe_ctx[i].plane_state &&
1701                                 (context->res_ctx.pipe_ctx[i].top_pipe == NULL ||
1702                                 context->res_ctx.pipe_ctx[i].plane_state != context->res_ctx.pipe_ctx[i].top_pipe->plane_state) &&
1703                                 context->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1704                         /* SS: all active surfaces stored in MALL */
1705                         if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type != SUBVP_PHANTOM) {
1706                                 context->bw_ctx.bw.dcn.mall_ss_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;
1707
1708                                 if (context->res_ctx.pipe_ctx[i].stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED) {
1709                                         /* SS PSR On: all active surfaces part of streams not supporting PSR stored in MALL */
1710                                         context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;
1711                                 }
1712                         } else {
1713                                 /* SUBVP: phantom surfaces only stored in MALL */
1714                                 context->bw_ctx.bw.dcn.mall_subvp_size_bytes += context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes;
1715                         }
1716                 }
1717
1718                 if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
1719                         dcn20_adjust_freesync_v_startup(
1720                                 &context->res_ctx.pipe_ctx[i].stream->timing,
1721                                 &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);
1722
1723                 pipe_idx++;
1724         }
1725         /* If DCN isn't making memory requests we can allow pstate change and lower clocks */
1726         if (!active_hubp_count) {
1727                 context->bw_ctx.bw.dcn.clk.socclk_khz = 0;
1728                 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
1729                 context->bw_ctx.bw.dcn.clk.dcfclk_khz = 0;
1730                 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = 0;
1731                 context->bw_ctx.bw.dcn.clk.dramclk_khz = 0;
1732                 context->bw_ctx.bw.dcn.clk.fclk_khz = 0;
1733                 context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
1734                 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true;
1735         }
1736         /*save a original dppclock copy*/
1737         context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
1738         context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
1739         context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz
1740                         * 1000;
1741         context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz
1742                         * 1000;
1743
1744         context->bw_ctx.bw.dcn.clk.num_ways = dcn32_helper_calculate_num_ways_for_subvp(dc, context);
1745
1746         context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes;
1747
1748         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1749                 if (context->res_ctx.pipe_ctx[i].stream)
1750                         context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[i].det_buffer_size_kb;
1751         }
1752
1753         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1754
1755                 if (!context->res_ctx.pipe_ctx[i].stream)
1756                         continue;
1757
1758                 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml,
1759                                 &context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes,
1760                                 pipe_cnt, pipe_idx);
1761
1762                 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg_v2(&context->res_ctx.pipe_ctx[i].rq_regs,
1763                                 &context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1764                 pipe_idx++;
1765         }
1766 }
1767
1768 static struct pipe_ctx *dcn32_find_split_pipe(
1769                 struct dc *dc,
1770                 struct dc_state *context,
1771                 int old_index)
1772 {
1773         struct pipe_ctx *pipe = NULL;
1774         int i;
1775
1776         if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
1777                 pipe = &context->res_ctx.pipe_ctx[old_index];
1778                 pipe->pipe_idx = old_index;
1779         }
1780
1781         if (!pipe)
1782                 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1783                         if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
1784                                         && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1785                                 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1786                                         pipe = &context->res_ctx.pipe_ctx[i];
1787                                         pipe->pipe_idx = i;
1788                                         break;
1789                                 }
1790                         }
1791                 }
1792
1793         /*
1794          * May need to fix pipes getting tossed from 1 opp to another on flip
1795          * Add for debugging transient underflow during topology updates:
1796          * ASSERT(pipe);
1797          */
1798         if (!pipe)
1799                 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1800                         if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1801                                 pipe = &context->res_ctx.pipe_ctx[i];
1802                                 pipe->pipe_idx = i;
1803                                 break;
1804                         }
1805                 }
1806
1807         return pipe;
1808 }
1809
1810 static bool dcn32_split_stream_for_mpc_or_odm(
1811                 const struct dc *dc,
1812                 struct resource_context *res_ctx,
1813                 struct pipe_ctx *pri_pipe,
1814                 struct pipe_ctx *sec_pipe,
1815                 bool odm)
1816 {
1817         int pipe_idx = sec_pipe->pipe_idx;
1818         const struct resource_pool *pool = dc->res_pool;
1819
1820         DC_LOGGER_INIT(dc->ctx->logger);
1821
1822         if (odm && pri_pipe->plane_state) {
1823                 /* ODM + window MPO, where MPO window is on left half only */
1824                 if (pri_pipe->plane_state->clip_rect.x + pri_pipe->plane_state->clip_rect.width <=
1825                                 pri_pipe->stream->src.x + pri_pipe->stream->src.width/2) {
1826
1827                         DC_LOG_SCALER("%s - ODM + window MPO(left). pri_pipe:%d\n",
1828                                         __func__,
1829                                         pri_pipe->pipe_idx);
1830                         return true;
1831                 }
1832
1833                 /* ODM + window MPO, where MPO window is on right half only */
1834                 if (pri_pipe->plane_state->clip_rect.x >= pri_pipe->stream->src.x +  pri_pipe->stream->src.width/2) {
1835
1836                         DC_LOG_SCALER("%s - ODM + window MPO(right). pri_pipe:%d\n",
1837                                         __func__,
1838                                         pri_pipe->pipe_idx);
1839                         return true;
1840                 }
1841         }
1842
1843         *sec_pipe = *pri_pipe;
1844
1845         sec_pipe->pipe_idx = pipe_idx;
1846         sec_pipe->plane_res.mi = pool->mis[pipe_idx];
1847         sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
1848         sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
1849         sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
1850         sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
1851         sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
1852         sec_pipe->stream_res.dsc = NULL;
1853         if (odm) {
1854                 if (pri_pipe->next_odm_pipe) {
1855                         ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
1856                         sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
1857                         sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
1858                 }
1859                 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
1860                         pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
1861                         sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
1862                 }
1863                 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
1864                         pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
1865                         sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
1866                 }
1867                 pri_pipe->next_odm_pipe = sec_pipe;
1868                 sec_pipe->prev_odm_pipe = pri_pipe;
1869                 ASSERT(sec_pipe->top_pipe == NULL);
1870
1871                 if (!sec_pipe->top_pipe)
1872                         sec_pipe->stream_res.opp = pool->opps[pipe_idx];
1873                 else
1874                         sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
1875                 if (sec_pipe->stream->timing.flags.DSC == 1) {
1876                         dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
1877                         ASSERT(sec_pipe->stream_res.dsc);
1878                         if (sec_pipe->stream_res.dsc == NULL)
1879                                 return false;
1880                 }
1881         } else {
1882                 if (pri_pipe->bottom_pipe) {
1883                         ASSERT(pri_pipe->bottom_pipe != sec_pipe);
1884                         sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
1885                         sec_pipe->bottom_pipe->top_pipe = sec_pipe;
1886                 }
1887                 pri_pipe->bottom_pipe = sec_pipe;
1888                 sec_pipe->top_pipe = pri_pipe;
1889
1890                 ASSERT(pri_pipe->plane_state);
1891         }
1892
1893         return true;
1894 }
1895
1896 bool dcn32_internal_validate_bw(struct dc *dc,
1897                                 struct dc_state *context,
1898                                 display_e2e_pipe_params_st *pipes,
1899                                 int *pipe_cnt_out,
1900                                 int *vlevel_out,
1901                                 bool fast_validate)
1902 {
1903         bool out = false;
1904         bool repopulate_pipes = false;
1905         int split[MAX_PIPES] = { 0 };
1906         bool merge[MAX_PIPES] = { false };
1907         bool newly_split[MAX_PIPES] = { false };
1908         int pipe_cnt, i, pipe_idx;
1909         int vlevel = context->bw_ctx.dml.soc.num_states;
1910         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1911
1912         dc_assert_fp_enabled();
1913
1914         ASSERT(pipes);
1915         if (!pipes)
1916                 return false;
1917
1918         // For each full update, remove all existing phantom pipes first
1919         dc->res_pool->funcs->remove_phantom_pipes(dc, context, fast_validate);
1920
1921         dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1922
1923         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1924
1925         if (!pipe_cnt) {
1926                 out = true;
1927                 goto validate_out;
1928         }
1929
1930         dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
1931         context->bw_ctx.dml.soc.max_vratio_pre = dcn32_determine_max_vratio_prefetch(dc, context);
1932
1933         if (!fast_validate)
1934                 dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge, &pipe_cnt);
1935
1936         if (fast_validate ||
1937                         (dc->debug.dml_disallow_alternate_prefetch_modes &&
1938                         (vlevel == context->bw_ctx.dml.soc.num_states ||
1939                                 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported))) {
1940                 /*
1941                  * If dml_disallow_alternate_prefetch_modes is false, then we have already
1942                  * tried alternate prefetch modes during full validation.
1943                  *
1944                  * If mode is unsupported or there is no p-state support, then
1945                  * fall back to favouring voltage.
1946                  *
1947                  * If Prefetch mode 0 failed for this config, or passed with Max UCLK, then try
1948                  * to support with Prefetch mode 1 (dm_prefetch_support_fclk_and_stutter == 2)
1949                  */
1950                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
1951                         dm_prefetch_support_none;
1952
1953                 context->bw_ctx.dml.validate_max_state = fast_validate;
1954                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1955
1956                 context->bw_ctx.dml.validate_max_state = false;
1957
1958                 if (vlevel < context->bw_ctx.dml.soc.num_states) {
1959                         memset(split, 0, sizeof(split));
1960                         memset(merge, 0, sizeof(merge));
1961                         vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1962                         // dcn20_validate_apply_pipe_split_flags can modify voltage level outside of DML
1963                         vba->VoltageLevel = vlevel;
1964                 }
1965         }
1966
1967         dml_log_mode_support_params(&context->bw_ctx.dml);
1968
1969         if (vlevel == context->bw_ctx.dml.soc.num_states)
1970                 goto validate_fail;
1971
1972         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1973                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1974                 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
1975
1976                 if (!pipe->stream)
1977                         continue;
1978
1979                 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1980                                 && !dc->config.enable_windowed_mpo_odm
1981                                 && pipe->plane_state && mpo_pipe
1982                                 && memcmp(&mpo_pipe->plane_state->clip_rect,
1983                                                 &pipe->stream->src,
1984                                                 sizeof(struct rect)) != 0) {
1985                         ASSERT(mpo_pipe->plane_state != pipe->plane_state);
1986                         goto validate_fail;
1987                 }
1988                 pipe_idx++;
1989         }
1990
1991         if (dc->config.enable_windowed_mpo_odm) {
1992                 repopulate_pipes = update_pipes_with_split_flags(
1993                                 dc, context, vba, split, merge);
1994         } else {
1995                 /* the code below will be removed once windowed mpo odm is fully
1996                  * enabled.
1997                  */
1998                 /* merge pipes if necessary */
1999                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2000                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2001
2002                         /*skip pipes that don't need merging*/
2003                         if (!merge[i])
2004                                 continue;
2005
2006                         /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
2007                         if (pipe->prev_odm_pipe) {
2008                                 /*split off odm pipe*/
2009                                 pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
2010                                 if (pipe->next_odm_pipe)
2011                                         pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
2012
2013                                 /*2:1ODM+MPC Split MPO to Single Pipe + MPC Split MPO*/
2014                                 if (pipe->bottom_pipe) {
2015                                         if (pipe->bottom_pipe->prev_odm_pipe || pipe->bottom_pipe->next_odm_pipe) {
2016                                                 /*MPC split rules will handle this case*/
2017                                                 pipe->bottom_pipe->top_pipe = NULL;
2018                                         } else {
2019                                                 /* when merging an ODM pipes, the bottom MPC pipe must now point to
2020                                                  * the previous ODM pipe and its associated stream assets
2021                                                  */
2022                                                 if (pipe->prev_odm_pipe->bottom_pipe) {
2023                                                         /* 3 plane MPO*/
2024                                                         pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe->bottom_pipe;
2025                                                         pipe->prev_odm_pipe->bottom_pipe->bottom_pipe = pipe->bottom_pipe;
2026                                                 } else {
2027                                                         /* 2 plane MPO*/
2028                                                         pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe;
2029                                                         pipe->prev_odm_pipe->bottom_pipe = pipe->bottom_pipe;
2030                                                 }
2031
2032                                                 memcpy(&pipe->bottom_pipe->stream_res, &pipe->bottom_pipe->top_pipe->stream_res, sizeof(struct stream_resource));
2033                                         }
2034                                 }
2035
2036                                 if (pipe->top_pipe) {
2037                                         pipe->top_pipe->bottom_pipe = NULL;
2038                                 }
2039
2040                                 pipe->bottom_pipe = NULL;
2041                                 pipe->next_odm_pipe = NULL;
2042                                 pipe->plane_state = NULL;
2043                                 pipe->stream = NULL;
2044                                 pipe->top_pipe = NULL;
2045                                 pipe->prev_odm_pipe = NULL;
2046                                 if (pipe->stream_res.dsc)
2047                                         dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
2048                                 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
2049                                 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
2050                                 memset(&pipe->link_res, 0, sizeof(pipe->link_res));
2051                                 repopulate_pipes = true;
2052                         } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
2053                                 struct pipe_ctx *top_pipe = pipe->top_pipe;
2054                                 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
2055
2056                                 top_pipe->bottom_pipe = bottom_pipe;
2057                                 if (bottom_pipe)
2058                                         bottom_pipe->top_pipe = top_pipe;
2059
2060                                 pipe->top_pipe = NULL;
2061                                 pipe->bottom_pipe = NULL;
2062                                 pipe->plane_state = NULL;
2063                                 pipe->stream = NULL;
2064                                 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
2065                                 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
2066                                 memset(&pipe->link_res, 0, sizeof(pipe->link_res));
2067                                 repopulate_pipes = true;
2068                         } else
2069                                 ASSERT(0); /* Should never try to merge master pipe */
2070
2071                 }
2072
2073                 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2074                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2075                         struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2076                         struct pipe_ctx *hsplit_pipe = NULL;
2077                         bool odm;
2078                         int old_index = -1;
2079
2080                         if (!pipe->stream || newly_split[i])
2081                                 continue;
2082
2083                         pipe_idx++;
2084                         odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
2085
2086                         if (!pipe->plane_state && !odm)
2087                                 continue;
2088
2089                         if (split[i]) {
2090                                 if (odm) {
2091                                         if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
2092                                                 old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
2093                                         else if (old_pipe->next_odm_pipe)
2094                                                 old_index = old_pipe->next_odm_pipe->pipe_idx;
2095                                 } else {
2096                                         if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
2097                                                         old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2098                                                 old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2099                                         else if (old_pipe->bottom_pipe &&
2100                                                         old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2101                                                 old_index = old_pipe->bottom_pipe->pipe_idx;
2102                                 }
2103                                 hsplit_pipe = dcn32_find_split_pipe(dc, context, old_index);
2104                                 ASSERT(hsplit_pipe);
2105                                 if (!hsplit_pipe)
2106                                         goto validate_fail;
2107
2108                                 if (!dcn32_split_stream_for_mpc_or_odm(
2109                                                 dc, &context->res_ctx,
2110                                                 pipe, hsplit_pipe, odm))
2111                                         goto validate_fail;
2112
2113                                 newly_split[hsplit_pipe->pipe_idx] = true;
2114                                 repopulate_pipes = true;
2115                         }
2116                         if (split[i] == 4) {
2117                                 struct pipe_ctx *pipe_4to1;
2118
2119                                 if (odm && old_pipe->next_odm_pipe)
2120                                         old_index = old_pipe->next_odm_pipe->pipe_idx;
2121                                 else if (!odm && old_pipe->bottom_pipe &&
2122                                                         old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2123                                         old_index = old_pipe->bottom_pipe->pipe_idx;
2124                                 else
2125                                         old_index = -1;
2126                                 pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
2127                                 ASSERT(pipe_4to1);
2128                                 if (!pipe_4to1)
2129                                         goto validate_fail;
2130                                 if (!dcn32_split_stream_for_mpc_or_odm(
2131                                                 dc, &context->res_ctx,
2132                                                 pipe, pipe_4to1, odm))
2133                                         goto validate_fail;
2134                                 newly_split[pipe_4to1->pipe_idx] = true;
2135
2136                                 if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
2137                                                 && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
2138                                         old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
2139                                 else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
2140                                                 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
2141                                                 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2142                                         old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2143                                 else
2144                                         old_index = -1;
2145                                 pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index);
2146                                 ASSERT(pipe_4to1);
2147                                 if (!pipe_4to1)
2148                                         goto validate_fail;
2149                                 if (!dcn32_split_stream_for_mpc_or_odm(
2150                                                 dc, &context->res_ctx,
2151                                                 hsplit_pipe, pipe_4to1, odm))
2152                                         goto validate_fail;
2153                                 newly_split[pipe_4to1->pipe_idx] = true;
2154                         }
2155                         if (odm)
2156                                 dcn20_build_mapped_resource(dc, context, pipe->stream);
2157                 }
2158
2159                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2160                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2161
2162                         if (pipe->plane_state) {
2163                                 if (!resource_build_scaling_params(pipe))
2164                                         goto validate_fail;
2165                         }
2166                 }
2167         }
2168
2169         /* Actual dsc count per stream dsc validation*/
2170         if (!dcn20_validate_dsc(dc, context)) {
2171                 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
2172                 goto validate_fail;
2173         }
2174
2175         if (repopulate_pipes) {
2176                 int flag_max_mpc_comb = vba->maxMpcComb;
2177                 int flag_vlevel = vlevel;
2178                 int i;
2179
2180                 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2181
2182                 /* repopulate_pipes = 1 means the pipes were either split or merged. In this case
2183                  * we have to re-calculate the DET allocation and run through DML once more to
2184                  * ensure all the params are calculated correctly. We do not need to run the
2185                  * pipe split check again after this call (pipes are already split / merged).
2186                  * */
2187                 context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
2188                                         dm_prefetch_support_uclk_fclk_and_stutter_if_possible;
2189                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2190                 if (vlevel == context->bw_ctx.dml.soc.num_states) {
2191                         /* failed after DET size changes */
2192                         goto validate_fail;
2193                 } else if (flag_max_mpc_comb == 0 &&
2194                                 flag_max_mpc_comb != context->bw_ctx.dml.vba.maxMpcComb) {
2195                         /* check the context constructed with pipe split flags is still valid*/
2196                         bool flags_valid = false;
2197                         for (i = flag_vlevel; i < context->bw_ctx.dml.soc.num_states; i++) {
2198                                 if (vba->ModeSupport[i][flag_max_mpc_comb]) {
2199                                         vba->maxMpcComb = flag_max_mpc_comb;
2200                                         vba->VoltageLevel = i;
2201                                         vlevel = i;
2202                                         flags_valid = true;
2203                                         break;
2204                                 }
2205                         }
2206
2207                         /* this should never happen */
2208                         if (!flags_valid)
2209                                 goto validate_fail;
2210                 }
2211         }
2212         *vlevel_out = vlevel;
2213         *pipe_cnt_out = pipe_cnt;
2214
2215         out = true;
2216         goto validate_out;
2217
2218 validate_fail:
2219         out = false;
2220
2221 validate_out:
2222         return out;
2223 }
2224
2225
2226 void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context,
2227                                 display_e2e_pipe_params_st *pipes,
2228                                 int pipe_cnt,
2229                                 int vlevel)
2230 {
2231         int i, pipe_idx, vlevel_temp = 0;
2232         double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
2233         double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2234         double dcfclk_from_fw_based_mclk_switching = dcfclk_from_validation;
2235         bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=
2236                         dm_dram_clock_change_unsupported;
2237         unsigned int dummy_latency_index = 0;
2238         int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
2239         unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
2240         bool subvp_in_use = dcn32_subvp_in_use(dc, context);
2241         unsigned int min_dram_speed_mts_margin;
2242         bool need_fclk_lat_as_dummy = false;
2243         bool is_subvp_p_drr = false;
2244         struct dc_stream_state *fpo_candidate_stream = NULL;
2245
2246         dc_assert_fp_enabled();
2247
2248         /* need to find dummy latency index for subvp */
2249         if (subvp_in_use) {
2250                 /* Override DRAMClockChangeSupport for SubVP + DRR case where the DRR cannot switch without stretching it's VBLANK */
2251                 if (!pstate_en) {
2252                         context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp;
2253                         context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = dm_prefetch_support_fclk_and_stutter;
2254                         pstate_en = true;
2255                         is_subvp_p_drr = true;
2256                 }
2257                 dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc,
2258                                                 context, pipes, pipe_cnt, vlevel);
2259
2260                 /* For DCN32/321 need to validate with fclk pstate change latency equal to dummy so prefetch is
2261                  * scheduled correctly to account for dummy pstate.
2262                  */
2263                 if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) {
2264                         need_fclk_lat_as_dummy = true;
2265                         context->bw_ctx.dml.soc.fclk_change_latency_us =
2266                                         dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
2267                 }
2268                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2269                                                         dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2270                 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
2271                 maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
2272                 if (is_subvp_p_drr) {
2273                         context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp;
2274                 }
2275         }
2276
2277         context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;
2278         for (i = 0; i < context->stream_count; i++) {
2279                 if (context->streams[i])
2280                         context->streams[i]->fpo_in_use = false;
2281         }
2282
2283         if (!pstate_en || (!dc->debug.disable_fpo_optimizations &&
2284                         pstate_en && vlevel != 0)) {
2285                 /* only when the mclk switch can not be natural, is the fw based vblank stretch attempted */
2286                 fpo_candidate_stream = dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context);
2287                 if (fpo_candidate_stream) {
2288                         fpo_candidate_stream->fpo_in_use = true;
2289                         context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = true;
2290                 }
2291
2292                 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
2293                         dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc,
2294                                 context, pipes, pipe_cnt, vlevel);
2295
2296                         /* After calling dcn30_find_dummy_latency_index_for_fw_based_mclk_switch
2297                          * we reinstate the original dram_clock_change_latency_us on the context
2298                          * and all variables that may have changed up to this point, except the
2299                          * newly found dummy_latency_index
2300                          */
2301                         context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2302                                         dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2303                         /* For DCN32/321 need to validate with fclk pstate change latency equal to dummy so
2304                          * prefetch is scheduled correctly to account for dummy pstate.
2305                          */
2306                         if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) {
2307                                 need_fclk_lat_as_dummy = true;
2308                                 context->bw_ctx.dml.soc.fclk_change_latency_us =
2309                                                 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
2310                         }
2311                         dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel_temp, false);
2312                         if (vlevel_temp < vlevel) {
2313                                 vlevel = vlevel_temp;
2314                                 maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
2315                                 dcfclk_from_fw_based_mclk_switching = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2316                                 pstate_en = true;
2317                                 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank;
2318                         } else {
2319                                 /* Restore FCLK latency and re-run validation to go back to original validation
2320                                  * output if we find that enabling FPO does not give us any benefit (i.e. lower
2321                                  * voltage level)
2322                                  */
2323                                 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;
2324                                 for (i = 0; i < context->stream_count; i++) {
2325                                         if (context->streams[i])
2326                                                 context->streams[i]->fpo_in_use = false;
2327                                 }
2328                                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;
2329                                 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
2330                         }
2331                 }
2332         }
2333
2334         /* Set B:
2335          * For Set B calculations use clocks from clock_limits[2] when available i.e. when SMU is present,
2336          * otherwise use arbitrary low value from spreadsheet for DCFCLK as lower is safer for watermark
2337          * calculations to cover bootup clocks.
2338          * DCFCLK: soc.clock_limits[2] when available
2339          * UCLK: soc.clock_limits[2] when available
2340          */
2341         if (dcn3_2_soc.num_states > 2) {
2342                 vlevel_temp = 2;
2343                 dcfclk = dcn3_2_soc.clock_limits[2].dcfclk_mhz;
2344         } else
2345                 dcfclk = 615; //DCFCLK Vmin_lv
2346
2347         pipes[0].clks_cfg.voltage = vlevel_temp;
2348         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2349         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;
2350
2351         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
2352                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
2353                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us;
2354                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
2355                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
2356         }
2357         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2358         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2359         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2360         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2361         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2362         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2363         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2364         context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2365         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2366         context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2367
2368         /* Set D:
2369          * All clocks min.
2370          * DCFCLK: Min, as reported by PM FW when available
2371          * UCLK  : Min, as reported by PM FW when available
2372          * sr_enter_exit/sr_exit should be lower than used for DRAM (TBD after bringup or later, use as decided in Clk Mgr)
2373          */
2374
2375         /*
2376         if (dcn3_2_soc.num_states > 2) {
2377                 vlevel_temp = 0;
2378                 dcfclk = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
2379         } else
2380                 dcfclk = 615; //DCFCLK Vmin_lv
2381
2382         pipes[0].clks_cfg.voltage = vlevel_temp;
2383         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2384         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;
2385
2386         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
2387                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
2388                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us;
2389                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
2390                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
2391         }
2392         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2393         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2394         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2395         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2396         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2397         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2398         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2399         context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2400         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2401         context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2402         */
2403
2404         /* Set C, for Dummy P-State:
2405          * All clocks min.
2406          * DCFCLK: Min, as reported by PM FW, when available
2407          * UCLK  : Min,  as reported by PM FW, when available
2408          * pstate latency as per UCLK state dummy pstate latency
2409          */
2410
2411         // For Set A and Set C use values from validation
2412         pipes[0].clks_cfg.voltage = vlevel;
2413         pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_validation;
2414         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2415
2416         if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
2417                 pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_fw_based_mclk_switching;
2418         }
2419
2420         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
2421                 min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
2422                 min_dram_speed_mts_margin = 160;
2423
2424                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2425                         dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us;
2426
2427                 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] ==
2428                         dm_dram_clock_change_unsupported) {
2429                         int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1;
2430
2431                         min_dram_speed_mts =
2432                                 dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16;
2433                 }
2434
2435                 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !subvp_in_use) {
2436                         /* find largest table entry that is lower than dram speed,
2437                          * but lower than DPM0 still uses DPM0
2438                          */
2439                         for (dummy_latency_index = 3; dummy_latency_index > 0; dummy_latency_index--)
2440                                 if (min_dram_speed_mts + min_dram_speed_mts_margin >
2441                                         dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts)
2442                                         break;
2443                 }
2444
2445                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2446                         dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
2447
2448                 context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us;
2449                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
2450                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
2451         }
2452
2453         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2454         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2455         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2456         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2457         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2458         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2459         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2460         context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2461         /* On DCN32/321, PMFW will set PSTATE_CHANGE_TYPE = 1 (FCLK) for UCLK dummy p-state.
2462          * In this case we must program FCLK WM Set C to use the UCLK dummy p-state WM
2463          * value.
2464          */
2465         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2466         context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2467
2468         if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) {
2469                 /* The only difference between A and C is p-state latency, if p-state is not supported
2470                  * with full p-state latency we want to calculate DLG based on dummy p-state latency,
2471                  * Set A p-state watermark set to 0 on DCN30, when p-state unsupported, for now keep as DCN30.
2472                  */
2473                 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;
2474                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;
2475                 /* Calculate FCLK p-state change watermark based on FCLK pstate change latency in case
2476                  * UCLK p-state is not supported, to avoid underflow in case FCLK pstate is supported
2477                  */
2478                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2479         } else {
2480                 /* Set A:
2481                  * All clocks min.
2482                  * DCFCLK: Min, as reported by PM FW, when available
2483                  * UCLK: Min, as reported by PM FW, when available
2484                  */
2485
2486                 /* For set A set the correct latency values (i.e. non-dummy values) unconditionally
2487                  */
2488                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2489                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
2490                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
2491
2492                 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2493                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2494                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2495                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2496                 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2497                 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2498                 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2499                 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2500                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2501                 context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2502         }
2503
2504         /* Make set D = set A since we do not optimized watermarks for MALL */
2505         context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
2506
2507         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2508                 if (!context->res_ctx.pipe_ctx[i].stream)
2509                         continue;
2510
2511                 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
2512                 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
2513
2514                 if (dc->config.forced_clocks) {
2515                         pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2516                         pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2517                 }
2518                 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
2519                         pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2520                 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2521                         pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2522
2523                 pipe_idx++;
2524         }
2525
2526         context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod;
2527
2528         /* for proper prefetch calculations, if dummy lat > fclk lat, use fclk lat = dummy lat */
2529         if (need_fclk_lat_as_dummy)
2530                 context->bw_ctx.dml.soc.fclk_change_latency_us =
2531                                 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
2532
2533         dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2534
2535         if (!pstate_en)
2536                 /* Restore full p-state latency */
2537                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2538                                 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2539
2540         /* revert fclk lat changes if required */
2541         if (need_fclk_lat_as_dummy)
2542                 context->bw_ctx.dml.soc.fclk_change_latency_us =
2543                                 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;
2544 }
2545
2546 static void dcn32_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
2547                 unsigned int *optimal_dcfclk,
2548                 unsigned int *optimal_fclk)
2549 {
2550         double bw_from_dram, bw_from_dram1, bw_from_dram2;
2551
2552         bw_from_dram1 = uclk_mts * dcn3_2_soc.num_chans *
2553                 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_dram_bw_use_normal_percent / 100);
2554         bw_from_dram2 = uclk_mts * dcn3_2_soc.num_chans *
2555                 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100);
2556
2557         bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
2558
2559         if (optimal_fclk)
2560                 *optimal_fclk = bw_from_dram /
2561                 (dcn3_2_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100));
2562
2563         if (optimal_dcfclk)
2564                 *optimal_dcfclk =  bw_from_dram /
2565                 (dcn3_2_soc.return_bus_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100));
2566 }
2567
2568 static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries,
2569                 unsigned int index)
2570 {
2571         int i;
2572
2573         if (*num_entries == 0)
2574                 return;
2575
2576         for (i = index; i < *num_entries - 1; i++) {
2577                 table[i] = table[i + 1];
2578         }
2579         memset(&table[--(*num_entries)], 0, sizeof(struct _vcs_dpi_voltage_scaling_st));
2580 }
2581
2582 void dcn32_patch_dpm_table(struct clk_bw_params *bw_params)
2583 {
2584         int i;
2585         unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0,
2586                         max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0;
2587
2588         for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2589                 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
2590                         max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2591                 if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz)
2592                         max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
2593                 if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz)
2594                         max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz;
2595                 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
2596                         max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2597                 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
2598                         max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2599                 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
2600                         max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2601                 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz)
2602                         max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
2603         }
2604
2605         /* Scan through clock values we currently have and if they are 0,
2606          *  then populate it with dcn3_2_soc.clock_limits[] value.
2607          *
2608          * Do it for DCFCLK, DISPCLK, DTBCLK and UCLK as any of those being
2609          *  0, will cause it to skip building the clock table.
2610          */
2611         if (max_dcfclk_mhz == 0)
2612                 bw_params->clk_table.entries[0].dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
2613         if (max_dispclk_mhz == 0)
2614                 bw_params->clk_table.entries[0].dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz;
2615         if (max_dtbclk_mhz == 0)
2616                 bw_params->clk_table.entries[0].dtbclk_mhz = dcn3_2_soc.clock_limits[0].dtbclk_mhz;
2617         if (max_uclk_mhz == 0)
2618                 bw_params->clk_table.entries[0].memclk_mhz = dcn3_2_soc.clock_limits[0].dram_speed_mts / 16;
2619 }
2620
2621 static void swap_table_entries(struct _vcs_dpi_voltage_scaling_st *first_entry,
2622                 struct _vcs_dpi_voltage_scaling_st *second_entry)
2623 {
2624         struct _vcs_dpi_voltage_scaling_st temp_entry = *first_entry;
2625         *first_entry = *second_entry;
2626         *second_entry = temp_entry;
2627 }
2628
2629 /*
2630  * sort_entries_with_same_bw - Sort entries sharing the same bandwidth by DCFCLK
2631  */
2632 static void sort_entries_with_same_bw(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
2633 {
2634         unsigned int start_index = 0;
2635         unsigned int end_index = 0;
2636         unsigned int current_bw = 0;
2637
2638         for (int i = 0; i < (*num_entries - 1); i++) {
2639                 if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) {
2640                         current_bw = table[i].net_bw_in_kbytes_sec;
2641                         start_index = i;
2642                         end_index = ++i;
2643
2644                         while ((i < (*num_entries - 1)) && (table[i+1].net_bw_in_kbytes_sec == current_bw))
2645                                 end_index = ++i;
2646                 }
2647
2648                 if (start_index != end_index) {
2649                         for (int j = start_index; j < end_index; j++) {
2650                                 for (int k = start_index; k < end_index; k++) {
2651                                         if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz)
2652                                                 swap_table_entries(&table[k], &table[k+1]);
2653                                 }
2654                         }
2655                 }
2656
2657                 start_index = 0;
2658                 end_index = 0;
2659
2660         }
2661 }
2662
2663 /*
2664  * remove_inconsistent_entries - Ensure entries with the same bandwidth have MEMCLK and FCLK monotonically increasing
2665  *                               and remove entries that do not
2666  */
2667 static void remove_inconsistent_entries(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
2668 {
2669         for (int i = 0; i < (*num_entries - 1); i++) {
2670                 if (table[i].net_bw_in_kbytes_sec == table[i+1].net_bw_in_kbytes_sec) {
2671                         if ((table[i].dram_speed_mts > table[i+1].dram_speed_mts) ||
2672                                 (table[i].fabricclk_mhz > table[i+1].fabricclk_mhz))
2673                                 remove_entry_from_table_at_index(table, num_entries, i);
2674                 }
2675         }
2676 }
2677
2678 /*
2679  * override_max_clk_values - Overwrite the max clock frequencies with the max DC mode timings
2680  * Input:
2681  *      max_clk_limit - struct containing the desired clock timings
2682  * Output:
2683  *      curr_clk_limit  - struct containing the timings that need to be overwritten
2684  * Return: 0 upon success, non-zero for failure
2685  */
2686 static int override_max_clk_values(struct clk_limit_table_entry *max_clk_limit,
2687                 struct clk_limit_table_entry *curr_clk_limit)
2688 {
2689         if (NULL == max_clk_limit || NULL == curr_clk_limit)
2690                 return -1; //invalid parameters
2691
2692         //only overwrite if desired max clock frequency is initialized
2693         if (max_clk_limit->dcfclk_mhz != 0)
2694                 curr_clk_limit->dcfclk_mhz = max_clk_limit->dcfclk_mhz;
2695
2696         if (max_clk_limit->fclk_mhz != 0)
2697                 curr_clk_limit->fclk_mhz = max_clk_limit->fclk_mhz;
2698
2699         if (max_clk_limit->memclk_mhz != 0)
2700                 curr_clk_limit->memclk_mhz = max_clk_limit->memclk_mhz;
2701
2702         if (max_clk_limit->socclk_mhz != 0)
2703                 curr_clk_limit->socclk_mhz = max_clk_limit->socclk_mhz;
2704
2705         if (max_clk_limit->dtbclk_mhz != 0)
2706                 curr_clk_limit->dtbclk_mhz = max_clk_limit->dtbclk_mhz;
2707
2708         if (max_clk_limit->dispclk_mhz != 0)
2709                 curr_clk_limit->dispclk_mhz = max_clk_limit->dispclk_mhz;
2710
2711         return 0;
2712 }
2713
2714 static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params,
2715                 struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
2716 {
2717         int i, j;
2718         struct _vcs_dpi_voltage_scaling_st entry = {0};
2719         struct clk_limit_table_entry max_clk_data = {0};
2720
2721         unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299;
2722
2723         static const unsigned int num_dcfclk_stas = 5;
2724         unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};
2725
2726         unsigned int num_uclk_dpms = 0;
2727         unsigned int num_fclk_dpms = 0;
2728         unsigned int num_dcfclk_dpms = 0;
2729
2730         unsigned int num_dc_uclk_dpms = 0;
2731         unsigned int num_dc_fclk_dpms = 0;
2732         unsigned int num_dc_dcfclk_dpms = 0;
2733
2734         for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2735                 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_clk_data.dcfclk_mhz)
2736                         max_clk_data.dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2737                 if (bw_params->clk_table.entries[i].fclk_mhz > max_clk_data.fclk_mhz)
2738                         max_clk_data.fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
2739                 if (bw_params->clk_table.entries[i].memclk_mhz > max_clk_data.memclk_mhz)
2740                         max_clk_data.memclk_mhz = bw_params->clk_table.entries[i].memclk_mhz;
2741                 if (bw_params->clk_table.entries[i].dispclk_mhz > max_clk_data.dispclk_mhz)
2742                         max_clk_data.dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2743                 if (bw_params->clk_table.entries[i].dppclk_mhz > max_clk_data.dppclk_mhz)
2744                         max_clk_data.dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2745                 if (bw_params->clk_table.entries[i].phyclk_mhz > max_clk_data.phyclk_mhz)
2746                         max_clk_data.phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2747                 if (bw_params->clk_table.entries[i].dtbclk_mhz > max_clk_data.dtbclk_mhz)
2748                         max_clk_data.dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
2749
2750                 if (bw_params->clk_table.entries[i].memclk_mhz > 0) {
2751                         num_uclk_dpms++;
2752                         if (bw_params->clk_table.entries[i].memclk_mhz <= bw_params->dc_mode_limit.memclk_mhz)
2753                                 num_dc_uclk_dpms++;
2754                 }
2755                 if (bw_params->clk_table.entries[i].fclk_mhz > 0) {
2756                         num_fclk_dpms++;
2757                         if (bw_params->clk_table.entries[i].fclk_mhz <= bw_params->dc_mode_limit.fclk_mhz)
2758                                 num_dc_fclk_dpms++;
2759                 }
2760                 if (bw_params->clk_table.entries[i].dcfclk_mhz > 0) {
2761                         num_dcfclk_dpms++;
2762                         if (bw_params->clk_table.entries[i].dcfclk_mhz <= bw_params->dc_mode_limit.dcfclk_mhz)
2763                                 num_dc_dcfclk_dpms++;
2764                 }
2765         }
2766
2767         if (!disable_dc_mode_overwrite) {
2768                 //Overwrite max frequencies with max DC mode frequencies for DC mode systems
2769                 override_max_clk_values(&bw_params->dc_mode_limit, &max_clk_data);
2770                 num_uclk_dpms = num_dc_uclk_dpms;
2771                 num_fclk_dpms = num_dc_fclk_dpms;
2772                 num_dcfclk_dpms = num_dc_dcfclk_dpms;
2773                 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = num_uclk_dpms;
2774                 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = num_fclk_dpms;
2775         }
2776
2777         if (num_dcfclk_dpms > 0 && bw_params->clk_table.entries[0].fclk_mhz > min_fclk_mhz)
2778                 min_fclk_mhz = bw_params->clk_table.entries[0].fclk_mhz;
2779
2780         if (!max_clk_data.dcfclk_mhz || !max_clk_data.dispclk_mhz || !max_clk_data.dtbclk_mhz)
2781                 return -1;
2782
2783         if (max_clk_data.dppclk_mhz == 0)
2784                 max_clk_data.dppclk_mhz = max_clk_data.dispclk_mhz;
2785
2786         if (max_clk_data.fclk_mhz == 0)
2787                 max_clk_data.fclk_mhz = max_clk_data.dcfclk_mhz *
2788                                 dcn3_2_soc.pct_ideal_sdp_bw_after_urgent /
2789                                 dcn3_2_soc.pct_ideal_fabric_bw_after_urgent;
2790
2791         if (max_clk_data.phyclk_mhz == 0)
2792                 max_clk_data.phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz;
2793
2794         *num_entries = 0;
2795         entry.dispclk_mhz = max_clk_data.dispclk_mhz;
2796         entry.dscclk_mhz = max_clk_data.dispclk_mhz / 3;
2797         entry.dppclk_mhz = max_clk_data.dppclk_mhz;
2798         entry.dtbclk_mhz = max_clk_data.dtbclk_mhz;
2799         entry.phyclk_mhz = max_clk_data.phyclk_mhz;
2800         entry.phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;
2801         entry.phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;
2802
2803         // Insert all the DCFCLK STAs
2804         for (i = 0; i < num_dcfclk_stas; i++) {
2805                 entry.dcfclk_mhz = dcfclk_sta_targets[i];
2806                 entry.fabricclk_mhz = 0;
2807                 entry.dram_speed_mts = 0;
2808
2809                 get_optimal_ntuple(&entry);
2810                 entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
2811                 insert_entry_into_table_sorted(table, num_entries, &entry);
2812         }
2813
2814         // Insert the max DCFCLK
2815         entry.dcfclk_mhz = max_clk_data.dcfclk_mhz;
2816         entry.fabricclk_mhz = 0;
2817         entry.dram_speed_mts = 0;
2818
2819         get_optimal_ntuple(&entry);
2820         entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
2821         insert_entry_into_table_sorted(table, num_entries, &entry);
2822
2823         // Insert the UCLK DPMS
2824         for (i = 0; i < num_uclk_dpms; i++) {
2825                 entry.dcfclk_mhz = 0;
2826                 entry.fabricclk_mhz = 0;
2827                 entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;
2828
2829                 get_optimal_ntuple(&entry);
2830                 entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
2831                 insert_entry_into_table_sorted(table, num_entries, &entry);
2832         }
2833
2834         // If FCLK is coarse grained, insert individual DPMs.
2835         if (num_fclk_dpms > 2) {
2836                 for (i = 0; i < num_fclk_dpms; i++) {
2837                         entry.dcfclk_mhz = 0;
2838                         entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
2839                         entry.dram_speed_mts = 0;
2840
2841                         get_optimal_ntuple(&entry);
2842                         entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
2843                         insert_entry_into_table_sorted(table, num_entries, &entry);
2844                 }
2845         }
2846         // If FCLK fine grained, only insert max
2847         else {
2848                 entry.dcfclk_mhz = 0;
2849                 entry.fabricclk_mhz = max_clk_data.fclk_mhz;
2850                 entry.dram_speed_mts = 0;
2851
2852                 get_optimal_ntuple(&entry);
2853                 entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
2854                 insert_entry_into_table_sorted(table, num_entries, &entry);
2855         }
2856
2857         // At this point, the table contains all "points of interest" based on
2858         // DPMs from PMFW, and STAs.  Table is sorted by BW, and all clock
2859         // ratios (by derate, are exact).
2860
2861         // Remove states that require higher clocks than are supported
2862         for (i = *num_entries - 1; i >= 0 ; i--) {
2863                 if (table[i].dcfclk_mhz > max_clk_data.dcfclk_mhz ||
2864                                 table[i].fabricclk_mhz > max_clk_data.fclk_mhz ||
2865                                 table[i].dram_speed_mts > max_clk_data.memclk_mhz * 16)
2866                         remove_entry_from_table_at_index(table, num_entries, i);
2867         }
2868
2869         // Insert entry with all max dc limits without bandwidth matching
2870         if (!disable_dc_mode_overwrite) {
2871                 struct _vcs_dpi_voltage_scaling_st max_dc_limits_entry = entry;
2872
2873                 max_dc_limits_entry.dcfclk_mhz = max_clk_data.dcfclk_mhz;
2874                 max_dc_limits_entry.fabricclk_mhz = max_clk_data.fclk_mhz;
2875                 max_dc_limits_entry.dram_speed_mts = max_clk_data.memclk_mhz * 16;
2876
2877                 max_dc_limits_entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&max_dc_limits_entry);
2878                 insert_entry_into_table_sorted(table, num_entries, &max_dc_limits_entry);
2879
2880                 sort_entries_with_same_bw(table, num_entries);
2881                 remove_inconsistent_entries(table, num_entries);
2882         }
2883
2884         // At this point, the table only contains supported points of interest
2885         // it could be used as is, but some states may be redundant due to
2886         // coarse grained nature of some clocks, so we want to round up to
2887         // coarse grained DPMs and remove duplicates.
2888
2889         // Round up UCLKs
2890         for (i = *num_entries - 1; i >= 0 ; i--) {
2891                 for (j = 0; j < num_uclk_dpms; j++) {
2892                         if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) {
2893                                 table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16;
2894                                 break;
2895                         }
2896                 }
2897         }
2898
2899         // If FCLK is coarse grained, round up to next DPMs
2900         if (num_fclk_dpms > 2) {
2901                 for (i = *num_entries - 1; i >= 0 ; i--) {
2902                         for (j = 0; j < num_fclk_dpms; j++) {
2903                                 if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) {
2904                                         table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz;
2905                                         break;
2906                                 }
2907                         }
2908                 }
2909         }
2910         // Otherwise, round up to minimum.
2911         else {
2912                 for (i = *num_entries - 1; i >= 0 ; i--) {
2913                         if (table[i].fabricclk_mhz < min_fclk_mhz) {
2914                                 table[i].fabricclk_mhz = min_fclk_mhz;
2915                         }
2916                 }
2917         }
2918
2919         // Round DCFCLKs up to minimum
2920         for (i = *num_entries - 1; i >= 0 ; i--) {
2921                 if (table[i].dcfclk_mhz < min_dcfclk_mhz) {
2922                         table[i].dcfclk_mhz = min_dcfclk_mhz;
2923                 }
2924         }
2925
2926         // Remove duplicate states, note duplicate states are always neighbouring since table is sorted.
2927         i = 0;
2928         while (i < *num_entries - 1) {
2929                 if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz &&
2930                                 table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz &&
2931                                 table[i].dram_speed_mts == table[i + 1].dram_speed_mts)
2932                         remove_entry_from_table_at_index(table, num_entries, i + 1);
2933                 else
2934                         i++;
2935         }
2936
2937         // Fix up the state indicies
2938         for (i = *num_entries - 1; i >= 0 ; i--) {
2939                 table[i].state = i;
2940         }
2941
2942         return 0;
2943 }
2944
2945 /*
2946  * dcn32_update_bw_bounding_box
2947  *
2948  * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from
2949  * spreadsheet with actual values as per dGPU SKU:
2950  * - with passed few options from dc->config
2951  * - with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might
2952  *   need to get it from PM FW)
2953  * - with passed latency values (passed in ns units) in dc-> bb override for
2954  *   debugging purposes
2955  * - with passed latencies from VBIOS (in 100_ns units) if available for
2956  *   certain dGPU SKU
2957  * - with number of DRAM channels from VBIOS (which differ for certain dGPU SKU
2958  *   of the same ASIC)
2959  * - clocks levels with passed clk_table entries from Clk Mgr as reported by PM
2960  *   FW for different clocks (which might differ for certain dGPU SKU of the
2961  *   same ASIC)
2962  */
2963 void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)
2964 {
2965         dc_assert_fp_enabled();
2966
2967         /* Overrides from dc->config options */
2968         dcn3_2_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
2969
2970         /* Override from passed dc->bb_overrides if available*/
2971         if ((int)(dcn3_2_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
2972                         && dc->bb_overrides.sr_exit_time_ns) {
2973                 dc->dml2_options.bbox_overrides.sr_exit_latency_us =
2974                 dcn3_2_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
2975         }
2976
2977         if ((int)(dcn3_2_soc.sr_enter_plus_exit_time_us * 1000)
2978                         != dc->bb_overrides.sr_enter_plus_exit_time_ns
2979                         && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
2980                 dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us =
2981                 dcn3_2_soc.sr_enter_plus_exit_time_us =
2982                         dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
2983         }
2984
2985         if ((int)(dcn3_2_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
2986                 && dc->bb_overrides.urgent_latency_ns) {
2987                 dcn3_2_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
2988                 dc->dml2_options.bbox_overrides.urgent_latency_us =
2989                 dcn3_2_soc.urgent_latency_pixel_data_only_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
2990         }
2991
2992         if ((int)(dcn3_2_soc.dram_clock_change_latency_us * 1000)
2993                         != dc->bb_overrides.dram_clock_change_latency_ns
2994                         && dc->bb_overrides.dram_clock_change_latency_ns) {
2995                 dc->dml2_options.bbox_overrides.dram_clock_change_latency_us =
2996                 dcn3_2_soc.dram_clock_change_latency_us =
2997                         dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
2998         }
2999
3000         if ((int)(dcn3_2_soc.fclk_change_latency_us * 1000)
3001                         != dc->bb_overrides.fclk_clock_change_latency_ns
3002                         && dc->bb_overrides.fclk_clock_change_latency_ns) {
3003                 dc->dml2_options.bbox_overrides.fclk_change_latency_us =
3004                 dcn3_2_soc.fclk_change_latency_us =
3005                         dc->bb_overrides.fclk_clock_change_latency_ns / 1000;
3006         }
3007
3008         if ((int)(dcn3_2_soc.dummy_pstate_latency_us * 1000)
3009                         != dc->bb_overrides.dummy_clock_change_latency_ns
3010                         && dc->bb_overrides.dummy_clock_change_latency_ns) {
3011                 dcn3_2_soc.dummy_pstate_latency_us =
3012                         dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;
3013         }
3014
3015         /* Override from VBIOS if VBIOS bb_info available */
3016         if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
3017                 struct bp_soc_bb_info bb_info = {0};
3018
3019                 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
3020                         if (bb_info.dram_clock_change_latency_100ns > 0)
3021                                 dc->dml2_options.bbox_overrides.dram_clock_change_latency_us =
3022                                 dcn3_2_soc.dram_clock_change_latency_us =
3023                                         bb_info.dram_clock_change_latency_100ns * 10;
3024
3025                         if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
3026                                 dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us =
3027                                 dcn3_2_soc.sr_enter_plus_exit_time_us =
3028                                         bb_info.dram_sr_enter_exit_latency_100ns * 10;
3029
3030                         if (bb_info.dram_sr_exit_latency_100ns > 0)
3031                                 dc->dml2_options.bbox_overrides.sr_exit_latency_us =
3032                                 dcn3_2_soc.sr_exit_time_us =
3033                                         bb_info.dram_sr_exit_latency_100ns * 10;
3034                 }
3035         }
3036
3037         /* Override from VBIOS for num_chan */
3038         if (dc->ctx->dc_bios->vram_info.num_chans) {
3039                 dc->dml2_options.bbox_overrides.dram_num_chan =
3040                 dcn3_2_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
3041                 dcn3_2_soc.mall_allocated_for_dcn_mbytes = (double)(dcn32_calc_num_avail_chans_for_mall(dc,
3042                         dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel);
3043         }
3044
3045         if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
3046                 dc->dml2_options.bbox_overrides.dram_chanel_width_bytes =
3047                 dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
3048
3049         /* DML DSC delay factor workaround */
3050         dcn3_2_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;
3051
3052         dcn3_2_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0;
3053
3054         /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */
3055         dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
3056         dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
3057         dc->dml2_options.bbox_overrides.disp_pll_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
3058         dc->dml2_options.bbox_overrides.xtalclk_mhz = dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000.0;
3059         dc->dml2_options.bbox_overrides.dchub_refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
3060         dc->dml2_options.bbox_overrides.dprefclk_mhz = dc->clk_mgr->dprefclk_khz / 1000.0;
3061
3062         /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */
3063         if (bw_params->clk_table.entries[0].memclk_mhz) {
3064                 if (dc->debug.use_legacy_soc_bb_mechanism) {
3065                         unsigned int i = 0, j = 0, num_states = 0;
3066
3067                         unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
3068                         unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
3069                         unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
3070                         unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
3071                         unsigned int min_dcfclk = UINT_MAX;
3072                         /* Set 199 as first value in STA target array to have a minimum DCFCLK value.
3073                          * For DCN32 we set min to 199 so minimum FCLK DPM0 (300Mhz can be achieved) */
3074                         unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};
3075                         unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0;
3076                         unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
3077
3078                         for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
3079                                 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
3080                                         max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
3081                                 if (bw_params->clk_table.entries[i].dcfclk_mhz != 0 &&
3082                                                 bw_params->clk_table.entries[i].dcfclk_mhz < min_dcfclk)
3083                                         min_dcfclk = bw_params->clk_table.entries[i].dcfclk_mhz;
3084                                 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
3085                                         max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
3086                                 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
3087                                         max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
3088                                 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
3089                                         max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
3090                         }
3091                         if (min_dcfclk > dcfclk_sta_targets[0])
3092                                 dcfclk_sta_targets[0] = min_dcfclk;
3093                         if (!max_dcfclk_mhz)
3094                                 max_dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
3095                         if (!max_dispclk_mhz)
3096                                 max_dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz;
3097                         if (!max_dppclk_mhz)
3098                                 max_dppclk_mhz = dcn3_2_soc.clock_limits[0].dppclk_mhz;
3099                         if (!max_phyclk_mhz)
3100                                 max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz;
3101
3102                         if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
3103                                 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
3104                                 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
3105                                 num_dcfclk_sta_targets++;
3106                         } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
3107                                 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
3108                                 for (i = 0; i < num_dcfclk_sta_targets; i++) {
3109                                         if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
3110                                                 dcfclk_sta_targets[i] = max_dcfclk_mhz;
3111                                                 break;
3112                                         }
3113                                 }
3114                                 // Update size of array since we "removed" duplicates
3115                                 num_dcfclk_sta_targets = i + 1;
3116                         }
3117
3118                         num_uclk_states = bw_params->clk_table.num_entries;
3119
3120                         // Calculate optimal dcfclk for each uclk
3121                         for (i = 0; i < num_uclk_states; i++) {
3122                                 dcn32_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
3123                                                 &optimal_dcfclk_for_uclk[i], NULL);
3124                                 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
3125                                         optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
3126                                 }
3127                         }
3128
3129                         // Calculate optimal uclk for each dcfclk sta target
3130                         for (i = 0; i < num_dcfclk_sta_targets; i++) {
3131                                 for (j = 0; j < num_uclk_states; j++) {
3132                                         if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
3133                                                 optimal_uclk_for_dcfclk_sta_targets[i] =
3134                                                                 bw_params->clk_table.entries[j].memclk_mhz * 16;
3135                                                 break;
3136                                         }
3137                                 }
3138                         }
3139
3140                         i = 0;
3141                         j = 0;
3142                         // create the final dcfclk and uclk table
3143                         while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
3144                                 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
3145                                         dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
3146                                         dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
3147                                 } else {
3148                                         if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
3149                                                 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
3150                                                 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
3151                                         } else {
3152                                                 j = num_uclk_states;
3153                                         }
3154                                 }
3155                         }
3156
3157                         while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
3158                                 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
3159                                 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
3160                         }
3161
3162                         while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
3163                                         optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
3164                                 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
3165                                 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
3166                         }
3167
3168                         dcn3_2_soc.num_states = num_states;
3169                         for (i = 0; i < dcn3_2_soc.num_states; i++) {
3170                                 dcn3_2_soc.clock_limits[i].state = i;
3171                                 dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
3172                                 dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
3173
3174                                 /* Fill all states with max values of all these clocks */
3175                                 dcn3_2_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
3176                                 dcn3_2_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
3177                                 dcn3_2_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
3178                                 dcn3_2_soc.clock_limits[i].dscclk_mhz  = max_dispclk_mhz / 3;
3179
3180                                 /* Populate from bw_params for DTBCLK, SOCCLK */
3181                                 if (i > 0) {
3182                                         if (!bw_params->clk_table.entries[i].dtbclk_mhz) {
3183                                                 dcn3_2_soc.clock_limits[i].dtbclk_mhz  = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz;
3184                                         } else {
3185                                                 dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
3186                                         }
3187                                 } else if (bw_params->clk_table.entries[i].dtbclk_mhz) {
3188                                         dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
3189                                 }
3190
3191                                 if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
3192                                         dcn3_2_soc.clock_limits[i].socclk_mhz = dcn3_2_soc.clock_limits[i-1].socclk_mhz;
3193                                 else
3194                                         dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
3195
3196                                 if (!dram_speed_mts[i] && i > 0)
3197                                         dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts;
3198                                 else
3199                                         dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
3200
3201                                 /* These clocks cannot come from bw_params, always fill from dcn3_2_soc[0] */
3202                                 /* PHYCLK_D18, PHYCLK_D32 */
3203                                 dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;
3204                                 dcn3_2_soc.clock_limits[i].phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;
3205                         }
3206                 } else {
3207                         build_synthetic_soc_states(dc->debug.disable_dc_mode_overwrite, bw_params,
3208                                         dcn3_2_soc.clock_limits, &dcn3_2_soc.num_states);
3209                 }
3210
3211                 /* Re-init DML with updated bb */
3212                 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
3213                 if (dc->current_state)
3214                         dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
3215         }
3216
3217         if (dc->clk_mgr->bw_params->clk_table.num_entries > 1) {
3218                 unsigned int i = 0;
3219
3220                 dc->dml2_options.bbox_overrides.clks_table.num_states = dc->clk_mgr->bw_params->clk_table.num_entries;
3221
3222                 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =
3223                         dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels;
3224
3225                 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =
3226                         dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels;
3227
3228                 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =
3229                         dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels;
3230
3231                 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels =
3232                         dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels;
3233
3234                 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels =
3235                         dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels;
3236
3237                 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels =
3238                         dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels;
3239
3240                 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels =
3241                         dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dppclk_levels;
3242
3243                 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; i++) {
3244                         if (dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz)
3245                                 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz =
3246                                         dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz;
3247                 }
3248
3249                 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels; i++) {
3250                         if (dc->clk_mgr->bw_params->clk_table.entries[i].fclk_mhz)
3251                                 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz =
3252                                         dc->clk_mgr->bw_params->clk_table.entries[i].fclk_mhz;
3253                 }
3254
3255                 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) {
3256                         if (dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)
3257                                 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =
3258                                         dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz;
3259                 }
3260
3261                 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels; i++) {
3262                         if (dc->clk_mgr->bw_params->clk_table.entries[i].socclk_mhz)
3263                                 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz =
3264                                         dc->clk_mgr->bw_params->clk_table.entries[i].socclk_mhz;
3265                 }
3266
3267                 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels; i++) {
3268                         if (dc->clk_mgr->bw_params->clk_table.entries[i].dtbclk_mhz)
3269                                 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz =
3270                                         dc->clk_mgr->bw_params->clk_table.entries[i].dtbclk_mhz;
3271                 }
3272
3273                 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; i++) {
3274                         if (dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz) {
3275                                 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz =
3276                                         dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz;
3277                                 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz =
3278                                         dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz;
3279                         }
3280                 }
3281         }
3282 }
3283
3284 void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
3285                                   int pipe_cnt)
3286 {
3287         dc_assert_fp_enabled();
3288
3289         pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
3290         pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
3291 }
3292
3293 bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe)
3294 {
3295         bool allow = false;
3296         uint32_t refresh_rate = 0;
3297
3298         /* Allow subvp on displays that have active margin for 2560x1440@60hz displays
3299          * only for now. There must be no scaling as well.
3300          *
3301          * For now we only enable on 2560x1440@60hz displays to enable 4K60 + 1440p60 configs
3302          * for p-state switching.
3303          */
3304         if (pipe->stream && pipe->plane_state) {
3305                 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
3306                                                 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
3307                                                 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
3308                 if (pipe->stream->timing.v_addressable == 1440 &&
3309                                 pipe->stream->timing.h_addressable == 2560 &&
3310                                 refresh_rate >= 55 && refresh_rate <= 65 &&
3311                                 pipe->plane_state->src_rect.height == 1440 &&
3312                                 pipe->plane_state->src_rect.width == 2560 &&
3313                                 pipe->plane_state->dst_rect.height == 1440 &&
3314                                 pipe->plane_state->dst_rect.width == 2560)
3315                         allow = true;
3316         }
3317         return allow;
3318 }
3319
3320 /**
3321  * dcn32_allow_subvp_high_refresh_rate: Determine if the high refresh rate config will allow subvp
3322  *
3323  * @dc: Current DC state
3324  * @context: New DC state to be programmed
3325  * @pipe: Pipe to be considered for use in subvp
3326  *
3327  * On high refresh rate display configs, we will allow subvp under the following conditions:
3328  * 1. Resolution is 3840x2160, 3440x1440, or 2560x1440
3329  * 2. Refresh rate is between 120hz - 165hz
3330  * 3. No scaling
3331  * 4. Freesync is inactive
3332  * 5. For single display cases, freesync must be disabled
3333  *
3334  * Return: True if pipe can be used for subvp, false otherwise
3335  */
3336 bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe)
3337 {
3338         bool allow = false;
3339         uint32_t refresh_rate = 0;
3340         uint32_t subvp_min_refresh = subvp_high_refresh_list.min_refresh;
3341         uint32_t subvp_max_refresh = subvp_high_refresh_list.max_refresh;
3342         uint32_t min_refresh = subvp_max_refresh;
3343         uint32_t i;
3344
3345         /* Only allow SubVP on high refresh displays if all connected displays
3346          * are considered "high refresh" (i.e. >= 120hz). We do not want to
3347          * allow combinations such as 120hz (SubVP) + 60hz (SubVP).
3348          */
3349         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3350                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
3351
3352                 if (!pipe_ctx->stream)
3353                         continue;
3354                 refresh_rate = (pipe_ctx->stream->timing.pix_clk_100hz * 100 +
3355                                 pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total - 1)
3356                                                 / (double)(pipe_ctx->stream->timing.v_total * pipe_ctx->stream->timing.h_total);
3357
3358                 if (refresh_rate < min_refresh)
3359                         min_refresh = refresh_rate;
3360         }
3361
3362         if (!dc->debug.disable_subvp_high_refresh && min_refresh >= subvp_min_refresh && pipe->stream &&
3363                         pipe->plane_state && !(pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) {
3364                 refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
3365                                                 pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
3366                                                 / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
3367                 if (refresh_rate >= subvp_min_refresh && refresh_rate <= subvp_max_refresh) {
3368                         for (i = 0; i < SUBVP_HIGH_REFRESH_LIST_LEN; i++) {
3369                                 uint32_t width = subvp_high_refresh_list.res[i].width;
3370                                 uint32_t height = subvp_high_refresh_list.res[i].height;
3371
3372                                 if (dcn32_check_native_scaling_for_res(pipe, width, height)) {
3373                                         if ((context->stream_count == 1 && !pipe->stream->allow_freesync) || context->stream_count > 1) {
3374                                                 allow = true;
3375                                                 break;
3376                                         }
3377                                 }
3378                         }
3379                 }
3380         }
3381         return allow;
3382 }
3383
3384 /**
3385  * dcn32_determine_max_vratio_prefetch: Determine max Vratio for prefetch by driver policy
3386  *
3387  * @dc: Current DC state
3388  * @context: New DC state to be programmed
3389  *
3390  * Return: Max vratio for prefetch
3391  */
3392 double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *context)
3393 {
3394         double max_vratio_pre = __DML_MAX_BW_RATIO_PRE__; // Default value is 4
3395         int i;
3396
3397         /* For single display MPO configs, allow the max vratio to be 8
3398          * if any plane is YUV420 format
3399          */
3400         if (context->stream_count == 1 && context->stream_status[0].plane_count > 1) {
3401                 for (i = 0; i < context->stream_status[0].plane_count; i++) {
3402                         if (context->stream_status[0].plane_states[i]->format == SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr ||
3403                                         context->stream_status[0].plane_states[i]->format == SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb) {
3404                                 max_vratio_pre = __DML_MAX_VRATIO_PRE__;
3405                         }
3406                 }
3407         }
3408         return max_vratio_pre;
3409 }
3410
3411 /**
3412  * dcn32_assign_fpo_vactive_candidate - Assign the FPO stream candidate for FPO + VActive case
3413  *
3414  * This function chooses the FPO candidate stream for FPO + VActive cases (2 stream config).
3415  * For FPO + VAtive cases, the assumption is that one display has ActiveMargin > 0, and the
3416  * other display has ActiveMargin <= 0. This function will choose the pipe/stream that has
3417  * ActiveMargin <= 0 to be the FPO stream candidate if found.
3418  *
3419  *
3420  * @dc: current dc state
3421  * @context: new dc state
3422  * @fpo_candidate_stream: pointer to FPO stream candidate if one is found
3423  *
3424  * Return: void
3425  */
3426 void dcn32_assign_fpo_vactive_candidate(struct dc *dc, const struct dc_state *context, struct dc_stream_state **fpo_candidate_stream)
3427 {
3428         unsigned int i, pipe_idx;
3429         const struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
3430
3431         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3432                 const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3433
3434                 if (!pipe->stream)
3435                         continue;
3436
3437                 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0) {
3438                         *fpo_candidate_stream = pipe->stream;
3439                         break;
3440                 }
3441                 pipe_idx++;
3442         }
3443 }
3444
3445 /**
3446  * dcn32_find_vactive_pipe - Determines if the config has a pipe that can switch in VACTIVE
3447  *
3448  * @dc: current dc state
3449  * @context: new dc state
3450  * @vactive_margin_req_us: The vactive marign required for a vactive pipe to be considered "found"
3451  *
3452  * Return: True if VACTIVE display is found, false otherwise
3453  */
3454 bool dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, uint32_t vactive_margin_req_us)
3455 {
3456         unsigned int i, pipe_idx;
3457         const struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
3458         bool vactive_found = false;
3459         unsigned int blank_us = 0;
3460
3461         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3462                 const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3463
3464                 if (!pipe->stream)
3465                         continue;
3466
3467                 blank_us = ((pipe->stream->timing.v_total - pipe->stream->timing.v_addressable) * pipe->stream->timing.h_total /
3468                                 (double)(pipe->stream->timing.pix_clk_100hz * 100)) * 1000000;
3469                 if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] >= vactive_margin_req_us &&
3470                                 !(pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed) && blank_us < dc->debug.fpo_vactive_max_blank_us) {
3471                         vactive_found = true;
3472                         break;
3473                 }
3474                 pipe_idx++;
3475         }
3476         return vactive_found;
3477 }
3478
3479 void dcn32_set_clock_limits(const struct _vcs_dpi_soc_bounding_box_st *soc_bb)
3480 {
3481         dc_assert_fp_enabled();
3482         dcn3_2_soc.clock_limits[0].dcfclk_mhz = 1200.0;
3483 }
3484
3485 void dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context)
3486 {
3487         // WA: restrict FPO and SubVP to use first non-strobe mode (DCN32 BW issue)
3488         if ((context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dcn32_subvp_in_use(dc, context)) &&
3489                         dc->dml.soc.num_chans <= 8) {
3490                 int num_mclk_levels = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels;
3491
3492                 if (context->bw_ctx.dml.vba.DRAMSpeed <= dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 16 &&
3493                                 num_mclk_levels > 1) {
3494                         context->bw_ctx.dml.vba.DRAMSpeed = dc->clk_mgr->bw_params->clk_table.entries[1].memclk_mhz * 16;
3495                         context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
3496                 }
3497         }
3498 }