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26 #ifndef __DCN31_FPU_H__
27 #define __DCN31_FPU_H__
29 #define DCN3_1_DEFAULT_DET_SIZE 384
30 #define DCN3_15_DEFAULT_DET_SIZE 192
31 #define DCN3_15_MIN_COMPBUF_SIZE_KB 128
32 #define DCN3_16_DEFAULT_DET_SIZE 192
34 void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
37 void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
38 void dcn315_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
40 void dcn31_calculate_wm_and_dlg_fp(
41 struct dc *dc, struct dc_state *context,
42 display_e2e_pipe_params_st *pipes,
46 void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
47 void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
48 void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
49 int dcn_get_max_non_odm_pix_rate_100hz(struct _vcs_dpi_soc_bounding_box_st *soc);
51 int dcn31x_populate_dml_pipes_from_context(struct dc *dc,
52 struct dc_state *context,
53 display_e2e_pipe_params_st *pipes,
55 #endif /* __DCN31_FPU_H__*/