drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 // header file of functions being implemented
  27 #include "dcn32/dcn32_resource.h"
  28 #include "dcn20/dcn20_resource.h"
  29 #include "dml/dcn32/display_mode_vba_util_32.h"
  30 #include "dml/dcn32/dcn32_fpu.h"
  31 #include "dc_state_priv.h"
  32
  33 static bool is_dual_plane(enum surface_pixel_format format)
  34 {
  35         return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
  36 }
  37
  38
  39 uint32_t dcn32_helper_mall_bytes_to_ways(
  40                 struct dc *dc,
  41                 uint32_t total_size_in_mall_bytes)
  42 {
  43         uint32_t cache_lines_used, lines_per_way, total_cache_lines, num_ways;
  44
  45         /* add 2 lines for worst case alignment */
  46         cache_lines_used = total_size_in_mall_bytes / dc->caps.cache_line_size + 2;
  47
  48         total_cache_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size;
  49         lines_per_way = total_cache_lines / dc->caps.cache_num_ways;
  50         num_ways = cache_lines_used / lines_per_way;
  51         if (cache_lines_used % lines_per_way > 0)
  52                 num_ways++;
  53
  54         return num_ways;
  55 }
  56
  57 uint32_t dcn32_helper_calculate_mall_bytes_for_cursor(
  58                 struct dc *dc,
  59                 struct pipe_ctx *pipe_ctx,
  60                 bool ignore_cursor_buf)
  61 {
  62         struct hubp *hubp = pipe_ctx->plane_res.hubp;
  63         uint32_t cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;
  64         uint32_t cursor_mall_size_bytes = 0;
  65
  66         switch (pipe_ctx->stream->cursor_attributes.color_format) {
  67         case CURSOR_MODE_MONO:
  68                 cursor_size /= 2;
  69                 break;
  70         case CURSOR_MODE_COLOR_1BIT_AND:
  71         case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
  72         case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
  73                 cursor_size *= 4;
  74                 break;
  75
  76         case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
  77         case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
  78                 cursor_size *= 8;
  79                 break;
  80         }
  81
  82         /* only count if cursor is enabled, and if additional allocation needed outside of the
  83          * DCN cursor buffer
  84          */
  85         if (pipe_ctx->stream->cursor_position.enable && (ignore_cursor_buf ||
  86                         cursor_size > 16384)) {
  87                 /* cursor_num_mblk = CEILING(num_cursors*cursor_width*cursor_width*cursor_Bpe/mblk_bytes, 1)
  88                  * Note: add 1 mblk in case of cursor misalignment
  89                  */
  90                 cursor_mall_size_bytes = ((cursor_size + DCN3_2_MALL_MBLK_SIZE_BYTES - 1) /
  91                                 DCN3_2_MALL_MBLK_SIZE_BYTES + 1) * DCN3_2_MALL_MBLK_SIZE_BYTES;
  92         }
  93
  94         return cursor_mall_size_bytes;
  95 }
  96
  97 /**
  98  * dcn32_helper_calculate_num_ways_for_subvp(): Calculate number of ways needed for SubVP
  99  *
 100  * Gets total allocation required for the phantom viewport calculated by DML in bytes and
 101  * converts to number of cache ways.
 102  *
 103  * @dc: current dc state
 104  * @context: new dc state
 105  *
 106  * Return: number of ways required for SubVP
 107  */
 108 uint32_t dcn32_helper_calculate_num_ways_for_subvp(
 109                 struct dc *dc,
 110                 struct dc_state *context)
 111 {
 112         if (context->bw_ctx.bw.dcn.mall_subvp_size_bytes > 0) {
 113                 if (dc->debug.force_subvp_num_ways) {
 114                         return dc->debug.force_subvp_num_ways;
 115                 } else {
 116                         return dcn32_helper_mall_bytes_to_ways(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes);
 117                 }
 118         } else {
 119                 return 0;
 120         }
 121 }
 122
 123 void dcn32_merge_pipes_for_subvp(struct dc *dc,
 124                 struct dc_state *context)
 125 {
 126         uint32_t i;
 127
 128         /* merge pipes if necessary */
 129         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 130                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 131
 132                 // For now merge all pipes for SubVP since pipe split case isn't supported yet
 133
 134                 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
 135                 if (pipe->prev_odm_pipe) {
 136                         /*split off odm pipe*/
 137                         pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
 138                         if (pipe->next_odm_pipe)
 139                                 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
 140
 141                         pipe->bottom_pipe = NULL;
 142                         pipe->next_odm_pipe = NULL;
 143                         pipe->plane_state = NULL;
 144                         pipe->stream = NULL;
 145                         pipe->top_pipe = NULL;
 146                         pipe->prev_odm_pipe = NULL;
 147                         if (pipe->stream_res.dsc)
 148                                 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
 149                         memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
 150                         memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
 151                 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
 152                         struct pipe_ctx *top_pipe = pipe->top_pipe;
 153                         struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
 154
 155                         top_pipe->bottom_pipe = bottom_pipe;
 156                         if (bottom_pipe)
 157                                 bottom_pipe->top_pipe = top_pipe;
 158
 159                         pipe->top_pipe = NULL;
 160                         pipe->bottom_pipe = NULL;
 161                         pipe->plane_state = NULL;
 162                         pipe->stream = NULL;
 163                         memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
 164                         memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
 165                 }
 166         }
 167 }
 168
 169 bool dcn32_all_pipes_have_stream_and_plane(struct dc *dc,
 170                 struct dc_state *context)
 171 {
 172         uint32_t i;
 173
 174         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 175                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 176
 177                 if (!pipe->stream)
 178                         continue;
 179
 180                 if (!pipe->plane_state)
 181                         return false;
 182         }
 183         return true;
 184 }
 185
 186 bool dcn32_mpo_in_use(struct dc_state *context)
 187 {
 188         uint32_t i;
 189
 190         for (i = 0; i < context->stream_count; i++) {
 191                 if (context->stream_status[i].plane_count > 1)
 192                         return true;
 193         }
 194         return false;
 195 }
 196
 197
 198 bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context)
 199 {
 200         uint32_t i;
 201
 202         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 203                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 204
 205                 if (!pipe->stream)
 206                         continue;
 207
 208                 if (pipe->plane_state && pipe->plane_state->rotation != ROTATION_ANGLE_0)
 209                         return true;
 210         }
 211         return false;
 212 }
 213
 214 bool dcn32_is_center_timing(struct pipe_ctx *pipe)
 215 {
 216         bool is_center_timing = false;
 217
 218         if (pipe->stream) {
 219                 if (pipe->stream->timing.v_addressable != pipe->stream->dst.height ||
 220                                 pipe->stream->timing.v_addressable != pipe->stream->src.height) {
 221                         is_center_timing = true;
 222                 }
 223         }
 224
 225         if (pipe->plane_state) {
 226                 if (pipe->stream->timing.v_addressable != pipe->plane_state->dst_rect.height &&
 227                                 pipe->stream->timing.v_addressable != pipe->plane_state->src_rect.height) {
 228                         is_center_timing = true;
 229                 }
 230         }
 231
 232         return is_center_timing;
 233 }
 234
 235 bool dcn32_is_psr_capable(struct pipe_ctx *pipe)
 236 {
 237         bool psr_capable = false;
 238
 239         if (pipe->stream && pipe->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) {
 240                 psr_capable = true;
 241         }
 242         return psr_capable;
 243 }
 244
 245 static void override_det_for_subvp(struct dc *dc, struct dc_state *context, uint8_t pipe_segments[])
 246 {
 247         uint32_t i;
 248         uint8_t fhd_count = 0;
 249         uint8_t subvp_high_refresh_count = 0;
 250         uint8_t stream_count = 0;
 251
 252         // Do not override if a stream has multiple planes
 253         for (i = 0; i < context->stream_count; i++) {
 254                 if (context->stream_status[i].plane_count > 1)
 255                         return;
 256
 257                 if (dc_state_get_stream_subvp_type(context, context->streams[i]) != SUBVP_PHANTOM)
 258                         stream_count++;
 259         }
 260
 261         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 262                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 263
 264                 if (pipe_ctx->stream && pipe_ctx->plane_state && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {
 265                         if (dcn32_allow_subvp_high_refresh_rate(dc, context, pipe_ctx)) {
 266
 267                                 if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 1920) {
 268                                         fhd_count++;
 269                                 }
 270                                 subvp_high_refresh_count++;
 271                         }
 272                 }
 273         }
 274
 275         if (stream_count == 2 && subvp_high_refresh_count == 2 && fhd_count == 1) {
 276                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
 277                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 278
 279                         if (pipe_ctx->stream && pipe_ctx->plane_state && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {
 280                                 if (pipe_ctx->stream->timing.v_addressable == 1080 && pipe_ctx->stream->timing.h_addressable == 1920) {
 281                                         if (pipe_segments[i] > 4)
 282                                                 pipe_segments[i] = 4;
 283                                 }
 284                         }
 285                 }
 286         }
 287 }
 288
 289 /**
 290  * dcn32_determine_det_override(): Determine DET allocation for each pipe
 291  *
 292  * This function determines how much DET to allocate for each pipe. The total number of
 293  * DET segments will be split equally among each of the streams, and after that the DET
 294  * segments per stream will be split equally among the planes for the given stream.
 295  *
 296  * If there is a plane that's driven by more than 1 pipe (i.e. pipe split), then the
 297  * number of DET for that given plane will be split among the pipes driving that plane.
 298  *
 299  *
 300  * High level algorithm:
 301  * 1. Split total DET among number of streams
 302  * 2. For each stream, split DET among the planes
 303  * 3. For each plane, check if there is a pipe split. If yes, split the DET allocation
 304  *    among those pipes.
 305  * 4. Assign the DET override to the DML pipes.
 306  *
 307  * @dc: Current DC state
 308  * @context: New DC state to be programmed
 309  * @pipes: Array of DML pipes
 310  *
 311  * Return: void
 312  */
 313 void dcn32_determine_det_override(struct dc *dc,
 314                 struct dc_state *context,
 315                 display_e2e_pipe_params_st *pipes)
 316 {
 317         uint32_t i, j, k;
 318         uint8_t pipe_plane_count, stream_segments, plane_segments, pipe_segments[MAX_PIPES] = {0};
 319         uint8_t pipe_counted[MAX_PIPES] = {0};
 320         uint8_t pipe_cnt = 0;
 321         struct dc_plane_state *current_plane = NULL;
 322         uint8_t stream_count = 0;
 323
 324         for (i = 0; i < context->stream_count; i++) {
 325                 /* Don't count SubVP streams for DET allocation */
 326                 if (dc_state_get_stream_subvp_type(context, context->streams[i]) != SUBVP_PHANTOM)
 327                         stream_count++;
 328         }
 329
 330         if (stream_count > 0) {
 331                 stream_segments = 18 / stream_count;
 332                 for (i = 0; i < context->stream_count; i++) {
 333                         if (dc_state_get_stream_subvp_type(context, context->streams[i]) == SUBVP_PHANTOM)
 334                                 continue;
 335
 336                         if (context->stream_status[i].plane_count > 0)
 337                                 plane_segments = stream_segments / context->stream_status[i].plane_count;
 338                         else
 339                                 plane_segments = stream_segments;
 340                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
 341                                 pipe_plane_count = 0;
 342                                 if (context->res_ctx.pipe_ctx[j].stream == context->streams[i] &&
 343                                                 pipe_counted[j] != 1) {
 344                                         /* Note: pipe_plane_count indicates the number of pipes to be used for a
 345                                          * given plane. e.g. pipe_plane_count = 1 means single pipe (i.e. not split),
 346                                          * pipe_plane_count = 2 means 2:1 split, etc.
 347                                          */
 348                                         pipe_plane_count++;
 349                                         pipe_counted[j] = 1;
 350                                         current_plane = context->res_ctx.pipe_ctx[j].plane_state;
 351                                         for (k = 0; k < dc->res_pool->pipe_count; k++) {
 352                                                 if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] &&
 353                                                                 context->res_ctx.pipe_ctx[k].plane_state == current_plane) {
 354                                                         pipe_plane_count++;
 355                                                         pipe_counted[k] = 1;
 356                                                 }
 357                                         }
 358
 359                                         pipe_segments[j] = plane_segments / pipe_plane_count;
 360                                         for (k = 0; k < dc->res_pool->pipe_count; k++) {
 361                                                 if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] &&
 362                                                                 context->res_ctx.pipe_ctx[k].plane_state == current_plane) {
 363                                                         pipe_segments[k] = plane_segments / pipe_plane_count;
 364                                                 }
 365                                         }
 366                                 }
 367                         }
 368                 }
 369
 370                 override_det_for_subvp(dc, context, pipe_segments);
 371                 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
 372                         if (!context->res_ctx.pipe_ctx[i].stream)
 373                                 continue;
 374                         pipes[pipe_cnt].pipe.src.det_size_override = pipe_segments[i] * DCN3_2_DET_SEG_SIZE;
 375                         pipe_cnt++;
 376                 }
 377         } else {
 378                 for (i = 0; i < dc->res_pool->pipe_count; i++)
 379                         pipes[i].pipe.src.det_size_override = 4 * DCN3_2_DET_SEG_SIZE; //DCN3_2_DEFAULT_DET_SIZE
 380         }
 381 }
 382
 383 void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context,
 384         display_e2e_pipe_params_st *pipes)
 385 {
 386         int i, pipe_cnt;
 387         struct resource_context *res_ctx = &context->res_ctx;
 388         struct pipe_ctx *pipe;
 389         bool disable_unbounded_requesting = dc->debug.disable_z9_mpc || dc->debug.disable_unbounded_requesting;
 390
 391         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
 392
 393                 if (!res_ctx->pipe_ctx[i].stream)
 394                         continue;
 395
 396                 pipe = &res_ctx->pipe_ctx[i];
 397                 pipe_cnt++;
 398         }
 399
 400         /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all
 401          * the DET available for each pipe). Use the DET override input to maintain our driver
 402          * policy.
 403          */
 404         if (pipe_cnt == 1) {
 405                 pipes[0].pipe.src.det_size_override = DCN3_2_MAX_DET_SIZE;
 406                 if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
 407                         if (!is_dual_plane(pipe->plane_state->format)) {
 408                                 pipes[0].pipe.src.det_size_override = DCN3_2_DEFAULT_DET_SIZE;
 409                                 pipes[0].pipe.src.unbounded_req_mode = true;
 410                                 if (pipe->plane_state->src_rect.width >= 5120 &&
 411                                         pipe->plane_state->src_rect.height >= 2880)
 412                                         pipes[0].pipe.src.det_size_override = 320; // 5K or higher
 413                         }
 414                 }
 415         } else
 416                 dcn32_determine_det_override(dc, context, pipes);
 417 }
 418
 419 #define MAX_STRETCHED_V_BLANK 1000 // in micro-seconds (must ensure to match value in FW)
 420 /*
 421  * Scaling factor for v_blank stretch calculations considering timing in
 422  * micro-seconds and pixel clock in 100hz.
 423  * Note: the parenthesis are necessary to ensure the correct order of
 424  * operation where V_SCALE is used.
 425  */
 426 #define V_SCALE (10000 / MAX_STRETCHED_V_BLANK)
 427
 428 static int get_frame_rate_at_max_stretch_100hz(
 429                 struct dc_stream_state *fpo_candidate_stream,
 430                 uint32_t fpo_vactive_margin_us)
 431 {
 432         struct dc_crtc_timing *timing = NULL;
 433         uint32_t sec_per_100_lines;
 434         uint32_t max_v_blank;
 435         uint32_t curr_v_blank;
 436         uint32_t v_stretch_max;
 437         uint32_t stretched_frame_pix_cnt;
 438         uint32_t scaled_stretched_frame_pix_cnt;
 439         uint32_t scaled_refresh_rate;
 440         uint32_t v_scale;
 441
 442         if (fpo_candidate_stream == NULL)
 443                 return 0;
 444
 445         /* check if refresh rate at least 120hz */
 446         timing = &fpo_candidate_stream->timing;
 447         if (timing == NULL)
 448                 return 0;
 449
 450         v_scale = 10000 / (MAX_STRETCHED_V_BLANK + fpo_vactive_margin_us);
 451
 452         sec_per_100_lines = timing->pix_clk_100hz / timing->h_total + 1;
 453         max_v_blank = sec_per_100_lines / v_scale + 1;
 454         curr_v_blank = timing->v_total - timing->v_addressable;
 455         v_stretch_max = (max_v_blank > curr_v_blank) ? (max_v_blank - curr_v_blank) : (0);
 456         stretched_frame_pix_cnt = (v_stretch_max + timing->v_total) * timing->h_total;
 457         scaled_stretched_frame_pix_cnt = stretched_frame_pix_cnt / 10000;
 458         scaled_refresh_rate = (timing->pix_clk_100hz) / scaled_stretched_frame_pix_cnt + 1;
 459
 460         return scaled_refresh_rate;
 461
 462 }
 463
 464 static bool is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(
 465                 struct dc_stream_state *fpo_candidate_stream, uint32_t fpo_vactive_margin_us)
 466 {
 467         int refresh_rate_max_stretch_100hz;
 468         int min_refresh_100hz;
 469
 470         if (fpo_candidate_stream == NULL)
 471                 return false;
 472
 473         refresh_rate_max_stretch_100hz = get_frame_rate_at_max_stretch_100hz(fpo_candidate_stream, fpo_vactive_margin_us);
 474         min_refresh_100hz = fpo_candidate_stream->timing.min_refresh_in_uhz / 10000;
 475
 476         if (refresh_rate_max_stretch_100hz < min_refresh_100hz)
 477                 return false;
 478
 479         return true;
 480 }
 481
 482 static int get_refresh_rate(struct dc_stream_state *fpo_candidate_stream)
 483 {
 484         int refresh_rate = 0;
 485         int h_v_total = 0;
 486         struct dc_crtc_timing *timing = NULL;
 487
 488         if (fpo_candidate_stream == NULL)
 489                 return 0;
 490
 491         /* check if refresh rate at least 120hz */
 492         timing = &fpo_candidate_stream->timing;
 493         if (timing == NULL)
 494                 return 0;
 495
 496         h_v_total = timing->h_total * timing->v_total;
 497         if (h_v_total == 0)
 498                 return 0;
 499
 500         refresh_rate = ((timing->pix_clk_100hz * 100) / (h_v_total)) + 1;
 501         return refresh_rate;
 502 }
 503
 504 /**
 505  * dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch() - Determines if config can
 506  *                                                                  support FPO
 507  *
 508  * @dc: current dc state
 509  * @context: new dc state
 510  *
 511  * Return: Pointer to FPO stream candidate if config can support FPO, otherwise NULL
 512  */
 513 struct dc_stream_state *dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)
 514 {
 515         int refresh_rate = 0;
 516         const int minimum_refreshrate_supported = 120;
 517         struct dc_stream_state *fpo_candidate_stream = NULL;
 518         bool is_fpo_vactive = false;
 519         uint32_t fpo_vactive_margin_us = 0;
 520         struct dc_stream_status *fpo_stream_status = NULL;
 521
 522         if (context == NULL)
 523                 return NULL;
 524
 525         if (dc->debug.disable_fams)
 526                 return NULL;
 527
 528         if (!dc->caps.dmub_caps.mclk_sw)
 529                 return NULL;
 530
 531         if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down)
 532                 return NULL;
 533
 534         /* For FPO we can support up to 2 display configs if:
 535          * - first display uses FPO
 536          * - Second display switches in VACTIVE */
 537         if (context->stream_count > 2)
 538                 return NULL;
 539         else if (context->stream_count == 2) {
 540                 DC_FP_START();
 541                 dcn32_assign_fpo_vactive_candidate(dc, context, &fpo_candidate_stream);
 542                 DC_FP_END();
 543                 if (fpo_candidate_stream)
 544                         fpo_stream_status = dc_state_get_stream_status(context, fpo_candidate_stream);
 545                 DC_FP_START();
 546                 is_fpo_vactive = dcn32_find_vactive_pipe(dc, context, dc->debug.fpo_vactive_min_active_margin_us);
 547                 DC_FP_END();
 548                 if (!is_fpo_vactive || dc->debug.disable_fpo_vactive)
 549                         return NULL;
 550         } else {
 551                 fpo_candidate_stream = context->streams[0];
 552                 if (fpo_candidate_stream)
 553                         fpo_stream_status = dc_state_get_stream_status(context, fpo_candidate_stream);
 554         }
 555
 556         /* In DCN32/321, FPO uses per-pipe P-State force.
 557          * If there's no planes, HUBP is power gated and
 558          * therefore programming UCLK_PSTATE_FORCE does
 559          * nothing (P-State will always be asserted naturally
 560          * on a pipe that has HUBP power gated. Therefore we
 561          * only want to enable FPO if the FPO pipe has both
 562          * a stream and a plane.
 563          */
 564         if (!fpo_candidate_stream || !fpo_stream_status || fpo_stream_status->plane_count == 0)
 565                 return NULL;
 566
 567         if (fpo_candidate_stream->sink->edid_caps.panel_patch.disable_fams)
 568                 return NULL;
 569
 570         refresh_rate = get_refresh_rate(fpo_candidate_stream);
 571         if (refresh_rate < minimum_refreshrate_supported)
 572                 return NULL;
 573
 574         fpo_vactive_margin_us = is_fpo_vactive ? dc->debug.fpo_vactive_margin_us : 0; // For now hardcode the FPO + Vactive stretch margin to be 2000us
 575         if (!is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(fpo_candidate_stream, fpo_vactive_margin_us))
 576                 return NULL;
 577
 578         if (!fpo_candidate_stream->allow_freesync)
 579                 return NULL;
 580
 581         if (fpo_candidate_stream->vrr_active_variable && dc->debug.disable_fams_gaming)
 582                 return NULL;
 583
 584         return fpo_candidate_stream;
 585 }
 586
 587 bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int width, unsigned int height)
 588 {
 589         bool is_native_scaling = false;
 590
 591         if (pipe->stream->timing.h_addressable == width &&
 592                         pipe->stream->timing.v_addressable == height &&
 593                         pipe->plane_state->src_rect.width == width &&
 594                         pipe->plane_state->src_rect.height == height &&
 595                         pipe->plane_state->dst_rect.width == width &&
 596                         pipe->plane_state->dst_rect.height == height)
 597                 is_native_scaling = true;
 598
 599         return is_native_scaling;
 600 }
 601
 602 /**
 603  * disallow_subvp_in_active_plus_blank() - Function to determine disallowed subvp + drr/vblank configs
 604  *
 605  * @pipe: subvp pipe to be used for the subvp + drr/vblank config
 606  *
 607  * Since subvp is being enabled on more configs (such as 1080p60), we want
 608  * to explicitly block any configs that we don't want to enable. We do not
 609  * want to enable any 1080p60 (SubVP) + drr / vblank configs since these
 610  * are already convered by FPO.
 611  *
 612  * Return: True if disallowed, false otherwise
 613  */
 614 static bool disallow_subvp_in_active_plus_blank(struct pipe_ctx *pipe)
 615 {
 616         bool disallow = false;
 617
 618         if (resource_is_pipe_type(pipe, OPP_HEAD) &&
 619                         resource_is_pipe_type(pipe, DPP_PIPE)) {
 620                 if (pipe->stream->timing.v_addressable == 1080 && pipe->stream->timing.h_addressable == 1920)
 621                         disallow = true;
 622         }
 623         return disallow;
 624 }
 625
 626 /**
 627  * dcn32_subvp_drr_admissable() - Determine if SubVP + DRR config is admissible
 628  *
 629  * @dc: Current DC state
 630  * @context: New DC state to be programmed
 631  *
 632  * SubVP + DRR is admissible under the following conditions:
 633  * - Config must have 2 displays (i.e., 2 non-phantom master pipes)
 634  * - One display is SubVP
 635  * - Other display must have Freesync enabled
 636  * - The potential DRR display must not be PSR capable
 637  *
 638  * Return: True if admissible, false otherwise
 639  */
 640 bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context)
 641 {
 642         bool result = false;
 643         uint32_t i;
 644         uint8_t subvp_count = 0;
 645         uint8_t non_subvp_pipes = 0;
 646         bool drr_pipe_found = false;
 647         bool drr_psr_capable = false;
 648         uint64_t refresh_rate = 0;
 649         bool subvp_disallow = false;
 650
 651         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 652                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 653                 enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);
 654
 655                 if (resource_is_pipe_type(pipe, OPP_HEAD) &&
 656                                 resource_is_pipe_type(pipe, DPP_PIPE)) {
 657                         if (pipe_mall_type == SUBVP_MAIN) {
 658                                 subvp_count++;
 659
 660                                 subvp_disallow |= disallow_subvp_in_active_plus_blank(pipe);
 661                                 refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +
 662                                         pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1);
 663                                 refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
 664                                 refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);
 665                         }
 666                         if (pipe_mall_type == SUBVP_NONE) {
 667                                 non_subvp_pipes++;
 668                                 drr_psr_capable = (drr_psr_capable || dcn32_is_psr_capable(pipe));
 669                                 if (pipe->stream->ignore_msa_timing_param &&
 670                                                 (pipe->stream->allow_freesync || pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) {
 671                                         drr_pipe_found = true;
 672                                 }
 673                         }
 674                 }
 675         }
 676
 677         if (subvp_count == 1 && !subvp_disallow && non_subvp_pipes == 1 && drr_pipe_found && !drr_psr_capable &&
 678                 ((uint32_t)refresh_rate < 120))
 679                 result = true;
 680
 681         return result;
 682 }
 683
 684 /**
 685  * dcn32_subvp_vblank_admissable() - Determine if SubVP + Vblank config is admissible
 686  *
 687  * @dc: Current DC state
 688  * @context: New DC state to be programmed
 689  * @vlevel: Voltage level calculated by DML
 690  *
 691  * SubVP + Vblank is admissible under the following conditions:
 692  * - Config must have 2 displays (i.e., 2 non-phantom master pipes)
 693  * - One display is SubVP
 694  * - Other display must not have Freesync capability
 695  * - DML must have output DRAM clock change support as SubVP + Vblank
 696  * - The potential vblank display must not be PSR capable
 697  *
 698  * Return: True if admissible, false otherwise
 699  */
 700 bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel)
 701 {
 702         bool result = false;
 703         uint32_t i;
 704         uint8_t subvp_count = 0;
 705         uint8_t non_subvp_pipes = 0;
 706         bool drr_pipe_found = false;
 707         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
 708         bool vblank_psr_capable = false;
 709         uint64_t refresh_rate = 0;
 710         bool subvp_disallow = false;
 711
 712         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 713                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 714                 enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);
 715
 716                 if (resource_is_pipe_type(pipe, OPP_HEAD) &&
 717                                 resource_is_pipe_type(pipe, DPP_PIPE)) {
 718                         if (pipe_mall_type == SUBVP_MAIN) {
 719                                 subvp_count++;
 720
 721                                 subvp_disallow |= disallow_subvp_in_active_plus_blank(pipe);
 722                                 refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +
 723                                         pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1);
 724                                 refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
 725                                 refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);
 726                         }
 727                         if (pipe_mall_type == SUBVP_NONE) {
 728                                 non_subvp_pipes++;
 729                                 vblank_psr_capable = (vblank_psr_capable || dcn32_is_psr_capable(pipe));
 730                                 if (pipe->stream->ignore_msa_timing_param &&
 731                                                 (pipe->stream->allow_freesync || pipe->stream->vrr_active_variable || pipe->stream->vrr_active_fixed)) {
 732                                         drr_pipe_found = true;
 733                                 }
 734                         }
 735                 }
 736         }
 737
 738         if (subvp_count == 1 && non_subvp_pipes == 1 && !drr_pipe_found && !vblank_psr_capable &&
 739                 ((uint32_t)refresh_rate < 120) && !subvp_disallow &&
 740                 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp)
 741                 result = true;
 742
 743         return result;
 744 }
 745
 746 void dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, struct dc_state *context,
 747                 display_e2e_pipe_params_st *pipes)
 748 {
 749         int i, pipe_cnt;
 750         struct resource_context *res_ctx = &context->res_ctx;
 751         struct pipe_ctx *pipe = NULL;
 752
 753         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
 754                 int odm_slice_count = 0;
 755
 756                 if (!res_ctx->pipe_ctx[i].stream)
 757                         continue;
 758                 pipe = &res_ctx->pipe_ctx[i];
 759                 odm_slice_count = resource_get_odm_slice_count(pipe);
 760
 761                 if (odm_slice_count == 1)
 762                         pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;
 763                 else if (odm_slice_count == 2)
 764                         pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;
 765                 else if (odm_slice_count == 4)
 766                         pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_4to1;
 767
 768                 pipe_cnt++;
 769         }
 770 }