drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright 2022 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27 #include "dm_services.h"
  28 #include "dc.h"
  29
  30 #include "dcn32_init.h"
  31
  32 #include "resource.h"
  33 #include "include/irq_service_interface.h"
  34 #include "dcn32_resource.h"
  35
  36 #include "dcn20/dcn20_resource.h"
  37 #include "dcn30/dcn30_resource.h"
  38
  39 #include "dcn10/dcn10_ipp.h"
  40 #include "dcn30/dcn30_hubbub.h"
  41 #include "dcn31/dcn31_hubbub.h"
  42 #include "dcn32/dcn32_hubbub.h"
  43 #include "dcn32/dcn32_mpc.h"
  44 #include "dcn32_hubp.h"
  45 #include "irq/dcn32/irq_service_dcn32.h"
  46 #include "dcn32/dcn32_dpp.h"
  47 #include "dcn32/dcn32_optc.h"
  48 #include "dcn20/dcn20_hwseq.h"
  49 #include "dcn30/dcn30_hwseq.h"
  50 #include "dce110/dce110_hw_sequencer.h"
  51 #include "dcn30/dcn30_opp.h"
  52 #include "dcn20/dcn20_dsc.h"
  53 #include "dcn30/dcn30_vpg.h"
  54 #include "dcn30/dcn30_afmt.h"
  55 #include "dcn30/dcn30_dio_stream_encoder.h"
  56 #include "dcn32/dcn32_dio_stream_encoder.h"
  57 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
  58 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
  59 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
  60 #include "dc_link_dp.h"
  61 #include "dcn31/dcn31_apg.h"
  62 #include "dcn31/dcn31_dio_link_encoder.h"
  63 #include "dcn32/dcn32_dio_link_encoder.h"
  64 #include "dce/dce_clock_source.h"
  65 #include "dce/dce_audio.h"
  66 #include "dce/dce_hwseq.h"
  67 #include "clk_mgr.h"
  68 #include "virtual/virtual_stream_encoder.h"
  69 #include "dml/display_mode_vba.h"
  70 #include "dcn32/dcn32_dccg.h"
  71 #include "dcn10/dcn10_resource.h"
  72 #include "dc_link_ddc.h"
  73 #include "dcn31/dcn31_panel_cntl.h"
  74
  75 #include "dcn30/dcn30_dwb.h"
  76 #include "dcn32/dcn32_mmhubbub.h"
  77
  78 #include "dcn/dcn_3_2_0_offset.h"
  79 #include "dcn/dcn_3_2_0_sh_mask.h"
  80 #include "nbio/nbio_4_3_0_offset.h"
  81
  82 #include "reg_helper.h"
  83 #include "dce/dmub_abm.h"
  84 #include "dce/dmub_psr.h"
  85 #include "dce/dce_aux.h"
  86 #include "dce/dce_i2c.h"
  87
  88 #include "dml/dcn30/display_mode_vba_30.h"
  89 #include "vm_helper.h"
  90 #include "dcn20/dcn20_vmid.h"
  91 #include "dml/dcn32/dcn32_fpu.h"
  92
  93 #define DCN_BASE__INST0_SEG1                       0x000000C0
  94 #define DCN_BASE__INST0_SEG2                       0x000034C0
  95 #define DCN_BASE__INST0_SEG3                       0x00009000
  96 #define NBIO_BASE__INST0_SEG1                      0x00000014
  97
  98 #define MAX_INSTANCE                                        6
  99 #define MAX_SEGMENT                                         6
 100
 101 struct IP_BASE_INSTANCE {
 102         unsigned int segment[MAX_SEGMENT];
 103 };
 104
 105 struct IP_BASE {
 106         struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
 107 };
 108
 109 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
 110                                         { { 0, 0, 0, 0, 0, 0 } },
 111                                         { { 0, 0, 0, 0, 0, 0 } },
 112                                         { { 0, 0, 0, 0, 0, 0 } },
 113                                         { { 0, 0, 0, 0, 0, 0 } },
 114                                         { { 0, 0, 0, 0, 0, 0 } } } };
 115
 116 #define DC_LOGGER_INIT(logger)
 117
 118 enum dcn32_clk_src_array_id {
 119         DCN32_CLK_SRC_PLL0,
 120         DCN32_CLK_SRC_PLL1,
 121         DCN32_CLK_SRC_PLL2,
 122         DCN32_CLK_SRC_PLL3,
 123         DCN32_CLK_SRC_PLL4,
 124         DCN32_CLK_SRC_TOTAL
 125 };
 126
 127 /* begin *********************
 128  * macros to expend register list macro defined in HW object header file
 129  */
 130
 131 /* DCN */
 132 /* TODO awful hack. fixup dcn20_dwb.h */
 133 #undef BASE_INNER
 134 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 135
 136 #define BASE(seg) BASE_INNER(seg)
 137
 138 #define SR(reg_name)\
 139                 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 140                                         reg ## reg_name
 141
 142 #define SRI(reg_name, block, id)\
 143         .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 144                                         reg ## block ## id ## _ ## reg_name
 145
 146 #define SRI2(reg_name, block, id)\
 147         .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 148                                         reg ## reg_name
 149
 150 #define SRIR(var_name, reg_name, block, id)\
 151         .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 152                                         reg ## block ## id ## _ ## reg_name
 153
 154 #define SRII(reg_name, block, id)\
 155         .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 156                                         reg ## block ## id ## _ ## reg_name
 157
 158 #define SRII_MPC_RMU(reg_name, block, id)\
 159         .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 160                                         reg ## block ## id ## _ ## reg_name
 161
 162 #define SRII_DWB(reg_name, temp_name, block, id)\
 163         .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 164                                         reg ## block ## id ## _ ## temp_name
 165
 166 #define DCCG_SRII(reg_name, block, id)\
 167         .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 168                                         reg ## block ## id ## _ ## reg_name
 169
 170 #define VUPDATE_SRII(reg_name, block, id)\
 171         .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 172                                         reg ## reg_name ## _ ## block ## id
 173
 174 /* NBIO */
 175 #define NBIO_BASE_INNER(seg) \
 176         NBIO_BASE__INST0_SEG ## seg
 177
 178 #define NBIO_BASE(seg) \
 179         NBIO_BASE_INNER(seg)
 180
 181 #define NBIO_SR(reg_name)\
 182                 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
 183                                         regBIF_BX0_ ## reg_name
 184
 185 #undef CTX
 186 #define CTX ctx
 187 #define REG(reg_name) \
 188         (DCN_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
 189
 190 static const struct bios_registers bios_regs = {
 191                 NBIO_SR(BIOS_SCRATCH_3),
 192                 NBIO_SR(BIOS_SCRATCH_6)
 193 };
 194
 195 #define clk_src_regs(index, pllid)\
 196 [index] = {\
 197         CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
 198 }
 199
 200 static const struct dce110_clk_src_regs clk_src_regs[] = {
 201         clk_src_regs(0, A),
 202         clk_src_regs(1, B),
 203         clk_src_regs(2, C),
 204         clk_src_regs(3, D),
 205         clk_src_regs(4, E)
 206 };
 207
 208 static const struct dce110_clk_src_shift cs_shift = {
 209                 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
 210 };
 211
 212 static const struct dce110_clk_src_mask cs_mask = {
 213                 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
 214 };
 215
 216 #define abm_regs(id)\
 217 [id] = {\
 218                 ABM_DCN32_REG_LIST(id)\
 219 }
 220
 221 static const struct dce_abm_registers abm_regs[] = {
 222                 abm_regs(0),
 223                 abm_regs(1),
 224                 abm_regs(2),
 225                 abm_regs(3),
 226 };
 227
 228 static const struct dce_abm_shift abm_shift = {
 229                 ABM_MASK_SH_LIST_DCN32(__SHIFT)
 230 };
 231
 232 static const struct dce_abm_mask abm_mask = {
 233                 ABM_MASK_SH_LIST_DCN32(_MASK)
 234 };
 235
 236 #define audio_regs(id)\
 237 [id] = {\
 238                 AUD_COMMON_REG_LIST(id)\
 239 }
 240
 241 static const struct dce_audio_registers audio_regs[] = {
 242         audio_regs(0),
 243         audio_regs(1),
 244         audio_regs(2),
 245         audio_regs(3),
 246         audio_regs(4)
 247 };
 248
 249 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 250                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 251                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 252                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 253
 254 static const struct dce_audio_shift audio_shift = {
 255                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 256 };
 257
 258 static const struct dce_audio_mask audio_mask = {
 259                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 260 };
 261
 262 #define vpg_regs(id)\
 263 [id] = {\
 264         VPG_DCN3_REG_LIST(id)\
 265 }
 266
 267 static const struct dcn30_vpg_registers vpg_regs[] = {
 268         vpg_regs(0),
 269         vpg_regs(1),
 270         vpg_regs(2),
 271         vpg_regs(3),
 272         vpg_regs(4),
 273         vpg_regs(5),
 274         vpg_regs(6),
 275         vpg_regs(7),
 276         vpg_regs(8),
 277         vpg_regs(9),
 278 };
 279
 280 static const struct dcn30_vpg_shift vpg_shift = {
 281         DCN3_VPG_MASK_SH_LIST(__SHIFT)
 282 };
 283
 284 static const struct dcn30_vpg_mask vpg_mask = {
 285         DCN3_VPG_MASK_SH_LIST(_MASK)
 286 };
 287
 288 #define afmt_regs(id)\
 289 [id] = {\
 290         AFMT_DCN3_REG_LIST(id)\
 291 }
 292
 293 static const struct dcn30_afmt_registers afmt_regs[] = {
 294         afmt_regs(0),
 295         afmt_regs(1),
 296         afmt_regs(2),
 297         afmt_regs(3),
 298         afmt_regs(4),
 299         afmt_regs(5)
 300 };
 301
 302 static const struct dcn30_afmt_shift afmt_shift = {
 303         DCN3_AFMT_MASK_SH_LIST(__SHIFT)
 304 };
 305
 306 static const struct dcn30_afmt_mask afmt_mask = {
 307         DCN3_AFMT_MASK_SH_LIST(_MASK)
 308 };
 309
 310 #define apg_regs(id)\
 311 [id] = {\
 312         APG_DCN31_REG_LIST(id)\
 313 }
 314
 315 static const struct dcn31_apg_registers apg_regs[] = {
 316         apg_regs(0),
 317         apg_regs(1),
 318         apg_regs(2),
 319         apg_regs(3)
 320 };
 321
 322 static const struct dcn31_apg_shift apg_shift = {
 323         DCN31_APG_MASK_SH_LIST(__SHIFT)
 324 };
 325
 326 static const struct dcn31_apg_mask apg_mask = {
 327                 DCN31_APG_MASK_SH_LIST(_MASK)
 328 };
 329
 330 #define stream_enc_regs(id)\
 331 [id] = {\
 332         SE_DCN32_REG_LIST(id)\
 333 }
 334
 335 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 336         stream_enc_regs(0),
 337         stream_enc_regs(1),
 338         stream_enc_regs(2),
 339         stream_enc_regs(3),
 340         stream_enc_regs(4)
 341 };
 342
 343 static const struct dcn10_stream_encoder_shift se_shift = {
 344                 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
 345 };
 346
 347 static const struct dcn10_stream_encoder_mask se_mask = {
 348                 SE_COMMON_MASK_SH_LIST_DCN32(_MASK)
 349 };
 350
 351
 352 #define aux_regs(id)\
 353 [id] = {\
 354         DCN2_AUX_REG_LIST(id)\
 355 }
 356
 357 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 358                 aux_regs(0),
 359                 aux_regs(1),
 360                 aux_regs(2),
 361                 aux_regs(3),
 362                 aux_regs(4)
 363 };
 364
 365 #define hpd_regs(id)\
 366 [id] = {\
 367         HPD_REG_LIST(id)\
 368 }
 369
 370 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 371                 hpd_regs(0),
 372                 hpd_regs(1),
 373                 hpd_regs(2),
 374                 hpd_regs(3),
 375                 hpd_regs(4)
 376 };
 377
 378 #define link_regs(id, phyid)\
 379 [id] = {\
 380         LE_DCN31_REG_LIST(id), \
 381         UNIPHY_DCN2_REG_LIST(phyid), \
 382         /*DPCS_DCN31_REG_LIST(id),*/ \
 383 }
 384
 385 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 386         link_regs(0, A),
 387         link_regs(1, B),
 388         link_regs(2, C),
 389         link_regs(3, D),
 390         link_regs(4, E)
 391 };
 392
 393 static const struct dcn10_link_enc_shift le_shift = {
 394         LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
 395         //DPCS_DCN31_MASK_SH_LIST(__SHIFT)
 396 };
 397
 398 static const struct dcn10_link_enc_mask le_mask = {
 399         LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
 400
 401         //DPCS_DCN31_MASK_SH_LIST(_MASK)
 402 };
 403
 404 #define hpo_dp_stream_encoder_reg_list(id)\
 405 [id] = {\
 406         DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
 407 }
 408
 409 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
 410         hpo_dp_stream_encoder_reg_list(0),
 411         hpo_dp_stream_encoder_reg_list(1),
 412         hpo_dp_stream_encoder_reg_list(2),
 413         hpo_dp_stream_encoder_reg_list(3),
 414 };
 415
 416 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
 417         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
 418 };
 419
 420 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
 421         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
 422 };
 423
 424
 425 #define hpo_dp_link_encoder_reg_list(id)\
 426 [id] = {\
 427         DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
 428         /*DCN3_1_RDPCSTX_REG_LIST(0),*/\
 429         /*DCN3_1_RDPCSTX_REG_LIST(1),*/\
 430         /*DCN3_1_RDPCSTX_REG_LIST(2),*/\
 431         /*DCN3_1_RDPCSTX_REG_LIST(3),*/\
 432         /*DCN3_1_RDPCSTX_REG_LIST(4)*/\
 433 }
 434
 435 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
 436         hpo_dp_link_encoder_reg_list(0),
 437         hpo_dp_link_encoder_reg_list(1),
 438 };
 439
 440 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
 441         DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
 442 };
 443
 444 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
 445         DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
 446 };
 447
 448 #define dpp_regs(id)\
 449 [id] = {\
 450         DPP_REG_LIST_DCN30_COMMON(id),\
 451 }
 452
 453 static const struct dcn3_dpp_registers dpp_regs[] = {
 454         dpp_regs(0),
 455         dpp_regs(1),
 456         dpp_regs(2),
 457         dpp_regs(3)
 458 };
 459
 460 static const struct dcn3_dpp_shift tf_shift = {
 461                 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT)
 462 };
 463
 464 static const struct dcn3_dpp_mask tf_mask = {
 465                 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK)
 466 };
 467
 468
 469 #define opp_regs(id)\
 470 [id] = {\
 471         OPP_REG_LIST_DCN30(id),\
 472 }
 473
 474 static const struct dcn20_opp_registers opp_regs[] = {
 475         opp_regs(0),
 476         opp_regs(1),
 477         opp_regs(2),
 478         opp_regs(3)
 479 };
 480
 481 static const struct dcn20_opp_shift opp_shift = {
 482         OPP_MASK_SH_LIST_DCN20(__SHIFT)
 483 };
 484
 485 static const struct dcn20_opp_mask opp_mask = {
 486         OPP_MASK_SH_LIST_DCN20(_MASK)
 487 };
 488
 489 #define aux_engine_regs(id)\
 490 [id] = {\
 491         AUX_COMMON_REG_LIST0(id), \
 492         .AUXN_IMPCAL = 0, \
 493         .AUXP_IMPCAL = 0, \
 494         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 495 }
 496
 497 static const struct dce110_aux_registers aux_engine_regs[] = {
 498                 aux_engine_regs(0),
 499                 aux_engine_regs(1),
 500                 aux_engine_regs(2),
 501                 aux_engine_regs(3),
 502                 aux_engine_regs(4)
 503 };
 504
 505 static const struct dce110_aux_registers_shift aux_shift = {
 506         DCN_AUX_MASK_SH_LIST(__SHIFT)
 507 };
 508
 509 static const struct dce110_aux_registers_mask aux_mask = {
 510         DCN_AUX_MASK_SH_LIST(_MASK)
 511 };
 512
 513
 514 #define dwbc_regs_dcn3(id)\
 515 [id] = {\
 516         DWBC_COMMON_REG_LIST_DCN30(id),\
 517 }
 518
 519 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 520         dwbc_regs_dcn3(0),
 521 };
 522
 523 static const struct dcn30_dwbc_shift dwbc30_shift = {
 524         DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 525 };
 526
 527 static const struct dcn30_dwbc_mask dwbc30_mask = {
 528         DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 529 };
 530
 531 #define mcif_wb_regs_dcn3(id)\
 532 [id] = {\
 533         MCIF_WB_COMMON_REG_LIST_DCN32(id),\
 534 }
 535
 536 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 537         mcif_wb_regs_dcn3(0)
 538 };
 539
 540 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 541         MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
 542 };
 543
 544 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 545         MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
 546 };
 547
 548 #define dsc_regsDCN20(id)\
 549 [id] = {\
 550         DSC_REG_LIST_DCN20(id)\
 551 }
 552
 553 static const struct dcn20_dsc_registers dsc_regs[] = {
 554         dsc_regsDCN20(0),
 555         dsc_regsDCN20(1),
 556         dsc_regsDCN20(2),
 557         dsc_regsDCN20(3)
 558 };
 559
 560 static const struct dcn20_dsc_shift dsc_shift = {
 561         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 562 };
 563
 564 static const struct dcn20_dsc_mask dsc_mask = {
 565         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 566 };
 567
 568 static const struct dcn30_mpc_registers mpc_regs = {
 569                 MPC_REG_LIST_DCN3_2(0),
 570                 MPC_REG_LIST_DCN3_2(1),
 571                 MPC_REG_LIST_DCN3_2(2),
 572                 MPC_REG_LIST_DCN3_2(3),
 573                 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 574                 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 575                 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
 576                 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
 577                 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 578 };
 579
 580 static const struct dcn30_mpc_shift mpc_shift = {
 581         MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
 582 };
 583
 584 static const struct dcn30_mpc_mask mpc_mask = {
 585         MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
 586 };
 587
 588 #define optc_regs(id)\
 589 [id] = {OPTC_COMMON_REG_LIST_DCN3_2(id)}
 590
 591 //#ifdef DIAGS_BUILD
 592 //static struct dcn_optc_registers optc_regs[] = {
 593 //#else
 594 static const struct dcn_optc_registers optc_regs[] = {
 595 //#endif
 596         optc_regs(0),
 597         optc_regs(1),
 598         optc_regs(2),
 599         optc_regs(3)
 600 };
 601
 602 static const struct dcn_optc_shift optc_shift = {
 603         OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
 604 };
 605
 606 static const struct dcn_optc_mask optc_mask = {
 607         OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
 608 };
 609
 610 #define hubp_regs(id)\
 611 [id] = {\
 612         HUBP_REG_LIST_DCN32(id)\
 613 }
 614
 615 static const struct dcn_hubp2_registers hubp_regs[] = {
 616                 hubp_regs(0),
 617                 hubp_regs(1),
 618                 hubp_regs(2),
 619                 hubp_regs(3)
 620 };
 621
 622
 623 static const struct dcn_hubp2_shift hubp_shift = {
 624                 HUBP_MASK_SH_LIST_DCN32(__SHIFT)
 625 };
 626
 627 static const struct dcn_hubp2_mask hubp_mask = {
 628                 HUBP_MASK_SH_LIST_DCN32(_MASK)
 629 };
 630 static const struct dcn_hubbub_registers hubbub_reg = {
 631                 HUBBUB_REG_LIST_DCN32(0)
 632 };
 633
 634 static const struct dcn_hubbub_shift hubbub_shift = {
 635                 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT)
 636 };
 637
 638 static const struct dcn_hubbub_mask hubbub_mask = {
 639                 HUBBUB_MASK_SH_LIST_DCN32(_MASK)
 640 };
 641
 642 static const struct dccg_registers dccg_regs = {
 643                 DCCG_REG_LIST_DCN32()
 644 };
 645
 646 static const struct dccg_shift dccg_shift = {
 647                 DCCG_MASK_SH_LIST_DCN32(__SHIFT)
 648 };
 649
 650 static const struct dccg_mask dccg_mask = {
 651                 DCCG_MASK_SH_LIST_DCN32(_MASK)
 652 };
 653
 654
 655 #define SRII2(reg_name_pre, reg_name_post, id)\
 656         .reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 657                         ## id ## _ ## reg_name_post ## _BASE_IDX) + \
 658                         reg ## reg_name_pre ## id ## _ ## reg_name_post
 659
 660
 661 #define HWSEQ_DCN32_REG_LIST()\
 662         SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
 663         SR(DIO_MEM_PWR_CTRL), \
 664         SR(ODM_MEM_PWR_CTRL3), \
 665         SR(MMHUBBUB_MEM_PWR_CNTL), \
 666         SR(DCCG_GATE_DISABLE_CNTL), \
 667         SR(DCCG_GATE_DISABLE_CNTL2), \
 668         SR(DCFCLK_CNTL),\
 669         SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
 670         SRII(PIXEL_RATE_CNTL, OTG, 0), \
 671         SRII(PIXEL_RATE_CNTL, OTG, 1),\
 672         SRII(PIXEL_RATE_CNTL, OTG, 2),\
 673         SRII(PIXEL_RATE_CNTL, OTG, 3),\
 674         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
 675         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
 676         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
 677         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
 678         SR(MICROSECOND_TIME_BASE_DIV), \
 679         SR(MILLISECOND_TIME_BASE_DIV), \
 680         SR(DISPCLK_FREQ_CHANGE_CNTL), \
 681         SR(RBBMIF_TIMEOUT_DIS), \
 682         SR(RBBMIF_TIMEOUT_DIS_2), \
 683         SR(DCHUBBUB_CRC_CTRL), \
 684         SR(DPP_TOP0_DPP_CRC_CTRL), \
 685         SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
 686         SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
 687         SR(MPC_CRC_CTRL), \
 688         SR(MPC_CRC_RESULT_GB), \
 689         SR(MPC_CRC_RESULT_C), \
 690         SR(MPC_CRC_RESULT_AR), \
 691         SR(DOMAIN0_PG_CONFIG), \
 692         SR(DOMAIN1_PG_CONFIG), \
 693         SR(DOMAIN2_PG_CONFIG), \
 694         SR(DOMAIN3_PG_CONFIG), \
 695         SR(DOMAIN16_PG_CONFIG), \
 696         SR(DOMAIN17_PG_CONFIG), \
 697         SR(DOMAIN18_PG_CONFIG), \
 698         SR(DOMAIN19_PG_CONFIG), \
 699         SR(DOMAIN0_PG_STATUS), \
 700         SR(DOMAIN1_PG_STATUS), \
 701         SR(DOMAIN2_PG_STATUS), \
 702         SR(DOMAIN3_PG_STATUS), \
 703         SR(DOMAIN16_PG_STATUS), \
 704         SR(DOMAIN17_PG_STATUS), \
 705         SR(DOMAIN18_PG_STATUS), \
 706         SR(DOMAIN19_PG_STATUS), \
 707         SR(D1VGA_CONTROL), \
 708         SR(D2VGA_CONTROL), \
 709         SR(D3VGA_CONTROL), \
 710         SR(D4VGA_CONTROL), \
 711         SR(D5VGA_CONTROL), \
 712         SR(D6VGA_CONTROL), \
 713         SR(DC_IP_REQUEST_CNTL), \
 714         SR(AZALIA_AUDIO_DTO), \
 715         SR(AZALIA_CONTROLLER_CLOCK_GATING)
 716
 717 static const struct dce_hwseq_registers hwseq_reg = {
 718                 HWSEQ_DCN32_REG_LIST()
 719 };
 720
 721 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\
 722         HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 723         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 724         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 725         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 726         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 727         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 728         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 729         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 730         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 731         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 732         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 733         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 734         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 735         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 736         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 737         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 738         HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 739         HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 740         HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 741         HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 742         HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 743         HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 744         HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 745         HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 746         HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 747         HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 748         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 749         HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 750         HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 751         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 752         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
 753         HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
 754
 755 static const struct dce_hwseq_shift hwseq_shift = {
 756                 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT)
 757 };
 758
 759 static const struct dce_hwseq_mask hwseq_mask = {
 760                 HWSEQ_DCN32_MASK_SH_LIST(_MASK)
 761 };
 762 #define vmid_regs(id)\
 763 [id] = {\
 764                 DCN20_VMID_REG_LIST(id)\
 765 }
 766
 767 static const struct dcn_vmid_registers vmid_regs[] = {
 768         vmid_regs(0),
 769         vmid_regs(1),
 770         vmid_regs(2),
 771         vmid_regs(3),
 772         vmid_regs(4),
 773         vmid_regs(5),
 774         vmid_regs(6),
 775         vmid_regs(7),
 776         vmid_regs(8),
 777         vmid_regs(9),
 778         vmid_regs(10),
 779         vmid_regs(11),
 780         vmid_regs(12),
 781         vmid_regs(13),
 782         vmid_regs(14),
 783         vmid_regs(15)
 784 };
 785
 786 static const struct dcn20_vmid_shift vmid_shifts = {
 787                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 788 };
 789
 790 static const struct dcn20_vmid_mask vmid_masks = {
 791                 DCN20_VMID_MASK_SH_LIST(_MASK)
 792 };
 793
 794 static const struct resource_caps res_cap_dcn32 = {
 795         .num_timing_generator = 4,
 796         .num_opp = 4,
 797         .num_video_plane = 4,
 798         .num_audio = 5,
 799         .num_stream_encoder = 5,
 800         .num_hpo_dp_stream_encoder = 4,
 801         .num_hpo_dp_link_encoder = 2,
 802         .num_pll = 5,
 803         .num_dwb = 1,
 804         .num_ddc = 5,
 805         .num_vmid = 16,
 806         .num_mpc_3dlut = 4,
 807         .num_dsc = 4,
 808 };
 809
 810 static const struct dc_plane_cap plane_cap = {
 811         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 812         .blends_with_above = true,
 813         .blends_with_below = true,
 814         .per_pixel_alpha = true,
 815
 816         .pixel_format_support = {
 817                         .argb8888 = true,
 818                         .nv12 = true,
 819                         .fp16 = true,
 820                         .p010 = true,
 821                         .ayuv = false,
 822         },
 823
 824         .max_upscale_factor = {
 825                         .argb8888 = 16000,
 826                         .nv12 = 16000,
 827                         .fp16 = 16000
 828         },
 829
 830         // 6:1 downscaling ratio: 1000/6 = 166.666
 831         .max_downscale_factor = {
 832                         .argb8888 = 167,
 833                         .nv12 = 167,
 834                         .fp16 = 167
 835         },
 836         64,
 837         64
 838 };
 839
 840 static const struct dc_debug_options debug_defaults_drv = {
 841         .disable_dmcu = true,
 842         .force_abm_enable = false,
 843         .timing_trace = false,
 844         .clock_trace = true,
 845         .disable_pplib_clock_request = false,
 846         .pipe_split_policy = MPC_SPLIT_AVOID, // Due to CRB, no need to MPC split anymore
 847         .force_single_disp_pipe_split = false,
 848         .disable_dcc = DCC_ENABLE,
 849         .vsr_support = true,
 850         .performance_trace = false,
 851         .max_downscale_src_width = 7680,/*upto 8K*/
 852         .disable_pplib_wm_range = false,
 853         .scl_reset_length10 = true,
 854         .sanity_checks = false,
 855         .underflow_assert_delay_us = 0xFFFFFFFF,
 856         .dwb_fi_phase = -1, // -1 = disable,
 857         .dmub_command_table = true,
 858         .enable_mem_low_power = {
 859                 .bits = {
 860                         .vga = false,
 861                         .i2c = false,
 862                         .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
 863                         .dscl = false,
 864                         .cm = false,
 865                         .mpc = false,
 866                         .optc = true,
 867                 }
 868         },
 869         .use_max_lb = true,
 870         .force_disable_subvp = false,
 871         .exit_idle_opt_for_cursor_updates = true,
 872         .enable_single_display_2to1_odm_policy = true,
 873         .enable_dp_dig_pixel_rate_div_policy = 1,
 874 };
 875
 876 static const struct dc_debug_options debug_defaults_diags = {
 877         .disable_dmcu = true,
 878         .force_abm_enable = false,
 879         .timing_trace = true,
 880         .clock_trace = true,
 881         .disable_dpp_power_gate = true,
 882         .disable_hubp_power_gate = true,
 883         .disable_dsc_power_gate = true,
 884         .disable_clock_gate = true,
 885         .disable_pplib_clock_request = true,
 886         .disable_pplib_wm_range = true,
 887         .disable_stutter = false,
 888         .scl_reset_length10 = true,
 889         .dwb_fi_phase = -1, // -1 = disable
 890         .dmub_command_table = true,
 891         .enable_tri_buf = true,
 892         .use_max_lb = true,
 893         .force_disable_subvp = true
 894 };
 895
 896 static struct dce_aux *dcn32_aux_engine_create(
 897         struct dc_context *ctx,
 898         uint32_t inst)
 899 {
 900         struct aux_engine_dce110 *aux_engine =
 901                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 902
 903         if (!aux_engine)
 904                 return NULL;
 905
 906         dce110_aux_engine_construct(aux_engine, ctx, inst,
 907                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 908                                     &aux_engine_regs[inst],
 909                                         &aux_mask,
 910                                         &aux_shift,
 911                                         ctx->dc->caps.extended_aux_timeout_support);
 912
 913         return &aux_engine->base;
 914 }
 915 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
 916
 917 static const struct dce_i2c_registers i2c_hw_regs[] = {
 918                 i2c_inst_regs(1),
 919                 i2c_inst_regs(2),
 920                 i2c_inst_regs(3),
 921                 i2c_inst_regs(4),
 922                 i2c_inst_regs(5),
 923 };
 924
 925 static const struct dce_i2c_shift i2c_shifts = {
 926                 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 927 };
 928
 929 static const struct dce_i2c_mask i2c_masks = {
 930                 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
 931 };
 932
 933 static struct dce_i2c_hw *dcn32_i2c_hw_create(
 934         struct dc_context *ctx,
 935         uint32_t inst)
 936 {
 937         struct dce_i2c_hw *dce_i2c_hw =
 938                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 939
 940         if (!dce_i2c_hw)
 941                 return NULL;
 942
 943         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 944                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 945
 946         return dce_i2c_hw;
 947 }
 948
 949 static struct clock_source *dcn32_clock_source_create(
 950                 struct dc_context *ctx,
 951                 struct dc_bios *bios,
 952                 enum clock_source_id id,
 953                 const struct dce110_clk_src_regs *regs,
 954                 bool dp_clk_src)
 955 {
 956         struct dce110_clk_src *clk_src =
 957                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 958
 959         if (!clk_src)
 960                 return NULL;
 961
 962         if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
 963                         regs, &cs_shift, &cs_mask)) {
 964                 clk_src->base.dp_clk_src = dp_clk_src;
 965                 return &clk_src->base;
 966         }
 967
 968         BREAK_TO_DEBUGGER();
 969         return NULL;
 970 }
 971
 972 static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx)
 973 {
 974         int i;
 975
 976         struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub),
 977                                           GFP_KERNEL);
 978
 979         if (!hubbub2)
 980                 return NULL;
 981
 982         hubbub32_construct(hubbub2, ctx,
 983                         &hubbub_reg,
 984                         &hubbub_shift,
 985                         &hubbub_mask,
 986                         ctx->dc->dml.ip.det_buffer_size_kbytes,
 987                         ctx->dc->dml.ip.pixel_chunk_size_kbytes,
 988                         ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);
 989
 990
 991         for (i = 0; i < res_cap_dcn32.num_vmid; i++) {
 992                 struct dcn20_vmid *vmid = &hubbub2->vmid[i];
 993
 994                 vmid->ctx = ctx;
 995
 996                 vmid->regs = &vmid_regs[i];
 997                 vmid->shifts = &vmid_shifts;
 998                 vmid->masks = &vmid_masks;
 999         }
1000
1001         return &hubbub2->base;
1002 }
1003
1004 static struct hubp *dcn32_hubp_create(
1005         struct dc_context *ctx,
1006         uint32_t inst)
1007 {
1008         struct dcn20_hubp *hubp2 =
1009                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1010
1011         if (!hubp2)
1012                 return NULL;
1013
1014         if (hubp32_construct(hubp2, ctx, inst,
1015                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1016                 return &hubp2->base;
1017
1018         BREAK_TO_DEBUGGER();
1019         kfree(hubp2);
1020         return NULL;
1021 }
1022
1023 static void dcn32_dpp_destroy(struct dpp **dpp)
1024 {
1025         kfree(TO_DCN30_DPP(*dpp));
1026         *dpp = NULL;
1027 }
1028
1029 static struct dpp *dcn32_dpp_create(
1030         struct dc_context *ctx,
1031         uint32_t inst)
1032 {
1033         struct dcn3_dpp *dpp3 =
1034                 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
1035
1036         if (!dpp3)
1037                 return NULL;
1038
1039         if (dpp32_construct(dpp3, ctx, inst,
1040                         &dpp_regs[inst], &tf_shift, &tf_mask))
1041                 return &dpp3->base;
1042
1043         BREAK_TO_DEBUGGER();
1044         kfree(dpp3);
1045         return NULL;
1046 }
1047
1048 static struct mpc *dcn32_mpc_create(
1049                 struct dc_context *ctx,
1050                 int num_mpcc,
1051                 int num_rmu)
1052 {
1053         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1054                                           GFP_KERNEL);
1055
1056         if (!mpc30)
1057                 return NULL;
1058
1059         dcn32_mpc_construct(mpc30, ctx,
1060                         &mpc_regs,
1061                         &mpc_shift,
1062                         &mpc_mask,
1063                         num_mpcc,
1064                         num_rmu);
1065
1066         return &mpc30->base;
1067 }
1068
1069 static struct output_pixel_processor *dcn32_opp_create(
1070         struct dc_context *ctx, uint32_t inst)
1071 {
1072         struct dcn20_opp *opp2 =
1073                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1074
1075         if (!opp2) {
1076                 BREAK_TO_DEBUGGER();
1077                 return NULL;
1078         }
1079
1080         dcn20_opp_construct(opp2, ctx, inst,
1081                         &opp_regs[inst], &opp_shift, &opp_mask);
1082         return &opp2->base;
1083 }
1084
1085
1086 static struct timing_generator *dcn32_timing_generator_create(
1087                 struct dc_context *ctx,
1088                 uint32_t instance)
1089 {
1090         struct optc *tgn10 =
1091                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1092
1093         if (!tgn10)
1094                 return NULL;
1095
1096         tgn10->base.inst = instance;
1097         tgn10->base.ctx = ctx;
1098
1099         tgn10->tg_regs = &optc_regs[instance];
1100         tgn10->tg_shift = &optc_shift;
1101         tgn10->tg_mask = &optc_mask;
1102
1103         dcn32_timing_generator_init(tgn10);
1104
1105         return &tgn10->base;
1106 }
1107
1108 static const struct encoder_feature_support link_enc_feature = {
1109                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1110                 .max_hdmi_pixel_clock = 600000,
1111                 .hdmi_ycbcr420_supported = true,
1112                 .dp_ycbcr420_supported = true,
1113                 .fec_supported = true,
1114                 .flags.bits.IS_HBR2_CAPABLE = true,
1115                 .flags.bits.IS_HBR3_CAPABLE = true,
1116                 .flags.bits.IS_TPS3_CAPABLE = true,
1117                 .flags.bits.IS_TPS4_CAPABLE = true
1118 };
1119
1120 static struct link_encoder *dcn32_link_encoder_create(
1121         struct dc_context *ctx,
1122         const struct encoder_init_data *enc_init_data)
1123 {
1124         struct dcn20_link_encoder *enc20 =
1125                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1126
1127         if (!enc20)
1128                 return NULL;
1129
1130         dcn32_link_encoder_construct(enc20,
1131                         enc_init_data,
1132                         &link_enc_feature,
1133                         &link_enc_regs[enc_init_data->transmitter],
1134                         &link_enc_aux_regs[enc_init_data->channel - 1],
1135                         &link_enc_hpd_regs[enc_init_data->hpd_source],
1136                         &le_shift,
1137                         &le_mask);
1138
1139         return &enc20->enc10.base;
1140 }
1141
1142 struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1143 {
1144         struct dcn31_panel_cntl *panel_cntl =
1145                 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1146
1147         if (!panel_cntl)
1148                 return NULL;
1149
1150         dcn31_panel_cntl_construct(panel_cntl, init_data);
1151
1152         return &panel_cntl->base;
1153 }
1154
1155 static void read_dce_straps(
1156         struct dc_context *ctx,
1157         struct resource_straps *straps)
1158 {
1159         generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1160                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1161
1162 }
1163
1164 static struct audio *dcn32_create_audio(
1165                 struct dc_context *ctx, unsigned int inst)
1166 {
1167         return dce_audio_create(ctx, inst,
1168                         &audio_regs[inst], &audio_shift, &audio_mask);
1169 }
1170
1171 static struct vpg *dcn32_vpg_create(
1172         struct dc_context *ctx,
1173         uint32_t inst)
1174 {
1175         struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
1176
1177         if (!vpg3)
1178                 return NULL;
1179
1180         vpg3_construct(vpg3, ctx, inst,
1181                         &vpg_regs[inst],
1182                         &vpg_shift,
1183                         &vpg_mask);
1184
1185         return &vpg3->base;
1186 }
1187
1188 static struct afmt *dcn32_afmt_create(
1189         struct dc_context *ctx,
1190         uint32_t inst)
1191 {
1192         struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1193
1194         if (!afmt3)
1195                 return NULL;
1196
1197         afmt3_construct(afmt3, ctx, inst,
1198                         &afmt_regs[inst],
1199                         &afmt_shift,
1200                         &afmt_mask);
1201
1202         return &afmt3->base;
1203 }
1204
1205 static struct apg *dcn31_apg_create(
1206         struct dc_context *ctx,
1207         uint32_t inst)
1208 {
1209         struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1210
1211         if (!apg31)
1212                 return NULL;
1213
1214         apg31_construct(apg31, ctx, inst,
1215                         &apg_regs[inst],
1216                         &apg_shift,
1217                         &apg_mask);
1218
1219         return &apg31->base;
1220 }
1221
1222 static struct stream_encoder *dcn32_stream_encoder_create(
1223         enum engine_id eng_id,
1224         struct dc_context *ctx)
1225 {
1226         struct dcn10_stream_encoder *enc1;
1227         struct vpg *vpg;
1228         struct afmt *afmt;
1229         int vpg_inst;
1230         int afmt_inst;
1231
1232         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1233         if (eng_id <= ENGINE_ID_DIGF) {
1234                 vpg_inst = eng_id;
1235                 afmt_inst = eng_id;
1236         } else
1237                 return NULL;
1238
1239         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1240         vpg = dcn32_vpg_create(ctx, vpg_inst);
1241         afmt = dcn32_afmt_create(ctx, afmt_inst);
1242
1243         if (!enc1 || !vpg || !afmt) {
1244                 kfree(enc1);
1245                 kfree(vpg);
1246                 kfree(afmt);
1247                 return NULL;
1248         }
1249
1250         dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1251                                         eng_id, vpg, afmt,
1252                                         &stream_enc_regs[eng_id],
1253                                         &se_shift, &se_mask);
1254
1255         return &enc1->base;
1256 }
1257
1258 static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create(
1259         enum engine_id eng_id,
1260         struct dc_context *ctx)
1261 {
1262         struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1263         struct vpg *vpg;
1264         struct apg *apg;
1265         uint32_t hpo_dp_inst;
1266         uint32_t vpg_inst;
1267         uint32_t apg_inst;
1268
1269         ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1270         hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1271
1272         /* Mapping of VPG register blocks to HPO DP block instance:
1273          * VPG[6] -> HPO_DP[0]
1274          * VPG[7] -> HPO_DP[1]
1275          * VPG[8] -> HPO_DP[2]
1276          * VPG[9] -> HPO_DP[3]
1277          */
1278         vpg_inst = hpo_dp_inst + 6;
1279
1280         /* Mapping of APG register blocks to HPO DP block instance:
1281          * APG[0] -> HPO_DP[0]
1282          * APG[1] -> HPO_DP[1]
1283          * APG[2] -> HPO_DP[2]
1284          * APG[3] -> HPO_DP[3]
1285          */
1286         apg_inst = hpo_dp_inst;
1287
1288         /* allocate HPO stream encoder and create VPG sub-block */
1289         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1290         vpg = dcn32_vpg_create(ctx, vpg_inst);
1291         apg = dcn31_apg_create(ctx, apg_inst);
1292
1293         if (!hpo_dp_enc31 || !vpg || !apg) {
1294                 kfree(hpo_dp_enc31);
1295                 kfree(vpg);
1296                 kfree(apg);
1297                 return NULL;
1298         }
1299
1300         dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1301                                         hpo_dp_inst, eng_id, vpg, apg,
1302                                         &hpo_dp_stream_enc_regs[hpo_dp_inst],
1303                                         &hpo_dp_se_shift, &hpo_dp_se_mask);
1304
1305         return &hpo_dp_enc31->base;
1306 }
1307
1308 static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create(
1309         uint8_t inst,
1310         struct dc_context *ctx)
1311 {
1312         struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1313
1314         /* allocate HPO link encoder */
1315         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1316
1317         hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
1318                                         &hpo_dp_link_enc_regs[inst],
1319                                         &hpo_dp_le_shift, &hpo_dp_le_mask);
1320
1321         return &hpo_dp_enc31->base;
1322 }
1323
1324 static struct dce_hwseq *dcn32_hwseq_create(
1325         struct dc_context *ctx)
1326 {
1327         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1328
1329         if (hws) {
1330                 hws->ctx = ctx;
1331                 hws->regs = &hwseq_reg;
1332                 hws->shifts = &hwseq_shift;
1333                 hws->masks = &hwseq_mask;
1334         }
1335         return hws;
1336 }
1337 static const struct resource_create_funcs res_create_funcs = {
1338         .read_dce_straps = read_dce_straps,
1339         .create_audio = dcn32_create_audio,
1340         .create_stream_encoder = dcn32_stream_encoder_create,
1341         .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create,
1342         .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create,
1343         .create_hwseq = dcn32_hwseq_create,
1344 };
1345
1346 static const struct resource_create_funcs res_create_maximus_funcs = {
1347         .read_dce_straps = NULL,
1348         .create_audio = NULL,
1349         .create_stream_encoder = NULL,
1350         .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create,
1351         .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create,
1352         .create_hwseq = dcn32_hwseq_create,
1353 };
1354
1355 static void dcn32_resource_destruct(struct dcn32_resource_pool *pool)
1356 {
1357         unsigned int i;
1358
1359         for (i = 0; i < pool->base.stream_enc_count; i++) {
1360                 if (pool->base.stream_enc[i] != NULL) {
1361                         if (pool->base.stream_enc[i]->vpg != NULL) {
1362                                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1363                                 pool->base.stream_enc[i]->vpg = NULL;
1364                         }
1365                         if (pool->base.stream_enc[i]->afmt != NULL) {
1366                                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1367                                 pool->base.stream_enc[i]->afmt = NULL;
1368                         }
1369                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1370                         pool->base.stream_enc[i] = NULL;
1371                 }
1372         }
1373
1374         for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1375                 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1376                         if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1377                                 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1378                                 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1379                         }
1380                         if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1381                                 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1382                                 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1383                         }
1384                         kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1385                         pool->base.hpo_dp_stream_enc[i] = NULL;
1386                 }
1387         }
1388
1389         for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1390                 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1391                         kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1392                         pool->base.hpo_dp_link_enc[i] = NULL;
1393                 }
1394         }
1395
1396         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1397                 if (pool->base.dscs[i] != NULL)
1398                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1399         }
1400
1401         if (pool->base.mpc != NULL) {
1402                 kfree(TO_DCN20_MPC(pool->base.mpc));
1403                 pool->base.mpc = NULL;
1404         }
1405         if (pool->base.hubbub != NULL) {
1406                 kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
1407                 pool->base.hubbub = NULL;
1408         }
1409         for (i = 0; i < pool->base.pipe_count; i++) {
1410                 if (pool->base.dpps[i] != NULL)
1411                         dcn32_dpp_destroy(&pool->base.dpps[i]);
1412
1413                 if (pool->base.ipps[i] != NULL)
1414                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1415
1416                 if (pool->base.hubps[i] != NULL) {
1417                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1418                         pool->base.hubps[i] = NULL;
1419                 }
1420
1421                 if (pool->base.irqs != NULL) {
1422                         dal_irq_service_destroy(&pool->base.irqs);
1423                 }
1424         }
1425
1426         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1427                 if (pool->base.engines[i] != NULL)
1428                         dce110_engine_destroy(&pool->base.engines[i]);
1429                 if (pool->base.hw_i2cs[i] != NULL) {
1430                         kfree(pool->base.hw_i2cs[i]);
1431                         pool->base.hw_i2cs[i] = NULL;
1432                 }
1433                 if (pool->base.sw_i2cs[i] != NULL) {
1434                         kfree(pool->base.sw_i2cs[i]);
1435                         pool->base.sw_i2cs[i] = NULL;
1436                 }
1437         }
1438
1439         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1440                 if (pool->base.opps[i] != NULL)
1441                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1442         }
1443
1444         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1445                 if (pool->base.timing_generators[i] != NULL)    {
1446                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1447                         pool->base.timing_generators[i] = NULL;
1448                 }
1449         }
1450
1451         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1452                 if (pool->base.dwbc[i] != NULL) {
1453                         kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1454                         pool->base.dwbc[i] = NULL;
1455                 }
1456                 if (pool->base.mcif_wb[i] != NULL) {
1457                         kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1458                         pool->base.mcif_wb[i] = NULL;
1459                 }
1460         }
1461
1462         for (i = 0; i < pool->base.audio_count; i++) {
1463                 if (pool->base.audios[i])
1464                         dce_aud_destroy(&pool->base.audios[i]);
1465         }
1466
1467         for (i = 0; i < pool->base.clk_src_count; i++) {
1468                 if (pool->base.clock_sources[i] != NULL) {
1469                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1470                         pool->base.clock_sources[i] = NULL;
1471                 }
1472         }
1473
1474         for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1475                 if (pool->base.mpc_lut[i] != NULL) {
1476                         dc_3dlut_func_release(pool->base.mpc_lut[i]);
1477                         pool->base.mpc_lut[i] = NULL;
1478                 }
1479                 if (pool->base.mpc_shaper[i] != NULL) {
1480                         dc_transfer_func_release(pool->base.mpc_shaper[i]);
1481                         pool->base.mpc_shaper[i] = NULL;
1482                 }
1483         }
1484
1485         if (pool->base.dp_clock_source != NULL) {
1486                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1487                 pool->base.dp_clock_source = NULL;
1488         }
1489
1490         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1491                 if (pool->base.multiple_abms[i] != NULL)
1492                         dce_abm_destroy(&pool->base.multiple_abms[i]);
1493         }
1494
1495         if (pool->base.psr != NULL)
1496                 dmub_psr_destroy(&pool->base.psr);
1497
1498         if (pool->base.dccg != NULL)
1499                 dcn_dccg_destroy(&pool->base.dccg);
1500
1501         if (pool->base.oem_device != NULL)
1502                 dal_ddc_service_destroy(&pool->base.oem_device);
1503 }
1504
1505
1506 static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1507 {
1508         int i;
1509         uint32_t dwb_count = pool->res_cap->num_dwb;
1510
1511         for (i = 0; i < dwb_count; i++) {
1512                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1513                                                     GFP_KERNEL);
1514
1515                 if (!dwbc30) {
1516                         dm_error("DC: failed to create dwbc30!\n");
1517                         return false;
1518                 }
1519
1520                 dcn30_dwbc_construct(dwbc30, ctx,
1521                                 &dwbc30_regs[i],
1522                                 &dwbc30_shift,
1523                                 &dwbc30_mask,
1524                                 i);
1525
1526                 pool->dwbc[i] = &dwbc30->base;
1527         }
1528         return true;
1529 }
1530
1531 static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1532 {
1533         int i;
1534         uint32_t dwb_count = pool->res_cap->num_dwb;
1535
1536         for (i = 0; i < dwb_count; i++) {
1537                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1538                                                     GFP_KERNEL);
1539
1540                 if (!mcif_wb30) {
1541                         dm_error("DC: failed to create mcif_wb30!\n");
1542                         return false;
1543                 }
1544
1545                 dcn32_mmhubbub_construct(mcif_wb30, ctx,
1546                                 &mcif_wb30_regs[i],
1547                                 &mcif_wb30_shift,
1548                                 &mcif_wb30_mask,
1549                                 i);
1550
1551                 pool->mcif_wb[i] = &mcif_wb30->base;
1552         }
1553         return true;
1554 }
1555
1556 static struct display_stream_compressor *dcn32_dsc_create(
1557         struct dc_context *ctx, uint32_t inst)
1558 {
1559         struct dcn20_dsc *dsc =
1560                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1561
1562         if (!dsc) {
1563                 BREAK_TO_DEBUGGER();
1564                 return NULL;
1565         }
1566
1567         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1568
1569         dsc->max_image_width = 6016;
1570
1571         return &dsc->base;
1572 }
1573
1574 static void dcn32_destroy_resource_pool(struct resource_pool **pool)
1575 {
1576         struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool);
1577
1578         dcn32_resource_destruct(dcn32_pool);
1579         kfree(dcn32_pool);
1580         *pool = NULL;
1581 }
1582
1583 bool dcn32_acquire_post_bldn_3dlut(
1584                 struct resource_context *res_ctx,
1585                 const struct resource_pool *pool,
1586                 int mpcc_id,
1587                 struct dc_3dlut **lut,
1588                 struct dc_transfer_func **shaper)
1589 {
1590         bool ret = false;
1591         union dc_3dlut_state *state;
1592
1593         ASSERT(*lut == NULL && *shaper == NULL);
1594         *lut = NULL;
1595         *shaper = NULL;
1596
1597         if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) {
1598                 *lut = pool->mpc_lut[mpcc_id];
1599                 *shaper = pool->mpc_shaper[mpcc_id];
1600                 state = &pool->mpc_lut[mpcc_id]->state;
1601                 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true;
1602                 ret = true;
1603         }
1604         return ret;
1605 }
1606
1607 bool dcn32_release_post_bldn_3dlut(
1608                 struct resource_context *res_ctx,
1609                 const struct resource_pool *pool,
1610                 struct dc_3dlut **lut,
1611                 struct dc_transfer_func **shaper)
1612 {
1613         int i;
1614         bool ret = false;
1615
1616         for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1617                 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1618                         res_ctx->is_mpc_3dlut_acquired[i] = false;
1619                         pool->mpc_lut[i]->state.raw = 0;
1620                         *lut = NULL;
1621                         *shaper = NULL;
1622                         ret = true;
1623                         break;
1624                 }
1625         }
1626         return ret;
1627 }
1628
1629 static void dcn32_enable_phantom_plane(struct dc *dc,
1630                 struct dc_state *context,
1631                 struct dc_stream_state *phantom_stream,
1632                 unsigned int dc_pipe_idx)
1633 {
1634         struct dc_plane_state *phantom_plane = NULL;
1635         struct dc_plane_state *prev_phantom_plane = NULL;
1636         struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
1637
1638         while (curr_pipe) {
1639                 if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state)
1640                         phantom_plane = prev_phantom_plane;
1641                 else
1642                         phantom_plane = dc_create_plane_state(dc);
1643
1644                 memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address));
1645                 memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality,
1646                                 sizeof(phantom_plane->scaling_quality));
1647                 memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect));
1648                 memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect));
1649                 memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect));
1650                 memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size,
1651                                 sizeof(phantom_plane->plane_size));
1652                 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info,
1653                                 sizeof(phantom_plane->tiling_info));
1654                 memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc));
1655                 phantom_plane->format = curr_pipe->plane_state->format;
1656                 phantom_plane->rotation = curr_pipe->plane_state->rotation;
1657                 phantom_plane->visible = curr_pipe->plane_state->visible;
1658
1659                 /* Shadow pipe has small viewport. */
1660                 phantom_plane->clip_rect.y = 0;
1661                 phantom_plane->clip_rect.height = phantom_stream->timing.v_addressable;
1662
1663                 dc_add_plane_to_context(dc, phantom_stream, phantom_plane, context);
1664
1665                 curr_pipe = curr_pipe->bottom_pipe;
1666                 prev_phantom_plane = phantom_plane;
1667         }
1668 }
1669
1670 static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc,
1671                 struct dc_state *context,
1672                 display_e2e_pipe_params_st *pipes,
1673                 unsigned int pipe_cnt,
1674                 unsigned int dc_pipe_idx)
1675 {
1676         struct dc_stream_state *phantom_stream = NULL;
1677         struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
1678
1679         phantom_stream = dc_create_stream_for_sink(ref_pipe->stream->sink);
1680         phantom_stream->signal = SIGNAL_TYPE_VIRTUAL;
1681         phantom_stream->dpms_off = true;
1682         phantom_stream->mall_stream_config.type = SUBVP_PHANTOM;
1683         phantom_stream->mall_stream_config.paired_stream = ref_pipe->stream;
1684         ref_pipe->stream->mall_stream_config.type = SUBVP_MAIN;
1685         ref_pipe->stream->mall_stream_config.paired_stream = phantom_stream;
1686
1687         /* stream has limited viewport and small timing */
1688         memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing));
1689         memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src));
1690         memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst));
1691         DC_FP_START();
1692         dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx);
1693         DC_FP_END();
1694
1695         dc_add_stream_to_ctx(dc, context, phantom_stream);
1696         return phantom_stream;
1697 }
1698
1699 // return true if removed piped from ctx, false otherwise
1700 bool dcn32_remove_phantom_pipes(struct dc *dc, struct dc_state *context)
1701 {
1702         int i;
1703         bool removed_pipe = false;
1704
1705         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1706                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1707                 // build scaling params for phantom pipes
1708                 if (pipe->plane_state && pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
1709                         dc_rem_all_planes_for_stream(dc, pipe->stream, context);
1710                         dc_remove_stream_from_ctx(dc, context, pipe->stream);
1711                         removed_pipe = true;
1712                 }
1713
1714                 // Clear all phantom stream info
1715                 if (pipe->stream) {
1716                         pipe->stream->mall_stream_config.type = SUBVP_NONE;
1717                         pipe->stream->mall_stream_config.paired_stream = NULL;
1718                 }
1719         }
1720         return removed_pipe;
1721 }
1722
1723 /* TODO: Input to this function should indicate which pipe indexes (or streams)
1724  * require a phantom pipe / stream
1725  */
1726 void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context,
1727                 display_e2e_pipe_params_st *pipes,
1728                 unsigned int pipe_cnt,
1729                 unsigned int index)
1730 {
1731         struct dc_stream_state *phantom_stream = NULL;
1732         unsigned int i;
1733
1734         // The index of the DC pipe passed into this function is guarenteed to
1735         // be a valid candidate for SubVP (i.e. has a plane, stream, doesn't
1736         // already have phantom pipe assigned, etc.) by previous checks.
1737         phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index);
1738         dcn32_enable_phantom_plane(dc, context, phantom_stream, index);
1739
1740         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1741                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1742
1743                 // Build scaling params for phantom pipes which were newly added.
1744                 // We determine which phantom pipes were added by comparing with
1745                 // the phantom stream.
1746                 if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream &&
1747                                 pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
1748                         pipe->stream->use_dynamic_meta = false;
1749                         pipe->plane_state->flip_immediate = false;
1750                         if (!resource_build_scaling_params(pipe)) {
1751                                 // Log / remove phantom pipes since failed to build scaling params
1752                         }
1753                 }
1754         }
1755 }
1756
1757 bool dcn32_validate_bandwidth(struct dc *dc,
1758                 struct dc_state *context,
1759                 bool fast_validate)
1760 {
1761         bool out = false;
1762
1763         BW_VAL_TRACE_SETUP();
1764
1765         int vlevel = 0;
1766         int pipe_cnt = 0;
1767         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1768         DC_LOGGER_INIT(dc->ctx->logger);
1769
1770         BW_VAL_TRACE_COUNT();
1771
1772         DC_FP_START();
1773         out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
1774         DC_FP_END();
1775
1776         if (pipe_cnt == 0)
1777                 goto validate_out;
1778
1779         if (!out)
1780                 goto validate_fail;
1781
1782         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1783
1784         if (fast_validate) {
1785                 BW_VAL_TRACE_SKIP(fast);
1786                 goto validate_out;
1787         }
1788
1789         dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1790
1791         BW_VAL_TRACE_END_WATERMARKS();
1792
1793         goto validate_out;
1794
1795 validate_fail:
1796         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1797                 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1798
1799         BW_VAL_TRACE_SKIP(fail);
1800         out = false;
1801
1802 validate_out:
1803         kfree(pipes);
1804
1805         BW_VAL_TRACE_FINISH();
1806
1807         return out;
1808 }
1809
1810
1811 static bool is_dual_plane(enum surface_pixel_format format)
1812 {
1813         return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1814 }
1815
1816 int dcn32_populate_dml_pipes_from_context(
1817         struct dc *dc, struct dc_state *context,
1818         display_e2e_pipe_params_st *pipes,
1819         bool fast_validate)
1820 {
1821         int i, pipe_cnt;
1822         struct resource_context *res_ctx = &context->res_ctx;
1823         struct pipe_ctx *pipe;
1824         bool subvp_in_use = false, is_pipe_split_expected[MAX_PIPES];
1825         int plane_count = 0;
1826         struct dc_crtc_timing *timing;
1827
1828         dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1829
1830         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1831
1832                 if (!res_ctx->pipe_ctx[i].stream)
1833                         continue;
1834                 pipe = &res_ctx->pipe_ctx[i];
1835                 timing = &pipe->stream->timing;
1836
1837                 pipes[pipe_cnt].pipe.src.gpuvm = true;
1838                 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
1839                 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
1840                 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1841                 pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet
1842                 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1843                 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19;
1844
1845                 switch (pipe->stream->mall_stream_config.type) {
1846                 case SUBVP_MAIN:
1847                         pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport;
1848                         subvp_in_use = true;
1849                         break;
1850                 case SUBVP_PHANTOM:
1851                         pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe;
1852                         pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable;
1853                         // Disallow unbounded req for SubVP according to DCHUB programming guide
1854                         pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1855                         break;
1856                 case SUBVP_NONE:
1857                         pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable;
1858                         pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable;
1859                         break;
1860                 default:
1861                         break;
1862                 }
1863
1864                 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1865                 if (pipes[pipe_cnt].dout.dsc_enable) {
1866                         switch (timing->display_color_depth) {
1867                         case COLOR_DEPTH_888:
1868                                 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1869                                 break;
1870                         case COLOR_DEPTH_101010:
1871                                 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1872                                 break;
1873                         case COLOR_DEPTH_121212:
1874                                 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1875                                 break;
1876                         default:
1877                                 ASSERT(0);
1878                                 break;
1879                         }
1880                 }
1881
1882                 /* Calculate the number of planes we have so we can determine
1883                  *  whether to apply ODM 2to1 policy or not
1884                  */
1885                 if (pipe->stream && !pipe->prev_odm_pipe &&
1886                                 (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state))
1887                         ++plane_count;
1888
1889                 DC_FP_START();
1890                 is_pipe_split_expected[i] = dcn32_predict_pipe_split(context, pipes[i].pipe, i);
1891                 DC_FP_END();
1892
1893                 pipe_cnt++;
1894         }
1895
1896         /* Determine whether we will apply ODM 2to1 policy
1897          * Applies to single display and where the number of planes is less than 3
1898          * For 3 plane case ( 2 MPO planes ), we will not set the policy for the MPO pipes
1899          */
1900         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1901                 if (!res_ctx->pipe_ctx[i].stream)
1902                         continue;
1903                 pipe = &res_ctx->pipe_ctx[i];
1904                 timing = &pipe->stream->timing;
1905
1906                 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;
1907                 res_ctx->pipe_ctx[i].stream->odm_2to1_policy_applied  = false;
1908                 if (context->stream_count == 1 && timing->dsc_cfg.num_slices_h != 1) {
1909                         if (dc->debug.enable_single_display_2to1_odm_policy) {
1910                                 if (!((plane_count > 2) && pipe->top_pipe))
1911                                         pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;
1912                         }
1913                         res_ctx->pipe_ctx[i].stream->odm_2to1_policy_applied = true;
1914                 }
1915                 pipe_cnt++;
1916         }
1917
1918         /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all
1919          * the DET available for each pipe). Use the DET override input to maintain our driver
1920          * policy.
1921          */
1922         if (pipe_cnt == 1 && !is_pipe_split_expected[0]) {
1923                 pipes[0].pipe.src.det_size_override = DCN3_2_MAX_DET_SIZE;
1924                 if (pipe->plane_state && !dc->debug.disable_z9_mpc) {
1925                         if (!is_dual_plane(pipe->plane_state->format)) {
1926                                 pipes[0].pipe.src.det_size_override = DCN3_2_DEFAULT_DET_SIZE;
1927                                 pipes[0].pipe.src.unbounded_req_mode = true;
1928                                 if (pipe->plane_state->src_rect.width >= 5120 &&
1929                                         pipe->plane_state->src_rect.height >= 2880)
1930                                         pipes[0].pipe.src.det_size_override = 320; // 5K or higher
1931                         }
1932                 }
1933         } else
1934                 dcn32_determine_det_override(context, pipes, is_pipe_split_expected, dc->res_pool->pipe_count);
1935
1936         // In general cases we want to keep the dram clock change requirement
1937         // (prefer configs that support MCLK switch). Only override to false
1938         // for SubVP
1939         if (subvp_in_use)
1940                 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false;
1941         else
1942                 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true;
1943
1944         return pipe_cnt;
1945 }
1946
1947 static struct dc_cap_funcs cap_funcs = {
1948         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1949 };
1950
1951 void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context,
1952                                 display_e2e_pipe_params_st *pipes,
1953                                 int pipe_cnt,
1954                                 int vlevel)
1955 {
1956     DC_FP_START();
1957     dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel);
1958     DC_FP_END();
1959 }
1960
1961 static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1962 {
1963         DC_FP_START();
1964         dcn32_update_bw_bounding_box_fpu(dc, bw_params);
1965         DC_FP_END();
1966 }
1967
1968 static struct resource_funcs dcn32_res_pool_funcs = {
1969         .destroy = dcn32_destroy_resource_pool,
1970         .link_enc_create = dcn32_link_encoder_create,
1971         .link_enc_create_minimal = NULL,
1972         .panel_cntl_create = dcn32_panel_cntl_create,
1973         .validate_bandwidth = dcn32_validate_bandwidth,
1974         .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg,
1975         .populate_dml_pipes = dcn32_populate_dml_pipes_from_context,
1976         .acquire_idle_pipe_for_head_pipe_in_layer = dcn32_acquire_idle_pipe_for_head_pipe_in_layer,
1977         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1978         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1979         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1980         .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1981         .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1982         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1983         .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
1984         .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
1985         .update_bw_bounding_box = dcn32_update_bw_bounding_box,
1986         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1987         .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1988         .add_phantom_pipes = dcn32_add_phantom_pipes,
1989         .remove_phantom_pipes = dcn32_remove_phantom_pipes,
1990 };
1991
1992
1993 static bool dcn32_resource_construct(
1994         uint8_t num_virtual_links,
1995         struct dc *dc,
1996         struct dcn32_resource_pool *pool)
1997 {
1998         int i, j;
1999         struct dc_context *ctx = dc->ctx;
2000         struct irq_service_init_data init_data;
2001         struct ddc_service_init_data ddc_init_data = {0};
2002         uint32_t pipe_fuses = 0;
2003         uint32_t num_pipes  = 4;
2004
2005         DC_FP_START();
2006
2007         ctx->dc_bios->regs = &bios_regs;
2008
2009         pool->base.res_cap = &res_cap_dcn32;
2010         /* max number of pipes for ASIC before checking for pipe fuses */
2011         num_pipes  = pool->base.res_cap->num_timing_generator;
2012         pipe_fuses = REG_READ(CC_DC_PIPE_DIS);
2013
2014         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
2015                 if (pipe_fuses & 1 << i)
2016                         num_pipes--;
2017
2018         if (pipe_fuses & 1)
2019                 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
2020
2021         if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
2022                 ASSERT(0); //Entire DCN is harvested!
2023
2024         /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the
2025          * value will be changed, update max_num_dpp and max_num_otg for dml.
2026          */
2027         dcn3_2_ip.max_num_dpp = num_pipes;
2028         dcn3_2_ip.max_num_otg = num_pipes;
2029
2030         pool->base.funcs = &dcn32_res_pool_funcs;
2031
2032         /*************************************************
2033          *  Resource + asic cap harcoding                *
2034          *************************************************/
2035         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2036         pool->base.timing_generator_count = num_pipes;
2037         pool->base.pipe_count = num_pipes;
2038         pool->base.mpcc_count = num_pipes;
2039         dc->caps.max_downscale_ratio = 600;
2040         dc->caps.i2c_speed_in_khz = 100;
2041         dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/
2042         dc->caps.max_cursor_size = 256;
2043         dc->caps.min_horizontal_blanking_period = 80;
2044         dc->caps.dmdata_alloc_size = 2048;
2045         dc->caps.mall_size_per_mem_channel = 0;
2046         dc->caps.mall_size_total = 0;
2047         dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2048
2049         dc->caps.cache_line_size = 64;
2050         dc->caps.cache_num_ways = 16;
2051         dc->caps.max_cab_allocation_bytes = 67108864; // 64MB = 1024 * 1024 * 64
2052         dc->caps.subvp_fw_processing_delay_us = 15;
2053         dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
2054         dc->caps.subvp_swath_height_margin_lines = 16;
2055         dc->caps.subvp_pstate_allow_width_us = 20;
2056         dc->caps.subvp_vertical_int_margin_us = 30;
2057
2058         dc->caps.max_slave_planes = 2;
2059         dc->caps.max_slave_yuv_planes = 2;
2060         dc->caps.max_slave_rgb_planes = 2;
2061         dc->caps.post_blend_color_processing = true;
2062         dc->caps.force_dp_tps4_for_cp2520 = true;
2063         dc->caps.dp_hpo = true;
2064         dc->caps.dp_hdmi21_pcon_support = true;
2065         dc->caps.edp_dsc_support = true;
2066         dc->caps.extended_aux_timeout_support = true;
2067         dc->caps.dmcub_support = true;
2068
2069         /* Color pipeline capabilities */
2070         dc->caps.color.dpp.dcn_arch = 1;
2071         dc->caps.color.dpp.input_lut_shared = 0;
2072         dc->caps.color.dpp.icsc = 1;
2073         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2074         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2075         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2076         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2077         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2078         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2079         dc->caps.color.dpp.post_csc = 1;
2080         dc->caps.color.dpp.gamma_corr = 1;
2081         dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2082
2083         dc->caps.color.dpp.hw_3d_lut = 1;
2084         dc->caps.color.dpp.ogam_ram = 0;  // no OGAM in DPP since DCN1
2085         // no OGAM ROM on DCN2 and later ASICs
2086         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2087         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2088         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2089         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2090         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2091         dc->caps.color.dpp.ocsc = 0;
2092
2093         dc->caps.color.mpc.gamut_remap = 1;
2094         dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
2095         dc->caps.color.mpc.ogam_ram = 1;
2096         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2097         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2098         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2099         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2100         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2101         dc->caps.color.mpc.ocsc = 1;
2102
2103         /* Use pipe context based otg sync logic */
2104         dc->config.use_pipe_ctx_sync_logic = true;
2105
2106         /* read VBIOS LTTPR caps */
2107         {
2108                 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2109                         enum bp_result bp_query_result;
2110                         uint8_t is_vbios_lttpr_enable = 0;
2111
2112                         bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2113                         dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2114                 }
2115
2116                 /* interop bit is implicit */
2117                 {
2118                         dc->caps.vbios_lttpr_aware = true;
2119                 }
2120         }
2121
2122         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2123                 dc->debug = debug_defaults_drv;
2124         else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2125                 dc->debug = debug_defaults_diags;
2126         } else
2127                 dc->debug = debug_defaults_diags;
2128         // Init the vm_helper
2129         if (dc->vm_helper)
2130                 vm_helper_init(dc->vm_helper, 16);
2131
2132         /*************************************************
2133          *  Create resources                             *
2134          *************************************************/
2135
2136         /* Clock Sources for Pixel Clock*/
2137         pool->base.clock_sources[DCN32_CLK_SRC_PLL0] =
2138                         dcn32_clock_source_create(ctx, ctx->dc_bios,
2139                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
2140                                 &clk_src_regs[0], false);
2141         pool->base.clock_sources[DCN32_CLK_SRC_PLL1] =
2142                         dcn32_clock_source_create(ctx, ctx->dc_bios,
2143                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
2144                                 &clk_src_regs[1], false);
2145         pool->base.clock_sources[DCN32_CLK_SRC_PLL2] =
2146                         dcn32_clock_source_create(ctx, ctx->dc_bios,
2147                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
2148                                 &clk_src_regs[2], false);
2149         pool->base.clock_sources[DCN32_CLK_SRC_PLL3] =
2150                         dcn32_clock_source_create(ctx, ctx->dc_bios,
2151                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
2152                                 &clk_src_regs[3], false);
2153         pool->base.clock_sources[DCN32_CLK_SRC_PLL4] =
2154                         dcn32_clock_source_create(ctx, ctx->dc_bios,
2155                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
2156                                 &clk_src_regs[4], false);
2157
2158         pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL;
2159
2160         /* todo: not reuse phy_pll registers */
2161         pool->base.dp_clock_source =
2162                         dcn32_clock_source_create(ctx, ctx->dc_bios,
2163                                 CLOCK_SOURCE_ID_DP_DTO,
2164                                 &clk_src_regs[0], true);
2165
2166         for (i = 0; i < pool->base.clk_src_count; i++) {
2167                 if (pool->base.clock_sources[i] == NULL) {
2168                         dm_error("DC: failed to create clock sources!\n");
2169                         BREAK_TO_DEBUGGER();
2170                         goto create_fail;
2171                 }
2172         }
2173
2174         /* DCCG */
2175         pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2176         if (pool->base.dccg == NULL) {
2177                 dm_error("DC: failed to create dccg!\n");
2178                 BREAK_TO_DEBUGGER();
2179                 goto create_fail;
2180         }
2181
2182         /* DML */
2183         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
2184                 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
2185
2186         /* IRQ Service */
2187         init_data.ctx = dc->ctx;
2188         pool->base.irqs = dal_irq_service_dcn32_create(&init_data);
2189         if (!pool->base.irqs)
2190                 goto create_fail;
2191
2192         /* HUBBUB */
2193         pool->base.hubbub = dcn32_hubbub_create(ctx);
2194         if (pool->base.hubbub == NULL) {
2195                 BREAK_TO_DEBUGGER();
2196                 dm_error("DC: failed to create hubbub!\n");
2197                 goto create_fail;
2198         }
2199
2200         /* HUBPs, DPPs, OPPs, TGs, ABMs */
2201         for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2202
2203                 /* if pipe is disabled, skip instance of HW pipe,
2204                  * i.e, skip ASIC register instance
2205                  */
2206                 if (pipe_fuses & 1 << i)
2207                         continue;
2208
2209                 /* HUBPs */
2210                 pool->base.hubps[j] = dcn32_hubp_create(ctx, i);
2211                 if (pool->base.hubps[j] == NULL) {
2212                         BREAK_TO_DEBUGGER();
2213                         dm_error(
2214                                 "DC: failed to create hubps!\n");
2215                         goto create_fail;
2216                 }
2217
2218                 /* DPPs */
2219                 pool->base.dpps[j] = dcn32_dpp_create(ctx, i);
2220                 if (pool->base.dpps[j] == NULL) {
2221                         BREAK_TO_DEBUGGER();
2222                         dm_error(
2223                                 "DC: failed to create dpps!\n");
2224                         goto create_fail;
2225                 }
2226
2227                 /* OPPs */
2228                 pool->base.opps[j] = dcn32_opp_create(ctx, i);
2229                 if (pool->base.opps[j] == NULL) {
2230                         BREAK_TO_DEBUGGER();
2231                         dm_error(
2232                                 "DC: failed to create output pixel processor!\n");
2233                         goto create_fail;
2234                 }
2235
2236                 /* TGs */
2237                 pool->base.timing_generators[j] = dcn32_timing_generator_create(
2238                                 ctx, i);
2239                 if (pool->base.timing_generators[j] == NULL) {
2240                         BREAK_TO_DEBUGGER();
2241                         dm_error("DC: failed to create tg!\n");
2242                         goto create_fail;
2243                 }
2244
2245                 /* ABMs */
2246                 pool->base.multiple_abms[j] = dmub_abm_create(ctx,
2247                                 &abm_regs[i],
2248                                 &abm_shift,
2249                                 &abm_mask);
2250                 if (pool->base.multiple_abms[j] == NULL) {
2251                         dm_error("DC: failed to create abm for pipe %d!\n", i);
2252                         BREAK_TO_DEBUGGER();
2253                         goto create_fail;
2254                 }
2255
2256                 /* index for resource pool arrays for next valid pipe */
2257                 j++;
2258         }
2259
2260         /* PSR */
2261         pool->base.psr = dmub_psr_create(ctx);
2262         if (pool->base.psr == NULL) {
2263                 dm_error("DC: failed to create psr obj!\n");
2264                 BREAK_TO_DEBUGGER();
2265                 goto create_fail;
2266         }
2267
2268         /* MPCCs */
2269         pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
2270         if (pool->base.mpc == NULL) {
2271                 BREAK_TO_DEBUGGER();
2272                 dm_error("DC: failed to create mpc!\n");
2273                 goto create_fail;
2274         }
2275
2276         /* DSCs */
2277         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2278                 pool->base.dscs[i] = dcn32_dsc_create(ctx, i);
2279                 if (pool->base.dscs[i] == NULL) {
2280                         BREAK_TO_DEBUGGER();
2281                         dm_error("DC: failed to create display stream compressor %d!\n", i);
2282                         goto create_fail;
2283                 }
2284         }
2285
2286         /* DWB */
2287         if (!dcn32_dwbc_create(ctx, &pool->base)) {
2288                 BREAK_TO_DEBUGGER();
2289                 dm_error("DC: failed to create dwbc!\n");
2290                 goto create_fail;
2291         }
2292
2293         /* MMHUBBUB */
2294         if (!dcn32_mmhubbub_create(ctx, &pool->base)) {
2295                 BREAK_TO_DEBUGGER();
2296                 dm_error("DC: failed to create mcif_wb!\n");
2297                 goto create_fail;
2298         }
2299
2300         /* AUX and I2C */
2301         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2302                 pool->base.engines[i] = dcn32_aux_engine_create(ctx, i);
2303                 if (pool->base.engines[i] == NULL) {
2304                         BREAK_TO_DEBUGGER();
2305                         dm_error(
2306                                 "DC:failed to create aux engine!!\n");
2307                         goto create_fail;
2308                 }
2309                 pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i);
2310                 if (pool->base.hw_i2cs[i] == NULL) {
2311                         BREAK_TO_DEBUGGER();
2312                         dm_error(
2313                                 "DC:failed to create hw i2c!!\n");
2314                         goto create_fail;
2315                 }
2316                 pool->base.sw_i2cs[i] = NULL;
2317         }
2318
2319         /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2320         if (!resource_construct(num_virtual_links, dc, &pool->base,
2321                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2322                         &res_create_funcs : &res_create_maximus_funcs)))
2323                         goto create_fail;
2324
2325         /* HW Sequencer init functions and Plane caps */
2326         dcn32_hw_sequencer_init_functions(dc);
2327
2328         dc->caps.max_planes =  pool->base.pipe_count;
2329
2330         for (i = 0; i < dc->caps.max_planes; ++i)
2331                 dc->caps.planes[i] = plane_cap;
2332
2333         dc->cap_funcs = cap_funcs;
2334
2335         if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2336                 ddc_init_data.ctx = dc->ctx;
2337                 ddc_init_data.link = NULL;
2338                 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2339                 ddc_init_data.id.enum_id = 0;
2340                 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2341                 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
2342         } else {
2343                 pool->base.oem_device = NULL;
2344         }
2345
2346         DC_FP_END();
2347
2348         return true;
2349
2350 create_fail:
2351
2352         DC_FP_END();
2353
2354         dcn32_resource_destruct(pool);
2355
2356         return false;
2357 }
2358
2359 struct resource_pool *dcn32_create_resource_pool(
2360                 const struct dc_init_data *init_data,
2361                 struct dc *dc)
2362 {
2363         struct dcn32_resource_pool *pool =
2364                 kzalloc(sizeof(struct dcn32_resource_pool), GFP_KERNEL);
2365
2366         if (!pool)
2367                 return NULL;
2368
2369         if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool))
2370                 return &pool->base;
2371
2372         BREAK_TO_DEBUGGER();
2373         kfree(pool);
2374         return NULL;
2375 }
2376
2377 static struct pipe_ctx *find_idle_secondary_pipe_check_mpo(
2378                 struct resource_context *res_ctx,
2379                 const struct resource_pool *pool,
2380                 const struct pipe_ctx *primary_pipe)
2381 {
2382         int i;
2383         struct pipe_ctx *secondary_pipe = NULL;
2384         struct pipe_ctx *next_odm_mpo_pipe = NULL;
2385         int primary_index, preferred_pipe_idx;
2386         struct pipe_ctx *old_primary_pipe = NULL;
2387
2388         /*
2389          * Modified from find_idle_secondary_pipe
2390          * With windowed MPO and ODM, we want to avoid the case where we want a
2391          *  free pipe for the left side but the free pipe is being used on the
2392          *  right side.
2393          * Add check on current_state if the primary_pipe is the left side,
2394          *  to check the right side ( primary_pipe->next_odm_pipe ) to see if
2395          *  it is using a pipe for MPO ( primary_pipe->next_odm_pipe->bottom_pipe )
2396          * - If so, then don't use this pipe
2397          * EXCEPTION - 3 plane ( 2 MPO plane ) case
2398          * - in this case, the primary pipe has already gotten a free pipe for the
2399          *  MPO window in the left
2400          * - when it tries to get a free pipe for the MPO window on the right,
2401          *  it will see that it is already assigned to the right side
2402          *  ( primary_pipe->next_odm_pipe ).  But in this case, we want this
2403          *  free pipe, since it will be for the right side.  So add an
2404          *  additional condition, that skipping the free pipe on the right only
2405          *  applies if the primary pipe has no bottom pipe currently assigned
2406          */
2407         if (primary_pipe) {
2408                 primary_index = primary_pipe->pipe_idx;
2409                 old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index];
2410                 if ((old_primary_pipe->next_odm_pipe) && (old_primary_pipe->next_odm_pipe->bottom_pipe)
2411                         && (!primary_pipe->bottom_pipe))
2412                         next_odm_mpo_pipe = old_primary_pipe->next_odm_pipe->bottom_pipe;
2413
2414                 preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
2415                 if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) &&
2416                         !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) {
2417                         secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2418                         secondary_pipe->pipe_idx = preferred_pipe_idx;
2419                 }
2420         }
2421
2422         /*
2423          * search backwards for the second pipe to keep pipe
2424          * assignment more consistent
2425          */
2426         if (!secondary_pipe)
2427                 for (i = pool->pipe_count - 1; i >= 0; i--) {
2428                         if ((res_ctx->pipe_ctx[i].stream == NULL) &&
2429                                 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) {
2430                                 secondary_pipe = &res_ctx->pipe_ctx[i];
2431                                 secondary_pipe->pipe_idx = i;
2432                                 break;
2433                         }
2434                 }
2435
2436         return secondary_pipe;
2437 }
2438
2439 struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
2440                 struct dc_state *state,
2441                 const struct resource_pool *pool,
2442                 struct dc_stream_state *stream,
2443                 struct pipe_ctx *head_pipe)
2444 {
2445         struct resource_context *res_ctx = &state->res_ctx;
2446         struct pipe_ctx *idle_pipe, *pipe;
2447         struct resource_context *old_ctx = &stream->ctx->dc->current_state->res_ctx;
2448         int head_index;
2449
2450         if (!head_pipe)
2451                 ASSERT(0);
2452
2453         /*
2454          * Modified from dcn20_acquire_idle_pipe_for_layer
2455          * Check if head_pipe in old_context already has bottom_pipe allocated.
2456          * - If so, check if that pipe is available in the current context.
2457          * --  If so, reuse pipe from old_context
2458          */
2459         head_index = head_pipe->pipe_idx;
2460         pipe = &old_ctx->pipe_ctx[head_index];
2461         if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) {
2462                 idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx];
2463                 idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx;
2464         } else {
2465                 idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe);
2466                 if (!idle_pipe)
2467                         return NULL;
2468         }
2469
2470         idle_pipe->stream = head_pipe->stream;
2471         idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
2472         idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
2473
2474         idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
2475         idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
2476         idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
2477         idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
2478
2479         return idle_pipe;
2480 }