drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dm_services.h"
  28 #include "dm_helpers.h"
  29 #include "core_types.h"
  30 #include "resource.h"
  31 #include "dccg.h"
  32 #include "dce/dce_hwseq.h"
  33 #include "dcn30/dcn30_cm_common.h"
  34 #include "reg_helper.h"
  35 #include "abm.h"
  36 #include "hubp.h"
  37 #include "dchubbub.h"
  38 #include "timing_generator.h"
  39 #include "opp.h"
  40 #include "ipp.h"
  41 #include "mpc.h"
  42 #include "mcif_wb.h"
  43 #include "dc_dmub_srv.h"
  44 #include "link_hwss.h"
  45 #include "dpcd_defs.h"
  46 #include "dcn32_hwseq.h"
  47 #include "clk_mgr.h"
  48 #include "dsc.h"
  49 #include "dcn20/dcn20_optc.h"
  50 #include "dce/dmub_hw_lock_mgr.h"
  51 #include "dcn32_resource.h"
  52 #include "link.h"
  53
  54 #define DC_LOGGER_INIT(logger)
  55
  56 #define CTX \
  57         hws->ctx
  58 #define REG(reg)\
  59         hws->regs->reg
  60 #define DC_LOGGER \
  61                 dc->ctx->logger
  62
  63
  64 #undef FN
  65 #define FN(reg_name, field_name) \
  66         hws->shifts->field_name, hws->masks->field_name
  67
  68 void dcn32_dsc_pg_control(
  69                 struct dce_hwseq *hws,
  70                 unsigned int dsc_inst,
  71                 bool power_on)
  72 {
  73         uint32_t power_gate = power_on ? 0 : 1;
  74         uint32_t pwr_status = power_on ? 0 : 2;
  75         uint32_t org_ip_request_cntl = 0;
  76
  77         if (hws->ctx->dc->debug.disable_dsc_power_gate)
  78                 return;
  79
  80         REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
  81         if (org_ip_request_cntl == 0)
  82                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
  83
  84         switch (dsc_inst) {
  85         case 0: /* DSC0 */
  86                 REG_UPDATE(DOMAIN16_PG_CONFIG,
  87                                 DOMAIN_POWER_GATE, power_gate);
  88
  89                 REG_WAIT(DOMAIN16_PG_STATUS,
  90                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
  91                                 1, 1000);
  92                 break;
  93         case 1: /* DSC1 */
  94                 REG_UPDATE(DOMAIN17_PG_CONFIG,
  95                                 DOMAIN_POWER_GATE, power_gate);
  96
  97                 REG_WAIT(DOMAIN17_PG_STATUS,
  98                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
  99                                 1, 1000);
 100                 break;
 101         case 2: /* DSC2 */
 102                 REG_UPDATE(DOMAIN18_PG_CONFIG,
 103                                 DOMAIN_POWER_GATE, power_gate);
 104
 105                 REG_WAIT(DOMAIN18_PG_STATUS,
 106                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
 107                                 1, 1000);
 108                 break;
 109         case 3: /* DSC3 */
 110                 REG_UPDATE(DOMAIN19_PG_CONFIG,
 111                                 DOMAIN_POWER_GATE, power_gate);
 112
 113                 REG_WAIT(DOMAIN19_PG_STATUS,
 114                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
 115                                 1, 1000);
 116                 break;
 117         default:
 118                 BREAK_TO_DEBUGGER();
 119                 break;
 120         }
 121
 122         if (org_ip_request_cntl == 0)
 123                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
 124 }
 125
 126
 127 void dcn32_enable_power_gating_plane(
 128         struct dce_hwseq *hws,
 129         bool enable)
 130 {
 131         bool force_on = true; /* disable power gating */
 132         uint32_t org_ip_request_cntl = 0;
 133
 134         if (enable)
 135                 force_on = false;
 136
 137         REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
 138         if (org_ip_request_cntl == 0)
 139                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
 140
 141         /* DCHUBP0/1/2/3 */
 142         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 143         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 144         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 145         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 146
 147         /* DCS0/1/2/3 */
 148         REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 149         REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 150         REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 151         REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 152
 153         if (org_ip_request_cntl == 0)
 154                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
 155 }
 156
 157 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
 158 {
 159         uint32_t power_gate = power_on ? 0 : 1;
 160         uint32_t pwr_status = power_on ? 0 : 2;
 161
 162         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 163                 return;
 164
 165         if (REG(DOMAIN0_PG_CONFIG) == 0)
 166                 return;
 167
 168         switch (hubp_inst) {
 169         case 0:
 170                 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
 171                 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
 172                 break;
 173         case 1:
 174                 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
 175                 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
 176                 break;
 177         case 2:
 178                 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
 179                 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
 180                 break;
 181         case 3:
 182                 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
 183                 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
 184                 break;
 185         default:
 186                 BREAK_TO_DEBUGGER();
 187                 break;
 188         }
 189 }
 190
 191 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc)
 192 {
 193         int i;
 194
 195     /* First, check no-memory-request case */
 196         for (i = 0; i < dc->current_state->stream_count; i++) {
 197                 if ((dc->current_state->stream_status[i].plane_count) &&
 198                         (dc->current_state->streams[i]->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED))
 199                         /* Fail eligibility on a visible stream */
 200                         break;
 201         }
 202
 203         if (i == dc->current_state->stream_count)
 204                 return true;
 205
 206         return false;
 207 }
 208
 209
 210 /* This function loops through every surface that needs to be cached in CAB for SS,
 211  * and calculates the total number of ways required to store all surfaces (primary,
 212  * meta, cursor).
 213  */
 214 static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)
 215 {
 216         int i;
 217         uint8_t num_ways = 0;
 218         uint32_t mall_ss_size_bytes = 0;
 219
 220         mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes;
 221         // TODO add additional logic for PSR active stream exclusion optimization
 222         // mall_ss_psr_active_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes;
 223
 224         // Include cursor size for CAB allocation
 225         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 226                 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i];
 227
 228                 if (!pipe->stream || !pipe->plane_state)
 229                         continue;
 230
 231                 mall_ss_size_bytes += dcn32_helper_calculate_mall_bytes_for_cursor(dc, pipe, false);
 232         }
 233
 234         // Convert number of cache lines required to number of ways
 235         if (dc->debug.force_mall_ss_num_ways > 0) {
 236                 num_ways = dc->debug.force_mall_ss_num_ways;
 237         } else {
 238                 num_ways = dcn32_helper_mall_bytes_to_ways(dc, mall_ss_size_bytes);
 239         }
 240
 241         return num_ways;
 242 }
 243
 244 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)
 245 {
 246         union dmub_rb_cmd cmd;
 247         uint8_t ways, i;
 248         int j;
 249         bool mall_ss_unsupported = false;
 250         struct dc_plane_state *plane = NULL;
 251
 252         if (!dc->ctx->dmub_srv)
 253                 return false;
 254
 255         for (i = 0; i < dc->current_state->stream_count; i++) {
 256                 /* MALL SS messaging is not supported with PSR at this time */
 257                 if (dc->current_state->streams[i] != NULL &&
 258                                 dc->current_state->streams[i]->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED)
 259                         return false;
 260         }
 261
 262         if (enable) {
 263                 if (dc->current_state) {
 264
 265                         /* 1. Check no memory request case for CAB.
 266                          * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message
 267                          */
 268                         if (dcn32_check_no_memory_request_for_cab(dc)) {
 269                                 /* Enable no-memory-requests case */
 270                                 memset(&cmd, 0, sizeof(cmd));
 271                                 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
 272                                 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ;
 273                                 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
 274
 275                                 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
 276
 277                                 return true;
 278                         }
 279
 280                         /* 2. Check if all surfaces can fit in CAB.
 281                          * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message
 282                          * and configure HUBP's to fetch from MALL
 283                          */
 284                         ways = dcn32_calculate_cab_allocation(dc, dc->current_state);
 285
 286                         /* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo,
 287                          * or TMZ surface, don't try to enter MALL.
 288                          */
 289                         for (i = 0; i < dc->current_state->stream_count; i++) {
 290                                 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {
 291                                         plane = dc->current_state->stream_status[i].plane_states[j];
 292
 293                                         if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO ||
 294                                                         plane->address.tmz_surface) {
 295                                                 mall_ss_unsupported = true;
 296                                                 break;
 297                                         }
 298                                 }
 299                                 if (mall_ss_unsupported)
 300                                         break;
 301                         }
 302                         if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) {
 303                                 memset(&cmd, 0, sizeof(cmd));
 304                                 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
 305                                 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;
 306                                 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
 307                                 cmd.cab.cab_alloc_ways = ways;
 308
 309                                 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
 310
 311                                 return true;
 312                         }
 313
 314                 }
 315                 return false;
 316         }
 317
 318         /* Disable CAB */
 319         memset(&cmd, 0, sizeof(cmd));
 320         cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
 321         cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION;
 322         cmd.cab.header.payload_bytes =
 323                         sizeof(cmd.cab) - sizeof(cmd.cab.header);
 324
 325         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 326
 327         return true;
 328 }
 329
 330 /* Send DMCUB message with SubVP pipe info
 331  * - For each pipe in context, populate payload with required SubVP information
 332  *   if the pipe is using SubVP for MCLK switch
 333  * - This function must be called while the DMUB HW lock is acquired by driver
 334  */
 335 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context)
 336 {
 337         int i;
 338         bool enable_subvp = false;
 339
 340         if (!dc->ctx || !dc->ctx->dmub_srv)
 341                 return;
 342
 343         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 344                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 345
 346                 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.paired_stream &&
 347                                 pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN) {
 348                         // There is at least 1 SubVP pipe, so enable SubVP
 349                         enable_subvp = true;
 350                         break;
 351                 }
 352         }
 353         dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp);
 354 }
 355
 356 /* Sub-Viewport DMUB lock needs to be acquired by driver whenever SubVP is active and:
 357  * 1. Any full update for any SubVP main pipe
 358  * 2. Any immediate flip for any SubVP pipe
 359  * 3. Any flip for DRR pipe
 360  * 4. If SubVP was previously in use (i.e. in old context)
 361  */
 362 void dcn32_subvp_pipe_control_lock(struct dc *dc,
 363                 struct dc_state *context,
 364                 bool lock,
 365                 bool should_lock_all_pipes,
 366                 struct pipe_ctx *top_pipe_to_program,
 367                 bool subvp_prev_use)
 368 {
 369         unsigned int i = 0;
 370         bool subvp_immediate_flip = false;
 371         bool subvp_in_use = false;
 372         struct pipe_ctx *pipe;
 373
 374         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 375                 pipe = &context->res_ctx.pipe_ctx[i];
 376
 377                 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
 378                         subvp_in_use = true;
 379                         break;
 380                 }
 381         }
 382
 383         if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) {
 384                 if (top_pipe_to_program->stream->mall_stream_config.type == SUBVP_MAIN &&
 385                                 top_pipe_to_program->plane_state->flip_immediate)
 386                         subvp_immediate_flip = true;
 387         }
 388
 389         // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared.
 390         if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip)) || (!subvp_in_use && subvp_prev_use)) {
 391                 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
 392
 393                 if (!lock) {
 394                         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 395                                 pipe = &context->res_ctx.pipe_ctx[i];
 396                                 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN &&
 397                                                 should_lock_all_pipes)
 398                                         pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);
 399                         }
 400                 }
 401
 402                 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;
 403                 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;
 404                 hw_lock_cmd.bits.lock = lock;
 405                 hw_lock_cmd.bits.should_release = !lock;
 406                 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);
 407         }
 408 }
 409
 410 void dcn32_subvp_pipe_control_lock_fast(union block_sequence_params *params)
 411 {
 412         struct dc *dc = params->subvp_pipe_control_lock_fast_params.dc;
 413         bool lock = params->subvp_pipe_control_lock_fast_params.lock;
 414         struct pipe_ctx *pipe_ctx = params->subvp_pipe_control_lock_fast_params.pipe_ctx;
 415         bool subvp_immediate_flip = false;
 416
 417         if (pipe_ctx && pipe_ctx->stream && pipe_ctx->plane_state) {
 418                 if (pipe_ctx->stream->mall_stream_config.type == SUBVP_MAIN &&
 419                                 pipe_ctx->plane_state->flip_immediate)
 420                         subvp_immediate_flip = true;
 421         }
 422
 423         // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared.
 424         if (subvp_immediate_flip) {
 425                 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
 426
 427                 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;
 428                 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;
 429                 hw_lock_cmd.bits.lock = lock;
 430                 hw_lock_cmd.bits.should_release = !lock;
 431                 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);
 432         }
 433 }
 434
 435 bool dcn32_set_mpc_shaper_3dlut(
 436         struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream)
 437 {
 438         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 439         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 440         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 441         bool result = false;
 442
 443         const struct pwl_params *shaper_lut = NULL;
 444         //get the shaper lut params
 445         if (stream->func_shaper) {
 446                 if (stream->func_shaper->type == TF_TYPE_HWPWL)
 447                         shaper_lut = &stream->func_shaper->pwl;
 448                 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
 449                         cm_helper_translate_curve_to_hw_format(stream->ctx,
 450                                         stream->func_shaper,
 451                                         &dpp_base->shaper_params, true);
 452                         shaper_lut = &dpp_base->shaper_params;
 453                 }
 454         }
 455
 456         if (stream->lut3d_func &&
 457                 stream->lut3d_func->state.bits.initialized == 1) {
 458
 459                 result = mpc->funcs->program_3dlut(mpc,
 460                                                                 &stream->lut3d_func->lut_3d,
 461                                                                 mpcc_id);
 462
 463                 result = mpc->funcs->program_shaper(mpc,
 464                                                                 shaper_lut,
 465                                                                 mpcc_id);
 466         }
 467
 468         return result;
 469 }
 470
 471 bool dcn32_set_mcm_luts(
 472         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 473 {
 474         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 475         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 476         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 477         bool result = true;
 478         struct pwl_params *lut_params = NULL;
 479
 480         // 1D LUT
 481         if (plane_state->blend_tf) {
 482                 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
 483                         lut_params = &plane_state->blend_tf->pwl;
 484                 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
 485                         cm_helper_translate_curve_to_hw_format(plane_state->ctx,
 486                                         plane_state->blend_tf,
 487                                         &dpp_base->regamma_params, false);
 488                         lut_params = &dpp_base->regamma_params;
 489                 }
 490         }
 491         result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);
 492
 493         // Shaper
 494         if (plane_state->in_shaper_func) {
 495                 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
 496                         lut_params = &plane_state->in_shaper_func->pwl;
 497                 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
 498                         // TODO: dpp_base replace
 499                         ASSERT(false);
 500                         cm_helper_translate_curve_to_hw_format(plane_state->ctx,
 501                                         plane_state->in_shaper_func,
 502                                         &dpp_base->shaper_params, true);
 503                         lut_params = &dpp_base->shaper_params;
 504                 }
 505         }
 506
 507         result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);
 508
 509         // 3D
 510         if (plane_state->lut3d_func && plane_state->lut3d_func->state.bits.initialized == 1)
 511                 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id);
 512         else
 513                 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id);
 514
 515         return result;
 516 }
 517
 518 bool dcn32_set_input_transfer_func(struct dc *dc,
 519                                 struct pipe_ctx *pipe_ctx,
 520                                 const struct dc_plane_state *plane_state)
 521 {
 522         struct dce_hwseq *hws = dc->hwseq;
 523         struct mpc *mpc = dc->res_pool->mpc;
 524         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 525
 526         enum dc_transfer_func_predefined tf;
 527         bool result = true;
 528         struct pwl_params *params = NULL;
 529
 530         if (mpc == NULL || plane_state == NULL)
 531                 return false;
 532
 533         tf = TRANSFER_FUNCTION_UNITY;
 534
 535         if (plane_state->in_transfer_func &&
 536                 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED)
 537                 tf = plane_state->in_transfer_func->tf;
 538
 539         dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);
 540
 541         if (plane_state->in_transfer_func) {
 542                 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL)
 543                         params = &plane_state->in_transfer_func->pwl;
 544                 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS &&
 545                         cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func,
 546                                         &dpp_base->degamma_params, false))
 547                         params = &dpp_base->degamma_params;
 548         }
 549
 550         dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
 551
 552         if (pipe_ctx->stream_res.opp &&
 553                         pipe_ctx->stream_res.opp->ctx &&
 554                         hws->funcs.set_mcm_luts)
 555                 result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state);
 556
 557         return result;
 558 }
 559
 560 bool dcn32_set_output_transfer_func(struct dc *dc,
 561                                 struct pipe_ctx *pipe_ctx,
 562                                 const struct dc_stream_state *stream)
 563 {
 564         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 565         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 566         struct pwl_params *params = NULL;
 567         bool ret = false;
 568
 569         /* program OGAM or 3DLUT only for the top pipe*/
 570         if (resource_is_pipe_type(pipe_ctx, OPP_HEAD)) {
 571                 /*program shaper and 3dlut in MPC*/
 572                 ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);
 573                 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
 574                         if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
 575                                 params = &stream->out_transfer_func->pwl;
 576                         else if (pipe_ctx->stream->out_transfer_func->type ==
 577                                         TF_TYPE_DISTRIBUTED_POINTS &&
 578                                         cm3_helper_translate_curve_to_hw_format(
 579                                         stream->out_transfer_func,
 580                                         &mpc->blender_params, false))
 581                                 params = &mpc->blender_params;
 582                         /* there are no ROM LUTs in OUTGAM */
 583                         if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
 584                                 BREAK_TO_DEBUGGER();
 585                 }
 586         }
 587
 588         mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
 589         return ret;
 590 }
 591
 592 /* Program P-State force value according to if pipe is using SubVP / FPO or not:
 593  * 1. Reset P-State force on all pipes first
 594  * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB)
 595  */
 596 void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context)
 597 {
 598         int i;
 599
 600         /* Unforce p-state for each pipe if it is not FPO or SubVP.
 601          * For FPO and SubVP, if it's already forced disallow, leave
 602          * it as disallow.
 603          */
 604         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 605                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 606                 struct hubp *hubp = pipe->plane_res.hubp;
 607
 608                 if (!pipe->stream || !(pipe->stream->mall_stream_config.type == SUBVP_MAIN ||
 609                     pipe->stream->fpo_in_use)) {
 610                         if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
 611                                 hubp->funcs->hubp_update_force_pstate_disallow(hubp, false);
 612                 }
 613
 614                 /* Today only FPO uses cursor P-State force. Only clear cursor P-State force
 615                  * if it's not FPO.
 616                  */
 617                 if (!pipe->stream || !pipe->stream->fpo_in_use) {
 618                         if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow)
 619                                 hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, false);
 620                 }
 621         }
 622
 623         /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false.
 624          */
 625         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 626                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 627                 struct hubp *hubp = pipe->plane_res.hubp;
 628
 629                 if (pipe->stream && pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
 630                         if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
 631                                 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true);
 632                 }
 633
 634                 if (pipe->stream && pipe->stream->fpo_in_use) {
 635                         if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
 636                                 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true);
 637                         /* For now only force cursor p-state disallow for FPO
 638                          * Needs to be added for subvp once FW side gets updated
 639                          */
 640                         if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow)
 641                                 hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, true);
 642                 }
 643         }
 644 }
 645
 646 /* Update MALL_SEL register based on if pipe / plane
 647  * is a phantom pipe, main pipe, and if using MALL
 648  * for SS.
 649  */
 650 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context)
 651 {
 652         int i;
 653         unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context);
 654         bool cache_cursor = false;
 655
 656         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 657                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 658                 struct hubp *hubp = pipe->plane_res.hubp;
 659
 660                 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {
 661                         int cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;
 662
 663                         switch (hubp->curs_attr.color_format) {
 664                         case CURSOR_MODE_MONO:
 665                                 cursor_size /= 2;
 666                                 break;
 667                         case CURSOR_MODE_COLOR_1BIT_AND:
 668                         case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
 669                         case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
 670                                 cursor_size *= 4;
 671                                 break;
 672
 673                         case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
 674                         case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
 675                         default:
 676                                 cursor_size *= 8;
 677                                 break;
 678                         }
 679
 680                         if (cursor_size > 16384)
 681                                 cache_cursor = true;
 682
 683                         if (pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
 684                                         hubp->funcs->hubp_update_mall_sel(hubp, 1, false);
 685                         } else {
 686                                 // MALL not supported with Stereo3D
 687                                 hubp->funcs->hubp_update_mall_sel(hubp,
 688                                         num_ways <= dc->caps.cache_num_ways &&
 689                                         pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
 690                                         pipe->plane_state->address.type !=  PLN_ADDR_TYPE_GRPH_STEREO &&
 691                                         !pipe->plane_state->address.tmz_surface ? 2 : 0,
 692                                                         cache_cursor);
 693                         }
 694                 }
 695         }
 696 }
 697
 698 /* Program the sub-viewport pipe configuration after the main / phantom pipes
 699  * have been programmed in hardware.
 700  * 1. Update force P-State for all the main pipes (disallow P-state)
 701  * 2. Update MALL_SEL register
 702  * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes
 703  */
 704 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context)
 705 {
 706         int i;
 707         struct dce_hwseq *hws = dc->hwseq;
 708
 709         // Don't force p-state disallow -- can't block dummy p-state
 710
 711         // Update MALL_SEL register for each pipe
 712         if (hws && hws->funcs.update_mall_sel)
 713                 hws->funcs.update_mall_sel(dc, context);
 714
 715         // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes
 716         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 717                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 718                 struct hubp *hubp = pipe->plane_res.hubp;
 719
 720                 if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) {
 721                         /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases
 722                          *      - need to investigate single pipe MPO + SubVP case to
 723                          *        see if CURSOR_REQ_MODE will be back to 1 for SubVP
 724                          *        when it should be 0 for MPO
 725                          */
 726                         if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
 727                                 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true);
 728                         }
 729                 }
 730         }
 731 }
 732
 733 static void dcn32_initialize_min_clocks(struct dc *dc)
 734 {
 735         struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk;
 736
 737         clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ;
 738         clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000;
 739         clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000;
 740         clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000;
 741         clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000;
 742         clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
 743         clocks->fclk_p_state_change_support = true;
 744         clocks->p_state_change_support = true;
 745         if (dc->debug.disable_boot_optimizations) {
 746                 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000;
 747         } else {
 748                 /* Even though DPG_EN = 1 for the connected display, it still requires the
 749                  * correct timing so we cannot set DISPCLK to min freq or it could cause
 750                  * audio corruption. Read current DISPCLK from DENTIST and request the same
 751                  * freq to ensure that the timing is valid and unchanged.
 752                  */
 753                 clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);
 754         }
 755
 756         dc->clk_mgr->funcs->update_clocks(
 757                         dc->clk_mgr,
 758                         dc->current_state,
 759                         true);
 760 }
 761
 762 void dcn32_init_hw(struct dc *dc)
 763 {
 764         struct abm **abms = dc->res_pool->multiple_abms;
 765         struct dce_hwseq *hws = dc->hwseq;
 766         struct dc_bios *dcb = dc->ctx->dc_bios;
 767         struct resource_pool *res_pool = dc->res_pool;
 768         int i;
 769         int edp_num;
 770         uint32_t backlight = MAX_BACKLIGHT_LEVEL;
 771
 772         if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
 773                 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
 774
 775         // Initialize the dccg
 776         if (res_pool->dccg->funcs->dccg_init)
 777                 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
 778
 779         if (!dcb->funcs->is_accelerated_mode(dcb)) {
 780                 hws->funcs.bios_golden_init(dc);
 781                 hws->funcs.disable_vga(dc->hwseq);
 782         }
 783
 784         // Set default OPTC memory power states
 785         if (dc->debug.enable_mem_low_power.bits.optc) {
 786                 // Shutdown when unassigned and light sleep in VBLANK
 787                 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
 788         }
 789
 790         if (dc->debug.enable_mem_low_power.bits.vga) {
 791                 // Power down VGA memory
 792                 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
 793         }
 794
 795         if (dc->ctx->dc_bios->fw_info_valid) {
 796                 res_pool->ref_clocks.xtalin_clock_inKhz =
 797                                 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
 798
 799                 if (res_pool->dccg && res_pool->hubbub) {
 800                         (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
 801                                         dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
 802                                         &res_pool->ref_clocks.dccg_ref_clock_inKhz);
 803
 804                         (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
 805                                         res_pool->ref_clocks.dccg_ref_clock_inKhz,
 806                                         &res_pool->ref_clocks.dchub_ref_clock_inKhz);
 807                 } else {
 808                         // Not all ASICs have DCCG sw component
 809                         res_pool->ref_clocks.dccg_ref_clock_inKhz =
 810                                         res_pool->ref_clocks.xtalin_clock_inKhz;
 811                         res_pool->ref_clocks.dchub_ref_clock_inKhz =
 812                                         res_pool->ref_clocks.xtalin_clock_inKhz;
 813                 }
 814         } else
 815                 ASSERT_CRITICAL(false);
 816
 817         for (i = 0; i < dc->link_count; i++) {
 818                 /* Power up AND update implementation according to the
 819                  * required signal (which may be different from the
 820                  * default signal on connector).
 821                  */
 822                 struct dc_link *link = dc->links[i];
 823
 824                 link->link_enc->funcs->hw_init(link->link_enc);
 825
 826                 /* Check for enabled DIG to identify enabled display */
 827                 if (link->link_enc->funcs->is_dig_enabled &&
 828                         link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
 829                         link->link_status.link_active = true;
 830                         link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
 831                         if (link->link_enc->funcs->fec_is_active &&
 832                                         link->link_enc->funcs->fec_is_active(link->link_enc))
 833                                 link->fec_state = dc_link_fec_enabled;
 834                 }
 835         }
 836
 837         /* enable_power_gating_plane before dsc_pg_control because
 838          * FORCEON = 1 with hw default value on bootup, resume from s3
 839          */
 840         if (hws->funcs.enable_power_gating_plane)
 841                 hws->funcs.enable_power_gating_plane(dc->hwseq, true);
 842
 843         /* we want to turn off all dp displays before doing detection */
 844         dc->link_srv->blank_all_dp_displays(dc);
 845
 846         /* If taking control over from VBIOS, we may want to optimize our first
 847          * mode set, so we need to skip powering down pipes until we know which
 848          * pipes we want to use.
 849          * Otherwise, if taking control is not possible, we need to power
 850          * everything down.
 851          */
 852         if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
 853                 /* Disable boot optimizations means power down everything including PHY, DIG,
 854                  * and OTG (i.e. the boot is not optimized because we do a full power down).
 855                  */
 856                 if (dc->hwss.enable_accelerated_mode && dc->debug.disable_boot_optimizations)
 857                         dc->hwss.enable_accelerated_mode(dc, dc->current_state);
 858                 else
 859                         hws->funcs.init_pipes(dc, dc->current_state);
 860
 861                 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
 862                         dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
 863                                         !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
 864
 865                 dcn32_initialize_min_clocks(dc);
 866
 867                 /* On HW init, allow idle optimizations after pipes have been turned off.
 868                  *
 869                  * In certain D3 cases (i.e. BOCO / BOMACO) it's possible that hardware state
 870                  * is reset (i.e. not in idle at the time hw init is called), but software state
 871                  * still has idle_optimizations = true, so we must disable idle optimizations first
 872                  * (i.e. set false), then re-enable (set true).
 873                  */
 874                 dc_allow_idle_optimizations(dc, false);
 875                 dc_allow_idle_optimizations(dc, true);
 876         }
 877
 878         /* In headless boot cases, DIG may be turned
 879          * on which causes HW/SW discrepancies.
 880          * To avoid this, power down hardware on boot
 881          * if DIG is turned on and seamless boot not enabled
 882          */
 883         if (!dc->config.seamless_boot_edp_requested) {
 884                 struct dc_link *edp_links[MAX_NUM_EDP];
 885                 struct dc_link *edp_link;
 886
 887                 dc_get_edp_links(dc, edp_links, &edp_num);
 888                 if (edp_num) {
 889                         for (i = 0; i < edp_num; i++) {
 890                                 edp_link = edp_links[i];
 891                                 if (edp_link->link_enc->funcs->is_dig_enabled &&
 892                                                 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
 893                                                 dc->hwss.edp_backlight_control &&
 894                                                 dc->hwss.power_down &&
 895                                                 dc->hwss.edp_power_control) {
 896                                         dc->hwss.edp_backlight_control(edp_link, false);
 897                                         dc->hwss.power_down(dc);
 898                                         dc->hwss.edp_power_control(edp_link, false);
 899                                 }
 900                         }
 901                 } else {
 902                         for (i = 0; i < dc->link_count; i++) {
 903                                 struct dc_link *link = dc->links[i];
 904
 905                                 if (link->link_enc->funcs->is_dig_enabled &&
 906                                                 link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
 907                                                 dc->hwss.power_down) {
 908                                         dc->hwss.power_down(dc);
 909                                         break;
 910                                 }
 911
 912                         }
 913                 }
 914         }
 915
 916         for (i = 0; i < res_pool->audio_count; i++) {
 917                 struct audio *audio = res_pool->audios[i];
 918
 919                 audio->funcs->hw_init(audio);
 920         }
 921
 922         for (i = 0; i < dc->link_count; i++) {
 923                 struct dc_link *link = dc->links[i];
 924
 925                 if (link->panel_cntl)
 926                         backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
 927         }
 928
 929         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 930                 if (abms[i] != NULL && abms[i]->funcs != NULL)
 931                         abms[i]->funcs->abm_init(abms[i], backlight);
 932         }
 933
 934         /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
 935         REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 936
 937         if (!dc->debug.disable_clock_gate) {
 938                 /* enable all DCN clock gating */
 939                 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
 940
 941                 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
 942
 943                 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
 944         }
 945
 946         if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
 947                 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
 948
 949         if (dc->clk_mgr->funcs->notify_wm_ranges)
 950                 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
 951
 952         if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)
 953                 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
 954
 955         if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
 956                 dc->res_pool->hubbub->funcs->force_pstate_change_control(
 957                                 dc->res_pool->hubbub, false, false);
 958
 959         if (dc->res_pool->hubbub->funcs->init_crb)
 960                 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
 961
 962         if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0)
 963                 dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc);
 964
 965         // Get DMCUB capabilities
 966         if (dc->ctx->dmub_srv) {
 967                 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);
 968                 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
 969                 dc->caps.dmub_caps.subvp_psr = dc->ctx->dmub_srv->dmub->feature_caps.subvp_psr_support;
 970                 dc->caps.dmub_caps.gecc_enable = dc->ctx->dmub_srv->dmub->feature_caps.gecc_enable;
 971                 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch;
 972         }
 973 }
 974
 975 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
 976                 int opp_cnt)
 977 {
 978         bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing);
 979         int flow_ctrl_cnt;
 980
 981         if (opp_cnt >= 2)
 982                 hblank_halved = true;
 983
 984         flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
 985                         stream->timing.h_border_left -
 986                         stream->timing.h_border_right;
 987
 988         if (hblank_halved)
 989                 flow_ctrl_cnt /= 2;
 990
 991         /* ODM combine 4:1 case */
 992         if (opp_cnt == 4)
 993                 flow_ctrl_cnt /= 2;
 994
 995         return flow_ctrl_cnt;
 996 }
 997
 998 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
 999 {
1000         struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
1001         struct dc_stream_state *stream = pipe_ctx->stream;
1002         struct pipe_ctx *odm_pipe;
1003         int opp_cnt = 1;
1004
1005         ASSERT(dsc);
1006         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1007                 opp_cnt++;
1008
1009         if (enable) {
1010                 struct dsc_config dsc_cfg;
1011                 struct dsc_optc_config dsc_optc_cfg;
1012                 enum optc_dsc_mode optc_dsc_mode;
1013
1014                 /* Enable DSC hw block */
1015                 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
1016                 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
1017                 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
1018                 dsc_cfg.color_depth = stream->timing.display_color_depth;
1019                 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
1020                 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
1021                 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
1022                 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
1023
1024                 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
1025                 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
1026                 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1027                         struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
1028
1029                         ASSERT(odm_dsc);
1030                         odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
1031                         odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
1032                 }
1033                 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
1034                 dsc_cfg.pic_width *= opp_cnt;
1035
1036                 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
1037
1038                 /* Enable DSC in OPTC */
1039                 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
1040                 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
1041                                                         optc_dsc_mode,
1042                                                         dsc_optc_cfg.bytes_per_pixel,
1043                                                         dsc_optc_cfg.slice_width);
1044         } else {
1045                 /* disable DSC in OPTC */
1046                 pipe_ctx->stream_res.tg->funcs->set_dsc_config(
1047                                 pipe_ctx->stream_res.tg,
1048                                 OPTC_DSC_DISABLED, 0, 0);
1049
1050                 /* disable DSC block */
1051                 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
1052                 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1053                         ASSERT(odm_pipe->stream_res.dsc);
1054                         odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);
1055                 }
1056         }
1057 }
1058
1059 /*
1060 * Given any pipe_ctx, return the total ODM combine factor, and optionally return
1061 * the OPPids which are used
1062 * */
1063 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)
1064 {
1065         unsigned int opp_count = 1;
1066         struct pipe_ctx *odm_pipe;
1067
1068         /* First get to the top pipe */
1069         for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)
1070                 ;
1071
1072         /* First pipe is always used */
1073         if (opp_instances)
1074                 opp_instances[0] = odm_pipe->stream_res.opp->inst;
1075
1076         /* Find and count odm pipes, if any */
1077         for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1078                 if (opp_instances)
1079                         opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;
1080                 opp_count++;
1081         }
1082
1083         return opp_count;
1084 }
1085
1086 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
1087 {
1088         struct pipe_ctx *odm_pipe;
1089         int opp_cnt = 0;
1090         int opp_inst[MAX_PIPES] = {0};
1091         bool rate_control_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing));
1092         struct mpc_dwb_flow_control flow_control;
1093         struct mpc *mpc = dc->res_pool->mpc;
1094         int i;
1095
1096         opp_cnt = get_odm_config(pipe_ctx, opp_inst);
1097
1098         if (opp_cnt > 1)
1099                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
1100                                 pipe_ctx->stream_res.tg,
1101                                 opp_inst, opp_cnt,
1102                                 &pipe_ctx->stream->timing);
1103         else
1104                 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
1105                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1106
1107         rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
1108         flow_control.flow_ctrl_mode = 0;
1109         flow_control.flow_ctrl_cnt0 = 0x80;
1110         flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(pipe_ctx->stream, opp_cnt);
1111         if (mpc->funcs->set_out_rate_control) {
1112                 for (i = 0; i < opp_cnt; ++i) {
1113                         mpc->funcs->set_out_rate_control(
1114                                         mpc, opp_inst[i],
1115                                         true,
1116                                         rate_control_2x_pclk,
1117                                         &flow_control);
1118                 }
1119         }
1120
1121         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1122                 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
1123                                 odm_pipe->stream_res.opp,
1124                                 true);
1125         }
1126
1127         if (pipe_ctx->stream_res.dsc) {
1128                 struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
1129
1130                 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
1131
1132                 /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */
1133                 if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&
1134                                 current_pipe_ctx->next_odm_pipe->stream_res.dsc) {
1135                         struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc;
1136                         /* disconnect DSC block from stream */
1137                         dsc->funcs->dsc_disconnect(dsc);
1138                 }
1139         }
1140 }
1141
1142 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
1143 {
1144         struct dc_stream_state *stream = pipe_ctx->stream;
1145         unsigned int odm_combine_factor = 0;
1146         bool two_pix_per_container = false;
1147
1148         two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);
1149         odm_combine_factor = get_odm_config(pipe_ctx, NULL);
1150
1151         if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1152                 *k1_div = PIXEL_RATE_DIV_BY_1;
1153                 *k2_div = PIXEL_RATE_DIV_BY_1;
1154         } else if (dc_is_hdmi_tmds_signal(stream->signal) || dc_is_dvi_signal(stream->signal)) {
1155                 *k1_div = PIXEL_RATE_DIV_BY_1;
1156                 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1157                         *k2_div = PIXEL_RATE_DIV_BY_2;
1158                 else
1159                         *k2_div = PIXEL_RATE_DIV_BY_4;
1160         } else if (dc_is_dp_signal(stream->signal) || dc_is_virtual_signal(stream->signal)) {
1161                 if (two_pix_per_container) {
1162                         *k1_div = PIXEL_RATE_DIV_BY_1;
1163                         *k2_div = PIXEL_RATE_DIV_BY_2;
1164                 } else {
1165                         *k1_div = PIXEL_RATE_DIV_BY_1;
1166                         *k2_div = PIXEL_RATE_DIV_BY_4;
1167                         if ((odm_combine_factor == 2) || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
1168                                 *k2_div = PIXEL_RATE_DIV_BY_2;
1169                 }
1170         }
1171
1172         if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
1173                 ASSERT(false);
1174
1175         return odm_combine_factor;
1176 }
1177
1178 void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
1179 {
1180         uint32_t pix_per_cycle = 1;
1181         uint32_t odm_combine_factor = 1;
1182
1183         if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc)
1184                 return;
1185
1186         odm_combine_factor = get_odm_config(pipe_ctx, NULL);
1187         if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1
1188                 || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
1189                 pix_per_cycle = 2;
1190
1191         if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)
1192                 pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,
1193                                 pix_per_cycle);
1194 }
1195
1196 void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context)
1197 {
1198         unsigned int i;
1199         struct pipe_ctx *pipe = NULL;
1200         bool otg_disabled[MAX_PIPES] = {false};
1201
1202         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1203                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1204
1205                 if (!resource_is_pipe_type(pipe, OTG_MASTER))
1206                         continue;
1207
1208                 if ((pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))
1209                         && pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) {
1210                         pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);
1211                         reset_sync_context_for_pipe(dc, context, i);
1212                         otg_disabled[i] = true;
1213                 }
1214         }
1215
1216         hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);
1217
1218         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1219                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1220
1221                 if (otg_disabled[i])
1222                         pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
1223         }
1224 }
1225
1226 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,
1227                 struct dc_link_settings *link_settings)
1228 {
1229         struct encoder_unblank_param params = {0};
1230         struct dc_stream_state *stream = pipe_ctx->stream;
1231         struct dc_link *link = stream->link;
1232         struct dce_hwseq *hws = link->dc->hwseq;
1233         struct pipe_ctx *odm_pipe;
1234         uint32_t pix_per_cycle = 1;
1235
1236         params.opp_cnt = 1;
1237         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1238                 params.opp_cnt++;
1239
1240         /* only 3 items below are used by unblank */
1241         params.timing = pipe_ctx->stream->timing;
1242
1243         params.link_settings.link_rate = link_settings->link_rate;
1244
1245         if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1246                 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
1247                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(
1248                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
1249                                 pipe_ctx->stream_res.tg->inst);
1250         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1251                 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1
1252                         || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx)) {
1253                         params.timing.pix_clk_100hz /= 2;
1254                         pix_per_cycle = 2;
1255                 }
1256                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
1257                                 pipe_ctx->stream_res.stream_enc, pix_per_cycle > 1);
1258                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
1259         }
1260
1261         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP)
1262                 hws->funcs.edp_backlight_control(link, true);
1263 }
1264
1265 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)
1266 {
1267         struct dc *dc = pipe_ctx->stream->ctx->dc;
1268
1269         if (!is_h_timing_divisible_by_2(pipe_ctx->stream))
1270                 return false;
1271
1272         if (dc_is_dp_signal(pipe_ctx->stream->signal) && !dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) &&
1273                 dc->debug.enable_dp_dig_pixel_rate_div_policy)
1274                 return true;
1275         return false;
1276 }
1277
1278 static void apply_symclk_on_tx_off_wa(struct dc_link *link)
1279 {
1280         /* There are use cases where SYMCLK is referenced by OTG. For instance
1281          * for TMDS signal, OTG relies SYMCLK even if TX video output is off.
1282          * However current link interface will power off PHY when disabling link
1283          * output. This will turn off SYMCLK generated by PHY. The workaround is
1284          * to identify such case where SYMCLK is still in use by OTG when we
1285          * power off PHY. When this is detected, we will temporarily power PHY
1286          * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling
1287          * program_pix_clk interface. When OTG is disabled, we will then power
1288          * off PHY by calling disable link output again.
1289          *
1290          * In future dcn generations, we plan to rework transmitter control
1291          * interface so that we could have an option to set SYMCLK ON TX OFF
1292          * state in one step without this workaround
1293          */
1294
1295         struct dc *dc = link->ctx->dc;
1296         struct pipe_ctx *pipe_ctx = NULL;
1297         uint8_t i;
1298
1299         if (link->phy_state.symclk_ref_cnts.otg > 0) {
1300                 for (i = 0; i < MAX_PIPES; i++) {
1301                         pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1302                         if (resource_is_pipe_type(pipe_ctx, OPP_HEAD) && pipe_ctx->stream->link == link) {
1303                                 pipe_ctx->clock_source->funcs->program_pix_clk(
1304                                                 pipe_ctx->clock_source,
1305                                                 &pipe_ctx->stream_res.pix_clk_params,
1306                                                 dc->link_srv->dp_get_encoding_format(
1307                                                                 &pipe_ctx->link_config.dp_link_settings),
1308                                                 &pipe_ctx->pll_settings);
1309                                 link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
1310                                 break;
1311                         }
1312                 }
1313         }
1314 }
1315
1316 void dcn32_disable_link_output(struct dc_link *link,
1317                 const struct link_resource *link_res,
1318                 enum signal_type signal)
1319 {
1320         struct dc *dc = link->ctx->dc;
1321         const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
1322         struct dmcu *dmcu = dc->res_pool->dmcu;
1323
1324         if (signal == SIGNAL_TYPE_EDP &&
1325                         link->dc->hwss.edp_backlight_control)
1326                 link->dc->hwss.edp_backlight_control(link, false);
1327         else if (dmcu != NULL && dmcu->funcs->lock_phy)
1328                 dmcu->funcs->lock_phy(dmcu);
1329
1330         link_hwss->disable_link_output(link, link_res, signal);
1331         link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
1332
1333         if (signal == SIGNAL_TYPE_EDP &&
1334                         link->dc->hwss.edp_backlight_control)
1335                 link->dc->hwss.edp_power_control(link, false);
1336         else if (dmcu != NULL && dmcu->funcs->lock_phy)
1337                 dmcu->funcs->unlock_phy(dmcu);
1338
1339         dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
1340
1341         apply_symclk_on_tx_off_wa(link);
1342 }
1343
1344 /* For SubVP the main pipe can have a viewport position change
1345  * without a full update. In this case we must also update the
1346  * viewport positions for the phantom pipe accordingly.
1347  */
1348 void dcn32_update_phantom_vp_position(struct dc *dc,
1349                 struct dc_state *context,
1350                 struct pipe_ctx *phantom_pipe)
1351 {
1352         uint32_t i;
1353         struct dc_plane_state *phantom_plane = phantom_pipe->plane_state;
1354
1355         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1356                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1357
1358                 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN &&
1359                                 pipe->stream->mall_stream_config.paired_stream == phantom_pipe->stream) {
1360                         if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) {
1361
1362                                 phantom_plane->src_rect.x = pipe->plane_state->src_rect.x;
1363                                 phantom_plane->src_rect.y = pipe->plane_state->src_rect.y;
1364                                 phantom_plane->clip_rect.x = pipe->plane_state->clip_rect.x;
1365                                 phantom_plane->dst_rect.x = pipe->plane_state->dst_rect.x;
1366                                 phantom_plane->dst_rect.y = pipe->plane_state->dst_rect.y;
1367
1368                                 phantom_pipe->plane_state->update_flags.bits.position_change = 1;
1369                                 resource_build_scaling_params(phantom_pipe);
1370                                 return;
1371                         }
1372                 }
1373         }
1374 }
1375
1376 /* Treat the phantom pipe as if it needs to be fully enabled.
1377  * If the pipe was previously in use but not phantom, it would
1378  * have been disabled earlier in the sequence so we need to run
1379  * the full enable sequence.
1380  */
1381 void dcn32_apply_update_flags_for_phantom(struct pipe_ctx *phantom_pipe)
1382 {
1383         phantom_pipe->update_flags.raw = 0;
1384         if (phantom_pipe->stream && phantom_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
1385                 if (resource_is_pipe_type(phantom_pipe, DPP_PIPE)) {
1386                         phantom_pipe->update_flags.bits.enable = 1;
1387                         phantom_pipe->update_flags.bits.mpcc = 1;
1388                         phantom_pipe->update_flags.bits.dppclk = 1;
1389                         phantom_pipe->update_flags.bits.hubp_interdependent = 1;
1390                         phantom_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1391                         phantom_pipe->update_flags.bits.gamut_remap = 1;
1392                         phantom_pipe->update_flags.bits.scaler = 1;
1393                         phantom_pipe->update_flags.bits.viewport = 1;
1394                         phantom_pipe->update_flags.bits.det_size = 1;
1395                         if (resource_is_pipe_type(phantom_pipe, OTG_MASTER)) {
1396                                 phantom_pipe->update_flags.bits.odm = 1;
1397                                 phantom_pipe->update_flags.bits.global_sync = 1;
1398                         }
1399                 }
1400         }
1401 }
1402
1403 bool dcn32_dsc_pg_status(
1404                 struct dce_hwseq *hws,
1405                 unsigned int dsc_inst)
1406 {
1407         uint32_t pwr_status = 0;
1408
1409         switch (dsc_inst) {
1410         case 0: /* DSC0 */
1411                 REG_GET(DOMAIN16_PG_STATUS,
1412                                 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1413                 break;
1414         case 1: /* DSC1 */
1415
1416                 REG_GET(DOMAIN17_PG_STATUS,
1417                                 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1418                 break;
1419         case 2: /* DSC2 */
1420                 REG_GET(DOMAIN18_PG_STATUS,
1421                                 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1422                 break;
1423         case 3: /* DSC3 */
1424                 REG_GET(DOMAIN19_PG_STATUS,
1425                                 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1426                 break;
1427         default:
1428                 BREAK_TO_DEBUGGER();
1429                 break;
1430         }
1431
1432         return pwr_status == 0;
1433 }
1434
1435 void dcn32_update_dsc_pg(struct dc *dc,
1436                 struct dc_state *context,
1437                 bool safe_to_disable)
1438 {
1439         struct dce_hwseq *hws = dc->hwseq;
1440         int i;
1441
1442         for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {
1443                 struct display_stream_compressor *dsc = dc->res_pool->dscs[i];
1444                 bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst);
1445
1446                 if (context->res_ctx.is_dsc_acquired[i]) {
1447                         if (!is_dsc_ungated) {
1448                                 hws->funcs.dsc_pg_control(hws, dsc->inst, true);
1449                         }
1450                 } else if (safe_to_disable) {
1451                         if (is_dsc_ungated) {
1452                                 hws->funcs.dsc_pg_control(hws, dsc->inst, false);
1453                         }
1454                 }
1455         }
1456 }
1457
1458 void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context)
1459 {
1460         unsigned int i;
1461
1462         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1463                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1464                 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1465
1466                 /* If an active, non-phantom pipe is being transitioned into a phantom
1467                  * pipe, wait for the double buffer update to complete first before we do
1468                  * ANY phantom pipe programming.
1469                  */
1470                 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM &&
1471                                 old_pipe->stream && old_pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) {
1472                         old_pipe->stream_res.tg->funcs->wait_for_state(
1473                                         old_pipe->stream_res.tg,
1474                                         CRTC_STATE_VBLANK);
1475                         old_pipe->stream_res.tg->funcs->wait_for_state(
1476                                         old_pipe->stream_res.tg,
1477                                         CRTC_STATE_VACTIVE);
1478                 }
1479         }
1480         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1481                 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
1482
1483                 if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
1484                         // If old context or new context has phantom pipes, apply
1485                         // the phantom timings now. We can't change the phantom
1486                         // pipe configuration safely without driver acquiring
1487                         // the DMCUB lock first.
1488                         dc->hwss.apply_ctx_to_hw(dc, context);
1489                         break;
1490                 }
1491         }
1492 }
1493
1494 /* Blank pixel data during initialization */
1495 void dcn32_init_blank(
1496                 struct dc *dc,
1497                 struct timing_generator *tg)
1498 {
1499         struct dce_hwseq *hws = dc->hwseq;
1500         enum dc_color_space color_space;
1501         struct tg_color black_color = {0};
1502         struct output_pixel_processor *opp = NULL;
1503         struct output_pixel_processor *bottom_opp = NULL;
1504         uint32_t num_opps, opp_id_src0, opp_id_src1;
1505         uint32_t otg_active_width, otg_active_height;
1506         uint32_t i;
1507
1508         /* program opp dpg blank color */
1509         color_space = COLOR_SPACE_SRGB;
1510         color_space_to_black_color(dc, color_space, &black_color);
1511
1512         /* get the OTG active size */
1513         tg->funcs->get_otg_active_size(tg,
1514                         &otg_active_width,
1515                         &otg_active_height);
1516
1517         /* get the OPTC source */
1518         tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
1519
1520         if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) {
1521                 ASSERT(false);
1522                 return;
1523         }
1524
1525         for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
1526                 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) {
1527                         opp = dc->res_pool->opps[i];
1528                         break;
1529                 }
1530         }
1531
1532         if (num_opps == 2) {
1533                 otg_active_width = otg_active_width / 2;
1534
1535                 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) {
1536                         ASSERT(false);
1537                         return;
1538                 }
1539                 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
1540                         if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src1) {
1541                                 bottom_opp = dc->res_pool->opps[i];
1542                                 break;
1543                         }
1544                 }
1545         }
1546
1547         if (opp && opp->funcs->opp_set_disp_pattern_generator)
1548                 opp->funcs->opp_set_disp_pattern_generator(
1549                                 opp,
1550                                 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
1551                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
1552                                 COLOR_DEPTH_UNDEFINED,
1553                                 &black_color,
1554                                 otg_active_width,
1555                                 otg_active_height,
1556                                 0);
1557
1558         if (num_opps == 2) {
1559                 if (bottom_opp && bottom_opp->funcs->opp_set_disp_pattern_generator) {
1560                         bottom_opp->funcs->opp_set_disp_pattern_generator(
1561                                         bottom_opp,
1562                                         CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
1563                                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
1564                                         COLOR_DEPTH_UNDEFINED,
1565                                         &black_color,
1566                                         otg_active_width,
1567                                         otg_active_height,
1568                                         0);
1569                         hws->funcs.wait_for_blank_complete(bottom_opp);
1570                 }
1571         }
1572
1573         if (opp)
1574                 hws->funcs.wait_for_blank_complete(opp);
1575 }