drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dm_services.h"
  28 #include "dc.h"
  29
  30 #include "dcn31/dcn31_init.h"
  31
  32 #include "resource.h"
  33 #include "include/irq_service_interface.h"
  34 #include "dcn315_resource.h"
  35
  36 #include "dcn20/dcn20_resource.h"
  37 #include "dcn30/dcn30_resource.h"
  38 #include "dcn31/dcn31_resource.h"
  39
  40 #include "dcn10/dcn10_ipp.h"
  41 #include "dcn30/dcn30_hubbub.h"
  42 #include "dcn31/dcn31_hubbub.h"
  43 #include "dcn30/dcn30_mpc.h"
  44 #include "dcn31/dcn31_hubp.h"
  45 #include "irq/dcn315/irq_service_dcn315.h"
  46 #include "dcn30/dcn30_dpp.h"
  47 #include "dcn31/dcn31_optc.h"
  48 #include "dcn20/dcn20_hwseq.h"
  49 #include "dcn30/dcn30_hwseq.h"
  50 #include "dce110/dce110_hwseq.h"
  51 #include "dcn30/dcn30_opp.h"
  52 #include "dcn20/dcn20_dsc.h"
  53 #include "dcn30/dcn30_vpg.h"
  54 #include "dcn30/dcn30_afmt.h"
  55 #include "dcn30/dcn30_dio_stream_encoder.h"
  56 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
  57 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
  58 #include "dcn31/dcn31_apg.h"
  59 #include "dcn31/dcn31_dio_link_encoder.h"
  60 #include "dcn31/dcn31_vpg.h"
  61 #include "dcn31/dcn31_afmt.h"
  62 #include "dce/dce_clock_source.h"
  63 #include "dce/dce_audio.h"
  64 #include "dce/dce_hwseq.h"
  65 #include "clk_mgr.h"
  66 #include "virtual/virtual_stream_encoder.h"
  67 #include "dce110/dce110_resource.h"
  68 #include "dml/display_mode_vba.h"
  69 #include "dml/dcn31/dcn31_fpu.h"
  70 #include "dcn31/dcn31_dccg.h"
  71 #include "dcn10/dcn10_resource.h"
  72 #include "dcn31/dcn31_panel_cntl.h"
  73
  74 #include "dcn30/dcn30_dwb.h"
  75 #include "dcn30/dcn30_mmhubbub.h"
  76
  77 #include "dcn/dcn_3_1_5_offset.h"
  78 #include "dcn/dcn_3_1_5_sh_mask.h"
  79 #include "dpcs/dpcs_4_2_2_offset.h"
  80 #include "dpcs/dpcs_4_2_2_sh_mask.h"
  81
  82 #define NBIO_BASE__INST0_SEG0                      0x00000000
  83 #define NBIO_BASE__INST0_SEG1                      0x00000014
  84 #define NBIO_BASE__INST0_SEG2                      0x00000D20
  85 #define NBIO_BASE__INST0_SEG3                      0x00010400
  86 #define NBIO_BASE__INST0_SEG4                      0x0241B000
  87 #define NBIO_BASE__INST0_SEG5                      0x04040000
  88
  89 #define DPCS_BASE__INST0_SEG0                      0x00000012
  90 #define DPCS_BASE__INST0_SEG1                      0x000000C0
  91 #define DPCS_BASE__INST0_SEG2                      0x000034C0
  92 #define DPCS_BASE__INST0_SEG3                      0x00009000
  93 #define DPCS_BASE__INST0_SEG4                      0x02403C00
  94 #define DPCS_BASE__INST0_SEG5                      0
  95
  96 #define DCN_BASE__INST0_SEG0                       0x00000012
  97 #define DCN_BASE__INST0_SEG1                       0x000000C0
  98 #define DCN_BASE__INST0_SEG2                       0x000034C0
  99 #define DCN_BASE__INST0_SEG3                       0x00009000
 100 #define DCN_BASE__INST0_SEG4                       0x02403C00
 101 #define DCN_BASE__INST0_SEG5                       0
 102
 103 #define regBIF_BX_PF2_RSMU_INDEX                                                                        0x0000
 104 #define regBIF_BX_PF2_RSMU_INDEX_BASE_IDX                                                               1
 105 #define regBIF_BX_PF2_RSMU_DATA                                                                         0x0001
 106 #define regBIF_BX_PF2_RSMU_DATA_BASE_IDX                                                                1
 107 #define regBIF_BX2_BIOS_SCRATCH_6                                                                       0x003e
 108 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX                                                              1
 109 #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT                                                         0x0
 110 #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK                                                           0xFFFFFFFFL
 111 #define regBIF_BX2_BIOS_SCRATCH_2                                                                       0x003a
 112 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX                                                              1
 113 #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT                                                         0x0
 114 #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK                                                           0xFFFFFFFFL
 115 #define regBIF_BX2_BIOS_SCRATCH_3                                                                       0x003b
 116 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX                                                              1
 117 #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT                                                         0x0
 118 #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK                                                           0xFFFFFFFFL
 119
 120 #define regDCHUBBUB_DEBUG_CTRL_0                                              0x04d6
 121 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                     2
 122 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT                               0x10
 123 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK                                 0x01FF0000L
 124
 125 #include "reg_helper.h"
 126 #include "dce/dmub_abm.h"
 127 #include "dce/dmub_psr.h"
 128 #include "dce/dce_aux.h"
 129 #include "dce/dce_i2c.h"
 130
 131 #include "dml/dcn30/display_mode_vba_30.h"
 132 #include "vm_helper.h"
 133 #include "dcn20/dcn20_vmid.h"
 134
 135 #include "link_enc_cfg.h"
 136
 137 #define DCN3_15_MAX_DET_SIZE 384
 138 #define DCN3_15_CRB_SEGMENT_SIZE_KB 64
 139 #define DCN3_15_MAX_DET_SEGS (DCN3_15_MAX_DET_SIZE / DCN3_15_CRB_SEGMENT_SIZE_KB)
 140 /* Minimum 3 extra segments need to be in compbuf and claimable to guarantee seamless mpo transitions */
 141 #define MIN_RESERVED_DET_SEGS 3
 142
 143 enum dcn31_clk_src_array_id {
 144         DCN31_CLK_SRC_PLL0,
 145         DCN31_CLK_SRC_PLL1,
 146         DCN31_CLK_SRC_PLL2,
 147         DCN31_CLK_SRC_PLL3,
 148         DCN31_CLK_SRC_PLL4,
 149         DCN30_CLK_SRC_TOTAL
 150 };
 151
 152 /* begin *********************
 153  * macros to expend register list macro defined in HW object header file
 154  */
 155
 156 /* DCN */
 157 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 158
 159 #define BASE(seg) BASE_INNER(seg)
 160
 161 #define SR(reg_name)\
 162                 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 163                                         reg ## reg_name
 164
 165 #define SRI(reg_name, block, id)\
 166         .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 167                                         reg ## block ## id ## _ ## reg_name
 168
 169 #define SRI2(reg_name, block, id)\
 170         .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 171                                         reg ## reg_name
 172
 173 #define SRIR(var_name, reg_name, block, id)\
 174         .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 175                                         reg ## block ## id ## _ ## reg_name
 176
 177 #define SRII(reg_name, block, id)\
 178         .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 179                                         reg ## block ## id ## _ ## reg_name
 180
 181 #define SRII_MPC_RMU(reg_name, block, id)\
 182         .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 183                                         reg ## block ## id ## _ ## reg_name
 184
 185 #define SRII_DWB(reg_name, temp_name, block, id)\
 186         .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 187                                         reg ## block ## id ## _ ## temp_name
 188
 189 #define SF_DWB2(reg_name, block, id, field_name, post_fix)      \
 190         .field_name = reg_name ## __ ## field_name ## post_fix
 191
 192 #define DCCG_SRII(reg_name, block, id)\
 193         .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 194                                         reg ## block ## id ## _ ## reg_name
 195
 196 #define VUPDATE_SRII(reg_name, block, id)\
 197         .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 198                                         reg ## reg_name ## _ ## block ## id
 199
 200 /* NBIO */
 201 #define NBIO_BASE_INNER(seg) \
 202         NBIO_BASE__INST0_SEG ## seg
 203
 204 #define NBIO_BASE(seg) \
 205         NBIO_BASE_INNER(seg)
 206
 207 #define NBIO_SR(reg_name)\
 208                 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
 209                                         regBIF_BX2_ ## reg_name
 210
 211 static const struct bios_registers bios_regs = {
 212                 NBIO_SR(BIOS_SCRATCH_3),
 213                 NBIO_SR(BIOS_SCRATCH_6)
 214 };
 215
 216 #define clk_src_regs(index, pllid)\
 217 [index] = {\
 218         CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
 219 }
 220
 221 static const struct dce110_clk_src_regs clk_src_regs[] = {
 222         clk_src_regs(0, A),
 223         clk_src_regs(1, B),
 224         clk_src_regs(2, C),
 225         clk_src_regs(3, D),
 226         clk_src_regs(4, E)
 227 };
 228
 229 static const struct dce110_clk_src_shift cs_shift = {
 230                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 231 };
 232
 233 static const struct dce110_clk_src_mask cs_mask = {
 234                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 235 };
 236
 237 #define abm_regs(id)\
 238 [id] = {\
 239                 ABM_DCN302_REG_LIST(id)\
 240 }
 241
 242 static const struct dce_abm_registers abm_regs[] = {
 243                 abm_regs(0),
 244                 abm_regs(1),
 245                 abm_regs(2),
 246                 abm_regs(3),
 247 };
 248
 249 static const struct dce_abm_shift abm_shift = {
 250                 ABM_MASK_SH_LIST_DCN30(__SHIFT)
 251 };
 252
 253 static const struct dce_abm_mask abm_mask = {
 254                 ABM_MASK_SH_LIST_DCN30(_MASK)
 255 };
 256
 257 #define audio_regs(id)\
 258 [id] = {\
 259                 AUD_COMMON_REG_LIST(id)\
 260 }
 261
 262 static const struct dce_audio_registers audio_regs[] = {
 263         audio_regs(0),
 264         audio_regs(1),
 265         audio_regs(2),
 266         audio_regs(3),
 267         audio_regs(4),
 268         audio_regs(5),
 269         audio_regs(6)
 270 };
 271
 272 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 273                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 274                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 275                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 276
 277 static const struct dce_audio_shift audio_shift = {
 278                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 279 };
 280
 281 static const struct dce_audio_mask audio_mask = {
 282                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 283 };
 284
 285 #define vpg_regs(id)\
 286 [id] = {\
 287         VPG_DCN31_REG_LIST(id)\
 288 }
 289
 290 static const struct dcn31_vpg_registers vpg_regs[] = {
 291         vpg_regs(0),
 292         vpg_regs(1),
 293         vpg_regs(2),
 294         vpg_regs(3),
 295         vpg_regs(4),
 296         vpg_regs(5),
 297         vpg_regs(6),
 298         vpg_regs(7),
 299         vpg_regs(8),
 300         vpg_regs(9),
 301 };
 302
 303 static const struct dcn31_vpg_shift vpg_shift = {
 304         DCN31_VPG_MASK_SH_LIST(__SHIFT)
 305 };
 306
 307 static const struct dcn31_vpg_mask vpg_mask = {
 308         DCN31_VPG_MASK_SH_LIST(_MASK)
 309 };
 310
 311 #define afmt_regs(id)\
 312 [id] = {\
 313         AFMT_DCN31_REG_LIST(id)\
 314 }
 315
 316 static const struct dcn31_afmt_registers afmt_regs[] = {
 317         afmt_regs(0),
 318         afmt_regs(1),
 319         afmt_regs(2),
 320         afmt_regs(3),
 321         afmt_regs(4),
 322         afmt_regs(5)
 323 };
 324
 325 static const struct dcn31_afmt_shift afmt_shift = {
 326         DCN31_AFMT_MASK_SH_LIST(__SHIFT)
 327 };
 328
 329 static const struct dcn31_afmt_mask afmt_mask = {
 330         DCN31_AFMT_MASK_SH_LIST(_MASK)
 331 };
 332
 333 #define apg_regs(id)\
 334 [id] = {\
 335         APG_DCN31_REG_LIST(id)\
 336 }
 337
 338 static const struct dcn31_apg_registers apg_regs[] = {
 339         apg_regs(0),
 340         apg_regs(1),
 341         apg_regs(2),
 342         apg_regs(3)
 343 };
 344
 345 static const struct dcn31_apg_shift apg_shift = {
 346         DCN31_APG_MASK_SH_LIST(__SHIFT)
 347 };
 348
 349 static const struct dcn31_apg_mask apg_mask = {
 350                 DCN31_APG_MASK_SH_LIST(_MASK)
 351 };
 352
 353 #define stream_enc_regs(id)\
 354 [id] = {\
 355         SE_DCN3_REG_LIST(id)\
 356 }
 357
 358 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 359         stream_enc_regs(0),
 360         stream_enc_regs(1),
 361         stream_enc_regs(2),
 362         stream_enc_regs(3),
 363         stream_enc_regs(4)
 364 };
 365
 366 static const struct dcn10_stream_encoder_shift se_shift = {
 367                 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 368 };
 369
 370 static const struct dcn10_stream_encoder_mask se_mask = {
 371                 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
 372 };
 373
 374
 375 #define aux_regs(id)\
 376 [id] = {\
 377         DCN2_AUX_REG_LIST(id)\
 378 }
 379
 380 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 381                 aux_regs(0),
 382                 aux_regs(1),
 383                 aux_regs(2),
 384                 aux_regs(3),
 385                 aux_regs(4)
 386 };
 387
 388 #define hpd_regs(id)\
 389 [id] = {\
 390         HPD_REG_LIST(id)\
 391 }
 392
 393 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 394                 hpd_regs(0),
 395                 hpd_regs(1),
 396                 hpd_regs(2),
 397                 hpd_regs(3),
 398                 hpd_regs(4)
 399 };
 400
 401 #define link_regs(id, phyid)\
 402 [id] = {\
 403         LE_DCN31_REG_LIST(id), \
 404         UNIPHY_DCN2_REG_LIST(phyid), \
 405         DPCS_DCN31_REG_LIST(id), \
 406 }
 407
 408 static const struct dce110_aux_registers_shift aux_shift = {
 409         DCN_AUX_MASK_SH_LIST(__SHIFT)
 410 };
 411
 412 static const struct dce110_aux_registers_mask aux_mask = {
 413         DCN_AUX_MASK_SH_LIST(_MASK)
 414 };
 415
 416 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 417         link_regs(0, A),
 418         link_regs(1, B),
 419         link_regs(2, C),
 420         link_regs(3, D),
 421         link_regs(4, E)
 422 };
 423
 424 static const struct dcn10_link_enc_shift le_shift = {
 425         LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
 426         DPCS_DCN31_MASK_SH_LIST(__SHIFT)
 427 };
 428
 429 static const struct dcn10_link_enc_mask le_mask = {
 430         LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
 431         DPCS_DCN31_MASK_SH_LIST(_MASK)
 432 };
 433
 434 #define hpo_dp_stream_encoder_reg_list(id)\
 435 [id] = {\
 436         DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
 437 }
 438
 439 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
 440         hpo_dp_stream_encoder_reg_list(0),
 441         hpo_dp_stream_encoder_reg_list(1),
 442         hpo_dp_stream_encoder_reg_list(2),
 443         hpo_dp_stream_encoder_reg_list(3),
 444 };
 445
 446 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
 447         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
 448 };
 449
 450 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
 451         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
 452 };
 453
 454
 455 #define hpo_dp_link_encoder_reg_list(id)\
 456 [id] = {\
 457         DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
 458         DCN3_1_RDPCSTX_REG_LIST(0),\
 459         DCN3_1_RDPCSTX_REG_LIST(1),\
 460         DCN3_1_RDPCSTX_REG_LIST(2),\
 461         DCN3_1_RDPCSTX_REG_LIST(3),\
 462         DCN3_1_RDPCSTX_REG_LIST(4)\
 463 }
 464
 465 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
 466         hpo_dp_link_encoder_reg_list(0),
 467         hpo_dp_link_encoder_reg_list(1),
 468 };
 469
 470 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
 471         DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
 472 };
 473
 474 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
 475         DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
 476 };
 477
 478 #define dpp_regs(id)\
 479 [id] = {\
 480         DPP_REG_LIST_DCN30(id),\
 481 }
 482
 483 static const struct dcn3_dpp_registers dpp_regs[] = {
 484         dpp_regs(0),
 485         dpp_regs(1),
 486         dpp_regs(2),
 487         dpp_regs(3)
 488 };
 489
 490 static const struct dcn3_dpp_shift tf_shift = {
 491                 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
 492 };
 493
 494 static const struct dcn3_dpp_mask tf_mask = {
 495                 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
 496 };
 497
 498 #define opp_regs(id)\
 499 [id] = {\
 500         OPP_REG_LIST_DCN30(id),\
 501 }
 502
 503 static const struct dcn20_opp_registers opp_regs[] = {
 504         opp_regs(0),
 505         opp_regs(1),
 506         opp_regs(2),
 507         opp_regs(3)
 508 };
 509
 510 static const struct dcn20_opp_shift opp_shift = {
 511         OPP_MASK_SH_LIST_DCN20(__SHIFT)
 512 };
 513
 514 static const struct dcn20_opp_mask opp_mask = {
 515         OPP_MASK_SH_LIST_DCN20(_MASK)
 516 };
 517
 518 #define aux_engine_regs(id)\
 519 [id] = {\
 520         AUX_COMMON_REG_LIST0(id), \
 521         .AUXN_IMPCAL = 0, \
 522         .AUXP_IMPCAL = 0, \
 523         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 524 }
 525
 526 static const struct dce110_aux_registers aux_engine_regs[] = {
 527                 aux_engine_regs(0),
 528                 aux_engine_regs(1),
 529                 aux_engine_regs(2),
 530                 aux_engine_regs(3),
 531                 aux_engine_regs(4)
 532 };
 533
 534 #define dwbc_regs_dcn3(id)\
 535 [id] = {\
 536         DWBC_COMMON_REG_LIST_DCN30(id),\
 537 }
 538
 539 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 540         dwbc_regs_dcn3(0),
 541 };
 542
 543 static const struct dcn30_dwbc_shift dwbc30_shift = {
 544         DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 545 };
 546
 547 static const struct dcn30_dwbc_mask dwbc30_mask = {
 548         DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 549 };
 550
 551 #define mcif_wb_regs_dcn3(id)\
 552 [id] = {\
 553         MCIF_WB_COMMON_REG_LIST_DCN30(id),\
 554 }
 555
 556 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 557         mcif_wb_regs_dcn3(0)
 558 };
 559
 560 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 561         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 562 };
 563
 564 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 565         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
 566 };
 567
 568 #define dsc_regsDCN20(id)\
 569 [id] = {\
 570         DSC_REG_LIST_DCN20(id)\
 571 }
 572
 573 static const struct dcn20_dsc_registers dsc_regs[] = {
 574         dsc_regsDCN20(0),
 575         dsc_regsDCN20(1),
 576         dsc_regsDCN20(2)
 577 };
 578
 579 static const struct dcn20_dsc_shift dsc_shift = {
 580         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 581 };
 582
 583 static const struct dcn20_dsc_mask dsc_mask = {
 584         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 585 };
 586
 587 static const struct dcn30_mpc_registers mpc_regs = {
 588                 MPC_REG_LIST_DCN3_0(0),
 589                 MPC_REG_LIST_DCN3_0(1),
 590                 MPC_REG_LIST_DCN3_0(2),
 591                 MPC_REG_LIST_DCN3_0(3),
 592                 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 593                 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 594                 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
 595                 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
 596                 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 597 };
 598
 599 static const struct dcn30_mpc_shift mpc_shift = {
 600         MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 601 };
 602
 603 static const struct dcn30_mpc_mask mpc_mask = {
 604         MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 605 };
 606
 607 #define optc_regs(id)\
 608 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
 609
 610 static const struct dcn_optc_registers optc_regs[] = {
 611         optc_regs(0),
 612         optc_regs(1),
 613         optc_regs(2),
 614         optc_regs(3)
 615 };
 616
 617 static const struct dcn_optc_shift optc_shift = {
 618         OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
 619 };
 620
 621 static const struct dcn_optc_mask optc_mask = {
 622         OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
 623 };
 624
 625 #define hubp_regs(id)\
 626 [id] = {\
 627         HUBP_REG_LIST_DCN30(id)\
 628 }
 629
 630 static const struct dcn_hubp2_registers hubp_regs[] = {
 631                 hubp_regs(0),
 632                 hubp_regs(1),
 633                 hubp_regs(2),
 634                 hubp_regs(3)
 635 };
 636
 637
 638 static const struct dcn_hubp2_shift hubp_shift = {
 639                 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
 640 };
 641
 642 static const struct dcn_hubp2_mask hubp_mask = {
 643                 HUBP_MASK_SH_LIST_DCN31(_MASK)
 644 };
 645 static const struct dcn_hubbub_registers hubbub_reg = {
 646                 HUBBUB_REG_LIST_DCN31(0)
 647 };
 648
 649 static const struct dcn_hubbub_shift hubbub_shift = {
 650                 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
 651 };
 652
 653 static const struct dcn_hubbub_mask hubbub_mask = {
 654                 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
 655 };
 656
 657 static const struct dccg_registers dccg_regs = {
 658                 DCCG_REG_LIST_DCN31()
 659 };
 660
 661 static const struct dccg_shift dccg_shift = {
 662                 DCCG_MASK_SH_LIST_DCN31(__SHIFT)
 663 };
 664
 665 static const struct dccg_mask dccg_mask = {
 666                 DCCG_MASK_SH_LIST_DCN31(_MASK)
 667 };
 668
 669
 670 #define SRII2(reg_name_pre, reg_name_post, id)\
 671         .reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 672                         ## id ## _ ## reg_name_post ## _BASE_IDX) + \
 673                         reg ## reg_name_pre ## id ## _ ## reg_name_post
 674
 675
 676 #define HWSEQ_DCN31_REG_LIST()\
 677         SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
 678         SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
 679         SR(DIO_MEM_PWR_CTRL), \
 680         SR(ODM_MEM_PWR_CTRL3), \
 681         SR(DMU_MEM_PWR_CNTL), \
 682         SR(MMHUBBUB_MEM_PWR_CNTL), \
 683         SR(DCCG_GATE_DISABLE_CNTL), \
 684         SR(DCCG_GATE_DISABLE_CNTL2), \
 685         SR(DCFCLK_CNTL),\
 686         SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
 687         SRII(PIXEL_RATE_CNTL, OTG, 0), \
 688         SRII(PIXEL_RATE_CNTL, OTG, 1),\
 689         SRII(PIXEL_RATE_CNTL, OTG, 2),\
 690         SRII(PIXEL_RATE_CNTL, OTG, 3),\
 691         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
 692         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
 693         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
 694         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
 695         SR(MICROSECOND_TIME_BASE_DIV), \
 696         SR(MILLISECOND_TIME_BASE_DIV), \
 697         SR(DISPCLK_FREQ_CHANGE_CNTL), \
 698         SR(RBBMIF_TIMEOUT_DIS), \
 699         SR(RBBMIF_TIMEOUT_DIS_2), \
 700         SR(DCHUBBUB_CRC_CTRL), \
 701         SR(DPP_TOP0_DPP_CRC_CTRL), \
 702         SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
 703         SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
 704         SR(MPC_CRC_CTRL), \
 705         SR(MPC_CRC_RESULT_GB), \
 706         SR(MPC_CRC_RESULT_C), \
 707         SR(MPC_CRC_RESULT_AR), \
 708         SR(DOMAIN0_PG_CONFIG), \
 709         SR(DOMAIN1_PG_CONFIG), \
 710         SR(DOMAIN2_PG_CONFIG), \
 711         SR(DOMAIN3_PG_CONFIG), \
 712         SR(DOMAIN16_PG_CONFIG), \
 713         SR(DOMAIN17_PG_CONFIG), \
 714         SR(DOMAIN18_PG_CONFIG), \
 715         SR(DOMAIN0_PG_STATUS), \
 716         SR(DOMAIN1_PG_STATUS), \
 717         SR(DOMAIN2_PG_STATUS), \
 718         SR(DOMAIN3_PG_STATUS), \
 719         SR(DOMAIN16_PG_STATUS), \
 720         SR(DOMAIN17_PG_STATUS), \
 721         SR(DOMAIN18_PG_STATUS), \
 722         SR(D1VGA_CONTROL), \
 723         SR(D2VGA_CONTROL), \
 724         SR(D3VGA_CONTROL), \
 725         SR(D4VGA_CONTROL), \
 726         SR(D5VGA_CONTROL), \
 727         SR(D6VGA_CONTROL), \
 728         SR(DC_IP_REQUEST_CNTL), \
 729         SR(AZALIA_AUDIO_DTO), \
 730         SR(AZALIA_CONTROLLER_CLOCK_GATING), \
 731         SR(HPO_TOP_HW_CONTROL)
 732
 733 static const struct dce_hwseq_registers hwseq_reg = {
 734                 HWSEQ_DCN31_REG_LIST()
 735 };
 736
 737 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
 738         HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 739         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 740         HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
 741         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 742         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 743         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 744         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 745         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 746         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 747         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 748         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 749         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 750         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 751         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 752         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 753         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 754         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 755         HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 756         HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 757         HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 758         HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 759         HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 760         HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 761         HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 762         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 763         HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 764         HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 765         HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
 766         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 767         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
 768         HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
 769         HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
 770         HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
 771
 772 static const struct dce_hwseq_shift hwseq_shift = {
 773                 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
 774 };
 775
 776 static const struct dce_hwseq_mask hwseq_mask = {
 777                 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
 778 };
 779 #define vmid_regs(id)\
 780 [id] = {\
 781                 DCN20_VMID_REG_LIST(id)\
 782 }
 783
 784 static const struct dcn_vmid_registers vmid_regs[] = {
 785         vmid_regs(0),
 786         vmid_regs(1),
 787         vmid_regs(2),
 788         vmid_regs(3),
 789         vmid_regs(4),
 790         vmid_regs(5),
 791         vmid_regs(6),
 792         vmid_regs(7),
 793         vmid_regs(8),
 794         vmid_regs(9),
 795         vmid_regs(10),
 796         vmid_regs(11),
 797         vmid_regs(12),
 798         vmid_regs(13),
 799         vmid_regs(14),
 800         vmid_regs(15)
 801 };
 802
 803 static const struct dcn20_vmid_shift vmid_shifts = {
 804                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 805 };
 806
 807 static const struct dcn20_vmid_mask vmid_masks = {
 808                 DCN20_VMID_MASK_SH_LIST(_MASK)
 809 };
 810
 811 static const struct resource_caps res_cap_dcn31 = {
 812         .num_timing_generator = 4,
 813         .num_opp = 4,
 814         .num_video_plane = 4,
 815         .num_audio = 5,
 816         .num_stream_encoder = 5,
 817         .num_dig_link_enc = 5,
 818         .num_hpo_dp_stream_encoder = 4,
 819         .num_hpo_dp_link_encoder = 2,
 820         .num_pll = 5,
 821         .num_dwb = 1,
 822         .num_ddc = 5,
 823         .num_vmid = 16,
 824         .num_mpc_3dlut = 2,
 825         .num_dsc = 3,
 826 };
 827
 828 static const struct dc_plane_cap plane_cap = {
 829         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 830         .per_pixel_alpha = true,
 831
 832         .pixel_format_support = {
 833                         .argb8888 = true,
 834                         .nv12 = true,
 835                         .fp16 = true,
 836                         .p010 = true,
 837                         .ayuv = false,
 838         },
 839
 840         .max_upscale_factor = {
 841                         .argb8888 = 16000,
 842                         .nv12 = 16000,
 843                         .fp16 = 16000
 844         },
 845
 846         // 6:1 downscaling ratio: 1000/6 = 166.666
 847         .max_downscale_factor = {
 848                         .argb8888 = 167,
 849                         .nv12 = 167,
 850                         .fp16 = 167
 851         },
 852         64,
 853         64
 854 };
 855
 856 static const struct dc_debug_options debug_defaults_drv = {
 857         .disable_z10 = true, /*hw not support it*/
 858         .disable_dmcu = true,
 859         .force_abm_enable = false,
 860         .timing_trace = false,
 861         .clock_trace = true,
 862         .disable_pplib_clock_request = false,
 863         .pipe_split_policy = MPC_SPLIT_DYNAMIC,
 864         .force_single_disp_pipe_split = false,
 865         .disable_dcc = DCC_ENABLE,
 866         .vsr_support = true,
 867         .performance_trace = false,
 868         .max_downscale_src_width = 4096,/*upto true 4k*/
 869         .disable_pplib_wm_range = false,
 870         .scl_reset_length10 = true,
 871         .sanity_checks = false,
 872         .underflow_assert_delay_us = 0xFFFFFFFF,
 873         .dwb_fi_phase = -1, // -1 = disable,
 874         .dmub_command_table = true,
 875         .pstate_enabled = true,
 876         .use_max_lb = true,
 877         .enable_mem_low_power = {
 878                 .bits = {
 879                         .vga = true,
 880                         .i2c = true,
 881                         .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
 882                         .dscl = true,
 883                         .cm = true,
 884                         .mpc = true,
 885                         .optc = true,
 886                         .vpg = true,
 887                         .afmt = true,
 888                 }
 889         },
 890         .enable_legacy_fast_update = true,
 891         .psr_power_use_phy_fsm = 0,
 892 };
 893
 894 static const struct dc_panel_config panel_config_defaults = {
 895         .psr = {
 896                 .disable_psr = false,
 897                 .disallow_psrsu = false,
 898                 .disallow_replay = false,
 899         },
 900         .ilr = {
 901                 .optimize_edp_link_rate = true,
 902         },
 903 };
 904
 905 static void dcn31_dpp_destroy(struct dpp **dpp)
 906 {
 907         kfree(TO_DCN20_DPP(*dpp));
 908         *dpp = NULL;
 909 }
 910
 911 static struct dpp *dcn31_dpp_create(
 912         struct dc_context *ctx,
 913         uint32_t inst)
 914 {
 915         struct dcn3_dpp *dpp =
 916                 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 917
 918         if (!dpp)
 919                 return NULL;
 920
 921         if (dpp3_construct(dpp, ctx, inst,
 922                         &dpp_regs[inst], &tf_shift, &tf_mask))
 923                 return &dpp->base;
 924
 925         BREAK_TO_DEBUGGER();
 926         kfree(dpp);
 927         return NULL;
 928 }
 929
 930 static struct output_pixel_processor *dcn31_opp_create(
 931         struct dc_context *ctx, uint32_t inst)
 932 {
 933         struct dcn20_opp *opp =
 934                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 935
 936         if (!opp) {
 937                 BREAK_TO_DEBUGGER();
 938                 return NULL;
 939         }
 940
 941         dcn20_opp_construct(opp, ctx, inst,
 942                         &opp_regs[inst], &opp_shift, &opp_mask);
 943         return &opp->base;
 944 }
 945
 946 static struct dce_aux *dcn31_aux_engine_create(
 947         struct dc_context *ctx,
 948         uint32_t inst)
 949 {
 950         struct aux_engine_dce110 *aux_engine =
 951                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 952
 953         if (!aux_engine)
 954                 return NULL;
 955
 956         dce110_aux_engine_construct(aux_engine, ctx, inst,
 957                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 958                                     &aux_engine_regs[inst],
 959                                         &aux_mask,
 960                                         &aux_shift,
 961                                         ctx->dc->caps.extended_aux_timeout_support);
 962
 963         return &aux_engine->base;
 964 }
 965 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
 966
 967 static const struct dce_i2c_registers i2c_hw_regs[] = {
 968                 i2c_inst_regs(1),
 969                 i2c_inst_regs(2),
 970                 i2c_inst_regs(3),
 971                 i2c_inst_regs(4),
 972                 i2c_inst_regs(5),
 973 };
 974
 975 static const struct dce_i2c_shift i2c_shifts = {
 976                 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 977 };
 978
 979 static const struct dce_i2c_mask i2c_masks = {
 980                 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
 981 };
 982
 983 static struct dce_i2c_hw *dcn31_i2c_hw_create(
 984         struct dc_context *ctx,
 985         uint32_t inst)
 986 {
 987         struct dce_i2c_hw *dce_i2c_hw =
 988                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 989
 990         if (!dce_i2c_hw)
 991                 return NULL;
 992
 993         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 994                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 995
 996         return dce_i2c_hw;
 997 }
 998 static struct mpc *dcn31_mpc_create(
 999                 struct dc_context *ctx,
1000                 int num_mpcc,
1001                 int num_rmu)
1002 {
1003         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1004                                           GFP_KERNEL);
1005
1006         if (!mpc30)
1007                 return NULL;
1008
1009         dcn30_mpc_construct(mpc30, ctx,
1010                         &mpc_regs,
1011                         &mpc_shift,
1012                         &mpc_mask,
1013                         num_mpcc,
1014                         num_rmu);
1015
1016         return &mpc30->base;
1017 }
1018
1019 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1020 {
1021         int i;
1022
1023         struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1024                                           GFP_KERNEL);
1025
1026         if (!hubbub3)
1027                 return NULL;
1028
1029         hubbub31_construct(hubbub3, ctx,
1030                         &hubbub_reg,
1031                         &hubbub_shift,
1032                         &hubbub_mask,
1033                         dcn3_15_ip.det_buffer_size_kbytes,
1034                         dcn3_15_ip.pixel_chunk_size_kbytes,
1035                         dcn3_15_ip.config_return_buffer_size_in_kbytes);
1036
1037
1038         for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1039                 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1040
1041                 vmid->ctx = ctx;
1042
1043                 vmid->regs = &vmid_regs[i];
1044                 vmid->shifts = &vmid_shifts;
1045                 vmid->masks = &vmid_masks;
1046         }
1047
1048         return &hubbub3->base;
1049 }
1050
1051 static struct timing_generator *dcn31_timing_generator_create(
1052                 struct dc_context *ctx,
1053                 uint32_t instance)
1054 {
1055         struct optc *tgn10 =
1056                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1057
1058         if (!tgn10)
1059                 return NULL;
1060
1061         tgn10->base.inst = instance;
1062         tgn10->base.ctx = ctx;
1063
1064         tgn10->tg_regs = &optc_regs[instance];
1065         tgn10->tg_shift = &optc_shift;
1066         tgn10->tg_mask = &optc_mask;
1067
1068         dcn31_timing_generator_init(tgn10);
1069
1070         return &tgn10->base;
1071 }
1072
1073 static const struct encoder_feature_support link_enc_feature = {
1074                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1075                 .max_hdmi_pixel_clock = 600000,
1076                 .hdmi_ycbcr420_supported = true,
1077                 .dp_ycbcr420_supported = true,
1078                 .fec_supported = true,
1079                 .flags.bits.IS_HBR2_CAPABLE = true,
1080                 .flags.bits.IS_HBR3_CAPABLE = true,
1081                 .flags.bits.IS_TPS3_CAPABLE = true,
1082                 .flags.bits.IS_TPS4_CAPABLE = true
1083 };
1084
1085 static struct link_encoder *dcn31_link_encoder_create(
1086         struct dc_context *ctx,
1087         const struct encoder_init_data *enc_init_data)
1088 {
1089         struct dcn20_link_encoder *enc20 =
1090                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1091
1092         if (!enc20)
1093                 return NULL;
1094
1095         dcn31_link_encoder_construct(enc20,
1096                         enc_init_data,
1097                         &link_enc_feature,
1098                         &link_enc_regs[enc_init_data->transmitter],
1099                         &link_enc_aux_regs[enc_init_data->channel - 1],
1100                         &link_enc_hpd_regs[enc_init_data->hpd_source],
1101                         &le_shift,
1102                         &le_mask);
1103
1104         return &enc20->enc10.base;
1105 }
1106
1107 /* Create a minimal link encoder object not associated with a particular
1108  * physical connector.
1109  * resource_funcs.link_enc_create_minimal
1110  */
1111 static struct link_encoder *dcn31_link_enc_create_minimal(
1112                 struct dc_context *ctx, enum engine_id eng_id)
1113 {
1114         struct dcn20_link_encoder *enc20;
1115
1116         if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1117                 return NULL;
1118
1119         enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1120         if (!enc20)
1121                 return NULL;
1122
1123         dcn31_link_encoder_construct_minimal(
1124                         enc20,
1125                         ctx,
1126                         &link_enc_feature,
1127                         &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1128                         eng_id);
1129
1130         return &enc20->enc10.base;
1131 }
1132
1133 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1134 {
1135         struct dcn31_panel_cntl *panel_cntl =
1136                 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1137
1138         if (!panel_cntl)
1139                 return NULL;
1140
1141         dcn31_panel_cntl_construct(panel_cntl, init_data);
1142
1143         return &panel_cntl->base;
1144 }
1145
1146 static void read_dce_straps(
1147         struct dc_context *ctx,
1148         struct resource_straps *straps)
1149 {
1150         generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1151                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1152
1153 }
1154
1155 static struct audio *dcn31_create_audio(
1156                 struct dc_context *ctx, unsigned int inst)
1157 {
1158         return dce_audio_create(ctx, inst,
1159                         &audio_regs[inst], &audio_shift, &audio_mask);
1160 }
1161
1162 static struct vpg *dcn31_vpg_create(
1163         struct dc_context *ctx,
1164         uint32_t inst)
1165 {
1166         struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1167
1168         if (!vpg31)
1169                 return NULL;
1170
1171         vpg31_construct(vpg31, ctx, inst,
1172                         &vpg_regs[inst],
1173                         &vpg_shift,
1174                         &vpg_mask);
1175
1176         return &vpg31->base;
1177 }
1178
1179 static struct afmt *dcn31_afmt_create(
1180         struct dc_context *ctx,
1181         uint32_t inst)
1182 {
1183         struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1184
1185         if (!afmt31)
1186                 return NULL;
1187
1188         afmt31_construct(afmt31, ctx, inst,
1189                         &afmt_regs[inst],
1190                         &afmt_shift,
1191                         &afmt_mask);
1192
1193         // Light sleep by default, no need to power down here
1194
1195         return &afmt31->base;
1196 }
1197
1198 static struct apg *dcn31_apg_create(
1199         struct dc_context *ctx,
1200         uint32_t inst)
1201 {
1202         struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1203
1204         if (!apg31)
1205                 return NULL;
1206
1207         apg31_construct(apg31, ctx, inst,
1208                         &apg_regs[inst],
1209                         &apg_shift,
1210                         &apg_mask);
1211
1212         return &apg31->base;
1213 }
1214
1215 static struct stream_encoder *dcn315_stream_encoder_create(
1216         enum engine_id eng_id,
1217         struct dc_context *ctx)
1218 {
1219         struct dcn10_stream_encoder *enc1;
1220         struct vpg *vpg;
1221         struct afmt *afmt;
1222         int vpg_inst;
1223         int afmt_inst;
1224
1225         /*PHYB is wired off in HW, allow front end to remapping, otherwise needs more changes*/
1226
1227         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1228         if (eng_id <= ENGINE_ID_DIGF) {
1229                 vpg_inst = eng_id;
1230                 afmt_inst = eng_id;
1231         } else
1232                 return NULL;
1233
1234         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1235         vpg = dcn31_vpg_create(ctx, vpg_inst);
1236         afmt = dcn31_afmt_create(ctx, afmt_inst);
1237
1238         if (!enc1 || !vpg || !afmt) {
1239                 kfree(enc1);
1240                 kfree(vpg);
1241                 kfree(afmt);
1242                 return NULL;
1243         }
1244
1245         dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1246                                         eng_id, vpg, afmt,
1247                                         &stream_enc_regs[eng_id],
1248                                         &se_shift, &se_mask);
1249
1250         return &enc1->base;
1251 }
1252
1253 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1254         enum engine_id eng_id,
1255         struct dc_context *ctx)
1256 {
1257         struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1258         struct vpg *vpg;
1259         struct apg *apg;
1260         uint32_t hpo_dp_inst;
1261         uint32_t vpg_inst;
1262         uint32_t apg_inst;
1263
1264         ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1265         hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1266
1267         /* Mapping of VPG register blocks to HPO DP block instance:
1268          * VPG[6] -> HPO_DP[0]
1269          * VPG[7] -> HPO_DP[1]
1270          * VPG[8] -> HPO_DP[2]
1271          * VPG[9] -> HPO_DP[3]
1272          */
1273         vpg_inst = hpo_dp_inst + 6;
1274
1275         /* Mapping of APG register blocks to HPO DP block instance:
1276          * APG[0] -> HPO_DP[0]
1277          * APG[1] -> HPO_DP[1]
1278          * APG[2] -> HPO_DP[2]
1279          * APG[3] -> HPO_DP[3]
1280          */
1281         apg_inst = hpo_dp_inst;
1282
1283         /* allocate HPO stream encoder and create VPG sub-block */
1284         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1285         vpg = dcn31_vpg_create(ctx, vpg_inst);
1286         apg = dcn31_apg_create(ctx, apg_inst);
1287
1288         if (!hpo_dp_enc31 || !vpg || !apg) {
1289                 kfree(hpo_dp_enc31);
1290                 kfree(vpg);
1291                 kfree(apg);
1292                 return NULL;
1293         }
1294
1295         dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1296                                         hpo_dp_inst, eng_id, vpg, apg,
1297                                         &hpo_dp_stream_enc_regs[hpo_dp_inst],
1298                                         &hpo_dp_se_shift, &hpo_dp_se_mask);
1299
1300         return &hpo_dp_enc31->base;
1301 }
1302
1303 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1304         uint8_t inst,
1305         struct dc_context *ctx)
1306 {
1307         struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1308
1309         /* allocate HPO link encoder */
1310         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1311
1312         hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1313                                         &hpo_dp_link_enc_regs[inst],
1314                                         &hpo_dp_le_shift, &hpo_dp_le_mask);
1315
1316         return &hpo_dp_enc31->base;
1317 }
1318
1319 static struct dce_hwseq *dcn31_hwseq_create(
1320         struct dc_context *ctx)
1321 {
1322         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1323
1324         if (hws) {
1325                 hws->ctx = ctx;
1326                 hws->regs = &hwseq_reg;
1327                 hws->shifts = &hwseq_shift;
1328                 hws->masks = &hwseq_mask;
1329         }
1330         return hws;
1331 }
1332 static const struct resource_create_funcs res_create_funcs = {
1333         .read_dce_straps = read_dce_straps,
1334         .create_audio = dcn31_create_audio,
1335         .create_stream_encoder = dcn315_stream_encoder_create,
1336         .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1337         .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1338         .create_hwseq = dcn31_hwseq_create,
1339 };
1340
1341 static void dcn315_resource_destruct(struct dcn315_resource_pool *pool)
1342 {
1343         unsigned int i;
1344
1345         for (i = 0; i < pool->base.stream_enc_count; i++) {
1346                 if (pool->base.stream_enc[i] != NULL) {
1347                         if (pool->base.stream_enc[i]->vpg != NULL) {
1348                                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1349                                 pool->base.stream_enc[i]->vpg = NULL;
1350                         }
1351                         if (pool->base.stream_enc[i]->afmt != NULL) {
1352                                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1353                                 pool->base.stream_enc[i]->afmt = NULL;
1354                         }
1355                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1356                         pool->base.stream_enc[i] = NULL;
1357                 }
1358         }
1359
1360         for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1361                 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1362                         if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1363                                 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1364                                 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1365                         }
1366                         if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1367                                 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1368                                 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1369                         }
1370                         kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1371                         pool->base.hpo_dp_stream_enc[i] = NULL;
1372                 }
1373         }
1374
1375         for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1376                 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1377                         kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1378                         pool->base.hpo_dp_link_enc[i] = NULL;
1379                 }
1380         }
1381
1382         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1383                 if (pool->base.dscs[i] != NULL)
1384                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1385         }
1386
1387         if (pool->base.mpc != NULL) {
1388                 kfree(TO_DCN20_MPC(pool->base.mpc));
1389                 pool->base.mpc = NULL;
1390         }
1391         if (pool->base.hubbub != NULL) {
1392                 kfree(pool->base.hubbub);
1393                 pool->base.hubbub = NULL;
1394         }
1395         for (i = 0; i < pool->base.pipe_count; i++) {
1396                 if (pool->base.dpps[i] != NULL)
1397                         dcn31_dpp_destroy(&pool->base.dpps[i]);
1398
1399                 if (pool->base.ipps[i] != NULL)
1400                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1401
1402                 if (pool->base.hubps[i] != NULL) {
1403                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1404                         pool->base.hubps[i] = NULL;
1405                 }
1406
1407                 if (pool->base.irqs != NULL) {
1408                         dal_irq_service_destroy(&pool->base.irqs);
1409                 }
1410         }
1411
1412         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1413                 if (pool->base.engines[i] != NULL)
1414                         dce110_engine_destroy(&pool->base.engines[i]);
1415                 if (pool->base.hw_i2cs[i] != NULL) {
1416                         kfree(pool->base.hw_i2cs[i]);
1417                         pool->base.hw_i2cs[i] = NULL;
1418                 }
1419                 if (pool->base.sw_i2cs[i] != NULL) {
1420                         kfree(pool->base.sw_i2cs[i]);
1421                         pool->base.sw_i2cs[i] = NULL;
1422                 }
1423         }
1424
1425         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1426                 if (pool->base.opps[i] != NULL)
1427                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1428         }
1429
1430         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1431                 if (pool->base.timing_generators[i] != NULL)    {
1432                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1433                         pool->base.timing_generators[i] = NULL;
1434                 }
1435         }
1436
1437         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1438                 if (pool->base.dwbc[i] != NULL) {
1439                         kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1440                         pool->base.dwbc[i] = NULL;
1441                 }
1442                 if (pool->base.mcif_wb[i] != NULL) {
1443                         kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1444                         pool->base.mcif_wb[i] = NULL;
1445                 }
1446         }
1447
1448         for (i = 0; i < pool->base.audio_count; i++) {
1449                 if (pool->base.audios[i])
1450                         dce_aud_destroy(&pool->base.audios[i]);
1451         }
1452
1453         for (i = 0; i < pool->base.clk_src_count; i++) {
1454                 if (pool->base.clock_sources[i] != NULL) {
1455                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1456                         pool->base.clock_sources[i] = NULL;
1457                 }
1458         }
1459
1460         for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1461                 if (pool->base.mpc_lut[i] != NULL) {
1462                         dc_3dlut_func_release(pool->base.mpc_lut[i]);
1463                         pool->base.mpc_lut[i] = NULL;
1464                 }
1465                 if (pool->base.mpc_shaper[i] != NULL) {
1466                         dc_transfer_func_release(pool->base.mpc_shaper[i]);
1467                         pool->base.mpc_shaper[i] = NULL;
1468                 }
1469         }
1470
1471         if (pool->base.dp_clock_source != NULL) {
1472                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1473                 pool->base.dp_clock_source = NULL;
1474         }
1475
1476         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1477                 if (pool->base.multiple_abms[i] != NULL)
1478                         dce_abm_destroy(&pool->base.multiple_abms[i]);
1479         }
1480
1481         if (pool->base.psr != NULL)
1482                 dmub_psr_destroy(&pool->base.psr);
1483
1484         if (pool->base.dccg != NULL)
1485                 dcn_dccg_destroy(&pool->base.dccg);
1486 }
1487
1488 static struct hubp *dcn31_hubp_create(
1489         struct dc_context *ctx,
1490         uint32_t inst)
1491 {
1492         struct dcn20_hubp *hubp2 =
1493                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1494
1495         if (!hubp2)
1496                 return NULL;
1497
1498         if (hubp31_construct(hubp2, ctx, inst,
1499                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1500                 return &hubp2->base;
1501
1502         BREAK_TO_DEBUGGER();
1503         kfree(hubp2);
1504         return NULL;
1505 }
1506
1507 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1508 {
1509         int i;
1510         uint32_t pipe_count = pool->res_cap->num_dwb;
1511
1512         for (i = 0; i < pipe_count; i++) {
1513                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1514                                                     GFP_KERNEL);
1515
1516                 if (!dwbc30) {
1517                         dm_error("DC: failed to create dwbc30!\n");
1518                         return false;
1519                 }
1520
1521                 dcn30_dwbc_construct(dwbc30, ctx,
1522                                 &dwbc30_regs[i],
1523                                 &dwbc30_shift,
1524                                 &dwbc30_mask,
1525                                 i);
1526
1527                 pool->dwbc[i] = &dwbc30->base;
1528         }
1529         return true;
1530 }
1531
1532 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1533 {
1534         int i;
1535         uint32_t pipe_count = pool->res_cap->num_dwb;
1536
1537         for (i = 0; i < pipe_count; i++) {
1538                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1539                                                     GFP_KERNEL);
1540
1541                 if (!mcif_wb30) {
1542                         dm_error("DC: failed to create mcif_wb30!\n");
1543                         return false;
1544                 }
1545
1546                 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1547                                 &mcif_wb30_regs[i],
1548                                 &mcif_wb30_shift,
1549                                 &mcif_wb30_mask,
1550                                 i);
1551
1552                 pool->mcif_wb[i] = &mcif_wb30->base;
1553         }
1554         return true;
1555 }
1556
1557 static struct display_stream_compressor *dcn31_dsc_create(
1558         struct dc_context *ctx, uint32_t inst)
1559 {
1560         struct dcn20_dsc *dsc =
1561                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1562
1563         if (!dsc) {
1564                 BREAK_TO_DEBUGGER();
1565                 return NULL;
1566         }
1567
1568         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1569         return &dsc->base;
1570 }
1571
1572 static void dcn315_destroy_resource_pool(struct resource_pool **pool)
1573 {
1574         struct dcn315_resource_pool *dcn31_pool = TO_DCN315_RES_POOL(*pool);
1575
1576         dcn315_resource_destruct(dcn31_pool);
1577         kfree(dcn31_pool);
1578         *pool = NULL;
1579 }
1580
1581 static struct clock_source *dcn31_clock_source_create(
1582                 struct dc_context *ctx,
1583                 struct dc_bios *bios,
1584                 enum clock_source_id id,
1585                 const struct dce110_clk_src_regs *regs,
1586                 bool dp_clk_src)
1587 {
1588         struct dce110_clk_src *clk_src =
1589                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1590
1591         if (!clk_src)
1592                 return NULL;
1593
1594         if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1595                         regs, &cs_shift, &cs_mask)) {
1596                 clk_src->base.dp_clk_src = dp_clk_src;
1597                 return &clk_src->base;
1598         }
1599
1600         kfree(clk_src);
1601         BREAK_TO_DEBUGGER();
1602         return NULL;
1603 }
1604
1605 static bool is_dual_plane(enum surface_pixel_format format)
1606 {
1607         return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1608 }
1609
1610 static int source_format_to_bpp (enum source_format_class SourcePixelFormat)
1611 {
1612         if (SourcePixelFormat == dm_444_64)
1613                 return 8;
1614         else if (SourcePixelFormat == dm_444_16)
1615                 return 2;
1616         else if (SourcePixelFormat == dm_444_8)
1617                 return 1;
1618         else if (SourcePixelFormat == dm_rgbe_alpha)
1619                 return 5;
1620         else if (SourcePixelFormat == dm_420_8)
1621                 return 3;
1622         else if (SourcePixelFormat == dm_420_12)
1623                 return 6;
1624         else
1625                 return 4;
1626 }
1627
1628 static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context)
1629 {
1630         int i;
1631         struct resource_context *res_ctx = &context->res_ctx;
1632
1633         /*Don't apply for single stream*/
1634         if (context->stream_count < 2)
1635                 return false;
1636
1637         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1638                 if (!res_ctx->pipe_ctx[i].stream)
1639                         continue;
1640
1641                 /*Don't apply if scaling*/
1642                 if (res_ctx->pipe_ctx[i].stream->src.width != res_ctx->pipe_ctx[i].stream->dst.width ||
1643                                 res_ctx->pipe_ctx[i].stream->src.height != res_ctx->pipe_ctx[i].stream->dst.height ||
1644                                 (res_ctx->pipe_ctx[i].plane_state && (res_ctx->pipe_ctx[i].plane_state->src_rect.width
1645                                                                                                                 != res_ctx->pipe_ctx[i].plane_state->dst_rect.width ||
1646                                         res_ctx->pipe_ctx[i].plane_state->src_rect.height
1647                                                                                                                 != res_ctx->pipe_ctx[i].plane_state->dst_rect.height)))
1648                         return false;
1649                 /*Don't apply if MPO to avoid transition issues*/
1650                 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state != res_ctx->pipe_ctx[i].plane_state)
1651                         return false;
1652         }
1653         return true;
1654 }
1655
1656 static int dcn315_populate_dml_pipes_from_context(
1657         struct dc *dc, struct dc_state *context,
1658         display_e2e_pipe_params_st *pipes,
1659         bool fast_validate)
1660 {
1661         int i, pipe_cnt, crb_idx, crb_pipes;
1662         struct resource_context *res_ctx = &context->res_ctx;
1663         struct pipe_ctx *pipe = NULL;
1664         const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB;
1665         int remaining_det_segs = max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB;
1666         bool pixel_rate_crb = allow_pixel_rate_crb(dc, context);
1667
1668         DC_FP_START();
1669         dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1670         DC_FP_END();
1671
1672         for (i = 0, pipe_cnt = 0, crb_pipes = 0; i < dc->res_pool->pipe_count; i++) {
1673                 struct dc_crtc_timing *timing;
1674
1675                 if (!res_ctx->pipe_ctx[i].stream)
1676                         continue;
1677                 pipe = &res_ctx->pipe_ctx[i];
1678                 timing = &pipe->stream->timing;
1679
1680                 /*
1681                  * Immediate flip can be set dynamically after enabling the plane.
1682                  * We need to require support for immediate flip or underflow can be
1683                  * intermittently experienced depending on peak b/w requirements.
1684                  */
1685                 pipes[pipe_cnt].pipe.src.immediate_flip = true;
1686
1687                 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1688                 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1689                 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1690                 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1691                 DC_FP_START();
1692                 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1693                 if (pixel_rate_crb && !pipe->top_pipe && !pipe->prev_odm_pipe) {
1694                         int bpp = source_format_to_bpp(pipes[pipe_cnt].pipe.src.source_format);
1695                         /* Ceil to crb segment size */
1696                         int approx_det_segs_required_for_pstate = dcn_get_approx_det_segs_required_for_pstate(
1697                                         &context->bw_ctx.dml.soc, timing->pix_clk_100hz, bpp, DCN3_15_CRB_SEGMENT_SIZE_KB);
1698
1699                         if (approx_det_segs_required_for_pstate <= 2 * DCN3_15_MAX_DET_SEGS) {
1700                                 bool split_required = approx_det_segs_required_for_pstate > DCN3_15_MAX_DET_SEGS;
1701                                 split_required = split_required || timing->pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc);
1702                                 split_required = split_required || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120);
1703
1704                                 /* Minimum 2 segments to allow mpc/odm combine if its used later */
1705                                 if (approx_det_segs_required_for_pstate < 2)
1706                                         approx_det_segs_required_for_pstate = 2;
1707                                 if (split_required)
1708                                         approx_det_segs_required_for_pstate += approx_det_segs_required_for_pstate % 2;
1709                                 pipes[pipe_cnt].pipe.src.det_size_override = approx_det_segs_required_for_pstate;
1710                                 remaining_det_segs -= approx_det_segs_required_for_pstate;
1711                         } else
1712                                 remaining_det_segs = -1;
1713                         crb_pipes++;
1714                 }
1715                 DC_FP_END();
1716
1717                 if (pipes[pipe_cnt].dout.dsc_enable) {
1718                         switch (timing->display_color_depth) {
1719                         case COLOR_DEPTH_888:
1720                                 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1721                                 break;
1722                         case COLOR_DEPTH_101010:
1723                                 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1724                                 break;
1725                         case COLOR_DEPTH_121212:
1726                                 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1727                                 break;
1728                         default:
1729                                 ASSERT(0);
1730                                 break;
1731                         }
1732                 }
1733                 pipe_cnt++;
1734         }
1735
1736         /* Spread remaining unreserved crb evenly among all pipes*/
1737         if (pixel_rate_crb) {
1738                 for (i = 0, pipe_cnt = 0, crb_idx = 0; i < dc->res_pool->pipe_count; i++) {
1739                         pipe = &res_ctx->pipe_ctx[i];
1740                         if (!pipe->stream)
1741                                 continue;
1742
1743                         /* Do not use asymetric crb if not enough for pstate support */
1744                         if (remaining_det_segs < 0) {
1745                                 pipes[pipe_cnt].pipe.src.det_size_override = 0;
1746                                 pipe_cnt++;
1747                                 continue;
1748                         }
1749
1750                         if (!pipe->top_pipe && !pipe->prev_odm_pipe) {
1751                                 bool split_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)
1752                                                 || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120);
1753
1754                                 if (remaining_det_segs > MIN_RESERVED_DET_SEGS)
1755                                         pipes[pipe_cnt].pipe.src.det_size_override += (remaining_det_segs - MIN_RESERVED_DET_SEGS) / crb_pipes +
1756                                                         (crb_idx < (remaining_det_segs - MIN_RESERVED_DET_SEGS) % crb_pipes ? 1 : 0);
1757                                 if (pipes[pipe_cnt].pipe.src.det_size_override > 2 * DCN3_15_MAX_DET_SEGS) {
1758                                         /* Clamp to 2 pipe split max det segments */
1759                                         remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override - 2 * (DCN3_15_MAX_DET_SEGS);
1760                                         pipes[pipe_cnt].pipe.src.det_size_override = 2 * DCN3_15_MAX_DET_SEGS;
1761                                 }
1762                                 if (pipes[pipe_cnt].pipe.src.det_size_override > DCN3_15_MAX_DET_SEGS || split_required) {
1763                                         /* If we are splitting we must have an even number of segments */
1764                                         remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override % 2;
1765                                         pipes[pipe_cnt].pipe.src.det_size_override -= pipes[pipe_cnt].pipe.src.det_size_override % 2;
1766                                 }
1767                                 /* Convert segments into size for DML use */
1768                                 pipes[pipe_cnt].pipe.src.det_size_override *= DCN3_15_CRB_SEGMENT_SIZE_KB;
1769
1770                                 crb_idx++;
1771                         }
1772                         pipe_cnt++;
1773                 }
1774         }
1775
1776         if (pipe_cnt)
1777                 context->bw_ctx.dml.ip.det_buffer_size_kbytes =
1778                                 (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / pipe_cnt) * DCN3_15_CRB_SEGMENT_SIZE_KB;
1779         if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_15_MAX_DET_SIZE)
1780                 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_15_MAX_DET_SIZE;
1781
1782         dc->config.enable_4to1MPC = false;
1783         if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1784                 if (is_dual_plane(pipe->plane_state->format)
1785                                 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1786                         dc->config.enable_4to1MPC = true;
1787                         context->bw_ctx.dml.ip.det_buffer_size_kbytes =
1788                                         (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB;
1789                 } else if (!is_dual_plane(pipe->plane_state->format)
1790                                 && pipe->plane_state->src_rect.width <= 5120
1791                                 && pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) {
1792                         /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */
1793                         context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1794                         pipes[0].pipe.src.unbounded_req_mode = true;
1795                 }
1796         }
1797
1798         return pipe_cnt;
1799 }
1800
1801 static void dcn315_get_panel_config_defaults(struct dc_panel_config *panel_config)
1802 {
1803         *panel_config = panel_config_defaults;
1804 }
1805
1806 static struct dc_cap_funcs cap_funcs = {
1807         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1808 };
1809
1810 static struct resource_funcs dcn315_res_pool_funcs = {
1811         .destroy = dcn315_destroy_resource_pool,
1812         .link_enc_create = dcn31_link_encoder_create,
1813         .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1814         .link_encs_assign = link_enc_cfg_link_encs_assign,
1815         .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1816         .panel_cntl_create = dcn31_panel_cntl_create,
1817         .validate_bandwidth = dcn31_validate_bandwidth,
1818         .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1819         .update_soc_for_wm_a = dcn315_update_soc_for_wm_a,
1820         .populate_dml_pipes = dcn315_populate_dml_pipes_from_context,
1821         .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1822         .release_pipe = dcn20_release_pipe,
1823         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1824         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1825         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1826         .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context,
1827         .set_mcif_arb_params = dcn31_set_mcif_arb_params,
1828         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1829         .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1830         .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1831         .update_bw_bounding_box = dcn315_update_bw_bounding_box,
1832         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1833         .get_panel_config_defaults = dcn315_get_panel_config_defaults,
1834 };
1835
1836 static bool dcn315_resource_construct(
1837         uint8_t num_virtual_links,
1838         struct dc *dc,
1839         struct dcn315_resource_pool *pool)
1840 {
1841         int i;
1842         struct dc_context *ctx = dc->ctx;
1843         struct irq_service_init_data init_data;
1844
1845         ctx->dc_bios->regs = &bios_regs;
1846
1847         pool->base.res_cap = &res_cap_dcn31;
1848
1849         pool->base.funcs = &dcn315_res_pool_funcs;
1850
1851         /*************************************************
1852          *  Resource + asic cap harcoding                *
1853          *************************************************/
1854         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1855         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1856         pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1857         dc->caps.max_downscale_ratio = 600;
1858         dc->caps.i2c_speed_in_khz = 100;
1859         dc->caps.i2c_speed_in_khz_hdcp = 100;
1860         dc->caps.max_cursor_size = 256;
1861         dc->caps.min_horizontal_blanking_period = 80;
1862         dc->caps.dmdata_alloc_size = 2048;
1863         dc->caps.max_slave_planes = 2;
1864         dc->caps.max_slave_yuv_planes = 2;
1865         dc->caps.max_slave_rgb_planes = 2;
1866         dc->caps.post_blend_color_processing = true;
1867         dc->caps.force_dp_tps4_for_cp2520 = true;
1868         if (dc->config.forceHBR2CP2520)
1869                 dc->caps.force_dp_tps4_for_cp2520 = false;
1870         dc->caps.dp_hpo = true;
1871         dc->caps.dp_hdmi21_pcon_support = true;
1872         dc->caps.edp_dsc_support = true;
1873         dc->caps.extended_aux_timeout_support = true;
1874         dc->caps.dmcub_support = true;
1875         dc->caps.is_apu = true;
1876
1877         /* Color pipeline capabilities */
1878         dc->caps.color.dpp.dcn_arch = 1;
1879         dc->caps.color.dpp.input_lut_shared = 0;
1880         dc->caps.color.dpp.icsc = 1;
1881         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1882         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1883         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1884         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1885         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1886         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1887         dc->caps.color.dpp.post_csc = 1;
1888         dc->caps.color.dpp.gamma_corr = 1;
1889         dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1890
1891         dc->caps.color.dpp.hw_3d_lut = 1;
1892         dc->caps.color.dpp.ogam_ram = 1;
1893         // no OGAM ROM on DCN301
1894         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1895         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1896         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1897         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1898         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1899         dc->caps.color.dpp.ocsc = 0;
1900
1901         dc->caps.color.mpc.gamut_remap = 1;
1902         dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1903         dc->caps.color.mpc.ogam_ram = 1;
1904         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1905         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1906         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1907         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1908         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1909         dc->caps.color.mpc.ocsc = 1;
1910
1911         /* read VBIOS LTTPR caps */
1912         {
1913                 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1914                         enum bp_result bp_query_result;
1915                         uint8_t is_vbios_lttpr_enable = 0;
1916
1917                         bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1918                         dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1919                 }
1920
1921                 /* interop bit is implicit */
1922                 {
1923                         dc->caps.vbios_lttpr_aware = true;
1924                 }
1925         }
1926
1927         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1928                 dc->debug = debug_defaults_drv;
1929
1930         // Init the vm_helper
1931         if (dc->vm_helper)
1932                 vm_helper_init(dc->vm_helper, 16);
1933
1934         /*************************************************
1935          *  Create resources                             *
1936          *************************************************/
1937
1938         /* Clock Sources for Pixel Clock*/
1939         pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1940                         dcn31_clock_source_create(ctx, ctx->dc_bios,
1941                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1942                                 &clk_src_regs[0], false);
1943         pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1944                         dcn31_clock_source_create(ctx, ctx->dc_bios,
1945                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1946                                 &clk_src_regs[1], false);
1947         pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1948                         dcn31_clock_source_create(ctx, ctx->dc_bios,
1949                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1950                                 &clk_src_regs[2], false);
1951         pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1952                         dcn31_clock_source_create(ctx, ctx->dc_bios,
1953                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
1954                                 &clk_src_regs[3], false);
1955         pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
1956                         dcn31_clock_source_create(ctx, ctx->dc_bios,
1957                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
1958                                 &clk_src_regs[4], false);
1959
1960         pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
1961
1962         /* todo: not reuse phy_pll registers */
1963         pool->base.dp_clock_source =
1964                         dcn31_clock_source_create(ctx, ctx->dc_bios,
1965                                 CLOCK_SOURCE_ID_DP_DTO,
1966                                 &clk_src_regs[0], true);
1967
1968         for (i = 0; i < pool->base.clk_src_count; i++) {
1969                 if (pool->base.clock_sources[i] == NULL) {
1970                         dm_error("DC: failed to create clock sources!\n");
1971                         BREAK_TO_DEBUGGER();
1972                         goto create_fail;
1973                 }
1974         }
1975
1976         /* TODO: DCCG */
1977         pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1978         if (pool->base.dccg == NULL) {
1979                 dm_error("DC: failed to create dccg!\n");
1980                 BREAK_TO_DEBUGGER();
1981                 goto create_fail;
1982         }
1983
1984         /* TODO: IRQ */
1985         init_data.ctx = dc->ctx;
1986         pool->base.irqs = dal_irq_service_dcn315_create(&init_data);
1987         if (!pool->base.irqs)
1988                 goto create_fail;
1989
1990         /* HUBBUB */
1991         pool->base.hubbub = dcn31_hubbub_create(ctx);
1992         if (pool->base.hubbub == NULL) {
1993                 BREAK_TO_DEBUGGER();
1994                 dm_error("DC: failed to create hubbub!\n");
1995                 goto create_fail;
1996         }
1997
1998         /* HUBPs, DPPs, OPPs and TGs */
1999         for (i = 0; i < pool->base.pipe_count; i++) {
2000                 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2001                 if (pool->base.hubps[i] == NULL) {
2002                         BREAK_TO_DEBUGGER();
2003                         dm_error(
2004                                 "DC: failed to create hubps!\n");
2005                         goto create_fail;
2006                 }
2007
2008                 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2009                 if (pool->base.dpps[i] == NULL) {
2010                         BREAK_TO_DEBUGGER();
2011                         dm_error(
2012                                 "DC: failed to create dpps!\n");
2013                         goto create_fail;
2014                 }
2015         }
2016
2017         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2018                 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2019                 if (pool->base.opps[i] == NULL) {
2020                         BREAK_TO_DEBUGGER();
2021                         dm_error(
2022                                 "DC: failed to create output pixel processor!\n");
2023                         goto create_fail;
2024                 }
2025         }
2026
2027         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2028                 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2029                                 ctx, i);
2030                 if (pool->base.timing_generators[i] == NULL) {
2031                         BREAK_TO_DEBUGGER();
2032                         dm_error("DC: failed to create tg!\n");
2033                         goto create_fail;
2034                 }
2035         }
2036         pool->base.timing_generator_count = i;
2037
2038         /* PSR */
2039         pool->base.psr = dmub_psr_create(ctx);
2040         if (pool->base.psr == NULL) {
2041                 dm_error("DC: failed to create psr obj!\n");
2042                 BREAK_TO_DEBUGGER();
2043                 goto create_fail;
2044         }
2045
2046         /* ABM */
2047         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2048                 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2049                                 &abm_regs[i],
2050                                 &abm_shift,
2051                                 &abm_mask);
2052                 if (pool->base.multiple_abms[i] == NULL) {
2053                         dm_error("DC: failed to create abm for pipe %d!\n", i);
2054                         BREAK_TO_DEBUGGER();
2055                         goto create_fail;
2056                 }
2057         }
2058
2059         /* MPC and DSC */
2060         pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2061         if (pool->base.mpc == NULL) {
2062                 BREAK_TO_DEBUGGER();
2063                 dm_error("DC: failed to create mpc!\n");
2064                 goto create_fail;
2065         }
2066
2067         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2068                 pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
2069                 if (pool->base.dscs[i] == NULL) {
2070                         BREAK_TO_DEBUGGER();
2071                         dm_error("DC: failed to create display stream compressor %d!\n", i);
2072                         goto create_fail;
2073                 }
2074         }
2075
2076         /* DWB and MMHUBBUB */
2077         if (!dcn31_dwbc_create(ctx, &pool->base)) {
2078                 BREAK_TO_DEBUGGER();
2079                 dm_error("DC: failed to create dwbc!\n");
2080                 goto create_fail;
2081         }
2082
2083         if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2084                 BREAK_TO_DEBUGGER();
2085                 dm_error("DC: failed to create mcif_wb!\n");
2086                 goto create_fail;
2087         }
2088
2089         /* AUX and I2C */
2090         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2091                 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2092                 if (pool->base.engines[i] == NULL) {
2093                         BREAK_TO_DEBUGGER();
2094                         dm_error(
2095                                 "DC:failed to create aux engine!!\n");
2096                         goto create_fail;
2097                 }
2098                 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2099                 if (pool->base.hw_i2cs[i] == NULL) {
2100                         BREAK_TO_DEBUGGER();
2101                         dm_error(
2102                                 "DC:failed to create hw i2c!!\n");
2103                         goto create_fail;
2104                 }
2105                 pool->base.sw_i2cs[i] = NULL;
2106         }
2107
2108         /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2109         if (!resource_construct(num_virtual_links, dc, &pool->base,
2110                         &res_create_funcs))
2111                 goto create_fail;
2112
2113         /* HW Sequencer and Plane caps */
2114         dcn31_hw_sequencer_construct(dc);
2115
2116         dc->caps.max_planes =  pool->base.pipe_count;
2117
2118         for (i = 0; i < dc->caps.max_planes; ++i)
2119                 dc->caps.planes[i] = plane_cap;
2120
2121         dc->cap_funcs = cap_funcs;
2122
2123         dc->dcn_ip->max_num_dpp = dcn3_15_ip.max_num_dpp;
2124
2125         return true;
2126
2127 create_fail:
2128
2129         dcn315_resource_destruct(pool);
2130
2131         return false;
2132 }
2133
2134 struct resource_pool *dcn315_create_resource_pool(
2135                 const struct dc_init_data *init_data,
2136                 struct dc *dc)
2137 {
2138         struct dcn315_resource_pool *pool =
2139                 kzalloc(sizeof(struct dcn315_resource_pool), GFP_KERNEL);
2140
2141         if (!pool)
2142                 return NULL;
2143
2144         if (dcn315_resource_construct(init_data->num_virtual_links, dc, pool))
2145                 return &pool->base;
2146
2147         BREAK_TO_DEBUGGER();
2148         kfree(pool);
2149         return NULL;
2150 }