drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright 2022 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27
  28 #include "dm_services.h"
  29 #include "dc.h"
  30
  31 #include "dcn31/dcn31_init.h"
  32 #include "dcn314/dcn314_init.h"
  33
  34 #include "resource.h"
  35 #include "include/irq_service_interface.h"
  36 #include "dcn314_resource.h"
  37
  38 #include "dcn20/dcn20_resource.h"
  39 #include "dcn30/dcn30_resource.h"
  40 #include "dcn31/dcn31_resource.h"
  41
  42 #include "dcn10/dcn10_ipp.h"
  43 #include "dcn30/dcn30_hubbub.h"
  44 #include "dcn31/dcn31_hubbub.h"
  45 #include "dcn30/dcn30_mpc.h"
  46 #include "dcn31/dcn31_hubp.h"
  47 #include "irq/dcn31/irq_service_dcn31.h"
  48 #include "irq/dcn314/irq_service_dcn314.h"
  49 #include "dcn30/dcn30_dpp.h"
  50 #include "dcn314/dcn314_optc.h"
  51 #include "dcn20/dcn20_hwseq.h"
  52 #include "dcn30/dcn30_hwseq.h"
  53 #include "dce110/dce110_hw_sequencer.h"
  54 #include "dcn30/dcn30_opp.h"
  55 #include "dcn20/dcn20_dsc.h"
  56 #include "dcn30/dcn30_vpg.h"
  57 #include "dcn30/dcn30_afmt.h"
  58 #include "dcn31/dcn31_dio_link_encoder.h"
  59 #include "dcn314/dcn314_dio_stream_encoder.h"
  60 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
  61 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
  62 #include "dcn31/dcn31_apg.h"
  63 #include "dcn31/dcn31_vpg.h"
  64 #include "dcn31/dcn31_afmt.h"
  65 #include "dce/dce_clock_source.h"
  66 #include "dce/dce_audio.h"
  67 #include "dce/dce_hwseq.h"
  68 #include "clk_mgr.h"
  69 #include "virtual/virtual_stream_encoder.h"
  70 #include "dce110/dce110_resource.h"
  71 #include "dml/display_mode_vba.h"
  72 #include "dcn314/dcn314_dccg.h"
  73 #include "dcn10/dcn10_resource.h"
  74 #include "dcn31/dcn31_panel_cntl.h"
  75 #include "dcn314/dcn314_hwseq.h"
  76
  77 #include "dcn30/dcn30_dwb.h"
  78 #include "dcn30/dcn30_mmhubbub.h"
  79
  80 #include "dcn/dcn_3_1_4_offset.h"
  81 #include "dcn/dcn_3_1_4_sh_mask.h"
  82 #include "dpcs/dpcs_3_1_4_offset.h"
  83 #include "dpcs/dpcs_3_1_4_sh_mask.h"
  84
  85 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT         0x10
  86 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK           0x01FF0000L
  87
  88 #include "reg_helper.h"
  89 #include "dce/dmub_abm.h"
  90 #include "dce/dmub_psr.h"
  91 #include "dce/dce_aux.h"
  92 #include "dce/dce_i2c.h"
  93 #include "dml/dcn314/display_mode_vba_314.h"
  94 #include "vm_helper.h"
  95 #include "dcn20/dcn20_vmid.h"
  96
  97 #include "link_enc_cfg.h"
  98
  99 #define DCN_BASE__INST0_SEG1                            0x000000C0
 100 #define DCN_BASE__INST0_SEG2                            0x000034C0
 101 #define DCN_BASE__INST0_SEG3                            0x00009000
 102
 103 #define NBIO_BASE__INST0_SEG1                           0x00000014
 104
 105 #define MAX_INSTANCE                                    7
 106 #define MAX_SEGMENT                                     8
 107
 108 #define regBIF_BX2_BIOS_SCRATCH_2                       0x003a
 109 #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX              1
 110 #define regBIF_BX2_BIOS_SCRATCH_3                       0x003b
 111 #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX              1
 112 #define regBIF_BX2_BIOS_SCRATCH_6                       0x003e
 113 #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX              1
 114
 115 struct IP_BASE_INSTANCE {
 116         unsigned int segment[MAX_SEGMENT];
 117 };
 118
 119 struct IP_BASE {
 120         struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
 121 };
 122
 123 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0, 0, 0 } },
 124                                         { { 0, 0, 0, 0, 0, 0, 0, 0 } },
 125                                         { { 0, 0, 0, 0, 0, 0, 0, 0 } },
 126                                         { { 0, 0, 0, 0, 0, 0, 0, 0 } },
 127                                         { { 0, 0, 0, 0, 0, 0, 0, 0 } },
 128                                         { { 0, 0, 0, 0, 0, 0, 0, 0 } },
 129                                         { { 0, 0, 0, 0, 0, 0, 0, 0 } } } };
 130
 131
 132 #define DC_LOGGER_INIT(logger)
 133
 134 #define DCN3_14_DEFAULT_DET_SIZE 384
 135 #define DCN3_14_MAX_DET_SIZE 384
 136 #define DCN3_14_MIN_COMPBUF_SIZE_KB 128
 137 #define DCN3_14_CRB_SEGMENT_SIZE_KB 64
 138 struct _vcs_dpi_ip_params_st dcn3_14_ip = {
 139         .VBlankNomDefaultUS = 668,
 140         .gpuvm_enable = 1,
 141         .gpuvm_max_page_table_levels = 1,
 142         .hostvm_enable = 1,
 143         .hostvm_max_page_table_levels = 2,
 144         .rob_buffer_size_kbytes = 64,
 145         .det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE,
 146         .config_return_buffer_size_in_kbytes = 1792,
 147         .compressed_buffer_segment_size_in_kbytes = 64,
 148         .meta_fifo_size_in_kentries = 32,
 149         .zero_size_buffer_entries = 512,
 150         .compbuf_reserved_space_64b = 256,
 151         .compbuf_reserved_space_zs = 64,
 152         .dpp_output_buffer_pixels = 2560,
 153         .opp_output_buffer_lines = 1,
 154         .pixel_chunk_size_kbytes = 8,
 155         .meta_chunk_size_kbytes = 2,
 156         .min_meta_chunk_size_bytes = 256,
 157         .writeback_chunk_size_kbytes = 8,
 158         .ptoi_supported = false,
 159         .num_dsc = 4,
 160         .maximum_dsc_bits_per_component = 10,
 161         .dsc422_native_support = false,
 162         .is_line_buffer_bpp_fixed = true,
 163         .line_buffer_fixed_bpp = 48,
 164         .line_buffer_size_bits = 789504,
 165         .max_line_buffer_lines = 12,
 166         .writeback_interface_buffer_size_kbytes = 90,
 167         .max_num_dpp = 4,
 168         .max_num_otg = 4,
 169         .max_num_hdmi_frl_outputs = 1,
 170         .max_num_wb = 1,
 171         .max_dchub_pscl_bw_pix_per_clk = 4,
 172         .max_pscl_lb_bw_pix_per_clk = 2,
 173         .max_lb_vscl_bw_pix_per_clk = 4,
 174         .max_vscl_hscl_bw_pix_per_clk = 4,
 175         .max_hscl_ratio = 6,
 176         .max_vscl_ratio = 6,
 177         .max_hscl_taps = 8,
 178         .max_vscl_taps = 8,
 179         .dpte_buffer_size_in_pte_reqs_luma = 64,
 180         .dpte_buffer_size_in_pte_reqs_chroma = 34,
 181         .dispclk_ramp_margin_percent = 1,
 182         .max_inter_dcn_tile_repeaters = 8,
 183         .cursor_buffer_size = 16,
 184         .cursor_chunk_size = 2,
 185         .writeback_line_buffer_buffer_size = 0,
 186         .writeback_min_hscl_ratio = 1,
 187         .writeback_min_vscl_ratio = 1,
 188         .writeback_max_hscl_ratio = 1,
 189         .writeback_max_vscl_ratio = 1,
 190         .writeback_max_hscl_taps = 1,
 191         .writeback_max_vscl_taps = 1,
 192         .dppclk_delay_subtotal = 46,
 193         .dppclk_delay_scl = 50,
 194         .dppclk_delay_scl_lb_only = 16,
 195         .dppclk_delay_cnvc_formatter = 27,
 196         .dppclk_delay_cnvc_cursor = 6,
 197         .dispclk_delay_subtotal = 119,
 198         .dynamic_metadata_vm_enabled = false,
 199         .odm_combine_4to1_supported = false,
 200         .dcc_supported = true,
 201 };
 202
 203 struct _vcs_dpi_soc_bounding_box_st dcn3_14_soc = {
 204                 /*TODO: correct dispclk/dppclk voltage level determination*/
 205         .clock_limits = {
 206                 {
 207                         .state = 0,
 208                         .dispclk_mhz = 1200.0,
 209                         .dppclk_mhz = 1200.0,
 210                         .phyclk_mhz = 600.0,
 211                         .phyclk_d18_mhz = 667.0,
 212                         .dscclk_mhz = 186.0,
 213                         .dtbclk_mhz = 625.0,
 214                 },
 215                 {
 216                         .state = 1,
 217                         .dispclk_mhz = 1200.0,
 218                         .dppclk_mhz = 1200.0,
 219                         .phyclk_mhz = 810.0,
 220                         .phyclk_d18_mhz = 667.0,
 221                         .dscclk_mhz = 209.0,
 222                         .dtbclk_mhz = 625.0,
 223                 },
 224                 {
 225                         .state = 2,
 226                         .dispclk_mhz = 1200.0,
 227                         .dppclk_mhz = 1200.0,
 228                         .phyclk_mhz = 810.0,
 229                         .phyclk_d18_mhz = 667.0,
 230                         .dscclk_mhz = 209.0,
 231                         .dtbclk_mhz = 625.0,
 232                 },
 233                 {
 234                         .state = 3,
 235                         .dispclk_mhz = 1200.0,
 236                         .dppclk_mhz = 1200.0,
 237                         .phyclk_mhz = 810.0,
 238                         .phyclk_d18_mhz = 667.0,
 239                         .dscclk_mhz = 371.0,
 240                         .dtbclk_mhz = 625.0,
 241                 },
 242                 {
 243                         .state = 4,
 244                         .dispclk_mhz = 1200.0,
 245                         .dppclk_mhz = 1200.0,
 246                         .phyclk_mhz = 810.0,
 247                         .phyclk_d18_mhz = 667.0,
 248                         .dscclk_mhz = 417.0,
 249                         .dtbclk_mhz = 625.0,
 250                 },
 251         },
 252         .num_states = 5,
 253         .sr_exit_time_us = 9.0,
 254         .sr_enter_plus_exit_time_us = 11.0,
 255         .sr_exit_z8_time_us = 442.0,
 256         .sr_enter_plus_exit_z8_time_us = 560.0,
 257         .writeback_latency_us = 12.0,
 258         .dram_channel_width_bytes = 4,
 259         .round_trip_ping_latency_dcfclk_cycles = 106,
 260         .urgent_latency_pixel_data_only_us = 4.0,
 261         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 262         .urgent_latency_vm_data_only_us = 4.0,
 263         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 264         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 265         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 266         .pct_ideal_sdp_bw_after_urgent = 80.0,
 267         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,
 268         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
 269         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
 270         .max_avg_sdp_bw_use_normal_percent = 60.0,
 271         .max_avg_dram_bw_use_normal_percent = 60.0,
 272         .fabric_datapath_to_dcn_data_return_bytes = 32,
 273         .return_bus_width_bytes = 64,
 274         .downspread_percent = 0.38,
 275         .dcn_downspread_percent = 0.5,
 276         .gpuvm_min_page_size_bytes = 4096,
 277         .hostvm_min_page_size_bytes = 4096,
 278         .do_urgent_latency_adjustment = false,
 279         .urgent_latency_adjustment_fabric_clock_component_us = 0,
 280         .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
 281 };
 282
 283 enum dcn31_clk_src_array_id {
 284         DCN31_CLK_SRC_PLL0,
 285         DCN31_CLK_SRC_PLL1,
 286         DCN31_CLK_SRC_PLL2,
 287         DCN31_CLK_SRC_PLL3,
 288         DCN31_CLK_SRC_PLL4,
 289         DCN30_CLK_SRC_TOTAL
 290 };
 291
 292 /* begin *********************
 293  * macros to expend register list macro defined in HW object header file
 294  */
 295
 296 /* DCN */
 297 /* TODO awful hack. fixup dcn20_dwb.h */
 298 #undef BASE_INNER
 299 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 300
 301 #define BASE(seg) BASE_INNER(seg)
 302
 303 #define SR(reg_name)\
 304                 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 305                                         reg ## reg_name
 306
 307 #define SRI(reg_name, block, id)\
 308         .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 309                                         reg ## block ## id ## _ ## reg_name
 310
 311 #define SRI2(reg_name, block, id)\
 312         .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 313                                         reg ## reg_name
 314
 315 #define SRIR(var_name, reg_name, block, id)\
 316         .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 317                                         reg ## block ## id ## _ ## reg_name
 318
 319 #define SRII(reg_name, block, id)\
 320         .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 321                                         reg ## block ## id ## _ ## reg_name
 322
 323 #define SRII_MPC_RMU(reg_name, block, id)\
 324         .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 325                                         reg ## block ## id ## _ ## reg_name
 326
 327 #define SRII_DWB(reg_name, temp_name, block, id)\
 328         .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 329                                         reg ## block ## id ## _ ## temp_name
 330
 331 #define DCCG_SRII(reg_name, block, id)\
 332         .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 333                                         reg ## block ## id ## _ ## reg_name
 334
 335 #define VUPDATE_SRII(reg_name, block, id)\
 336         .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 337                                         reg ## reg_name ## _ ## block ## id
 338
 339 /* NBIO */
 340 #define NBIO_BASE_INNER(seg) \
 341         NBIO_BASE__INST0_SEG ## seg
 342
 343 #define NBIO_BASE(seg) \
 344         NBIO_BASE_INNER(seg)
 345
 346 #define NBIO_SR(reg_name)\
 347                 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
 348                                         regBIF_BX2_ ## reg_name
 349
 350 /* MMHUB */
 351 #define MMHUB_BASE_INNER(seg) \
 352         MMHUB_BASE__INST0_SEG ## seg
 353
 354 #define MMHUB_BASE(seg) \
 355         MMHUB_BASE_INNER(seg)
 356
 357 #define MMHUB_SR(reg_name)\
 358                 .reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \
 359                                         reg ## reg_name
 360
 361 /* CLOCK */
 362 #define CLK_BASE_INNER(seg) \
 363         CLK_BASE__INST0_SEG ## seg
 364
 365 #define CLK_BASE(seg) \
 366         CLK_BASE_INNER(seg)
 367
 368 #define CLK_SRI(reg_name, block, inst)\
 369         .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
 370                                         reg ## block ## _ ## inst ## _ ## reg_name
 371
 372
 373 static const struct bios_registers bios_regs = {
 374                 NBIO_SR(BIOS_SCRATCH_3),
 375                 NBIO_SR(BIOS_SCRATCH_6)
 376 };
 377
 378 #define clk_src_regs(index, pllid)\
 379 [index] = {\
 380         CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
 381 }
 382
 383 static const struct dce110_clk_src_regs clk_src_regs[] = {
 384         clk_src_regs(0, A),
 385         clk_src_regs(1, B),
 386         clk_src_regs(2, C),
 387         clk_src_regs(3, D),
 388         clk_src_regs(4, E)
 389 };
 390
 391 static const struct dce110_clk_src_shift cs_shift = {
 392                 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
 393 };
 394
 395 static const struct dce110_clk_src_mask cs_mask = {
 396                 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
 397 };
 398
 399 #define abm_regs(id)\
 400 [id] = {\
 401                 ABM_DCN302_REG_LIST(id)\
 402 }
 403
 404 static const struct dce_abm_registers abm_regs[] = {
 405                 abm_regs(0),
 406                 abm_regs(1),
 407                 abm_regs(2),
 408                 abm_regs(3),
 409 };
 410
 411 static const struct dce_abm_shift abm_shift = {
 412                 ABM_MASK_SH_LIST_DCN30(__SHIFT)
 413 };
 414
 415 static const struct dce_abm_mask abm_mask = {
 416                 ABM_MASK_SH_LIST_DCN30(_MASK)
 417 };
 418
 419 #define audio_regs(id)\
 420 [id] = {\
 421                 AUD_COMMON_REG_LIST(id)\
 422 }
 423
 424 static const struct dce_audio_registers audio_regs[] = {
 425         audio_regs(0),
 426         audio_regs(1),
 427         audio_regs(2),
 428         audio_regs(3),
 429         audio_regs(4),
 430         audio_regs(5),
 431         audio_regs(6)
 432 };
 433
 434 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 435                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 436                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 437                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 438
 439 static const struct dce_audio_shift audio_shift = {
 440                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 441 };
 442
 443 static const struct dce_audio_mask audio_mask = {
 444                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 445 };
 446
 447 #define vpg_regs(id)\
 448 [id] = {\
 449         VPG_DCN31_REG_LIST(id)\
 450 }
 451
 452 static const struct dcn31_vpg_registers vpg_regs[] = {
 453         vpg_regs(0),
 454         vpg_regs(1),
 455         vpg_regs(2),
 456         vpg_regs(3),
 457         vpg_regs(4),
 458         vpg_regs(5),
 459         vpg_regs(6),
 460         vpg_regs(7),
 461         vpg_regs(8),
 462         vpg_regs(9),
 463 };
 464
 465 static const struct dcn31_vpg_shift vpg_shift = {
 466         DCN31_VPG_MASK_SH_LIST(__SHIFT)
 467 };
 468
 469 static const struct dcn31_vpg_mask vpg_mask = {
 470         DCN31_VPG_MASK_SH_LIST(_MASK)
 471 };
 472
 473 #define afmt_regs(id)\
 474 [id] = {\
 475         AFMT_DCN31_REG_LIST(id)\
 476 }
 477
 478 static const struct dcn31_afmt_registers afmt_regs[] = {
 479         afmt_regs(0),
 480         afmt_regs(1),
 481         afmt_regs(2),
 482         afmt_regs(3),
 483         afmt_regs(4),
 484         afmt_regs(5)
 485 };
 486
 487 static const struct dcn31_afmt_shift afmt_shift = {
 488         DCN31_AFMT_MASK_SH_LIST(__SHIFT)
 489 };
 490
 491 static const struct dcn31_afmt_mask afmt_mask = {
 492         DCN31_AFMT_MASK_SH_LIST(_MASK)
 493 };
 494
 495 #define apg_regs(id)\
 496 [id] = {\
 497         APG_DCN31_REG_LIST(id)\
 498 }
 499
 500 static const struct dcn31_apg_registers apg_regs[] = {
 501         apg_regs(0),
 502         apg_regs(1),
 503         apg_regs(2),
 504         apg_regs(3)
 505 };
 506
 507 static const struct dcn31_apg_shift apg_shift = {
 508         DCN31_APG_MASK_SH_LIST(__SHIFT)
 509 };
 510
 511 static const struct dcn31_apg_mask apg_mask = {
 512                 DCN31_APG_MASK_SH_LIST(_MASK)
 513 };
 514
 515 #define stream_enc_regs(id)\
 516 [id] = {\
 517                 SE_DCN314_REG_LIST(id)\
 518 }
 519
 520 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 521         stream_enc_regs(0),
 522         stream_enc_regs(1),
 523         stream_enc_regs(2),
 524         stream_enc_regs(3),
 525         stream_enc_regs(4)
 526 };
 527
 528 static const struct dcn10_stream_encoder_shift se_shift = {
 529                 SE_COMMON_MASK_SH_LIST_DCN314(__SHIFT)
 530 };
 531
 532 static const struct dcn10_stream_encoder_mask se_mask = {
 533                 SE_COMMON_MASK_SH_LIST_DCN314(_MASK)
 534 };
 535
 536
 537 #define aux_regs(id)\
 538 [id] = {\
 539         DCN2_AUX_REG_LIST(id)\
 540 }
 541
 542 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 543                 aux_regs(0),
 544                 aux_regs(1),
 545                 aux_regs(2),
 546                 aux_regs(3),
 547                 aux_regs(4)
 548 };
 549
 550 #define hpd_regs(id)\
 551 [id] = {\
 552         HPD_REG_LIST(id)\
 553 }
 554
 555 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 556                 hpd_regs(0),
 557                 hpd_regs(1),
 558                 hpd_regs(2),
 559                 hpd_regs(3),
 560                 hpd_regs(4)
 561 };
 562
 563 #define link_regs(id, phyid)\
 564 [id] = {\
 565         LE_DCN31_REG_LIST(id), \
 566         UNIPHY_DCN2_REG_LIST(phyid), \
 567 }
 568
 569 static const struct dce110_aux_registers_shift aux_shift = {
 570         DCN_AUX_MASK_SH_LIST(__SHIFT)
 571 };
 572
 573 static const struct dce110_aux_registers_mask aux_mask = {
 574         DCN_AUX_MASK_SH_LIST(_MASK)
 575 };
 576
 577 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 578         link_regs(0, A),
 579         link_regs(1, B),
 580         link_regs(2, C),
 581         link_regs(3, D),
 582         link_regs(4, E)
 583 };
 584
 585 static const struct dcn10_link_enc_shift le_shift = {
 586         LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT),
 587         DPCS_DCN31_MASK_SH_LIST(__SHIFT)
 588 };
 589
 590 static const struct dcn10_link_enc_mask le_mask = {
 591         LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK),
 592         DPCS_DCN31_MASK_SH_LIST(_MASK)
 593 };
 594
 595 #define hpo_dp_stream_encoder_reg_list(id)\
 596 [id] = {\
 597         DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
 598 }
 599
 600 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
 601         hpo_dp_stream_encoder_reg_list(0),
 602         hpo_dp_stream_encoder_reg_list(1),
 603         hpo_dp_stream_encoder_reg_list(2),
 604 };
 605
 606 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
 607         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
 608 };
 609
 610 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
 611         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
 612 };
 613
 614
 615 #define hpo_dp_link_encoder_reg_list(id)\
 616 [id] = {\
 617         DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
 618         DCN3_1_RDPCSTX_REG_LIST(0),\
 619         DCN3_1_RDPCSTX_REG_LIST(1),\
 620         DCN3_1_RDPCSTX_REG_LIST(2),\
 621 }
 622
 623 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
 624         hpo_dp_link_encoder_reg_list(0),
 625         hpo_dp_link_encoder_reg_list(1),
 626 };
 627
 628 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
 629         DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
 630 };
 631
 632 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
 633         DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
 634 };
 635
 636 #define dpp_regs(id)\
 637 [id] = {\
 638         DPP_REG_LIST_DCN30(id),\
 639 }
 640
 641 static const struct dcn3_dpp_registers dpp_regs[] = {
 642         dpp_regs(0),
 643         dpp_regs(1),
 644         dpp_regs(2),
 645         dpp_regs(3)
 646 };
 647
 648 static const struct dcn3_dpp_shift tf_shift = {
 649                 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
 650 };
 651
 652 static const struct dcn3_dpp_mask tf_mask = {
 653                 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
 654 };
 655
 656 #define opp_regs(id)\
 657 [id] = {\
 658         OPP_REG_LIST_DCN30(id),\
 659 }
 660
 661 static const struct dcn20_opp_registers opp_regs[] = {
 662         opp_regs(0),
 663         opp_regs(1),
 664         opp_regs(2),
 665         opp_regs(3)
 666 };
 667
 668 static const struct dcn20_opp_shift opp_shift = {
 669         OPP_MASK_SH_LIST_DCN20(__SHIFT)
 670 };
 671
 672 static const struct dcn20_opp_mask opp_mask = {
 673         OPP_MASK_SH_LIST_DCN20(_MASK)
 674 };
 675
 676 #define aux_engine_regs(id)\
 677 [id] = {\
 678         AUX_COMMON_REG_LIST0(id), \
 679         .AUXN_IMPCAL = 0, \
 680         .AUXP_IMPCAL = 0, \
 681         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 682 }
 683
 684 static const struct dce110_aux_registers aux_engine_regs[] = {
 685                 aux_engine_regs(0),
 686                 aux_engine_regs(1),
 687                 aux_engine_regs(2),
 688                 aux_engine_regs(3),
 689                 aux_engine_regs(4)
 690 };
 691
 692 #define dwbc_regs_dcn3(id)\
 693 [id] = {\
 694         DWBC_COMMON_REG_LIST_DCN30(id),\
 695 }
 696
 697 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 698         dwbc_regs_dcn3(0),
 699 };
 700
 701 static const struct dcn30_dwbc_shift dwbc30_shift = {
 702         DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 703 };
 704
 705 static const struct dcn30_dwbc_mask dwbc30_mask = {
 706         DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 707 };
 708
 709 #define mcif_wb_regs_dcn3(id)\
 710 [id] = {\
 711         MCIF_WB_COMMON_REG_LIST_DCN30(id),\
 712 }
 713
 714 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 715         mcif_wb_regs_dcn3(0)
 716 };
 717
 718 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 719         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 720 };
 721
 722 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 723         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
 724 };
 725
 726 #define dsc_regsDCN314(id)\
 727 [id] = {\
 728         DSC_REG_LIST_DCN314(id)\
 729 }
 730
 731 static const struct dcn20_dsc_registers dsc_regs[] = {
 732         dsc_regsDCN314(0),
 733         dsc_regsDCN314(1),
 734         dsc_regsDCN314(2),
 735         dsc_regsDCN314(3)
 736 };
 737
 738 static const struct dcn20_dsc_shift dsc_shift = {
 739         DSC_REG_LIST_SH_MASK_DCN314(__SHIFT)
 740 };
 741
 742 static const struct dcn20_dsc_mask dsc_mask = {
 743         DSC_REG_LIST_SH_MASK_DCN314(_MASK)
 744 };
 745
 746 static const struct dcn30_mpc_registers mpc_regs = {
 747                 MPC_REG_LIST_DCN3_0(0),
 748                 MPC_REG_LIST_DCN3_0(1),
 749                 MPC_REG_LIST_DCN3_0(2),
 750                 MPC_REG_LIST_DCN3_0(3),
 751                 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 752                 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 753                 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
 754                 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
 755                 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
 756                 MPC_RMU_REG_LIST_DCN3AG(0),
 757                 MPC_RMU_REG_LIST_DCN3AG(1),
 758                 //MPC_RMU_REG_LIST_DCN3AG(2),
 759                 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 760 };
 761
 762 static const struct dcn30_mpc_shift mpc_shift = {
 763         MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 764 };
 765
 766 static const struct dcn30_mpc_mask mpc_mask = {
 767         MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 768 };
 769
 770 #define optc_regs(id)\
 771 [id] = {OPTC_COMMON_REG_LIST_DCN3_14(id)}
 772
 773 static const struct dcn_optc_registers optc_regs[] = {
 774         optc_regs(0),
 775         optc_regs(1),
 776         optc_regs(2),
 777         optc_regs(3)
 778 };
 779
 780 static const struct dcn_optc_shift optc_shift = {
 781         OPTC_COMMON_MASK_SH_LIST_DCN3_14(__SHIFT)
 782 };
 783
 784 static const struct dcn_optc_mask optc_mask = {
 785         OPTC_COMMON_MASK_SH_LIST_DCN3_14(_MASK)
 786 };
 787
 788 #define hubp_regs(id)\
 789 [id] = {\
 790         HUBP_REG_LIST_DCN30(id)\
 791 }
 792
 793 static const struct dcn_hubp2_registers hubp_regs[] = {
 794                 hubp_regs(0),
 795                 hubp_regs(1),
 796                 hubp_regs(2),
 797                 hubp_regs(3)
 798 };
 799
 800
 801 static const struct dcn_hubp2_shift hubp_shift = {
 802                 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
 803 };
 804
 805 static const struct dcn_hubp2_mask hubp_mask = {
 806                 HUBP_MASK_SH_LIST_DCN31(_MASK)
 807 };
 808 static const struct dcn_hubbub_registers hubbub_reg = {
 809                 HUBBUB_REG_LIST_DCN31(0)
 810 };
 811
 812 static const struct dcn_hubbub_shift hubbub_shift = {
 813                 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
 814 };
 815
 816 static const struct dcn_hubbub_mask hubbub_mask = {
 817                 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
 818 };
 819
 820 static const struct dccg_registers dccg_regs = {
 821                 DCCG_REG_LIST_DCN314()
 822 };
 823
 824 static const struct dccg_shift dccg_shift = {
 825                 DCCG_MASK_SH_LIST_DCN314(__SHIFT)
 826 };
 827
 828 static const struct dccg_mask dccg_mask = {
 829                 DCCG_MASK_SH_LIST_DCN314(_MASK)
 830 };
 831
 832
 833 #define SRII2(reg_name_pre, reg_name_post, id)\
 834         .reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 835                         ## id ## _ ## reg_name_post ## _BASE_IDX) + \
 836                         reg ## reg_name_pre ## id ## _ ## reg_name_post
 837
 838
 839 #define HWSEQ_DCN31_REG_LIST()\
 840         SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
 841         SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
 842         SR(DIO_MEM_PWR_CTRL), \
 843         SR(ODM_MEM_PWR_CTRL3), \
 844         SR(DMU_MEM_PWR_CNTL), \
 845         SR(MMHUBBUB_MEM_PWR_CNTL), \
 846         SR(DCCG_GATE_DISABLE_CNTL), \
 847         SR(DCCG_GATE_DISABLE_CNTL2), \
 848         SR(DCFCLK_CNTL),\
 849         SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
 850         SRII(PIXEL_RATE_CNTL, OTG, 0), \
 851         SRII(PIXEL_RATE_CNTL, OTG, 1),\
 852         SRII(PIXEL_RATE_CNTL, OTG, 2),\
 853         SRII(PIXEL_RATE_CNTL, OTG, 3),\
 854         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
 855         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
 856         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
 857         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
 858         SR(MICROSECOND_TIME_BASE_DIV), \
 859         SR(MILLISECOND_TIME_BASE_DIV), \
 860         SR(DISPCLK_FREQ_CHANGE_CNTL), \
 861         SR(RBBMIF_TIMEOUT_DIS), \
 862         SR(RBBMIF_TIMEOUT_DIS_2), \
 863         SR(DCHUBBUB_CRC_CTRL), \
 864         SR(DPP_TOP0_DPP_CRC_CTRL), \
 865         SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
 866         SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
 867         SR(MPC_CRC_CTRL), \
 868         SR(MPC_CRC_RESULT_GB), \
 869         SR(MPC_CRC_RESULT_C), \
 870         SR(MPC_CRC_RESULT_AR), \
 871         SR(DOMAIN0_PG_CONFIG), \
 872         SR(DOMAIN1_PG_CONFIG), \
 873         SR(DOMAIN2_PG_CONFIG), \
 874         SR(DOMAIN3_PG_CONFIG), \
 875         SR(DOMAIN16_PG_CONFIG), \
 876         SR(DOMAIN17_PG_CONFIG), \
 877         SR(DOMAIN18_PG_CONFIG), \
 878         SR(DOMAIN19_PG_CONFIG), \
 879         SR(DOMAIN0_PG_STATUS), \
 880         SR(DOMAIN1_PG_STATUS), \
 881         SR(DOMAIN2_PG_STATUS), \
 882         SR(DOMAIN3_PG_STATUS), \
 883         SR(DOMAIN16_PG_STATUS), \
 884         SR(DOMAIN17_PG_STATUS), \
 885         SR(DOMAIN18_PG_STATUS), \
 886         SR(DOMAIN19_PG_STATUS), \
 887         SR(D1VGA_CONTROL), \
 888         SR(D2VGA_CONTROL), \
 889         SR(D3VGA_CONTROL), \
 890         SR(D4VGA_CONTROL), \
 891         SR(D5VGA_CONTROL), \
 892         SR(D6VGA_CONTROL), \
 893         SR(DC_IP_REQUEST_CNTL), \
 894         SR(AZALIA_AUDIO_DTO), \
 895         SR(AZALIA_CONTROLLER_CLOCK_GATING), \
 896         SR(HPO_TOP_HW_CONTROL)
 897
 898 static const struct dce_hwseq_registers hwseq_reg = {
 899                 HWSEQ_DCN31_REG_LIST()
 900 };
 901
 902 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
 903         HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 904         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 905         HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
 906         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 907         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 908         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 909         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 910         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 911         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 912         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 913         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 914         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 915         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 916         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 917         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 918         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 919         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 920         HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 921         HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 922         HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 923         HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 924         HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 925         HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 926         HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 927         HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 928         HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 929         HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 930         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 931         HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 932         HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 933         HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
 934         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 935         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
 936         HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
 937         HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
 938         HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
 939
 940 static const struct dce_hwseq_shift hwseq_shift = {
 941                 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
 942 };
 943
 944 static const struct dce_hwseq_mask hwseq_mask = {
 945                 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
 946 };
 947 #define vmid_regs(id)\
 948 [id] = {\
 949                 DCN20_VMID_REG_LIST(id)\
 950 }
 951
 952 static const struct dcn_vmid_registers vmid_regs[] = {
 953         vmid_regs(0),
 954         vmid_regs(1),
 955         vmid_regs(2),
 956         vmid_regs(3),
 957         vmid_regs(4),
 958         vmid_regs(5),
 959         vmid_regs(6),
 960         vmid_regs(7),
 961         vmid_regs(8),
 962         vmid_regs(9),
 963         vmid_regs(10),
 964         vmid_regs(11),
 965         vmid_regs(12),
 966         vmid_regs(13),
 967         vmid_regs(14),
 968         vmid_regs(15)
 969 };
 970
 971 static const struct dcn20_vmid_shift vmid_shifts = {
 972                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 973 };
 974
 975 static const struct dcn20_vmid_mask vmid_masks = {
 976                 DCN20_VMID_MASK_SH_LIST(_MASK)
 977 };
 978
 979 static const struct resource_caps res_cap_dcn314 = {
 980         .num_timing_generator = 4,
 981         .num_opp = 4,
 982         .num_video_plane = 4,
 983         .num_audio = 5,
 984         .num_stream_encoder = 5,
 985         .num_dig_link_enc = 5,
 986         .num_hpo_dp_stream_encoder = 4,
 987         .num_hpo_dp_link_encoder = 2,
 988         .num_pll = 5,
 989         .num_dwb = 1,
 990         .num_ddc = 5,
 991         .num_vmid = 16,
 992         .num_mpc_3dlut = 2,
 993         .num_dsc = 4,
 994 };
 995
 996 static const struct dc_plane_cap plane_cap = {
 997         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 998         .blends_with_above = true,
 999         .blends_with_below = true,
1000         .per_pixel_alpha = true,
1001
1002         .pixel_format_support = {
1003                         .argb8888 = true,
1004                         .nv12 = true,
1005                         .fp16 = true,
1006                         .p010 = true,
1007                         .ayuv = false,
1008         },
1009
1010         .max_upscale_factor = {
1011                         .argb8888 = 16000,
1012                         .nv12 = 16000,
1013                         .fp16 = 16000
1014         },
1015
1016         // 6:1 downscaling ratio: 1000/6 = 166.666
1017         .max_downscale_factor = {
1018                         .argb8888 = 167,
1019                         .nv12 = 167,
1020                         .fp16 = 167
1021         },
1022         64,
1023         64
1024 };
1025
1026 static const struct dc_debug_options debug_defaults_drv = {
1027         .disable_z10 = true, /*hw not support it*/
1028         .disable_dmcu = true,
1029         .force_abm_enable = false,
1030         .timing_trace = false,
1031         .clock_trace = true,
1032         .disable_pplib_clock_request = false,
1033         .pipe_split_policy = MPC_SPLIT_DYNAMIC,
1034         .force_single_disp_pipe_split = false,
1035         .disable_dcc = DCC_ENABLE,
1036         .vsr_support = true,
1037         .performance_trace = false,
1038         .max_downscale_src_width = 4096,/*upto true 4k*/
1039         .disable_pplib_wm_range = false,
1040         .scl_reset_length10 = true,
1041         .sanity_checks = false,
1042         .underflow_assert_delay_us = 0xFFFFFFFF,
1043         .dwb_fi_phase = -1, // -1 = disable,
1044         .dmub_command_table = true,
1045         .pstate_enabled = true,
1046         .use_max_lb = true,
1047         .enable_mem_low_power = {
1048                 .bits = {
1049                         .vga = true,
1050                         .i2c = true,
1051                         .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
1052                         .dscl = true,
1053                         .cm = true,
1054                         .mpc = true,
1055                         .optc = true,
1056                         .vpg = true,
1057                         .afmt = true,
1058                 }
1059         },
1060         .optimize_edp_link_rate = true,
1061         .enable_sw_cntl_psr = true,
1062         .seamless_boot_odm_combine = true
1063 };
1064
1065 static const struct dc_debug_options debug_defaults_diags = {
1066         .disable_dmcu = true,
1067         .force_abm_enable = false,
1068         .timing_trace = true,
1069         .clock_trace = true,
1070         .disable_dpp_power_gate = true,
1071         .disable_hubp_power_gate = true,
1072         .disable_clock_gate = true,
1073         .disable_pplib_clock_request = true,
1074         .disable_pplib_wm_range = true,
1075         .disable_stutter = false,
1076         .scl_reset_length10 = true,
1077         .dwb_fi_phase = -1, // -1 = disable
1078         .dmub_command_table = true,
1079         .enable_tri_buf = true,
1080         .use_max_lb = true
1081 };
1082
1083 static void dcn31_dpp_destroy(struct dpp **dpp)
1084 {
1085         kfree(TO_DCN20_DPP(*dpp));
1086         *dpp = NULL;
1087 }
1088
1089 static struct dpp *dcn31_dpp_create(
1090         struct dc_context *ctx,
1091         uint32_t inst)
1092 {
1093         struct dcn3_dpp *dpp =
1094                 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
1095
1096         if (!dpp)
1097                 return NULL;
1098
1099         if (dpp3_construct(dpp, ctx, inst,
1100                         &dpp_regs[inst], &tf_shift, &tf_mask))
1101                 return &dpp->base;
1102
1103         BREAK_TO_DEBUGGER();
1104         kfree(dpp);
1105         return NULL;
1106 }
1107
1108 static struct output_pixel_processor *dcn31_opp_create(
1109         struct dc_context *ctx, uint32_t inst)
1110 {
1111         struct dcn20_opp *opp =
1112                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1113
1114         if (!opp) {
1115                 BREAK_TO_DEBUGGER();
1116                 return NULL;
1117         }
1118
1119         dcn20_opp_construct(opp, ctx, inst,
1120                         &opp_regs[inst], &opp_shift, &opp_mask);
1121         return &opp->base;
1122 }
1123
1124 static struct dce_aux *dcn31_aux_engine_create(
1125         struct dc_context *ctx,
1126         uint32_t inst)
1127 {
1128         struct aux_engine_dce110 *aux_engine =
1129                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1130
1131         if (!aux_engine)
1132                 return NULL;
1133
1134         dce110_aux_engine_construct(aux_engine, ctx, inst,
1135                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1136                                     &aux_engine_regs[inst],
1137                                         &aux_mask,
1138                                         &aux_shift,
1139                                         ctx->dc->caps.extended_aux_timeout_support);
1140
1141         return &aux_engine->base;
1142 }
1143 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
1144
1145 static const struct dce_i2c_registers i2c_hw_regs[] = {
1146                 i2c_inst_regs(1),
1147                 i2c_inst_regs(2),
1148                 i2c_inst_regs(3),
1149                 i2c_inst_regs(4),
1150                 i2c_inst_regs(5),
1151 };
1152
1153 static const struct dce_i2c_shift i2c_shifts = {
1154                 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
1155 };
1156
1157 static const struct dce_i2c_mask i2c_masks = {
1158                 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1159 };
1160
1161 static struct dce_i2c_hw *dcn31_i2c_hw_create(
1162         struct dc_context *ctx,
1163         uint32_t inst)
1164 {
1165         struct dce_i2c_hw *dce_i2c_hw =
1166                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1167
1168         if (!dce_i2c_hw)
1169                 return NULL;
1170
1171         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1172                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1173
1174         return dce_i2c_hw;
1175 }
1176 static struct mpc *dcn31_mpc_create(
1177                 struct dc_context *ctx,
1178                 int num_mpcc,
1179                 int num_rmu)
1180 {
1181         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1182                                           GFP_KERNEL);
1183
1184         if (!mpc30)
1185                 return NULL;
1186
1187         dcn30_mpc_construct(mpc30, ctx,
1188                         &mpc_regs,
1189                         &mpc_shift,
1190                         &mpc_mask,
1191                         num_mpcc,
1192                         num_rmu);
1193
1194         return &mpc30->base;
1195 }
1196
1197 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1198 {
1199         int i;
1200
1201         struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1202                                           GFP_KERNEL);
1203
1204         if (!hubbub3)
1205                 return NULL;
1206
1207         hubbub31_construct(hubbub3, ctx,
1208                         &hubbub_reg,
1209                         &hubbub_shift,
1210                         &hubbub_mask,
1211                         dcn3_14_ip.det_buffer_size_kbytes,
1212                         dcn3_14_ip.pixel_chunk_size_kbytes,
1213                         dcn3_14_ip.config_return_buffer_size_in_kbytes);
1214
1215
1216         for (i = 0; i < res_cap_dcn314.num_vmid; i++) {
1217                 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1218
1219                 vmid->ctx = ctx;
1220
1221                 vmid->regs = &vmid_regs[i];
1222                 vmid->shifts = &vmid_shifts;
1223                 vmid->masks = &vmid_masks;
1224         }
1225
1226         return &hubbub3->base;
1227 }
1228
1229 static struct timing_generator *dcn31_timing_generator_create(
1230                 struct dc_context *ctx,
1231                 uint32_t instance)
1232 {
1233         struct optc *tgn10 =
1234                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1235
1236         if (!tgn10)
1237                 return NULL;
1238
1239         tgn10->base.inst = instance;
1240         tgn10->base.ctx = ctx;
1241
1242         tgn10->tg_regs = &optc_regs[instance];
1243         tgn10->tg_shift = &optc_shift;
1244         tgn10->tg_mask = &optc_mask;
1245
1246         dcn314_timing_generator_init(tgn10);
1247
1248         return &tgn10->base;
1249 }
1250
1251 static const struct encoder_feature_support link_enc_feature = {
1252                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1253                 .max_hdmi_pixel_clock = 600000,
1254                 .hdmi_ycbcr420_supported = true,
1255                 .dp_ycbcr420_supported = true,
1256                 .fec_supported = true,
1257                 .flags.bits.IS_HBR2_CAPABLE = true,
1258                 .flags.bits.IS_HBR3_CAPABLE = true,
1259                 .flags.bits.IS_TPS3_CAPABLE = true,
1260                 .flags.bits.IS_TPS4_CAPABLE = true
1261 };
1262
1263 static struct link_encoder *dcn31_link_encoder_create(
1264         const struct encoder_init_data *enc_init_data)
1265 {
1266         struct dcn20_link_encoder *enc20 =
1267                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1268
1269         if (!enc20)
1270                 return NULL;
1271
1272         dcn31_link_encoder_construct(enc20,
1273                         enc_init_data,
1274                         &link_enc_feature,
1275                         &link_enc_regs[enc_init_data->transmitter],
1276                         &link_enc_aux_regs[enc_init_data->channel - 1],
1277                         &link_enc_hpd_regs[enc_init_data->hpd_source],
1278                         &le_shift,
1279                         &le_mask);
1280
1281         return &enc20->enc10.base;
1282 }
1283
1284 /* Create a minimal link encoder object not associated with a particular
1285  * physical connector.
1286  * resource_funcs.link_enc_create_minimal
1287  */
1288 static struct link_encoder *dcn31_link_enc_create_minimal(
1289                 struct dc_context *ctx, enum engine_id eng_id)
1290 {
1291         struct dcn20_link_encoder *enc20;
1292
1293         if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1294                 return NULL;
1295
1296         enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1297         if (!enc20)
1298                 return NULL;
1299
1300         dcn31_link_encoder_construct_minimal(
1301                         enc20,
1302                         ctx,
1303                         &link_enc_feature,
1304                         &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1305                         eng_id);
1306
1307         return &enc20->enc10.base;
1308 }
1309
1310 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1311 {
1312         struct dcn31_panel_cntl *panel_cntl =
1313                 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1314
1315         if (!panel_cntl)
1316                 return NULL;
1317
1318         dcn31_panel_cntl_construct(panel_cntl, init_data);
1319
1320         return &panel_cntl->base;
1321 }
1322
1323 static void read_dce_straps(
1324         struct dc_context *ctx,
1325         struct resource_straps *straps)
1326 {
1327         generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1328                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1329
1330 }
1331
1332 static struct audio *dcn31_create_audio(
1333                 struct dc_context *ctx, unsigned int inst)
1334 {
1335         return dce_audio_create(ctx, inst,
1336                         &audio_regs[inst], &audio_shift, &audio_mask);
1337 }
1338
1339 static struct vpg *dcn31_vpg_create(
1340         struct dc_context *ctx,
1341         uint32_t inst)
1342 {
1343         struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1344
1345         if (!vpg31)
1346                 return NULL;
1347
1348         vpg31_construct(vpg31, ctx, inst,
1349                         &vpg_regs[inst],
1350                         &vpg_shift,
1351                         &vpg_mask);
1352
1353         return &vpg31->base;
1354 }
1355
1356 static struct afmt *dcn31_afmt_create(
1357         struct dc_context *ctx,
1358         uint32_t inst)
1359 {
1360         struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1361
1362         if (!afmt31)
1363                 return NULL;
1364
1365         afmt31_construct(afmt31, ctx, inst,
1366                         &afmt_regs[inst],
1367                         &afmt_shift,
1368                         &afmt_mask);
1369
1370         // Light sleep by default, no need to power down here
1371
1372         return &afmt31->base;
1373 }
1374
1375 static struct apg *dcn31_apg_create(
1376         struct dc_context *ctx,
1377         uint32_t inst)
1378 {
1379         struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1380
1381         if (!apg31)
1382                 return NULL;
1383
1384         apg31_construct(apg31, ctx, inst,
1385                         &apg_regs[inst],
1386                         &apg_shift,
1387                         &apg_mask);
1388
1389         return &apg31->base;
1390 }
1391
1392 static struct stream_encoder *dcn314_stream_encoder_create(
1393         enum engine_id eng_id,
1394         struct dc_context *ctx)
1395 {
1396         struct dcn10_stream_encoder *enc1;
1397         struct vpg *vpg;
1398         struct afmt *afmt;
1399         int vpg_inst;
1400         int afmt_inst;
1401
1402         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1403         if (eng_id <= ENGINE_ID_DIGF) {
1404                 vpg_inst = eng_id;
1405                 afmt_inst = eng_id;
1406         } else
1407                 return NULL;
1408
1409         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1410         vpg = dcn31_vpg_create(ctx, vpg_inst);
1411         afmt = dcn31_afmt_create(ctx, afmt_inst);
1412
1413         if (!enc1 || !vpg || !afmt) {
1414                 kfree(enc1);
1415                 kfree(vpg);
1416                 kfree(afmt);
1417                 return NULL;
1418         }
1419
1420         dcn314_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1421                                         eng_id, vpg, afmt,
1422                                         &stream_enc_regs[eng_id],
1423                                         &se_shift, &se_mask);
1424
1425         return &enc1->base;
1426 }
1427
1428 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1429         enum engine_id eng_id,
1430         struct dc_context *ctx)
1431 {
1432         struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1433         struct vpg *vpg;
1434         struct apg *apg;
1435         uint32_t hpo_dp_inst;
1436         uint32_t vpg_inst;
1437         uint32_t apg_inst;
1438
1439         ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1440         hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1441
1442         /* Mapping of VPG register blocks to HPO DP block instance:
1443          * VPG[6] -> HPO_DP[0]
1444          * VPG[7] -> HPO_DP[1]
1445          * VPG[8] -> HPO_DP[2]
1446          * VPG[9] -> HPO_DP[3]
1447          */
1448         vpg_inst = hpo_dp_inst + 6;
1449
1450         /* Mapping of APG register blocks to HPO DP block instance:
1451          * APG[0] -> HPO_DP[0]
1452          * APG[1] -> HPO_DP[1]
1453          * APG[2] -> HPO_DP[2]
1454          * APG[3] -> HPO_DP[3]
1455          */
1456         apg_inst = hpo_dp_inst;
1457
1458         /* allocate HPO stream encoder and create VPG sub-block */
1459         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1460         vpg = dcn31_vpg_create(ctx, vpg_inst);
1461         apg = dcn31_apg_create(ctx, apg_inst);
1462
1463         if (!hpo_dp_enc31 || !vpg || !apg) {
1464                 kfree(hpo_dp_enc31);
1465                 kfree(vpg);
1466                 kfree(apg);
1467                 return NULL;
1468         }
1469
1470         dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1471                                         hpo_dp_inst, eng_id, vpg, apg,
1472                                         &hpo_dp_stream_enc_regs[hpo_dp_inst],
1473                                         &hpo_dp_se_shift, &hpo_dp_se_mask);
1474
1475         return &hpo_dp_enc31->base;
1476 }
1477
1478 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1479         uint8_t inst,
1480         struct dc_context *ctx)
1481 {
1482         struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1483
1484         /* allocate HPO link encoder */
1485         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1486
1487         hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1488                                         &hpo_dp_link_enc_regs[inst],
1489                                         &hpo_dp_le_shift, &hpo_dp_le_mask);
1490
1491         return &hpo_dp_enc31->base;
1492 }
1493
1494 static struct dce_hwseq *dcn314_hwseq_create(
1495         struct dc_context *ctx)
1496 {
1497         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1498
1499         if (hws) {
1500                 hws->ctx = ctx;
1501                 hws->regs = &hwseq_reg;
1502                 hws->shifts = &hwseq_shift;
1503                 hws->masks = &hwseq_mask;
1504                 /* DCN3.1 FPGA Workaround
1505                  * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1506                  * To do so, move calling function enable_stream_timing to only be done AFTER calling
1507                  * function core_link_enable_stream
1508                  */
1509                 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
1510                         hws->wa.dp_hpo_and_otg_sequence = true;
1511         }
1512         return hws;
1513 }
1514 static const struct resource_create_funcs res_create_funcs = {
1515         .read_dce_straps = read_dce_straps,
1516         .create_audio = dcn31_create_audio,
1517         .create_stream_encoder = dcn314_stream_encoder_create,
1518         .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1519         .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1520         .create_hwseq = dcn314_hwseq_create,
1521 };
1522
1523 static const struct resource_create_funcs res_create_maximus_funcs = {
1524         .read_dce_straps = NULL,
1525         .create_audio = NULL,
1526         .create_stream_encoder = NULL,
1527         .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1528         .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1529         .create_hwseq = dcn314_hwseq_create,
1530 };
1531
1532 static void dcn314_resource_destruct(struct dcn314_resource_pool *pool)
1533 {
1534         unsigned int i;
1535
1536         for (i = 0; i < pool->base.stream_enc_count; i++) {
1537                 if (pool->base.stream_enc[i] != NULL) {
1538                         if (pool->base.stream_enc[i]->vpg != NULL) {
1539                                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1540                                 pool->base.stream_enc[i]->vpg = NULL;
1541                         }
1542                         if (pool->base.stream_enc[i]->afmt != NULL) {
1543                                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1544                                 pool->base.stream_enc[i]->afmt = NULL;
1545                         }
1546                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1547                         pool->base.stream_enc[i] = NULL;
1548                 }
1549         }
1550
1551         for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1552                 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1553                         if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1554                                 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1555                                 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1556                         }
1557                         if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1558                                 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1559                                 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1560                         }
1561                         kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1562                         pool->base.hpo_dp_stream_enc[i] = NULL;
1563                 }
1564         }
1565
1566         for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1567                 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1568                         kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1569                         pool->base.hpo_dp_link_enc[i] = NULL;
1570                 }
1571         }
1572
1573         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1574                 if (pool->base.dscs[i] != NULL)
1575                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1576         }
1577
1578         if (pool->base.mpc != NULL) {
1579                 kfree(TO_DCN20_MPC(pool->base.mpc));
1580                 pool->base.mpc = NULL;
1581         }
1582         if (pool->base.hubbub != NULL) {
1583                 kfree(pool->base.hubbub);
1584                 pool->base.hubbub = NULL;
1585         }
1586         for (i = 0; i < pool->base.pipe_count; i++) {
1587                 if (pool->base.dpps[i] != NULL)
1588                         dcn31_dpp_destroy(&pool->base.dpps[i]);
1589
1590                 if (pool->base.ipps[i] != NULL)
1591                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1592
1593                 if (pool->base.hubps[i] != NULL) {
1594                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1595                         pool->base.hubps[i] = NULL;
1596                 }
1597
1598                 if (pool->base.irqs != NULL)
1599                         dal_irq_service_destroy(&pool->base.irqs);
1600         }
1601
1602         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1603                 if (pool->base.engines[i] != NULL)
1604                         dce110_engine_destroy(&pool->base.engines[i]);
1605                 if (pool->base.hw_i2cs[i] != NULL) {
1606                         kfree(pool->base.hw_i2cs[i]);
1607                         pool->base.hw_i2cs[i] = NULL;
1608                 }
1609                 if (pool->base.sw_i2cs[i] != NULL) {
1610                         kfree(pool->base.sw_i2cs[i]);
1611                         pool->base.sw_i2cs[i] = NULL;
1612                 }
1613         }
1614
1615         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1616                 if (pool->base.opps[i] != NULL)
1617                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1618         }
1619
1620         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1621                 if (pool->base.timing_generators[i] != NULL)    {
1622                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1623                         pool->base.timing_generators[i] = NULL;
1624                 }
1625         }
1626
1627         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1628                 if (pool->base.dwbc[i] != NULL) {
1629                         kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1630                         pool->base.dwbc[i] = NULL;
1631                 }
1632                 if (pool->base.mcif_wb[i] != NULL) {
1633                         kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1634                         pool->base.mcif_wb[i] = NULL;
1635                 }
1636         }
1637
1638         for (i = 0; i < pool->base.audio_count; i++) {
1639                 if (pool->base.audios[i])
1640                         dce_aud_destroy(&pool->base.audios[i]);
1641         }
1642
1643         for (i = 0; i < pool->base.clk_src_count; i++) {
1644                 if (pool->base.clock_sources[i] != NULL) {
1645                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1646                         pool->base.clock_sources[i] = NULL;
1647                 }
1648         }
1649
1650         for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1651                 if (pool->base.mpc_lut[i] != NULL) {
1652                         dc_3dlut_func_release(pool->base.mpc_lut[i]);
1653                         pool->base.mpc_lut[i] = NULL;
1654                 }
1655                 if (pool->base.mpc_shaper[i] != NULL) {
1656                         dc_transfer_func_release(pool->base.mpc_shaper[i]);
1657                         pool->base.mpc_shaper[i] = NULL;
1658                 }
1659         }
1660
1661         if (pool->base.dp_clock_source != NULL) {
1662                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1663                 pool->base.dp_clock_source = NULL;
1664         }
1665
1666         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1667                 if (pool->base.multiple_abms[i] != NULL)
1668                         dce_abm_destroy(&pool->base.multiple_abms[i]);
1669         }
1670
1671         if (pool->base.psr != NULL)
1672                 dmub_psr_destroy(&pool->base.psr);
1673
1674         if (pool->base.dccg != NULL)
1675                 dcn_dccg_destroy(&pool->base.dccg);
1676 }
1677
1678 static struct hubp *dcn31_hubp_create(
1679         struct dc_context *ctx,
1680         uint32_t inst)
1681 {
1682         struct dcn20_hubp *hubp2 =
1683                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1684
1685         if (!hubp2)
1686                 return NULL;
1687
1688         if (hubp31_construct(hubp2, ctx, inst,
1689                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1690                 return &hubp2->base;
1691
1692         BREAK_TO_DEBUGGER();
1693         kfree(hubp2);
1694         return NULL;
1695 }
1696
1697 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1698 {
1699         int i;
1700         uint32_t pipe_count = pool->res_cap->num_dwb;
1701
1702         for (i = 0; i < pipe_count; i++) {
1703                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1704                                                     GFP_KERNEL);
1705
1706                 if (!dwbc30) {
1707                         dm_error("DC: failed to create dwbc30!\n");
1708                         return false;
1709                 }
1710
1711                 dcn30_dwbc_construct(dwbc30, ctx,
1712                                 &dwbc30_regs[i],
1713                                 &dwbc30_shift,
1714                                 &dwbc30_mask,
1715                                 i);
1716
1717                 pool->dwbc[i] = &dwbc30->base;
1718         }
1719         return true;
1720 }
1721
1722 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1723 {
1724         int i;
1725         uint32_t pipe_count = pool->res_cap->num_dwb;
1726
1727         for (i = 0; i < pipe_count; i++) {
1728                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1729                                                     GFP_KERNEL);
1730
1731                 if (!mcif_wb30) {
1732                         dm_error("DC: failed to create mcif_wb30!\n");
1733                         return false;
1734                 }
1735
1736                 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1737                                 &mcif_wb30_regs[i],
1738                                 &mcif_wb30_shift,
1739                                 &mcif_wb30_mask,
1740                                 i);
1741
1742                 pool->mcif_wb[i] = &mcif_wb30->base;
1743         }
1744         return true;
1745 }
1746
1747 static struct display_stream_compressor *dcn314_dsc_create(
1748         struct dc_context *ctx, uint32_t inst)
1749 {
1750         struct dcn20_dsc *dsc =
1751                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1752
1753         if (!dsc) {
1754                 BREAK_TO_DEBUGGER();
1755                 return NULL;
1756         }
1757
1758         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1759         return &dsc->base;
1760 }
1761
1762 static void dcn314_destroy_resource_pool(struct resource_pool **pool)
1763 {
1764         struct dcn314_resource_pool *dcn314_pool = TO_DCN314_RES_POOL(*pool);
1765
1766         dcn314_resource_destruct(dcn314_pool);
1767         kfree(dcn314_pool);
1768         *pool = NULL;
1769 }
1770
1771 static struct clock_source *dcn31_clock_source_create(
1772                 struct dc_context *ctx,
1773                 struct dc_bios *bios,
1774                 enum clock_source_id id,
1775                 const struct dce110_clk_src_regs *regs,
1776                 bool dp_clk_src)
1777 {
1778         struct dce110_clk_src *clk_src =
1779                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1780
1781         if (!clk_src)
1782                 return NULL;
1783
1784         if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1785                         regs, &cs_shift, &cs_mask)) {
1786                 clk_src->base.dp_clk_src = dp_clk_src;
1787                 return &clk_src->base;
1788         }
1789
1790         BREAK_TO_DEBUGGER();
1791         return NULL;
1792 }
1793
1794 static bool is_dual_plane(enum surface_pixel_format format)
1795 {
1796         return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1797 }
1798
1799 static int dcn314_populate_dml_pipes_from_context(
1800         struct dc *dc, struct dc_state *context,
1801         display_e2e_pipe_params_st *pipes,
1802         bool fast_validate)
1803 {
1804         int i, pipe_cnt;
1805         struct resource_context *res_ctx = &context->res_ctx;
1806         struct pipe_ctx *pipe;
1807         bool upscaled = false;
1808
1809         dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1810
1811         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1812                 struct dc_crtc_timing *timing;
1813
1814                 if (!res_ctx->pipe_ctx[i].stream)
1815                         continue;
1816                 pipe = &res_ctx->pipe_ctx[i];
1817                 timing = &pipe->stream->timing;
1818
1819                 if (dc_extended_blank_supported(dc) && pipe->stream->adjust.v_total_max == pipe->stream->adjust.v_total_min
1820                         && pipe->stream->adjust.v_total_min > timing->v_total)
1821                         pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min;
1822
1823                 if (pipe->plane_state &&
1824                                 (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height ||
1825                                 pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width))
1826                         upscaled = true;
1827
1828                 /*
1829                  * Immediate flip can be set dynamically after enabling the plane.
1830                  * We need to require support for immediate flip or underflow can be
1831                  * intermittently experienced depending on peak b/w requirements.
1832                  */
1833                 pipes[pipe_cnt].pipe.src.immediate_flip = true;
1834
1835                 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1836                 pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
1837                 pipes[pipe_cnt].pipe.src.gpuvm = true;
1838                 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
1839                 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
1840                 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1841                 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1842                 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1843
1844                 if (pipes[pipe_cnt].dout.dsc_enable) {
1845                         switch (timing->display_color_depth) {
1846                         case COLOR_DEPTH_888:
1847                                 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1848                                 break;
1849                         case COLOR_DEPTH_101010:
1850                                 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1851                                 break;
1852                         case COLOR_DEPTH_121212:
1853                                 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1854                                 break;
1855                         default:
1856                                 ASSERT(0);
1857                                 break;
1858                         }
1859                 }
1860
1861                 pipe_cnt++;
1862         }
1863         context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE;
1864
1865         dc->config.enable_4to1MPC = false;
1866         if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1867                 if (is_dual_plane(pipe->plane_state->format)
1868                                 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1869                         dc->config.enable_4to1MPC = true;
1870                 } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) {
1871                         /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */
1872                         context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1873                         pipes[0].pipe.src.unbounded_req_mode = true;
1874                 }
1875         } else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count
1876                         && dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {
1877                 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64;
1878         } else if (context->stream_count >= 3 && upscaled) {
1879                 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1880         }
1881
1882         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1883                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1884
1885                 if (!pipe->stream)
1886                         continue;
1887
1888                 if (pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine &&
1889                                 pipe->stream->apply_seamless_boot_optimization) {
1890
1891                         if (pipe->stream->apply_boot_odm_mode == dm_odm_combine_policy_2to1) {
1892                                 context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1;
1893                                 break;
1894                         }
1895                 }
1896         }
1897
1898         return pipe_cnt;
1899 }
1900
1901 static struct dc_cap_funcs cap_funcs = {
1902         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1903 };
1904
1905 static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1906 {
1907         struct clk_limit_table *clk_table = &bw_params->clk_table;
1908         struct _vcs_dpi_voltage_scaling_st *clock_tmp = dcn3_14_soc._clock_tmp;
1909         unsigned int i, closest_clk_lvl;
1910         int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
1911         int j;
1912
1913         // Default clock levels are used for diags, which may lead to overclocking.
1914         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
1915
1916                 dcn3_14_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
1917                 dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count;
1918                 dcn3_14_soc.num_chans = bw_params->num_channels;
1919
1920                 ASSERT(clk_table->num_entries);
1921
1922                 /* Prepass to find max clocks independent of voltage level. */
1923                 for (i = 0; i < clk_table->num_entries; ++i) {
1924                         if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
1925                                 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
1926                         if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
1927                                 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
1928                 }
1929
1930                 for (i = 0; i < clk_table->num_entries; i++) {
1931                         /* loop backwards*/
1932                         for (closest_clk_lvl = 0, j = dcn3_14_soc.num_states - 1; j >= 0; j--) {
1933                                 if ((unsigned int) dcn3_14_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
1934                                         closest_clk_lvl = j;
1935                                         break;
1936                                 }
1937                         }
1938                         if (clk_table->num_entries == 1) {
1939                                 /*smu gives one DPM level, let's take the highest one*/
1940                                 closest_clk_lvl = dcn3_14_soc.num_states - 1;
1941                         }
1942
1943                         clock_tmp[i].state = i;
1944
1945                         /* Clocks dependent on voltage level. */
1946                         clock_tmp[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1947                         if (clk_table->num_entries == 1 &&
1948                                 clock_tmp[i].dcfclk_mhz < dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
1949                                 /*SMU fix not released yet*/
1950                                 clock_tmp[i].dcfclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
1951                         }
1952                         clock_tmp[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1953                         clock_tmp[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
1954
1955                         if (clk_table->entries[i].memclk_mhz && clk_table->entries[i].wck_ratio)
1956                                 clock_tmp[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
1957
1958                         /* Clocks independent of voltage level. */
1959                         clock_tmp[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
1960                                 dcn3_14_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
1961
1962                         clock_tmp[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
1963                                 dcn3_14_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
1964
1965                         clock_tmp[i].dram_bw_per_chan_gbps = dcn3_14_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
1966                         clock_tmp[i].dscclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
1967                         clock_tmp[i].dtbclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
1968                         clock_tmp[i].phyclk_d18_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
1969                         clock_tmp[i].phyclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
1970                 }
1971                 for (i = 0; i < clk_table->num_entries; i++)
1972                         dcn3_14_soc.clock_limits[i] = clock_tmp[i];
1973                 if (clk_table->num_entries)
1974                         dcn3_14_soc.num_states = clk_table->num_entries;
1975         }
1976
1977         if (max_dispclk_mhz) {
1978                 dcn3_14_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
1979                 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2;
1980         }
1981
1982         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1983                 dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN31);
1984         else
1985                 dml_init_instance(&dc->dml, &dcn3_14_soc, &dcn3_14_ip, DML_PROJECT_DCN31_FPGA);
1986 }
1987
1988 static struct resource_funcs dcn314_res_pool_funcs = {
1989         .destroy = dcn314_destroy_resource_pool,
1990         .link_enc_create = dcn31_link_encoder_create,
1991         .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1992         .link_encs_assign = link_enc_cfg_link_encs_assign,
1993         .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1994         .panel_cntl_create = dcn31_panel_cntl_create,
1995         .validate_bandwidth = dcn31_validate_bandwidth,
1996         .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1997         .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1998         .populate_dml_pipes = dcn314_populate_dml_pipes_from_context,
1999         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2000         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2001         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2002         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2003         .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2004         .set_mcif_arb_params = dcn30_set_mcif_arb_params,
2005         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2006         .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
2007         .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
2008         .update_bw_bounding_box = dcn314_update_bw_bounding_box,
2009         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2010 };
2011
2012 static struct clock_source *dcn30_clock_source_create(
2013                 struct dc_context *ctx,
2014                 struct dc_bios *bios,
2015                 enum clock_source_id id,
2016                 const struct dce110_clk_src_regs *regs,
2017                 bool dp_clk_src)
2018 {
2019         struct dce110_clk_src *clk_src =
2020                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
2021
2022         if (!clk_src)
2023                 return NULL;
2024
2025         if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
2026                         regs, &cs_shift, &cs_mask)) {
2027                 clk_src->base.dp_clk_src = dp_clk_src;
2028                 return &clk_src->base;
2029         }
2030
2031         BREAK_TO_DEBUGGER();
2032         return NULL;
2033 }
2034
2035 static bool dcn314_resource_construct(
2036         uint8_t num_virtual_links,
2037         struct dc *dc,
2038         struct dcn314_resource_pool *pool)
2039 {
2040         int i;
2041         struct dc_context *ctx = dc->ctx;
2042         struct irq_service_init_data init_data;
2043
2044         ctx->dc_bios->regs = &bios_regs;
2045
2046         pool->base.res_cap = &res_cap_dcn314;
2047         pool->base.funcs = &dcn314_res_pool_funcs;
2048
2049         /*************************************************
2050          *  Resource + asic cap harcoding                *
2051          *************************************************/
2052         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2053         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2054         pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2055         dc->caps.max_downscale_ratio = 600;
2056         dc->caps.i2c_speed_in_khz = 100;
2057         dc->caps.i2c_speed_in_khz_hdcp = 100;
2058         dc->caps.max_cursor_size = 256;
2059         dc->caps.min_horizontal_blanking_period = 80;
2060         dc->caps.dmdata_alloc_size = 2048;
2061         dc->caps.max_slave_planes = 2;
2062         dc->caps.max_slave_yuv_planes = 2;
2063         dc->caps.max_slave_rgb_planes = 2;
2064         dc->caps.post_blend_color_processing = true;
2065         dc->caps.force_dp_tps4_for_cp2520 = true;
2066         dc->caps.dp_hpo = true;
2067         dc->caps.edp_dsc_support = true;
2068         dc->caps.extended_aux_timeout_support = true;
2069         dc->caps.dmcub_support = true;
2070         dc->caps.is_apu = true;
2071         dc->caps.seamless_odm = true;
2072
2073         dc->caps.zstate_support = true;
2074
2075         /* Color pipeline capabilities */
2076         dc->caps.color.dpp.dcn_arch = 1;
2077         dc->caps.color.dpp.input_lut_shared = 0;
2078         dc->caps.color.dpp.icsc = 1;
2079         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2080         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2081         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2082         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2083         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2084         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2085         dc->caps.color.dpp.post_csc = 1;
2086         dc->caps.color.dpp.gamma_corr = 1;
2087         dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2088
2089         dc->caps.color.dpp.hw_3d_lut = 1;
2090         dc->caps.color.dpp.ogam_ram = 1;
2091         // no OGAM ROM on DCN301
2092         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2093         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2094         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2095         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2096         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2097         dc->caps.color.dpp.ocsc = 0;
2098
2099         dc->caps.color.mpc.gamut_remap = 1;
2100         dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
2101         dc->caps.color.mpc.ogam_ram = 1;
2102         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2103         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2104         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2105         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2106         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2107         dc->caps.color.mpc.ocsc = 1;
2108
2109         /* Use pipe context based otg sync logic */
2110         dc->config.use_pipe_ctx_sync_logic = true;
2111
2112         /* read VBIOS LTTPR caps */
2113         {
2114                 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2115                         enum bp_result bp_query_result;
2116                         uint8_t is_vbios_lttpr_enable = 0;
2117
2118                         bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2119                         dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2120                 }
2121
2122                 /* interop bit is implicit */
2123                 {
2124                         dc->caps.vbios_lttpr_aware = true;
2125                 }
2126         }
2127
2128         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2129                 dc->debug = debug_defaults_drv;
2130         else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS)
2131                 dc->debug = debug_defaults_diags;
2132         else
2133                 dc->debug = debug_defaults_diags;
2134         // Init the vm_helper
2135         if (dc->vm_helper)
2136                 vm_helper_init(dc->vm_helper, 16);
2137
2138         /*************************************************
2139          *  Create resources                             *
2140          *************************************************/
2141
2142         /* Clock Sources for Pixel Clock*/
2143         pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
2144                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2145                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
2146                                 &clk_src_regs[0], false);
2147         pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
2148                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2149                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
2150                                 &clk_src_regs[1], false);
2151         pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
2152                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2153                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
2154                                 &clk_src_regs[2], false);
2155         pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
2156                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2157                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
2158                                 &clk_src_regs[3], false);
2159         pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
2160                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2161                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
2162                                 &clk_src_regs[4], false);
2163
2164         pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2165
2166         /* todo: not reuse phy_pll registers */
2167         pool->base.dp_clock_source =
2168                         dcn31_clock_source_create(ctx, ctx->dc_bios,
2169                                 CLOCK_SOURCE_ID_DP_DTO,
2170                                 &clk_src_regs[0], true);
2171
2172         for (i = 0; i < pool->base.clk_src_count; i++) {
2173                 if (pool->base.clock_sources[i] == NULL) {
2174                         dm_error("DC: failed to create clock sources!\n");
2175                         BREAK_TO_DEBUGGER();
2176                         goto create_fail;
2177                 }
2178         }
2179
2180         pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2181         if (pool->base.dccg == NULL) {
2182                 dm_error("DC: failed to create dccg!\n");
2183                 BREAK_TO_DEBUGGER();
2184                 goto create_fail;
2185         }
2186
2187         init_data.ctx = dc->ctx;
2188         pool->base.irqs = dal_irq_service_dcn314_create(&init_data);
2189         if (!pool->base.irqs)
2190                 goto create_fail;
2191
2192         /* HUBBUB */
2193         pool->base.hubbub = dcn31_hubbub_create(ctx);
2194         if (pool->base.hubbub == NULL) {
2195                 BREAK_TO_DEBUGGER();
2196                 dm_error("DC: failed to create hubbub!\n");
2197                 goto create_fail;
2198         }
2199
2200         /* HUBPs, DPPs, OPPs and TGs */
2201         for (i = 0; i < pool->base.pipe_count; i++) {
2202                 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2203                 if (pool->base.hubps[i] == NULL) {
2204                         BREAK_TO_DEBUGGER();
2205                         dm_error(
2206                                 "DC: failed to create hubps!\n");
2207                         goto create_fail;
2208                 }
2209
2210                 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2211                 if (pool->base.dpps[i] == NULL) {
2212                         BREAK_TO_DEBUGGER();
2213                         dm_error(
2214                                 "DC: failed to create dpps!\n");
2215                         goto create_fail;
2216                 }
2217         }
2218
2219         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2220                 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2221                 if (pool->base.opps[i] == NULL) {
2222                         BREAK_TO_DEBUGGER();
2223                         dm_error(
2224                                 "DC: failed to create output pixel processor!\n");
2225                         goto create_fail;
2226                 }
2227         }
2228
2229         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2230                 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2231                                 ctx, i);
2232                 if (pool->base.timing_generators[i] == NULL) {
2233                         BREAK_TO_DEBUGGER();
2234                         dm_error("DC: failed to create tg!\n");
2235                         goto create_fail;
2236                 }
2237         }
2238         pool->base.timing_generator_count = i;
2239
2240         /* PSR */
2241         pool->base.psr = dmub_psr_create(ctx);
2242         if (pool->base.psr == NULL) {
2243                 dm_error("DC: failed to create psr obj!\n");
2244                 BREAK_TO_DEBUGGER();
2245                 goto create_fail;
2246         }
2247
2248         /* ABM */
2249         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2250                 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2251                                 &abm_regs[i],
2252                                 &abm_shift,
2253                                 &abm_mask);
2254                 if (pool->base.multiple_abms[i] == NULL) {
2255                         dm_error("DC: failed to create abm for pipe %d!\n", i);
2256                         BREAK_TO_DEBUGGER();
2257                         goto create_fail;
2258                 }
2259         }
2260
2261         /* MPC and DSC */
2262         pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2263         if (pool->base.mpc == NULL) {
2264                 BREAK_TO_DEBUGGER();
2265                 dm_error("DC: failed to create mpc!\n");
2266                 goto create_fail;
2267         }
2268
2269         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2270                 pool->base.dscs[i] = dcn314_dsc_create(ctx, i);
2271                 if (pool->base.dscs[i] == NULL) {
2272                         BREAK_TO_DEBUGGER();
2273                         dm_error("DC: failed to create display stream compressor %d!\n", i);
2274                         goto create_fail;
2275                 }
2276         }
2277
2278         /* DWB and MMHUBBUB */
2279         if (!dcn31_dwbc_create(ctx, &pool->base)) {
2280                 BREAK_TO_DEBUGGER();
2281                 dm_error("DC: failed to create dwbc!\n");
2282                 goto create_fail;
2283         }
2284
2285         if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2286                 BREAK_TO_DEBUGGER();
2287                 dm_error("DC: failed to create mcif_wb!\n");
2288                 goto create_fail;
2289         }
2290
2291         /* AUX and I2C */
2292         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2293                 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2294                 if (pool->base.engines[i] == NULL) {
2295                         BREAK_TO_DEBUGGER();
2296                         dm_error(
2297                                 "DC:failed to create aux engine!!\n");
2298                         goto create_fail;
2299                 }
2300                 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2301                 if (pool->base.hw_i2cs[i] == NULL) {
2302                         BREAK_TO_DEBUGGER();
2303                         dm_error(
2304                                 "DC:failed to create hw i2c!!\n");
2305                         goto create_fail;
2306                 }
2307                 pool->base.sw_i2cs[i] = NULL;
2308         }
2309
2310         /* DCN314 has 4 DPIA */
2311         pool->base.usb4_dpia_count = 4;
2312
2313         /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2314         if (!resource_construct(num_virtual_links, dc, &pool->base,
2315                                 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2316                                  &res_create_funcs : &res_create_maximus_funcs)))
2317                 goto create_fail;
2318
2319         /* HW Sequencer and Plane caps */
2320         dcn314_hw_sequencer_construct(dc);
2321
2322         dc->caps.max_planes =  pool->base.pipe_count;
2323
2324         for (i = 0; i < dc->caps.max_planes; ++i)
2325                 dc->caps.planes[i] = plane_cap;
2326
2327         dc->cap_funcs = cap_funcs;
2328
2329         dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp;
2330
2331         return true;
2332
2333 create_fail:
2334
2335         dcn314_resource_destruct(pool);
2336
2337         return false;
2338 }
2339
2340 struct resource_pool *dcn314_create_resource_pool(
2341                 const struct dc_init_data *init_data,
2342                 struct dc *dc)
2343 {
2344         struct dcn314_resource_pool *pool =
2345                 kzalloc(sizeof(struct dcn314_resource_pool), GFP_KERNEL);
2346
2347         if (!pool)
2348                 return NULL;
2349
2350         if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool))
2351                 return &pool->base;
2352
2353         BREAK_TO_DEBUGGER();
2354         kfree(pool);
2355         return NULL;
2356 }