drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "reg_helper.h"
  28
  29 #include "core_types.h"
  30 #include "link_encoder.h"
  31 #include "dcn31_dio_link_encoder.h"
  32 #include "stream_encoder.h"
  33 #include "i2caux_interface.h"
  34 #include "dc_bios_types.h"
  35
  36 #include "gpio_service_interface.h"
  37
  38 #include "link_enc_cfg.h"
  39 #include "dc_dmub_srv.h"
  40 #include "dal_asic_id.h"
  41
  42 #define CTX \
  43         enc10->base.ctx
  44 #define DC_LOGGER \
  45         enc10->base.ctx->logger
  46
  47 #define REG(reg)\
  48         (enc10->link_regs->reg)
  49
  50 #undef FN
  51 #define FN(reg_name, field_name) \
  52         enc10->link_shift->field_name, enc10->link_mask->field_name
  53
  54 #define IND_REG(index) \
  55         (enc10->link_regs->index)
  56
  57 #define AUX_REG(reg)\
  58         (enc10->aux_regs->reg)
  59
  60 #define AUX_REG_READ(reg_name) \
  61                 dm_read_reg(CTX, AUX_REG(reg_name))
  62
  63 #define AUX_REG_WRITE(reg_name, val) \
  64                         dm_write_reg(CTX, AUX_REG(reg_name), val)
  65
  66 void dcn31_link_encoder_set_dio_phy_mux(
  67         struct link_encoder *enc,
  68         enum encoder_type_select sel,
  69         uint32_t hpo_inst)
  70 {
  71         struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
  72
  73         switch (enc->transmitter) {
  74         case TRANSMITTER_UNIPHY_A:
  75                 if (sel == ENCODER_TYPE_HDMI_FRL)
  76                         REG_UPDATE(DIO_LINKA_CNTL,
  77                                         HPO_HDMI_ENC_SEL, hpo_inst);
  78                 else if (sel == ENCODER_TYPE_DP_128B132B)
  79                         REG_UPDATE(DIO_LINKA_CNTL,
  80                                         HPO_DP_ENC_SEL, hpo_inst);
  81                 REG_UPDATE(DIO_LINKA_CNTL,
  82                                 ENC_TYPE_SEL, sel);
  83                 break;
  84         case TRANSMITTER_UNIPHY_B:
  85                 if (sel == ENCODER_TYPE_HDMI_FRL)
  86                         REG_UPDATE(DIO_LINKB_CNTL,
  87                                         HPO_HDMI_ENC_SEL, hpo_inst);
  88                 else if (sel == ENCODER_TYPE_DP_128B132B)
  89                         REG_UPDATE(DIO_LINKB_CNTL,
  90                                         HPO_DP_ENC_SEL, hpo_inst);
  91                 REG_UPDATE(DIO_LINKB_CNTL,
  92                                 ENC_TYPE_SEL, sel);
  93                 break;
  94         case TRANSMITTER_UNIPHY_C:
  95                 if (sel == ENCODER_TYPE_HDMI_FRL)
  96                         REG_UPDATE(DIO_LINKC_CNTL,
  97                                         HPO_HDMI_ENC_SEL, hpo_inst);
  98                 else if (sel == ENCODER_TYPE_DP_128B132B)
  99                         REG_UPDATE(DIO_LINKC_CNTL,
 100                                         HPO_DP_ENC_SEL, hpo_inst);
 101                 REG_UPDATE(DIO_LINKC_CNTL,
 102                                 ENC_TYPE_SEL, sel);
 103                 break;
 104         case TRANSMITTER_UNIPHY_D:
 105                 if (sel == ENCODER_TYPE_HDMI_FRL)
 106                         REG_UPDATE(DIO_LINKD_CNTL,
 107                                         HPO_HDMI_ENC_SEL, hpo_inst);
 108                 else if (sel == ENCODER_TYPE_DP_128B132B)
 109                         REG_UPDATE(DIO_LINKD_CNTL,
 110                                         HPO_DP_ENC_SEL, hpo_inst);
 111                 REG_UPDATE(DIO_LINKD_CNTL,
 112                                 ENC_TYPE_SEL, sel);
 113                 break;
 114         case TRANSMITTER_UNIPHY_E:
 115                 if (sel == ENCODER_TYPE_HDMI_FRL)
 116                         REG_UPDATE(DIO_LINKE_CNTL,
 117                                         HPO_HDMI_ENC_SEL, hpo_inst);
 118                 else if (sel == ENCODER_TYPE_DP_128B132B)
 119                         REG_UPDATE(DIO_LINKE_CNTL,
 120                                         HPO_DP_ENC_SEL, hpo_inst);
 121                 REG_UPDATE(DIO_LINKE_CNTL,
 122                                 ENC_TYPE_SEL, sel);
 123                 break;
 124         case TRANSMITTER_UNIPHY_F:
 125                 if (sel == ENCODER_TYPE_HDMI_FRL)
 126                         REG_UPDATE(DIO_LINKF_CNTL,
 127                                         HPO_HDMI_ENC_SEL, hpo_inst);
 128                 else if (sel == ENCODER_TYPE_DP_128B132B)
 129                         REG_UPDATE(DIO_LINKF_CNTL,
 130                                         HPO_DP_ENC_SEL, hpo_inst);
 131                 REG_UPDATE(DIO_LINKF_CNTL,
 132                                 ENC_TYPE_SEL, sel);
 133                 break;
 134         default:
 135                 /* Do nothing */
 136                 break;
 137         }
 138 }
 139
 140 void enc31_hw_init(struct link_encoder *enc)
 141 {
 142         struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 143
 144 /*
 145         00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
 146         01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
 147         02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
 148         03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
 149         04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
 150         05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
 151         06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
 152         07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
 153 */
 154
 155 /*
 156         AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
 157         AUX_RX_START_WINDOW = 1 [6:4]
 158         AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
 159         AUX_RX_HALF_SYM_DETECT_LEN  = 1 [13:12] default is 1
 160         AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
 161         AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0  default is 0
 162         AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1  default is 1
 163         AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1  default is 1
 164         AUX_RX_PHASE_DETECT_LEN,  [21,20] = 0x3 default is 3
 165         AUX_RX_DETECTION_THRESHOLD [30:28] = 1
 166 */
 167         AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
 168
 169         AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
 170
 171         //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
 172         // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
 173         // 27MHz -> 0xd
 174         // 100MHz -> 0x32
 175         // 48MHz -> 0x18
 176
 177 #ifdef CLEANUP_FIXME
 178         /*from display_init*/
 179         REG_WRITE(RDPCSTX_DEBUG_CONFIG, 0);
 180 #endif
 181
 182         // Set TMDS_CTL0 to 1.  This is a legacy setting.
 183         REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
 184
 185         /*HW default is 5*/
 186         REG_UPDATE(RDPCSTX_CNTL,
 187                         RDPCS_TX_FIFO_RD_START_DELAY, 4);
 188
 189         dcn10_aux_initialize(enc10);
 190 }
 191
 192 static const struct link_encoder_funcs dcn31_link_enc_funcs = {
 193         .read_state = link_enc2_read_state,
 194         .validate_output_with_stream =
 195                         dcn30_link_encoder_validate_output_with_stream,
 196         .hw_init = enc31_hw_init,
 197         .setup = dcn10_link_encoder_setup,
 198         .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
 199         .enable_dp_output = dcn31_link_encoder_enable_dp_output,
 200         .enable_dp_mst_output = dcn31_link_encoder_enable_dp_mst_output,
 201         .disable_output = dcn31_link_encoder_disable_output,
 202         .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
 203         .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
 204         .update_mst_stream_allocation_table =
 205                 dcn10_link_encoder_update_mst_stream_allocation_table,
 206         .psr_program_dp_dphy_fast_training =
 207                         dcn10_psr_program_dp_dphy_fast_training,
 208         .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
 209         .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
 210         .enable_hpd = dcn10_link_encoder_enable_hpd,
 211         .disable_hpd = dcn10_link_encoder_disable_hpd,
 212         .is_dig_enabled = dcn10_is_dig_enabled,
 213         .destroy = dcn10_link_encoder_destroy,
 214         .fec_set_enable = enc2_fec_set_enable,
 215         .fec_set_ready = enc2_fec_set_ready,
 216         .fec_is_active = enc2_fec_is_active,
 217         .get_dig_frontend = dcn10_get_dig_frontend,
 218         .get_dig_mode = dcn10_get_dig_mode,
 219         .is_in_alt_mode = dcn31_link_encoder_is_in_alt_mode,
 220         .get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
 221         .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
 222 };
 223
 224 void dcn31_link_encoder_construct(
 225         struct dcn20_link_encoder *enc20,
 226         const struct encoder_init_data *init_data,
 227         const struct encoder_feature_support *enc_features,
 228         const struct dcn10_link_enc_registers *link_regs,
 229         const struct dcn10_link_enc_aux_registers *aux_regs,
 230         const struct dcn10_link_enc_hpd_registers *hpd_regs,
 231         const struct dcn10_link_enc_shift *link_shift,
 232         const struct dcn10_link_enc_mask *link_mask)
 233 {
 234         struct bp_encoder_cap_info bp_cap_info = {0};
 235         const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
 236         enum bp_result result = BP_RESULT_OK;
 237         struct dcn10_link_encoder *enc10 = &enc20->enc10;
 238
 239         enc10->base.funcs = &dcn31_link_enc_funcs;
 240         enc10->base.ctx = init_data->ctx;
 241         enc10->base.id = init_data->encoder;
 242
 243         enc10->base.hpd_source = init_data->hpd_source;
 244         enc10->base.connector = init_data->connector;
 245
 246         enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
 247
 248         enc10->base.features = *enc_features;
 249
 250         enc10->base.transmitter = init_data->transmitter;
 251
 252         /* set the flag to indicate whether driver poll the I2C data pin
 253          * while doing the DP sink detect
 254          */
 255
 256 /*      if (dal_adapter_service_is_feature_supported(as,
 257                 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
 258                 enc10->base.features.flags.bits.
 259                         DP_SINK_DETECT_POLL_DATA_PIN = true;*/
 260
 261         enc10->base.output_signals =
 262                 SIGNAL_TYPE_DVI_SINGLE_LINK |
 263                 SIGNAL_TYPE_DVI_DUAL_LINK |
 264                 SIGNAL_TYPE_LVDS |
 265                 SIGNAL_TYPE_DISPLAY_PORT |
 266                 SIGNAL_TYPE_DISPLAY_PORT_MST |
 267                 SIGNAL_TYPE_EDP |
 268                 SIGNAL_TYPE_HDMI_TYPE_A;
 269
 270         /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
 271          * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
 272          * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
 273          * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
 274          * Prefer DIG assignment is decided by board design.
 275          * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
 276          * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
 277          * By this, adding DIGG should not hurt DCE 8.0.
 278          * This will let DCE 8.1 share DCE 8.0 as much as possible
 279          */
 280
 281         enc10->link_regs = link_regs;
 282         enc10->aux_regs = aux_regs;
 283         enc10->hpd_regs = hpd_regs;
 284         enc10->link_shift = link_shift;
 285         enc10->link_mask = link_mask;
 286
 287         switch (enc10->base.transmitter) {
 288         case TRANSMITTER_UNIPHY_A:
 289                 enc10->base.preferred_engine = ENGINE_ID_DIGA;
 290         break;
 291         case TRANSMITTER_UNIPHY_B:
 292                 enc10->base.preferred_engine = ENGINE_ID_DIGB;
 293         break;
 294         case TRANSMITTER_UNIPHY_C:
 295                 enc10->base.preferred_engine = ENGINE_ID_DIGC;
 296         break;
 297         case TRANSMITTER_UNIPHY_D:
 298                 enc10->base.preferred_engine = ENGINE_ID_DIGD;
 299         break;
 300         case TRANSMITTER_UNIPHY_E:
 301                 enc10->base.preferred_engine = ENGINE_ID_DIGE;
 302         break;
 303         case TRANSMITTER_UNIPHY_F:
 304                 enc10->base.preferred_engine = ENGINE_ID_DIGF;
 305         break;
 306         default:
 307                 ASSERT_CRITICAL(false);
 308                 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
 309         }
 310
 311         /* default to one to mirror Windows behavior */
 312         enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
 313
 314         result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
 315                                                 enc10->base.id, &bp_cap_info);
 316
 317         /* Override features with DCE-specific values */
 318         if (result == BP_RESULT_OK) {
 319                 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
 320                                 bp_cap_info.DP_HBR2_EN;
 321                 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
 322                                 bp_cap_info.DP_HBR3_EN;
 323                 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
 324                 enc10->base.features.flags.bits.IS_DP2_CAPABLE = bp_cap_info.IS_DP2_CAPABLE;
 325                 enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;
 326                 enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;
 327                 enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;
 328                 enc10->base.features.flags.bits.DP_IS_USB_C =
 329                                 bp_cap_info.DP_IS_USB_C;
 330         } else {
 331                 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
 332                                 __func__,
 333                                 result);
 334         }
 335         if (enc10->base.ctx->dc->debug.hdmi20_disable) {
 336                 enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
 337         }
 338 }
 339
 340 void dcn31_link_encoder_construct_minimal(
 341         struct dcn20_link_encoder *enc20,
 342         struct dc_context *ctx,
 343         const struct encoder_feature_support *enc_features,
 344         const struct dcn10_link_enc_registers *link_regs,
 345         enum engine_id eng_id)
 346 {
 347         struct dcn10_link_encoder *enc10 = &enc20->enc10;
 348
 349         enc10->base.funcs = &dcn31_link_enc_funcs;
 350         enc10->base.ctx = ctx;
 351         enc10->base.id.type = OBJECT_TYPE_ENCODER;
 352         enc10->base.hpd_source = HPD_SOURCEID_UNKNOWN;
 353         enc10->base.connector.type = OBJECT_TYPE_CONNECTOR;
 354         enc10->base.preferred_engine = eng_id;
 355         enc10->base.features = *enc_features;
 356         enc10->base.transmitter = TRANSMITTER_UNKNOWN;
 357         enc10->link_regs = link_regs;
 358
 359         enc10->base.output_signals =
 360                 SIGNAL_TYPE_DISPLAY_PORT |
 361                 SIGNAL_TYPE_DISPLAY_PORT_MST |
 362                 SIGNAL_TYPE_EDP;
 363 }
 364
 365 void dcn31_link_encoder_enable_dp_output(
 366         struct link_encoder *enc,
 367         const struct dc_link_settings *link_settings,
 368         enum clock_source_id clock_source)
 369 {
 370         /* Enable transmitter and encoder. */
 371         if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {
 372
 373                 dcn20_link_encoder_enable_dp_output(enc, link_settings, clock_source);
 374
 375         } else {
 376
 377                 /** @todo Handle transmitter with programmable mapping to link encoder. */
 378         }
 379 }
 380
 381 void dcn31_link_encoder_enable_dp_mst_output(
 382         struct link_encoder *enc,
 383         const struct dc_link_settings *link_settings,
 384         enum clock_source_id clock_source)
 385 {
 386         /* Enable transmitter and encoder. */
 387         if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {
 388
 389                 dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source);
 390
 391         } else {
 392
 393                 /** @todo Handle transmitter with programmable mapping to link encoder. */
 394         }
 395 }
 396
 397 void dcn31_link_encoder_disable_output(
 398         struct link_encoder *enc,
 399         enum signal_type signal)
 400 {
 401         /* Disable transmitter and encoder. */
 402         if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) {
 403
 404                 dcn10_link_encoder_disable_output(enc, signal);
 405
 406         } else {
 407
 408                 /** @todo Handle transmitter with programmable mapping to link encoder. */
 409         }
 410 }
 411
 412 bool dcn31_link_encoder_is_in_alt_mode(struct link_encoder *enc)
 413 {
 414         struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 415         uint32_t dp_alt_mode_disable;
 416         bool is_usb_c_alt_mode = false;
 417
 418         if (enc->features.flags.bits.DP_IS_USB_C) {
 419                 if (enc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_B0) {
 420                         // [Note] no need to check hw_internal_rev once phy mux selection is ready
 421                         REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
 422                 } else {
 423                 /*
 424                  * B0 phys use a new set of registers to check whether alt mode is disabled.
 425                  * if value == 1 alt mode is disabled, otherwise it is enabled.
 426                  */
 427                         if ((enc10->base.transmitter == TRANSMITTER_UNIPHY_A)
 428                                         || (enc10->base.transmitter == TRANSMITTER_UNIPHY_B)
 429                                         || (enc10->base.transmitter == TRANSMITTER_UNIPHY_E)) {
 430                                 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
 431                         } else {
 432                         // [Note] need to change TRANSMITTER_UNIPHY_C/D to F/G once phy mux selection is ready
 433                                 REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
 434                         }
 435                 }
 436
 437                 is_usb_c_alt_mode = (dp_alt_mode_disable == 0);
 438         }
 439
 440         return is_usb_c_alt_mode;
 441 }