drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c

   1 /*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "dc.h"
  28
  29 #include "dcn201_init.h"
  30 #include "dml/dcn20/dcn20_fpu.h"
  31 #include "resource.h"
  32 #include "include/irq_service_interface.h"
  33 #include "dcn201_resource.h"
  34
  35 #include "dcn20/dcn20_resource.h"
  36
  37 #include "dcn10/dcn10_hubp.h"
  38 #include "dcn10/dcn10_ipp.h"
  39 #include "dcn201_mpc.h"
  40 #include "dcn201_hubp.h"
  41 #include "irq/dcn201/irq_service_dcn201.h"
  42 #include "dcn201/dcn201_dpp.h"
  43 #include "dcn201/dcn201_hubbub.h"
  44 #include "dcn201_dccg.h"
  45 #include "dcn201_optc.h"
  46 #include "dcn201_hwseq.h"
  47 #include "dce110/dce110_hw_sequencer.h"
  48 #include "dcn201_opp.h"
  49 #include "dcn201/dcn201_link_encoder.h"
  50 #include "dcn20/dcn20_stream_encoder.h"
  51 #include "dce/dce_clock_source.h"
  52 #include "dce/dce_audio.h"
  53 #include "dce/dce_hwseq.h"
  54 #include "virtual/virtual_stream_encoder.h"
  55 #include "dce110/dce110_resource.h"
  56 #include "dce/dce_aux.h"
  57 #include "dce/dce_i2c.h"
  58 #include "dcn201_hubbub.h"
  59 #include "dcn10/dcn10_resource.h"
  60
  61 #include "cyan_skillfish_ip_offset.h"
  62
  63 #include "dcn/dcn_2_0_3_offset.h"
  64 #include "dcn/dcn_2_0_3_sh_mask.h"
  65 #include "dpcs/dpcs_2_0_3_offset.h"
  66 #include "dpcs/dpcs_2_0_3_sh_mask.h"
  67
  68 #include "mmhub/mmhub_2_0_0_offset.h"
  69 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  70 #include "nbio/nbio_7_4_offset.h"
  71
  72 #include "reg_helper.h"
  73
  74 #define MIN_DISP_CLK_KHZ 100000
  75 #define MIN_DPP_CLK_KHZ 100000
  76
  77 static struct _vcs_dpi_ip_params_st dcn201_ip = {
  78         .gpuvm_enable = 0,
  79         .hostvm_enable = 0,
  80         .gpuvm_max_page_table_levels = 4,
  81         .hostvm_max_page_table_levels = 4,
  82         .hostvm_cached_page_table_levels = 0,
  83         .pte_group_size_bytes = 2048,
  84         .rob_buffer_size_kbytes = 168,
  85         .det_buffer_size_kbytes = 164,
  86         .dpte_buffer_size_in_pte_reqs_luma = 84,
  87         .pde_proc_buffer_size_64k_reqs = 48,
  88         .dpp_output_buffer_pixels = 2560,
  89         .opp_output_buffer_lines = 1,
  90         .pixel_chunk_size_kbytes = 8,
  91         .pte_chunk_size_kbytes = 2,
  92         .meta_chunk_size_kbytes = 2,
  93         .writeback_chunk_size_kbytes = 2,
  94         .line_buffer_size_bits = 789504,
  95         .is_line_buffer_bpp_fixed = 0,
  96         .line_buffer_fixed_bpp = 0,
  97         .dcc_supported = true,
  98         .max_line_buffer_lines = 12,
  99         .writeback_luma_buffer_size_kbytes = 12,
 100         .writeback_chroma_buffer_size_kbytes = 8,
 101         .writeback_chroma_line_buffer_width_pixels = 4,
 102         .writeback_max_hscl_ratio = 1,
 103         .writeback_max_vscl_ratio = 1,
 104         .writeback_min_hscl_ratio = 1,
 105         .writeback_min_vscl_ratio = 1,
 106         .writeback_max_hscl_taps = 12,
 107         .writeback_max_vscl_taps = 12,
 108         .writeback_line_buffer_luma_buffer_size = 0,
 109         .writeback_line_buffer_chroma_buffer_size = 9600,
 110         .cursor_buffer_size = 8,
 111         .cursor_chunk_size = 2,
 112         .max_num_otg = 2,
 113         .max_num_dpp = 4,
 114         .max_num_wb = 0,
 115         .max_dchub_pscl_bw_pix_per_clk = 4,
 116         .max_pscl_lb_bw_pix_per_clk = 2,
 117         .max_lb_vscl_bw_pix_per_clk = 4,
 118         .max_vscl_hscl_bw_pix_per_clk = 4,
 119         .max_hscl_ratio = 8,
 120         .max_vscl_ratio = 8,
 121         .hscl_mults = 4,
 122         .vscl_mults = 4,
 123         .max_hscl_taps = 8,
 124         .max_vscl_taps = 8,
 125         .dispclk_ramp_margin_percent = 1,
 126         .underscan_factor = 1.10,
 127         .min_vblank_lines = 30,
 128         .dppclk_delay_subtotal = 77,
 129         .dppclk_delay_scl_lb_only = 16,
 130         .dppclk_delay_scl = 50,
 131         .dppclk_delay_cnvc_formatter = 8,
 132         .dppclk_delay_cnvc_cursor = 6,
 133         .dispclk_delay_subtotal = 87,
 134         .dcfclk_cstate_latency = 10,
 135         .max_inter_dcn_tile_repeaters = 8,
 136         .number_of_cursors = 1,
 137 };
 138
 139 static struct _vcs_dpi_soc_bounding_box_st dcn201_soc = {
 140         .clock_limits = {
 141                         {
 142                                 .state = 0,
 143                                 .dscclk_mhz = 400.0,
 144                                 .dcfclk_mhz = 1000.0,
 145                                 .fabricclk_mhz = 200.0,
 146                                 .dispclk_mhz = 300.0,
 147                                 .dppclk_mhz = 300.0,
 148                                 .phyclk_mhz = 810.0,
 149                                 .socclk_mhz = 1254.0,
 150                                 .dram_speed_mts = 2000.0,
 151                         },
 152                         {
 153                                 .state = 1,
 154                                 .dscclk_mhz = 400.0,
 155                                 .dcfclk_mhz = 1000.0,
 156                                 .fabricclk_mhz = 250.0,
 157                                 .dispclk_mhz = 1200.0,
 158                                 .dppclk_mhz = 1200.0,
 159                                 .phyclk_mhz = 810.0,
 160                                 .socclk_mhz = 1254.0,
 161                                 .dram_speed_mts = 3600.0,
 162                         },
 163                         {
 164                                 .state = 2,
 165                                 .dscclk_mhz = 400.0,
 166                                 .dcfclk_mhz = 1000.0,
 167                                 .fabricclk_mhz = 750.0,
 168                                 .dispclk_mhz = 1200.0,
 169                                 .dppclk_mhz = 1200.0,
 170                                 .phyclk_mhz = 810.0,
 171                                 .socclk_mhz = 1254.0,
 172                                 .dram_speed_mts = 6800.0,
 173                         },
 174                         {
 175                                 .state = 3,
 176                                 .dscclk_mhz = 400.0,
 177                                 .dcfclk_mhz = 1000.0,
 178                                 .fabricclk_mhz = 250.0,
 179                                 .dispclk_mhz = 1200.0,
 180                                 .dppclk_mhz = 1200.0,
 181                                 .phyclk_mhz = 810.0,
 182                                 .socclk_mhz = 1254.0,
 183                                 .dram_speed_mts = 14000.0,
 184                         },
 185                         {
 186                                 .state = 4,
 187                                 .dscclk_mhz = 400.0,
 188                                 .dcfclk_mhz = 1000.0,
 189                                 .fabricclk_mhz = 750.0,
 190                                 .dispclk_mhz = 1200.0,
 191                                 .dppclk_mhz = 1200.0,
 192                                 .phyclk_mhz = 810.0,
 193                                 .socclk_mhz = 1254.0,
 194                                 .dram_speed_mts = 14000.0,
 195                         }
 196                 },
 197         .num_states = 4,
 198         .sr_exit_time_us = 9.0,
 199         .sr_enter_plus_exit_time_us = 11.0,
 200         .urgent_latency_us = 4.0,
 201         .urgent_latency_pixel_data_only_us = 4.0,
 202         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 203         .urgent_latency_vm_data_only_us = 4.0,
 204         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 256,
 205         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 256,
 206         .urgent_out_of_order_return_per_channel_vm_only_bytes = 256,
 207         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
 208         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 80.0,
 209         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 80.0,
 210         .max_avg_sdp_bw_use_normal_percent = 80.0,
 211         .max_avg_dram_bw_use_normal_percent = 69.0,
 212         .writeback_latency_us = 12.0,
 213         .ideal_dram_bw_after_urgent_percent = 80.0,
 214         .max_request_size_bytes = 256,
 215         .dram_channel_width_bytes = 2,
 216         .fabric_datapath_to_dcn_data_return_bytes = 64,
 217         .dcn_downspread_percent = 0.3,
 218         .downspread_percent = 0.3,
 219         .dram_page_open_time_ns = 50.0,
 220         .dram_rw_turnaround_time_ns = 17.5,
 221         .dram_return_buffer_per_channel_bytes = 8192,
 222         .round_trip_ping_latency_dcfclk_cycles = 128,
 223         .urgent_out_of_order_return_per_channel_bytes = 256,
 224         .channel_interleave_bytes = 256,
 225         .num_banks = 8,
 226         .num_chans = 16,
 227         .vmm_page_size_bytes = 4096,
 228         .dram_clock_change_latency_us = 250.0,
 229         .writeback_dram_clock_change_latency_us = 23.0,
 230         .return_bus_width_bytes = 64,
 231         .dispclk_dppclk_vco_speed_mhz = 3000,
 232         .use_urgent_burst_bw = 0,
 233 };
 234
 235 enum dcn20_clk_src_array_id {
 236         DCN20_CLK_SRC_PLL0,
 237         DCN20_CLK_SRC_PLL1,
 238         DCN20_CLK_SRC_TOTAL_DCN201
 239 };
 240
 241 /* begin *********************
 242  * macros to expend register list macro defined in HW object header file */
 243
 244 /* DCN */
 245
 246 #undef BASE_INNER
 247 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
 248
 249 #define BASE(seg) BASE_INNER(seg)
 250
 251 #define SR(reg_name)\
 252                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 253                                         mm ## reg_name
 254
 255 #define SRI(reg_name, block, id)\
 256         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 257                                         mm ## block ## id ## _ ## reg_name
 258
 259 #define SRIR(var_name, reg_name, block, id)\
 260         .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 261                                         mm ## block ## id ## _ ## reg_name
 262
 263 #define SRII(reg_name, block, id)\
 264         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 265                                         mm ## block ## id ## _ ## reg_name
 266
 267 #define SRI_IX(reg_name, block, id)\
 268         .reg_name = ix ## block ## id ## _ ## reg_name
 269
 270 #define DCCG_SRII(reg_name, block, id)\
 271         .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 272                                         mm ## block ## id ## _ ## reg_name
 273
 274 #define VUPDATE_SRII(reg_name, block, id)\
 275         .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 276                                         mm ## reg_name ## _ ## block ## id
 277
 278 /* NBIO */
 279 #define NBIO_BASE_INNER(seg) \
 280         NBIO_BASE__INST0_SEG ## seg
 281
 282 #define NBIO_BASE(seg) \
 283         NBIO_BASE_INNER(seg)
 284
 285 #define NBIO_SR(reg_name)\
 286                 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
 287                                         mm ## reg_name
 288
 289 /* MMHUB */
 290 #define MMHUB_BASE_INNER(seg) \
 291         MMHUB_BASE__INST0_SEG ## seg
 292
 293 #define MMHUB_BASE(seg) \
 294         MMHUB_BASE_INNER(seg)
 295
 296 #define MMHUB_SR(reg_name)\
 297                 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
 298                                         mmMM ## reg_name
 299
 300 static const struct bios_registers bios_regs = {
 301                 NBIO_SR(BIOS_SCRATCH_3),
 302                 NBIO_SR(BIOS_SCRATCH_6)
 303 };
 304
 305 #define clk_src_regs(index, pllid)\
 306 [index] = {\
 307         CS_COMMON_REG_LIST_DCN201(index, pllid),\
 308 }
 309
 310 static const struct dce110_clk_src_regs clk_src_regs[] = {
 311         clk_src_regs(0, A),
 312         clk_src_regs(1, B)
 313 };
 314
 315 static const struct dce110_clk_src_shift cs_shift = {
 316                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 317 };
 318
 319 static const struct dce110_clk_src_mask cs_mask = {
 320                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 321 };
 322
 323 #define audio_regs(id)\
 324 [id] = {\
 325                 AUD_COMMON_REG_LIST(id)\
 326 }
 327
 328 static const struct dce_audio_registers audio_regs[] = {
 329         audio_regs(0),
 330         audio_regs(1),
 331 };
 332
 333 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 334                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 335                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 336                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 337
 338 static const struct dce_audio_shift audio_shift = {
 339                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 340 };
 341
 342 static const struct dce_audio_mask audio_mask = {
 343                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 344 };
 345
 346 #define stream_enc_regs(id)\
 347 [id] = {\
 348         SE_DCN2_REG_LIST(id)\
 349 }
 350
 351 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 352         stream_enc_regs(0),
 353         stream_enc_regs(1)
 354 };
 355
 356 static const struct dcn10_stream_encoder_shift se_shift = {
 357                 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
 358 };
 359
 360 static const struct dcn10_stream_encoder_mask se_mask = {
 361                 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
 362 };
 363
 364 static const struct dce110_aux_registers_shift aux_shift = {
 365         DCN_AUX_MASK_SH_LIST(__SHIFT)
 366 };
 367
 368 static const struct dce110_aux_registers_mask aux_mask = {
 369         DCN_AUX_MASK_SH_LIST(_MASK)
 370 };
 371
 372 #define aux_regs(id)\
 373 [id] = {\
 374         DCN2_AUX_REG_LIST(id)\
 375 }
 376
 377 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 378                 aux_regs(0),
 379                 aux_regs(1),
 380 };
 381
 382 #define hpd_regs(id)\
 383 [id] = {\
 384         HPD_REG_LIST(id)\
 385 }
 386
 387 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 388                 hpd_regs(0),
 389                 hpd_regs(1),
 390 };
 391
 392 #define link_regs(id, phyid)\
 393 [id] = {\
 394         LE_DCN_COMMON_REG_LIST(id), \
 395         UNIPHY_DCN2_REG_LIST(phyid) \
 396 }
 397
 398 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 399         link_regs(0, A),
 400         link_regs(1, B),
 401 };
 402
 403 #define LINK_ENCODER_MASK_SH_LIST_DCN201(mask_sh)\
 404         LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)
 405
 406 static const struct dcn10_link_enc_shift le_shift = {
 407                 LINK_ENCODER_MASK_SH_LIST_DCN201(__SHIFT)
 408 };
 409
 410 static const struct dcn10_link_enc_mask le_mask = {
 411                 LINK_ENCODER_MASK_SH_LIST_DCN201(_MASK)
 412 };
 413
 414 #define ipp_regs(id)\
 415 [id] = {\
 416                 IPP_REG_LIST_DCN201(id),\
 417 }
 418
 419 static const struct dcn10_ipp_registers ipp_regs[] = {
 420         ipp_regs(0),
 421         ipp_regs(1),
 422         ipp_regs(2),
 423         ipp_regs(3),
 424 };
 425
 426 static const struct dcn10_ipp_shift ipp_shift = {
 427                 IPP_MASK_SH_LIST_DCN201(__SHIFT)
 428 };
 429
 430 static const struct dcn10_ipp_mask ipp_mask = {
 431                 IPP_MASK_SH_LIST_DCN201(_MASK)
 432 };
 433
 434 #define opp_regs(id)\
 435 [id] = {\
 436         OPP_REG_LIST_DCN201(id),\
 437 }
 438
 439 static const struct dcn201_opp_registers opp_regs[] = {
 440         opp_regs(0),
 441         opp_regs(1),
 442 };
 443
 444 static const struct dcn201_opp_shift opp_shift = {
 445                 OPP_MASK_SH_LIST_DCN201(__SHIFT)
 446 };
 447
 448 static const struct dcn201_opp_mask opp_mask = {
 449                 OPP_MASK_SH_LIST_DCN201(_MASK)
 450 };
 451
 452 #define aux_engine_regs(id)\
 453 [id] = {\
 454         AUX_COMMON_REG_LIST0(id), \
 455         .AUX_RESET_MASK = 0 \
 456 }
 457
 458 static const struct dce110_aux_registers aux_engine_regs[] = {
 459                 aux_engine_regs(0),
 460                 aux_engine_regs(1)
 461 };
 462
 463 #define tf_regs(id)\
 464 [id] = {\
 465         TF_REG_LIST_DCN201(id),\
 466 }
 467
 468 static const struct dcn201_dpp_registers tf_regs[] = {
 469         tf_regs(0),
 470         tf_regs(1),
 471         tf_regs(2),
 472         tf_regs(3),
 473 };
 474
 475 static const struct dcn201_dpp_shift tf_shift = {
 476                 TF_REG_LIST_SH_MASK_DCN201(__SHIFT)
 477 };
 478
 479 static const struct dcn201_dpp_mask tf_mask = {
 480                 TF_REG_LIST_SH_MASK_DCN201(_MASK)
 481 };
 482
 483 static const struct dcn201_mpc_registers mpc_regs = {
 484                 MPC_REG_LIST_DCN201(0),
 485                 MPC_REG_LIST_DCN201(1),
 486                 MPC_REG_LIST_DCN201(2),
 487                 MPC_REG_LIST_DCN201(3),
 488                 MPC_REG_LIST_DCN201(4),
 489                 MPC_OUT_MUX_REG_LIST_DCN201(0),
 490                 MPC_OUT_MUX_REG_LIST_DCN201(1),
 491 };
 492
 493 static const struct dcn201_mpc_shift mpc_shift = {
 494         MPC_COMMON_MASK_SH_LIST_DCN201(__SHIFT)
 495 };
 496
 497 static const struct dcn201_mpc_mask mpc_mask = {
 498         MPC_COMMON_MASK_SH_LIST_DCN201(_MASK)
 499 };
 500
 501 #define tg_regs_dcn201(id)\
 502 [id] = {TG_COMMON_REG_LIST_DCN201(id)}
 503
 504 static const struct dcn_optc_registers tg_regs[] = {
 505         tg_regs_dcn201(0),
 506         tg_regs_dcn201(1)
 507 };
 508
 509 static const struct dcn_optc_shift tg_shift = {
 510         TG_COMMON_MASK_SH_LIST_DCN201(__SHIFT)
 511 };
 512
 513 static const struct dcn_optc_mask tg_mask = {
 514         TG_COMMON_MASK_SH_LIST_DCN201(_MASK)
 515 };
 516
 517 #define hubp_regsDCN201(id)\
 518 [id] = {\
 519         HUBP_REG_LIST_DCN201(id)\
 520 }
 521
 522 static const struct dcn201_hubp_registers hubp_regs[] = {
 523                 hubp_regsDCN201(0),
 524                 hubp_regsDCN201(1),
 525                 hubp_regsDCN201(2),
 526                 hubp_regsDCN201(3)
 527 };
 528
 529 static const struct dcn201_hubp_shift hubp_shift = {
 530                 HUBP_MASK_SH_LIST_DCN201(__SHIFT)
 531 };
 532
 533 static const struct dcn201_hubp_mask hubp_mask = {
 534                 HUBP_MASK_SH_LIST_DCN201(_MASK)
 535 };
 536
 537 static const struct dcn_hubbub_registers hubbub_reg = {
 538                 HUBBUB_REG_LIST_DCN201(0)
 539 };
 540
 541 static const struct dcn_hubbub_shift hubbub_shift = {
 542                 HUBBUB_MASK_SH_LIST_DCN201(__SHIFT)
 543 };
 544
 545 static const struct dcn_hubbub_mask hubbub_mask = {
 546                 HUBBUB_MASK_SH_LIST_DCN201(_MASK)
 547 };
 548
 549
 550 static const struct dccg_registers dccg_regs = {
 551                 DCCG_COMMON_REG_LIST_DCN_BASE()
 552 };
 553
 554 static const struct dccg_shift dccg_shift = {
 555                 DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(__SHIFT)
 556 };
 557
 558 static const struct dccg_mask dccg_mask = {
 559                 DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(_MASK)
 560 };
 561
 562 static const struct resource_caps res_cap_dnc201 = {
 563                 .num_timing_generator = 2,
 564                 .num_opp = 2,
 565                 .num_video_plane = 4,
 566                 .num_audio = 2,
 567                 .num_stream_encoder = 2,
 568                 .num_pll = 2,
 569                 .num_ddc = 2,
 570 };
 571
 572 static const struct dc_plane_cap plane_cap = {
 573         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 574         .per_pixel_alpha = true,
 575
 576         .pixel_format_support = {
 577                         .argb8888 = true,
 578                         .nv12 = false,
 579                         .fp16 = true,
 580                         .p010 = false,
 581         },
 582
 583         .max_upscale_factor = {
 584                         .argb8888 = 16000,
 585                         .nv12 = 16000,
 586                         .fp16 = 1
 587         },
 588
 589         .max_downscale_factor = {
 590                         .argb8888 = 250,
 591                         .nv12 = 250,
 592                         .fp16 = 250
 593         },
 594         64,
 595         64
 596 };
 597
 598 static const struct dc_debug_options debug_defaults_drv = {
 599                 .disable_dmcu = true,
 600                 .force_abm_enable = false,
 601                 .timing_trace = false,
 602                 .clock_trace = true,
 603                 .disable_pplib_clock_request = true,
 604                 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
 605                 .force_single_disp_pipe_split = false,
 606                 .disable_dcc = DCC_ENABLE,
 607                 .vsr_support = true,
 608                 .performance_trace = false,
 609                 .az_endpoint_mute_only = true,
 610                 .max_downscale_src_width = 3840,
 611                 .disable_pplib_wm_range = true,
 612                 .scl_reset_length10 = true,
 613                 .sanity_checks = false,
 614                 .underflow_assert_delay_us = 0xFFFFFFFF,
 615                 .enable_tri_buf = false,
 616                 .enable_legacy_fast_update = true,
 617 };
 618
 619 static void dcn201_dpp_destroy(struct dpp **dpp)
 620 {
 621         kfree(TO_DCN201_DPP(*dpp));
 622         *dpp = NULL;
 623 }
 624
 625 static struct dpp *dcn201_dpp_create(
 626         struct dc_context *ctx,
 627         uint32_t inst)
 628 {
 629         struct dcn201_dpp *dpp =
 630                 kzalloc(sizeof(struct dcn201_dpp), GFP_ATOMIC);
 631
 632         if (!dpp)
 633                 return NULL;
 634
 635         if (dpp201_construct(dpp, ctx, inst,
 636                         &tf_regs[inst], &tf_shift, &tf_mask))
 637                 return &dpp->base;
 638
 639         kfree(dpp);
 640         return NULL;
 641 }
 642
 643 static struct input_pixel_processor *dcn201_ipp_create(
 644         struct dc_context *ctx, uint32_t inst)
 645 {
 646         struct dcn10_ipp *ipp =
 647                 kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC);
 648
 649         if (!ipp) {
 650                 return NULL;
 651         }
 652
 653         dcn20_ipp_construct(ipp, ctx, inst,
 654                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 655         return &ipp->base;
 656 }
 657
 658
 659 static struct output_pixel_processor *dcn201_opp_create(
 660         struct dc_context *ctx, uint32_t inst)
 661 {
 662         struct dcn201_opp *opp =
 663                 kzalloc(sizeof(struct dcn201_opp), GFP_ATOMIC);
 664
 665         if (!opp) {
 666                 return NULL;
 667         }
 668
 669         dcn201_opp_construct(opp, ctx, inst,
 670                         &opp_regs[inst], &opp_shift, &opp_mask);
 671         return &opp->base;
 672 }
 673
 674 static struct dce_aux *dcn201_aux_engine_create(struct dc_context *ctx,
 675                                                 uint32_t inst)
 676 {
 677         struct aux_engine_dce110 *aux_engine =
 678                 kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC);
 679
 680         if (!aux_engine)
 681                 return NULL;
 682
 683         dce110_aux_engine_construct(aux_engine, ctx, inst,
 684                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 685                                     &aux_engine_regs[inst],
 686                                         &aux_mask,
 687                                         &aux_shift,
 688                                         ctx->dc->caps.extended_aux_timeout_support);
 689
 690         return &aux_engine->base;
 691 }
 692 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 693
 694 static const struct dce_i2c_registers i2c_hw_regs[] = {
 695                 i2c_inst_regs(1),
 696                 i2c_inst_regs(2),
 697 };
 698
 699 static const struct dce_i2c_shift i2c_shifts = {
 700                 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
 701 };
 702
 703 static const struct dce_i2c_mask i2c_masks = {
 704                 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
 705 };
 706
 707 static struct dce_i2c_hw *dcn201_i2c_hw_create(struct dc_context *ctx,
 708                                                uint32_t inst)
 709 {
 710         struct dce_i2c_hw *dce_i2c_hw =
 711                 kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC);
 712
 713         if (!dce_i2c_hw)
 714                 return NULL;
 715
 716         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 717                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 718
 719         return dce_i2c_hw;
 720 }
 721
 722 static struct mpc *dcn201_mpc_create(struct dc_context *ctx, uint32_t num_mpcc)
 723 {
 724         struct dcn201_mpc *mpc201 = kzalloc(sizeof(struct dcn201_mpc),
 725                                             GFP_ATOMIC);
 726
 727         if (!mpc201)
 728                 return NULL;
 729
 730         dcn201_mpc_construct(mpc201, ctx,
 731                         &mpc_regs,
 732                         &mpc_shift,
 733                         &mpc_mask,
 734                         num_mpcc);
 735
 736         return &mpc201->base;
 737 }
 738
 739 static struct hubbub *dcn201_hubbub_create(struct dc_context *ctx)
 740 {
 741         struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
 742                                           GFP_ATOMIC);
 743
 744         if (!hubbub)
 745                 return NULL;
 746
 747         hubbub201_construct(hubbub, ctx,
 748                         &hubbub_reg,
 749                         &hubbub_shift,
 750                         &hubbub_mask);
 751
 752         return &hubbub->base;
 753 }
 754
 755 static struct timing_generator *dcn201_timing_generator_create(
 756                 struct dc_context *ctx,
 757                 uint32_t instance)
 758 {
 759         struct optc *tgn10 =
 760                 kzalloc(sizeof(struct optc), GFP_ATOMIC);
 761
 762         if (!tgn10)
 763                 return NULL;
 764
 765         tgn10->base.inst = instance;
 766         tgn10->base.ctx = ctx;
 767
 768         tgn10->tg_regs = &tg_regs[instance];
 769         tgn10->tg_shift = &tg_shift;
 770         tgn10->tg_mask = &tg_mask;
 771
 772         dcn201_timing_generator_init(tgn10);
 773
 774         return &tgn10->base;
 775 }
 776
 777 static const struct encoder_feature_support link_enc_feature = {
 778                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 779                 .max_hdmi_pixel_clock = 600000,
 780                 .hdmi_ycbcr420_supported = true,
 781                 .dp_ycbcr420_supported = true,
 782                 .fec_supported = true,
 783                 .flags.bits.IS_HBR2_CAPABLE = true,
 784                 .flags.bits.IS_HBR3_CAPABLE = true,
 785                 .flags.bits.IS_TPS3_CAPABLE = true,
 786                 .flags.bits.IS_TPS4_CAPABLE = true
 787 };
 788
 789 static struct link_encoder *dcn201_link_encoder_create(
 790         struct dc_context *ctx,
 791         const struct encoder_init_data *enc_init_data)
 792 {
 793         struct dcn20_link_encoder *enc20 =
 794                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_ATOMIC);
 795         struct dcn10_link_encoder *enc10 = &enc20->enc10;
 796
 797         if (!enc20)
 798                 return NULL;
 799
 800         dcn201_link_encoder_construct(enc20,
 801                         enc_init_data,
 802                         &link_enc_feature,
 803                         &link_enc_regs[enc_init_data->transmitter],
 804                         &link_enc_aux_regs[enc_init_data->channel - 1],
 805                         &link_enc_hpd_regs[enc_init_data->hpd_source],
 806                         &le_shift,
 807                         &le_mask);
 808
 809         return &enc10->base;
 810 }
 811
 812 static struct clock_source *dcn201_clock_source_create(
 813         struct dc_context *ctx,
 814         struct dc_bios *bios,
 815         enum clock_source_id id,
 816         const struct dce110_clk_src_regs *regs,
 817         bool dp_clk_src)
 818 {
 819         struct dce110_clk_src *clk_src =
 820                 kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC);
 821
 822         if (!clk_src)
 823                 return NULL;
 824
 825         if (dce112_clk_src_construct(clk_src, ctx, bios, id,
 826                         regs, &cs_shift, &cs_mask)) {
 827                 clk_src->base.dp_clk_src = dp_clk_src;
 828                 return &clk_src->base;
 829         }
 830         kfree(clk_src);
 831         return NULL;
 832 }
 833
 834 static void read_dce_straps(
 835         struct dc_context *ctx,
 836         struct resource_straps *straps)
 837 {
 838         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
 839
 840                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
 841 }
 842
 843 static struct audio *dcn201_create_audio(
 844                 struct dc_context *ctx, unsigned int inst)
 845 {
 846         return dce_audio_create(ctx, inst,
 847                         &audio_regs[inst], &audio_shift, &audio_mask);
 848 }
 849
 850 static struct stream_encoder *dcn201_stream_encoder_create(
 851         enum engine_id eng_id,
 852         struct dc_context *ctx)
 853 {
 854         struct dcn10_stream_encoder *enc1 =
 855                 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_ATOMIC);
 856
 857         if (!enc1)
 858                 return NULL;
 859
 860         dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
 861                                         &stream_enc_regs[eng_id],
 862                                         &se_shift, &se_mask);
 863
 864         return &enc1->base;
 865 }
 866
 867 static const struct dce_hwseq_registers hwseq_reg = {
 868                 HWSEQ_DCN201_REG_LIST()
 869 };
 870
 871 static const struct dce_hwseq_shift hwseq_shift = {
 872                 HWSEQ_DCN201_MASK_SH_LIST(__SHIFT)
 873 };
 874
 875 static const struct dce_hwseq_mask hwseq_mask = {
 876                 HWSEQ_DCN201_MASK_SH_LIST(_MASK)
 877 };
 878
 879 static struct dce_hwseq *dcn201_hwseq_create(
 880         struct dc_context *ctx)
 881 {
 882         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_ATOMIC);
 883
 884         if (hws) {
 885                 hws->ctx = ctx;
 886                 hws->regs = &hwseq_reg;
 887                 hws->shifts = &hwseq_shift;
 888                 hws->masks = &hwseq_mask;
 889         }
 890         return hws;
 891 }
 892
 893 static const struct resource_create_funcs res_create_funcs = {
 894         .read_dce_straps = read_dce_straps,
 895         .create_audio = dcn201_create_audio,
 896         .create_stream_encoder = dcn201_stream_encoder_create,
 897         .create_hwseq = dcn201_hwseq_create,
 898 };
 899
 900 static void dcn201_clock_source_destroy(struct clock_source **clk_src)
 901 {
 902         kfree(TO_DCE110_CLK_SRC(*clk_src));
 903         *clk_src = NULL;
 904 }
 905
 906 static void dcn201_resource_destruct(struct dcn201_resource_pool *pool)
 907 {
 908         unsigned int i;
 909
 910         for (i = 0; i < pool->base.stream_enc_count; i++) {
 911                 if (pool->base.stream_enc[i] != NULL) {
 912                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 913                         pool->base.stream_enc[i] = NULL;
 914                 }
 915         }
 916
 917
 918         if (pool->base.mpc != NULL) {
 919                 kfree(TO_DCN201_MPC(pool->base.mpc));
 920                 pool->base.mpc = NULL;
 921         }
 922
 923         if (pool->base.hubbub != NULL) {
 924                 kfree(pool->base.hubbub);
 925                 pool->base.hubbub = NULL;
 926         }
 927
 928         for (i = 0; i < pool->base.pipe_count; i++) {
 929                 if (pool->base.dpps[i] != NULL)
 930                         dcn201_dpp_destroy(&pool->base.dpps[i]);
 931
 932                 if (pool->base.ipps[i] != NULL)
 933                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
 934
 935                 if (pool->base.hubps[i] != NULL) {
 936                         kfree(TO_DCN10_HUBP(pool->base.hubps[i]));
 937                         pool->base.hubps[i] = NULL;
 938                 }
 939
 940                 if (pool->base.irqs != NULL) {
 941                         dal_irq_service_destroy(&pool->base.irqs);
 942                 }
 943         }
 944
 945         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
 946                 if (pool->base.opps[i] != NULL)
 947                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
 948         }
 949
 950         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
 951                 if (pool->base.timing_generators[i] != NULL)    {
 952                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
 953                         pool->base.timing_generators[i] = NULL;
 954                 }
 955         }
 956         for (i = 0; i < pool->base.audio_count; i++) {
 957                 if (pool->base.audios[i])
 958                         dce_aud_destroy(&pool->base.audios[i]);
 959         }
 960
 961         for (i = 0; i < pool->base.clk_src_count; i++) {
 962                 if (pool->base.clock_sources[i] != NULL) {
 963                         dcn201_clock_source_destroy(&pool->base.clock_sources[i]);
 964                         pool->base.clock_sources[i] = NULL;
 965                 }
 966         }
 967
 968         if (pool->base.dp_clock_source != NULL) {
 969                 dcn201_clock_source_destroy(&pool->base.dp_clock_source);
 970                 pool->base.dp_clock_source = NULL;
 971         }
 972
 973         if (pool->base.dccg != NULL)
 974                 dcn_dccg_destroy(&pool->base.dccg);
 975 }
 976
 977 static struct hubp *dcn201_hubp_create(
 978         struct dc_context *ctx,
 979         uint32_t inst)
 980 {
 981         struct dcn201_hubp *hubp201 =
 982                 kzalloc(sizeof(struct dcn201_hubp), GFP_ATOMIC);
 983
 984         if (!hubp201)
 985                 return NULL;
 986
 987         if (dcn201_hubp_construct(hubp201, ctx, inst,
 988                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
 989                 return &hubp201->base;
 990
 991         kfree(hubp201);
 992         return NULL;
 993 }
 994
 995 static struct pipe_ctx *dcn201_acquire_idle_pipe_for_layer(
 996                 struct dc_state *context,
 997                 const struct resource_pool *pool,
 998                 struct dc_stream_state *stream)
 999 {
1000         struct resource_context *res_ctx = &context->res_ctx;
1001         struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1002         struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
1003
1004         if (!head_pipe)
1005                 ASSERT(0);
1006
1007         if (!idle_pipe)
1008                 return NULL;
1009
1010         idle_pipe->stream = head_pipe->stream;
1011         idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
1012         idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
1013
1014         idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
1015         idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
1016         idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
1017         idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
1018
1019         return idle_pipe;
1020 }
1021
1022 static bool dcn201_get_dcc_compression_cap(const struct dc *dc,
1023                 const struct dc_dcc_surface_param *input,
1024                 struct dc_surface_dcc_cap *output)
1025 {
1026         return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
1027                         dc->res_pool->hubbub,
1028                         input,
1029                         output);
1030 }
1031
1032 static void dcn201_populate_dml_writeback_from_context(struct dc *dc,
1033                                                        struct resource_context *res_ctx,
1034                                                        display_e2e_pipe_params_st *pipes)
1035 {
1036         DC_FP_START();
1037         dcn201_populate_dml_writeback_from_context_fpu(dc, res_ctx, pipes);
1038         DC_FP_END();
1039 }
1040
1041 static void dcn201_destroy_resource_pool(struct resource_pool **pool)
1042 {
1043         struct dcn201_resource_pool *dcn201_pool = TO_DCN201_RES_POOL(*pool);
1044
1045         dcn201_resource_destruct(dcn201_pool);
1046         kfree(dcn201_pool);
1047         *pool = NULL;
1048 }
1049
1050 static void dcn201_link_init(struct dc_link *link)
1051 {
1052         if (link->ctx->dc_bios->integrated_info)
1053                 link->dp_ss_off = !link->ctx->dc_bios->integrated_info->dp_ss_control;
1054 }
1055
1056 static struct dc_cap_funcs cap_funcs = {
1057         .get_dcc_compression_cap = dcn201_get_dcc_compression_cap,
1058 };
1059
1060 static struct resource_funcs dcn201_res_pool_funcs = {
1061         .link_init = dcn201_link_init,
1062         .destroy = dcn201_destroy_resource_pool,
1063         .link_enc_create = dcn201_link_encoder_create,
1064         .panel_cntl_create = NULL,
1065         .validate_bandwidth = dcn20_validate_bandwidth,
1066         .populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
1067         .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1068         .add_dsc_to_stream_resource = NULL,
1069         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1070         .acquire_idle_pipe_for_layer = dcn201_acquire_idle_pipe_for_layer,
1071         .populate_dml_writeback_from_context = dcn201_populate_dml_writeback_from_context,
1072         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1073         .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1074         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
1075 };
1076
1077 static bool dcn201_resource_construct(
1078         uint8_t num_virtual_links,
1079         struct dc *dc,
1080         struct dcn201_resource_pool *pool)
1081 {
1082         int i;
1083         struct dc_context *ctx = dc->ctx;
1084
1085         ctx->dc_bios->regs = &bios_regs;
1086
1087         pool->base.res_cap = &res_cap_dnc201;
1088         pool->base.funcs = &dcn201_res_pool_funcs;
1089
1090         /*************************************************
1091          *  Resource + asic cap harcoding                *
1092          *************************************************/
1093         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1094
1095         pool->base.pipe_count = 4;
1096         pool->base.mpcc_count = 5;
1097         dc->caps.max_downscale_ratio = 200;
1098         dc->caps.i2c_speed_in_khz = 100;
1099         dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.5 w/a applied by default*/
1100         dc->caps.max_cursor_size = 256;
1101         dc->caps.min_horizontal_blanking_period = 80;
1102         dc->caps.dmdata_alloc_size = 2048;
1103
1104         dc->caps.max_slave_planes = 1;
1105         dc->caps.max_slave_yuv_planes = 1;
1106         dc->caps.max_slave_rgb_planes = 1;
1107         dc->caps.post_blend_color_processing = true;
1108         dc->caps.force_dp_tps4_for_cp2520 = true;
1109         dc->caps.extended_aux_timeout_support = true;
1110
1111         /* Color pipeline capabilities */
1112         dc->caps.color.dpp.dcn_arch = 1;
1113         dc->caps.color.dpp.input_lut_shared = 0;
1114         dc->caps.color.dpp.icsc = 1;
1115         dc->caps.color.dpp.dgam_ram = 1;
1116         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1117         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1118         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1119         dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1120         dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1121         dc->caps.color.dpp.post_csc = 0;
1122         dc->caps.color.dpp.gamma_corr = 0;
1123         dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1124
1125         dc->caps.color.dpp.hw_3d_lut = 1;
1126         dc->caps.color.dpp.ogam_ram = 1;
1127         // no OGAM ROM on DCN2
1128         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1129         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1130         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1131         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1132         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1133         dc->caps.color.dpp.ocsc = 0;
1134
1135         dc->caps.color.mpc.gamut_remap = 0;
1136         dc->caps.color.mpc.num_3dluts = 0;
1137         dc->caps.color.mpc.shared_3d_lut = 0;
1138         dc->caps.color.mpc.ogam_ram = 1;
1139         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1140         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1141         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1142         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1143         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1144         dc->caps.color.mpc.ocsc = 1;
1145
1146         dc->debug = debug_defaults_drv;
1147
1148         /*a0 only, remove later*/
1149         dc->work_arounds.no_connect_phy_config  = true;
1150         dc->work_arounds.dedcn20_305_wa = true;
1151         /*************************************************
1152          *  Create resources                             *
1153          *************************************************/
1154
1155         pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1156                         dcn201_clock_source_create(ctx, ctx->dc_bios,
1157                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1158                                 &clk_src_regs[0], false);
1159         pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1160                         dcn201_clock_source_create(ctx, ctx->dc_bios,
1161                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1162                                 &clk_src_regs[1], false);
1163
1164         pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN201;
1165
1166         /* todo: not reuse phy_pll registers */
1167         pool->base.dp_clock_source =
1168                         dcn201_clock_source_create(ctx, ctx->dc_bios,
1169                                 CLOCK_SOURCE_ID_DP_DTO,
1170                                 &clk_src_regs[0], true);
1171
1172         for (i = 0; i < pool->base.clk_src_count; i++) {
1173                 if (pool->base.clock_sources[i] == NULL) {
1174                         dm_error("DC: failed to create clock sources!\n");
1175                         goto create_fail;
1176                 }
1177         }
1178
1179         pool->base.dccg = dccg201_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1180         if (pool->base.dccg == NULL) {
1181                 dm_error("DC: failed to create dccg!\n");
1182                 goto create_fail;
1183         }
1184
1185         dcn201_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1186         dcn201_ip.max_num_dpp = pool->base.pipe_count;
1187         dml_init_instance(&dc->dml, &dcn201_soc, &dcn201_ip, DML_PROJECT_DCN201);
1188         {
1189                 struct irq_service_init_data init_data;
1190                 init_data.ctx = dc->ctx;
1191                 pool->base.irqs = dal_irq_service_dcn201_create(&init_data);
1192                 if (!pool->base.irqs)
1193                         goto create_fail;
1194         }
1195
1196         /* mem input -> ipp -> dpp -> opp -> TG */
1197         for (i = 0; i < pool->base.pipe_count; i++) {
1198                 pool->base.hubps[i] = dcn201_hubp_create(ctx, i);
1199                 if (pool->base.hubps[i] == NULL) {
1200                         dm_error(
1201                                 "DC: failed to create memory input!\n");
1202                         goto create_fail;
1203                 }
1204
1205                 pool->base.ipps[i] = dcn201_ipp_create(ctx, i);
1206                 if (pool->base.ipps[i] == NULL) {
1207                         dm_error(
1208                                 "DC: failed to create input pixel processor!\n");
1209                         goto create_fail;
1210                 }
1211
1212                 pool->base.dpps[i] = dcn201_dpp_create(ctx, i);
1213                 if (pool->base.dpps[i] == NULL) {
1214                         dm_error(
1215                                 "DC: failed to create dpps!\n");
1216                         goto create_fail;
1217                 }
1218         }
1219
1220         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1221                 pool->base.opps[i] = dcn201_opp_create(ctx, i);
1222                 if (pool->base.opps[i] == NULL) {
1223                         dm_error(
1224                                 "DC: failed to create output pixel processor!\n");
1225                         goto create_fail;
1226                 }
1227         }
1228
1229         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1230                 pool->base.engines[i] = dcn201_aux_engine_create(ctx, i);
1231                 if (pool->base.engines[i] == NULL) {
1232                         dm_error(
1233                                 "DC:failed to create aux engine!!\n");
1234                         goto create_fail;
1235                 }
1236                 pool->base.hw_i2cs[i] = dcn201_i2c_hw_create(ctx, i);
1237                 if (pool->base.hw_i2cs[i] == NULL) {
1238                         dm_error(
1239                                 "DC:failed to create hw i2c!!\n");
1240                         goto create_fail;
1241                 }
1242                 pool->base.sw_i2cs[i] = NULL;
1243         }
1244
1245         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1246                 pool->base.timing_generators[i] = dcn201_timing_generator_create(
1247                                 ctx, i);
1248                 if (pool->base.timing_generators[i] == NULL) {
1249                         dm_error("DC: failed to create tg!\n");
1250                         goto create_fail;
1251                 }
1252         }
1253
1254         pool->base.timing_generator_count = i;
1255
1256         pool->base.mpc = dcn201_mpc_create(ctx, pool->base.mpcc_count);
1257         if (pool->base.mpc == NULL) {
1258                 dm_error("DC: failed to create mpc!\n");
1259                 goto create_fail;
1260         }
1261
1262         pool->base.hubbub = dcn201_hubbub_create(ctx);
1263         if (pool->base.hubbub == NULL) {
1264                 dm_error("DC: failed to create hubbub!\n");
1265                 goto create_fail;
1266         }
1267
1268         if (!resource_construct(num_virtual_links, dc, &pool->base,
1269                         &res_create_funcs))
1270                 goto create_fail;
1271
1272         dcn201_hw_sequencer_construct(dc);
1273
1274         dc->caps.max_planes =  pool->base.pipe_count;
1275
1276         for (i = 0; i < dc->caps.max_planes; ++i)
1277                 dc->caps.planes[i] = plane_cap;
1278
1279         dc->cap_funcs = cap_funcs;
1280
1281         return true;
1282
1283 create_fail:
1284
1285         dcn201_resource_destruct(pool);
1286
1287         return false;
1288 }
1289
1290 struct resource_pool *dcn201_create_resource_pool(
1291                 const struct dc_init_data *init_data,
1292                 struct dc *dc)
1293 {
1294         struct dcn201_resource_pool *pool =
1295                 kzalloc(sizeof(struct dcn201_resource_pool), GFP_ATOMIC);
1296
1297         if (!pool)
1298                 return NULL;
1299
1300         if (dcn201_resource_construct(init_data->num_virtual_links, dc, pool))
1301                 return &pool->base;
1302
1303         kfree(pool);
1304         return NULL;
1305 }