drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "dm_services.h"
  26 #include "dc.h"
  27 #include "dc_bios_types.h"
  28 #include "core_types.h"
  29 #include "core_status.h"
  30 #include "resource.h"
  31 #include "dm_helpers.h"
  32 #include "dce110_hw_sequencer.h"
  33 #include "dce110_timing_generator.h"
  34 #include "dce/dce_hwseq.h"
  35 #include "gpio_service_interface.h"
  36
  37 #include "dce110_compressor.h"
  38
  39 #include "bios/bios_parser_helper.h"
  40 #include "timing_generator.h"
  41 #include "mem_input.h"
  42 #include "opp.h"
  43 #include "ipp.h"
  44 #include "transform.h"
  45 #include "stream_encoder.h"
  46 #include "link_encoder.h"
  47 #include "link_hwss.h"
  48 #include "clock_source.h"
  49 #include "abm.h"
  50 #include "audio.h"
  51 #include "reg_helper.h"
  52
  53 /* include DCE11 register header files */
  54 #include "dce/dce_11_0_d.h"
  55 #include "dce/dce_11_0_sh_mask.h"
  56 #include "custom_float.h"
  57
  58 #include "atomfirmware.h"
  59
  60 /*
  61  * All values are in milliseconds;
  62  * For eDP, after power-up/power/down,
  63  * 300/500 msec max. delay from LCDVCC to black video generation
  64  */
  65 #define PANEL_POWER_UP_TIMEOUT 300
  66 #define PANEL_POWER_DOWN_TIMEOUT 500
  67 #define HPD_CHECK_INTERVAL 10
  68
  69 #define CTX \
  70         hws->ctx
  71
  72 #define DC_LOGGER_INIT()
  73
  74 #define REG(reg)\
  75         hws->regs->reg
  76
  77 #undef FN
  78 #define FN(reg_name, field_name) \
  79         hws->shifts->field_name, hws->masks->field_name
  80
  81 struct dce110_hw_seq_reg_offsets {
  82         uint32_t crtc;
  83 };
  84
  85 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
  86 {
  87         .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  88 },
  89 {
  90         .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  91 },
  92 {
  93         .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  94 },
  95 {
  96         .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  97 }
  98 };
  99
 100 #define HW_REG_BLND(reg, id)\
 101         (reg + reg_offsets[id].blnd)
 102
 103 #define HW_REG_CRTC(reg, id)\
 104         (reg + reg_offsets[id].crtc)
 105
 106 #define MAX_WATERMARK 0xFFFF
 107 #define SAFE_NBP_MARK 0x7FFF
 108
 109 /*******************************************************************************
 110  * Private definitions
 111  ******************************************************************************/
 112 /***************************PIPE_CONTROL***********************************/
 113 static void dce110_init_pte(struct dc_context *ctx)
 114 {
 115         uint32_t addr;
 116         uint32_t value = 0;
 117         uint32_t chunk_int = 0;
 118         uint32_t chunk_mul = 0;
 119
 120         addr = mmUNP_DVMM_PTE_CONTROL;
 121         value = dm_read_reg(ctx, addr);
 122
 123         set_reg_field_value(
 124                 value,
 125                 0,
 126                 DVMM_PTE_CONTROL,
 127                 DVMM_USE_SINGLE_PTE);
 128
 129         set_reg_field_value(
 130                 value,
 131                 1,
 132                 DVMM_PTE_CONTROL,
 133                 DVMM_PTE_BUFFER_MODE0);
 134
 135         set_reg_field_value(
 136                 value,
 137                 1,
 138                 DVMM_PTE_CONTROL,
 139                 DVMM_PTE_BUFFER_MODE1);
 140
 141         dm_write_reg(ctx, addr, value);
 142
 143         addr = mmDVMM_PTE_REQ;
 144         value = dm_read_reg(ctx, addr);
 145
 146         chunk_int = get_reg_field_value(
 147                 value,
 148                 DVMM_PTE_REQ,
 149                 HFLIP_PTEREQ_PER_CHUNK_INT);
 150
 151         chunk_mul = get_reg_field_value(
 152                 value,
 153                 DVMM_PTE_REQ,
 154                 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 155
 156         if (chunk_int != 0x4 || chunk_mul != 0x4) {
 157
 158                 set_reg_field_value(
 159                         value,
 160                         255,
 161                         DVMM_PTE_REQ,
 162                         MAX_PTEREQ_TO_ISSUE);
 163
 164                 set_reg_field_value(
 165                         value,
 166                         4,
 167                         DVMM_PTE_REQ,
 168                         HFLIP_PTEREQ_PER_CHUNK_INT);
 169
 170                 set_reg_field_value(
 171                         value,
 172                         4,
 173                         DVMM_PTE_REQ,
 174                         HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 175
 176                 dm_write_reg(ctx, addr, value);
 177         }
 178 }
 179 /**************************************************************************/
 180
 181 static void enable_display_pipe_clock_gating(
 182         struct dc_context *ctx,
 183         bool clock_gating)
 184 {
 185         /*TODO*/
 186 }
 187
 188 static bool dce110_enable_display_power_gating(
 189         struct dc *dc,
 190         uint8_t controller_id,
 191         struct dc_bios *dcb,
 192         enum pipe_gating_control power_gating)
 193 {
 194         enum bp_result bp_result = BP_RESULT_OK;
 195         enum bp_pipe_control_action cntl;
 196         struct dc_context *ctx = dc->ctx;
 197         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
 198
 199         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
 200                 return true;
 201
 202         if (power_gating == PIPE_GATING_CONTROL_INIT)
 203                 cntl = ASIC_PIPE_INIT;
 204         else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
 205                 cntl = ASIC_PIPE_ENABLE;
 206         else
 207                 cntl = ASIC_PIPE_DISABLE;
 208
 209         if (controller_id == underlay_idx)
 210                 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
 211
 212         if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
 213
 214                 bp_result = dcb->funcs->enable_disp_power_gating(
 215                                                 dcb, controller_id + 1, cntl);
 216
 217                 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
 218                  * by default when command table is called
 219                  *
 220                  * Bios parser accepts controller_id = 6 as indicative of
 221                  * underlay pipe in dce110. But we do not support more
 222                  * than 3.
 223                  */
 224                 if (controller_id < CONTROLLER_ID_MAX - 1)
 225                         dm_write_reg(ctx,
 226                                 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
 227                                 0);
 228         }
 229
 230         if (power_gating != PIPE_GATING_CONTROL_ENABLE)
 231                 dce110_init_pte(ctx);
 232
 233         if (bp_result == BP_RESULT_OK)
 234                 return true;
 235         else
 236                 return false;
 237 }
 238
 239 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
 240                 const struct dc_plane_state *plane_state)
 241 {
 242         prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
 243
 244         switch (plane_state->format) {
 245         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 246         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 247                 prescale_params->scale = 0x2020;
 248                 break;
 249         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 250         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 251                 prescale_params->scale = 0x2008;
 252                 break;
 253         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 254         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 255                 prescale_params->scale = 0x2000;
 256                 break;
 257         default:
 258                 ASSERT(false);
 259                 break;
 260         }
 261 }
 262
 263 static bool
 264 dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
 265                                const struct dc_plane_state *plane_state)
 266 {
 267         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
 268         const struct dc_transfer_func *tf = NULL;
 269         struct ipp_prescale_params prescale_params = { 0 };
 270         bool result = true;
 271
 272         if (ipp == NULL)
 273                 return false;
 274
 275         if (plane_state->in_transfer_func)
 276                 tf = plane_state->in_transfer_func;
 277
 278         build_prescale_params(&prescale_params, plane_state);
 279         ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
 280
 281         if (plane_state->gamma_correction &&
 282                         !plane_state->gamma_correction->is_identity &&
 283                         dce_use_lut(plane_state->format))
 284                 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
 285
 286         if (tf == NULL) {
 287                 /* Default case if no input transfer function specified */
 288                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 289         } else if (tf->type == TF_TYPE_PREDEFINED) {
 290                 switch (tf->tf) {
 291                 case TRANSFER_FUNCTION_SRGB:
 292                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 293                         break;
 294                 case TRANSFER_FUNCTION_BT709:
 295                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
 296                         break;
 297                 case TRANSFER_FUNCTION_LINEAR:
 298                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 299                         break;
 300                 case TRANSFER_FUNCTION_PQ:
 301                 default:
 302                         result = false;
 303                         break;
 304                 }
 305         } else if (tf->type == TF_TYPE_BYPASS) {
 306                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 307         } else {
 308                 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
 309                 result = false;
 310         }
 311
 312         return result;
 313 }
 314
 315 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
 316                                     struct curve_points *arr_points,
 317                                     uint32_t hw_points_num)
 318 {
 319         struct custom_float_format fmt;
 320
 321         struct pwl_result_data *rgb = rgb_resulted;
 322
 323         uint32_t i = 0;
 324
 325         fmt.exponenta_bits = 6;
 326         fmt.mantissa_bits = 12;
 327         fmt.sign = true;
 328
 329         if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
 330                                             &arr_points[0].custom_float_x)) {
 331                 BREAK_TO_DEBUGGER();
 332                 return false;
 333         }
 334
 335         if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
 336                                             &arr_points[0].custom_float_offset)) {
 337                 BREAK_TO_DEBUGGER();
 338                 return false;
 339         }
 340
 341         if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
 342                                             &arr_points[0].custom_float_slope)) {
 343                 BREAK_TO_DEBUGGER();
 344                 return false;
 345         }
 346
 347         fmt.mantissa_bits = 10;
 348         fmt.sign = false;
 349
 350         if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
 351                                             &arr_points[1].custom_float_x)) {
 352                 BREAK_TO_DEBUGGER();
 353                 return false;
 354         }
 355
 356         if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
 357                                             &arr_points[1].custom_float_y)) {
 358                 BREAK_TO_DEBUGGER();
 359                 return false;
 360         }
 361
 362         if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
 363                                             &arr_points[1].custom_float_slope)) {
 364                 BREAK_TO_DEBUGGER();
 365                 return false;
 366         }
 367
 368         fmt.mantissa_bits = 12;
 369         fmt.sign = true;
 370
 371         while (i != hw_points_num) {
 372                 if (!convert_to_custom_float_format(rgb->red, &fmt,
 373                                                     &rgb->red_reg)) {
 374                         BREAK_TO_DEBUGGER();
 375                         return false;
 376                 }
 377
 378                 if (!convert_to_custom_float_format(rgb->green, &fmt,
 379                                                     &rgb->green_reg)) {
 380                         BREAK_TO_DEBUGGER();
 381                         return false;
 382                 }
 383
 384                 if (!convert_to_custom_float_format(rgb->blue, &fmt,
 385                                                     &rgb->blue_reg)) {
 386                         BREAK_TO_DEBUGGER();
 387                         return false;
 388                 }
 389
 390                 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
 391                                                     &rgb->delta_red_reg)) {
 392                         BREAK_TO_DEBUGGER();
 393                         return false;
 394                 }
 395
 396                 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
 397                                                     &rgb->delta_green_reg)) {
 398                         BREAK_TO_DEBUGGER();
 399                         return false;
 400                 }
 401
 402                 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
 403                                                     &rgb->delta_blue_reg)) {
 404                         BREAK_TO_DEBUGGER();
 405                         return false;
 406                 }
 407
 408                 ++rgb;
 409                 ++i;
 410         }
 411
 412         return true;
 413 }
 414
 415 #define MAX_LOW_POINT      25
 416 #define NUMBER_REGIONS     16
 417 #define NUMBER_SW_SEGMENTS 16
 418
 419 static bool
 420 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
 421                                       struct pwl_params *regamma_params)
 422 {
 423         struct curve_points *arr_points;
 424         struct pwl_result_data *rgb_resulted;
 425         struct pwl_result_data *rgb;
 426         struct pwl_result_data *rgb_plus_1;
 427         struct fixed31_32 y_r;
 428         struct fixed31_32 y_g;
 429         struct fixed31_32 y_b;
 430         struct fixed31_32 y1_min;
 431         struct fixed31_32 y3_max;
 432
 433         int32_t region_start, region_end;
 434         uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
 435
 436         if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
 437                 return false;
 438
 439         arr_points = regamma_params->arr_points;
 440         rgb_resulted = regamma_params->rgb_resulted;
 441         hw_points = 0;
 442
 443         memset(regamma_params, 0, sizeof(struct pwl_params));
 444
 445         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 446                 /* 16 segments
 447                  * segments are from 2^-11 to 2^5
 448                  */
 449                 region_start = -11;
 450                 region_end = region_start + NUMBER_REGIONS;
 451
 452                 for (i = 0; i < NUMBER_REGIONS; i++)
 453                         seg_distr[i] = 4;
 454
 455         } else {
 456                 /* 10 segments
 457                  * segment is from 2^-10 to 2^1
 458                  * We include an extra segment for range [2^0, 2^1). This is to
 459                  * ensure that colors with normalized values of 1 don't miss the
 460                  * LUT.
 461                  */
 462                 region_start = -10;
 463                 region_end = 1;
 464
 465                 seg_distr[0] = 4;
 466                 seg_distr[1] = 4;
 467                 seg_distr[2] = 4;
 468                 seg_distr[3] = 4;
 469                 seg_distr[4] = 4;
 470                 seg_distr[5] = 4;
 471                 seg_distr[6] = 4;
 472                 seg_distr[7] = 4;
 473                 seg_distr[8] = 4;
 474                 seg_distr[9] = 4;
 475                 seg_distr[10] = 0;
 476                 seg_distr[11] = -1;
 477                 seg_distr[12] = -1;
 478                 seg_distr[13] = -1;
 479                 seg_distr[14] = -1;
 480                 seg_distr[15] = -1;
 481         }
 482
 483         for (k = 0; k < 16; k++) {
 484                 if (seg_distr[k] != -1)
 485                         hw_points += (1 << seg_distr[k]);
 486         }
 487
 488         j = 0;
 489         for (k = 0; k < (region_end - region_start); k++) {
 490                 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
 491                 start_index = (region_start + k + MAX_LOW_POINT) *
 492                                 NUMBER_SW_SEGMENTS;
 493                 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
 494                                 i += increment) {
 495                         if (j == hw_points - 1)
 496                                 break;
 497                         rgb_resulted[j].red = output_tf->tf_pts.red[i];
 498                         rgb_resulted[j].green = output_tf->tf_pts.green[i];
 499                         rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
 500                         j++;
 501                 }
 502         }
 503
 504         /* last point */
 505         start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
 506         rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
 507         rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
 508         rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
 509
 510         arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 511                                              dc_fixpt_from_int(region_start));
 512         arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 513                                              dc_fixpt_from_int(region_end));
 514
 515         y_r = rgb_resulted[0].red;
 516         y_g = rgb_resulted[0].green;
 517         y_b = rgb_resulted[0].blue;
 518
 519         y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
 520
 521         arr_points[0].y = y1_min;
 522         arr_points[0].slope = dc_fixpt_div(arr_points[0].y,
 523                                                  arr_points[0].x);
 524
 525         y_r = rgb_resulted[hw_points - 1].red;
 526         y_g = rgb_resulted[hw_points - 1].green;
 527         y_b = rgb_resulted[hw_points - 1].blue;
 528
 529         /* see comment above, m_arrPoints[1].y should be the Y value for the
 530          * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
 531          */
 532         y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
 533
 534         arr_points[1].y = y3_max;
 535
 536         arr_points[1].slope = dc_fixpt_zero;
 537
 538         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 539                 /* for PQ, we want to have a straight line from last HW X point,
 540                  * and the slope to be such that we hit 1.0 at 10000 nits.
 541                  */
 542                 const struct fixed31_32 end_value = dc_fixpt_from_int(125);
 543
 544                 arr_points[1].slope = dc_fixpt_div(
 545                                 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
 546                                 dc_fixpt_sub(end_value, arr_points[1].x));
 547         }
 548
 549         regamma_params->hw_points_num = hw_points;
 550
 551         k = 0;
 552         for (i = 1; i < 16; i++) {
 553                 if (seg_distr[k] != -1) {
 554                         regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 555                         regamma_params->arr_curve_points[i].offset =
 556                                         regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
 557                 }
 558                 k++;
 559         }
 560
 561         if (seg_distr[k] != -1)
 562                 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 563
 564         rgb = rgb_resulted;
 565         rgb_plus_1 = rgb_resulted + 1;
 566
 567         i = 1;
 568
 569         while (i != hw_points + 1) {
 570                 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
 571                         rgb_plus_1->red = rgb->red;
 572                 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
 573                         rgb_plus_1->green = rgb->green;
 574                 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
 575                         rgb_plus_1->blue = rgb->blue;
 576
 577                 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
 578                 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
 579                 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
 580
 581                 ++rgb_plus_1;
 582                 ++rgb;
 583                 ++i;
 584         }
 585
 586         convert_to_custom_float(rgb_resulted, arr_points, hw_points);
 587
 588         return true;
 589 }
 590
 591 static bool
 592 dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
 593                                 const struct dc_stream_state *stream)
 594 {
 595         struct transform *xfm = pipe_ctx->plane_res.xfm;
 596
 597         xfm->funcs->opp_power_on_regamma_lut(xfm, true);
 598         xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 599
 600         if (stream->out_transfer_func &&
 601             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
 602             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
 603                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
 604         } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func,
 605                                                          &xfm->regamma_params)) {
 606                 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
 607                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
 608         } else {
 609                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
 610         }
 611
 612         xfm->funcs->opp_power_on_regamma_lut(xfm, false);
 613
 614         return true;
 615 }
 616
 617 static enum dc_status bios_parser_crtc_source_select(
 618                 struct pipe_ctx *pipe_ctx)
 619 {
 620         struct dc_bios *dcb;
 621         /* call VBIOS table to set CRTC source for the HW
 622          * encoder block
 623          * note: video bios clears all FMT setting here. */
 624         struct bp_crtc_source_select crtc_source_select = {0};
 625         const struct dc_sink *sink = pipe_ctx->stream->sink;
 626
 627         crtc_source_select.engine_id = pipe_ctx->stream_res.stream_enc->id;
 628         crtc_source_select.controller_id = pipe_ctx->stream_res.tg->inst + 1;
 629         /*TODO: Need to un-hardcode color depth, dp_audio and account for
 630          * the case where signal and sink signal is different (translator
 631          * encoder)*/
 632         crtc_source_select.signal = pipe_ctx->stream->signal;
 633         crtc_source_select.enable_dp_audio = false;
 634         crtc_source_select.sink_signal = pipe_ctx->stream->signal;
 635
 636         switch (pipe_ctx->stream->timing.display_color_depth) {
 637         case COLOR_DEPTH_666:
 638                 crtc_source_select.display_output_bit_depth = PANEL_6BIT_COLOR;
 639                 break;
 640         case COLOR_DEPTH_888:
 641                 crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
 642                 break;
 643         case COLOR_DEPTH_101010:
 644                 crtc_source_select.display_output_bit_depth = PANEL_10BIT_COLOR;
 645                 break;
 646         case COLOR_DEPTH_121212:
 647                 crtc_source_select.display_output_bit_depth = PANEL_12BIT_COLOR;
 648                 break;
 649         default:
 650                 BREAK_TO_DEBUGGER();
 651                 crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
 652                 break;
 653         }
 654
 655         dcb = sink->ctx->dc_bios;
 656
 657         if (BP_RESULT_OK != dcb->funcs->crtc_source_select(
 658                 dcb,
 659                 &crtc_source_select)) {
 660                 return DC_ERROR_UNEXPECTED;
 661         }
 662
 663         return DC_OK;
 664 }
 665
 666 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 667 {
 668         bool is_hdmi;
 669         bool is_dp;
 670
 671         ASSERT(pipe_ctx->stream);
 672
 673         if (pipe_ctx->stream_res.stream_enc == NULL)
 674                 return;  /* this is not root pipe */
 675
 676         is_hdmi = dc_is_hdmi_signal(pipe_ctx->stream->signal);
 677         is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
 678
 679         if (!is_hdmi && !is_dp)
 680                 return;
 681
 682         if (is_hdmi)
 683                 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
 684                         pipe_ctx->stream_res.stream_enc,
 685                         &pipe_ctx->stream_res.encoder_info_frame);
 686         else
 687                 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
 688                         pipe_ctx->stream_res.stream_enc,
 689                         &pipe_ctx->stream_res.encoder_info_frame);
 690 }
 691
 692 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 693 {
 694         enum dc_lane_count lane_count =
 695                 pipe_ctx->stream->sink->link->cur_link_settings.lane_count;
 696
 697         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
 698         struct dc_link *link = pipe_ctx->stream->sink->link;
 699
 700
 701         uint32_t active_total_with_borders;
 702         uint32_t early_control = 0;
 703         struct timing_generator *tg = pipe_ctx->stream_res.tg;
 704
 705         /* For MST, there are multiply stream go to only one link.
 706          * connect DIG back_end to front_end while enable_stream and
 707          * disconnect them during disable_stream
 708          * BY this, it is logic clean to separate stream and link */
 709         link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
 710                                                     pipe_ctx->stream_res.stream_enc->id, true);
 711
 712         /* update AVI info frame (HDMI, DP)*/
 713         /* TODO: FPGA may change to hwss.update_info_frame */
 714         dce110_update_info_frame(pipe_ctx);
 715
 716         /* enable early control to avoid corruption on DP monitor*/
 717         active_total_with_borders =
 718                         timing->h_addressable
 719                                 + timing->h_border_left
 720                                 + timing->h_border_right;
 721
 722         if (lane_count != 0)
 723                 early_control = active_total_with_borders % lane_count;
 724
 725         if (early_control == 0)
 726                 early_control = lane_count;
 727
 728         tg->funcs->set_early_control(tg, early_control);
 729
 730         /* enable audio only within mode set */
 731         if (pipe_ctx->stream_res.audio != NULL) {
 732                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
 733                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
 734         }
 735
 736
 737
 738
 739 }
 740
 741 /*todo: cloned in stream enc, fix*/
 742 static bool is_panel_backlight_on(struct dce_hwseq *hws)
 743 {
 744         uint32_t value;
 745
 746         REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value);
 747
 748         return value;
 749 }
 750
 751 static bool is_panel_powered_on(struct dce_hwseq *hws)
 752 {
 753         uint32_t pwr_seq_state, dig_on, dig_on_ovrd;
 754
 755
 756         REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state);
 757
 758         REG_GET_2(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, &dig_on, LVTMA_DIGON_OVRD, &dig_on_ovrd);
 759
 760         return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1);
 761 }
 762
 763 static enum bp_result link_transmitter_control(
 764                 struct dc_bios *bios,
 765         struct bp_transmitter_control *cntl)
 766 {
 767         enum bp_result result;
 768
 769         result = bios->funcs->transmitter_control(bios, cntl);
 770
 771         return result;
 772 }
 773
 774 /*
 775  * @brief
 776  * eDP only.
 777  */
 778 void hwss_edp_wait_for_hpd_ready(
 779                 struct dc_link *link,
 780                 bool power_up)
 781 {
 782         struct dc_context *ctx = link->ctx;
 783         struct graphics_object_id connector = link->link_enc->connector;
 784         struct gpio *hpd;
 785         bool edp_hpd_high = false;
 786         uint32_t time_elapsed = 0;
 787         uint32_t timeout = power_up ?
 788                 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
 789
 790         if (dal_graphics_object_id_get_connector_id(connector)
 791                         != CONNECTOR_ID_EDP) {
 792                 BREAK_TO_DEBUGGER();
 793                 return;
 794         }
 795
 796         if (!power_up)
 797                 /*
 798                  * From KV, we will not HPD low after turning off VCC -
 799                  * instead, we will check the SW timer in power_up().
 800                  */
 801                 return;
 802
 803         /*
 804          * When we power on/off the eDP panel,
 805          * we need to wait until SENSE bit is high/low.
 806          */
 807
 808         /* obtain HPD */
 809         /* TODO what to do with this? */
 810         hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
 811
 812         if (!hpd) {
 813                 BREAK_TO_DEBUGGER();
 814                 return;
 815         }
 816
 817         dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
 818
 819         /* wait until timeout or panel detected */
 820
 821         do {
 822                 uint32_t detected = 0;
 823
 824                 dal_gpio_get_value(hpd, &detected);
 825
 826                 if (!(detected ^ power_up)) {
 827                         edp_hpd_high = true;
 828                         break;
 829                 }
 830
 831                 msleep(HPD_CHECK_INTERVAL);
 832
 833                 time_elapsed += HPD_CHECK_INTERVAL;
 834         } while (time_elapsed < timeout);
 835
 836         dal_gpio_close(hpd);
 837
 838         dal_gpio_destroy_irq(&hpd);
 839
 840         if (false == edp_hpd_high) {
 841                 DC_LOG_ERROR(
 842                                 "%s: wait timed out!\n", __func__);
 843         }
 844 }
 845
 846 void hwss_edp_power_control(
 847                 struct dc_link *link,
 848                 bool power_up)
 849 {
 850         struct dc_context *ctx = link->ctx;
 851         struct dce_hwseq *hwseq = ctx->dc->hwseq;
 852         struct bp_transmitter_control cntl = { 0 };
 853         enum bp_result bp_result;
 854
 855
 856         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 857                         != CONNECTOR_ID_EDP) {
 858                 BREAK_TO_DEBUGGER();
 859                 return;
 860         }
 861
 862         if (power_up != is_panel_powered_on(hwseq)) {
 863                 /* Send VBIOS command to prompt eDP panel power */
 864                 if (power_up) {
 865                         unsigned long long current_ts = dm_get_timestamp(ctx);
 866                         unsigned long long duration_in_ms =
 867                                         div64_u64(dm_get_elapse_time_in_ns(
 868                                                         ctx,
 869                                                         current_ts,
 870                                                         link->link_trace.time_stamp.edp_poweroff), 1000000);
 871                         unsigned long long wait_time_ms = 0;
 872
 873                         /* max 500ms from LCDVDD off to on */
 874                         unsigned long long edp_poweroff_time_ms = 500;
 875
 876                         if (link->local_sink != NULL)
 877                                 edp_poweroff_time_ms =
 878                                                 500 + link->local_sink->edid_caps.panel_patch.extra_t12_ms;
 879                         if (link->link_trace.time_stamp.edp_poweroff == 0)
 880                                 wait_time_ms = edp_poweroff_time_ms;
 881                         else if (duration_in_ms < edp_poweroff_time_ms)
 882                                 wait_time_ms = edp_poweroff_time_ms - duration_in_ms;
 883
 884                         if (wait_time_ms) {
 885                                 msleep(wait_time_ms);
 886                                 dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
 887                                                 __func__, wait_time_ms);
 888                         }
 889
 890                 }
 891
 892                 DC_LOG_HW_RESUME_S3(
 893                                 "%s: Panel Power action: %s\n",
 894                                 __func__, (power_up ? "On":"Off"));
 895
 896                 cntl.action = power_up ?
 897                         TRANSMITTER_CONTROL_POWER_ON :
 898                         TRANSMITTER_CONTROL_POWER_OFF;
 899                 cntl.transmitter = link->link_enc->transmitter;
 900                 cntl.connector_obj_id = link->link_enc->connector;
 901                 cntl.coherent = false;
 902                 cntl.lanes_number = LANE_COUNT_FOUR;
 903                 cntl.hpd_sel = link->link_enc->hpd_source;
 904                 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
 905
 906                 if (!power_up)
 907                         /*save driver power off time stamp*/
 908                         link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx);
 909                 else
 910                         link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx);
 911
 912                 if (bp_result != BP_RESULT_OK)
 913                         DC_LOG_ERROR(
 914                                         "%s: Panel Power bp_result: %d\n",
 915                                         __func__, bp_result);
 916         } else {
 917                 DC_LOG_HW_RESUME_S3(
 918                                 "%s: Skipping Panel Power action: %s\n",
 919                                 __func__, (power_up ? "On":"Off"));
 920         }
 921 }
 922
 923 /*todo: cloned in stream enc, fix*/
 924 /*
 925  * @brief
 926  * eDP only. Control the backlight of the eDP panel
 927  */
 928 void hwss_edp_backlight_control(
 929                 struct dc_link *link,
 930                 bool enable)
 931 {
 932         struct dc_context *ctx = link->ctx;
 933         struct dce_hwseq *hws = ctx->dc->hwseq;
 934         struct bp_transmitter_control cntl = { 0 };
 935
 936         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 937                 != CONNECTOR_ID_EDP) {
 938                 BREAK_TO_DEBUGGER();
 939                 return;
 940         }
 941
 942         if (enable && is_panel_backlight_on(hws)) {
 943                 DC_LOG_HW_RESUME_S3(
 944                                 "%s: panel already powered up. Do nothing.\n",
 945                                 __func__);
 946                 return;
 947         }
 948
 949         /* Send VBIOS command to control eDP panel backlight */
 950
 951         DC_LOG_HW_RESUME_S3(
 952                         "%s: backlight action: %s\n",
 953                         __func__, (enable ? "On":"Off"));
 954
 955         cntl.action = enable ?
 956                 TRANSMITTER_CONTROL_BACKLIGHT_ON :
 957                 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
 958
 959         /*cntl.engine_id = ctx->engine;*/
 960         cntl.transmitter = link->link_enc->transmitter;
 961         cntl.connector_obj_id = link->link_enc->connector;
 962         /*todo: unhardcode*/
 963         cntl.lanes_number = LANE_COUNT_FOUR;
 964         cntl.hpd_sel = link->link_enc->hpd_source;
 965         cntl.signal = SIGNAL_TYPE_EDP;
 966
 967         /* For eDP, the following delays might need to be considered
 968          * after link training completed:
 969          * idle period - min. accounts for required BS-Idle pattern,
 970          * max. allows for source frame synchronization);
 971          * 50 msec max. delay from valid video data from source
 972          * to video on dislpay or backlight enable.
 973          *
 974          * Disable the delay for now.
 975          * Enable it in the future if necessary.
 976          */
 977         /* dc_service_sleep_in_milliseconds(50); */
 978                 /*edp 1.2*/
 979         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
 980                 edp_receiver_ready_T7(link);
 981         link_transmitter_control(ctx->dc_bios, &cntl);
 982         /*edp 1.2*/
 983         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)
 984                 edp_receiver_ready_T9(link);
 985 }
 986
 987 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
 988 {
 989         struct dc *core_dc = pipe_ctx->stream->ctx->dc;
 990         /* notify audio driver for audio modes of monitor */
 991         struct pp_smu_funcs_rv *pp_smu = core_dc->res_pool->pp_smu;
 992         unsigned int i, num_audio = 1;
 993
 994         if (pipe_ctx->stream_res.audio) {
 995                 for (i = 0; i < MAX_PIPES; i++) {
 996                         /*current_state not updated yet*/
 997                         if (core_dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
 998                                 num_audio++;
 999                 }
1000
1001                 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
1002
1003                 if (num_audio == 1 && pp_smu != NULL && pp_smu->set_pme_wa_enable != NULL)
1004                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1005                         pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
1006                 /* un-mute audio */
1007                 /* TODO: audio should be per stream rather than per link */
1008                 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1009                         pipe_ctx->stream_res.stream_enc, false);
1010         }
1011 }
1012
1013 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
1014 {
1015         struct dc *dc = pipe_ctx->stream->ctx->dc;
1016
1017         pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1018                         pipe_ctx->stream_res.stream_enc, true);
1019         if (pipe_ctx->stream_res.audio) {
1020                 if (option != KEEP_ACQUIRED_RESOURCE ||
1021                                 !dc->debug.az_endpoint_mute_only) {
1022                         /*only disalbe az_endpoint if power down or free*/
1023                         pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
1024                 }
1025
1026                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1027                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
1028                                         pipe_ctx->stream_res.stream_enc);
1029                 else
1030                         pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
1031                                         pipe_ctx->stream_res.stream_enc);
1032                 /*don't free audio if it is from retrain or internal disable stream*/
1033                 if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) {
1034                         /*we have to dynamic arbitrate the audio endpoints*/
1035                         /*we free the resource, need reset is_audio_acquired*/
1036                         update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);
1037                         pipe_ctx->stream_res.audio = NULL;
1038                 }
1039
1040                 /* TODO: notify audio driver for if audio modes list changed
1041                  * add audio mode list change flag */
1042                 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1043                  * stream->stream_engine_id);
1044                  */
1045         }
1046 }
1047
1048 void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
1049 {
1050         struct dc_stream_state *stream = pipe_ctx->stream;
1051         struct dc_link *link = stream->sink->link;
1052         struct dc *dc = pipe_ctx->stream->ctx->dc;
1053
1054         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1055                 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
1056                         pipe_ctx->stream_res.stream_enc);
1057
1058         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1059                 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
1060                         pipe_ctx->stream_res.stream_enc);
1061
1062         dc->hwss.disable_audio_stream(pipe_ctx, option);
1063
1064         link->link_enc->funcs->connect_dig_be_to_fe(
1065                         link->link_enc,
1066                         pipe_ctx->stream_res.stream_enc->id,
1067                         false);
1068
1069 }
1070
1071 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1072                 struct dc_link_settings *link_settings)
1073 {
1074         struct encoder_unblank_param params = { { 0 } };
1075         struct dc_stream_state *stream = pipe_ctx->stream;
1076         struct dc_link *link = stream->sink->link;
1077
1078         /* only 3 items below are used by unblank */
1079         params.pixel_clk_khz =
1080                 pipe_ctx->stream->timing.pix_clk_khz;
1081         params.link_settings.link_rate = link_settings->link_rate;
1082
1083         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1084                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
1085
1086         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1087                 link->dc->hwss.edp_backlight_control(link, true);
1088         }
1089 }
1090 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1091 {
1092         struct dc_stream_state *stream = pipe_ctx->stream;
1093         struct dc_link *link = stream->sink->link;
1094
1095         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1096                 link->dc->hwss.edp_backlight_control(link, false);
1097                 dc_link_set_abm_disable(link);
1098         }
1099
1100         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1101                 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
1102 }
1103
1104
1105 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1106 {
1107         if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1108                 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1109 }
1110
1111 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1112 {
1113         switch (crtc_id) {
1114         case CONTROLLER_ID_D0:
1115                 return DTO_SOURCE_ID0;
1116         case CONTROLLER_ID_D1:
1117                 return DTO_SOURCE_ID1;
1118         case CONTROLLER_ID_D2:
1119                 return DTO_SOURCE_ID2;
1120         case CONTROLLER_ID_D3:
1121                 return DTO_SOURCE_ID3;
1122         case CONTROLLER_ID_D4:
1123                 return DTO_SOURCE_ID4;
1124         case CONTROLLER_ID_D5:
1125                 return DTO_SOURCE_ID5;
1126         default:
1127                 return DTO_SOURCE_UNKNOWN;
1128         }
1129 }
1130
1131 static void build_audio_output(
1132         struct dc_state *state,
1133         const struct pipe_ctx *pipe_ctx,
1134         struct audio_output *audio_output)
1135 {
1136         const struct dc_stream_state *stream = pipe_ctx->stream;
1137         audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1138
1139         audio_output->signal = pipe_ctx->stream->signal;
1140
1141         /* audio_crtc_info  */
1142
1143         audio_output->crtc_info.h_total =
1144                 stream->timing.h_total;
1145
1146         /*
1147          * Audio packets are sent during actual CRTC blank physical signal, we
1148          * need to specify actual active signal portion
1149          */
1150         audio_output->crtc_info.h_active =
1151                         stream->timing.h_addressable
1152                         + stream->timing.h_border_left
1153                         + stream->timing.h_border_right;
1154
1155         audio_output->crtc_info.v_active =
1156                         stream->timing.v_addressable
1157                         + stream->timing.v_border_top
1158                         + stream->timing.v_border_bottom;
1159
1160         audio_output->crtc_info.pixel_repetition = 1;
1161
1162         audio_output->crtc_info.interlaced =
1163                         stream->timing.flags.INTERLACE;
1164
1165         audio_output->crtc_info.refresh_rate =
1166                 (stream->timing.pix_clk_khz*1000)/
1167                 (stream->timing.h_total*stream->timing.v_total);
1168
1169         audio_output->crtc_info.color_depth =
1170                 stream->timing.display_color_depth;
1171
1172         audio_output->crtc_info.requested_pixel_clock =
1173                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1174
1175         audio_output->crtc_info.calculated_pixel_clock =
1176                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
1177
1178 /*for HDMI, audio ACR is with deep color ratio factor*/
1179         if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
1180                 audio_output->crtc_info.requested_pixel_clock ==
1181                                 stream->timing.pix_clk_khz) {
1182                 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1183                         audio_output->crtc_info.requested_pixel_clock =
1184                                         audio_output->crtc_info.requested_pixel_clock/2;
1185                         audio_output->crtc_info.calculated_pixel_clock =
1186                                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk/2;
1187
1188                 }
1189         }
1190
1191         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1192                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1193                 audio_output->pll_info.dp_dto_source_clock_in_khz =
1194                                 state->dccg->funcs->get_dp_ref_clk_frequency(
1195                                                 state->dccg);
1196         }
1197
1198         audio_output->pll_info.feed_back_divider =
1199                         pipe_ctx->pll_settings.feedback_divider;
1200
1201         audio_output->pll_info.dto_source =
1202                 translate_to_dto_source(
1203                         pipe_ctx->stream_res.tg->inst + 1);
1204
1205         /* TODO hard code to enable for now. Need get from stream */
1206         audio_output->pll_info.ss_enabled = true;
1207
1208         audio_output->pll_info.ss_percentage =
1209                         pipe_ctx->pll_settings.ss_percentage;
1210 }
1211
1212 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
1213                 struct tg_color *color)
1214 {
1215         uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;
1216
1217         switch (pipe_ctx->plane_res.scl_data.format) {
1218         case PIXEL_FORMAT_ARGB8888:
1219                 /* set boarder color to red */
1220                 color->color_r_cr = color_value;
1221                 break;
1222
1223         case PIXEL_FORMAT_ARGB2101010:
1224                 /* set boarder color to blue */
1225                 color->color_b_cb = color_value;
1226                 break;
1227         case PIXEL_FORMAT_420BPP8:
1228                 /* set boarder color to green */
1229                 color->color_g_y = color_value;
1230                 break;
1231         case PIXEL_FORMAT_420BPP10:
1232                 /* set boarder color to yellow */
1233                 color->color_g_y = color_value;
1234                 color->color_r_cr = color_value;
1235                 break;
1236         case PIXEL_FORMAT_FP16:
1237                 /* set boarder color to white */
1238                 color->color_r_cr = color_value;
1239                 color->color_b_cb = color_value;
1240                 color->color_g_y = color_value;
1241                 break;
1242         default:
1243                 break;
1244         }
1245 }
1246
1247 static void program_scaler(const struct dc *dc,
1248                 const struct pipe_ctx *pipe_ctx)
1249 {
1250         struct tg_color color = {0};
1251
1252 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1253         /* TOFPGA */
1254         if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1255                 return;
1256 #endif
1257
1258         if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1259                 get_surface_visual_confirm_color(pipe_ctx, &color);
1260         else
1261                 color_space_to_black_color(dc,
1262                                 pipe_ctx->stream->output_color_space,
1263                                 &color);
1264
1265         pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1266                 pipe_ctx->plane_res.xfm,
1267                 pipe_ctx->plane_res.scl_data.lb_params.depth,
1268                 &pipe_ctx->stream->bit_depth_params);
1269
1270         if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
1271                 /*
1272                  * The way 420 is packed, 2 channels carry Y component, 1 channel
1273                  * alternate between Cb and Cr, so both channels need the pixel
1274                  * value for Y
1275                  */
1276                 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1277                         color.color_r_cr = color.color_g_y;
1278
1279                 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1280                                 pipe_ctx->stream_res.tg,
1281                                 &color);
1282         }
1283
1284         pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1285                 &pipe_ctx->plane_res.scl_data);
1286 }
1287
1288 static enum dc_status dce110_enable_stream_timing(
1289                 struct pipe_ctx *pipe_ctx,
1290                 struct dc_state *context,
1291                 struct dc *dc)
1292 {
1293         struct dc_stream_state *stream = pipe_ctx->stream;
1294         struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1295                         pipe_ctx[pipe_ctx->pipe_idx];
1296         struct tg_color black_color = {0};
1297         struct drr_params params = {0};
1298         unsigned int event_triggers = 0;
1299
1300         if (!pipe_ctx_old->stream) {
1301
1302                 /* program blank color */
1303                 color_space_to_black_color(dc,
1304                                 stream->output_color_space, &black_color);
1305                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1306                                 pipe_ctx->stream_res.tg,
1307                                 &black_color);
1308
1309                 /*
1310                  * Must blank CRTC after disabling power gating and before any
1311                  * programming, otherwise CRTC will be hung in bad state
1312                  */
1313                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1314
1315                 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1316                                 pipe_ctx->clock_source,
1317                                 &pipe_ctx->stream_res.pix_clk_params,
1318                                 &pipe_ctx->pll_settings)) {
1319                         BREAK_TO_DEBUGGER();
1320                         return DC_ERROR_UNEXPECTED;
1321                 }
1322
1323                 pipe_ctx->stream_res.tg->funcs->program_timing(
1324                                 pipe_ctx->stream_res.tg,
1325                                 &stream->timing,
1326                                 true);
1327
1328                 params.vertical_total_min = stream->adjust.v_total_min;
1329                 params.vertical_total_max = stream->adjust.v_total_max;
1330                 if (pipe_ctx->stream_res.tg->funcs->set_drr)
1331                         pipe_ctx->stream_res.tg->funcs->set_drr(
1332                                 pipe_ctx->stream_res.tg, &params);
1333
1334                 // DRR should set trigger event to monitor surface update event
1335                 if (stream->adjust.v_total_min != 0 &&
1336                                 stream->adjust.v_total_max != 0)
1337                         event_triggers = 0x80;
1338                 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
1339                         pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1340                                 pipe_ctx->stream_res.tg, event_triggers);
1341         }
1342
1343         if (!pipe_ctx_old->stream) {
1344                 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1345                                 pipe_ctx->stream_res.tg)) {
1346                         BREAK_TO_DEBUGGER();
1347                         return DC_ERROR_UNEXPECTED;
1348                 }
1349         }
1350
1351         return DC_OK;
1352 }
1353
1354 static enum dc_status apply_single_controller_ctx_to_hw(
1355                 struct pipe_ctx *pipe_ctx,
1356                 struct dc_state *context,
1357                 struct dc *dc)
1358 {
1359         struct dc_stream_state *stream = pipe_ctx->stream;
1360
1361         if (pipe_ctx->stream_res.audio != NULL) {
1362                 struct audio_output audio_output;
1363
1364                 build_audio_output(context, pipe_ctx, &audio_output);
1365
1366                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1367                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
1368                                         pipe_ctx->stream_res.stream_enc,
1369                                         pipe_ctx->stream_res.audio->inst,
1370                                         &pipe_ctx->stream->audio_info);
1371                 else
1372                         pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
1373                                         pipe_ctx->stream_res.stream_enc,
1374                                         pipe_ctx->stream_res.audio->inst,
1375                                         &pipe_ctx->stream->audio_info,
1376                                         &audio_output.crtc_info);
1377
1378                 pipe_ctx->stream_res.audio->funcs->az_configure(
1379                                 pipe_ctx->stream_res.audio,
1380                                 pipe_ctx->stream->signal,
1381                                 &audio_output.crtc_info,
1382                                 &pipe_ctx->stream->audio_info);
1383         }
1384
1385         /*  */
1386         dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
1387
1388         /* TODO: move to stream encoder */
1389         if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
1390                 if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
1391                         BREAK_TO_DEBUGGER();
1392                         return DC_ERROR_UNEXPECTED;
1393                 }
1394
1395         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1396                         pipe_ctx->stream_res.opp,
1397                         COLOR_SPACE_YCBCR601,
1398                         stream->timing.display_color_depth,
1399                         pipe_ctx->stream->signal);
1400
1401         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1402                 pipe_ctx->stream_res.opp,
1403                 &stream->bit_depth_params,
1404                 &stream->clamping);
1405
1406         if (!stream->dpms_off)
1407                 core_link_enable_stream(context, pipe_ctx);
1408
1409         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1410
1411         pipe_ctx->stream->sink->link->psr_enabled = false;
1412
1413         return DC_OK;
1414 }
1415
1416 /******************************************************************************/
1417
1418 static void power_down_encoders(struct dc *dc)
1419 {
1420         int i;
1421         enum connector_id connector_id;
1422         enum signal_type signal = SIGNAL_TYPE_NONE;
1423
1424         /* do not know BIOS back-front mapping, simply blank all. It will not
1425          * hurt for non-DP
1426          */
1427         for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1428                 dc->res_pool->stream_enc[i]->funcs->dp_blank(
1429                                         dc->res_pool->stream_enc[i]);
1430         }
1431
1432         for (i = 0; i < dc->link_count; i++) {
1433                 connector_id = dal_graphics_object_id_get_connector_id(dc->links[i]->link_id);
1434                 if ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
1435                         (connector_id == CONNECTOR_ID_EDP)) {
1436
1437                         if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
1438                                 dp_receiver_power_ctrl(dc->links[i], false);
1439                         if (connector_id == CONNECTOR_ID_EDP)
1440                                 signal = SIGNAL_TYPE_EDP;
1441                 }
1442
1443                 dc->links[i]->link_enc->funcs->disable_output(
1444                                 dc->links[i]->link_enc, signal);
1445         }
1446 }
1447
1448 static void power_down_controllers(struct dc *dc)
1449 {
1450         int i;
1451
1452         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1453                 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1454                                 dc->res_pool->timing_generators[i]);
1455         }
1456 }
1457
1458 static void power_down_clock_sources(struct dc *dc)
1459 {
1460         int i;
1461
1462         if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1463                 dc->res_pool->dp_clock_source) == false)
1464                 dm_error("Failed to power down pll! (dp clk src)\n");
1465
1466         for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1467                 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1468                                 dc->res_pool->clock_sources[i]) == false)
1469                         dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1470         }
1471 }
1472
1473 static void power_down_all_hw_blocks(struct dc *dc)
1474 {
1475         power_down_encoders(dc);
1476
1477         power_down_controllers(dc);
1478
1479         power_down_clock_sources(dc);
1480
1481         if (dc->fbc_compressor)
1482                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1483 }
1484
1485 static void disable_vga_and_power_gate_all_controllers(
1486                 struct dc *dc)
1487 {
1488         int i;
1489         struct timing_generator *tg;
1490         struct dc_context *ctx = dc->ctx;
1491
1492         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1493                 tg = dc->res_pool->timing_generators[i];
1494
1495                 if (tg->funcs->disable_vga)
1496                         tg->funcs->disable_vga(tg);
1497         }
1498         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1499                 /* Enable CLOCK gating for each pipe BEFORE controller
1500                  * powergating. */
1501                 enable_display_pipe_clock_gating(ctx,
1502                                 true);
1503
1504                 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1505                 dc->hwss.disable_plane(dc,
1506                         &dc->current_state->res_ctx.pipe_ctx[i]);
1507         }
1508 }
1509
1510 static struct dc_link *get_link_for_edp(struct dc *dc)
1511 {
1512         int i;
1513
1514         for (i = 0; i < dc->link_count; i++) {
1515                 if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP)
1516                         return dc->links[i];
1517         }
1518         return NULL;
1519 }
1520
1521 static struct dc_link *get_link_for_edp_not_in_use(
1522                 struct dc *dc,
1523                 struct dc_state *context)
1524 {
1525         int i;
1526         struct dc_link *link = NULL;
1527
1528         /* check if eDP panel is suppose to be set mode, if yes, no need to disable */
1529         for (i = 0; i < context->stream_count; i++) {
1530                 if (context->streams[i]->signal == SIGNAL_TYPE_EDP)
1531                         return NULL;
1532         }
1533
1534         /* check if there is an eDP panel not in use */
1535         for (i = 0; i < dc->link_count; i++) {
1536                 if (dc->links[i]->local_sink &&
1537                         dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1538                         link = dc->links[i];
1539                         break;
1540                 }
1541         }
1542
1543         return link;
1544 }
1545
1546 /**
1547  * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1548  *  1. Power down all DC HW blocks
1549  *  2. Disable VGA engine on all controllers
1550  *  3. Enable power gating for controller
1551  *  4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1552  */
1553 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
1554 {
1555         int i;
1556         struct dc_link *edp_link_to_turnoff = NULL;
1557         struct dc_link *edp_link = get_link_for_edp(dc);
1558         struct dc_bios *bios = dc->ctx->dc_bios;
1559         bool can_edp_fast_boot_optimize = false;
1560         bool apply_edp_fast_boot_optimization = false;
1561
1562         if (edp_link) {
1563                 /* this seems to cause blank screens on DCE8 */
1564                 if ((dc->ctx->dce_version == DCE_VERSION_8_0) ||
1565                     (dc->ctx->dce_version == DCE_VERSION_8_1) ||
1566                     (dc->ctx->dce_version == DCE_VERSION_8_3))
1567                         can_edp_fast_boot_optimize = false;
1568                 else
1569                         can_edp_fast_boot_optimize =
1570                                 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc);
1571         }
1572
1573         if (can_edp_fast_boot_optimize)
1574                 edp_link_to_turnoff = get_link_for_edp_not_in_use(dc, context);
1575
1576         /* if OS doesn't light up eDP and eDP link is available, we want to disable
1577          * If resume from S4/S5, should optimization.
1578          */
1579         if (can_edp_fast_boot_optimize && !edp_link_to_turnoff) {
1580                 /* Find eDP stream and set optimization flag */
1581                 for (i = 0; i < context->stream_count; i++) {
1582                         if (context->streams[i]->signal == SIGNAL_TYPE_EDP) {
1583                                 context->streams[i]->apply_edp_fast_boot_optimization = true;
1584                                 apply_edp_fast_boot_optimization = true;
1585
1586                                 /* When after S4 and S5, vbios may post edp and previous dpms_off
1587                                  * doesn't make sense.
1588                                  * Update dpms_off state to align hw and sw state via check
1589                                  * vBios scratch register.
1590                                  */
1591                                 if (bios->funcs->is_active_display)     {
1592                                         const struct connector_device_tag_info *device_tag = &(edp_link->device_tag);
1593
1594                                         if (bios->funcs->is_active_display(bios,
1595                                                         context->streams[i]->signal,
1596                                                         device_tag))
1597                                                 context->streams[i]->dpms_off = false;
1598                                 }
1599                         }
1600                 }
1601         }
1602
1603         if (!apply_edp_fast_boot_optimization) {
1604                 if (edp_link_to_turnoff) {
1605                         /*turn off backlight before DP_blank and encoder powered down*/
1606                         dc->hwss.edp_backlight_control(edp_link_to_turnoff, false);
1607                 }
1608                 /*resume from S3, no vbios posting, no need to power down again*/
1609                 power_down_all_hw_blocks(dc);
1610                 disable_vga_and_power_gate_all_controllers(dc);
1611                 if (edp_link_to_turnoff)
1612                         dc->hwss.edp_power_control(edp_link_to_turnoff, false);
1613         }
1614         bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
1615 }
1616
1617 static uint32_t compute_pstate_blackout_duration(
1618         struct bw_fixed blackout_duration,
1619         const struct dc_stream_state *stream)
1620 {
1621         uint32_t total_dest_line_time_ns;
1622         uint32_t pstate_blackout_duration_ns;
1623
1624         pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1625
1626         total_dest_line_time_ns = 1000000UL *
1627                 stream->timing.h_total /
1628                 stream->timing.pix_clk_khz +
1629                 pstate_blackout_duration_ns;
1630
1631         return total_dest_line_time_ns;
1632 }
1633
1634 static void dce110_set_displaymarks(
1635         const struct dc *dc,
1636         struct dc_state *context)
1637 {
1638         uint8_t i, num_pipes;
1639         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1640
1641         for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1642                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1643                 uint32_t total_dest_line_time_ns;
1644
1645                 if (pipe_ctx->stream == NULL)
1646                         continue;
1647
1648                 total_dest_line_time_ns = compute_pstate_blackout_duration(
1649                         dc->bw_vbios->blackout_duration, pipe_ctx->stream);
1650                 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1651                         pipe_ctx->plane_res.mi,
1652                         context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1653                         context->bw.dce.stutter_exit_wm_ns[num_pipes],
1654                         context->bw.dce.stutter_entry_wm_ns[num_pipes],
1655                         context->bw.dce.urgent_wm_ns[num_pipes],
1656                         total_dest_line_time_ns);
1657                 if (i == underlay_idx) {
1658                         num_pipes++;
1659                         pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1660                                 pipe_ctx->plane_res.mi,
1661                                 context->bw.dce.nbp_state_change_wm_ns[num_pipes],
1662                                 context->bw.dce.stutter_exit_wm_ns[num_pipes],
1663                                 context->bw.dce.urgent_wm_ns[num_pipes],
1664                                 total_dest_line_time_ns);
1665                 }
1666                 num_pipes++;
1667         }
1668 }
1669
1670 void dce110_set_safe_displaymarks(
1671                 struct resource_context *res_ctx,
1672                 const struct resource_pool *pool)
1673 {
1674         int i;
1675         int underlay_idx = pool->underlay_pipe_index;
1676         struct dce_watermarks max_marks = {
1677                 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1678         struct dce_watermarks nbp_marks = {
1679                 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1680         struct dce_watermarks min_marks = { 0, 0, 0, 0};
1681
1682         for (i = 0; i < MAX_PIPES; i++) {
1683                 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1684                         continue;
1685
1686                 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1687                                 res_ctx->pipe_ctx[i].plane_res.mi,
1688                                 nbp_marks,
1689                                 max_marks,
1690                                 min_marks,
1691                                 max_marks,
1692                                 MAX_WATERMARK);
1693
1694                 if (i == underlay_idx)
1695                         res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1696                                 res_ctx->pipe_ctx[i].plane_res.mi,
1697                                 nbp_marks,
1698                                 max_marks,
1699                                 max_marks,
1700                                 MAX_WATERMARK);
1701
1702         }
1703 }
1704
1705 /*******************************************************************************
1706  * Public functions
1707  ******************************************************************************/
1708
1709 static void set_drr(struct pipe_ctx **pipe_ctx,
1710                 int num_pipes, int vmin, int vmax)
1711 {
1712         int i = 0;
1713         struct drr_params params = {0};
1714         // DRR should set trigger event to monitor surface update event
1715         unsigned int event_triggers = 0x80;
1716
1717         params.vertical_total_max = vmax;
1718         params.vertical_total_min = vmin;
1719
1720         /* TODO: If multiple pipes are to be supported, you need
1721          * some GSL stuff. Static screen triggers may be programmed differently
1722          * as well.
1723          */
1724         for (i = 0; i < num_pipes; i++) {
1725                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
1726                         pipe_ctx[i]->stream_res.tg, &params);
1727
1728                 if (vmax != 0 && vmin != 0)
1729                         pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
1730                                         pipe_ctx[i]->stream_res.tg,
1731                                         event_triggers);
1732         }
1733 }
1734
1735 static void get_position(struct pipe_ctx **pipe_ctx,
1736                 int num_pipes,
1737                 struct crtc_position *position)
1738 {
1739         int i = 0;
1740
1741         /* TODO: handle pipes > 1
1742          */
1743         for (i = 0; i < num_pipes; i++)
1744                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
1745 }
1746
1747 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1748                 int num_pipes, const struct dc_static_screen_events *events)
1749 {
1750         unsigned int i;
1751         unsigned int value = 0;
1752
1753         if (events->overlay_update)
1754                 value |= 0x100;
1755         if (events->surface_update)
1756                 value |= 0x80;
1757         if (events->cursor_update)
1758                 value |= 0x2;
1759         if (events->force_trigger)
1760                 value |= 0x1;
1761
1762         if (num_pipes) {
1763                 struct dc *dc = pipe_ctx[0]->stream->ctx->dc;
1764
1765                 if (dc->fbc_compressor)
1766                         value |= 0x84;
1767         }
1768
1769         for (i = 0; i < num_pipes; i++)
1770                 pipe_ctx[i]->stream_res.tg->funcs->
1771                         set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
1772 }
1773
1774 /*
1775  *  Check if FBC can be enabled
1776  */
1777 static bool should_enable_fbc(struct dc *dc,
1778                 struct dc_state *context,
1779                 uint32_t *pipe_idx)
1780 {
1781         uint32_t i;
1782         struct pipe_ctx *pipe_ctx = NULL;
1783         struct resource_context *res_ctx = &context->res_ctx;
1784         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1785
1786
1787         ASSERT(dc->fbc_compressor);
1788
1789         /* FBC memory should be allocated */
1790         if (!dc->ctx->fbc_gpu_addr)
1791                 return false;
1792
1793         /* Only supports single display */
1794         if (context->stream_count != 1)
1795                 return false;
1796
1797         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1798                 if (res_ctx->pipe_ctx[i].stream) {
1799
1800                         pipe_ctx = &res_ctx->pipe_ctx[i];
1801
1802                         if (!pipe_ctx)
1803                                 continue;
1804
1805                         /* fbc not applicable on underlay pipe */
1806                         if (pipe_ctx->pipe_idx != underlay_idx) {
1807                                 *pipe_idx = i;
1808                                 break;
1809                         }
1810                 }
1811         }
1812
1813         if (i == dc->res_pool->pipe_count)
1814                 return false;
1815
1816         if (!pipe_ctx->stream->sink)
1817                 return false;
1818
1819         if (!pipe_ctx->stream->sink->link)
1820                 return false;
1821
1822         /* Only supports eDP */
1823         if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)
1824                 return false;
1825
1826         /* PSR should not be enabled */
1827         if (pipe_ctx->stream->sink->link->psr_enabled)
1828                 return false;
1829
1830         /* Nothing to compress */
1831         if (!pipe_ctx->plane_state)
1832                 return false;
1833
1834         /* Only for non-linear tiling */
1835         if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
1836                 return false;
1837
1838         return true;
1839 }
1840
1841 /*
1842  *  Enable FBC
1843  */
1844 static void enable_fbc(
1845                 struct dc *dc,
1846                 struct dc_state *context)
1847 {
1848         uint32_t pipe_idx = 0;
1849
1850         if (should_enable_fbc(dc, context, &pipe_idx)) {
1851                 /* Program GRPH COMPRESSED ADDRESS and PITCH */
1852                 struct compr_addr_and_pitch_params params = {0, 0, 0};
1853                 struct compressor *compr = dc->fbc_compressor;
1854                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
1855
1856                 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
1857                 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
1858                 params.inst = pipe_ctx->stream_res.tg->inst;
1859                 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
1860
1861                 compr->funcs->surface_address_and_pitch(compr, &params);
1862                 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
1863
1864                 compr->funcs->enable_fbc(compr, &params);
1865         }
1866 }
1867
1868 static void dce110_reset_hw_ctx_wrap(
1869                 struct dc *dc,
1870                 struct dc_state *context)
1871 {
1872         int i;
1873
1874         /* Reset old context */
1875         /* look up the targets that have been removed since last commit */
1876         for (i = 0; i < MAX_PIPES; i++) {
1877                 struct pipe_ctx *pipe_ctx_old =
1878                         &dc->current_state->res_ctx.pipe_ctx[i];
1879                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1880
1881                 /* Note: We need to disable output if clock sources change,
1882                  * since bios does optimization and doesn't apply if changing
1883                  * PHY when not already disabled.
1884                  */
1885
1886                 /* Skip underlay pipe since it will be handled in commit surface*/
1887                 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
1888                         continue;
1889
1890                 if (!pipe_ctx->stream ||
1891                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1892                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
1893
1894                         /* Disable if new stream is null. O/w, if stream is
1895                          * disabled already, no need to disable again.
1896                          */
1897                         if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off)
1898                                 core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE);
1899
1900                         pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
1901                         if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
1902                                 dm_error("DC: failed to blank crtc!\n");
1903                                 BREAK_TO_DEBUGGER();
1904                         }
1905                         pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
1906                         pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
1907                                         pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
1908
1909                         if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx,
1910                                                                                 dc->res_pool,
1911                                                                                 old_clk))
1912                                 old_clk->funcs->cs_power_down(old_clk);
1913
1914                         dc->hwss.disable_plane(dc, pipe_ctx_old);
1915
1916                         pipe_ctx_old->stream = NULL;
1917                 }
1918         }
1919 }
1920
1921 static void dce110_setup_audio_dto(
1922                 struct dc *dc,
1923                 struct dc_state *context)
1924 {
1925         int i;
1926
1927         /* program audio wall clock. use HDMI as clock source if HDMI
1928          * audio active. Otherwise, use DP as clock source
1929          * first, loop to find any HDMI audio, if not, loop find DP audio
1930          */
1931         /* Setup audio rate clock source */
1932         /* Issue:
1933         * Audio lag happened on DP monitor when unplug a HDMI monitor
1934         *
1935         * Cause:
1936         * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
1937         * is set to either dto0 or dto1, audio should work fine.
1938         * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
1939         * set to dto0 will cause audio lag.
1940         *
1941         * Solution:
1942         * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
1943         * find first available pipe with audio, setup audio wall DTO per topology
1944         * instead of per pipe.
1945         */
1946         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1947                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1948
1949                 if (pipe_ctx->stream == NULL)
1950                         continue;
1951
1952                 if (pipe_ctx->top_pipe)
1953                         continue;
1954
1955                 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
1956                         continue;
1957
1958                 if (pipe_ctx->stream_res.audio != NULL) {
1959                         struct audio_output audio_output;
1960
1961                         build_audio_output(context, pipe_ctx, &audio_output);
1962
1963                         pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
1964                                 pipe_ctx->stream_res.audio,
1965                                 pipe_ctx->stream->signal,
1966                                 &audio_output.crtc_info,
1967                                 &audio_output.pll_info);
1968                         break;
1969                 }
1970         }
1971
1972         /* no HDMI audio is found, try DP audio */
1973         if (i == dc->res_pool->pipe_count) {
1974                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1975                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1976
1977                         if (pipe_ctx->stream == NULL)
1978                                 continue;
1979
1980                         if (pipe_ctx->top_pipe)
1981                                 continue;
1982
1983                         if (!dc_is_dp_signal(pipe_ctx->stream->signal))
1984                                 continue;
1985
1986                         if (pipe_ctx->stream_res.audio != NULL) {
1987                                 struct audio_output audio_output;
1988
1989                                 build_audio_output(context, pipe_ctx, &audio_output);
1990
1991                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
1992                                         pipe_ctx->stream_res.audio,
1993                                         pipe_ctx->stream->signal,
1994                                         &audio_output.crtc_info,
1995                                         &audio_output.pll_info);
1996                                 break;
1997                         }
1998                 }
1999         }
2000 }
2001
2002 enum dc_status dce110_apply_ctx_to_hw(
2003                 struct dc *dc,
2004                 struct dc_state *context)
2005 {
2006         struct dc_bios *dcb = dc->ctx->dc_bios;
2007         enum dc_status status;
2008         int i;
2009
2010         /* Reset old context */
2011         /* look up the targets that have been removed since last commit */
2012         dc->hwss.reset_hw_ctx_wrap(dc, context);
2013
2014         /* Skip applying if no targets */
2015         if (context->stream_count <= 0)
2016                 return DC_OK;
2017
2018         /* Apply new context */
2019         dcb->funcs->set_scratch_critical_state(dcb, true);
2020
2021         /* below is for real asic only */
2022         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2023                 struct pipe_ctx *pipe_ctx_old =
2024                                         &dc->current_state->res_ctx.pipe_ctx[i];
2025                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2026
2027                 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
2028                         continue;
2029
2030                 if (pipe_ctx->stream == pipe_ctx_old->stream) {
2031                         if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
2032                                 dce_crtc_switch_to_clk_src(dc->hwseq,
2033                                                 pipe_ctx->clock_source, i);
2034                         continue;
2035                 }
2036
2037                 dc->hwss.enable_display_power_gating(
2038                                 dc, i, dc->ctx->dc_bios,
2039                                 PIPE_GATING_CONTROL_DISABLE);
2040         }
2041
2042         if (dc->fbc_compressor)
2043                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2044
2045         dce110_setup_audio_dto(dc, context);
2046
2047         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2048                 struct pipe_ctx *pipe_ctx_old =
2049                                         &dc->current_state->res_ctx.pipe_ctx[i];
2050                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2051
2052                 if (pipe_ctx->stream == NULL)
2053                         continue;
2054
2055                 if (pipe_ctx->stream == pipe_ctx_old->stream)
2056                         continue;
2057
2058                 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2059                         continue;
2060
2061                 if (pipe_ctx->top_pipe)
2062                         continue;
2063
2064                 status = apply_single_controller_ctx_to_hw(
2065                                 pipe_ctx,
2066                                 context,
2067                                 dc);
2068
2069                 if (DC_OK != status)
2070                         return status;
2071         }
2072
2073         if (dc->fbc_compressor)
2074                 enable_fbc(dc, dc->current_state);
2075
2076         dcb->funcs->set_scratch_critical_state(dcb, false);
2077
2078         return DC_OK;
2079 }
2080
2081 /*******************************************************************************
2082  * Front End programming
2083  ******************************************************************************/
2084 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2085 {
2086         struct default_adjustment default_adjust = { 0 };
2087
2088         default_adjust.force_hw_default = false;
2089         default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
2090         default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
2091         default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2092         default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2093
2094         /* display color depth */
2095         default_adjust.color_depth =
2096                 pipe_ctx->stream->timing.display_color_depth;
2097
2098         /* Lb color depth */
2099         default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2100
2101         pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2102                                         pipe_ctx->plane_res.xfm, &default_adjust);
2103 }
2104
2105
2106 /*******************************************************************************
2107  * In order to turn on/off specific surface we will program
2108  * Blender + CRTC
2109  *
2110  * In case that we have two surfaces and they have a different visibility
2111  * we can't turn off the CRTC since it will turn off the entire display
2112  *
2113  * |----------------------------------------------- |
2114  * |bottom pipe|curr pipe  |              |         |
2115  * |Surface    |Surface    | Blender      |  CRCT   |
2116  * |visibility |visibility | Configuration|         |
2117  * |------------------------------------------------|
2118  * |   off     |    off    | CURRENT_PIPE | blank   |
2119  * |   off     |    on     | CURRENT_PIPE | unblank |
2120  * |   on      |    off    | OTHER_PIPE   | unblank |
2121  * |   on      |    on     | BLENDING     | unblank |
2122  * -------------------------------------------------|
2123  *
2124  ******************************************************************************/
2125 static void program_surface_visibility(const struct dc *dc,
2126                 struct pipe_ctx *pipe_ctx)
2127 {
2128         enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2129         bool blank_target = false;
2130
2131         if (pipe_ctx->bottom_pipe) {
2132
2133                 /* For now we are supporting only two pipes */
2134                 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2135
2136                 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2137                         if (pipe_ctx->plane_state->visible)
2138                                 blender_mode = BLND_MODE_BLENDING;
2139                         else
2140                                 blender_mode = BLND_MODE_OTHER_PIPE;
2141
2142                 } else if (!pipe_ctx->plane_state->visible)
2143                         blank_target = true;
2144
2145         } else if (!pipe_ctx->plane_state->visible)
2146                 blank_target = true;
2147
2148         dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
2149         pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2150
2151 }
2152
2153 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2154 {
2155         int i = 0;
2156         struct xfm_grph_csc_adjustment adjust;
2157         memset(&adjust, 0, sizeof(adjust));
2158         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2159
2160
2161         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2162                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2163
2164                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2165                         adjust.temperature_matrix[i] =
2166                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2167         }
2168
2169         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2170 }
2171 static void update_plane_addr(const struct dc *dc,
2172                 struct pipe_ctx *pipe_ctx)
2173 {
2174         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2175
2176         if (plane_state == NULL)
2177                 return;
2178
2179         pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2180                         pipe_ctx->plane_res.mi,
2181                         &plane_state->address,
2182                         plane_state->flip_immediate);
2183
2184         plane_state->status.requested_address = plane_state->address;
2185 }
2186
2187 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2188 {
2189         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2190
2191         if (plane_state == NULL)
2192                 return;
2193
2194         plane_state->status.is_flip_pending =
2195                         pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2196                                         pipe_ctx->plane_res.mi);
2197
2198         if (plane_state->status.is_flip_pending && !plane_state->visible)
2199                 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2200
2201         plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2202         if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2203                         pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2204                 plane_state->status.is_right_eye =\
2205                                 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2206         }
2207 }
2208
2209 void dce110_power_down(struct dc *dc)
2210 {
2211         power_down_all_hw_blocks(dc);
2212         disable_vga_and_power_gate_all_controllers(dc);
2213 }
2214
2215 static bool wait_for_reset_trigger_to_occur(
2216         struct dc_context *dc_ctx,
2217         struct timing_generator *tg)
2218 {
2219         bool rc = false;
2220
2221         /* To avoid endless loop we wait at most
2222          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2223         const uint32_t frames_to_wait_on_triggered_reset = 10;
2224         uint32_t i;
2225
2226         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2227
2228                 if (!tg->funcs->is_counter_moving(tg)) {
2229                         DC_ERROR("TG counter is not moving!\n");
2230                         break;
2231                 }
2232
2233                 if (tg->funcs->did_triggered_reset_occur(tg)) {
2234                         rc = true;
2235                         /* usually occurs at i=1 */
2236                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2237                                         i);
2238                         break;
2239                 }
2240
2241                 /* Wait for one frame. */
2242                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2243                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2244         }
2245
2246         if (false == rc)
2247                 DC_ERROR("GSL: Timeout on reset trigger!\n");
2248
2249         return rc;
2250 }
2251
2252 /* Enable timing synchronization for a group of Timing Generators. */
2253 static void dce110_enable_timing_synchronization(
2254                 struct dc *dc,
2255                 int group_index,
2256                 int group_size,
2257                 struct pipe_ctx *grouped_pipes[])
2258 {
2259         struct dc_context *dc_ctx = dc->ctx;
2260         struct dcp_gsl_params gsl_params = { 0 };
2261         int i;
2262
2263         DC_SYNC_INFO("GSL: Setting-up...\n");
2264
2265         /* Designate a single TG in the group as a master.
2266          * Since HW doesn't care which one, we always assign
2267          * the 1st one in the group. */
2268         gsl_params.gsl_group = 0;
2269         gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2270
2271         for (i = 0; i < group_size; i++)
2272                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2273                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2274
2275         /* Reset slave controllers on master VSync */
2276         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2277
2278         for (i = 1 /* skip the master */; i < group_size; i++)
2279                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2280                                 grouped_pipes[i]->stream_res.tg,
2281                                 gsl_params.gsl_group);
2282
2283         for (i = 1 /* skip the master */; i < group_size; i++) {
2284                 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2285                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2286                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
2287                                 grouped_pipes[i]->stream_res.tg);
2288         }
2289
2290         /* GSL Vblank synchronization is a one time sync mechanism, assumption
2291          * is that the sync'ed displays will not drift out of sync over time*/
2292         DC_SYNC_INFO("GSL: Restoring register states.\n");
2293         for (i = 0; i < group_size; i++)
2294                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2295
2296         DC_SYNC_INFO("GSL: Set-up complete.\n");
2297 }
2298
2299 static void dce110_enable_per_frame_crtc_position_reset(
2300                 struct dc *dc,
2301                 int group_size,
2302                 struct pipe_ctx *grouped_pipes[])
2303 {
2304         struct dc_context *dc_ctx = dc->ctx;
2305         struct dcp_gsl_params gsl_params = { 0 };
2306         int i;
2307
2308         gsl_params.gsl_group = 0;
2309         gsl_params.gsl_master = 0;
2310
2311         for (i = 0; i < group_size; i++)
2312                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2313                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2314
2315         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2316
2317         for (i = 1; i < group_size; i++)
2318                 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
2319                                 grouped_pipes[i]->stream_res.tg,
2320                                 gsl_params.gsl_master,
2321                                 &grouped_pipes[i]->stream->triggered_crtc_reset);
2322
2323         DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2324         for (i = 1; i < group_size; i++)
2325                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2326
2327         for (i = 0; i < group_size; i++)
2328                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2329
2330 }
2331
2332 static void init_hw(struct dc *dc)
2333 {
2334         int i;
2335         struct dc_bios *bp;
2336         struct transform *xfm;
2337         struct abm *abm;
2338
2339         bp = dc->ctx->dc_bios;
2340         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2341                 xfm = dc->res_pool->transforms[i];
2342                 xfm->funcs->transform_reset(xfm);
2343
2344                 dc->hwss.enable_display_power_gating(
2345                                 dc, i, bp,
2346                                 PIPE_GATING_CONTROL_INIT);
2347                 dc->hwss.enable_display_power_gating(
2348                                 dc, i, bp,
2349                                 PIPE_GATING_CONTROL_DISABLE);
2350                 dc->hwss.enable_display_pipe_clock_gating(
2351                         dc->ctx,
2352                         true);
2353         }
2354
2355         dce_clock_gating_power_up(dc->hwseq, false);
2356         /***************************************/
2357
2358         for (i = 0; i < dc->link_count; i++) {
2359                 /****************************************/
2360                 /* Power up AND update implementation according to the
2361                  * required signal (which may be different from the
2362                  * default signal on connector). */
2363                 struct dc_link *link = dc->links[i];
2364
2365                 if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
2366                         dc->hwss.edp_power_control(link, true);
2367
2368                 link->link_enc->funcs->hw_init(link->link_enc);
2369         }
2370
2371         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2372                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2373
2374                 tg->funcs->disable_vga(tg);
2375
2376                 /* Blank controller using driver code instead of
2377                  * command table. */
2378                 tg->funcs->set_blank(tg, true);
2379                 hwss_wait_for_blank_complete(tg);
2380         }
2381
2382         for (i = 0; i < dc->res_pool->audio_count; i++) {
2383                 struct audio *audio = dc->res_pool->audios[i];
2384                 audio->funcs->hw_init(audio);
2385         }
2386
2387         abm = dc->res_pool->abm;
2388         if (abm != NULL) {
2389                 abm->funcs->init_backlight(abm);
2390                 abm->funcs->abm_init(abm);
2391         }
2392
2393         if (dc->fbc_compressor)
2394                 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2395
2396 }
2397
2398
2399 void dce110_prepare_bandwidth(
2400                 struct dc *dc,
2401                 struct dc_state *context)
2402 {
2403         struct clk_mgr *dccg = dc->res_pool->clk_mgr;
2404
2405         dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
2406
2407         dccg->funcs->update_clocks(
2408                         dccg,
2409                         context,
2410                         false);
2411 }
2412
2413 void dce110_optimize_bandwidth(
2414                 struct dc *dc,
2415                 struct dc_state *context)
2416 {
2417         struct clk_mgr *dccg = dc->res_pool->clk_mgr;
2418
2419         dce110_set_displaymarks(dc, context);
2420
2421         dccg->funcs->update_clocks(
2422                         dccg,
2423                         context,
2424                         true);
2425 }
2426
2427 static void dce110_program_front_end_for_pipe(
2428                 struct dc *dc, struct pipe_ctx *pipe_ctx)
2429 {
2430         struct mem_input *mi = pipe_ctx->plane_res.mi;
2431         struct pipe_ctx *old_pipe = NULL;
2432         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2433         struct xfm_grph_csc_adjustment adjust;
2434         struct out_csc_color_matrix tbl_entry;
2435         unsigned int i;
2436         DC_LOGGER_INIT();
2437         memset(&tbl_entry, 0, sizeof(tbl_entry));
2438
2439         if (dc->current_state)
2440                 old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
2441
2442         memset(&adjust, 0, sizeof(adjust));
2443         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2444
2445         dce_enable_fe_clock(dc->hwseq, mi->inst, true);
2446
2447         set_default_colors(pipe_ctx);
2448         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2449                         == true) {
2450                 tbl_entry.color_space =
2451                         pipe_ctx->stream->output_color_space;
2452
2453                 for (i = 0; i < 12; i++)
2454                         tbl_entry.regval[i] =
2455                         pipe_ctx->stream->csc_color_matrix.matrix[i];
2456
2457                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2458                                 (pipe_ctx->plane_res.xfm, &tbl_entry);
2459         }
2460
2461         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2462                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2463
2464                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2465                         adjust.temperature_matrix[i] =
2466                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2467         }
2468
2469         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2470
2471         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2472
2473         program_scaler(dc, pipe_ctx);
2474
2475         mi->funcs->mem_input_program_surface_config(
2476                         mi,
2477                         plane_state->format,
2478                         &plane_state->tiling_info,
2479                         &plane_state->plane_size,
2480                         plane_state->rotation,
2481                         NULL,
2482                         false);
2483         if (mi->funcs->set_blank)
2484                 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2485
2486         if (dc->config.gpu_vm_support)
2487                 mi->funcs->mem_input_program_pte_vm(
2488                                 pipe_ctx->plane_res.mi,
2489                                 plane_state->format,
2490                                 &plane_state->tiling_info,
2491                                 plane_state->rotation);
2492
2493         /* Moved programming gamma from dc to hwss */
2494         if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2495                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2496                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
2497                 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
2498
2499         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2500                 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
2501
2502         DC_LOG_SURFACE(
2503                         "Pipe:%d %p: addr hi:0x%x, "
2504                         "addr low:0x%x, "
2505                         "src: %d, %d, %d,"
2506                         " %d; dst: %d, %d, %d, %d;"
2507                         "clip: %d, %d, %d, %d\n",
2508                         pipe_ctx->pipe_idx,
2509                         (void *) pipe_ctx->plane_state,
2510                         pipe_ctx->plane_state->address.grph.addr.high_part,
2511                         pipe_ctx->plane_state->address.grph.addr.low_part,
2512                         pipe_ctx->plane_state->src_rect.x,
2513                         pipe_ctx->plane_state->src_rect.y,
2514                         pipe_ctx->plane_state->src_rect.width,
2515                         pipe_ctx->plane_state->src_rect.height,
2516                         pipe_ctx->plane_state->dst_rect.x,
2517                         pipe_ctx->plane_state->dst_rect.y,
2518                         pipe_ctx->plane_state->dst_rect.width,
2519                         pipe_ctx->plane_state->dst_rect.height,
2520                         pipe_ctx->plane_state->clip_rect.x,
2521                         pipe_ctx->plane_state->clip_rect.y,
2522                         pipe_ctx->plane_state->clip_rect.width,
2523                         pipe_ctx->plane_state->clip_rect.height);
2524
2525         DC_LOG_SURFACE(
2526                         "Pipe %d: width, height, x, y\n"
2527                         "viewport:%d, %d, %d, %d\n"
2528                         "recout:  %d, %d, %d, %d\n",
2529                         pipe_ctx->pipe_idx,
2530                         pipe_ctx->plane_res.scl_data.viewport.width,
2531                         pipe_ctx->plane_res.scl_data.viewport.height,
2532                         pipe_ctx->plane_res.scl_data.viewport.x,
2533                         pipe_ctx->plane_res.scl_data.viewport.y,
2534                         pipe_ctx->plane_res.scl_data.recout.width,
2535                         pipe_ctx->plane_res.scl_data.recout.height,
2536                         pipe_ctx->plane_res.scl_data.recout.x,
2537                         pipe_ctx->plane_res.scl_data.recout.y);
2538 }
2539
2540 static void dce110_apply_ctx_for_surface(
2541                 struct dc *dc,
2542                 const struct dc_stream_state *stream,
2543                 int num_planes,
2544                 struct dc_state *context)
2545 {
2546         int i;
2547
2548         if (num_planes == 0)
2549                 return;
2550
2551         if (dc->fbc_compressor)
2552                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2553
2554         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2555                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2556                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2557
2558                 if (stream == pipe_ctx->stream) {
2559                         if (!pipe_ctx->top_pipe &&
2560                                 (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
2561                                 dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
2562                 }
2563         }
2564
2565         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2566                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2567
2568                 if (pipe_ctx->stream != stream)
2569                         continue;
2570
2571                 /* Need to allocate mem before program front end for Fiji */
2572                 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
2573                                 pipe_ctx->plane_res.mi,
2574                                 pipe_ctx->stream->timing.h_total,
2575                                 pipe_ctx->stream->timing.v_total,
2576                                 pipe_ctx->stream->timing.pix_clk_khz,
2577                                 context->stream_count);
2578
2579                 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2580
2581                 dc->hwss.update_plane_addr(dc, pipe_ctx);
2582
2583                 program_surface_visibility(dc, pipe_ctx);
2584
2585         }
2586
2587         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2588                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2589                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2590
2591                 if ((stream == pipe_ctx->stream) &&
2592                         (!pipe_ctx->top_pipe) &&
2593                         (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
2594                         dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
2595         }
2596
2597         if (dc->fbc_compressor)
2598                 enable_fbc(dc, dc->current_state);
2599 }
2600
2601 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
2602 {
2603         int fe_idx = pipe_ctx->plane_res.mi ?
2604                 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
2605
2606         /* Do not power down fe when stream is active on dce*/
2607         if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
2608                 return;
2609
2610         dc->hwss.enable_display_power_gating(
2611                 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2612
2613         dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2614                                 dc->res_pool->transforms[fe_idx]);
2615 }
2616
2617 static void dce110_wait_for_mpcc_disconnect(
2618                 struct dc *dc,
2619                 struct resource_pool *res_pool,
2620                 struct pipe_ctx *pipe_ctx)
2621 {
2622         /* do nothing*/
2623 }
2624
2625 void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
2626 {
2627         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2628         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
2629         struct mem_input *mi = pipe_ctx->plane_res.mi;
2630         struct dc_cursor_mi_param param = {
2631                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
2632                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
2633                 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2634                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2635                 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2636                 .rotation = pipe_ctx->plane_state->rotation,
2637                 .mirror = pipe_ctx->plane_state->horizontal_mirror
2638         };
2639
2640         if (pipe_ctx->plane_state->address.type
2641                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2642                 pos_cpy.enable = false;
2643
2644         if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2645                 pos_cpy.enable = false;
2646
2647         if (ipp->funcs->ipp_cursor_set_position)
2648                 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
2649         if (mi->funcs->set_cursor_position)
2650                 mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
2651 }
2652
2653 void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2654 {
2655         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2656
2657         if (pipe_ctx->plane_res.ipp &&
2658             pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
2659                 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
2660                                 pipe_ctx->plane_res.ipp, attributes);
2661
2662         if (pipe_ctx->plane_res.mi &&
2663             pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
2664                 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
2665                                 pipe_ctx->plane_res.mi, attributes);
2666
2667         if (pipe_ctx->plane_res.xfm &&
2668             pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
2669                 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
2670                                 pipe_ctx->plane_res.xfm, attributes);
2671 }
2672
2673 static const struct hw_sequencer_funcs dce110_funcs = {
2674         .program_gamut_remap = program_gamut_remap,
2675         .init_hw = init_hw,
2676         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2677         .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
2678         .update_plane_addr = update_plane_addr,
2679         .update_pending_status = dce110_update_pending_status,
2680         .set_input_transfer_func = dce110_set_input_transfer_func,
2681         .set_output_transfer_func = dce110_set_output_transfer_func,
2682         .power_down = dce110_power_down,
2683         .enable_accelerated_mode = dce110_enable_accelerated_mode,
2684         .enable_timing_synchronization = dce110_enable_timing_synchronization,
2685         .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
2686         .update_info_frame = dce110_update_info_frame,
2687         .enable_stream = dce110_enable_stream,
2688         .disable_stream = dce110_disable_stream,
2689         .unblank_stream = dce110_unblank_stream,
2690         .blank_stream = dce110_blank_stream,
2691         .enable_audio_stream = dce110_enable_audio_stream,
2692         .disable_audio_stream = dce110_disable_audio_stream,
2693         .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
2694         .enable_display_power_gating = dce110_enable_display_power_gating,
2695         .disable_plane = dce110_power_down_fe,
2696         .pipe_control_lock = dce_pipe_control_lock,
2697         .prepare_bandwidth = dce110_prepare_bandwidth,
2698         .optimize_bandwidth = dce110_optimize_bandwidth,
2699         .set_drr = set_drr,
2700         .get_position = get_position,
2701         .set_static_screen_control = set_static_screen_control,
2702         .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
2703         .enable_stream_timing = dce110_enable_stream_timing,
2704         .setup_stereo = NULL,
2705         .set_avmute = dce110_set_avmute,
2706         .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
2707         .edp_backlight_control = hwss_edp_backlight_control,
2708         .edp_power_control = hwss_edp_power_control,
2709         .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
2710         .set_cursor_position = dce110_set_cursor_position,
2711         .set_cursor_attribute = dce110_set_cursor_attribute
2712 };
2713
2714 void dce110_hw_sequencer_construct(struct dc *dc)
2715 {
2716         dc->hwss = dce110_funcs;
2717 }
2718